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Generate the Verilog code corresponding to this FIRRTL code module BoomProbeUnit : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, rep : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<3>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}}, flip way_en : UInt<8>, flip wb_rdy : UInt<1>, flip mshr_rdy : UInt<1>, mshr_wb_rdy : UInt<1>, flip block_state : { state : UInt<2>}, lsu_release : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, state : { valid : UInt<1>, bits : UInt<40>}} regreset state : UInt<4>, clock, reset, UInt<4>(0h0) reg req : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}, clock node req_idx = bits(req.address, 11, 6) node req_tag = shr(req.address, 12) reg way_en : UInt, clock node tag_matches = orr(way_en) reg old_coh : { state : UInt<2>}, clock wire miss_coh : { state : UInt<2>} connect miss_coh.state, UInt<2>(0h0) node reply_coh = mux(tag_matches, old_coh, miss_coh) node _r_T = cat(req.param, reply_coh.state) node _r_T_1 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_2 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_3 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_4 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_5 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_6 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_7 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_8 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_9 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_10 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_11 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_12 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_13 = eq(_r_T_12, _r_T) node _r_T_14 = mux(_r_T_13, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_15 = mux(_r_T_13, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_16 = mux(_r_T_13, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_17 = eq(_r_T_11, _r_T) node _r_T_18 = mux(_r_T_17, UInt<1>(0h0), _r_T_14) node _r_T_19 = mux(_r_T_17, UInt<3>(0h2), _r_T_15) node _r_T_20 = mux(_r_T_17, UInt<2>(0h0), _r_T_16) node _r_T_21 = eq(_r_T_10, _r_T) node _r_T_22 = mux(_r_T_21, UInt<1>(0h0), _r_T_18) node _r_T_23 = mux(_r_T_21, UInt<3>(0h1), _r_T_19) node _r_T_24 = mux(_r_T_21, UInt<2>(0h0), _r_T_20) node _r_T_25 = eq(_r_T_9, _r_T) node _r_T_26 = mux(_r_T_25, UInt<1>(0h1), _r_T_22) node _r_T_27 = mux(_r_T_25, UInt<3>(0h1), _r_T_23) node _r_T_28 = mux(_r_T_25, UInt<2>(0h0), _r_T_24) node _r_T_29 = eq(_r_T_8, _r_T) node _r_T_30 = mux(_r_T_29, UInt<1>(0h0), _r_T_26) node _r_T_31 = mux(_r_T_29, UInt<3>(0h5), _r_T_27) node _r_T_32 = mux(_r_T_29, UInt<2>(0h0), _r_T_28) node _r_T_33 = eq(_r_T_7, _r_T) node _r_T_34 = mux(_r_T_33, UInt<1>(0h0), _r_T_30) node _r_T_35 = mux(_r_T_33, UInt<3>(0h4), _r_T_31) node _r_T_36 = mux(_r_T_33, UInt<2>(0h1), _r_T_32) node _r_T_37 = eq(_r_T_6, _r_T) node _r_T_38 = mux(_r_T_37, UInt<1>(0h0), _r_T_34) node _r_T_39 = mux(_r_T_37, UInt<3>(0h0), _r_T_35) node _r_T_40 = mux(_r_T_37, UInt<2>(0h1), _r_T_36) node _r_T_41 = eq(_r_T_5, _r_T) node _r_T_42 = mux(_r_T_41, UInt<1>(0h1), _r_T_38) node _r_T_43 = mux(_r_T_41, UInt<3>(0h0), _r_T_39) node _r_T_44 = mux(_r_T_41, UInt<2>(0h1), _r_T_40) node _r_T_45 = eq(_r_T_4, _r_T) node _r_T_46 = mux(_r_T_45, UInt<1>(0h0), _r_T_42) node _r_T_47 = mux(_r_T_45, UInt<3>(0h5), _r_T_43) node _r_T_48 = mux(_r_T_45, UInt<2>(0h0), _r_T_44) node _r_T_49 = eq(_r_T_3, _r_T) node _r_T_50 = mux(_r_T_49, UInt<1>(0h0), _r_T_46) node _r_T_51 = mux(_r_T_49, UInt<3>(0h4), _r_T_47) node _r_T_52 = mux(_r_T_49, UInt<2>(0h1), _r_T_48) node _r_T_53 = eq(_r_T_2, _r_T) node _r_T_54 = mux(_r_T_53, UInt<1>(0h0), _r_T_50) node _r_T_55 = mux(_r_T_53, UInt<3>(0h3), _r_T_51) node _r_T_56 = mux(_r_T_53, UInt<2>(0h2), _r_T_52) node _r_T_57 = eq(_r_T_1, _r_T) node is_dirty = mux(_r_T_57, UInt<1>(0h1), _r_T_54) node report_param = mux(_r_T_57, UInt<3>(0h3), _r_T_55) node r_3 = mux(_r_T_57, UInt<2>(0h2), _r_T_56) wire new_coh : { state : UInt<2>} connect new_coh.state, r_3 node _io_state_valid_T = neq(state, UInt<4>(0h0)) connect io.state.valid, _io_state_valid_T connect io.state.bits, req.address node _io_req_ready_T = eq(state, UInt<4>(0h0)) connect io.req.ready, _io_req_ready_T node _io_rep_valid_T = eq(state, UInt<4>(0h6)) connect io.rep.valid, _io_rep_valid_T wire io_rep_bits_c : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} connect io_rep_bits_c.opcode, UInt<3>(0h4) connect io_rep_bits_c.param, report_param connect io_rep_bits_c.size, req.size connect io_rep_bits_c.source, req.source connect io_rep_bits_c.address, req.address invalidate io_rep_bits_c.data connect io_rep_bits_c.corrupt, UInt<1>(0h0) connect io.rep.bits, io_rep_bits_c node _T = eq(io.rep.valid, UInt<1>(0h0)) node opdata = bits(io.rep.bits.opcode, 0, 0) node _T_1 = eq(opdata, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed: ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it\n at dcache.scala:185 assert(!io.rep.valid || !edge.hasData(io.rep.bits),\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_meta_read_valid_T = eq(state, UInt<4>(0h1)) connect io.meta_read.valid, _io_meta_read_valid_T connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, req_tag node _io_meta_read_bits_way_en_T = not(UInt<8>(0h0)) connect io.meta_read.bits.way_en, _io_meta_read_bits_way_en_T node _io_meta_write_valid_T = eq(state, UInt<4>(0h9)) connect io.meta_write.valid, _io_meta_write_valid_T connect io.meta_write.bits.way_en, way_en connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.tag, req_tag connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.data.coh, new_coh node _io_wb_req_valid_T = eq(state, UInt<4>(0h7)) connect io.wb_req.valid, _io_wb_req_valid_T connect io.wb_req.bits.source, req.source connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.tag, req_tag connect io.wb_req.bits.param, report_param connect io.wb_req.bits.way_en, way_en connect io.wb_req.bits.voluntary, UInt<1>(0h0) node _io_mshr_wb_rdy_T = eq(state, UInt<4>(0h6)) node _io_mshr_wb_rdy_T_1 = eq(state, UInt<4>(0h7)) node _io_mshr_wb_rdy_T_2 = eq(state, UInt<4>(0h8)) node _io_mshr_wb_rdy_T_3 = eq(state, UInt<4>(0h9)) node _io_mshr_wb_rdy_T_4 = eq(state, UInt<4>(0ha)) node _io_mshr_wb_rdy_T_5 = or(_io_mshr_wb_rdy_T, _io_mshr_wb_rdy_T_1) node _io_mshr_wb_rdy_T_6 = or(_io_mshr_wb_rdy_T_5, _io_mshr_wb_rdy_T_2) node _io_mshr_wb_rdy_T_7 = or(_io_mshr_wb_rdy_T_6, _io_mshr_wb_rdy_T_3) node _io_mshr_wb_rdy_T_8 = or(_io_mshr_wb_rdy_T_7, _io_mshr_wb_rdy_T_4) node _io_mshr_wb_rdy_T_9 = eq(_io_mshr_wb_rdy_T_8, UInt<1>(0h0)) connect io.mshr_wb_rdy, _io_mshr_wb_rdy_T_9 node _io_lsu_release_valid_T = eq(state, UInt<4>(0h5)) connect io.lsu_release.valid, _io_lsu_release_valid_T wire io_lsu_release_bits_c : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} connect io_lsu_release_bits_c.opcode, UInt<3>(0h4) connect io_lsu_release_bits_c.param, report_param connect io_lsu_release_bits_c.size, req.size connect io_lsu_release_bits_c.source, req.source connect io_lsu_release_bits_c.address, req.address invalidate io_lsu_release_bits_c.data connect io_lsu_release_bits_c.corrupt, UInt<1>(0h0) connect io.lsu_release.bits, io_lsu_release_bits_c node _T_6 = eq(state, UInt<4>(0h0)) when _T_6 : node _T_7 = and(io.req.ready, io.req.valid) when _T_7 : connect state, UInt<4>(0h1) connect req, io.req.bits else : node _T_8 = eq(state, UInt<4>(0h1)) when _T_8 : node _T_9 = and(io.meta_read.ready, io.meta_read.valid) when _T_9 : connect state, UInt<4>(0h2) else : node _T_10 = eq(state, UInt<4>(0h2)) when _T_10 : connect state, UInt<4>(0h3) else : node _T_11 = eq(state, UInt<4>(0h3)) when _T_11 : connect old_coh, io.block_state connect way_en, io.way_en node _state_T = and(io.mshr_rdy, io.wb_rdy) node _state_T_1 = mux(_state_T, UInt<4>(0h4), UInt<4>(0h1)) connect state, _state_T_1 else : node _T_12 = eq(state, UInt<4>(0h4)) when _T_12 : node _state_T_2 = and(tag_matches, is_dirty) node _state_T_3 = mux(_state_T_2, UInt<4>(0h7), UInt<4>(0h5)) connect state, _state_T_3 else : node _T_13 = eq(state, UInt<4>(0h5)) when _T_13 : node _T_14 = and(io.lsu_release.ready, io.lsu_release.valid) when _T_14 : connect state, UInt<4>(0h6) else : node _T_15 = eq(state, UInt<4>(0h6)) when _T_15 : when io.rep.ready : node _state_T_4 = mux(tag_matches, UInt<4>(0h9), UInt<4>(0h0)) connect state, _state_T_4 else : node _T_16 = eq(state, UInt<4>(0h7)) when _T_16 : node _T_17 = and(io.wb_req.ready, io.wb_req.valid) when _T_17 : connect state, UInt<4>(0h8) else : node _T_18 = eq(state, UInt<4>(0h8)) when _T_18 : when io.wb_req.ready : connect state, UInt<4>(0h9) else : node _T_19 = eq(state, UInt<4>(0h9)) when _T_19 : node _T_20 = and(io.meta_write.ready, io.meta_write.valid) when _T_20 : connect state, UInt<4>(0ha) else : node _T_21 = eq(state, UInt<4>(0ha)) when _T_21 : connect state, UInt<4>(0h0)
module BoomProbeUnit( // @[dcache.scala:145:7] input clock, // @[dcache.scala:145:7] input reset, // @[dcache.scala:145:7] output io_req_ready, // @[dcache.scala:146:14] input io_req_valid, // @[dcache.scala:146:14] input [2:0] io_req_bits_opcode, // @[dcache.scala:146:14] input [1:0] io_req_bits_param, // @[dcache.scala:146:14] input [3:0] io_req_bits_size, // @[dcache.scala:146:14] input [2:0] io_req_bits_source, // @[dcache.scala:146:14] input [31:0] io_req_bits_address, // @[dcache.scala:146:14] input [15:0] io_req_bits_mask, // @[dcache.scala:146:14] input [127:0] io_req_bits_data, // @[dcache.scala:146:14] input io_req_bits_corrupt, // @[dcache.scala:146:14] input io_rep_ready, // @[dcache.scala:146:14] output io_rep_valid, // @[dcache.scala:146:14] output [2:0] io_rep_bits_param, // @[dcache.scala:146:14] output [3:0] io_rep_bits_size, // @[dcache.scala:146:14] output [2:0] io_rep_bits_source, // @[dcache.scala:146:14] output [31:0] io_rep_bits_address, // @[dcache.scala:146:14] input io_meta_read_ready, // @[dcache.scala:146:14] output io_meta_read_valid, // @[dcache.scala:146:14] output [5:0] io_meta_read_bits_idx, // @[dcache.scala:146:14] output [19:0] io_meta_read_bits_tag, // @[dcache.scala:146:14] input io_meta_write_ready, // @[dcache.scala:146:14] output io_meta_write_valid, // @[dcache.scala:146:14] output [5:0] io_meta_write_bits_idx, // @[dcache.scala:146:14] output [7:0] io_meta_write_bits_way_en, // @[dcache.scala:146:14] output [19:0] io_meta_write_bits_tag, // @[dcache.scala:146:14] output [1:0] io_meta_write_bits_data_coh_state, // @[dcache.scala:146:14] output [19:0] io_meta_write_bits_data_tag, // @[dcache.scala:146:14] input io_wb_req_ready, // @[dcache.scala:146:14] output io_wb_req_valid, // @[dcache.scala:146:14] output [19:0] io_wb_req_bits_tag, // @[dcache.scala:146:14] output [5:0] io_wb_req_bits_idx, // @[dcache.scala:146:14] output [2:0] io_wb_req_bits_source, // @[dcache.scala:146:14] output [2:0] io_wb_req_bits_param, // @[dcache.scala:146:14] output [7:0] io_wb_req_bits_way_en, // @[dcache.scala:146:14] input [7:0] io_way_en, // @[dcache.scala:146:14] input io_wb_rdy, // @[dcache.scala:146:14] input io_mshr_rdy, // @[dcache.scala:146:14] output io_mshr_wb_rdy, // @[dcache.scala:146:14] input [1:0] io_block_state_state, // @[dcache.scala:146:14] input io_lsu_release_ready, // @[dcache.scala:146:14] output io_lsu_release_valid, // @[dcache.scala:146:14] output [2:0] io_lsu_release_bits_param, // @[dcache.scala:146:14] output [3:0] io_lsu_release_bits_size, // @[dcache.scala:146:14] output [2:0] io_lsu_release_bits_source, // @[dcache.scala:146:14] output [31:0] io_lsu_release_bits_address, // @[dcache.scala:146:14] output io_state_valid, // @[dcache.scala:146:14] output [39:0] io_state_bits // @[dcache.scala:146:14] ); wire io_req_valid_0 = io_req_valid; // @[dcache.scala:145:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[dcache.scala:145:7] wire [1:0] io_req_bits_param_0 = io_req_bits_param; // @[dcache.scala:145:7] wire [3:0] io_req_bits_size_0 = io_req_bits_size; // @[dcache.scala:145:7] wire [2:0] io_req_bits_source_0 = io_req_bits_source; // @[dcache.scala:145:7] wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[dcache.scala:145:7] wire [15:0] io_req_bits_mask_0 = io_req_bits_mask; // @[dcache.scala:145:7] wire [127:0] io_req_bits_data_0 = io_req_bits_data; // @[dcache.scala:145:7] wire io_req_bits_corrupt_0 = io_req_bits_corrupt; // @[dcache.scala:145:7] wire io_rep_ready_0 = io_rep_ready; // @[dcache.scala:145:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[dcache.scala:145:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[dcache.scala:145:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[dcache.scala:145:7] wire [7:0] io_way_en_0 = io_way_en; // @[dcache.scala:145:7] wire io_wb_rdy_0 = io_wb_rdy; // @[dcache.scala:145:7] wire io_mshr_rdy_0 = io_mshr_rdy; // @[dcache.scala:145:7] wire [1:0] io_block_state_state_0 = io_block_state_state; // @[dcache.scala:145:7] wire io_lsu_release_ready_0 = io_lsu_release_ready; // @[dcache.scala:145:7] wire [3:0] _r_T_1 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_2 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_3 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_4 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_5 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_6 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_7 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_8 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_9 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_10 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_11 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_12 = 4'h8; // @[Metadata.scala:133:10] wire [1:0] miss_coh_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_16 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_20 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_24 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_28 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_32 = 2'h0; // @[Misc.scala:38:63] wire [7:0] io_meta_read_bits_way_en = 8'hFF; // @[dcache.scala:145:7] wire [7:0] _io_meta_read_bits_way_en_T = 8'hFF; // @[dcache.scala:191:31] wire io_rep_bits_corrupt = 1'h0; // @[dcache.scala:145:7] wire io_wb_req_bits_voluntary = 1'h0; // @[dcache.scala:145:7] wire io_lsu_release_bits_corrupt = 1'h0; // @[dcache.scala:145:7] wire _r_T_14 = 1'h0; // @[Misc.scala:38:9] wire _r_T_18 = 1'h0; // @[Misc.scala:38:9] wire _r_T_22 = 1'h0; // @[Misc.scala:38:9] wire io_rep_bits_c_corrupt = 1'h0; // @[Edges.scala:416:17] wire opdata = 1'h0; // @[Edges.scala:102:36] wire io_lsu_release_bits_c_corrupt = 1'h0; // @[Edges.scala:416:17] wire [127:0] io_rep_bits_data = 128'h0; // @[dcache.scala:145:7] wire [127:0] io_lsu_release_bits_data = 128'h0; // @[dcache.scala:145:7] wire [127:0] io_rep_bits_c_data = 128'h0; // @[Edges.scala:416:17] wire [127:0] io_lsu_release_bits_c_data = 128'h0; // @[Edges.scala:416:17] wire [2:0] io_rep_bits_opcode = 3'h4; // @[dcache.scala:145:7] wire [2:0] io_lsu_release_bits_opcode = 3'h4; // @[dcache.scala:145:7] wire _io_req_ready_T; // @[dcache.scala:181:25] wire [2:0] io_rep_bits_c_opcode = 3'h4; // @[Edges.scala:416:17] wire [2:0] io_lsu_release_bits_c_opcode = 3'h4; // @[Edges.scala:416:17] wire _io_rep_valid_T; // @[dcache.scala:182:25] wire [2:0] io_rep_bits_c_param; // @[Edges.scala:416:17] wire [3:0] io_rep_bits_c_size; // @[Edges.scala:416:17] wire [2:0] io_rep_bits_c_source; // @[Edges.scala:416:17] wire [31:0] io_rep_bits_c_address; // @[Edges.scala:416:17] wire _io_meta_read_valid_T; // @[dcache.scala:188:31] wire [5:0] req_idx; // @[dcache.scala:168:28] wire [19:0] req_tag; // @[dcache.scala:169:29] wire _io_meta_write_valid_T; // @[dcache.scala:193:32] wire [1:0] new_coh_state; // @[Metadata.scala:160:20] wire _io_wb_req_valid_T; // @[dcache.scala:200:28] wire [2:0] report_param; // @[Misc.scala:38:36] wire _io_mshr_wb_rdy_T_9; // @[dcache.scala:209:21] wire _io_lsu_release_valid_T; // @[dcache.scala:211:33] wire [2:0] io_lsu_release_bits_c_param; // @[Edges.scala:416:17] wire [3:0] io_lsu_release_bits_c_size; // @[Edges.scala:416:17] wire [2:0] io_lsu_release_bits_c_source; // @[Edges.scala:416:17] wire [31:0] io_lsu_release_bits_c_address; // @[Edges.scala:416:17] wire _io_state_valid_T; // @[dcache.scala:178:27] wire io_req_ready_0; // @[dcache.scala:145:7] wire [2:0] io_rep_bits_param_0; // @[dcache.scala:145:7] wire [3:0] io_rep_bits_size_0; // @[dcache.scala:145:7] wire [2:0] io_rep_bits_source_0; // @[dcache.scala:145:7] wire [31:0] io_rep_bits_address_0; // @[dcache.scala:145:7] wire io_rep_valid_0; // @[dcache.scala:145:7] wire [5:0] io_meta_read_bits_idx_0; // @[dcache.scala:145:7] wire [19:0] io_meta_read_bits_tag_0; // @[dcache.scala:145:7] wire io_meta_read_valid_0; // @[dcache.scala:145:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[dcache.scala:145:7] wire [19:0] io_meta_write_bits_data_tag_0; // @[dcache.scala:145:7] wire [5:0] io_meta_write_bits_idx_0; // @[dcache.scala:145:7] wire [7:0] io_meta_write_bits_way_en_0; // @[dcache.scala:145:7] wire [19:0] io_meta_write_bits_tag_0; // @[dcache.scala:145:7] wire io_meta_write_valid_0; // @[dcache.scala:145:7] wire [19:0] io_wb_req_bits_tag_0; // @[dcache.scala:145:7] wire [5:0] io_wb_req_bits_idx_0; // @[dcache.scala:145:7] wire [2:0] io_wb_req_bits_source_0; // @[dcache.scala:145:7] wire [2:0] io_wb_req_bits_param_0; // @[dcache.scala:145:7] wire [7:0] io_wb_req_bits_way_en_0; // @[dcache.scala:145:7] wire io_wb_req_valid_0; // @[dcache.scala:145:7] wire [2:0] io_lsu_release_bits_param_0; // @[dcache.scala:145:7] wire [3:0] io_lsu_release_bits_size_0; // @[dcache.scala:145:7] wire [2:0] io_lsu_release_bits_source_0; // @[dcache.scala:145:7] wire [31:0] io_lsu_release_bits_address_0; // @[dcache.scala:145:7] wire io_lsu_release_valid_0; // @[dcache.scala:145:7] wire io_state_valid_0; // @[dcache.scala:145:7] wire [39:0] io_state_bits_0; // @[dcache.scala:145:7] wire io_mshr_wb_rdy_0; // @[dcache.scala:145:7] reg [3:0] state; // @[dcache.scala:165:22] reg [2:0] req_opcode; // @[dcache.scala:167:16] reg [1:0] req_param; // @[dcache.scala:167:16] reg [3:0] req_size; // @[dcache.scala:167:16] assign io_rep_bits_c_size = req_size; // @[Edges.scala:416:17] assign io_lsu_release_bits_c_size = req_size; // @[Edges.scala:416:17] reg [2:0] req_source; // @[dcache.scala:167:16] assign io_wb_req_bits_source_0 = req_source; // @[dcache.scala:145:7, :167:16] assign io_rep_bits_c_source = req_source; // @[Edges.scala:416:17] assign io_lsu_release_bits_c_source = req_source; // @[Edges.scala:416:17] reg [31:0] req_address; // @[dcache.scala:167:16] assign io_rep_bits_c_address = req_address; // @[Edges.scala:416:17] assign io_lsu_release_bits_c_address = req_address; // @[Edges.scala:416:17] reg [15:0] req_mask; // @[dcache.scala:167:16] reg [127:0] req_data; // @[dcache.scala:167:16] reg req_corrupt; // @[dcache.scala:167:16] assign req_idx = req_address[11:6]; // @[dcache.scala:167:16, :168:28] assign io_meta_read_bits_idx_0 = req_idx; // @[dcache.scala:145:7, :168:28] assign io_meta_write_bits_idx_0 = req_idx; // @[dcache.scala:145:7, :168:28] assign io_wb_req_bits_idx_0 = req_idx; // @[dcache.scala:145:7, :168:28] assign req_tag = req_address[31:12]; // @[dcache.scala:167:16, :169:29] assign io_meta_read_bits_tag_0 = req_tag; // @[dcache.scala:145:7, :169:29] assign io_meta_write_bits_tag_0 = req_tag; // @[dcache.scala:145:7, :169:29] assign io_meta_write_bits_data_tag_0 = req_tag; // @[dcache.scala:145:7, :169:29] assign io_wb_req_bits_tag_0 = req_tag; // @[dcache.scala:145:7, :169:29] reg [7:0] way_en; // @[dcache.scala:171:19] assign io_meta_write_bits_way_en_0 = way_en; // @[dcache.scala:145:7, :171:19] assign io_wb_req_bits_way_en_0 = way_en; // @[dcache.scala:145:7, :171:19] wire tag_matches = |way_en; // @[dcache.scala:171:19, :172:28] reg [1:0] old_coh_state; // @[dcache.scala:173:20] wire [1:0] reply_coh_state = tag_matches ? old_coh_state : 2'h0; // @[dcache.scala:172:28, :173:20, :175:22] wire [3:0] _r_T = {req_param, reply_coh_state}; // @[Metadata.scala:120:19] wire _r_T_13 = _r_T == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_15 = _r_T_13 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_17 = _r_T == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_19 = _r_T_17 ? 3'h2 : _r_T_15; // @[Misc.scala:38:36, :56:20] wire _r_T_21 = _r_T == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_23 = _r_T_21 ? 3'h1 : _r_T_19; // @[Misc.scala:38:36, :56:20] wire _r_T_25 = _r_T == 4'hB; // @[Misc.scala:56:20] wire _r_T_26 = _r_T_25; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_27 = _r_T_25 ? 3'h1 : _r_T_23; // @[Misc.scala:38:36, :56:20] wire _r_T_29 = _r_T == 4'h4; // @[Misc.scala:56:20] wire _r_T_30 = ~_r_T_29 & _r_T_26; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_31 = _r_T_29 ? 3'h5 : _r_T_27; // @[Misc.scala:38:36, :56:20] wire _r_T_33 = _r_T == 4'h5; // @[Misc.scala:56:20] wire _r_T_34 = ~_r_T_33 & _r_T_30; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_35 = _r_T_33 ? 3'h4 : _r_T_31; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_36 = {1'h0, _r_T_33}; // @[Misc.scala:38:63, :56:20] wire _r_T_37 = _r_T == 4'h6; // @[Misc.scala:56:20] wire _r_T_38 = ~_r_T_37 & _r_T_34; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_39 = _r_T_37 ? 3'h0 : _r_T_35; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_40 = _r_T_37 ? 2'h1 : _r_T_36; // @[Misc.scala:38:63, :56:20] wire _r_T_41 = _r_T == 4'h7; // @[Misc.scala:56:20] wire _r_T_42 = _r_T_41 | _r_T_38; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_43 = _r_T_41 ? 3'h0 : _r_T_39; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_44 = _r_T_41 ? 2'h1 : _r_T_40; // @[Misc.scala:38:63, :56:20] wire _r_T_45 = _r_T == 4'h0; // @[Misc.scala:56:20] wire _r_T_46 = ~_r_T_45 & _r_T_42; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_47 = _r_T_45 ? 3'h5 : _r_T_43; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_48 = _r_T_45 ? 2'h0 : _r_T_44; // @[Misc.scala:38:63, :56:20] wire _r_T_49 = _r_T == 4'h1; // @[Misc.scala:56:20] wire _r_T_50 = ~_r_T_49 & _r_T_46; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_51 = _r_T_49 ? 3'h4 : _r_T_47; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_52 = _r_T_49 ? 2'h1 : _r_T_48; // @[Misc.scala:38:63, :56:20] wire _r_T_53 = _r_T == 4'h2; // @[Misc.scala:56:20] wire _r_T_54 = ~_r_T_53 & _r_T_50; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_55 = _r_T_53 ? 3'h3 : _r_T_51; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_56 = _r_T_53 ? 2'h2 : _r_T_52; // @[Misc.scala:38:63, :56:20] wire _r_T_57 = _r_T == 4'h3; // @[Misc.scala:56:20] wire is_dirty = _r_T_57 | _r_T_54; // @[Misc.scala:38:9, :56:20] assign report_param = _r_T_57 ? 3'h3 : _r_T_55; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = report_param; // @[Misc.scala:38:36] assign io_rep_bits_c_param = report_param; // @[Misc.scala:38:36] assign io_lsu_release_bits_c_param = report_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_57 ? 2'h2 : _r_T_56; // @[Misc.scala:38:63, :56:20] assign new_coh_state = r_3; // @[Misc.scala:38:63] assign io_meta_write_bits_data_coh_state_0 = new_coh_state; // @[Metadata.scala:160:20] assign _io_state_valid_T = |state; // @[dcache.scala:165:22, :178:27] assign io_state_valid_0 = _io_state_valid_T; // @[dcache.scala:145:7, :178:27] assign io_state_bits_0 = {8'h0, req_address}; // @[dcache.scala:145:7, :167:16, :172:28, :179:18] assign _io_req_ready_T = ~(|state); // @[dcache.scala:165:22, :178:27, :181:25] assign io_req_ready_0 = _io_req_ready_T; // @[dcache.scala:145:7, :181:25] wire _T_15 = state == 4'h6; // @[dcache.scala:165:22, :182:25] assign _io_rep_valid_T = _T_15; // @[dcache.scala:182:25] wire _io_mshr_wb_rdy_T; // @[package.scala:16:47] assign _io_mshr_wb_rdy_T = _T_15; // @[package.scala:16:47] assign io_rep_valid_0 = _io_rep_valid_T; // @[dcache.scala:145:7, :182:25] assign io_rep_bits_param_0 = io_rep_bits_c_param; // @[Edges.scala:416:17] assign io_rep_bits_size_0 = io_rep_bits_c_size; // @[Edges.scala:416:17] assign io_rep_bits_source_0 = io_rep_bits_c_source; // @[Edges.scala:416:17] assign io_rep_bits_address_0 = io_rep_bits_c_address; // @[Edges.scala:416:17] assign _io_meta_read_valid_T = state == 4'h1; // @[dcache.scala:165:22, :188:31] assign io_meta_read_valid_0 = _io_meta_read_valid_T; // @[dcache.scala:145:7, :188:31] wire _T_19 = state == 4'h9; // @[dcache.scala:165:22, :193:32] assign _io_meta_write_valid_T = _T_19; // @[dcache.scala:193:32] wire _io_mshr_wb_rdy_T_3; // @[package.scala:16:47] assign _io_mshr_wb_rdy_T_3 = _T_19; // @[package.scala:16:47] assign io_meta_write_valid_0 = _io_meta_write_valid_T; // @[dcache.scala:145:7, :193:32] wire _T_16 = state == 4'h7; // @[dcache.scala:165:22, :200:28] assign _io_wb_req_valid_T = _T_16; // @[dcache.scala:200:28] wire _io_mshr_wb_rdy_T_1; // @[package.scala:16:47] assign _io_mshr_wb_rdy_T_1 = _T_16; // @[package.scala:16:47] assign io_wb_req_valid_0 = _io_wb_req_valid_T; // @[dcache.scala:145:7, :200:28] wire _io_mshr_wb_rdy_T_2 = state == 4'h8; // @[package.scala:16:47] wire _io_mshr_wb_rdy_T_4 = state == 4'hA; // @[package.scala:16:47] wire _io_mshr_wb_rdy_T_5 = _io_mshr_wb_rdy_T | _io_mshr_wb_rdy_T_1; // @[package.scala:16:47, :81:59] wire _io_mshr_wb_rdy_T_6 = _io_mshr_wb_rdy_T_5 | _io_mshr_wb_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_mshr_wb_rdy_T_7 = _io_mshr_wb_rdy_T_6 | _io_mshr_wb_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_mshr_wb_rdy_T_8 = _io_mshr_wb_rdy_T_7 | _io_mshr_wb_rdy_T_4; // @[package.scala:16:47, :81:59] assign _io_mshr_wb_rdy_T_9 = ~_io_mshr_wb_rdy_T_8; // @[package.scala:81:59] assign io_mshr_wb_rdy_0 = _io_mshr_wb_rdy_T_9; // @[dcache.scala:145:7, :209:21] assign _io_lsu_release_valid_T = state == 4'h5; // @[dcache.scala:165:22, :211:33] assign io_lsu_release_valid_0 = _io_lsu_release_valid_T; // @[dcache.scala:145:7, :211:33] assign io_lsu_release_bits_param_0 = io_lsu_release_bits_c_param; // @[Edges.scala:416:17] assign io_lsu_release_bits_size_0 = io_lsu_release_bits_c_size; // @[Edges.scala:416:17] assign io_lsu_release_bits_source_0 = io_lsu_release_bits_c_source; // @[Edges.scala:416:17] assign io_lsu_release_bits_address_0 = io_lsu_release_bits_c_address; // @[Edges.scala:416:17] wire _state_T = io_mshr_rdy_0 & io_wb_rdy_0; // @[dcache.scala:145:7, :231:30] wire [3:0] _state_T_1 = _state_T ? 4'h4 : 4'h1; // @[dcache.scala:231:{17,30}] wire _state_T_2 = tag_matches & is_dirty; // @[Misc.scala:38:9] wire [3:0] _state_T_3 = {2'h1, _state_T_2, 1'h1}; // @[dcache.scala:233:{17,30}] wire [3:0] _state_T_4 = tag_matches ? 4'h9 : 4'h0; // @[dcache.scala:172:28, :240:19] wire [15:0][3:0] _GEN = {{state}, {state}, {state}, {state}, {state}, {4'h0}, {io_meta_write_ready_0 & io_meta_write_valid_0 ? 4'hA : state}, {io_wb_req_ready_0 ? 4'h9 : state}, {io_wb_req_ready_0 & io_wb_req_valid_0 ? 4'h8 : state}, {io_rep_ready_0 ? _state_T_4 : state}, {io_lsu_release_ready_0 & io_lsu_release_valid_0 ? 4'h6 : state}, {_state_T_3}, {_state_T_1}, {4'h3}, {io_meta_read_ready_0 & io_meta_read_valid_0 ? 4'h2 : state}, {state}}; // @[Decoupled.scala:51:35] wire _T_7 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[dcache.scala:145:7] if (reset) // @[dcache.scala:145:7] state <= 4'h0; // @[dcache.scala:165:22] else if (|state) // @[dcache.scala:165:22, :178:27] state <= _GEN[state]; // @[package.scala:16:47] else if (_T_7) // @[Decoupled.scala:51:35] state <= 4'h1; // @[dcache.scala:165:22] if (~(|state) & _T_7) begin // @[Decoupled.scala:51:35] req_opcode <= io_req_bits_opcode_0; // @[dcache.scala:145:7, :167:16] req_param <= io_req_bits_param_0; // @[dcache.scala:145:7, :167:16] req_size <= io_req_bits_size_0; // @[dcache.scala:145:7, :167:16] req_source <= io_req_bits_source_0; // @[dcache.scala:145:7, :167:16] req_address <= io_req_bits_address_0; // @[dcache.scala:145:7, :167:16] req_mask <= io_req_bits_mask_0; // @[dcache.scala:145:7, :167:16] req_data <= io_req_bits_data_0; // @[dcache.scala:145:7, :167:16] req_corrupt <= io_req_bits_corrupt_0; // @[dcache.scala:145:7, :167:16] end if (~(|state) | _io_meta_read_valid_T | state == 4'h2 | state != 4'h3) begin // @[dcache.scala:165:22, :173:20, :178:27, :181:25, :188:31, :215:30, :220:39, :224:{22,39}, :227:{22,38}] end else begin // @[dcache.scala:173:20, :215:30, :220:39, :224:39, :227:38] way_en <= io_way_en_0; // @[dcache.scala:145:7, :171:19] old_coh_state <= io_block_state_state_0; // @[dcache.scala:145:7, :173:20] end always @(posedge) assign io_req_ready = io_req_ready_0; // @[dcache.scala:145:7] assign io_rep_valid = io_rep_valid_0; // @[dcache.scala:145:7] assign io_rep_bits_param = io_rep_bits_param_0; // @[dcache.scala:145:7] assign io_rep_bits_size = io_rep_bits_size_0; // @[dcache.scala:145:7] assign io_rep_bits_source = io_rep_bits_source_0; // @[dcache.scala:145:7] assign io_rep_bits_address = io_rep_bits_address_0; // @[dcache.scala:145:7] assign io_meta_read_valid = io_meta_read_valid_0; // @[dcache.scala:145:7] assign io_meta_read_bits_idx = io_meta_read_bits_idx_0; // @[dcache.scala:145:7] assign io_meta_read_bits_tag = io_meta_read_bits_tag_0; // @[dcache.scala:145:7] assign io_meta_write_valid = io_meta_write_valid_0; // @[dcache.scala:145:7] assign io_meta_write_bits_idx = io_meta_write_bits_idx_0; // @[dcache.scala:145:7] assign io_meta_write_bits_way_en = io_meta_write_bits_way_en_0; // @[dcache.scala:145:7] assign io_meta_write_bits_tag = io_meta_write_bits_tag_0; // @[dcache.scala:145:7] assign io_meta_write_bits_data_coh_state = io_meta_write_bits_data_coh_state_0; // @[dcache.scala:145:7] assign io_meta_write_bits_data_tag = io_meta_write_bits_data_tag_0; // @[dcache.scala:145:7] assign io_wb_req_valid = io_wb_req_valid_0; // @[dcache.scala:145:7] assign io_wb_req_bits_tag = io_wb_req_bits_tag_0; // @[dcache.scala:145:7] assign io_wb_req_bits_idx = io_wb_req_bits_idx_0; // @[dcache.scala:145:7] assign io_wb_req_bits_source = io_wb_req_bits_source_0; // @[dcache.scala:145:7] assign io_wb_req_bits_param = io_wb_req_bits_param_0; // @[dcache.scala:145:7] assign io_wb_req_bits_way_en = io_wb_req_bits_way_en_0; // @[dcache.scala:145:7] assign io_mshr_wb_rdy = io_mshr_wb_rdy_0; // @[dcache.scala:145:7] assign io_lsu_release_valid = io_lsu_release_valid_0; // @[dcache.scala:145:7] assign io_lsu_release_bits_param = io_lsu_release_bits_param_0; // @[dcache.scala:145:7] assign io_lsu_release_bits_size = io_lsu_release_bits_size_0; // @[dcache.scala:145:7] assign io_lsu_release_bits_source = io_lsu_release_bits_source_0; // @[dcache.scala:145:7] assign io_lsu_release_bits_address = io_lsu_release_bits_address_0; // @[dcache.scala:145:7] assign io_state_valid = io_state_valid_0; // @[dcache.scala:145:7] assign io_state_bits = io_state_bits_0; // @[dcache.scala:145:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_67 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_67( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_240 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_257 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_240( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_257 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_4 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}} inst input_buffer of InputBuffer_4 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) inst route_arbiter of Arbiter6_RouteComputerReq_4 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<6>}[6], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_10 : connect states[0].g, UInt<3>(0h2) node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_11 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_11 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_12 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_12 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_13 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_13 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_14 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_14 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_15 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_15 : connect states[5].g, UInt<3>(0h2) node _T_16 = and(io.router_req.ready, io.router_req.valid) when _T_16 : node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_21 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_22 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_23 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_24 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_25 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_26 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` regreset mask : UInt<6>, clock, reset, UInt<6>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}[6] wire vcalloc_vals : UInt<1>[6] node vcalloc_filter_lo_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_vals[0]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[3]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_vals[0]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[3]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_16, UInt<12>(0h800), UInt<12>(0h0)) node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_15, UInt<12>(0h400), _vcalloc_filter_T_17) node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_14, UInt<12>(0h200), _vcalloc_filter_T_18) node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_13, UInt<12>(0h100), _vcalloc_filter_T_19) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_12, UInt<12>(0h80), _vcalloc_filter_T_20) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_11, UInt<12>(0h40), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_10, UInt<12>(0h20), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_9, UInt<12>(0h10), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_8, UInt<12>(0h8), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_7, UInt<12>(0h4), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_6, UInt<12>(0h2), _vcalloc_filter_T_26) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<12>(0h1), _vcalloc_filter_T_27) node _vcalloc_sel_T = bits(vcalloc_filter, 5, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 6) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_27 = and(io.router_req.ready, io.router_req.valid) when _T_27 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_28 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_29 = or(_T_28, vcalloc_vals[2]) node _T_30 = or(_T_29, vcalloc_vals[3]) node _T_31 = or(_T_30, vcalloc_vals[4]) node _T_32 = or(_T_31, vcalloc_vals[5]) when _T_32 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = bits(vcalloc_sel, 0, 0) node _mask_T_10 = bits(vcalloc_sel, 1, 1) node _mask_T_11 = bits(vcalloc_sel, 2, 2) node _mask_T_12 = bits(vcalloc_sel, 3, 3) node _mask_T_13 = bits(vcalloc_sel, 4, 4) node _mask_T_14 = bits(vcalloc_sel, 5, 5) node _mask_T_15 = mux(_mask_T_9, _mask_T_3, UInt<1>(0h0)) node _mask_T_16 = mux(_mask_T_10, _mask_T_4, UInt<1>(0h0)) node _mask_T_17 = mux(_mask_T_11, _mask_T_5, UInt<1>(0h0)) node _mask_T_18 = mux(_mask_T_12, _mask_T_6, UInt<1>(0h0)) node _mask_T_19 = mux(_mask_T_13, _mask_T_7, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_14, _mask_T_8, UInt<1>(0h0)) node _mask_T_21 = or(_mask_T_15, _mask_T_16) node _mask_T_22 = or(_mask_T_21, _mask_T_17) node _mask_T_23 = or(_mask_T_22, _mask_T_18) node _mask_T_24 = or(_mask_T_23, _mask_T_19) node _mask_T_25 = or(_mask_T_24, _mask_T_20) wire _mask_WIRE : UInt<6> connect _mask_WIRE, _mask_T_25 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_4 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}} wire _io_vcalloc_req_bits_WIRE_1 : { `1` : UInt<1>[1], `0` : UInt<1>[6]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[6] node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_7) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_8) node _io_vcalloc_req_bits_T_14 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_15 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_15, _io_vcalloc_req_bits_T_11) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_16 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_22 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_20) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_21) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_22) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_33) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_38 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_44) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_49 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_60 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_62) node _io_vcalloc_req_bits_T_68 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_63) node _io_vcalloc_req_bits_T_69 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_70 = or(_io_vcalloc_req_bits_T_69, _io_vcalloc_req_bits_T_65) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_70, _io_vcalloc_req_bits_T_66) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_71 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>[1] node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_72, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_76) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_77) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_9[0], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_9 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_90 = or(_io_vcalloc_req_bits_T_89, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_90, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_88) wire _io_vcalloc_req_bits_WIRE_11 : UInt<3> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_93 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_12 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_95) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_96) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_97) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_98) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_99) wire _io_vcalloc_req_bits_WIRE_13 : UInt<2> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE_12.egress_node_id, _io_vcalloc_req_bits_WIRE_13 node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_113 = or(_io_vcalloc_req_bits_T_112, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_114 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_114, _io_vcalloc_req_bits_T_110) wire _io_vcalloc_req_bits_WIRE_14 : UInt<4> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_115 connect _io_vcalloc_req_bits_WIRE_12.egress_node, _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_120) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_121) wire _io_vcalloc_req_bits_WIRE_15 : UInt<2> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_126 connect _io_vcalloc_req_bits_WIRE_12.ingress_node_id, _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_133, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_132) wire _io_vcalloc_req_bits_WIRE_16 : UInt<4> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_137 connect _io_vcalloc_req_bits_WIRE_12.ingress_node, _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_138 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_139 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_140 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_141 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_142 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_139) node _io_vcalloc_req_bits_T_145 = or(_io_vcalloc_req_bits_T_144, _io_vcalloc_req_bits_T_140) node _io_vcalloc_req_bits_T_146 = or(_io_vcalloc_req_bits_T_145, _io_vcalloc_req_bits_T_141) node _io_vcalloc_req_bits_T_147 = or(_io_vcalloc_req_bits_T_146, _io_vcalloc_req_bits_T_142) node _io_vcalloc_req_bits_T_148 = or(_io_vcalloc_req_bits_T_147, _io_vcalloc_req_bits_T_143) wire _io_vcalloc_req_bits_WIRE_17 : UInt<2> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_148 connect _io_vcalloc_req_bits_WIRE_12.vnet_id, _io_vcalloc_req_bits_WIRE_17 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_12 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].flow, states[0].flow node _T_33 = bits(vcalloc_sel, 0, 0) node _T_34 = and(vcalloc_vals[0], _T_33) node _T_35 = and(_T_34, io.vcalloc_req.ready) when _T_35 : connect states[0].g, UInt<3>(0h3) node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].flow, states[1].flow node _T_36 = bits(vcalloc_sel, 1, 1) node _T_37 = and(vcalloc_vals[1], _T_36) node _T_38 = and(_T_37, io.vcalloc_req.ready) when _T_38 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].flow, states[2].flow node _T_39 = bits(vcalloc_sel, 2, 2) node _T_40 = and(vcalloc_vals[2], _T_39) node _T_41 = and(_T_40, io.vcalloc_req.ready) when _T_41 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].flow, states[3].flow node _T_42 = bits(vcalloc_sel, 3, 3) node _T_43 = and(vcalloc_vals[3], _T_42) node _T_44 = and(_T_43, io.vcalloc_req.ready) when _T_44 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].flow, states[4].flow node _T_45 = bits(vcalloc_sel, 4, 4) node _T_46 = and(vcalloc_vals[4], _T_45) node _T_47 = and(_T_46, io.vcalloc_req.ready) when _T_47 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].flow, states[5].flow node _T_48 = bits(vcalloc_sel, 5, 5) node _T_49 = and(vcalloc_vals[5], _T_48) node _T_50 = and(_T_49, io.vcalloc_req.ready) when _T_50 : connect states[5].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[3], _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(_io_debug_va_stall_T_3, _io_debug_va_stall_T_7) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 2, 0) node _io_debug_va_stall_T_10 = sub(_io_debug_va_stall_T_9, io.vcalloc_req.ready) node _io_debug_va_stall_T_11 = tail(_io_debug_va_stall_T_10, 1) connect io.debug.va_stall, _io_debug_va_stall_T_11 node _T_51 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_51 : node _T_52 = bits(vcalloc_sel, 0, 0) when _T_52 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].g, UInt<3>(0h3) node _T_53 = eq(states[0].g, UInt<3>(0h2)) node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : node _T_56 = eq(_T_53, UInt<1>(0h0)) when _T_56 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_53, UInt<1>(0h1), "") : assert_3 node _T_57 = bits(vcalloc_sel, 1, 1) when _T_57 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].g, UInt<3>(0h3) node _T_58 = eq(states[1].g, UInt<3>(0h2)) node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_T_58, UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_58, UInt<1>(0h1), "") : assert_4 node _T_62 = bits(vcalloc_sel, 2, 2) when _T_62 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].g, UInt<3>(0h3) node _T_63 = eq(states[2].g, UInt<3>(0h2)) node _T_64 = asUInt(reset) node _T_65 = eq(_T_64, UInt<1>(0h0)) when _T_65 : node _T_66 = eq(_T_63, UInt<1>(0h0)) when _T_66 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_63, UInt<1>(0h1), "") : assert_5 node _T_67 = bits(vcalloc_sel, 3, 3) when _T_67 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].g, UInt<3>(0h3) node _T_68 = eq(states[3].g, UInt<3>(0h2)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_68, UInt<1>(0h1), "") : assert_6 node _T_72 = bits(vcalloc_sel, 4, 4) when _T_72 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].g, UInt<3>(0h3) node _T_73 = eq(states[4].g, UInt<3>(0h2)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_73, UInt<1>(0h1), "") : assert_7 node _T_77 = bits(vcalloc_sel, 5, 5) when _T_77 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].g, UInt<3>(0h3) node _T_78 = eq(states[5].g, UInt<3>(0h2)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_78, UInt<1>(0h1), "") : assert_8 inst salloc_arb of SwitchArbiter_12 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_lo_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1]) node credit_available_lo = cat(credit_available_lo_hi, states[0].vc_sel.`0`[0]) node credit_available_hi_hi = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4]) node credit_available_hi = cat(credit_available_hi_hi, states[0].vc_sel.`0`[3]) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node _credit_available_T_1 = cat(states[0].vc_sel.`1`[0], _credit_available_T) node credit_available_lo_hi_1 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, io.out_credit_available.`0`[0]) node credit_available_hi_hi_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, io.out_credit_available.`0`[3]) node _credit_available_T_2 = cat(credit_available_hi_1, credit_available_lo_1) node _credit_available_T_3 = cat(io.out_credit_available.`1`[0], _credit_available_T_2) node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3) node credit_available = neq(_credit_available_T_4, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3] connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4] connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_82 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_83 = and(_T_82, input_buffer.io.deq[0].bits.tail) when _T_83 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready node credit_available_lo_hi_2 = cat(states[1].vc_sel.`0`[2], states[1].vc_sel.`0`[1]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, states[1].vc_sel.`0`[0]) node credit_available_hi_hi_2 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, states[1].vc_sel.`0`[3]) node _credit_available_T_5 = cat(credit_available_hi_2, credit_available_lo_2) node _credit_available_T_6 = cat(states[1].vc_sel.`1`[0], _credit_available_T_5) node credit_available_lo_hi_3 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, io.out_credit_available.`0`[0]) node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, io.out_credit_available.`0`[3]) node _credit_available_T_7 = cat(credit_available_hi_3, credit_available_lo_3) node _credit_available_T_8 = cat(io.out_credit_available.`1`[0], _credit_available_T_7) node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8) node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_84 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_85 = and(_T_84, input_buffer.io.deq[1].bits.tail) when _T_85 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_hi_4 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, states[2].vc_sel.`0`[0]) node credit_available_hi_hi_4 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_4 = cat(credit_available_hi_hi_4, states[2].vc_sel.`0`[3]) node _credit_available_T_10 = cat(credit_available_hi_4, credit_available_lo_4) node _credit_available_T_11 = cat(states[2].vc_sel.`1`[0], _credit_available_T_10) node credit_available_lo_hi_5 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_5 = cat(credit_available_lo_hi_5, io.out_credit_available.`0`[0]) node credit_available_hi_hi_5 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_5 = cat(credit_available_hi_hi_5, io.out_credit_available.`0`[3]) node _credit_available_T_12 = cat(credit_available_hi_5, credit_available_lo_5) node _credit_available_T_13 = cat(io.out_credit_available.`1`[0], _credit_available_T_12) node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13) node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_86 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_87 = and(_T_86, input_buffer.io.deq[2].bits.tail) when _T_87 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_hi_6 = cat(states[3].vc_sel.`0`[2], states[3].vc_sel.`0`[1]) node credit_available_lo_6 = cat(credit_available_lo_hi_6, states[3].vc_sel.`0`[0]) node credit_available_hi_hi_6 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_6 = cat(credit_available_hi_hi_6, states[3].vc_sel.`0`[3]) node _credit_available_T_15 = cat(credit_available_hi_6, credit_available_lo_6) node _credit_available_T_16 = cat(states[3].vc_sel.`1`[0], _credit_available_T_15) node credit_available_lo_hi_7 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_7 = cat(credit_available_lo_hi_7, io.out_credit_available.`0`[0]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_7 = cat(credit_available_hi_hi_7, io.out_credit_available.`0`[3]) node _credit_available_T_17 = cat(credit_available_hi_7, credit_available_lo_7) node _credit_available_T_18 = cat(io.out_credit_available.`1`[0], _credit_available_T_17) node _credit_available_T_19 = and(_credit_available_T_16, _credit_available_T_18) node credit_available_3 = neq(_credit_available_T_19, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_88 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_89 = and(_T_88, input_buffer.io.deq[3].bits.tail) when _T_89 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_hi_8 = cat(states[4].vc_sel.`0`[2], states[4].vc_sel.`0`[1]) node credit_available_lo_8 = cat(credit_available_lo_hi_8, states[4].vc_sel.`0`[0]) node credit_available_hi_hi_8 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_8 = cat(credit_available_hi_hi_8, states[4].vc_sel.`0`[3]) node _credit_available_T_20 = cat(credit_available_hi_8, credit_available_lo_8) node _credit_available_T_21 = cat(states[4].vc_sel.`1`[0], _credit_available_T_20) node credit_available_lo_hi_9 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_9 = cat(credit_available_lo_hi_9, io.out_credit_available.`0`[0]) node credit_available_hi_hi_9 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_9 = cat(credit_available_hi_hi_9, io.out_credit_available.`0`[3]) node _credit_available_T_22 = cat(credit_available_hi_9, credit_available_lo_9) node _credit_available_T_23 = cat(io.out_credit_available.`1`[0], _credit_available_T_22) node _credit_available_T_24 = and(_credit_available_T_21, _credit_available_T_23) node credit_available_4 = neq(_credit_available_T_24, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_90 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_91 = and(_T_90, input_buffer.io.deq[4].bits.tail) when _T_91 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_hi_10 = cat(states[5].vc_sel.`0`[2], states[5].vc_sel.`0`[1]) node credit_available_lo_10 = cat(credit_available_lo_hi_10, states[5].vc_sel.`0`[0]) node credit_available_hi_hi_10 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_10 = cat(credit_available_hi_hi_10, states[5].vc_sel.`0`[3]) node _credit_available_T_25 = cat(credit_available_hi_10, credit_available_lo_10) node _credit_available_T_26 = cat(states[5].vc_sel.`1`[0], _credit_available_T_25) node credit_available_lo_hi_11 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node credit_available_lo_11 = cat(credit_available_lo_hi_11, io.out_credit_available.`0`[0]) node credit_available_hi_hi_11 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_11 = cat(credit_available_hi_hi_11, io.out_credit_available.`0`[3]) node _credit_available_T_27 = cat(credit_available_hi_11, credit_available_lo_11) node _credit_available_T_28 = cat(io.out_credit_available.`1`[0], _credit_available_T_27) node _credit_available_T_29 = and(_credit_available_T_26, _credit_available_T_28) node credit_available_5 = neq(_credit_available_T_29, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_92 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_93 = and(_T_92, input_buffer.io.deq[5].bits.tail) when _T_93 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0) node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_17) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_21 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_8) node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_9) node _io_in_vc_free_T_15 = or(_io_in_vc_free_T_14, _io_in_vc_free_T_10) node _io_in_vc_free_T_16 = or(_io_in_vc_free_T_15, _io_in_vc_free_T_11) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_16, _io_in_vc_free_T_12) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_17 node _io_in_vc_free_T_18 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_18, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_19 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 5, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) wire vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]} wire _vc_sel_WIRE : UInt<1>[6] node _vc_sel_T_6 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_7 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_8 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = or(_vc_sel_T_6, _vc_sel_T_7) node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_8) node _vc_sel_T_14 = or(_vc_sel_T_13, _vc_sel_T_9) node _vc_sel_T_15 = or(_vc_sel_T_14, _vc_sel_T_10) node _vc_sel_T_16 = or(_vc_sel_T_15, _vc_sel_T_11) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_16 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_21 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_22 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_23 = or(_vc_sel_T_17, _vc_sel_T_18) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_19) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_20) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_21) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_22) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_27 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_34 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_30) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_31) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_32) node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_33) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_38 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_39 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_45 = or(_vc_sel_T_39, _vc_sel_T_40) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_41) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_42) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_43) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_44) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_49 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_56 = or(_vc_sel_T_50, _vc_sel_T_51) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_52) node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_53) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_54) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_55) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_60 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_61 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_62 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_63 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_64 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_65 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_66 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_67 = or(_vc_sel_T_61, _vc_sel_T_62) node _vc_sel_T_68 = or(_vc_sel_T_67, _vc_sel_T_63) node _vc_sel_T_69 = or(_vc_sel_T_68, _vc_sel_T_64) node _vc_sel_T_70 = or(_vc_sel_T_69, _vc_sel_T_65) node _vc_sel_T_71 = or(_vc_sel_T_70, _vc_sel_T_66) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_71 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_7 : UInt<1>[1] node _vc_sel_T_72 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_77 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_78 = or(_vc_sel_T_72, _vc_sel_T_73) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_74) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_75) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_76) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_77) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_82 connect _vc_sel_WIRE_7[0], _vc_sel_WIRE_8 connect vc_sel.`1`, _vc_sel_WIRE_7 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node channel_oh_0 = or(_channel_oh_T_3, vc_sel.`0`[5]) node virt_channel_lo_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node virt_channel_lo = cat(virt_channel_lo_hi, vc_sel.`0`[0]) node virt_channel_hi_hi = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[3]) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 5, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node _virt_channel_T_8 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_9 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_10 = or(_virt_channel_T_8, _virt_channel_T_9) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_10 node _T_94 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_94 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_7) node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_8) node _salloc_outs_0_flit_payload_T_14 = or(_salloc_outs_0_flit_payload_T_13, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_15 = or(_salloc_outs_0_flit_payload_T_14, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_15, _salloc_outs_0_flit_payload_T_11) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_16 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_7) node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_8) node _salloc_outs_0_flit_head_T_14 = or(_salloc_outs_0_flit_head_T_13, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_15 = or(_salloc_outs_0_flit_head_T_14, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_15, _salloc_outs_0_flit_head_T_11) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_16 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_7) node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_8) node _salloc_outs_0_flit_tail_T_14 = or(_salloc_outs_0_flit_tail_T_13, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_15 = or(_salloc_outs_0_flit_tail_T_14, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_15, _salloc_outs_0_flit_tail_T_11) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_16 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_7) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_8) node _salloc_outs_0_flit_flow_T_14 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_15 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_15, _salloc_outs_0_flit_flow_T_11) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_16 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_22 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_20) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_21) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_22) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_33) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_38 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_44) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_49 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_57 = or(_salloc_outs_0_flit_flow_T_56, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_57, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_55) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_60 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`0`[2], UInt<1>(0h0) connect states[0].vc_sel.`0`[3], UInt<1>(0h0) connect states[0].vc_sel.`0`[4], UInt<1>(0h0) connect states[0].vc_sel.`0`[5], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`0`[3], UInt<1>(0h0) connect states[1].vc_sel.`0`[4], UInt<1>(0h0) connect states[1].vc_sel.`0`[5], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`0`[3], UInt<1>(0h0) connect states[2].vc_sel.`0`[4], UInt<1>(0h0) connect states[2].vc_sel.`0`[5], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`0`[1], UInt<1>(0h0) connect states[3].vc_sel.`0`[4], UInt<1>(0h0) connect states[3].vc_sel.`0`[5], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`0`[2], UInt<1>(0h0) connect states[4].vc_sel.`0`[3], UInt<1>(0h0) connect states[4].vc_sel.`0`[5], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`0`[1], UInt<1>(0h0) connect states[5].vc_sel.`0`[2], UInt<1>(0h0) connect states[5].vc_sel.`0`[3], UInt<1>(0h0) node _T_95 = asUInt(reset) when _T_95 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0)
module InputUnit_4( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [5:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [5:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [5:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [5:0] mask; // @[InputUnit.scala:250:21] wire [5:0] _vcalloc_filter_T_3 = {vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [11:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 12'h1 : _vcalloc_filter_T_3[1] ? 12'h2 : _vcalloc_filter_T_3[2] ? 12'h4 : _vcalloc_filter_T_3[3] ? 12'h8 : _vcalloc_filter_T_3[4] ? 12'h10 : _vcalloc_filter_T_3[5] ? 12'h20 : vcalloc_vals_0 ? 12'h40 : vcalloc_vals_1 ? 12'h80 : vcalloc_vals_2 ? 12'h100 : vcalloc_vals_3 ? 12'h200 : vcalloc_vals_4 ? 12'h400 : {vcalloc_vals_5, 11'h0}; // @[OneHot.scala:85:71] wire [5:0] vcalloc_sel = vcalloc_filter[5:0] | vcalloc_filter[11:6]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_309 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_309( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_116 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_116( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ICache_3 : input clock : Clock input reset : Reset output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<39>}}, flip s1_paddr : UInt<32>, flip s1_kill : UInt<1>, flip s2_kill : UInt<1>, resp : { valid : UInt<1>, bits : { data : UInt<128>, replay : UInt<1>, ae : UInt<1>}}, flip invalidate : UInt<1>, perf : { acquire : UInt<1>}} wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect auto.master_out, masterNodeOut node s0_valid = and(io.req.ready, io.req.valid) reg s1_valid : UInt<1>, clock connect s1_valid, s0_valid wire s1_tag_hit : UInt<1>[8] node _s1_hit_T = or(s1_tag_hit[0], s1_tag_hit[1]) node _s1_hit_T_1 = or(_s1_hit_T, s1_tag_hit[2]) node _s1_hit_T_2 = or(_s1_hit_T_1, s1_tag_hit[3]) node _s1_hit_T_3 = or(_s1_hit_T_2, s1_tag_hit[4]) node _s1_hit_T_4 = or(_s1_hit_T_3, s1_tag_hit[5]) node _s1_hit_T_5 = or(_s1_hit_T_4, s1_tag_hit[6]) node s1_hit = or(_s1_hit_T_5, s1_tag_hit[7]) node _s2_valid_T = eq(io.s1_kill, UInt<1>(0h0)) node _s2_valid_T_1 = and(s1_valid, _s2_valid_T) reg s2_valid : UInt<1>, clock connect s2_valid, _s2_valid_T_1 reg s2_hit : UInt<1>, clock connect s2_hit, s1_hit reg invalidated : UInt<1>, clock regreset refill_valid : UInt<1>, clock, reset, UInt<1>(0h0) node refill_fire = and(masterNodeOut.a.ready, masterNodeOut.a.valid) node _s2_miss_T = eq(s2_hit, UInt<1>(0h0)) node _s2_miss_T_1 = and(s2_valid, _s2_miss_T) reg s2_miss_REG : UInt<1>, clock connect s2_miss_REG, refill_valid node _s2_miss_T_2 = eq(s2_miss_REG, UInt<1>(0h0)) node s2_miss = and(_s2_miss_T_1, _s2_miss_T_2) node _refill_paddr_T = or(refill_valid, s2_miss) node _refill_paddr_T_1 = eq(_refill_paddr_T, UInt<1>(0h0)) node _refill_paddr_T_2 = and(s1_valid, _refill_paddr_T_1) reg refill_paddr : UInt<32>, clock when _refill_paddr_T_2 : connect refill_paddr, io.s1_paddr node refill_tag = bits(refill_paddr, 31, 12) node refill_idx = bits(refill_paddr, 11, 6) node _refill_one_beat_T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node refill_one_beat_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) node refill_one_beat = and(_refill_one_beat_T, refill_one_beat_opdata) node _io_req_ready_T = eq(refill_one_beat, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), masterNodeOut.d.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 4) node r_beats1_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node d_done = and(r_2, _T) node _r_count_T = not(r_counter1) node refill_cnt = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_done = and(refill_one_beat, d_done) connect masterNodeOut.d.ready, UInt<1>(0h1) inst repl_way_prng of MaxPeriodFibonacciLFSR_16 connect repl_way_prng.clock, clock connect repl_way_prng.reset, reset connect repl_way_prng.io.seed.valid, UInt<1>(0h0) invalidate repl_way_prng.io.seed.bits[0] invalidate repl_way_prng.io.seed.bits[1] invalidate repl_way_prng.io.seed.bits[2] invalidate repl_way_prng.io.seed.bits[3] invalidate repl_way_prng.io.seed.bits[4] invalidate repl_way_prng.io.seed.bits[5] invalidate repl_way_prng.io.seed.bits[6] invalidate repl_way_prng.io.seed.bits[7] invalidate repl_way_prng.io.seed.bits[8] invalidate repl_way_prng.io.seed.bits[9] invalidate repl_way_prng.io.seed.bits[10] invalidate repl_way_prng.io.seed.bits[11] invalidate repl_way_prng.io.seed.bits[12] invalidate repl_way_prng.io.seed.bits[13] invalidate repl_way_prng.io.seed.bits[14] invalidate repl_way_prng.io.seed.bits[15] connect repl_way_prng.io.increment, refill_fire node repl_way_lo_lo_lo = cat(repl_way_prng.io.out[1], repl_way_prng.io.out[0]) node repl_way_lo_lo_hi = cat(repl_way_prng.io.out[3], repl_way_prng.io.out[2]) node repl_way_lo_lo = cat(repl_way_lo_lo_hi, repl_way_lo_lo_lo) node repl_way_lo_hi_lo = cat(repl_way_prng.io.out[5], repl_way_prng.io.out[4]) node repl_way_lo_hi_hi = cat(repl_way_prng.io.out[7], repl_way_prng.io.out[6]) node repl_way_lo_hi = cat(repl_way_lo_hi_hi, repl_way_lo_hi_lo) node repl_way_lo = cat(repl_way_lo_hi, repl_way_lo_lo) node repl_way_hi_lo_lo = cat(repl_way_prng.io.out[9], repl_way_prng.io.out[8]) node repl_way_hi_lo_hi = cat(repl_way_prng.io.out[11], repl_way_prng.io.out[10]) node repl_way_hi_lo = cat(repl_way_hi_lo_hi, repl_way_hi_lo_lo) node repl_way_hi_hi_lo = cat(repl_way_prng.io.out[13], repl_way_prng.io.out[12]) node repl_way_hi_hi_hi = cat(repl_way_prng.io.out[15], repl_way_prng.io.out[14]) node repl_way_hi_hi = cat(repl_way_hi_hi_hi, repl_way_hi_hi_lo) node repl_way_hi = cat(repl_way_hi_hi, repl_way_hi_lo) node _repl_way_T = cat(repl_way_hi, repl_way_lo) node repl_way = bits(_repl_way_T, 2, 0) smem tag_array : UInt<20>[8] [64] node _tag_rdata_T = bits(io.req.bits.addr, 11, 6) node _tag_rdata_T_1 = eq(refill_done, UInt<1>(0h0)) node _tag_rdata_T_2 = and(_tag_rdata_T_1, s0_valid) wire _tag_rdata_WIRE : UInt<6> invalidate _tag_rdata_WIRE when _tag_rdata_T_2 : connect _tag_rdata_WIRE, _tag_rdata_T read mport tag_rdata = tag_array[_tag_rdata_WIRE], clock when refill_done : wire _WIRE : UInt<20>[8] connect _WIRE[0], refill_tag connect _WIRE[1], refill_tag connect _WIRE[2], refill_tag connect _WIRE[3], refill_tag connect _WIRE[4], refill_tag connect _WIRE[5], refill_tag connect _WIRE[6], refill_tag connect _WIRE[7], refill_tag node _T_1 = eq(repl_way, UInt<1>(0h0)) node _T_2 = eq(repl_way, UInt<1>(0h1)) node _T_3 = eq(repl_way, UInt<2>(0h2)) node _T_4 = eq(repl_way, UInt<2>(0h3)) node _T_5 = eq(repl_way, UInt<3>(0h4)) node _T_6 = eq(repl_way, UInt<3>(0h5)) node _T_7 = eq(repl_way, UInt<3>(0h6)) node _T_8 = eq(repl_way, UInt<3>(0h7)) write mport MPORT = tag_array[refill_idx], clock when _T_1 : connect MPORT[0], _WIRE[0] when _T_2 : connect MPORT[1], _WIRE[1] when _T_3 : connect MPORT[2], _WIRE[2] when _T_4 : connect MPORT[3], _WIRE[3] when _T_5 : connect MPORT[4], _WIRE[4] when _T_6 : connect MPORT[5], _WIRE[5] when _T_7 : connect MPORT[6], _WIRE[6] when _T_8 : connect MPORT[7], _WIRE[7] regreset vb_array : UInt<512>, clock, reset, UInt<512>(0h0) when refill_one_beat : node _vb_array_T = cat(repl_way, refill_idx) node _vb_array_T_1 = eq(invalidated, UInt<1>(0h0)) node _vb_array_T_2 = and(refill_done, _vb_array_T_1) node _vb_array_T_3 = dshl(UInt<1>(0h1), _vb_array_T) node _vb_array_T_4 = or(vb_array, _vb_array_T_3) node _vb_array_T_5 = not(vb_array) node _vb_array_T_6 = or(_vb_array_T_5, _vb_array_T_3) node _vb_array_T_7 = not(_vb_array_T_6) node _vb_array_T_8 = mux(_vb_array_T_2, _vb_array_T_4, _vb_array_T_7) connect vb_array, _vb_array_T_8 when io.invalidate : connect vb_array, UInt<1>(0h0) connect invalidated, UInt<1>(0h1) wire s2_dout : UInt<128>[8] wire s1_bankid : UInt<1> node s1_idx = bits(io.s1_paddr, 11, 6) node s1_tag = bits(io.s1_paddr, 31, 12) node _s1_vb_T = cat(UInt<1>(0h0), s1_idx) node _s1_vb_T_1 = dshr(vb_array, _s1_vb_T) node s1_vb = bits(_s1_vb_T_1, 0, 0) node _s1_tag_hit_0_T = eq(tag_rdata[0], s1_tag) node _s1_tag_hit_0_T_1 = and(s1_vb, _s1_tag_hit_0_T) connect s1_tag_hit[0], _s1_tag_hit_0_T_1 node s1_idx_1 = bits(io.s1_paddr, 11, 6) node s1_tag_1 = bits(io.s1_paddr, 31, 12) node _s1_vb_T_2 = cat(UInt<1>(0h1), s1_idx_1) node _s1_vb_T_3 = dshr(vb_array, _s1_vb_T_2) node s1_vb_1 = bits(_s1_vb_T_3, 0, 0) node _s1_tag_hit_1_T = eq(tag_rdata[1], s1_tag_1) node _s1_tag_hit_1_T_1 = and(s1_vb_1, _s1_tag_hit_1_T) connect s1_tag_hit[1], _s1_tag_hit_1_T_1 node s1_idx_2 = bits(io.s1_paddr, 11, 6) node s1_tag_2 = bits(io.s1_paddr, 31, 12) node _s1_vb_T_4 = cat(UInt<2>(0h2), s1_idx_2) node _s1_vb_T_5 = dshr(vb_array, _s1_vb_T_4) node s1_vb_2 = bits(_s1_vb_T_5, 0, 0) node _s1_tag_hit_2_T = eq(tag_rdata[2], s1_tag_2) node _s1_tag_hit_2_T_1 = and(s1_vb_2, _s1_tag_hit_2_T) connect s1_tag_hit[2], _s1_tag_hit_2_T_1 node s1_idx_3 = bits(io.s1_paddr, 11, 6) node s1_tag_3 = bits(io.s1_paddr, 31, 12) node _s1_vb_T_6 = cat(UInt<2>(0h3), s1_idx_3) node _s1_vb_T_7 = dshr(vb_array, _s1_vb_T_6) node s1_vb_3 = bits(_s1_vb_T_7, 0, 0) node _s1_tag_hit_3_T = eq(tag_rdata[3], s1_tag_3) node _s1_tag_hit_3_T_1 = and(s1_vb_3, _s1_tag_hit_3_T) connect s1_tag_hit[3], _s1_tag_hit_3_T_1 node s1_idx_4 = bits(io.s1_paddr, 11, 6) node s1_tag_4 = bits(io.s1_paddr, 31, 12) node _s1_vb_T_8 = cat(UInt<3>(0h4), s1_idx_4) node _s1_vb_T_9 = dshr(vb_array, _s1_vb_T_8) node s1_vb_4 = bits(_s1_vb_T_9, 0, 0) node _s1_tag_hit_4_T = eq(tag_rdata[4], s1_tag_4) node _s1_tag_hit_4_T_1 = and(s1_vb_4, _s1_tag_hit_4_T) connect s1_tag_hit[4], _s1_tag_hit_4_T_1 node s1_idx_5 = bits(io.s1_paddr, 11, 6) node s1_tag_5 = bits(io.s1_paddr, 31, 12) node _s1_vb_T_10 = cat(UInt<3>(0h5), s1_idx_5) node _s1_vb_T_11 = dshr(vb_array, _s1_vb_T_10) node s1_vb_5 = bits(_s1_vb_T_11, 0, 0) node _s1_tag_hit_5_T = eq(tag_rdata[5], s1_tag_5) node _s1_tag_hit_5_T_1 = and(s1_vb_5, _s1_tag_hit_5_T) connect s1_tag_hit[5], _s1_tag_hit_5_T_1 node s1_idx_6 = bits(io.s1_paddr, 11, 6) node s1_tag_6 = bits(io.s1_paddr, 31, 12) node _s1_vb_T_12 = cat(UInt<3>(0h6), s1_idx_6) node _s1_vb_T_13 = dshr(vb_array, _s1_vb_T_12) node s1_vb_6 = bits(_s1_vb_T_13, 0, 0) node _s1_tag_hit_6_T = eq(tag_rdata[6], s1_tag_6) node _s1_tag_hit_6_T_1 = and(s1_vb_6, _s1_tag_hit_6_T) connect s1_tag_hit[6], _s1_tag_hit_6_T_1 node s1_idx_7 = bits(io.s1_paddr, 11, 6) node s1_tag_7 = bits(io.s1_paddr, 31, 12) node _s1_vb_T_14 = cat(UInt<3>(0h7), s1_idx_7) node _s1_vb_T_15 = dshr(vb_array, _s1_vb_T_14) node s1_vb_7 = bits(_s1_vb_T_15, 0, 0) node _s1_tag_hit_7_T = eq(tag_rdata[7], s1_tag_7) node _s1_tag_hit_7_T_1 = and(s1_vb_7, _s1_tag_hit_7_T) connect s1_tag_hit[7], _s1_tag_hit_7_T_1 node _T_9 = add(s1_tag_hit[0], s1_tag_hit[1]) node _T_10 = bits(_T_9, 1, 0) node _T_11 = add(s1_tag_hit[2], s1_tag_hit[3]) node _T_12 = bits(_T_11, 1, 0) node _T_13 = add(_T_10, _T_12) node _T_14 = bits(_T_13, 2, 0) node _T_15 = add(s1_tag_hit[4], s1_tag_hit[5]) node _T_16 = bits(_T_15, 1, 0) node _T_17 = add(s1_tag_hit[6], s1_tag_hit[7]) node _T_18 = bits(_T_17, 1, 0) node _T_19 = add(_T_16, _T_18) node _T_20 = bits(_T_19, 2, 0) node _T_21 = add(_T_14, _T_20) node _T_22 = bits(_T_21, 3, 0) node _T_23 = leq(_T_22, UInt<1>(0h1)) node _T_24 = eq(s1_valid, UInt<1>(0h0)) node _T_25 = or(_T_23, _T_24) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at icache.scala:179 assert(PopCount(s1_tag_hit) <= 1.U || !s1_valid)\n") : printf assert(clock, _T_25, UInt<1>(0h1), "") : assert smem dataArrayB0Way_0 : UInt<64> [256] smem dataArrayB0Way_1 : UInt<64> [256] smem dataArrayB0Way_2 : UInt<64> [256] smem dataArrayB0Way_3 : UInt<64> [256] smem dataArrayB0Way_4 : UInt<64> [256] smem dataArrayB0Way_5 : UInt<64> [256] smem dataArrayB0Way_6 : UInt<64> [256] smem dataArrayB0Way_7 : UInt<64> [256] smem dataArrayB1Way_0 : UInt<64> [256] smem dataArrayB1Way_1 : UInt<64> [256] smem dataArrayB1Way_2 : UInt<64> [256] smem dataArrayB1Way_3 : UInt<64> [256] smem dataArrayB1Way_4 : UInt<64> [256] smem dataArrayB1Way_5 : UInt<64> [256] smem dataArrayB1Way_6 : UInt<64> [256] smem dataArrayB1Way_7 : UInt<64> [256] node _s1_bankid_T = bits(io.req.bits.addr, 3, 3) reg s1_bankid_REG : UInt<1>, clock connect s1_bankid_REG, _s1_bankid_T connect s1_bankid, s1_bankid_REG node _wen_T = eq(invalidated, UInt<1>(0h0)) node _wen_T_1 = and(refill_one_beat, _wen_T) node _wen_T_2 = eq(repl_way, UInt<1>(0h0)) node wen = and(_wen_T_1, _wen_T_2) node _T_29 = shl(refill_idx, 2) node _T_30 = or(_T_29, refill_cnt) node _T_31 = bits(io.req.bits.addr, 11, 4) node _T_32 = bits(io.req.bits.addr, 3, 3) node _T_33 = add(_T_31, _T_32) node _T_34 = tail(_T_33, 1) node _T_35 = mux(refill_one_beat, _T_30, _T_34) node _T_36 = shl(refill_idx, 2) node _T_37 = or(_T_36, refill_cnt) node _T_38 = bits(io.req.bits.addr, 11, 4) node _T_39 = mux(refill_one_beat, _T_37, _T_38) when wen : node _T_40 = bits(masterNodeOut.d.bits.data, 63, 0) write mport MPORT_1 = dataArrayB0Way_0[_T_35], clock connect MPORT_1, _T_40 node _T_41 = bits(masterNodeOut.d.bits.data, 127, 64) write mport MPORT_2 = dataArrayB1Way_0[_T_39], clock connect MPORT_2, _T_41 node _s2_dout_0_T = eq(wen, UInt<1>(0h0)) node _s2_dout_0_T_1 = and(_s2_dout_0_T, s0_valid) wire _s2_dout_0_WIRE : UInt<8> invalidate _s2_dout_0_WIRE when _s2_dout_0_T_1 : connect _s2_dout_0_WIRE, _T_39 read mport s2_dout_0_MPORT = dataArrayB1Way_0[_s2_dout_0_WIRE], clock node _s2_dout_0_T_2 = eq(wen, UInt<1>(0h0)) node _s2_dout_0_T_3 = and(_s2_dout_0_T_2, s0_valid) wire _s2_dout_0_WIRE_1 : UInt<8> invalidate _s2_dout_0_WIRE_1 when _s2_dout_0_T_3 : connect _s2_dout_0_WIRE_1, _T_35 read mport s2_dout_0_MPORT_1 = dataArrayB0Way_0[_s2_dout_0_WIRE_1], clock node _s2_dout_0_T_4 = cat(s2_dout_0_MPORT, s2_dout_0_MPORT_1) reg s2_dout_0_REG : UInt, clock connect s2_dout_0_REG, _s2_dout_0_T_4 connect s2_dout[0], s2_dout_0_REG node _wen_T_3 = eq(invalidated, UInt<1>(0h0)) node _wen_T_4 = and(refill_one_beat, _wen_T_3) node _wen_T_5 = eq(repl_way, UInt<1>(0h1)) node wen_1 = and(_wen_T_4, _wen_T_5) node _T_42 = shl(refill_idx, 2) node _T_43 = or(_T_42, refill_cnt) node _T_44 = bits(io.req.bits.addr, 11, 4) node _T_45 = bits(io.req.bits.addr, 3, 3) node _T_46 = add(_T_44, _T_45) node _T_47 = tail(_T_46, 1) node _T_48 = mux(refill_one_beat, _T_43, _T_47) node _T_49 = shl(refill_idx, 2) node _T_50 = or(_T_49, refill_cnt) node _T_51 = bits(io.req.bits.addr, 11, 4) node _T_52 = mux(refill_one_beat, _T_50, _T_51) when wen_1 : node _T_53 = bits(masterNodeOut.d.bits.data, 63, 0) write mport MPORT_3 = dataArrayB0Way_1[_T_48], clock connect MPORT_3, _T_53 node _T_54 = bits(masterNodeOut.d.bits.data, 127, 64) write mport MPORT_4 = dataArrayB1Way_1[_T_52], clock connect MPORT_4, _T_54 node _s2_dout_1_T = eq(wen_1, UInt<1>(0h0)) node _s2_dout_1_T_1 = and(_s2_dout_1_T, s0_valid) wire _s2_dout_1_WIRE : UInt<8> invalidate _s2_dout_1_WIRE when _s2_dout_1_T_1 : connect _s2_dout_1_WIRE, _T_52 read mport s2_dout_1_MPORT = dataArrayB1Way_1[_s2_dout_1_WIRE], clock node _s2_dout_1_T_2 = eq(wen_1, UInt<1>(0h0)) node _s2_dout_1_T_3 = and(_s2_dout_1_T_2, s0_valid) wire _s2_dout_1_WIRE_1 : UInt<8> invalidate _s2_dout_1_WIRE_1 when _s2_dout_1_T_3 : connect _s2_dout_1_WIRE_1, _T_48 read mport s2_dout_1_MPORT_1 = dataArrayB0Way_1[_s2_dout_1_WIRE_1], clock node _s2_dout_1_T_4 = cat(s2_dout_1_MPORT, s2_dout_1_MPORT_1) reg s2_dout_1_REG : UInt, clock connect s2_dout_1_REG, _s2_dout_1_T_4 connect s2_dout[1], s2_dout_1_REG node _wen_T_6 = eq(invalidated, UInt<1>(0h0)) node _wen_T_7 = and(refill_one_beat, _wen_T_6) node _wen_T_8 = eq(repl_way, UInt<2>(0h2)) node wen_2 = and(_wen_T_7, _wen_T_8) node _T_55 = shl(refill_idx, 2) node _T_56 = or(_T_55, refill_cnt) node _T_57 = bits(io.req.bits.addr, 11, 4) node _T_58 = bits(io.req.bits.addr, 3, 3) node _T_59 = add(_T_57, _T_58) node _T_60 = tail(_T_59, 1) node _T_61 = mux(refill_one_beat, _T_56, _T_60) node _T_62 = shl(refill_idx, 2) node _T_63 = or(_T_62, refill_cnt) node _T_64 = bits(io.req.bits.addr, 11, 4) node _T_65 = mux(refill_one_beat, _T_63, _T_64) when wen_2 : node _T_66 = bits(masterNodeOut.d.bits.data, 63, 0) write mport MPORT_5 = dataArrayB0Way_2[_T_61], clock connect MPORT_5, _T_66 node _T_67 = bits(masterNodeOut.d.bits.data, 127, 64) write mport MPORT_6 = dataArrayB1Way_2[_T_65], clock connect MPORT_6, _T_67 node _s2_dout_2_T = eq(wen_2, UInt<1>(0h0)) node _s2_dout_2_T_1 = and(_s2_dout_2_T, s0_valid) wire _s2_dout_2_WIRE : UInt<8> invalidate _s2_dout_2_WIRE when _s2_dout_2_T_1 : connect _s2_dout_2_WIRE, _T_65 read mport s2_dout_2_MPORT = dataArrayB1Way_2[_s2_dout_2_WIRE], clock node _s2_dout_2_T_2 = eq(wen_2, UInt<1>(0h0)) node _s2_dout_2_T_3 = and(_s2_dout_2_T_2, s0_valid) wire _s2_dout_2_WIRE_1 : UInt<8> invalidate _s2_dout_2_WIRE_1 when _s2_dout_2_T_3 : connect _s2_dout_2_WIRE_1, _T_61 read mport s2_dout_2_MPORT_1 = dataArrayB0Way_2[_s2_dout_2_WIRE_1], clock node _s2_dout_2_T_4 = cat(s2_dout_2_MPORT, s2_dout_2_MPORT_1) reg s2_dout_2_REG : UInt, clock connect s2_dout_2_REG, _s2_dout_2_T_4 connect s2_dout[2], s2_dout_2_REG node _wen_T_9 = eq(invalidated, UInt<1>(0h0)) node _wen_T_10 = and(refill_one_beat, _wen_T_9) node _wen_T_11 = eq(repl_way, UInt<2>(0h3)) node wen_3 = and(_wen_T_10, _wen_T_11) node _T_68 = shl(refill_idx, 2) node _T_69 = or(_T_68, refill_cnt) node _T_70 = bits(io.req.bits.addr, 11, 4) node _T_71 = bits(io.req.bits.addr, 3, 3) node _T_72 = add(_T_70, _T_71) node _T_73 = tail(_T_72, 1) node _T_74 = mux(refill_one_beat, _T_69, _T_73) node _T_75 = shl(refill_idx, 2) node _T_76 = or(_T_75, refill_cnt) node _T_77 = bits(io.req.bits.addr, 11, 4) node _T_78 = mux(refill_one_beat, _T_76, _T_77) when wen_3 : node _T_79 = bits(masterNodeOut.d.bits.data, 63, 0) write mport MPORT_7 = dataArrayB0Way_3[_T_74], clock connect MPORT_7, _T_79 node _T_80 = bits(masterNodeOut.d.bits.data, 127, 64) write mport MPORT_8 = dataArrayB1Way_3[_T_78], clock connect MPORT_8, _T_80 node _s2_dout_3_T = eq(wen_3, UInt<1>(0h0)) node _s2_dout_3_T_1 = and(_s2_dout_3_T, s0_valid) wire _s2_dout_3_WIRE : UInt<8> invalidate _s2_dout_3_WIRE when _s2_dout_3_T_1 : connect _s2_dout_3_WIRE, _T_78 read mport s2_dout_3_MPORT = dataArrayB1Way_3[_s2_dout_3_WIRE], clock node _s2_dout_3_T_2 = eq(wen_3, UInt<1>(0h0)) node _s2_dout_3_T_3 = and(_s2_dout_3_T_2, s0_valid) wire _s2_dout_3_WIRE_1 : UInt<8> invalidate _s2_dout_3_WIRE_1 when _s2_dout_3_T_3 : connect _s2_dout_3_WIRE_1, _T_74 read mport s2_dout_3_MPORT_1 = dataArrayB0Way_3[_s2_dout_3_WIRE_1], clock node _s2_dout_3_T_4 = cat(s2_dout_3_MPORT, s2_dout_3_MPORT_1) reg s2_dout_3_REG : UInt, clock connect s2_dout_3_REG, _s2_dout_3_T_4 connect s2_dout[3], s2_dout_3_REG node _wen_T_12 = eq(invalidated, UInt<1>(0h0)) node _wen_T_13 = and(refill_one_beat, _wen_T_12) node _wen_T_14 = eq(repl_way, UInt<3>(0h4)) node wen_4 = and(_wen_T_13, _wen_T_14) node _T_81 = shl(refill_idx, 2) node _T_82 = or(_T_81, refill_cnt) node _T_83 = bits(io.req.bits.addr, 11, 4) node _T_84 = bits(io.req.bits.addr, 3, 3) node _T_85 = add(_T_83, _T_84) node _T_86 = tail(_T_85, 1) node _T_87 = mux(refill_one_beat, _T_82, _T_86) node _T_88 = shl(refill_idx, 2) node _T_89 = or(_T_88, refill_cnt) node _T_90 = bits(io.req.bits.addr, 11, 4) node _T_91 = mux(refill_one_beat, _T_89, _T_90) when wen_4 : node _T_92 = bits(masterNodeOut.d.bits.data, 63, 0) write mport MPORT_9 = dataArrayB0Way_4[_T_87], clock connect MPORT_9, _T_92 node _T_93 = bits(masterNodeOut.d.bits.data, 127, 64) write mport MPORT_10 = dataArrayB1Way_4[_T_91], clock connect MPORT_10, _T_93 node _s2_dout_4_T = eq(wen_4, UInt<1>(0h0)) node _s2_dout_4_T_1 = and(_s2_dout_4_T, s0_valid) wire _s2_dout_4_WIRE : UInt<8> invalidate _s2_dout_4_WIRE when _s2_dout_4_T_1 : connect _s2_dout_4_WIRE, _T_91 read mport s2_dout_4_MPORT = dataArrayB1Way_4[_s2_dout_4_WIRE], clock node _s2_dout_4_T_2 = eq(wen_4, UInt<1>(0h0)) node _s2_dout_4_T_3 = and(_s2_dout_4_T_2, s0_valid) wire _s2_dout_4_WIRE_1 : UInt<8> invalidate _s2_dout_4_WIRE_1 when _s2_dout_4_T_3 : connect _s2_dout_4_WIRE_1, _T_87 read mport s2_dout_4_MPORT_1 = dataArrayB0Way_4[_s2_dout_4_WIRE_1], clock node _s2_dout_4_T_4 = cat(s2_dout_4_MPORT, s2_dout_4_MPORT_1) reg s2_dout_4_REG : UInt, clock connect s2_dout_4_REG, _s2_dout_4_T_4 connect s2_dout[4], s2_dout_4_REG node _wen_T_15 = eq(invalidated, UInt<1>(0h0)) node _wen_T_16 = and(refill_one_beat, _wen_T_15) node _wen_T_17 = eq(repl_way, UInt<3>(0h5)) node wen_5 = and(_wen_T_16, _wen_T_17) node _T_94 = shl(refill_idx, 2) node _T_95 = or(_T_94, refill_cnt) node _T_96 = bits(io.req.bits.addr, 11, 4) node _T_97 = bits(io.req.bits.addr, 3, 3) node _T_98 = add(_T_96, _T_97) node _T_99 = tail(_T_98, 1) node _T_100 = mux(refill_one_beat, _T_95, _T_99) node _T_101 = shl(refill_idx, 2) node _T_102 = or(_T_101, refill_cnt) node _T_103 = bits(io.req.bits.addr, 11, 4) node _T_104 = mux(refill_one_beat, _T_102, _T_103) when wen_5 : node _T_105 = bits(masterNodeOut.d.bits.data, 63, 0) write mport MPORT_11 = dataArrayB0Way_5[_T_100], clock connect MPORT_11, _T_105 node _T_106 = bits(masterNodeOut.d.bits.data, 127, 64) write mport MPORT_12 = dataArrayB1Way_5[_T_104], clock connect MPORT_12, _T_106 node _s2_dout_5_T = eq(wen_5, UInt<1>(0h0)) node _s2_dout_5_T_1 = and(_s2_dout_5_T, s0_valid) wire _s2_dout_5_WIRE : UInt<8> invalidate _s2_dout_5_WIRE when _s2_dout_5_T_1 : connect _s2_dout_5_WIRE, _T_104 read mport s2_dout_5_MPORT = dataArrayB1Way_5[_s2_dout_5_WIRE], clock node _s2_dout_5_T_2 = eq(wen_5, UInt<1>(0h0)) node _s2_dout_5_T_3 = and(_s2_dout_5_T_2, s0_valid) wire _s2_dout_5_WIRE_1 : UInt<8> invalidate _s2_dout_5_WIRE_1 when _s2_dout_5_T_3 : connect _s2_dout_5_WIRE_1, _T_100 read mport s2_dout_5_MPORT_1 = dataArrayB0Way_5[_s2_dout_5_WIRE_1], clock node _s2_dout_5_T_4 = cat(s2_dout_5_MPORT, s2_dout_5_MPORT_1) reg s2_dout_5_REG : UInt, clock connect s2_dout_5_REG, _s2_dout_5_T_4 connect s2_dout[5], s2_dout_5_REG node _wen_T_18 = eq(invalidated, UInt<1>(0h0)) node _wen_T_19 = and(refill_one_beat, _wen_T_18) node _wen_T_20 = eq(repl_way, UInt<3>(0h6)) node wen_6 = and(_wen_T_19, _wen_T_20) node _T_107 = shl(refill_idx, 2) node _T_108 = or(_T_107, refill_cnt) node _T_109 = bits(io.req.bits.addr, 11, 4) node _T_110 = bits(io.req.bits.addr, 3, 3) node _T_111 = add(_T_109, _T_110) node _T_112 = tail(_T_111, 1) node _T_113 = mux(refill_one_beat, _T_108, _T_112) node _T_114 = shl(refill_idx, 2) node _T_115 = or(_T_114, refill_cnt) node _T_116 = bits(io.req.bits.addr, 11, 4) node _T_117 = mux(refill_one_beat, _T_115, _T_116) when wen_6 : node _T_118 = bits(masterNodeOut.d.bits.data, 63, 0) write mport MPORT_13 = dataArrayB0Way_6[_T_113], clock connect MPORT_13, _T_118 node _T_119 = bits(masterNodeOut.d.bits.data, 127, 64) write mport MPORT_14 = dataArrayB1Way_6[_T_117], clock connect MPORT_14, _T_119 node _s2_dout_6_T = eq(wen_6, UInt<1>(0h0)) node _s2_dout_6_T_1 = and(_s2_dout_6_T, s0_valid) wire _s2_dout_6_WIRE : UInt<8> invalidate _s2_dout_6_WIRE when _s2_dout_6_T_1 : connect _s2_dout_6_WIRE, _T_117 read mport s2_dout_6_MPORT = dataArrayB1Way_6[_s2_dout_6_WIRE], clock node _s2_dout_6_T_2 = eq(wen_6, UInt<1>(0h0)) node _s2_dout_6_T_3 = and(_s2_dout_6_T_2, s0_valid) wire _s2_dout_6_WIRE_1 : UInt<8> invalidate _s2_dout_6_WIRE_1 when _s2_dout_6_T_3 : connect _s2_dout_6_WIRE_1, _T_113 read mport s2_dout_6_MPORT_1 = dataArrayB0Way_6[_s2_dout_6_WIRE_1], clock node _s2_dout_6_T_4 = cat(s2_dout_6_MPORT, s2_dout_6_MPORT_1) reg s2_dout_6_REG : UInt, clock connect s2_dout_6_REG, _s2_dout_6_T_4 connect s2_dout[6], s2_dout_6_REG node _wen_T_21 = eq(invalidated, UInt<1>(0h0)) node _wen_T_22 = and(refill_one_beat, _wen_T_21) node _wen_T_23 = eq(repl_way, UInt<3>(0h7)) node wen_7 = and(_wen_T_22, _wen_T_23) node _T_120 = shl(refill_idx, 2) node _T_121 = or(_T_120, refill_cnt) node _T_122 = bits(io.req.bits.addr, 11, 4) node _T_123 = bits(io.req.bits.addr, 3, 3) node _T_124 = add(_T_122, _T_123) node _T_125 = tail(_T_124, 1) node _T_126 = mux(refill_one_beat, _T_121, _T_125) node _T_127 = shl(refill_idx, 2) node _T_128 = or(_T_127, refill_cnt) node _T_129 = bits(io.req.bits.addr, 11, 4) node _T_130 = mux(refill_one_beat, _T_128, _T_129) when wen_7 : node _T_131 = bits(masterNodeOut.d.bits.data, 63, 0) write mport MPORT_15 = dataArrayB0Way_7[_T_126], clock connect MPORT_15, _T_131 node _T_132 = bits(masterNodeOut.d.bits.data, 127, 64) write mport MPORT_16 = dataArrayB1Way_7[_T_130], clock connect MPORT_16, _T_132 node _s2_dout_7_T = eq(wen_7, UInt<1>(0h0)) node _s2_dout_7_T_1 = and(_s2_dout_7_T, s0_valid) wire _s2_dout_7_WIRE : UInt<8> invalidate _s2_dout_7_WIRE when _s2_dout_7_T_1 : connect _s2_dout_7_WIRE, _T_130 read mport s2_dout_7_MPORT = dataArrayB1Way_7[_s2_dout_7_WIRE], clock node _s2_dout_7_T_2 = eq(wen_7, UInt<1>(0h0)) node _s2_dout_7_T_3 = and(_s2_dout_7_T_2, s0_valid) wire _s2_dout_7_WIRE_1 : UInt<8> invalidate _s2_dout_7_WIRE_1 when _s2_dout_7_T_3 : connect _s2_dout_7_WIRE_1, _T_126 read mport s2_dout_7_MPORT_1 = dataArrayB0Way_7[_s2_dout_7_WIRE_1], clock node _s2_dout_7_T_4 = cat(s2_dout_7_MPORT, s2_dout_7_MPORT_1) reg s2_dout_7_REG : UInt, clock connect s2_dout_7_REG, _s2_dout_7_T_4 connect s2_dout[7], s2_dout_7_REG reg s2_tag_hit : UInt<1>[8], clock connect s2_tag_hit, s1_tag_hit node s2_hit_way_lo_lo = cat(s2_tag_hit[1], s2_tag_hit[0]) node s2_hit_way_lo_hi = cat(s2_tag_hit[3], s2_tag_hit[2]) node s2_hit_way_lo = cat(s2_hit_way_lo_hi, s2_hit_way_lo_lo) node s2_hit_way_hi_lo = cat(s2_tag_hit[5], s2_tag_hit[4]) node s2_hit_way_hi_hi = cat(s2_tag_hit[7], s2_tag_hit[6]) node s2_hit_way_hi = cat(s2_hit_way_hi_hi, s2_hit_way_hi_lo) node _s2_hit_way_T = cat(s2_hit_way_hi, s2_hit_way_lo) node s2_hit_way_hi_1 = bits(_s2_hit_way_T, 7, 4) node s2_hit_way_lo_1 = bits(_s2_hit_way_T, 3, 0) node _s2_hit_way_T_1 = orr(s2_hit_way_hi_1) node _s2_hit_way_T_2 = or(s2_hit_way_hi_1, s2_hit_way_lo_1) node s2_hit_way_hi_2 = bits(_s2_hit_way_T_2, 3, 2) node s2_hit_way_lo_2 = bits(_s2_hit_way_T_2, 1, 0) node _s2_hit_way_T_3 = orr(s2_hit_way_hi_2) node _s2_hit_way_T_4 = or(s2_hit_way_hi_2, s2_hit_way_lo_2) node _s2_hit_way_T_5 = bits(_s2_hit_way_T_4, 1, 1) node _s2_hit_way_T_6 = cat(_s2_hit_way_T_3, _s2_hit_way_T_5) node s2_hit_way = cat(_s2_hit_way_T_1, _s2_hit_way_T_6) reg s2_bankid : UInt<1>, clock connect s2_bankid, s1_bankid node _s2_way_mux_T = mux(s2_tag_hit[0], s2_dout[0], UInt<1>(0h0)) node _s2_way_mux_T_1 = mux(s2_tag_hit[1], s2_dout[1], UInt<1>(0h0)) node _s2_way_mux_T_2 = mux(s2_tag_hit[2], s2_dout[2], UInt<1>(0h0)) node _s2_way_mux_T_3 = mux(s2_tag_hit[3], s2_dout[3], UInt<1>(0h0)) node _s2_way_mux_T_4 = mux(s2_tag_hit[4], s2_dout[4], UInt<1>(0h0)) node _s2_way_mux_T_5 = mux(s2_tag_hit[5], s2_dout[5], UInt<1>(0h0)) node _s2_way_mux_T_6 = mux(s2_tag_hit[6], s2_dout[6], UInt<1>(0h0)) node _s2_way_mux_T_7 = mux(s2_tag_hit[7], s2_dout[7], UInt<1>(0h0)) node _s2_way_mux_T_8 = or(_s2_way_mux_T, _s2_way_mux_T_1) node _s2_way_mux_T_9 = or(_s2_way_mux_T_8, _s2_way_mux_T_2) node _s2_way_mux_T_10 = or(_s2_way_mux_T_9, _s2_way_mux_T_3) node _s2_way_mux_T_11 = or(_s2_way_mux_T_10, _s2_way_mux_T_4) node _s2_way_mux_T_12 = or(_s2_way_mux_T_11, _s2_way_mux_T_5) node _s2_way_mux_T_13 = or(_s2_way_mux_T_12, _s2_way_mux_T_6) node _s2_way_mux_T_14 = or(_s2_way_mux_T_13, _s2_way_mux_T_7) wire s2_way_mux : UInt<128> connect s2_way_mux, _s2_way_mux_T_14 node s2_bank0_data = bits(s2_way_mux, 63, 0) node s2_bank1_data = bits(s2_way_mux, 127, 64) node _s2_data_T = cat(s2_bank0_data, s2_bank1_data) node _s2_data_T_1 = cat(s2_bank1_data, s2_bank0_data) node s2_data = mux(s2_bankid, _s2_data_T, _s2_data_T_1) invalidate io.resp.bits.ae invalidate io.resp.bits.replay connect io.resp.bits.data, s2_data node _io_resp_valid_T = and(s2_valid, s2_hit) connect io.resp.valid, _io_resp_valid_T node _masterNodeOut_a_valid_T = eq(refill_valid, UInt<1>(0h0)) node _masterNodeOut_a_valid_T_1 = and(s2_miss, _masterNodeOut_a_valid_T) node _masterNodeOut_a_valid_T_2 = eq(io.s2_kill, UInt<1>(0h0)) node _masterNodeOut_a_valid_T_3 = and(_masterNodeOut_a_valid_T_1, _masterNodeOut_a_valid_T_2) connect masterNodeOut.a.valid, _masterNodeOut_a_valid_T_3 node _masterNodeOut_a_bits_T = shr(refill_paddr, 6) node _masterNodeOut_a_bits_T_1 = shl(_masterNodeOut_a_bits_T, 6) node _masterNodeOut_a_bits_legal_T = leq(UInt<1>(0h0), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_1 = leq(UInt<3>(0h6), UInt<4>(0hc)) node _masterNodeOut_a_bits_legal_T_2 = and(_masterNodeOut_a_bits_legal_T, _masterNodeOut_a_bits_legal_T_1) node _masterNodeOut_a_bits_legal_T_3 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_2) node _masterNodeOut_a_bits_legal_T_4 = xor(_masterNodeOut_a_bits_T_1, UInt<14>(0h3000)) node _masterNodeOut_a_bits_legal_T_5 = cvt(_masterNodeOut_a_bits_legal_T_4) node _masterNodeOut_a_bits_legal_T_6 = and(_masterNodeOut_a_bits_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _masterNodeOut_a_bits_legal_T_7 = asSInt(_masterNodeOut_a_bits_legal_T_6) node _masterNodeOut_a_bits_legal_T_8 = eq(_masterNodeOut_a_bits_legal_T_7, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_9 = and(_masterNodeOut_a_bits_legal_T_3, _masterNodeOut_a_bits_legal_T_8) node _masterNodeOut_a_bits_legal_T_10 = leq(UInt<1>(0h0), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_11 = leq(UInt<3>(0h6), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_12 = and(_masterNodeOut_a_bits_legal_T_10, _masterNodeOut_a_bits_legal_T_11) node _masterNodeOut_a_bits_legal_T_13 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_12) node _masterNodeOut_a_bits_legal_T_14 = xor(_masterNodeOut_a_bits_T_1, UInt<1>(0h0)) node _masterNodeOut_a_bits_legal_T_15 = cvt(_masterNodeOut_a_bits_legal_T_14) node _masterNodeOut_a_bits_legal_T_16 = and(_masterNodeOut_a_bits_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _masterNodeOut_a_bits_legal_T_17 = asSInt(_masterNodeOut_a_bits_legal_T_16) node _masterNodeOut_a_bits_legal_T_18 = eq(_masterNodeOut_a_bits_legal_T_17, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_19 = xor(_masterNodeOut_a_bits_T_1, UInt<17>(0h10000)) node _masterNodeOut_a_bits_legal_T_20 = cvt(_masterNodeOut_a_bits_legal_T_19) node _masterNodeOut_a_bits_legal_T_21 = and(_masterNodeOut_a_bits_legal_T_20, asSInt(UInt<33>(0h98013000))) node _masterNodeOut_a_bits_legal_T_22 = asSInt(_masterNodeOut_a_bits_legal_T_21) node _masterNodeOut_a_bits_legal_T_23 = eq(_masterNodeOut_a_bits_legal_T_22, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_24 = xor(_masterNodeOut_a_bits_T_1, UInt<17>(0h10000)) node _masterNodeOut_a_bits_legal_T_25 = cvt(_masterNodeOut_a_bits_legal_T_24) node _masterNodeOut_a_bits_legal_T_26 = and(_masterNodeOut_a_bits_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _masterNodeOut_a_bits_legal_T_27 = asSInt(_masterNodeOut_a_bits_legal_T_26) node _masterNodeOut_a_bits_legal_T_28 = eq(_masterNodeOut_a_bits_legal_T_27, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_29 = xor(_masterNodeOut_a_bits_T_1, UInt<26>(0h2000000)) node _masterNodeOut_a_bits_legal_T_30 = cvt(_masterNodeOut_a_bits_legal_T_29) node _masterNodeOut_a_bits_legal_T_31 = and(_masterNodeOut_a_bits_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _masterNodeOut_a_bits_legal_T_32 = asSInt(_masterNodeOut_a_bits_legal_T_31) node _masterNodeOut_a_bits_legal_T_33 = eq(_masterNodeOut_a_bits_legal_T_32, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_34 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0h8000000)) node _masterNodeOut_a_bits_legal_T_35 = cvt(_masterNodeOut_a_bits_legal_T_34) node _masterNodeOut_a_bits_legal_T_36 = and(_masterNodeOut_a_bits_legal_T_35, asSInt(UInt<33>(0h98000000))) node _masterNodeOut_a_bits_legal_T_37 = asSInt(_masterNodeOut_a_bits_legal_T_36) node _masterNodeOut_a_bits_legal_T_38 = eq(_masterNodeOut_a_bits_legal_T_37, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_39 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0h8000000)) node _masterNodeOut_a_bits_legal_T_40 = cvt(_masterNodeOut_a_bits_legal_T_39) node _masterNodeOut_a_bits_legal_T_41 = and(_masterNodeOut_a_bits_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _masterNodeOut_a_bits_legal_T_42 = asSInt(_masterNodeOut_a_bits_legal_T_41) node _masterNodeOut_a_bits_legal_T_43 = eq(_masterNodeOut_a_bits_legal_T_42, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_44 = xor(_masterNodeOut_a_bits_T_1, UInt<29>(0h10000000)) node _masterNodeOut_a_bits_legal_T_45 = cvt(_masterNodeOut_a_bits_legal_T_44) node _masterNodeOut_a_bits_legal_T_46 = and(_masterNodeOut_a_bits_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _masterNodeOut_a_bits_legal_T_47 = asSInt(_masterNodeOut_a_bits_legal_T_46) node _masterNodeOut_a_bits_legal_T_48 = eq(_masterNodeOut_a_bits_legal_T_47, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_49 = xor(_masterNodeOut_a_bits_T_1, UInt<32>(0h80000000)) node _masterNodeOut_a_bits_legal_T_50 = cvt(_masterNodeOut_a_bits_legal_T_49) node _masterNodeOut_a_bits_legal_T_51 = and(_masterNodeOut_a_bits_legal_T_50, asSInt(UInt<33>(0h90000000))) node _masterNodeOut_a_bits_legal_T_52 = asSInt(_masterNodeOut_a_bits_legal_T_51) node _masterNodeOut_a_bits_legal_T_53 = eq(_masterNodeOut_a_bits_legal_T_52, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_54 = or(_masterNodeOut_a_bits_legal_T_18, _masterNodeOut_a_bits_legal_T_23) node _masterNodeOut_a_bits_legal_T_55 = or(_masterNodeOut_a_bits_legal_T_54, _masterNodeOut_a_bits_legal_T_28) node _masterNodeOut_a_bits_legal_T_56 = or(_masterNodeOut_a_bits_legal_T_55, _masterNodeOut_a_bits_legal_T_33) node _masterNodeOut_a_bits_legal_T_57 = or(_masterNodeOut_a_bits_legal_T_56, _masterNodeOut_a_bits_legal_T_38) node _masterNodeOut_a_bits_legal_T_58 = or(_masterNodeOut_a_bits_legal_T_57, _masterNodeOut_a_bits_legal_T_43) node _masterNodeOut_a_bits_legal_T_59 = or(_masterNodeOut_a_bits_legal_T_58, _masterNodeOut_a_bits_legal_T_48) node _masterNodeOut_a_bits_legal_T_60 = or(_masterNodeOut_a_bits_legal_T_59, _masterNodeOut_a_bits_legal_T_53) node _masterNodeOut_a_bits_legal_T_61 = and(_masterNodeOut_a_bits_legal_T_13, _masterNodeOut_a_bits_legal_T_60) node _masterNodeOut_a_bits_legal_T_62 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_9) node masterNodeOut_a_bits_legal = or(_masterNodeOut_a_bits_legal_T_62, _masterNodeOut_a_bits_legal_T_61) wire masterNodeOut_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect masterNodeOut_a_bits_a.opcode, UInt<3>(0h4) connect masterNodeOut_a_bits_a.param, UInt<1>(0h0) connect masterNodeOut_a_bits_a.size, UInt<3>(0h6) connect masterNodeOut_a_bits_a.source, UInt<1>(0h0) connect masterNodeOut_a_bits_a.address, _masterNodeOut_a_bits_T_1 node _masterNodeOut_a_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<4>(0h0)) node masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T, 1, 0) node _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount) node _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T_1, 3, 0) node masterNodeOut_a_bits_a_mask_sizeOH = or(_masterNodeOut_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node masterNodeOut_a_bits_a_mask_sub_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<3>(0h4)) node masterNodeOut_a_bits_a_mask_sub_sub_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 3, 3) node masterNodeOut_a_bits_a_mask_sub_sub_sub_bit = bits(_masterNodeOut_a_bits_T_1, 3, 3) node masterNodeOut_a_bits_a_mask_sub_sub_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_sub_0_2) node masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T) node masterNodeOut_a_bits_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_sub_1_2) node masterNodeOut_a_bits_a_mask_sub_sub_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T_1) node masterNodeOut_a_bits_a_mask_sub_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 2, 2) node masterNodeOut_a_bits_a_mask_sub_sub_bit = bits(_masterNodeOut_a_bits_T_1, 2, 2) node masterNodeOut_a_bits_a_mask_sub_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_sub_sub_0_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_0_2) node masterNodeOut_a_bits_a_mask_sub_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T) node masterNodeOut_a_bits_a_mask_sub_sub_1_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_1_2) node masterNodeOut_a_bits_a_mask_sub_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1) node masterNodeOut_a_bits_a_mask_sub_sub_2_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_2_2) node masterNodeOut_a_bits_a_mask_sub_sub_2_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_2) node masterNodeOut_a_bits_a_mask_sub_sub_3_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_3 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_3_2) node masterNodeOut_a_bits_a_mask_sub_sub_3_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_3) node masterNodeOut_a_bits_a_mask_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 1, 1) node masterNodeOut_a_bits_a_mask_sub_bit = bits(_masterNodeOut_a_bits_T_1, 1, 1) node masterNodeOut_a_bits_a_mask_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_sub_0_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_0_2) node masterNodeOut_a_bits_a_mask_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T) node masterNodeOut_a_bits_a_mask_sub_1_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_1_2) node masterNodeOut_a_bits_a_mask_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_1) node masterNodeOut_a_bits_a_mask_sub_2_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_2_2) node masterNodeOut_a_bits_a_mask_sub_2_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_2) node masterNodeOut_a_bits_a_mask_sub_3_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_3_2) node masterNodeOut_a_bits_a_mask_sub_3_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_3) node masterNodeOut_a_bits_a_mask_sub_4_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_2_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_4 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_4_2) node masterNodeOut_a_bits_a_mask_sub_4_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_2_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_4) node masterNodeOut_a_bits_a_mask_sub_5_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_2_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_5 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_5_2) node masterNodeOut_a_bits_a_mask_sub_5_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_2_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_5) node masterNodeOut_a_bits_a_mask_sub_6_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_3_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_6 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_6_2) node masterNodeOut_a_bits_a_mask_sub_6_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_3_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_6) node masterNodeOut_a_bits_a_mask_sub_7_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_3_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_7 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_7_2) node masterNodeOut_a_bits_a_mask_sub_7_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_3_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_7) node masterNodeOut_a_bits_a_mask_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 0, 0) node masterNodeOut_a_bits_a_mask_bit = bits(_masterNodeOut_a_bits_T_1, 0, 0) node masterNodeOut_a_bits_a_mask_nbit = eq(masterNodeOut_a_bits_a_mask_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_eq = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq) node masterNodeOut_a_bits_a_mask_acc = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T) node masterNodeOut_a_bits_a_mask_eq_1 = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_1 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_1) node masterNodeOut_a_bits_a_mask_acc_1 = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T_1) node masterNodeOut_a_bits_a_mask_eq_2 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_2 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_2) node masterNodeOut_a_bits_a_mask_acc_2 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_2) node masterNodeOut_a_bits_a_mask_eq_3 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_3 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_3) node masterNodeOut_a_bits_a_mask_acc_3 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_3) node masterNodeOut_a_bits_a_mask_eq_4 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_4 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_4) node masterNodeOut_a_bits_a_mask_acc_4 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_4) node masterNodeOut_a_bits_a_mask_eq_5 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_5 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_5) node masterNodeOut_a_bits_a_mask_acc_5 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_5) node masterNodeOut_a_bits_a_mask_eq_6 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_6 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_6) node masterNodeOut_a_bits_a_mask_acc_6 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_6) node masterNodeOut_a_bits_a_mask_eq_7 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_7 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_7) node masterNodeOut_a_bits_a_mask_acc_7 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_7) node masterNodeOut_a_bits_a_mask_eq_8 = and(masterNodeOut_a_bits_a_mask_sub_4_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_8 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_8) node masterNodeOut_a_bits_a_mask_acc_8 = or(masterNodeOut_a_bits_a_mask_sub_4_1, _masterNodeOut_a_bits_a_mask_acc_T_8) node masterNodeOut_a_bits_a_mask_eq_9 = and(masterNodeOut_a_bits_a_mask_sub_4_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_9 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_9) node masterNodeOut_a_bits_a_mask_acc_9 = or(masterNodeOut_a_bits_a_mask_sub_4_1, _masterNodeOut_a_bits_a_mask_acc_T_9) node masterNodeOut_a_bits_a_mask_eq_10 = and(masterNodeOut_a_bits_a_mask_sub_5_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_10 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_10) node masterNodeOut_a_bits_a_mask_acc_10 = or(masterNodeOut_a_bits_a_mask_sub_5_1, _masterNodeOut_a_bits_a_mask_acc_T_10) node masterNodeOut_a_bits_a_mask_eq_11 = and(masterNodeOut_a_bits_a_mask_sub_5_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_11 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_11) node masterNodeOut_a_bits_a_mask_acc_11 = or(masterNodeOut_a_bits_a_mask_sub_5_1, _masterNodeOut_a_bits_a_mask_acc_T_11) node masterNodeOut_a_bits_a_mask_eq_12 = and(masterNodeOut_a_bits_a_mask_sub_6_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_12 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_12) node masterNodeOut_a_bits_a_mask_acc_12 = or(masterNodeOut_a_bits_a_mask_sub_6_1, _masterNodeOut_a_bits_a_mask_acc_T_12) node masterNodeOut_a_bits_a_mask_eq_13 = and(masterNodeOut_a_bits_a_mask_sub_6_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_13 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_13) node masterNodeOut_a_bits_a_mask_acc_13 = or(masterNodeOut_a_bits_a_mask_sub_6_1, _masterNodeOut_a_bits_a_mask_acc_T_13) node masterNodeOut_a_bits_a_mask_eq_14 = and(masterNodeOut_a_bits_a_mask_sub_7_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_14 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_14) node masterNodeOut_a_bits_a_mask_acc_14 = or(masterNodeOut_a_bits_a_mask_sub_7_1, _masterNodeOut_a_bits_a_mask_acc_T_14) node masterNodeOut_a_bits_a_mask_eq_15 = and(masterNodeOut_a_bits_a_mask_sub_7_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_15 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_15) node masterNodeOut_a_bits_a_mask_acc_15 = or(masterNodeOut_a_bits_a_mask_sub_7_1, _masterNodeOut_a_bits_a_mask_acc_T_15) node masterNodeOut_a_bits_a_mask_lo_lo_lo = cat(masterNodeOut_a_bits_a_mask_acc_1, masterNodeOut_a_bits_a_mask_acc) node masterNodeOut_a_bits_a_mask_lo_lo_hi = cat(masterNodeOut_a_bits_a_mask_acc_3, masterNodeOut_a_bits_a_mask_acc_2) node masterNodeOut_a_bits_a_mask_lo_lo = cat(masterNodeOut_a_bits_a_mask_lo_lo_hi, masterNodeOut_a_bits_a_mask_lo_lo_lo) node masterNodeOut_a_bits_a_mask_lo_hi_lo = cat(masterNodeOut_a_bits_a_mask_acc_5, masterNodeOut_a_bits_a_mask_acc_4) node masterNodeOut_a_bits_a_mask_lo_hi_hi = cat(masterNodeOut_a_bits_a_mask_acc_7, masterNodeOut_a_bits_a_mask_acc_6) node masterNodeOut_a_bits_a_mask_lo_hi = cat(masterNodeOut_a_bits_a_mask_lo_hi_hi, masterNodeOut_a_bits_a_mask_lo_hi_lo) node masterNodeOut_a_bits_a_mask_lo = cat(masterNodeOut_a_bits_a_mask_lo_hi, masterNodeOut_a_bits_a_mask_lo_lo) node masterNodeOut_a_bits_a_mask_hi_lo_lo = cat(masterNodeOut_a_bits_a_mask_acc_9, masterNodeOut_a_bits_a_mask_acc_8) node masterNodeOut_a_bits_a_mask_hi_lo_hi = cat(masterNodeOut_a_bits_a_mask_acc_11, masterNodeOut_a_bits_a_mask_acc_10) node masterNodeOut_a_bits_a_mask_hi_lo = cat(masterNodeOut_a_bits_a_mask_hi_lo_hi, masterNodeOut_a_bits_a_mask_hi_lo_lo) node masterNodeOut_a_bits_a_mask_hi_hi_lo = cat(masterNodeOut_a_bits_a_mask_acc_13, masterNodeOut_a_bits_a_mask_acc_12) node masterNodeOut_a_bits_a_mask_hi_hi_hi = cat(masterNodeOut_a_bits_a_mask_acc_15, masterNodeOut_a_bits_a_mask_acc_14) node masterNodeOut_a_bits_a_mask_hi_hi = cat(masterNodeOut_a_bits_a_mask_hi_hi_hi, masterNodeOut_a_bits_a_mask_hi_hi_lo) node masterNodeOut_a_bits_a_mask_hi = cat(masterNodeOut_a_bits_a_mask_hi_hi, masterNodeOut_a_bits_a_mask_hi_lo) node _masterNodeOut_a_bits_a_mask_T = cat(masterNodeOut_a_bits_a_mask_hi, masterNodeOut_a_bits_a_mask_lo) connect masterNodeOut_a_bits_a.mask, _masterNodeOut_a_bits_a_mask_T invalidate masterNodeOut_a_bits_a.data connect masterNodeOut_a_bits_a.corrupt, UInt<1>(0h0) connect masterNodeOut.a.bits, masterNodeOut_a_bits_a wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits.corrupt, UInt<1>(0h0) connect _WIRE_1.bits.data, UInt<128>(0h0) connect _WIRE_1.bits.mask, UInt<16>(0h0) connect _WIRE_1.bits.address, UInt<32>(0h0) connect _WIRE_1.bits.source, UInt<1>(0h0) connect _WIRE_1.bits.size, UInt<4>(0h0) connect _WIRE_1.bits.param, UInt<2>(0h0) connect _WIRE_1.bits.opcode, UInt<3>(0h0) connect _WIRE_1.valid, UInt<1>(0h0) connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits, _WIRE_1.bits connect _WIRE_2.valid, _WIRE_1.valid connect _WIRE_2.ready, _WIRE_1.ready connect _WIRE_2.ready, UInt<1>(0h1) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits.corrupt, UInt<1>(0h0) connect _WIRE_3.bits.data, UInt<128>(0h0) connect _WIRE_3.bits.address, UInt<32>(0h0) connect _WIRE_3.bits.source, UInt<1>(0h0) connect _WIRE_3.bits.size, UInt<4>(0h0) connect _WIRE_3.bits.param, UInt<3>(0h0) connect _WIRE_3.bits.opcode, UInt<3>(0h0) connect _WIRE_3.valid, UInt<1>(0h0) connect _WIRE_3.ready, UInt<1>(0h0) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_4.bits, _WIRE_3.bits connect _WIRE_4.valid, _WIRE_3.valid connect _WIRE_4.ready, _WIRE_3.ready connect _WIRE_4.valid, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits.sink, UInt<4>(0h0) connect _WIRE_5.valid, UInt<1>(0h0) connect _WIRE_5.ready, UInt<1>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_6.bits, _WIRE_5.bits connect _WIRE_6.valid, _WIRE_5.valid connect _WIRE_6.ready, _WIRE_5.ready connect _WIRE_6.valid, UInt<1>(0h0) node _io_perf_acquire_T = and(masterNodeOut.a.ready, masterNodeOut.a.valid) connect io.perf.acquire, _io_perf_acquire_T node _T_133 = eq(refill_valid, UInt<1>(0h0)) when _T_133 : connect invalidated, UInt<1>(0h0) when refill_fire : connect refill_valid, UInt<1>(0h1) when refill_done : connect refill_valid, UInt<1>(0h0)
module ICache_3( // @[icache.scala:103:7] input clock, // @[icache.scala:103:7] input reset, // @[icache.scala:103:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_req_valid, // @[icache.scala:107:14] input [38:0] io_req_bits_addr, // @[icache.scala:107:14] input [31:0] io_s1_paddr, // @[icache.scala:107:14] input io_s1_kill, // @[icache.scala:107:14] input io_s2_kill, // @[icache.scala:107:14] output io_resp_valid, // @[icache.scala:107:14] output [127:0] io_resp_bits_data, // @[icache.scala:107:14] input io_invalidate, // @[icache.scala:107:14] output io_perf_acquire // @[icache.scala:107:14] ); wire tag_array_MPORT_mask_7; // @[icache.scala:156:100] wire tag_array_MPORT_mask_6; // @[icache.scala:156:100] wire tag_array_MPORT_mask_5; // @[icache.scala:156:100] wire tag_array_MPORT_mask_4; // @[icache.scala:156:100] wire tag_array_MPORT_mask_3; // @[icache.scala:156:100] wire tag_array_MPORT_mask_2; // @[icache.scala:156:100] wire tag_array_MPORT_mask_1; // @[icache.scala:156:100] wire tag_array_MPORT_mask_0; // @[icache.scala:156:100] wire [63:0] _dataArrayB1Way_7_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB1Way_6_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB1Way_5_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB1Way_4_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB1Way_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB1Way_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB1Way_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB1Way_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB0Way_7_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB0Way_6_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB0Way_5_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB0Way_4_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB0Way_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB0Way_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB0Way_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _dataArrayB0Way_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [159:0] _tag_array_RW0_rdata; // @[icache.scala:153:30] wire _repl_way_prng_io_out_0; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_1; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_2; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_3; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_4; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_5; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_6; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_7; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_8; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_9; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_10; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_11; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_12; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_13; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_14; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_15; // @[PRNG.scala:91:22] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[icache.scala:103:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[icache.scala:103:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[icache.scala:103:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[icache.scala:103:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[icache.scala:103:7] wire [3:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[icache.scala:103:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[icache.scala:103:7] wire [127:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[icache.scala:103:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[icache.scala:103:7] wire io_req_valid_0 = io_req_valid; // @[icache.scala:103:7] wire [38:0] io_req_bits_addr_0 = io_req_bits_addr; // @[icache.scala:103:7] wire [31:0] io_s1_paddr_0 = io_s1_paddr; // @[icache.scala:103:7] wire io_s1_kill_0 = io_s1_kill; // @[icache.scala:103:7] wire io_s2_kill_0 = io_s2_kill; // @[icache.scala:103:7] wire io_invalidate_0 = io_invalidate; // @[icache.scala:103:7] wire [2:0] auto_master_out_a_bits_opcode = 3'h4; // @[icache.scala:103:7] wire [2:0] masterNodeOut_a_bits_opcode = 3'h4; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_a_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] auto_master_out_a_bits_param = 3'h0; // @[icache.scala:103:7] wire [2:0] masterNodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_a_param = 3'h0; // @[Edges.scala:460:17] wire [3:0] auto_master_out_a_bits_size = 4'h6; // @[icache.scala:103:7] wire [3:0] masterNodeOut_a_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_a_size = 4'h6; // @[Edges.scala:460:17] wire [3:0] _masterNodeOut_a_bits_a_mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire auto_master_out_a_bits_source = 1'h0; // @[icache.scala:103:7] wire auto_master_out_a_bits_corrupt = 1'h0; // @[icache.scala:103:7] wire auto_master_out_d_bits_source = 1'h0; // @[icache.scala:103:7] wire io_resp_bits_replay = 1'h0; // @[icache.scala:103:7] wire io_resp_bits_ae = 1'h0; // @[icache.scala:103:7] wire masterNodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_a_source = 1'h0; // @[Edges.scala:460:17] wire masterNodeOut_a_bits_a_corrupt = 1'h0; // @[Edges.scala:460:17] wire masterNodeOut_a_bits_a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire masterNodeOut_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _masterNodeOut_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire [15:0] auto_master_out_a_bits_mask = 16'hFFFF; // @[icache.scala:103:7] wire [15:0] masterNodeOut_a_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] masterNodeOut_a_bits_a_mask = 16'hFFFF; // @[Edges.scala:460:17] wire [15:0] _masterNodeOut_a_bits_a_mask_T = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] auto_master_out_a_bits_data = 128'h0; // @[icache.scala:103:7] wire [127:0] masterNodeOut_a_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] masterNodeOut_a_bits_a_data = 128'h0; // @[Edges.scala:460:17] wire auto_master_out_d_ready = 1'h1; // @[icache.scala:103:7] wire masterNodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire _masterNodeOut_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _masterNodeOut_a_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _masterNodeOut_a_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _masterNodeOut_a_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _masterNodeOut_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _masterNodeOut_a_bits_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _masterNodeOut_a_bits_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _masterNodeOut_a_bits_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire masterNodeOut_a_bits_a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire masterNodeOut_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire masterNodeOut_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire [7:0] masterNodeOut_a_bits_a_mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] masterNodeOut_a_bits_a_mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [3:0] _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [1:0] masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [127:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire _io_req_ready_T; // @[icache.scala:144:19] wire _io_resp_valid_T; // @[icache.scala:324:29] wire [127:0] s2_data; // @[icache.scala:314:10] wire _io_perf_acquire_T; // @[Decoupled.scala:51:35] wire [31:0] auto_master_out_a_bits_address_0; // @[icache.scala:103:7] wire auto_master_out_a_valid_0; // @[icache.scala:103:7] wire io_req_ready; // @[icache.scala:103:7] wire [127:0] io_resp_bits_data_0; // @[icache.scala:103:7] wire io_resp_valid_0; // @[icache.scala:103:7] wire io_perf_acquire_0; // @[icache.scala:103:7] wire _masterNodeOut_a_valid_T_3; // @[icache.scala:326:46] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_a_address; // @[Edges.scala:460:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire _refill_one_beat_T = masterNodeOut_d_valid; // @[Decoupled.scala:51:35] wire s0_valid = io_req_ready & io_req_valid_0; // @[Decoupled.scala:51:35] reg s1_valid; // @[icache.scala:128:25] wire _s1_tag_hit_0_T_1; // @[icache.scala:177:28] wire _s1_tag_hit_1_T_1; // @[icache.scala:177:28] wire _s1_tag_hit_2_T_1; // @[icache.scala:177:28] wire _s1_tag_hit_3_T_1; // @[icache.scala:177:28] wire _s1_tag_hit_4_T_1; // @[icache.scala:177:28] wire _s1_tag_hit_5_T_1; // @[icache.scala:177:28] wire _s1_tag_hit_6_T_1; // @[icache.scala:177:28] wire _s1_tag_hit_7_T_1; // @[icache.scala:177:28] wire s1_tag_hit_0; // @[icache.scala:129:24] wire s1_tag_hit_1; // @[icache.scala:129:24] wire s1_tag_hit_2; // @[icache.scala:129:24] wire s1_tag_hit_3; // @[icache.scala:129:24] wire s1_tag_hit_4; // @[icache.scala:129:24] wire s1_tag_hit_5; // @[icache.scala:129:24] wire s1_tag_hit_6; // @[icache.scala:129:24] wire s1_tag_hit_7; // @[icache.scala:129:24] wire _s1_hit_T = s1_tag_hit_0 | s1_tag_hit_1; // @[icache.scala:129:24, :130:35] wire _s1_hit_T_1 = _s1_hit_T | s1_tag_hit_2; // @[icache.scala:129:24, :130:35] wire _s1_hit_T_2 = _s1_hit_T_1 | s1_tag_hit_3; // @[icache.scala:129:24, :130:35] wire _s1_hit_T_3 = _s1_hit_T_2 | s1_tag_hit_4; // @[icache.scala:129:24, :130:35] wire _s1_hit_T_4 = _s1_hit_T_3 | s1_tag_hit_5; // @[icache.scala:129:24, :130:35] wire _s1_hit_T_5 = _s1_hit_T_4 | s1_tag_hit_6; // @[icache.scala:129:24, :130:35] wire s1_hit = _s1_hit_T_5 | s1_tag_hit_7; // @[icache.scala:129:24, :130:35] wire _s2_valid_T = ~io_s1_kill_0; // @[icache.scala:103:7, :131:38] wire _s2_valid_T_1 = s1_valid & _s2_valid_T; // @[icache.scala:128:25, :131:{35,38}] reg s2_valid; // @[icache.scala:131:25] reg s2_hit; // @[icache.scala:132:23] reg invalidated; // @[icache.scala:135:24] reg refill_valid; // @[icache.scala:136:29] wire _GEN = masterNodeOut_a_ready & masterNodeOut_a_valid; // @[Decoupled.scala:51:35] wire refill_fire; // @[Decoupled.scala:51:35] assign refill_fire = _GEN; // @[Decoupled.scala:51:35] assign _io_perf_acquire_T = _GEN; // @[Decoupled.scala:51:35] wire _s2_miss_T = ~s2_hit; // @[icache.scala:132:23, :138:29] wire _s2_miss_T_1 = s2_valid & _s2_miss_T; // @[icache.scala:131:25, :138:{26,29}] reg s2_miss_REG; // @[icache.scala:138:48] wire _s2_miss_T_2 = ~s2_miss_REG; // @[icache.scala:138:{40,48}] wire s2_miss = _s2_miss_T_1 & _s2_miss_T_2; // @[icache.scala:138:{26,37,40}] wire _refill_paddr_T = refill_valid | s2_miss; // @[icache.scala:136:29, :138:37, :139:72] wire _refill_paddr_T_1 = ~_refill_paddr_T; // @[icache.scala:139:{57,72}] wire _refill_paddr_T_2 = s1_valid & _refill_paddr_T_1; // @[icache.scala:128:25, :139:{54,57}] reg [31:0] refill_paddr; // @[icache.scala:139:31] wire [19:0] refill_tag = refill_paddr[31:12]; // @[icache.scala:139:31, :140:32] wire [5:0] refill_idx = refill_paddr[11:6]; // @[icache.scala:139:31, :141:32] wire refill_one_beat_opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire r_beats1_opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire refill_one_beat = _refill_one_beat_T & refill_one_beat_opdata; // @[Decoupled.scala:51:35] assign _io_req_ready_T = ~refill_one_beat; // @[icache.scala:142:39, :144:19] assign io_req_ready = _io_req_ready_T; // @[icache.scala:103:7, :144:19] wire [26:0] _r_beats1_decode_T = 27'hFFF << masterNodeOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode = _r_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire [7:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] r_counter; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28] wire r_1 = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_done = r_2 & masterNodeOut_d_valid; // @[Edges.scala:232:33, :233:22] wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] refill_cnt = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T = r_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire refill_done = refill_one_beat & d_done; // @[Edges.scala:233:22] wire [1:0] repl_way_lo_lo_lo = {_repl_way_prng_io_out_1, _repl_way_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_lo_lo_hi = {_repl_way_prng_io_out_3, _repl_way_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_lo_lo = {repl_way_lo_lo_hi, repl_way_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] repl_way_lo_hi_lo = {_repl_way_prng_io_out_5, _repl_way_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_lo_hi_hi = {_repl_way_prng_io_out_7, _repl_way_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_lo_hi = {repl_way_lo_hi_hi, repl_way_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] repl_way_lo = {repl_way_lo_hi, repl_way_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] repl_way_hi_lo_lo = {_repl_way_prng_io_out_9, _repl_way_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_hi_lo_hi = {_repl_way_prng_io_out_11, _repl_way_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_hi_lo = {repl_way_hi_lo_hi, repl_way_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] repl_way_hi_hi_lo = {_repl_way_prng_io_out_13, _repl_way_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_hi_hi_hi = {_repl_way_prng_io_out_15, _repl_way_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_hi_hi = {repl_way_hi_hi_hi, repl_way_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] repl_way_hi = {repl_way_hi_hi, repl_way_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] _repl_way_T = {repl_way_hi, repl_way_lo}; // @[PRNG.scala:95:17] wire [2:0] repl_way = _repl_way_T[2:0]; // @[PRNG.scala:95:17] wire [5:0] _tag_rdata_WIRE; // @[icache.scala:154:33] wire _tag_rdata_T_2; // @[icache.scala:154:84] wire [5:0] _tag_rdata_T = io_req_bits_addr_0[11:6]; // @[icache.scala:103:7, :154:42] assign _tag_rdata_WIRE = _tag_rdata_T; // @[icache.scala:154:{33,42}] wire _tag_rdata_T_1 = ~refill_done; // @[icache.scala:147:37, :154:71] assign _tag_rdata_T_2 = _tag_rdata_T_1 & s0_valid; // @[Decoupled.scala:51:35] assign tag_array_MPORT_mask_0 = ~(|repl_way); // @[icache.scala:151:58, :156:100] assign tag_array_MPORT_mask_1 = repl_way == 3'h1; // @[icache.scala:151:58, :156:100] assign tag_array_MPORT_mask_2 = repl_way == 3'h2; // @[icache.scala:151:58, :156:100] assign tag_array_MPORT_mask_3 = repl_way == 3'h3; // @[icache.scala:151:58, :156:100] assign tag_array_MPORT_mask_4 = repl_way == 3'h4; // @[icache.scala:151:58, :156:100] assign tag_array_MPORT_mask_5 = repl_way == 3'h5; // @[icache.scala:151:58, :156:100] assign tag_array_MPORT_mask_6 = repl_way == 3'h6; // @[icache.scala:151:58, :156:100] assign tag_array_MPORT_mask_7 = &repl_way; // @[icache.scala:151:58, :156:100] reg [511:0] vb_array; // @[icache.scala:159:25] wire [8:0] _vb_array_T = {repl_way, refill_idx}; // @[icache.scala:141:32, :151:58, :161:36] wire _vb_array_T_1 = ~invalidated; // @[icache.scala:135:24, :161:75] wire _vb_array_T_2 = refill_done & _vb_array_T_1; // @[icache.scala:147:37, :161:{72,75}] wire [511:0] _vb_array_T_3 = 512'h1 << _vb_array_T; // @[icache.scala:161:{32,36}] wire [511:0] _vb_array_T_4 = vb_array | _vb_array_T_3; // @[icache.scala:159:25, :161:32] wire [511:0] _vb_array_T_5 = ~vb_array; // @[icache.scala:159:25, :161:32] wire [511:0] _vb_array_T_6 = _vb_array_T_5 | _vb_array_T_3; // @[icache.scala:161:32] wire [511:0] _vb_array_T_7 = ~_vb_array_T_6; // @[icache.scala:161:32] wire [511:0] _vb_array_T_8 = _vb_array_T_2 ? _vb_array_T_4 : _vb_array_T_7; // @[icache.scala:161:{32,72}] wire [127:0] s2_dout_0; // @[icache.scala:169:23] wire [127:0] s2_dout_1; // @[icache.scala:169:23] wire [127:0] s2_dout_2; // @[icache.scala:169:23] wire [127:0] s2_dout_3; // @[icache.scala:169:23] wire [127:0] s2_dout_4; // @[icache.scala:169:23] wire [127:0] s2_dout_5; // @[icache.scala:169:23] wire [127:0] s2_dout_6; // @[icache.scala:169:23] wire [127:0] s2_dout_7; // @[icache.scala:169:23] wire s1_bankid; // @[icache.scala:170:23] wire [5:0] s1_idx = io_s1_paddr_0[11:6]; // @[icache.scala:103:7, :173:29] wire [5:0] s1_idx_1 = io_s1_paddr_0[11:6]; // @[icache.scala:103:7, :173:29] wire [5:0] s1_idx_2 = io_s1_paddr_0[11:6]; // @[icache.scala:103:7, :173:29] wire [5:0] s1_idx_3 = io_s1_paddr_0[11:6]; // @[icache.scala:103:7, :173:29] wire [5:0] s1_idx_4 = io_s1_paddr_0[11:6]; // @[icache.scala:103:7, :173:29] wire [5:0] s1_idx_5 = io_s1_paddr_0[11:6]; // @[icache.scala:103:7, :173:29] wire [5:0] s1_idx_6 = io_s1_paddr_0[11:6]; // @[icache.scala:103:7, :173:29] wire [5:0] s1_idx_7 = io_s1_paddr_0[11:6]; // @[icache.scala:103:7, :173:29] wire [19:0] s1_tag = io_s1_paddr_0[31:12]; // @[icache.scala:103:7, :174:29] wire [19:0] s1_tag_1 = io_s1_paddr_0[31:12]; // @[icache.scala:103:7, :174:29] wire [19:0] s1_tag_2 = io_s1_paddr_0[31:12]; // @[icache.scala:103:7, :174:29] wire [19:0] s1_tag_3 = io_s1_paddr_0[31:12]; // @[icache.scala:103:7, :174:29] wire [19:0] s1_tag_4 = io_s1_paddr_0[31:12]; // @[icache.scala:103:7, :174:29] wire [19:0] s1_tag_5 = io_s1_paddr_0[31:12]; // @[icache.scala:103:7, :174:29] wire [19:0] s1_tag_6 = io_s1_paddr_0[31:12]; // @[icache.scala:103:7, :174:29] wire [19:0] s1_tag_7 = io_s1_paddr_0[31:12]; // @[icache.scala:103:7, :174:29] wire [6:0] _s1_vb_T = {1'h0, s1_idx}; // @[icache.scala:173:29, :175:29] wire [511:0] _s1_vb_T_1 = vb_array >> _s1_vb_T; // @[icache.scala:159:25, :175:{25,29}] wire s1_vb = _s1_vb_T_1[0]; // @[icache.scala:175:25] wire _s1_tag_hit_0_T = _tag_array_RW0_rdata[19:0] == s1_tag; // @[icache.scala:153:30, :174:29, :177:35] assign _s1_tag_hit_0_T_1 = s1_vb & _s1_tag_hit_0_T; // @[icache.scala:175:25, :177:{28,35}] assign s1_tag_hit_0 = _s1_tag_hit_0_T_1; // @[icache.scala:129:24, :177:28] wire [6:0] _s1_vb_T_2 = {1'h1, s1_idx_1}; // @[icache.scala:173:29, :175:29] wire [511:0] _s1_vb_T_3 = vb_array >> _s1_vb_T_2; // @[icache.scala:159:25, :175:{25,29}] wire s1_vb_1 = _s1_vb_T_3[0]; // @[icache.scala:175:25] wire _s1_tag_hit_1_T = _tag_array_RW0_rdata[39:20] == s1_tag_1; // @[icache.scala:153:30, :174:29, :177:35] assign _s1_tag_hit_1_T_1 = s1_vb_1 & _s1_tag_hit_1_T; // @[icache.scala:175:25, :177:{28,35}] assign s1_tag_hit_1 = _s1_tag_hit_1_T_1; // @[icache.scala:129:24, :177:28] wire [7:0] _s1_vb_T_4 = {2'h2, s1_idx_2}; // @[icache.scala:173:29, :175:29] wire [511:0] _s1_vb_T_5 = vb_array >> _s1_vb_T_4; // @[icache.scala:159:25, :175:{25,29}] wire s1_vb_2 = _s1_vb_T_5[0]; // @[icache.scala:175:25] wire _s1_tag_hit_2_T = _tag_array_RW0_rdata[59:40] == s1_tag_2; // @[icache.scala:153:30, :174:29, :177:35] assign _s1_tag_hit_2_T_1 = s1_vb_2 & _s1_tag_hit_2_T; // @[icache.scala:175:25, :177:{28,35}] assign s1_tag_hit_2 = _s1_tag_hit_2_T_1; // @[icache.scala:129:24, :177:28] wire [7:0] _s1_vb_T_6 = {2'h3, s1_idx_3}; // @[icache.scala:173:29, :175:29] wire [511:0] _s1_vb_T_7 = vb_array >> _s1_vb_T_6; // @[icache.scala:159:25, :175:{25,29}] wire s1_vb_3 = _s1_vb_T_7[0]; // @[icache.scala:175:25] wire _s1_tag_hit_3_T = _tag_array_RW0_rdata[79:60] == s1_tag_3; // @[icache.scala:153:30, :174:29, :177:35] assign _s1_tag_hit_3_T_1 = s1_vb_3 & _s1_tag_hit_3_T; // @[icache.scala:175:25, :177:{28,35}] assign s1_tag_hit_3 = _s1_tag_hit_3_T_1; // @[icache.scala:129:24, :177:28] wire [8:0] _s1_vb_T_8 = {3'h4, s1_idx_4}; // @[icache.scala:173:29, :175:29] wire [511:0] _s1_vb_T_9 = vb_array >> _s1_vb_T_8; // @[icache.scala:159:25, :175:{25,29}] wire s1_vb_4 = _s1_vb_T_9[0]; // @[icache.scala:175:25] wire _s1_tag_hit_4_T = _tag_array_RW0_rdata[99:80] == s1_tag_4; // @[icache.scala:153:30, :174:29, :177:35] assign _s1_tag_hit_4_T_1 = s1_vb_4 & _s1_tag_hit_4_T; // @[icache.scala:175:25, :177:{28,35}] assign s1_tag_hit_4 = _s1_tag_hit_4_T_1; // @[icache.scala:129:24, :177:28] wire [8:0] _s1_vb_T_10 = {3'h5, s1_idx_5}; // @[icache.scala:173:29, :175:29] wire [511:0] _s1_vb_T_11 = vb_array >> _s1_vb_T_10; // @[icache.scala:159:25, :175:{25,29}] wire s1_vb_5 = _s1_vb_T_11[0]; // @[icache.scala:175:25] wire _s1_tag_hit_5_T = _tag_array_RW0_rdata[119:100] == s1_tag_5; // @[icache.scala:153:30, :174:29, :177:35] assign _s1_tag_hit_5_T_1 = s1_vb_5 & _s1_tag_hit_5_T; // @[icache.scala:175:25, :177:{28,35}] assign s1_tag_hit_5 = _s1_tag_hit_5_T_1; // @[icache.scala:129:24, :177:28] wire [8:0] _s1_vb_T_12 = {3'h6, s1_idx_6}; // @[icache.scala:173:29, :175:29] wire [511:0] _s1_vb_T_13 = vb_array >> _s1_vb_T_12; // @[icache.scala:159:25, :175:{25,29}] wire s1_vb_6 = _s1_vb_T_13[0]; // @[icache.scala:175:25] wire _s1_tag_hit_6_T = _tag_array_RW0_rdata[139:120] == s1_tag_6; // @[icache.scala:153:30, :174:29, :177:35] assign _s1_tag_hit_6_T_1 = s1_vb_6 & _s1_tag_hit_6_T; // @[icache.scala:175:25, :177:{28,35}] assign s1_tag_hit_6 = _s1_tag_hit_6_T_1; // @[icache.scala:129:24, :177:28] wire [8:0] _s1_vb_T_14 = {3'h7, s1_idx_7}; // @[icache.scala:173:29, :175:29] wire [511:0] _s1_vb_T_15 = vb_array >> _s1_vb_T_14; // @[icache.scala:159:25, :175:{25,29}] wire s1_vb_7 = _s1_vb_T_15[0]; // @[icache.scala:175:25] wire _s1_tag_hit_7_T = _tag_array_RW0_rdata[159:140] == s1_tag_7; // @[icache.scala:153:30, :174:29, :177:35] assign _s1_tag_hit_7_T_1 = s1_vb_7 & _s1_tag_hit_7_T; // @[icache.scala:175:25, :177:{28,35}] assign s1_tag_hit_7 = _s1_tag_hit_7_T_1; // @[icache.scala:129:24, :177:28]
Generate the Verilog code corresponding to this FIRRTL code module BeatMerger : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { shift : UInt<6>, addr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<8>, len : UInt<16>, block_stride : UInt<16>, spad_row_offset : UInt<9>, lg_len_req : UInt<3>, bytes_to_read : UInt<7>, cmd_id : UInt<1>}}, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<128>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<512>, addr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, mask : UInt<1>[64], last : UInt<1>}}} reg req : { valid : UInt<1>, bits : { shift : UInt<6>, addr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<8>, len : UInt<16>, block_stride : UInt<16>, spad_row_offset : UInt<9>, lg_len_req : UInt<3>, bytes_to_read : UInt<7>, cmd_id : UInt<1>}}, clock reg buffer : UInt<512>, clock node rowBytes = mux(req.bits.has_acc_bitwidth, UInt<7>(0h40), UInt<5>(0h10)) reg bytesSent : UInt<7>, clock reg bytesRead : UInt<7>, clock node _bytesReadAfterShift_T = gt(bytesRead, req.bits.shift) node _bytesReadAfterShift_T_1 = sub(bytesRead, req.bits.shift) node _bytesReadAfterShift_T_2 = tail(_bytesReadAfterShift_T_1, 1) node bytesReadAfterShift = mux(_bytesReadAfterShift_T, _bytesReadAfterShift_T_2, UInt<1>(0h0)) node _bytesDiscarded_T = sub(bytesRead, bytesReadAfterShift) node bytesDiscarded = tail(_bytesDiscarded_T, 1) node _usefulBytesRead_T = lt(bytesReadAfterShift, req.bits.bytes_to_read) node usefulBytesRead = mux(_usefulBytesRead_T, bytesReadAfterShift, req.bits.bytes_to_read) node _bytesSent_next_spad_row_offset_T = eq(bytesSent, UInt<1>(0h0)) node bytesSent_next_spad_row_offset = mux(_bytesSent_next_spad_row_offset_T, req.bits.spad_row_offset, UInt<1>(0h0)) node _bytesSent_next_T = sub(rowBytes, bytesSent_next_spad_row_offset) node _bytesSent_next_T_1 = tail(_bytesSent_next_T, 1) node _bytesSent_next_T_2 = add(bytesSent, _bytesSent_next_T_1) node _bytesSent_next_T_3 = gt(_bytesSent_next_T_2, req.bits.bytes_to_read) node _bytesSent_next_T_4 = add(bytesSent, _bytesSent_next_T_1) node _bytesSent_next_T_5 = tail(_bytesSent_next_T_4, 1) node bytesSent_next = mux(_bytesSent_next_T_3, req.bits.bytes_to_read, _bytesSent_next_T_5) node last_sending = eq(bytesSent_next, req.bits.bytes_to_read) node _last_reading_T = dshl(UInt<1>(0h1), req.bits.lg_len_req) node _last_reading_T_1 = sub(_last_reading_T, bytesRead) node _last_reading_T_2 = tail(_last_reading_T_1, 1) node last_reading = geq(UInt<5>(0h10), _last_reading_T_2) node _io_req_ready_T = eq(req.valid, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _io_in_ready_T = and(io.req.ready, io.req.valid) node _io_in_ready_T_1 = dshl(UInt<1>(0h1), req.bits.lg_len_req) node _io_in_ready_T_2 = neq(bytesRead, _io_in_ready_T_1) node _io_in_ready_T_3 = and(req.valid, _io_in_ready_T_2) node _io_in_ready_T_4 = or(_io_in_ready_T, _io_in_ready_T_3) connect io.in.ready, _io_in_ready_T_4 node _io_out_valid_T = gt(usefulBytesRead, bytesSent) node _io_out_valid_T_1 = and(req.valid, _io_out_valid_T) node _io_out_valid_T_2 = sub(usefulBytesRead, bytesSent) node _io_out_valid_T_3 = tail(_io_out_valid_T_2, 1) node _io_out_valid_T_4 = geq(_io_out_valid_T_3, rowBytes) node _io_out_valid_T_5 = eq(usefulBytesRead, req.bits.bytes_to_read) node _io_out_valid_T_6 = or(_io_out_valid_T_4, _io_out_valid_T_5) node _io_out_valid_T_7 = and(_io_out_valid_T_1, _io_out_valid_T_6) connect io.out.valid, _io_out_valid_T_7 node _io_out_bits_data_T = mul(bytesSent, UInt<4>(0h8)) node _io_out_bits_data_T_1 = dshr(buffer, _io_out_bits_data_T) node _io_out_bits_data_T_2 = eq(bytesSent, UInt<1>(0h0)) node _io_out_bits_data_T_3 = mul(req.bits.spad_row_offset, UInt<4>(0h8)) node _io_out_bits_data_T_4 = mux(_io_out_bits_data_T_2, _io_out_bits_data_T_3, UInt<1>(0h0)) node _io_out_bits_data_T_5 = dshl(_io_out_bits_data_T_1, _io_out_bits_data_T_4) connect io.out.bits.data, _io_out_bits_data_T_5 node _spad_row_offset_T = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset = mux(_spad_row_offset_T, req.bits.spad_row_offset, UInt<1>(0h0)) node _T = geq(UInt<1>(0h0), spad_row_offset) node _T_1 = sub(req.bits.bytes_to_read, bytesSent) node _T_2 = tail(_T_1, 1) node _T_3 = add(spad_row_offset, _T_2) node _T_4 = lt(UInt<1>(0h0), _T_3) node _T_5 = and(_T, _T_4) node _spad_row_offset_T_1 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_1 = mux(_spad_row_offset_T_1, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_6 = geq(UInt<1>(0h1), spad_row_offset_1) node _T_7 = sub(req.bits.bytes_to_read, bytesSent) node _T_8 = tail(_T_7, 1) node _T_9 = add(spad_row_offset_1, _T_8) node _T_10 = lt(UInt<1>(0h1), _T_9) node _T_11 = and(_T_6, _T_10) node _spad_row_offset_T_2 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_2 = mux(_spad_row_offset_T_2, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_12 = geq(UInt<2>(0h2), spad_row_offset_2) node _T_13 = sub(req.bits.bytes_to_read, bytesSent) node _T_14 = tail(_T_13, 1) node _T_15 = add(spad_row_offset_2, _T_14) node _T_16 = lt(UInt<2>(0h2), _T_15) node _T_17 = and(_T_12, _T_16) node _spad_row_offset_T_3 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_3 = mux(_spad_row_offset_T_3, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_18 = geq(UInt<2>(0h3), spad_row_offset_3) node _T_19 = sub(req.bits.bytes_to_read, bytesSent) node _T_20 = tail(_T_19, 1) node _T_21 = add(spad_row_offset_3, _T_20) node _T_22 = lt(UInt<2>(0h3), _T_21) node _T_23 = and(_T_18, _T_22) node _spad_row_offset_T_4 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_4 = mux(_spad_row_offset_T_4, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_24 = geq(UInt<3>(0h4), spad_row_offset_4) node _T_25 = sub(req.bits.bytes_to_read, bytesSent) node _T_26 = tail(_T_25, 1) node _T_27 = add(spad_row_offset_4, _T_26) node _T_28 = lt(UInt<3>(0h4), _T_27) node _T_29 = and(_T_24, _T_28) node _spad_row_offset_T_5 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_5 = mux(_spad_row_offset_T_5, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_30 = geq(UInt<3>(0h5), spad_row_offset_5) node _T_31 = sub(req.bits.bytes_to_read, bytesSent) node _T_32 = tail(_T_31, 1) node _T_33 = add(spad_row_offset_5, _T_32) node _T_34 = lt(UInt<3>(0h5), _T_33) node _T_35 = and(_T_30, _T_34) node _spad_row_offset_T_6 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_6 = mux(_spad_row_offset_T_6, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_36 = geq(UInt<3>(0h6), spad_row_offset_6) node _T_37 = sub(req.bits.bytes_to_read, bytesSent) node _T_38 = tail(_T_37, 1) node _T_39 = add(spad_row_offset_6, _T_38) node _T_40 = lt(UInt<3>(0h6), _T_39) node _T_41 = and(_T_36, _T_40) node _spad_row_offset_T_7 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_7 = mux(_spad_row_offset_T_7, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_42 = geq(UInt<3>(0h7), spad_row_offset_7) node _T_43 = sub(req.bits.bytes_to_read, bytesSent) node _T_44 = tail(_T_43, 1) node _T_45 = add(spad_row_offset_7, _T_44) node _T_46 = lt(UInt<3>(0h7), _T_45) node _T_47 = and(_T_42, _T_46) node _spad_row_offset_T_8 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_8 = mux(_spad_row_offset_T_8, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_48 = geq(UInt<4>(0h8), spad_row_offset_8) node _T_49 = sub(req.bits.bytes_to_read, bytesSent) node _T_50 = tail(_T_49, 1) node _T_51 = add(spad_row_offset_8, _T_50) node _T_52 = lt(UInt<4>(0h8), _T_51) node _T_53 = and(_T_48, _T_52) node _spad_row_offset_T_9 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_9 = mux(_spad_row_offset_T_9, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_54 = geq(UInt<4>(0h9), spad_row_offset_9) node _T_55 = sub(req.bits.bytes_to_read, bytesSent) node _T_56 = tail(_T_55, 1) node _T_57 = add(spad_row_offset_9, _T_56) node _T_58 = lt(UInt<4>(0h9), _T_57) node _T_59 = and(_T_54, _T_58) node _spad_row_offset_T_10 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_10 = mux(_spad_row_offset_T_10, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_60 = geq(UInt<4>(0ha), spad_row_offset_10) node _T_61 = sub(req.bits.bytes_to_read, bytesSent) node _T_62 = tail(_T_61, 1) node _T_63 = add(spad_row_offset_10, _T_62) node _T_64 = lt(UInt<4>(0ha), _T_63) node _T_65 = and(_T_60, _T_64) node _spad_row_offset_T_11 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_11 = mux(_spad_row_offset_T_11, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_66 = geq(UInt<4>(0hb), spad_row_offset_11) node _T_67 = sub(req.bits.bytes_to_read, bytesSent) node _T_68 = tail(_T_67, 1) node _T_69 = add(spad_row_offset_11, _T_68) node _T_70 = lt(UInt<4>(0hb), _T_69) node _T_71 = and(_T_66, _T_70) node _spad_row_offset_T_12 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_12 = mux(_spad_row_offset_T_12, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_72 = geq(UInt<4>(0hc), spad_row_offset_12) node _T_73 = sub(req.bits.bytes_to_read, bytesSent) node _T_74 = tail(_T_73, 1) node _T_75 = add(spad_row_offset_12, _T_74) node _T_76 = lt(UInt<4>(0hc), _T_75) node _T_77 = and(_T_72, _T_76) node _spad_row_offset_T_13 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_13 = mux(_spad_row_offset_T_13, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_78 = geq(UInt<4>(0hd), spad_row_offset_13) node _T_79 = sub(req.bits.bytes_to_read, bytesSent) node _T_80 = tail(_T_79, 1) node _T_81 = add(spad_row_offset_13, _T_80) node _T_82 = lt(UInt<4>(0hd), _T_81) node _T_83 = and(_T_78, _T_82) node _spad_row_offset_T_14 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_14 = mux(_spad_row_offset_T_14, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_84 = geq(UInt<4>(0he), spad_row_offset_14) node _T_85 = sub(req.bits.bytes_to_read, bytesSent) node _T_86 = tail(_T_85, 1) node _T_87 = add(spad_row_offset_14, _T_86) node _T_88 = lt(UInt<4>(0he), _T_87) node _T_89 = and(_T_84, _T_88) node _spad_row_offset_T_15 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_15 = mux(_spad_row_offset_T_15, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_90 = geq(UInt<4>(0hf), spad_row_offset_15) node _T_91 = sub(req.bits.bytes_to_read, bytesSent) node _T_92 = tail(_T_91, 1) node _T_93 = add(spad_row_offset_15, _T_92) node _T_94 = lt(UInt<4>(0hf), _T_93) node _T_95 = and(_T_90, _T_94) node _spad_row_offset_T_16 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_16 = mux(_spad_row_offset_T_16, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_96 = geq(UInt<5>(0h10), spad_row_offset_16) node _T_97 = sub(req.bits.bytes_to_read, bytesSent) node _T_98 = tail(_T_97, 1) node _T_99 = add(spad_row_offset_16, _T_98) node _T_100 = lt(UInt<5>(0h10), _T_99) node _T_101 = and(_T_96, _T_100) node _spad_row_offset_T_17 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_17 = mux(_spad_row_offset_T_17, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_102 = geq(UInt<5>(0h11), spad_row_offset_17) node _T_103 = sub(req.bits.bytes_to_read, bytesSent) node _T_104 = tail(_T_103, 1) node _T_105 = add(spad_row_offset_17, _T_104) node _T_106 = lt(UInt<5>(0h11), _T_105) node _T_107 = and(_T_102, _T_106) node _spad_row_offset_T_18 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_18 = mux(_spad_row_offset_T_18, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_108 = geq(UInt<5>(0h12), spad_row_offset_18) node _T_109 = sub(req.bits.bytes_to_read, bytesSent) node _T_110 = tail(_T_109, 1) node _T_111 = add(spad_row_offset_18, _T_110) node _T_112 = lt(UInt<5>(0h12), _T_111) node _T_113 = and(_T_108, _T_112) node _spad_row_offset_T_19 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_19 = mux(_spad_row_offset_T_19, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_114 = geq(UInt<5>(0h13), spad_row_offset_19) node _T_115 = sub(req.bits.bytes_to_read, bytesSent) node _T_116 = tail(_T_115, 1) node _T_117 = add(spad_row_offset_19, _T_116) node _T_118 = lt(UInt<5>(0h13), _T_117) node _T_119 = and(_T_114, _T_118) node _spad_row_offset_T_20 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_20 = mux(_spad_row_offset_T_20, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_120 = geq(UInt<5>(0h14), spad_row_offset_20) node _T_121 = sub(req.bits.bytes_to_read, bytesSent) node _T_122 = tail(_T_121, 1) node _T_123 = add(spad_row_offset_20, _T_122) node _T_124 = lt(UInt<5>(0h14), _T_123) node _T_125 = and(_T_120, _T_124) node _spad_row_offset_T_21 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_21 = mux(_spad_row_offset_T_21, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_126 = geq(UInt<5>(0h15), spad_row_offset_21) node _T_127 = sub(req.bits.bytes_to_read, bytesSent) node _T_128 = tail(_T_127, 1) node _T_129 = add(spad_row_offset_21, _T_128) node _T_130 = lt(UInt<5>(0h15), _T_129) node _T_131 = and(_T_126, _T_130) node _spad_row_offset_T_22 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_22 = mux(_spad_row_offset_T_22, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_132 = geq(UInt<5>(0h16), spad_row_offset_22) node _T_133 = sub(req.bits.bytes_to_read, bytesSent) node _T_134 = tail(_T_133, 1) node _T_135 = add(spad_row_offset_22, _T_134) node _T_136 = lt(UInt<5>(0h16), _T_135) node _T_137 = and(_T_132, _T_136) node _spad_row_offset_T_23 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_23 = mux(_spad_row_offset_T_23, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_138 = geq(UInt<5>(0h17), spad_row_offset_23) node _T_139 = sub(req.bits.bytes_to_read, bytesSent) node _T_140 = tail(_T_139, 1) node _T_141 = add(spad_row_offset_23, _T_140) node _T_142 = lt(UInt<5>(0h17), _T_141) node _T_143 = and(_T_138, _T_142) node _spad_row_offset_T_24 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_24 = mux(_spad_row_offset_T_24, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_144 = geq(UInt<5>(0h18), spad_row_offset_24) node _T_145 = sub(req.bits.bytes_to_read, bytesSent) node _T_146 = tail(_T_145, 1) node _T_147 = add(spad_row_offset_24, _T_146) node _T_148 = lt(UInt<5>(0h18), _T_147) node _T_149 = and(_T_144, _T_148) node _spad_row_offset_T_25 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_25 = mux(_spad_row_offset_T_25, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_150 = geq(UInt<5>(0h19), spad_row_offset_25) node _T_151 = sub(req.bits.bytes_to_read, bytesSent) node _T_152 = tail(_T_151, 1) node _T_153 = add(spad_row_offset_25, _T_152) node _T_154 = lt(UInt<5>(0h19), _T_153) node _T_155 = and(_T_150, _T_154) node _spad_row_offset_T_26 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_26 = mux(_spad_row_offset_T_26, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_156 = geq(UInt<5>(0h1a), spad_row_offset_26) node _T_157 = sub(req.bits.bytes_to_read, bytesSent) node _T_158 = tail(_T_157, 1) node _T_159 = add(spad_row_offset_26, _T_158) node _T_160 = lt(UInt<5>(0h1a), _T_159) node _T_161 = and(_T_156, _T_160) node _spad_row_offset_T_27 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_27 = mux(_spad_row_offset_T_27, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_162 = geq(UInt<5>(0h1b), spad_row_offset_27) node _T_163 = sub(req.bits.bytes_to_read, bytesSent) node _T_164 = tail(_T_163, 1) node _T_165 = add(spad_row_offset_27, _T_164) node _T_166 = lt(UInt<5>(0h1b), _T_165) node _T_167 = and(_T_162, _T_166) node _spad_row_offset_T_28 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_28 = mux(_spad_row_offset_T_28, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_168 = geq(UInt<5>(0h1c), spad_row_offset_28) node _T_169 = sub(req.bits.bytes_to_read, bytesSent) node _T_170 = tail(_T_169, 1) node _T_171 = add(spad_row_offset_28, _T_170) node _T_172 = lt(UInt<5>(0h1c), _T_171) node _T_173 = and(_T_168, _T_172) node _spad_row_offset_T_29 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_29 = mux(_spad_row_offset_T_29, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_174 = geq(UInt<5>(0h1d), spad_row_offset_29) node _T_175 = sub(req.bits.bytes_to_read, bytesSent) node _T_176 = tail(_T_175, 1) node _T_177 = add(spad_row_offset_29, _T_176) node _T_178 = lt(UInt<5>(0h1d), _T_177) node _T_179 = and(_T_174, _T_178) node _spad_row_offset_T_30 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_30 = mux(_spad_row_offset_T_30, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_180 = geq(UInt<5>(0h1e), spad_row_offset_30) node _T_181 = sub(req.bits.bytes_to_read, bytesSent) node _T_182 = tail(_T_181, 1) node _T_183 = add(spad_row_offset_30, _T_182) node _T_184 = lt(UInt<5>(0h1e), _T_183) node _T_185 = and(_T_180, _T_184) node _spad_row_offset_T_31 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_31 = mux(_spad_row_offset_T_31, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_186 = geq(UInt<5>(0h1f), spad_row_offset_31) node _T_187 = sub(req.bits.bytes_to_read, bytesSent) node _T_188 = tail(_T_187, 1) node _T_189 = add(spad_row_offset_31, _T_188) node _T_190 = lt(UInt<5>(0h1f), _T_189) node _T_191 = and(_T_186, _T_190) node _spad_row_offset_T_32 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_32 = mux(_spad_row_offset_T_32, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_192 = geq(UInt<6>(0h20), spad_row_offset_32) node _T_193 = sub(req.bits.bytes_to_read, bytesSent) node _T_194 = tail(_T_193, 1) node _T_195 = add(spad_row_offset_32, _T_194) node _T_196 = lt(UInt<6>(0h20), _T_195) node _T_197 = and(_T_192, _T_196) node _spad_row_offset_T_33 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_33 = mux(_spad_row_offset_T_33, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_198 = geq(UInt<6>(0h21), spad_row_offset_33) node _T_199 = sub(req.bits.bytes_to_read, bytesSent) node _T_200 = tail(_T_199, 1) node _T_201 = add(spad_row_offset_33, _T_200) node _T_202 = lt(UInt<6>(0h21), _T_201) node _T_203 = and(_T_198, _T_202) node _spad_row_offset_T_34 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_34 = mux(_spad_row_offset_T_34, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_204 = geq(UInt<6>(0h22), spad_row_offset_34) node _T_205 = sub(req.bits.bytes_to_read, bytesSent) node _T_206 = tail(_T_205, 1) node _T_207 = add(spad_row_offset_34, _T_206) node _T_208 = lt(UInt<6>(0h22), _T_207) node _T_209 = and(_T_204, _T_208) node _spad_row_offset_T_35 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_35 = mux(_spad_row_offset_T_35, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_210 = geq(UInt<6>(0h23), spad_row_offset_35) node _T_211 = sub(req.bits.bytes_to_read, bytesSent) node _T_212 = tail(_T_211, 1) node _T_213 = add(spad_row_offset_35, _T_212) node _T_214 = lt(UInt<6>(0h23), _T_213) node _T_215 = and(_T_210, _T_214) node _spad_row_offset_T_36 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_36 = mux(_spad_row_offset_T_36, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_216 = geq(UInt<6>(0h24), spad_row_offset_36) node _T_217 = sub(req.bits.bytes_to_read, bytesSent) node _T_218 = tail(_T_217, 1) node _T_219 = add(spad_row_offset_36, _T_218) node _T_220 = lt(UInt<6>(0h24), _T_219) node _T_221 = and(_T_216, _T_220) node _spad_row_offset_T_37 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_37 = mux(_spad_row_offset_T_37, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_222 = geq(UInt<6>(0h25), spad_row_offset_37) node _T_223 = sub(req.bits.bytes_to_read, bytesSent) node _T_224 = tail(_T_223, 1) node _T_225 = add(spad_row_offset_37, _T_224) node _T_226 = lt(UInt<6>(0h25), _T_225) node _T_227 = and(_T_222, _T_226) node _spad_row_offset_T_38 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_38 = mux(_spad_row_offset_T_38, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_228 = geq(UInt<6>(0h26), spad_row_offset_38) node _T_229 = sub(req.bits.bytes_to_read, bytesSent) node _T_230 = tail(_T_229, 1) node _T_231 = add(spad_row_offset_38, _T_230) node _T_232 = lt(UInt<6>(0h26), _T_231) node _T_233 = and(_T_228, _T_232) node _spad_row_offset_T_39 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_39 = mux(_spad_row_offset_T_39, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_234 = geq(UInt<6>(0h27), spad_row_offset_39) node _T_235 = sub(req.bits.bytes_to_read, bytesSent) node _T_236 = tail(_T_235, 1) node _T_237 = add(spad_row_offset_39, _T_236) node _T_238 = lt(UInt<6>(0h27), _T_237) node _T_239 = and(_T_234, _T_238) node _spad_row_offset_T_40 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_40 = mux(_spad_row_offset_T_40, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_240 = geq(UInt<6>(0h28), spad_row_offset_40) node _T_241 = sub(req.bits.bytes_to_read, bytesSent) node _T_242 = tail(_T_241, 1) node _T_243 = add(spad_row_offset_40, _T_242) node _T_244 = lt(UInt<6>(0h28), _T_243) node _T_245 = and(_T_240, _T_244) node _spad_row_offset_T_41 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_41 = mux(_spad_row_offset_T_41, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_246 = geq(UInt<6>(0h29), spad_row_offset_41) node _T_247 = sub(req.bits.bytes_to_read, bytesSent) node _T_248 = tail(_T_247, 1) node _T_249 = add(spad_row_offset_41, _T_248) node _T_250 = lt(UInt<6>(0h29), _T_249) node _T_251 = and(_T_246, _T_250) node _spad_row_offset_T_42 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_42 = mux(_spad_row_offset_T_42, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_252 = geq(UInt<6>(0h2a), spad_row_offset_42) node _T_253 = sub(req.bits.bytes_to_read, bytesSent) node _T_254 = tail(_T_253, 1) node _T_255 = add(spad_row_offset_42, _T_254) node _T_256 = lt(UInt<6>(0h2a), _T_255) node _T_257 = and(_T_252, _T_256) node _spad_row_offset_T_43 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_43 = mux(_spad_row_offset_T_43, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_258 = geq(UInt<6>(0h2b), spad_row_offset_43) node _T_259 = sub(req.bits.bytes_to_read, bytesSent) node _T_260 = tail(_T_259, 1) node _T_261 = add(spad_row_offset_43, _T_260) node _T_262 = lt(UInt<6>(0h2b), _T_261) node _T_263 = and(_T_258, _T_262) node _spad_row_offset_T_44 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_44 = mux(_spad_row_offset_T_44, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_264 = geq(UInt<6>(0h2c), spad_row_offset_44) node _T_265 = sub(req.bits.bytes_to_read, bytesSent) node _T_266 = tail(_T_265, 1) node _T_267 = add(spad_row_offset_44, _T_266) node _T_268 = lt(UInt<6>(0h2c), _T_267) node _T_269 = and(_T_264, _T_268) node _spad_row_offset_T_45 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_45 = mux(_spad_row_offset_T_45, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_270 = geq(UInt<6>(0h2d), spad_row_offset_45) node _T_271 = sub(req.bits.bytes_to_read, bytesSent) node _T_272 = tail(_T_271, 1) node _T_273 = add(spad_row_offset_45, _T_272) node _T_274 = lt(UInt<6>(0h2d), _T_273) node _T_275 = and(_T_270, _T_274) node _spad_row_offset_T_46 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_46 = mux(_spad_row_offset_T_46, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_276 = geq(UInt<6>(0h2e), spad_row_offset_46) node _T_277 = sub(req.bits.bytes_to_read, bytesSent) node _T_278 = tail(_T_277, 1) node _T_279 = add(spad_row_offset_46, _T_278) node _T_280 = lt(UInt<6>(0h2e), _T_279) node _T_281 = and(_T_276, _T_280) node _spad_row_offset_T_47 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_47 = mux(_spad_row_offset_T_47, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_282 = geq(UInt<6>(0h2f), spad_row_offset_47) node _T_283 = sub(req.bits.bytes_to_read, bytesSent) node _T_284 = tail(_T_283, 1) node _T_285 = add(spad_row_offset_47, _T_284) node _T_286 = lt(UInt<6>(0h2f), _T_285) node _T_287 = and(_T_282, _T_286) node _spad_row_offset_T_48 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_48 = mux(_spad_row_offset_T_48, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_288 = geq(UInt<6>(0h30), spad_row_offset_48) node _T_289 = sub(req.bits.bytes_to_read, bytesSent) node _T_290 = tail(_T_289, 1) node _T_291 = add(spad_row_offset_48, _T_290) node _T_292 = lt(UInt<6>(0h30), _T_291) node _T_293 = and(_T_288, _T_292) node _spad_row_offset_T_49 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_49 = mux(_spad_row_offset_T_49, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_294 = geq(UInt<6>(0h31), spad_row_offset_49) node _T_295 = sub(req.bits.bytes_to_read, bytesSent) node _T_296 = tail(_T_295, 1) node _T_297 = add(spad_row_offset_49, _T_296) node _T_298 = lt(UInt<6>(0h31), _T_297) node _T_299 = and(_T_294, _T_298) node _spad_row_offset_T_50 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_50 = mux(_spad_row_offset_T_50, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_300 = geq(UInt<6>(0h32), spad_row_offset_50) node _T_301 = sub(req.bits.bytes_to_read, bytesSent) node _T_302 = tail(_T_301, 1) node _T_303 = add(spad_row_offset_50, _T_302) node _T_304 = lt(UInt<6>(0h32), _T_303) node _T_305 = and(_T_300, _T_304) node _spad_row_offset_T_51 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_51 = mux(_spad_row_offset_T_51, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_306 = geq(UInt<6>(0h33), spad_row_offset_51) node _T_307 = sub(req.bits.bytes_to_read, bytesSent) node _T_308 = tail(_T_307, 1) node _T_309 = add(spad_row_offset_51, _T_308) node _T_310 = lt(UInt<6>(0h33), _T_309) node _T_311 = and(_T_306, _T_310) node _spad_row_offset_T_52 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_52 = mux(_spad_row_offset_T_52, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_312 = geq(UInt<6>(0h34), spad_row_offset_52) node _T_313 = sub(req.bits.bytes_to_read, bytesSent) node _T_314 = tail(_T_313, 1) node _T_315 = add(spad_row_offset_52, _T_314) node _T_316 = lt(UInt<6>(0h34), _T_315) node _T_317 = and(_T_312, _T_316) node _spad_row_offset_T_53 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_53 = mux(_spad_row_offset_T_53, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_318 = geq(UInt<6>(0h35), spad_row_offset_53) node _T_319 = sub(req.bits.bytes_to_read, bytesSent) node _T_320 = tail(_T_319, 1) node _T_321 = add(spad_row_offset_53, _T_320) node _T_322 = lt(UInt<6>(0h35), _T_321) node _T_323 = and(_T_318, _T_322) node _spad_row_offset_T_54 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_54 = mux(_spad_row_offset_T_54, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_324 = geq(UInt<6>(0h36), spad_row_offset_54) node _T_325 = sub(req.bits.bytes_to_read, bytesSent) node _T_326 = tail(_T_325, 1) node _T_327 = add(spad_row_offset_54, _T_326) node _T_328 = lt(UInt<6>(0h36), _T_327) node _T_329 = and(_T_324, _T_328) node _spad_row_offset_T_55 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_55 = mux(_spad_row_offset_T_55, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_330 = geq(UInt<6>(0h37), spad_row_offset_55) node _T_331 = sub(req.bits.bytes_to_read, bytesSent) node _T_332 = tail(_T_331, 1) node _T_333 = add(spad_row_offset_55, _T_332) node _T_334 = lt(UInt<6>(0h37), _T_333) node _T_335 = and(_T_330, _T_334) node _spad_row_offset_T_56 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_56 = mux(_spad_row_offset_T_56, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_336 = geq(UInt<6>(0h38), spad_row_offset_56) node _T_337 = sub(req.bits.bytes_to_read, bytesSent) node _T_338 = tail(_T_337, 1) node _T_339 = add(spad_row_offset_56, _T_338) node _T_340 = lt(UInt<6>(0h38), _T_339) node _T_341 = and(_T_336, _T_340) node _spad_row_offset_T_57 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_57 = mux(_spad_row_offset_T_57, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_342 = geq(UInt<6>(0h39), spad_row_offset_57) node _T_343 = sub(req.bits.bytes_to_read, bytesSent) node _T_344 = tail(_T_343, 1) node _T_345 = add(spad_row_offset_57, _T_344) node _T_346 = lt(UInt<6>(0h39), _T_345) node _T_347 = and(_T_342, _T_346) node _spad_row_offset_T_58 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_58 = mux(_spad_row_offset_T_58, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_348 = geq(UInt<6>(0h3a), spad_row_offset_58) node _T_349 = sub(req.bits.bytes_to_read, bytesSent) node _T_350 = tail(_T_349, 1) node _T_351 = add(spad_row_offset_58, _T_350) node _T_352 = lt(UInt<6>(0h3a), _T_351) node _T_353 = and(_T_348, _T_352) node _spad_row_offset_T_59 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_59 = mux(_spad_row_offset_T_59, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_354 = geq(UInt<6>(0h3b), spad_row_offset_59) node _T_355 = sub(req.bits.bytes_to_read, bytesSent) node _T_356 = tail(_T_355, 1) node _T_357 = add(spad_row_offset_59, _T_356) node _T_358 = lt(UInt<6>(0h3b), _T_357) node _T_359 = and(_T_354, _T_358) node _spad_row_offset_T_60 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_60 = mux(_spad_row_offset_T_60, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_360 = geq(UInt<6>(0h3c), spad_row_offset_60) node _T_361 = sub(req.bits.bytes_to_read, bytesSent) node _T_362 = tail(_T_361, 1) node _T_363 = add(spad_row_offset_60, _T_362) node _T_364 = lt(UInt<6>(0h3c), _T_363) node _T_365 = and(_T_360, _T_364) node _spad_row_offset_T_61 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_61 = mux(_spad_row_offset_T_61, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_366 = geq(UInt<6>(0h3d), spad_row_offset_61) node _T_367 = sub(req.bits.bytes_to_read, bytesSent) node _T_368 = tail(_T_367, 1) node _T_369 = add(spad_row_offset_61, _T_368) node _T_370 = lt(UInt<6>(0h3d), _T_369) node _T_371 = and(_T_366, _T_370) node _spad_row_offset_T_62 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_62 = mux(_spad_row_offset_T_62, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_372 = geq(UInt<6>(0h3e), spad_row_offset_62) node _T_373 = sub(req.bits.bytes_to_read, bytesSent) node _T_374 = tail(_T_373, 1) node _T_375 = add(spad_row_offset_62, _T_374) node _T_376 = lt(UInt<6>(0h3e), _T_375) node _T_377 = and(_T_372, _T_376) node _spad_row_offset_T_63 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_63 = mux(_spad_row_offset_T_63, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_378 = geq(UInt<6>(0h3f), spad_row_offset_63) node _T_379 = sub(req.bits.bytes_to_read, bytesSent) node _T_380 = tail(_T_379, 1) node _T_381 = add(spad_row_offset_63, _T_380) node _T_382 = lt(UInt<6>(0h3f), _T_381) node _T_383 = and(_T_378, _T_382) wire _WIRE : UInt<1>[64] connect _WIRE[0], _T_5 connect _WIRE[1], _T_11 connect _WIRE[2], _T_17 connect _WIRE[3], _T_23 connect _WIRE[4], _T_29 connect _WIRE[5], _T_35 connect _WIRE[6], _T_41 connect _WIRE[7], _T_47 connect _WIRE[8], _T_53 connect _WIRE[9], _T_59 connect _WIRE[10], _T_65 connect _WIRE[11], _T_71 connect _WIRE[12], _T_77 connect _WIRE[13], _T_83 connect _WIRE[14], _T_89 connect _WIRE[15], _T_95 connect _WIRE[16], _T_101 connect _WIRE[17], _T_107 connect _WIRE[18], _T_113 connect _WIRE[19], _T_119 connect _WIRE[20], _T_125 connect _WIRE[21], _T_131 connect _WIRE[22], _T_137 connect _WIRE[23], _T_143 connect _WIRE[24], _T_149 connect _WIRE[25], _T_155 connect _WIRE[26], _T_161 connect _WIRE[27], _T_167 connect _WIRE[28], _T_173 connect _WIRE[29], _T_179 connect _WIRE[30], _T_185 connect _WIRE[31], _T_191 connect _WIRE[32], _T_197 connect _WIRE[33], _T_203 connect _WIRE[34], _T_209 connect _WIRE[35], _T_215 connect _WIRE[36], _T_221 connect _WIRE[37], _T_227 connect _WIRE[38], _T_233 connect _WIRE[39], _T_239 connect _WIRE[40], _T_245 connect _WIRE[41], _T_251 connect _WIRE[42], _T_257 connect _WIRE[43], _T_263 connect _WIRE[44], _T_269 connect _WIRE[45], _T_275 connect _WIRE[46], _T_281 connect _WIRE[47], _T_287 connect _WIRE[48], _T_293 connect _WIRE[49], _T_299 connect _WIRE[50], _T_305 connect _WIRE[51], _T_311 connect _WIRE[52], _T_317 connect _WIRE[53], _T_323 connect _WIRE[54], _T_329 connect _WIRE[55], _T_335 connect _WIRE[56], _T_341 connect _WIRE[57], _T_347 connect _WIRE[58], _T_353 connect _WIRE[59], _T_359 connect _WIRE[60], _T_365 connect _WIRE[61], _T_371 connect _WIRE[62], _T_377 connect _WIRE[63], _T_383 connect io.out.bits.mask, _WIRE node _io_out_bits_addr_total_bytes_sent_T = add(req.bits.spad_row_offset, bytesSent) node io_out_bits_addr_total_bytes_sent = tail(_io_out_bits_addr_total_bytes_sent_T, 1) node _io_out_bits_addr_T = div(io_out_bits_addr_total_bytes_sent, UInt<9>(0h40)) node _io_out_bits_addr_T_1 = div(io_out_bits_addr_total_bytes_sent, UInt<9>(0h10)) node _io_out_bits_addr_T_2 = mux(req.bits.has_acc_bitwidth, _io_out_bits_addr_T, _io_out_bits_addr_T_1) node _io_out_bits_addr_T_3 = mul(req.bits.block_stride, _io_out_bits_addr_T_2) node _io_out_bits_addr_T_4 = add(req.bits.addr, _io_out_bits_addr_T_3) node _io_out_bits_addr_T_5 = tail(_io_out_bits_addr_T_4, 1) connect io.out.bits.addr, _io_out_bits_addr_T_5 connect io.out.bits.is_acc, req.bits.is_acc connect io.out.bits.accumulate, req.bits.accumulate connect io.out.bits.has_acc_bitwidth, req.bits.has_acc_bitwidth connect io.out.bits.last, last_sending connect io.out.bits.accumulate, req.bits.accumulate connect io.out.bits.has_acc_bitwidth, req.bits.has_acc_bitwidth node _T_384 = dshl(UInt<1>(0h1), req.bits.lg_len_req) node _T_385 = eq(bytesRead, _T_384) node _T_386 = eq(bytesSent, req.bits.bytes_to_read) node _T_387 = and(_T_385, _T_386) when _T_387 : connect req.valid, UInt<1>(0h0) node _T_388 = and(io.out.ready, io.out.valid) when _T_388 : connect bytesSent, bytesSent_next node _T_389 = dshl(UInt<1>(0h1), req.bits.lg_len_req) node _T_390 = eq(bytesRead, _T_389) node _T_391 = and(last_sending, _T_390) when _T_391 : connect req.valid, UInt<1>(0h0) connect io.req.ready, UInt<1>(0h1) node _T_392 = and(io.req.ready, io.req.valid) when _T_392 : connect req.valid, UInt<1>(0h1) connect req.bits, io.req.bits connect bytesRead, UInt<1>(0h0) connect bytesSent, UInt<1>(0h0) node _T_393 = and(io.in.ready, io.in.valid) when _T_393 : node _current_bytesRead_T = and(io.req.ready, io.req.valid) node current_bytesRead = mux(_current_bytesRead_T, UInt<1>(0h0), bytesRead) node _current_bytesDiscarded_T = and(io.req.ready, io.req.valid) node current_bytesDiscarded = mux(_current_bytesDiscarded_T, UInt<1>(0h0), bytesDiscarded) node _current_usefulBytesRead_T = and(io.req.ready, io.req.valid) node current_usefulBytesRead = mux(_current_usefulBytesRead_T, UInt<1>(0h0), usefulBytesRead) node _current_shift_T = and(io.req.ready, io.req.valid) node current_shift = mux(_current_shift_T, io.req.bits.shift, req.bits.shift) node _current_lg_len_req_T = and(io.req.ready, io.req.valid) node current_lg_len_req = mux(_current_lg_len_req_T, io.req.bits.lg_len_req, req.bits.lg_len_req) node current_len_req = dshl(UInt<1>(0h1), current_lg_len_req) node _T_394 = sub(current_shift, current_bytesDiscarded) node _T_395 = tail(_T_394, 1) node _T_396 = leq(_T_395, UInt<5>(0h10)) when _T_396 : node _rshift_T = sub(current_shift, current_bytesDiscarded) node _rshift_T_1 = tail(_rshift_T, 1) node rshift = mul(_rshift_T_1, UInt<4>(0h8)) node lshift = mul(current_usefulBytesRead, UInt<4>(0h8)) node _mask_T = not(UInt<128>(0h0)) node _mask_T_1 = dshr(_mask_T, rshift) node _mask_T_2 = dshl(_mask_T_1, lshift) node mask = not(_mask_T_2) node _buffer_T = and(buffer, mask) node _buffer_T_1 = dshr(io.in.bits, rshift) node _buffer_T_2 = dshl(_buffer_T_1, lshift) node _buffer_T_3 = or(_buffer_T, _buffer_T_2) connect buffer, _buffer_T_3 node _bytesRead_T = add(current_bytesRead, UInt<5>(0h10)) node _bytesRead_T_1 = gt(_bytesRead_T, current_len_req) node _bytesRead_T_2 = add(current_bytesRead, UInt<5>(0h10)) node _bytesRead_T_3 = tail(_bytesRead_T_2, 1) node _bytesRead_T_4 = mux(_bytesRead_T_1, current_len_req, _bytesRead_T_3) connect bytesRead, _bytesRead_T_4 node _T_397 = and(io.req.ready, io.req.valid) node _T_398 = eq(_T_397, UInt<1>(0h0)) node _T_399 = eq(bytesSent, req.bits.bytes_to_read) node _T_400 = and(_T_398, _T_399) node _T_401 = and(_T_400, last_reading) when _T_401 : connect req.valid, UInt<1>(0h0) node _T_402 = asUInt(reset) when _T_402 : connect req.valid, UInt<1>(0h0)
module BeatMerger( // @[BeatMerger.scala:30:7] input clock, // @[BeatMerger.scala:30:7] input reset, // @[BeatMerger.scala:30:7] output io_req_ready, // @[BeatMerger.scala:33:14] input io_req_valid, // @[BeatMerger.scala:33:14] input [5:0] io_req_bits_shift, // @[BeatMerger.scala:33:14] input [13:0] io_req_bits_addr, // @[BeatMerger.scala:33:14] input io_req_bits_is_acc, // @[BeatMerger.scala:33:14] input io_req_bits_accumulate, // @[BeatMerger.scala:33:14] input io_req_bits_has_acc_bitwidth, // @[BeatMerger.scala:33:14] input [31:0] io_req_bits_scale, // @[BeatMerger.scala:33:14] input [15:0] io_req_bits_repeats, // @[BeatMerger.scala:33:14] input [7:0] io_req_bits_pixel_repeats, // @[BeatMerger.scala:33:14] input [15:0] io_req_bits_len, // @[BeatMerger.scala:33:14] input [15:0] io_req_bits_block_stride, // @[BeatMerger.scala:33:14] input [8:0] io_req_bits_spad_row_offset, // @[BeatMerger.scala:33:14] input [2:0] io_req_bits_lg_len_req, // @[BeatMerger.scala:33:14] input [6:0] io_req_bits_bytes_to_read, // @[BeatMerger.scala:33:14] input io_req_bits_cmd_id, // @[BeatMerger.scala:33:14] output io_in_ready, // @[BeatMerger.scala:33:14] input io_in_valid, // @[BeatMerger.scala:33:14] input [127:0] io_in_bits, // @[BeatMerger.scala:33:14] input io_out_ready, // @[BeatMerger.scala:33:14] output io_out_valid, // @[BeatMerger.scala:33:14] output [511:0] io_out_bits_data, // @[BeatMerger.scala:33:14] output [13:0] io_out_bits_addr, // @[BeatMerger.scala:33:14] output io_out_bits_is_acc, // @[BeatMerger.scala:33:14] output io_out_bits_accumulate, // @[BeatMerger.scala:33:14] output io_out_bits_has_acc_bitwidth, // @[BeatMerger.scala:33:14] output io_out_bits_mask_0, // @[BeatMerger.scala:33:14] output io_out_bits_mask_1, // @[BeatMerger.scala:33:14] output io_out_bits_mask_2, // @[BeatMerger.scala:33:14] output io_out_bits_mask_3, // @[BeatMerger.scala:33:14] output io_out_bits_mask_4, // @[BeatMerger.scala:33:14] output io_out_bits_mask_5, // @[BeatMerger.scala:33:14] output io_out_bits_mask_6, // @[BeatMerger.scala:33:14] output io_out_bits_mask_7, // @[BeatMerger.scala:33:14] output io_out_bits_mask_8, // @[BeatMerger.scala:33:14] output io_out_bits_mask_9, // @[BeatMerger.scala:33:14] output io_out_bits_mask_10, // @[BeatMerger.scala:33:14] output io_out_bits_mask_11, // @[BeatMerger.scala:33:14] output io_out_bits_mask_12, // @[BeatMerger.scala:33:14] output io_out_bits_mask_13, // @[BeatMerger.scala:33:14] output io_out_bits_mask_14, // @[BeatMerger.scala:33:14] output io_out_bits_mask_15, // @[BeatMerger.scala:33:14] output io_out_bits_mask_16, // @[BeatMerger.scala:33:14] output io_out_bits_mask_17, // @[BeatMerger.scala:33:14] output io_out_bits_mask_18, // @[BeatMerger.scala:33:14] output io_out_bits_mask_19, // @[BeatMerger.scala:33:14] output io_out_bits_mask_20, // @[BeatMerger.scala:33:14] output io_out_bits_mask_21, // @[BeatMerger.scala:33:14] output io_out_bits_mask_22, // @[BeatMerger.scala:33:14] output io_out_bits_mask_23, // @[BeatMerger.scala:33:14] output io_out_bits_mask_24, // @[BeatMerger.scala:33:14] output io_out_bits_mask_25, // @[BeatMerger.scala:33:14] output io_out_bits_mask_26, // @[BeatMerger.scala:33:14] output io_out_bits_mask_27, // @[BeatMerger.scala:33:14] output io_out_bits_mask_28, // @[BeatMerger.scala:33:14] output io_out_bits_mask_29, // @[BeatMerger.scala:33:14] output io_out_bits_mask_30, // @[BeatMerger.scala:33:14] output io_out_bits_mask_31, // @[BeatMerger.scala:33:14] output io_out_bits_mask_32, // @[BeatMerger.scala:33:14] output io_out_bits_mask_33, // @[BeatMerger.scala:33:14] output io_out_bits_mask_34, // @[BeatMerger.scala:33:14] output io_out_bits_mask_35, // @[BeatMerger.scala:33:14] output io_out_bits_mask_36, // @[BeatMerger.scala:33:14] output io_out_bits_mask_37, // @[BeatMerger.scala:33:14] output io_out_bits_mask_38, // @[BeatMerger.scala:33:14] output io_out_bits_mask_39, // @[BeatMerger.scala:33:14] output io_out_bits_mask_40, // @[BeatMerger.scala:33:14] output io_out_bits_mask_41, // @[BeatMerger.scala:33:14] output io_out_bits_mask_42, // @[BeatMerger.scala:33:14] output io_out_bits_mask_43, // @[BeatMerger.scala:33:14] output io_out_bits_mask_44, // @[BeatMerger.scala:33:14] output io_out_bits_mask_45, // @[BeatMerger.scala:33:14] output io_out_bits_mask_46, // @[BeatMerger.scala:33:14] output io_out_bits_mask_47, // @[BeatMerger.scala:33:14] output io_out_bits_mask_48, // @[BeatMerger.scala:33:14] output io_out_bits_mask_49, // @[BeatMerger.scala:33:14] output io_out_bits_mask_50, // @[BeatMerger.scala:33:14] output io_out_bits_mask_51, // @[BeatMerger.scala:33:14] output io_out_bits_mask_52, // @[BeatMerger.scala:33:14] output io_out_bits_mask_53, // @[BeatMerger.scala:33:14] output io_out_bits_mask_54, // @[BeatMerger.scala:33:14] output io_out_bits_mask_55, // @[BeatMerger.scala:33:14] output io_out_bits_mask_56, // @[BeatMerger.scala:33:14] output io_out_bits_mask_57, // @[BeatMerger.scala:33:14] output io_out_bits_mask_58, // @[BeatMerger.scala:33:14] output io_out_bits_mask_59, // @[BeatMerger.scala:33:14] output io_out_bits_mask_60, // @[BeatMerger.scala:33:14] output io_out_bits_mask_61, // @[BeatMerger.scala:33:14] output io_out_bits_mask_62, // @[BeatMerger.scala:33:14] output io_out_bits_mask_63, // @[BeatMerger.scala:33:14] output io_out_bits_last // @[BeatMerger.scala:33:14] ); wire io_req_valid_0 = io_req_valid; // @[BeatMerger.scala:30:7] wire [5:0] io_req_bits_shift_0 = io_req_bits_shift; // @[BeatMerger.scala:30:7] wire [13:0] io_req_bits_addr_0 = io_req_bits_addr; // @[BeatMerger.scala:30:7] wire io_req_bits_is_acc_0 = io_req_bits_is_acc; // @[BeatMerger.scala:30:7] wire io_req_bits_accumulate_0 = io_req_bits_accumulate; // @[BeatMerger.scala:30:7] wire io_req_bits_has_acc_bitwidth_0 = io_req_bits_has_acc_bitwidth; // @[BeatMerger.scala:30:7] wire [31:0] io_req_bits_scale_0 = io_req_bits_scale; // @[BeatMerger.scala:30:7] wire [15:0] io_req_bits_repeats_0 = io_req_bits_repeats; // @[BeatMerger.scala:30:7] wire [7:0] io_req_bits_pixel_repeats_0 = io_req_bits_pixel_repeats; // @[BeatMerger.scala:30:7] wire [15:0] io_req_bits_len_0 = io_req_bits_len; // @[BeatMerger.scala:30:7] wire [15:0] io_req_bits_block_stride_0 = io_req_bits_block_stride; // @[BeatMerger.scala:30:7] wire [8:0] io_req_bits_spad_row_offset_0 = io_req_bits_spad_row_offset; // @[BeatMerger.scala:30:7] wire [2:0] io_req_bits_lg_len_req_0 = io_req_bits_lg_len_req; // @[BeatMerger.scala:30:7] wire [6:0] io_req_bits_bytes_to_read_0 = io_req_bits_bytes_to_read; // @[BeatMerger.scala:30:7] wire io_req_bits_cmd_id_0 = io_req_bits_cmd_id; // @[BeatMerger.scala:30:7] wire io_in_valid_0 = io_in_valid; // @[BeatMerger.scala:30:7] wire [127:0] io_in_bits_0 = io_in_bits; // @[BeatMerger.scala:30:7] wire io_out_ready_0 = io_out_ready; // @[BeatMerger.scala:30:7] wire [127:0] _mask_T = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[BeatMerger.scala:126:23] wire _io_in_ready_T_4; // @[BeatMerger.scala:66:30] wire _io_out_valid_T_7; // @[BeatMerger.scala:68:60] wire last_sending; // @[BeatMerger.scala:61:37] wire io_req_ready_0; // @[BeatMerger.scala:30:7] wire io_in_ready_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_0_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_1_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_2_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_3_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_4_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_5_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_6_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_7_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_8_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_9_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_10_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_11_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_12_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_13_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_14_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_15_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_16_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_17_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_18_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_19_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_20_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_21_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_22_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_23_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_24_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_25_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_26_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_27_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_28_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_29_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_30_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_31_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_32_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_33_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_34_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_35_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_36_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_37_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_38_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_39_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_40_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_41_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_42_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_43_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_44_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_45_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_46_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_47_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_48_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_49_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_50_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_51_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_52_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_53_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_54_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_55_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_56_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_57_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_58_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_59_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_60_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_61_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_62_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_63_0; // @[BeatMerger.scala:30:7] wire [511:0] io_out_bits_data_0; // @[BeatMerger.scala:30:7] wire [13:0] io_out_bits_addr_0; // @[BeatMerger.scala:30:7] wire io_out_bits_is_acc_0; // @[BeatMerger.scala:30:7] wire io_out_bits_accumulate_0; // @[BeatMerger.scala:30:7] wire io_out_bits_has_acc_bitwidth_0; // @[BeatMerger.scala:30:7] wire io_out_bits_last_0; // @[BeatMerger.scala:30:7] wire io_out_valid_0; // @[BeatMerger.scala:30:7] reg req_valid; // @[BeatMerger.scala:43:16] reg [5:0] req_bits_shift; // @[BeatMerger.scala:43:16] reg [13:0] req_bits_addr; // @[BeatMerger.scala:43:16] reg req_bits_is_acc; // @[BeatMerger.scala:43:16] assign io_out_bits_is_acc_0 = req_bits_is_acc; // @[BeatMerger.scala:30:7, :43:16] reg req_bits_accumulate; // @[BeatMerger.scala:43:16] assign io_out_bits_accumulate_0 = req_bits_accumulate; // @[BeatMerger.scala:30:7, :43:16] reg req_bits_has_acc_bitwidth; // @[BeatMerger.scala:43:16] assign io_out_bits_has_acc_bitwidth_0 = req_bits_has_acc_bitwidth; // @[BeatMerger.scala:30:7, :43:16] reg [31:0] req_bits_scale; // @[BeatMerger.scala:43:16] reg [15:0] req_bits_repeats; // @[BeatMerger.scala:43:16] reg [7:0] req_bits_pixel_repeats; // @[BeatMerger.scala:43:16] reg [15:0] req_bits_len; // @[BeatMerger.scala:43:16] reg [15:0] req_bits_block_stride; // @[BeatMerger.scala:43:16] reg [8:0] req_bits_spad_row_offset; // @[BeatMerger.scala:43:16] reg [2:0] req_bits_lg_len_req; // @[BeatMerger.scala:43:16] reg [6:0] req_bits_bytes_to_read; // @[BeatMerger.scala:43:16] reg req_bits_cmd_id; // @[BeatMerger.scala:43:16] reg [511:0] buffer; // @[BeatMerger.scala:46:19] wire [6:0] rowBytes = req_bits_has_acc_bitwidth ? 7'h40 : 7'h10; // @[BeatMerger.scala:43:16, :48:21, :121:50] reg [6:0] bytesSent; // @[BeatMerger.scala:50:22] reg [6:0] bytesRead; // @[BeatMerger.scala:51:22] wire _bytesReadAfterShift_T = bytesRead > {1'h0, req_bits_shift}; // @[BeatMerger.scala:43:16, :51:22, :52:43] wire [7:0] _GEN = {1'h0, bytesRead}; // @[BeatMerger.scala:51:22, :52:71] wire [7:0] _bytesReadAfterShift_T_1 = _GEN - {2'h0, req_bits_shift}; // @[BeatMerger.scala:43:16, :52:71] wire [6:0] _bytesReadAfterShift_T_2 = _bytesReadAfterShift_T_1[6:0]; // @[BeatMerger.scala:52:71] wire [6:0] bytesReadAfterShift = _bytesReadAfterShift_T ? _bytesReadAfterShift_T_2 : 7'h0; // @[BeatMerger.scala:52:{32,43,71}] wire [7:0] _bytesDiscarded_T = _GEN - {1'h0, bytesReadAfterShift}; // @[BeatMerger.scala:52:{32,71}, :53:34] wire [6:0] bytesDiscarded = _bytesDiscarded_T[6:0]; // @[BeatMerger.scala:53:34] wire _usefulBytesRead_T = bytesReadAfterShift < req_bits_bytes_to_read; // @[Util.scala:109:12] wire [6:0] usefulBytesRead = _usefulBytesRead_T ? bytesReadAfterShift : req_bits_bytes_to_read; // @[Util.scala:109:{8,12}] wire _GEN_0 = bytesSent == 7'h0; // @[BeatMerger.scala:50:22, :57:41] wire _bytesSent_next_spad_row_offset_T; // @[BeatMerger.scala:57:41] assign _bytesSent_next_spad_row_offset_T = _GEN_0; // @[BeatMerger.scala:57:41] wire _io_out_bits_data_T_2; // @[BeatMerger.scala:70:70] assign _io_out_bits_data_T_2 = _GEN_0; // @[BeatMerger.scala:57:41, :70:70] wire _spad_row_offset_T; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_1; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_1 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_2; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_2 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_3; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_3 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_4; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_4 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_5; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_5 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_6; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_6 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_7; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_7 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_8; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_8 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_9; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_9 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_10; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_10 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_11; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_11 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_12; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_12 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_13; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_13 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_14; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_14 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_15; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_15 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_16; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_16 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_17; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_17 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_18; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_18 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_19; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_19 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_20; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_20 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_21; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_21 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_22; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_22 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_23; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_23 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_24; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_24 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_25; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_25 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_26; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_26 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_27; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_27 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_28; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_28 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_29; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_29 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_30; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_30 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_31; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_31 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_32; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_32 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_33; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_33 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_34; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_34 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_35; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_35 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_36; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_36 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_37; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_37 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_38; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_38 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_39; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_39 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_40; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_40 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_41; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_41 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_42; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_42 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_43; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_43 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_44; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_44 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_45; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_45 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_46; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_46 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_47; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_47 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_48; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_48 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_49; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_49 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_50; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_50 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_51; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_51 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_52; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_52 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_53; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_53 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_54; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_54 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_55; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_55 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_56; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_56 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_57; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_57 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_58; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_58 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_59; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_59 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_60; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_60 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_61; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_61 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_62; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_62 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_63; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_63 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire [8:0] bytesSent_next_spad_row_offset = _bytesSent_next_spad_row_offset_T ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :57:{30,41}] wire [9:0] _bytesSent_next_T = {3'h0, rowBytes} - {1'h0, bytesSent_next_spad_row_offset}; // @[BeatMerger.scala:48:21, :57:30, :58:32] wire [8:0] _bytesSent_next_T_1 = _bytesSent_next_T[8:0]; // @[BeatMerger.scala:58:32] wire [9:0] _GEN_1 = {3'h0, bytesSent}; // @[Util.scala:35:11] wire [9:0] _GEN_2 = _GEN_1 + {1'h0, _bytesSent_next_T_1}; // @[Util.scala:35:11] wire [9:0] _bytesSent_next_T_2; // @[Util.scala:35:11] assign _bytesSent_next_T_2 = _GEN_2; // @[Util.scala:35:11] wire [9:0] _bytesSent_next_T_4; // @[Util.scala:35:30] assign _bytesSent_next_T_4 = _GEN_2; // @[Util.scala:35:{11,30}] wire _bytesSent_next_T_3 = _bytesSent_next_T_2 > {3'h0, req_bits_bytes_to_read}; // @[Util.scala:35:{11,16}] wire [8:0] _bytesSent_next_T_5 = _bytesSent_next_T_4[8:0]; // @[Util.scala:35:30] wire [8:0] _GEN_3 = {2'h0, req_bits_bytes_to_read}; // @[Util.scala:35:8] wire [8:0] bytesSent_next = _bytesSent_next_T_3 ? _GEN_3 : _bytesSent_next_T_5; // @[Util.scala:35:{8,16,30}] assign last_sending = bytesSent_next == _GEN_3; // @[Util.scala:35:8] assign io_out_bits_last_0 = last_sending; // @[BeatMerger.scala:30:7, :61:37] wire [7:0] _T_389 = 8'h1 << req_bits_lg_len_req; // @[BeatMerger.scala:43:16, :62:42] wire [7:0] _last_reading_T; // @[BeatMerger.scala:62:42] assign _last_reading_T = _T_389; // @[BeatMerger.scala:62:42] wire [7:0] _io_in_ready_T_1; // @[BeatMerger.scala:66:66] assign _io_in_ready_T_1 = _T_389; // @[BeatMerger.scala:62:42, :66:66] wire [8:0] _last_reading_T_1 = {1'h0, _last_reading_T} - {2'h0, bytesRead}; // @[BeatMerger.scala:51:22, :52:71, :62:{42,73}] wire [7:0] _last_reading_T_2 = _last_reading_T_1[7:0]; // @[BeatMerger.scala:62:73] wire last_reading = _last_reading_T_2 < 8'h11; // @[BeatMerger.scala:62:{34,73}] wire _io_req_ready_T = ~req_valid; // @[BeatMerger.scala:43:16, :64:19] wire _T_397 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire _io_in_ready_T; // @[Decoupled.scala:51:35] assign _io_in_ready_T = _T_397; // @[Decoupled.scala:51:35] wire _current_bytesRead_T; // @[Decoupled.scala:51:35] assign _current_bytesRead_T = _T_397; // @[Decoupled.scala:51:35] wire _current_bytesDiscarded_T; // @[Decoupled.scala:51:35] assign _current_bytesDiscarded_T = _T_397; // @[Decoupled.scala:51:35] wire _current_usefulBytesRead_T; // @[Decoupled.scala:51:35] assign _current_usefulBytesRead_T = _T_397; // @[Decoupled.scala:51:35] wire _current_shift_T; // @[Decoupled.scala:51:35] assign _current_shift_T = _T_397; // @[Decoupled.scala:51:35] wire _current_lg_len_req_T; // @[Decoupled.scala:51:35] assign _current_lg_len_req_T = _T_397; // @[Decoupled.scala:51:35] wire _io_in_ready_T_2 = _GEN != _io_in_ready_T_1; // @[BeatMerger.scala:52:71, :66:{57,66}] wire _io_in_ready_T_3 = req_valid & _io_in_ready_T_2; // @[BeatMerger.scala:43:16, :66:{44,57}] assign _io_in_ready_T_4 = _io_in_ready_T | _io_in_ready_T_3; // @[Decoupled.scala:51:35] assign io_in_ready_0 = _io_in_ready_T_4; // @[BeatMerger.scala:30:7, :66:30] wire _io_out_valid_T = usefulBytesRead > bytesSent; // @[Util.scala:109:8] wire _io_out_valid_T_1 = req_valid & _io_out_valid_T; // @[BeatMerger.scala:43:16, :68:{29,48}] wire [7:0] _io_out_valid_T_2 = {1'h0, usefulBytesRead} - {1'h0, bytesSent}; // @[Util.scala:109:8] wire [6:0] _io_out_valid_T_3 = _io_out_valid_T_2[6:0]; // @[BeatMerger.scala:68:80] wire _io_out_valid_T_4 = _io_out_valid_T_3 >= rowBytes; // @[BeatMerger.scala:48:21, :68:{80,92}] wire _io_out_valid_T_5 = usefulBytesRead == req_bits_bytes_to_read; // @[Util.scala:109:8] wire _io_out_valid_T_6 = _io_out_valid_T_4 | _io_out_valid_T_5; // @[BeatMerger.scala:68:{92,104}, :69:21] assign _io_out_valid_T_7 = _io_out_valid_T_1 & _io_out_valid_T_6; // @[BeatMerger.scala:68:{29,60,104}] assign io_out_valid_0 = _io_out_valid_T_7; // @[BeatMerger.scala:30:7, :68:60] wire [10:0] _io_out_bits_data_T = {1'h0, bytesSent, 3'h0}; // @[BeatMerger.scala:50:22, :70:45] wire [511:0] _io_out_bits_data_T_1 = buffer >> _io_out_bits_data_T; // @[BeatMerger.scala:46:19, :70:{31,45}] wire [12:0] _io_out_bits_data_T_3 = {1'h0, req_bits_spad_row_offset, 3'h0}; // @[BeatMerger.scala:43:16, :70:104] wire [12:0] _io_out_bits_data_T_4 = _io_out_bits_data_T_2 ? _io_out_bits_data_T_3 : 13'h0; // @[BeatMerger.scala:70:{59,70,104}] wire [8702:0] _io_out_bits_data_T_5 = {8191'h0, _io_out_bits_data_T_1} << _io_out_bits_data_T_4; // @[BeatMerger.scala:70:{31,53,59}] assign io_out_bits_data_0 = _io_out_bits_data_T_5[511:0]; // @[BeatMerger.scala:30:7, :70:{20,53}] wire [8:0] spad_row_offset = _spad_row_offset_T ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _GEN_4 = {3'h0, req_bits_bytes_to_read - bytesSent}; // @[BeatMerger.scala:43:16, :50:22, :74:{29,56}] assign io_out_bits_mask_0_0 = spad_row_offset == 9'h0 & (|({1'h0, spad_row_offset} + _GEN_4)); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_1 = _spad_row_offset_T_1 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_9 = {1'h0, spad_row_offset_1} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_1_0 = spad_row_offset_1 < 9'h2 & (|(_T_9[9:1])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_2 = _spad_row_offset_T_2 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_2_0 = spad_row_offset_2 < 9'h3 & {1'h0, spad_row_offset_2} + _GEN_4 > 10'h2; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_3 = _spad_row_offset_T_3 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_21 = {1'h0, spad_row_offset_3} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_3_0 = spad_row_offset_3 < 9'h4 & (|(_T_21[9:2])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_4 = _spad_row_offset_T_4 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_4_0 = spad_row_offset_4 < 9'h5 & {1'h0, spad_row_offset_4} + _GEN_4 > 10'h4; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_5 = _spad_row_offset_T_5 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_5_0 = spad_row_offset_5 < 9'h6 & {1'h0, spad_row_offset_5} + _GEN_4 > 10'h5; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_6 = _spad_row_offset_T_6 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_6_0 = spad_row_offset_6 < 9'h7 & {1'h0, spad_row_offset_6} + _GEN_4 > 10'h6; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_7 = _spad_row_offset_T_7 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_45 = {1'h0, spad_row_offset_7} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_7_0 = spad_row_offset_7 < 9'h8 & (|(_T_45[9:3])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_8 = _spad_row_offset_T_8 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_8_0 = spad_row_offset_8 < 9'h9 & {1'h0, spad_row_offset_8} + _GEN_4 > 10'h8; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_9 = _spad_row_offset_T_9 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_9_0 = spad_row_offset_9 < 9'hA & {1'h0, spad_row_offset_9} + _GEN_4 > 10'h9; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_10 = _spad_row_offset_T_10 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_10_0 = spad_row_offset_10 < 9'hB & {1'h0, spad_row_offset_10} + _GEN_4 > 10'hA; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_11 = _spad_row_offset_T_11 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_11_0 = spad_row_offset_11 < 9'hC & {1'h0, spad_row_offset_11} + _GEN_4 > 10'hB; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_12 = _spad_row_offset_T_12 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_12_0 = spad_row_offset_12 < 9'hD & {1'h0, spad_row_offset_12} + _GEN_4 > 10'hC; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_13 = _spad_row_offset_T_13 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_13_0 = spad_row_offset_13 < 9'hE & {1'h0, spad_row_offset_13} + _GEN_4 > 10'hD; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_14 = _spad_row_offset_T_14 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_14_0 = spad_row_offset_14 < 9'hF & {1'h0, spad_row_offset_14} + _GEN_4 > 10'hE; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_15 = _spad_row_offset_T_15 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_93 = {1'h0, spad_row_offset_15} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_15_0 = spad_row_offset_15 < 9'h10 & (|(_T_93[9:4])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_16 = _spad_row_offset_T_16 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_16_0 = spad_row_offset_16 < 9'h11 & {1'h0, spad_row_offset_16} + _GEN_4 > 10'h10; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_17 = _spad_row_offset_T_17 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_17_0 = spad_row_offset_17 < 9'h12 & {1'h0, spad_row_offset_17} + _GEN_4 > 10'h11; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_18 = _spad_row_offset_T_18 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_18_0 = spad_row_offset_18 < 9'h13 & {1'h0, spad_row_offset_18} + _GEN_4 > 10'h12; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_19 = _spad_row_offset_T_19 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_19_0 = spad_row_offset_19 < 9'h14 & {1'h0, spad_row_offset_19} + _GEN_4 > 10'h13; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_20 = _spad_row_offset_T_20 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_20_0 = spad_row_offset_20 < 9'h15 & {1'h0, spad_row_offset_20} + _GEN_4 > 10'h14; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_21 = _spad_row_offset_T_21 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_21_0 = spad_row_offset_21 < 9'h16 & {1'h0, spad_row_offset_21} + _GEN_4 > 10'h15; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_22 = _spad_row_offset_T_22 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_22_0 = spad_row_offset_22 < 9'h17 & {1'h0, spad_row_offset_22} + _GEN_4 > 10'h16; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_23 = _spad_row_offset_T_23 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_23_0 = spad_row_offset_23 < 9'h18 & {1'h0, spad_row_offset_23} + _GEN_4 > 10'h17; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_24 = _spad_row_offset_T_24 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_24_0 = spad_row_offset_24 < 9'h19 & {1'h0, spad_row_offset_24} + _GEN_4 > 10'h18; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_25 = _spad_row_offset_T_25 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_25_0 = spad_row_offset_25 < 9'h1A & {1'h0, spad_row_offset_25} + _GEN_4 > 10'h19; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_26 = _spad_row_offset_T_26 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_26_0 = spad_row_offset_26 < 9'h1B & {1'h0, spad_row_offset_26} + _GEN_4 > 10'h1A; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_27 = _spad_row_offset_T_27 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_27_0 = spad_row_offset_27 < 9'h1C & {1'h0, spad_row_offset_27} + _GEN_4 > 10'h1B; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_28 = _spad_row_offset_T_28 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_28_0 = spad_row_offset_28 < 9'h1D & {1'h0, spad_row_offset_28} + _GEN_4 > 10'h1C; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_29 = _spad_row_offset_T_29 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_29_0 = spad_row_offset_29 < 9'h1E & {1'h0, spad_row_offset_29} + _GEN_4 > 10'h1D; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_30 = _spad_row_offset_T_30 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_30_0 = spad_row_offset_30 < 9'h1F & {1'h0, spad_row_offset_30} + _GEN_4 > 10'h1E; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_31 = _spad_row_offset_T_31 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_189 = {1'h0, spad_row_offset_31} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_31_0 = spad_row_offset_31 < 9'h20 & (|(_T_189[9:5])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_32 = _spad_row_offset_T_32 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_32_0 = spad_row_offset_32 < 9'h21 & {1'h0, spad_row_offset_32} + _GEN_4 > 10'h20; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_33 = _spad_row_offset_T_33 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_33_0 = spad_row_offset_33 < 9'h22 & {1'h0, spad_row_offset_33} + _GEN_4 > 10'h21; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_34 = _spad_row_offset_T_34 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_34_0 = spad_row_offset_34 < 9'h23 & {1'h0, spad_row_offset_34} + _GEN_4 > 10'h22; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_35 = _spad_row_offset_T_35 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_35_0 = spad_row_offset_35 < 9'h24 & {1'h0, spad_row_offset_35} + _GEN_4 > 10'h23; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_36 = _spad_row_offset_T_36 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_36_0 = spad_row_offset_36 < 9'h25 & {1'h0, spad_row_offset_36} + _GEN_4 > 10'h24; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_37 = _spad_row_offset_T_37 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_37_0 = spad_row_offset_37 < 9'h26 & {1'h0, spad_row_offset_37} + _GEN_4 > 10'h25; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_38 = _spad_row_offset_T_38 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_38_0 = spad_row_offset_38 < 9'h27 & {1'h0, spad_row_offset_38} + _GEN_4 > 10'h26; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_39 = _spad_row_offset_T_39 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_39_0 = spad_row_offset_39 < 9'h28 & {1'h0, spad_row_offset_39} + _GEN_4 > 10'h27; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_40 = _spad_row_offset_T_40 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_40_0 = spad_row_offset_40 < 9'h29 & {1'h0, spad_row_offset_40} + _GEN_4 > 10'h28; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_41 = _spad_row_offset_T_41 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_41_0 = spad_row_offset_41 < 9'h2A & {1'h0, spad_row_offset_41} + _GEN_4 > 10'h29; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_42 = _spad_row_offset_T_42 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_42_0 = spad_row_offset_42 < 9'h2B & {1'h0, spad_row_offset_42} + _GEN_4 > 10'h2A; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_43 = _spad_row_offset_T_43 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_43_0 = spad_row_offset_43 < 9'h2C & {1'h0, spad_row_offset_43} + _GEN_4 > 10'h2B; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_44 = _spad_row_offset_T_44 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_44_0 = spad_row_offset_44 < 9'h2D & {1'h0, spad_row_offset_44} + _GEN_4 > 10'h2C; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_45 = _spad_row_offset_T_45 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_45_0 = spad_row_offset_45 < 9'h2E & {1'h0, spad_row_offset_45} + _GEN_4 > 10'h2D; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_46 = _spad_row_offset_T_46 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_46_0 = spad_row_offset_46 < 9'h2F & {1'h0, spad_row_offset_46} + _GEN_4 > 10'h2E; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_47 = _spad_row_offset_T_47 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_47_0 = spad_row_offset_47 < 9'h30 & {1'h0, spad_row_offset_47} + _GEN_4 > 10'h2F; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_48 = _spad_row_offset_T_48 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_48_0 = spad_row_offset_48 < 9'h31 & {1'h0, spad_row_offset_48} + _GEN_4 > 10'h30; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_49 = _spad_row_offset_T_49 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_49_0 = spad_row_offset_49 < 9'h32 & {1'h0, spad_row_offset_49} + _GEN_4 > 10'h31; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_50 = _spad_row_offset_T_50 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_50_0 = spad_row_offset_50 < 9'h33 & {1'h0, spad_row_offset_50} + _GEN_4 > 10'h32; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_51 = _spad_row_offset_T_51 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_51_0 = spad_row_offset_51 < 9'h34 & {1'h0, spad_row_offset_51} + _GEN_4 > 10'h33; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_52 = _spad_row_offset_T_52 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_52_0 = spad_row_offset_52 < 9'h35 & {1'h0, spad_row_offset_52} + _GEN_4 > 10'h34; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_53 = _spad_row_offset_T_53 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_53_0 = spad_row_offset_53 < 9'h36 & {1'h0, spad_row_offset_53} + _GEN_4 > 10'h35; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_54 = _spad_row_offset_T_54 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_54_0 = spad_row_offset_54 < 9'h37 & {1'h0, spad_row_offset_54} + _GEN_4 > 10'h36; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_55 = _spad_row_offset_T_55 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_55_0 = spad_row_offset_55 < 9'h38 & {1'h0, spad_row_offset_55} + _GEN_4 > 10'h37; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_56 = _spad_row_offset_T_56 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_56_0 = spad_row_offset_56 < 9'h39 & {1'h0, spad_row_offset_56} + _GEN_4 > 10'h38; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_57 = _spad_row_offset_T_57 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_57_0 = spad_row_offset_57 < 9'h3A & {1'h0, spad_row_offset_57} + _GEN_4 > 10'h39; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_58 = _spad_row_offset_T_58 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_58_0 = spad_row_offset_58 < 9'h3B & {1'h0, spad_row_offset_58} + _GEN_4 > 10'h3A; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_59 = _spad_row_offset_T_59 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_59_0 = spad_row_offset_59 < 9'h3C & {1'h0, spad_row_offset_59} + _GEN_4 > 10'h3B; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_60 = _spad_row_offset_T_60 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_60_0 = spad_row_offset_60 < 9'h3D & {1'h0, spad_row_offset_60} + _GEN_4 > 10'h3C; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_61 = _spad_row_offset_T_61 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_61_0 = spad_row_offset_61 < 9'h3E & {1'h0, spad_row_offset_61} + _GEN_4 > 10'h3D; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_62 = _spad_row_offset_T_62 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_62_0 = spad_row_offset_62 < 9'h3F & {1'h0, spad_row_offset_62} + _GEN_4 > 10'h3E; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_63 = _spad_row_offset_T_63 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_381 = {1'h0, spad_row_offset_63} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_63_0 = spad_row_offset_63 < 9'h40 & (|(_T_381[9:6])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [9:0] _io_out_bits_addr_total_bytes_sent_T = {1'h0, req_bits_spad_row_offset} + _GEN_1; // @[Util.scala:35:11] wire [8:0] io_out_bits_addr_total_bytes_sent = _io_out_bits_addr_total_bytes_sent_T[8:0]; // @[BeatMerger.scala:77:53] wire [8:0] _io_out_bits_addr_T = io_out_bits_addr_total_bytes_sent / 9'h40; // @[BeatMerger.scala:77:53, :82:84] wire [8:0] _io_out_bits_addr_T_1 = io_out_bits_addr_total_bytes_sent / 9'h10; // @[BeatMerger.scala:77:53, :83:85] wire [8:0] _io_out_bits_addr_T_2 = req_bits_has_acc_bitwidth ? _io_out_bits_addr_T : _io_out_bits_addr_T_1; // @[BeatMerger.scala:43:16, :78:8, :82:84, :83:85] wire [24:0] _io_out_bits_addr_T_3 = {9'h0, req_bits_block_stride} * {16'h0, _io_out_bits_addr_T_2}; // @[BeatMerger.scala:43:16, :76:61, :78:8] wire [25:0] _io_out_bits_addr_T_4 = {12'h0, req_bits_addr} + {1'h0, _io_out_bits_addr_T_3}; // @[BeatMerger.scala:43:16, :76:{37,61}] wire [24:0] _io_out_bits_addr_T_5 = _io_out_bits_addr_T_4[24:0]; // @[BeatMerger.scala:76:37] assign io_out_bits_addr_0 = _io_out_bits_addr_T_5[13:0]; // @[BeatMerger.scala:30:7, :76:{20,37}] wire _T_388 = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] wire _T_391 = last_sending & _GEN == _T_389; // @[BeatMerger.scala:52:71, :61:37, :62:42, :101:{24,37}] assign io_req_ready_0 = _T_388 & _T_391 | _io_req_ready_T; // @[Decoupled.scala:51:35] wire [6:0] current_bytesRead = _current_bytesRead_T ? 7'h0 : bytesRead; // @[Decoupled.scala:51:35] wire [6:0] current_bytesDiscarded = _current_bytesDiscarded_T ? 7'h0 : bytesDiscarded; // @[Decoupled.scala:51:35] wire [6:0] current_usefulBytesRead = _current_usefulBytesRead_T ? 7'h0 : usefulBytesRead; // @[Decoupled.scala:51:35] wire [5:0] current_shift = _current_shift_T ? io_req_bits_shift_0 : req_bits_shift; // @[Decoupled.scala:51:35] wire [2:0] current_lg_len_req = _current_lg_len_req_T ? io_req_bits_lg_len_req_0 : req_bits_lg_len_req; // @[Decoupled.scala:51:35] wire [7:0] current_len_req = 8'h1 << current_lg_len_req; // @[BeatMerger.scala:118:33, :119:32] wire [7:0] _rshift_T = {2'h0, current_shift} - {1'h0, current_bytesDiscarded}; // @[BeatMerger.scala:52:71, :115:37, :117:28, :121:25, :124:35] wire [6:0] _rshift_T_1 = _rshift_T[6:0]; // @[BeatMerger.scala:124:35] wire [10:0] rshift = {1'h0, _rshift_T_1, 3'h0}; // @[BeatMerger.scala:124:{35,61}] wire [10:0] lshift = {1'h0, current_usefulBytesRead, 3'h0}; // @[BeatMerger.scala:116:38, :125:44] wire [127:0] _GEN_5 = {117'h0, rshift}; // @[BeatMerger.scala:124:61, :126:41] wire [127:0] _mask_T_1 = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF >> _GEN_5; // @[BeatMerger.scala:126:41] wire [2174:0] _GEN_6 = {2164'h0, lshift}; // @[BeatMerger.scala:125:44, :126:52] wire [2174:0] _mask_T_2 = {2047'h0, _mask_T_1} << _GEN_6; // @[BeatMerger.scala:126:{41,52}] wire [2174:0] mask = ~_mask_T_2; // @[BeatMerger.scala:126:{19,52}] wire [2174:0] _buffer_T = {1663'h0, mask[511:0] & buffer}; // @[BeatMerger.scala:46:19, :126:19, :128:25] wire [127:0] _buffer_T_1 = io_in_bits_0 >> _GEN_5; // @[BeatMerger.scala:30:7, :126:41, :128:48] wire [2174:0] _buffer_T_2 = {2047'h0, _buffer_T_1} << _GEN_6; // @[BeatMerger.scala:126:52, :128:{48,59}] wire [2174:0] _buffer_T_3 = _buffer_T | _buffer_T_2; // @[BeatMerger.scala:128:{25,33,59}] wire [7:0] _GEN_7 = {1'h0, current_bytesRead} + 8'h10; // @[Util.scala:35:11] wire [7:0] _bytesRead_T; // @[Util.scala:35:11] assign _bytesRead_T = _GEN_7; // @[Util.scala:35:11] wire [7:0] _bytesRead_T_2; // @[Util.scala:35:30] assign _bytesRead_T_2 = _GEN_7; // @[Util.scala:35:{11,30}] wire _bytesRead_T_1 = _bytesRead_T > current_len_req; // @[Util.scala:35:{11,16}] wire [6:0] _bytesRead_T_3 = _bytesRead_T_2[6:0]; // @[Util.scala:35:30] wire [7:0] _bytesRead_T_4 = _bytesRead_T_1 ? current_len_req : {1'h0, _bytesRead_T_3}; // @[Util.scala:35:{8,16,30}] wire _T_399 = bytesSent == req_bits_bytes_to_read; // @[BeatMerger.scala:43:16, :50:22, :94:15] wire _T_387 = _GEN == _T_389 & _T_399; // @[BeatMerger.scala:52:71, :62:42, :93:{19,59}, :94:15] wire _T_393 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[BeatMerger.scala:30:7] req_valid <= ~(reset | _T_393 & ~_T_397 & _T_399 & last_reading) & (_T_397 | (_T_388 ? ~(_T_391 | _T_387) & req_valid : ~_T_387 & req_valid)); // @[Decoupled.scala:51:35] if (_T_397) begin // @[Decoupled.scala:51:35] req_bits_shift <= io_req_bits_shift_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_addr <= io_req_bits_addr_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_is_acc <= io_req_bits_is_acc_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_accumulate <= io_req_bits_accumulate_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_has_acc_bitwidth <= io_req_bits_has_acc_bitwidth_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_scale <= io_req_bits_scale_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_repeats <= io_req_bits_repeats_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_pixel_repeats <= io_req_bits_pixel_repeats_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_len <= io_req_bits_len_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_block_stride <= io_req_bits_block_stride_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_spad_row_offset <= io_req_bits_spad_row_offset_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_lg_len_req <= io_req_bits_lg_len_req_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_bytes_to_read <= io_req_bits_bytes_to_read_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_cmd_id <= io_req_bits_cmd_id_0; // @[BeatMerger.scala:30:7, :43:16] bytesSent <= 7'h0; // @[BeatMerger.scala:50:22] end else if (_T_388) // @[Decoupled.scala:51:35] bytesSent <= bytesSent_next[6:0]; // @[Util.scala:35:8] if (_T_393 & _rshift_T[6:0] < 7'h11) // @[Decoupled.scala:51:35] buffer <= _buffer_T_3[511:0]; // @[BeatMerger.scala:46:19, :128:{14,33}] if (_T_393) // @[Decoupled.scala:51:35] bytesRead <= _bytesRead_T_4[6:0]; // @[Util.scala:35:8] else if (_T_397) // @[Decoupled.scala:51:35] bytesRead <= 7'h0; // @[BeatMerger.scala:51:22] always @(posedge) assign io_req_ready = io_req_ready_0; // @[BeatMerger.scala:30:7] assign io_in_ready = io_in_ready_0; // @[BeatMerger.scala:30:7] assign io_out_valid = io_out_valid_0; // @[BeatMerger.scala:30:7] assign io_out_bits_data = io_out_bits_data_0; // @[BeatMerger.scala:30:7] assign io_out_bits_addr = io_out_bits_addr_0; // @[BeatMerger.scala:30:7] assign io_out_bits_is_acc = io_out_bits_is_acc_0; // @[BeatMerger.scala:30:7] assign io_out_bits_accumulate = io_out_bits_accumulate_0; // @[BeatMerger.scala:30:7] assign io_out_bits_has_acc_bitwidth = io_out_bits_has_acc_bitwidth_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_0 = io_out_bits_mask_0_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_1 = io_out_bits_mask_1_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_2 = io_out_bits_mask_2_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_3 = io_out_bits_mask_3_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_4 = io_out_bits_mask_4_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_5 = io_out_bits_mask_5_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_6 = io_out_bits_mask_6_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_7 = io_out_bits_mask_7_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_8 = io_out_bits_mask_8_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_9 = io_out_bits_mask_9_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_10 = io_out_bits_mask_10_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_11 = io_out_bits_mask_11_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_12 = io_out_bits_mask_12_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_13 = io_out_bits_mask_13_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_14 = io_out_bits_mask_14_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_15 = io_out_bits_mask_15_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_16 = io_out_bits_mask_16_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_17 = io_out_bits_mask_17_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_18 = io_out_bits_mask_18_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_19 = io_out_bits_mask_19_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_20 = io_out_bits_mask_20_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_21 = io_out_bits_mask_21_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_22 = io_out_bits_mask_22_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_23 = io_out_bits_mask_23_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_24 = io_out_bits_mask_24_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_25 = io_out_bits_mask_25_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_26 = io_out_bits_mask_26_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_27 = io_out_bits_mask_27_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_28 = io_out_bits_mask_28_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_29 = io_out_bits_mask_29_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_30 = io_out_bits_mask_30_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_31 = io_out_bits_mask_31_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_32 = io_out_bits_mask_32_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_33 = io_out_bits_mask_33_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_34 = io_out_bits_mask_34_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_35 = io_out_bits_mask_35_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_36 = io_out_bits_mask_36_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_37 = io_out_bits_mask_37_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_38 = io_out_bits_mask_38_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_39 = io_out_bits_mask_39_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_40 = io_out_bits_mask_40_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_41 = io_out_bits_mask_41_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_42 = io_out_bits_mask_42_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_43 = io_out_bits_mask_43_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_44 = io_out_bits_mask_44_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_45 = io_out_bits_mask_45_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_46 = io_out_bits_mask_46_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_47 = io_out_bits_mask_47_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_48 = io_out_bits_mask_48_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_49 = io_out_bits_mask_49_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_50 = io_out_bits_mask_50_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_51 = io_out_bits_mask_51_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_52 = io_out_bits_mask_52_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_53 = io_out_bits_mask_53_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_54 = io_out_bits_mask_54_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_55 = io_out_bits_mask_55_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_56 = io_out_bits_mask_56_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_57 = io_out_bits_mask_57_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_58 = io_out_bits_mask_58_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_59 = io_out_bits_mask_59_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_60 = io_out_bits_mask_60_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_61 = io_out_bits_mask_61_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_62 = io_out_bits_mask_62_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_63 = io_out_bits_mask_63_0; // @[BeatMerger.scala:30:7] assign io_out_bits_last = io_out_bits_last_0; // @[BeatMerger.scala:30:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_281 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_281( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_78 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_118 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_78( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_118 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueUnitCollapsing_4 : input clock : Clock input reset : Reset output io : { flip dis_uops : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3], iss_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[1], flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>, flip fu_types : UInt<1>[10][1], flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip flush_pipeline : UInt<1>, flip squash_grant : UInt<1>, flip tsc_reg : UInt<64>} wire _WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} wire _WIRE_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} wire _WIRE_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect _WIRE, io.dis_uops[0].bits connect _WIRE.iw_issued, UInt<1>(0h0) connect _WIRE.iw_issued_partial_agen, UInt<1>(0h0) connect _WIRE.iw_issued_partial_dgen, UInt<1>(0h0) connect _WIRE.iw_p1_bypass_hint, UInt<1>(0h0) connect _WIRE.iw_p2_bypass_hint, UInt<1>(0h0) connect _WIRE.iw_p3_bypass_hint, UInt<1>(0h0) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs1) node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[0].bits.prs1) node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[0].bits.prs1) node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[0].bits.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs2) node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[0].bits.prs2) node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[0].bits.prs2) node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[0].bits.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs3) node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[0].bits.prs3) node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[0].bits.prs3) node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[0].bits.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4) node _T = or(prs1_wakeups_0, prs1_wakeups_1) node _T_1 = or(_T, prs1_wakeups_2) node _T_2 = or(_T_1, prs1_wakeups_3) node _T_3 = or(_T_2, prs1_wakeups_4) when _T_3 : connect _WIRE.prs1_busy, UInt<1>(0h0) node _T_4 = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_5 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_6 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _T_7 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _T_8 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _T_9 = or(_T_4, _T_5) node _T_10 = or(_T_9, _T_6) node _T_11 = or(_T_10, _T_7) node _T_12 = or(_T_11, _T_8) wire _WIRE_3 : UInt<3> connect _WIRE_3, _T_12 connect _WIRE.iw_p1_speculative_child, _WIRE_3 node _T_13 = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_14 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_15 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_16 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_17 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_18 = or(_T_13, _T_14) node _T_19 = or(_T_18, _T_15) node _T_20 = or(_T_19, _T_16) node _T_21 = or(_T_20, _T_17) wire _WIRE_4 : UInt<1> connect _WIRE_4, _T_21 connect _WIRE.iw_p1_bypass_hint, _WIRE_4 node _T_22 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_23 = or(_T_22, prs1_rebusys_2) node _T_24 = or(_T_23, prs1_rebusys_3) node _T_25 = or(_T_24, prs1_rebusys_4) node _T_26 = and(io.child_rebusys, io.dis_uops[0].bits.iw_p1_speculative_child) node _T_27 = neq(_T_26, UInt<1>(0h0)) node _T_28 = or(_T_25, _T_27) when _T_28 : node _T_29 = eq(io.dis_uops[0].bits.lrs1_rtype, UInt<2>(0h0)) connect _WIRE.prs1_busy, _T_29 node _T_30 = or(prs2_wakeups_0, prs2_wakeups_1) node _T_31 = or(_T_30, prs2_wakeups_2) node _T_32 = or(_T_31, prs2_wakeups_3) node _T_33 = or(_T_32, prs2_wakeups_4) when _T_33 : connect _WIRE.prs2_busy, UInt<1>(0h0) node _T_34 = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_35 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_36 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _T_37 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _T_38 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _T_39 = or(_T_34, _T_35) node _T_40 = or(_T_39, _T_36) node _T_41 = or(_T_40, _T_37) node _T_42 = or(_T_41, _T_38) wire _WIRE_5 : UInt<3> connect _WIRE_5, _T_42 connect _WIRE.iw_p2_speculative_child, _WIRE_5 node _T_43 = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_44 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_45 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_46 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_47 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_48 = or(_T_43, _T_44) node _T_49 = or(_T_48, _T_45) node _T_50 = or(_T_49, _T_46) node _T_51 = or(_T_50, _T_47) wire _WIRE_6 : UInt<1> connect _WIRE_6, _T_51 connect _WIRE.iw_p2_bypass_hint, _WIRE_6 node _T_52 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_53 = or(_T_52, prs2_rebusys_2) node _T_54 = or(_T_53, prs2_rebusys_3) node _T_55 = or(_T_54, prs2_rebusys_4) node _T_56 = and(io.child_rebusys, io.dis_uops[0].bits.iw_p2_speculative_child) node _T_57 = neq(_T_56, UInt<1>(0h0)) node _T_58 = or(_T_55, _T_57) when _T_58 : node _T_59 = eq(io.dis_uops[0].bits.lrs2_rtype, UInt<2>(0h0)) connect _WIRE.prs2_busy, _T_59 node _T_60 = or(prs3_wakeups_0, prs3_wakeups_1) node _T_61 = or(_T_60, prs3_wakeups_2) node _T_62 = or(_T_61, prs3_wakeups_3) node _T_63 = or(_T_62, prs3_wakeups_4) when _T_63 : connect _WIRE.prs3_busy, UInt<1>(0h0) node _T_64 = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_65 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_66 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_67 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_68 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_69 = or(_T_64, _T_65) node _T_70 = or(_T_69, _T_66) node _T_71 = or(_T_70, _T_67) node _T_72 = or(_T_71, _T_68) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_72 connect _WIRE.iw_p3_bypass_hint, _WIRE_7 node _T_73 = eq(io.pred_wakeup_port.bits, io.dis_uops[0].bits.ppred) node _T_74 = and(io.pred_wakeup_port.valid, _T_73) when _T_74 : connect _WIRE.ppred_busy, UInt<1>(0h0) connect _WIRE_1, io.dis_uops[1].bits connect _WIRE_1.iw_issued, UInt<1>(0h0) connect _WIRE_1.iw_issued_partial_agen, UInt<1>(0h0) connect _WIRE_1.iw_issued_partial_dgen, UInt<1>(0h0) connect _WIRE_1.iw_p1_bypass_hint, UInt<1>(0h0) connect _WIRE_1.iw_p2_bypass_hint, UInt<1>(0h0) connect _WIRE_1.iw_p3_bypass_hint, UInt<1>(0h0) node prs1_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs1) node prs1_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs1) node prs1_matches_2_1 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[1].bits.prs1) node prs1_matches_3_1 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[1].bits.prs1) node prs1_matches_4_1 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[1].bits.prs1) node prs2_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs2) node prs2_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs2) node prs2_matches_2_1 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[1].bits.prs2) node prs2_matches_3_1 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[1].bits.prs2) node prs2_matches_4_1 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[1].bits.prs2) node prs3_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs3) node prs3_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs3) node prs3_matches_2_1 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[1].bits.prs3) node prs3_matches_3_1 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[1].bits.prs3) node prs3_matches_4_1 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[1].bits.prs3) node prs1_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs1_matches_0_1) node prs1_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs1_matches_1_1) node prs1_wakeups_2_1 = and(io.wakeup_ports[2].valid, prs1_matches_2_1) node prs1_wakeups_3_1 = and(io.wakeup_ports[3].valid, prs1_matches_3_1) node prs1_wakeups_4_1 = and(io.wakeup_ports[4].valid, prs1_matches_4_1) node prs2_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs2_matches_0_1) node prs2_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs2_matches_1_1) node prs2_wakeups_2_1 = and(io.wakeup_ports[2].valid, prs2_matches_2_1) node prs2_wakeups_3_1 = and(io.wakeup_ports[3].valid, prs2_matches_3_1) node prs2_wakeups_4_1 = and(io.wakeup_ports[4].valid, prs2_matches_4_1) node prs3_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs3_matches_0_1) node prs3_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs3_matches_1_1) node prs3_wakeups_2_1 = and(io.wakeup_ports[2].valid, prs3_matches_2_1) node prs3_wakeups_3_1 = and(io.wakeup_ports[3].valid, prs3_matches_3_1) node prs3_wakeups_4_1 = and(io.wakeup_ports[4].valid, prs3_matches_4_1) node prs1_rebusys_0_1 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0_1) node prs1_rebusys_1_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1_1) node prs1_rebusys_2_1 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2_1) node prs1_rebusys_3_1 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3_1) node prs1_rebusys_4_1 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4_1) node prs2_rebusys_0_1 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0_1) node prs2_rebusys_1_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1_1) node prs2_rebusys_2_1 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2_1) node prs2_rebusys_3_1 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3_1) node prs2_rebusys_4_1 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4_1) node _T_75 = or(prs1_wakeups_0_1, prs1_wakeups_1_1) node _T_76 = or(_T_75, prs1_wakeups_2_1) node _T_77 = or(_T_76, prs1_wakeups_3_1) node _T_78 = or(_T_77, prs1_wakeups_4_1) when _T_78 : connect _WIRE_1.prs1_busy, UInt<1>(0h0) node _T_79 = mux(prs1_wakeups_0_1, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_80 = mux(prs1_wakeups_1_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_81 = mux(prs1_wakeups_2_1, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _T_82 = mux(prs1_wakeups_3_1, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _T_83 = mux(prs1_wakeups_4_1, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _T_84 = or(_T_79, _T_80) node _T_85 = or(_T_84, _T_81) node _T_86 = or(_T_85, _T_82) node _T_87 = or(_T_86, _T_83) wire _WIRE_8 : UInt<3> connect _WIRE_8, _T_87 connect _WIRE_1.iw_p1_speculative_child, _WIRE_8 node _T_88 = mux(prs1_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_89 = mux(prs1_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_90 = mux(prs1_wakeups_2_1, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_91 = mux(prs1_wakeups_3_1, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_92 = mux(prs1_wakeups_4_1, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_93 = or(_T_88, _T_89) node _T_94 = or(_T_93, _T_90) node _T_95 = or(_T_94, _T_91) node _T_96 = or(_T_95, _T_92) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_96 connect _WIRE_1.iw_p1_bypass_hint, _WIRE_9 node _T_97 = or(prs1_rebusys_0_1, prs1_rebusys_1_1) node _T_98 = or(_T_97, prs1_rebusys_2_1) node _T_99 = or(_T_98, prs1_rebusys_3_1) node _T_100 = or(_T_99, prs1_rebusys_4_1) node _T_101 = and(io.child_rebusys, io.dis_uops[1].bits.iw_p1_speculative_child) node _T_102 = neq(_T_101, UInt<1>(0h0)) node _T_103 = or(_T_100, _T_102) when _T_103 : node _T_104 = eq(io.dis_uops[1].bits.lrs1_rtype, UInt<2>(0h0)) connect _WIRE_1.prs1_busy, _T_104 node _T_105 = or(prs2_wakeups_0_1, prs2_wakeups_1_1) node _T_106 = or(_T_105, prs2_wakeups_2_1) node _T_107 = or(_T_106, prs2_wakeups_3_1) node _T_108 = or(_T_107, prs2_wakeups_4_1) when _T_108 : connect _WIRE_1.prs2_busy, UInt<1>(0h0) node _T_109 = mux(prs2_wakeups_0_1, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_110 = mux(prs2_wakeups_1_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_111 = mux(prs2_wakeups_2_1, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _T_112 = mux(prs2_wakeups_3_1, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _T_113 = mux(prs2_wakeups_4_1, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _T_114 = or(_T_109, _T_110) node _T_115 = or(_T_114, _T_111) node _T_116 = or(_T_115, _T_112) node _T_117 = or(_T_116, _T_113) wire _WIRE_10 : UInt<3> connect _WIRE_10, _T_117 connect _WIRE_1.iw_p2_speculative_child, _WIRE_10 node _T_118 = mux(prs2_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_119 = mux(prs2_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_120 = mux(prs2_wakeups_2_1, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_121 = mux(prs2_wakeups_3_1, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_122 = mux(prs2_wakeups_4_1, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_123 = or(_T_118, _T_119) node _T_124 = or(_T_123, _T_120) node _T_125 = or(_T_124, _T_121) node _T_126 = or(_T_125, _T_122) wire _WIRE_11 : UInt<1> connect _WIRE_11, _T_126 connect _WIRE_1.iw_p2_bypass_hint, _WIRE_11 node _T_127 = or(prs2_rebusys_0_1, prs2_rebusys_1_1) node _T_128 = or(_T_127, prs2_rebusys_2_1) node _T_129 = or(_T_128, prs2_rebusys_3_1) node _T_130 = or(_T_129, prs2_rebusys_4_1) node _T_131 = and(io.child_rebusys, io.dis_uops[1].bits.iw_p2_speculative_child) node _T_132 = neq(_T_131, UInt<1>(0h0)) node _T_133 = or(_T_130, _T_132) when _T_133 : node _T_134 = eq(io.dis_uops[1].bits.lrs2_rtype, UInt<2>(0h0)) connect _WIRE_1.prs2_busy, _T_134 node _T_135 = or(prs3_wakeups_0_1, prs3_wakeups_1_1) node _T_136 = or(_T_135, prs3_wakeups_2_1) node _T_137 = or(_T_136, prs3_wakeups_3_1) node _T_138 = or(_T_137, prs3_wakeups_4_1) when _T_138 : connect _WIRE_1.prs3_busy, UInt<1>(0h0) node _T_139 = mux(prs3_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_140 = mux(prs3_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_141 = mux(prs3_wakeups_2_1, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_142 = mux(prs3_wakeups_3_1, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_143 = mux(prs3_wakeups_4_1, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_144 = or(_T_139, _T_140) node _T_145 = or(_T_144, _T_141) node _T_146 = or(_T_145, _T_142) node _T_147 = or(_T_146, _T_143) wire _WIRE_12 : UInt<1> connect _WIRE_12, _T_147 connect _WIRE_1.iw_p3_bypass_hint, _WIRE_12 node _T_148 = eq(io.pred_wakeup_port.bits, io.dis_uops[1].bits.ppred) node _T_149 = and(io.pred_wakeup_port.valid, _T_148) when _T_149 : connect _WIRE_1.ppred_busy, UInt<1>(0h0) connect _WIRE_2, io.dis_uops[2].bits connect _WIRE_2.iw_issued, UInt<1>(0h0) connect _WIRE_2.iw_issued_partial_agen, UInt<1>(0h0) connect _WIRE_2.iw_issued_partial_dgen, UInt<1>(0h0) connect _WIRE_2.iw_p1_bypass_hint, UInt<1>(0h0) connect _WIRE_2.iw_p2_bypass_hint, UInt<1>(0h0) connect _WIRE_2.iw_p3_bypass_hint, UInt<1>(0h0) node prs1_matches_0_2 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[2].bits.prs1) node prs1_matches_1_2 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[2].bits.prs1) node prs1_matches_2_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[2].bits.prs1) node prs1_matches_3_2 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[2].bits.prs1) node prs1_matches_4_2 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[2].bits.prs1) node prs2_matches_0_2 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[2].bits.prs2) node prs2_matches_1_2 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[2].bits.prs2) node prs2_matches_2_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[2].bits.prs2) node prs2_matches_3_2 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[2].bits.prs2) node prs2_matches_4_2 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[2].bits.prs2) node prs3_matches_0_2 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[2].bits.prs3) node prs3_matches_1_2 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[2].bits.prs3) node prs3_matches_2_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[2].bits.prs3) node prs3_matches_3_2 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[2].bits.prs3) node prs3_matches_4_2 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[2].bits.prs3) node prs1_wakeups_0_2 = and(io.wakeup_ports[0].valid, prs1_matches_0_2) node prs1_wakeups_1_2 = and(io.wakeup_ports[1].valid, prs1_matches_1_2) node prs1_wakeups_2_2 = and(io.wakeup_ports[2].valid, prs1_matches_2_2) node prs1_wakeups_3_2 = and(io.wakeup_ports[3].valid, prs1_matches_3_2) node prs1_wakeups_4_2 = and(io.wakeup_ports[4].valid, prs1_matches_4_2) node prs2_wakeups_0_2 = and(io.wakeup_ports[0].valid, prs2_matches_0_2) node prs2_wakeups_1_2 = and(io.wakeup_ports[1].valid, prs2_matches_1_2) node prs2_wakeups_2_2 = and(io.wakeup_ports[2].valid, prs2_matches_2_2) node prs2_wakeups_3_2 = and(io.wakeup_ports[3].valid, prs2_matches_3_2) node prs2_wakeups_4_2 = and(io.wakeup_ports[4].valid, prs2_matches_4_2) node prs3_wakeups_0_2 = and(io.wakeup_ports[0].valid, prs3_matches_0_2) node prs3_wakeups_1_2 = and(io.wakeup_ports[1].valid, prs3_matches_1_2) node prs3_wakeups_2_2 = and(io.wakeup_ports[2].valid, prs3_matches_2_2) node prs3_wakeups_3_2 = and(io.wakeup_ports[3].valid, prs3_matches_3_2) node prs3_wakeups_4_2 = and(io.wakeup_ports[4].valid, prs3_matches_4_2) node prs1_rebusys_0_2 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0_2) node prs1_rebusys_1_2 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1_2) node prs1_rebusys_2_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2_2) node prs1_rebusys_3_2 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3_2) node prs1_rebusys_4_2 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4_2) node prs2_rebusys_0_2 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0_2) node prs2_rebusys_1_2 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1_2) node prs2_rebusys_2_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2_2) node prs2_rebusys_3_2 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3_2) node prs2_rebusys_4_2 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4_2) node _T_150 = or(prs1_wakeups_0_2, prs1_wakeups_1_2) node _T_151 = or(_T_150, prs1_wakeups_2_2) node _T_152 = or(_T_151, prs1_wakeups_3_2) node _T_153 = or(_T_152, prs1_wakeups_4_2) when _T_153 : connect _WIRE_2.prs1_busy, UInt<1>(0h0) node _T_154 = mux(prs1_wakeups_0_2, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_155 = mux(prs1_wakeups_1_2, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_156 = mux(prs1_wakeups_2_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _T_157 = mux(prs1_wakeups_3_2, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _T_158 = mux(prs1_wakeups_4_2, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _T_159 = or(_T_154, _T_155) node _T_160 = or(_T_159, _T_156) node _T_161 = or(_T_160, _T_157) node _T_162 = or(_T_161, _T_158) wire _WIRE_13 : UInt<3> connect _WIRE_13, _T_162 connect _WIRE_2.iw_p1_speculative_child, _WIRE_13 node _T_163 = mux(prs1_wakeups_0_2, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_164 = mux(prs1_wakeups_1_2, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_165 = mux(prs1_wakeups_2_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_166 = mux(prs1_wakeups_3_2, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_167 = mux(prs1_wakeups_4_2, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_168 = or(_T_163, _T_164) node _T_169 = or(_T_168, _T_165) node _T_170 = or(_T_169, _T_166) node _T_171 = or(_T_170, _T_167) wire _WIRE_14 : UInt<1> connect _WIRE_14, _T_171 connect _WIRE_2.iw_p1_bypass_hint, _WIRE_14 node _T_172 = or(prs1_rebusys_0_2, prs1_rebusys_1_2) node _T_173 = or(_T_172, prs1_rebusys_2_2) node _T_174 = or(_T_173, prs1_rebusys_3_2) node _T_175 = or(_T_174, prs1_rebusys_4_2) node _T_176 = and(io.child_rebusys, io.dis_uops[2].bits.iw_p1_speculative_child) node _T_177 = neq(_T_176, UInt<1>(0h0)) node _T_178 = or(_T_175, _T_177) when _T_178 : node _T_179 = eq(io.dis_uops[2].bits.lrs1_rtype, UInt<2>(0h0)) connect _WIRE_2.prs1_busy, _T_179 node _T_180 = or(prs2_wakeups_0_2, prs2_wakeups_1_2) node _T_181 = or(_T_180, prs2_wakeups_2_2) node _T_182 = or(_T_181, prs2_wakeups_3_2) node _T_183 = or(_T_182, prs2_wakeups_4_2) when _T_183 : connect _WIRE_2.prs2_busy, UInt<1>(0h0) node _T_184 = mux(prs2_wakeups_0_2, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_185 = mux(prs2_wakeups_1_2, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_186 = mux(prs2_wakeups_2_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _T_187 = mux(prs2_wakeups_3_2, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _T_188 = mux(prs2_wakeups_4_2, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _T_189 = or(_T_184, _T_185) node _T_190 = or(_T_189, _T_186) node _T_191 = or(_T_190, _T_187) node _T_192 = or(_T_191, _T_188) wire _WIRE_15 : UInt<3> connect _WIRE_15, _T_192 connect _WIRE_2.iw_p2_speculative_child, _WIRE_15 node _T_193 = mux(prs2_wakeups_0_2, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_194 = mux(prs2_wakeups_1_2, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_195 = mux(prs2_wakeups_2_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_196 = mux(prs2_wakeups_3_2, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_197 = mux(prs2_wakeups_4_2, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_198 = or(_T_193, _T_194) node _T_199 = or(_T_198, _T_195) node _T_200 = or(_T_199, _T_196) node _T_201 = or(_T_200, _T_197) wire _WIRE_16 : UInt<1> connect _WIRE_16, _T_201 connect _WIRE_2.iw_p2_bypass_hint, _WIRE_16 node _T_202 = or(prs2_rebusys_0_2, prs2_rebusys_1_2) node _T_203 = or(_T_202, prs2_rebusys_2_2) node _T_204 = or(_T_203, prs2_rebusys_3_2) node _T_205 = or(_T_204, prs2_rebusys_4_2) node _T_206 = and(io.child_rebusys, io.dis_uops[2].bits.iw_p2_speculative_child) node _T_207 = neq(_T_206, UInt<1>(0h0)) node _T_208 = or(_T_205, _T_207) when _T_208 : node _T_209 = eq(io.dis_uops[2].bits.lrs2_rtype, UInt<2>(0h0)) connect _WIRE_2.prs2_busy, _T_209 node _T_210 = or(prs3_wakeups_0_2, prs3_wakeups_1_2) node _T_211 = or(_T_210, prs3_wakeups_2_2) node _T_212 = or(_T_211, prs3_wakeups_3_2) node _T_213 = or(_T_212, prs3_wakeups_4_2) when _T_213 : connect _WIRE_2.prs3_busy, UInt<1>(0h0) node _T_214 = mux(prs3_wakeups_0_2, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_215 = mux(prs3_wakeups_1_2, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_216 = mux(prs3_wakeups_2_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_217 = mux(prs3_wakeups_3_2, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_218 = mux(prs3_wakeups_4_2, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_219 = or(_T_214, _T_215) node _T_220 = or(_T_219, _T_216) node _T_221 = or(_T_220, _T_217) node _T_222 = or(_T_221, _T_218) wire _WIRE_17 : UInt<1> connect _WIRE_17, _T_222 connect _WIRE_2.iw_p3_bypass_hint, _WIRE_17 node _T_223 = eq(io.pred_wakeup_port.bits, io.dis_uops[2].bits.ppred) node _T_224 = and(io.pred_wakeup_port.valid, _T_223) when _T_224 : connect _WIRE_2.ppred_busy, UInt<1>(0h0) inst slots_0 of IssueSlot_72 connect slots_0.clock, clock connect slots_0.reset, reset inst slots_1 of IssueSlot_73 connect slots_1.clock, clock connect slots_1.reset, reset inst slots_2 of IssueSlot_74 connect slots_2.clock, clock connect slots_2.reset, reset inst slots_3 of IssueSlot_75 connect slots_3.clock, clock connect slots_3.reset, reset inst slots_4 of IssueSlot_76 connect slots_4.clock, clock connect slots_4.reset, reset inst slots_5 of IssueSlot_77 connect slots_5.clock, clock connect slots_5.reset, reset inst slots_6 of IssueSlot_78 connect slots_6.clock, clock connect slots_6.reset, reset inst slots_7 of IssueSlot_79 connect slots_7.clock, clock connect slots_7.reset, reset inst slots_8 of IssueSlot_80 connect slots_8.clock, clock connect slots_8.reset, reset inst slots_9 of IssueSlot_81 connect slots_9.clock, clock connect slots_9.reset, reset inst slots_10 of IssueSlot_82 connect slots_10.clock, clock connect slots_10.reset, reset inst slots_11 of IssueSlot_83 connect slots_11.clock, clock connect slots_11.reset, reset inst slots_12 of IssueSlot_84 connect slots_12.clock, clock connect slots_12.reset, reset inst slots_13 of IssueSlot_85 connect slots_13.clock, clock connect slots_13.reset, reset inst slots_14 of IssueSlot_86 connect slots_14.clock, clock connect slots_14.reset, reset inst slots_15 of IssueSlot_87 connect slots_15.clock, clock connect slots_15.reset, reset wire issue_slots : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>}[16] connect slots_0.io.child_rebusys, issue_slots[0].child_rebusys connect slots_0.io.pred_wakeup_port.bits, issue_slots[0].pred_wakeup_port.bits connect slots_0.io.pred_wakeup_port.valid, issue_slots[0].pred_wakeup_port.valid connect slots_0.io.wakeup_ports[0].bits.rebusy, issue_slots[0].wakeup_ports[0].bits.rebusy connect slots_0.io.wakeup_ports[0].bits.speculative_mask, issue_slots[0].wakeup_ports[0].bits.speculative_mask connect slots_0.io.wakeup_ports[0].bits.bypassable, issue_slots[0].wakeup_ports[0].bits.bypassable connect slots_0.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[0].bits.uop.debug_tsrc connect slots_0.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[0].bits.uop.debug_fsrc connect slots_0.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_0.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[0].bits.uop.bp_debug_if connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_0.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[0].wakeup_ports[0].bits.uop.fp_typ connect slots_0.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[0].wakeup_ports[0].bits.uop.fp_rm connect slots_0.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[0].wakeup_ports[0].bits.uop.fp_val connect slots_0.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[0].wakeup_ports[0].bits.uop.fcn_op connect slots_0.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[0].bits.uop.fcn_dw connect slots_0.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[0].wakeup_ports[0].bits.uop.frs3_en connect slots_0.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_0.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_0.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[0].bits.uop.dst_rtype connect slots_0.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[0].wakeup_ports[0].bits.uop.lrs3 connect slots_0.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[0].wakeup_ports[0].bits.uop.lrs2 connect slots_0.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[0].wakeup_ports[0].bits.uop.lrs1 connect slots_0.io.wakeup_ports[0].bits.uop.ldst, issue_slots[0].wakeup_ports[0].bits.uop.ldst connect slots_0.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_0.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[0].bits.uop.csr_cmd connect slots_0.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[0].bits.uop.flush_on_commit connect slots_0.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[0].wakeup_ports[0].bits.uop.is_unique connect slots_0.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[0].wakeup_ports[0].bits.uop.uses_stq connect slots_0.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[0].bits.uop.uses_ldq connect slots_0.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[0].wakeup_ports[0].bits.uop.mem_signed connect slots_0.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[0].wakeup_ports[0].bits.uop.mem_size connect slots_0.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[0].bits.uop.mem_cmd connect slots_0.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[0].wakeup_ports[0].bits.uop.exc_cause connect slots_0.io.wakeup_ports[0].bits.uop.exception, issue_slots[0].wakeup_ports[0].bits.uop.exception connect slots_0.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[0].bits.uop.stale_pdst connect slots_0.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[0].bits.uop.ppred_busy connect slots_0.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs3_busy connect slots_0.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs2_busy connect slots_0.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs1_busy connect slots_0.io.wakeup_ports[0].bits.uop.ppred, issue_slots[0].wakeup_ports[0].bits.uop.ppred connect slots_0.io.wakeup_ports[0].bits.uop.prs3, issue_slots[0].wakeup_ports[0].bits.uop.prs3 connect slots_0.io.wakeup_ports[0].bits.uop.prs2, issue_slots[0].wakeup_ports[0].bits.uop.prs2 connect slots_0.io.wakeup_ports[0].bits.uop.prs1, issue_slots[0].wakeup_ports[0].bits.uop.prs1 connect slots_0.io.wakeup_ports[0].bits.uop.pdst, issue_slots[0].wakeup_ports[0].bits.uop.pdst connect slots_0.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[0].bits.uop.rxq_idx connect slots_0.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[0].wakeup_ports[0].bits.uop.stq_idx connect slots_0.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[0].bits.uop.ldq_idx connect slots_0.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[0].wakeup_ports[0].bits.uop.rob_idx connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_0.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[0].wakeup_ports[0].bits.uop.op2_sel connect slots_0.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[0].wakeup_ports[0].bits.uop.op1_sel connect slots_0.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[0].wakeup_ports[0].bits.uop.imm_packed connect slots_0.io.wakeup_ports[0].bits.uop.pimm, issue_slots[0].wakeup_ports[0].bits.uop.pimm connect slots_0.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[0].wakeup_ports[0].bits.uop.imm_sel connect slots_0.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[0].wakeup_ports[0].bits.uop.imm_rename connect slots_0.io.wakeup_ports[0].bits.uop.taken, issue_slots[0].wakeup_ports[0].bits.uop.taken connect slots_0.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[0].wakeup_ports[0].bits.uop.pc_lob connect slots_0.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[0].wakeup_ports[0].bits.uop.edge_inst connect slots_0.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[0].bits.uop.ftq_idx connect slots_0.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[0].wakeup_ports[0].bits.uop.is_mov connect slots_0.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[0].wakeup_ports[0].bits.uop.is_rocc connect slots_0.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_0.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[0].wakeup_ports[0].bits.uop.is_eret connect slots_0.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[0].wakeup_ports[0].bits.uop.is_amo connect slots_0.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[0].wakeup_ports[0].bits.uop.is_sfence connect slots_0.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[0].wakeup_ports[0].bits.uop.is_fencei connect slots_0.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[0].wakeup_ports[0].bits.uop.is_fence connect slots_0.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[0].wakeup_ports[0].bits.uop.is_sfb connect slots_0.io.wakeup_ports[0].bits.uop.br_type, issue_slots[0].wakeup_ports[0].bits.uop.br_type connect slots_0.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[0].wakeup_ports[0].bits.uop.br_tag connect slots_0.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[0].wakeup_ports[0].bits.uop.br_mask connect slots_0.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[0].bits.uop.dis_col_sel connect slots_0.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_0.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_0.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_0.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_0.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[0] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[1] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[2] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[3] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[4] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[5] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[6] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[7] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[8] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[9] connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[0] connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[1] connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[2] connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[3] connect slots_0.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[0].wakeup_ports[0].bits.uop.debug_pc connect slots_0.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[0].wakeup_ports[0].bits.uop.is_rvc connect slots_0.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[0].wakeup_ports[0].bits.uop.debug_inst connect slots_0.io.wakeup_ports[0].bits.uop.inst, issue_slots[0].wakeup_ports[0].bits.uop.inst connect slots_0.io.wakeup_ports[0].valid, issue_slots[0].wakeup_ports[0].valid connect slots_0.io.wakeup_ports[1].bits.rebusy, issue_slots[0].wakeup_ports[1].bits.rebusy connect slots_0.io.wakeup_ports[1].bits.speculative_mask, issue_slots[0].wakeup_ports[1].bits.speculative_mask connect slots_0.io.wakeup_ports[1].bits.bypassable, issue_slots[0].wakeup_ports[1].bits.bypassable connect slots_0.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[1].bits.uop.debug_tsrc connect slots_0.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[1].bits.uop.debug_fsrc connect slots_0.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_0.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[1].bits.uop.bp_debug_if connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_0.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[0].wakeup_ports[1].bits.uop.fp_typ connect slots_0.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[0].wakeup_ports[1].bits.uop.fp_rm connect slots_0.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[0].wakeup_ports[1].bits.uop.fp_val connect slots_0.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[0].wakeup_ports[1].bits.uop.fcn_op connect slots_0.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[1].bits.uop.fcn_dw connect slots_0.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[0].wakeup_ports[1].bits.uop.frs3_en connect slots_0.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_0.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_0.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[1].bits.uop.dst_rtype connect slots_0.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[0].wakeup_ports[1].bits.uop.lrs3 connect slots_0.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[0].wakeup_ports[1].bits.uop.lrs2 connect slots_0.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[0].wakeup_ports[1].bits.uop.lrs1 connect slots_0.io.wakeup_ports[1].bits.uop.ldst, issue_slots[0].wakeup_ports[1].bits.uop.ldst connect slots_0.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_0.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[1].bits.uop.csr_cmd connect slots_0.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[1].bits.uop.flush_on_commit connect slots_0.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[0].wakeup_ports[1].bits.uop.is_unique connect slots_0.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[0].wakeup_ports[1].bits.uop.uses_stq connect slots_0.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[1].bits.uop.uses_ldq connect slots_0.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[0].wakeup_ports[1].bits.uop.mem_signed connect slots_0.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[0].wakeup_ports[1].bits.uop.mem_size connect slots_0.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[1].bits.uop.mem_cmd connect slots_0.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[0].wakeup_ports[1].bits.uop.exc_cause connect slots_0.io.wakeup_ports[1].bits.uop.exception, issue_slots[0].wakeup_ports[1].bits.uop.exception connect slots_0.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[1].bits.uop.stale_pdst connect slots_0.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[1].bits.uop.ppred_busy connect slots_0.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs3_busy connect slots_0.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs2_busy connect slots_0.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs1_busy connect slots_0.io.wakeup_ports[1].bits.uop.ppred, issue_slots[0].wakeup_ports[1].bits.uop.ppred connect slots_0.io.wakeup_ports[1].bits.uop.prs3, issue_slots[0].wakeup_ports[1].bits.uop.prs3 connect slots_0.io.wakeup_ports[1].bits.uop.prs2, issue_slots[0].wakeup_ports[1].bits.uop.prs2 connect slots_0.io.wakeup_ports[1].bits.uop.prs1, issue_slots[0].wakeup_ports[1].bits.uop.prs1 connect slots_0.io.wakeup_ports[1].bits.uop.pdst, issue_slots[0].wakeup_ports[1].bits.uop.pdst connect slots_0.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[1].bits.uop.rxq_idx connect slots_0.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[0].wakeup_ports[1].bits.uop.stq_idx connect slots_0.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[1].bits.uop.ldq_idx connect slots_0.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[0].wakeup_ports[1].bits.uop.rob_idx connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_0.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[0].wakeup_ports[1].bits.uop.op2_sel connect slots_0.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[0].wakeup_ports[1].bits.uop.op1_sel connect slots_0.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[0].wakeup_ports[1].bits.uop.imm_packed connect slots_0.io.wakeup_ports[1].bits.uop.pimm, issue_slots[0].wakeup_ports[1].bits.uop.pimm connect slots_0.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[0].wakeup_ports[1].bits.uop.imm_sel connect slots_0.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[0].wakeup_ports[1].bits.uop.imm_rename connect slots_0.io.wakeup_ports[1].bits.uop.taken, issue_slots[0].wakeup_ports[1].bits.uop.taken connect slots_0.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[0].wakeup_ports[1].bits.uop.pc_lob connect slots_0.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[0].wakeup_ports[1].bits.uop.edge_inst connect slots_0.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[1].bits.uop.ftq_idx connect slots_0.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[0].wakeup_ports[1].bits.uop.is_mov connect slots_0.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[0].wakeup_ports[1].bits.uop.is_rocc connect slots_0.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_0.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[0].wakeup_ports[1].bits.uop.is_eret connect slots_0.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[0].wakeup_ports[1].bits.uop.is_amo connect slots_0.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[0].wakeup_ports[1].bits.uop.is_sfence connect slots_0.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[0].wakeup_ports[1].bits.uop.is_fencei connect slots_0.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[0].wakeup_ports[1].bits.uop.is_fence connect slots_0.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[0].wakeup_ports[1].bits.uop.is_sfb connect slots_0.io.wakeup_ports[1].bits.uop.br_type, issue_slots[0].wakeup_ports[1].bits.uop.br_type connect slots_0.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[0].wakeup_ports[1].bits.uop.br_tag connect slots_0.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[0].wakeup_ports[1].bits.uop.br_mask connect slots_0.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[1].bits.uop.dis_col_sel connect slots_0.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_0.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_0.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_0.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_0.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[0] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[1] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[2] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[3] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[4] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[5] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[6] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[7] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[8] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[9] connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[0] connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[1] connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[2] connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[3] connect slots_0.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[0].wakeup_ports[1].bits.uop.debug_pc connect slots_0.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[0].wakeup_ports[1].bits.uop.is_rvc connect slots_0.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[0].wakeup_ports[1].bits.uop.debug_inst connect slots_0.io.wakeup_ports[1].bits.uop.inst, issue_slots[0].wakeup_ports[1].bits.uop.inst connect slots_0.io.wakeup_ports[1].valid, issue_slots[0].wakeup_ports[1].valid connect slots_0.io.wakeup_ports[2].bits.rebusy, issue_slots[0].wakeup_ports[2].bits.rebusy connect slots_0.io.wakeup_ports[2].bits.speculative_mask, issue_slots[0].wakeup_ports[2].bits.speculative_mask connect slots_0.io.wakeup_ports[2].bits.bypassable, issue_slots[0].wakeup_ports[2].bits.bypassable connect slots_0.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[2].bits.uop.debug_tsrc connect slots_0.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[2].bits.uop.debug_fsrc connect slots_0.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_0.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[2].bits.uop.bp_debug_if connect slots_0.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_0.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_0.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_0.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[0].wakeup_ports[2].bits.uop.fp_typ connect slots_0.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[0].wakeup_ports[2].bits.uop.fp_rm connect slots_0.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[0].wakeup_ports[2].bits.uop.fp_val connect slots_0.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[0].wakeup_ports[2].bits.uop.fcn_op connect slots_0.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[2].bits.uop.fcn_dw connect slots_0.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[0].wakeup_ports[2].bits.uop.frs3_en connect slots_0.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_0.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_0.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[2].bits.uop.dst_rtype connect slots_0.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[0].wakeup_ports[2].bits.uop.lrs3 connect slots_0.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[0].wakeup_ports[2].bits.uop.lrs2 connect slots_0.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[0].wakeup_ports[2].bits.uop.lrs1 connect slots_0.io.wakeup_ports[2].bits.uop.ldst, issue_slots[0].wakeup_ports[2].bits.uop.ldst connect slots_0.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_0.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[2].bits.uop.csr_cmd connect slots_0.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[2].bits.uop.flush_on_commit connect slots_0.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[0].wakeup_ports[2].bits.uop.is_unique connect slots_0.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[0].wakeup_ports[2].bits.uop.uses_stq connect slots_0.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[2].bits.uop.uses_ldq connect slots_0.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[0].wakeup_ports[2].bits.uop.mem_signed connect slots_0.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[0].wakeup_ports[2].bits.uop.mem_size connect slots_0.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[2].bits.uop.mem_cmd connect slots_0.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[0].wakeup_ports[2].bits.uop.exc_cause connect slots_0.io.wakeup_ports[2].bits.uop.exception, issue_slots[0].wakeup_ports[2].bits.uop.exception connect slots_0.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[2].bits.uop.stale_pdst connect slots_0.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[2].bits.uop.ppred_busy connect slots_0.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[2].bits.uop.prs3_busy connect slots_0.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[2].bits.uop.prs2_busy connect slots_0.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[2].bits.uop.prs1_busy connect slots_0.io.wakeup_ports[2].bits.uop.ppred, issue_slots[0].wakeup_ports[2].bits.uop.ppred connect slots_0.io.wakeup_ports[2].bits.uop.prs3, issue_slots[0].wakeup_ports[2].bits.uop.prs3 connect slots_0.io.wakeup_ports[2].bits.uop.prs2, issue_slots[0].wakeup_ports[2].bits.uop.prs2 connect slots_0.io.wakeup_ports[2].bits.uop.prs1, issue_slots[0].wakeup_ports[2].bits.uop.prs1 connect slots_0.io.wakeup_ports[2].bits.uop.pdst, issue_slots[0].wakeup_ports[2].bits.uop.pdst connect slots_0.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[2].bits.uop.rxq_idx connect slots_0.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[0].wakeup_ports[2].bits.uop.stq_idx connect slots_0.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[2].bits.uop.ldq_idx connect slots_0.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[0].wakeup_ports[2].bits.uop.rob_idx connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_0.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[0].wakeup_ports[2].bits.uop.op2_sel connect slots_0.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[0].wakeup_ports[2].bits.uop.op1_sel connect slots_0.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[0].wakeup_ports[2].bits.uop.imm_packed connect slots_0.io.wakeup_ports[2].bits.uop.pimm, issue_slots[0].wakeup_ports[2].bits.uop.pimm connect slots_0.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[0].wakeup_ports[2].bits.uop.imm_sel connect slots_0.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[0].wakeup_ports[2].bits.uop.imm_rename connect slots_0.io.wakeup_ports[2].bits.uop.taken, issue_slots[0].wakeup_ports[2].bits.uop.taken connect slots_0.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[0].wakeup_ports[2].bits.uop.pc_lob connect slots_0.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[0].wakeup_ports[2].bits.uop.edge_inst connect slots_0.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[2].bits.uop.ftq_idx connect slots_0.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[0].wakeup_ports[2].bits.uop.is_mov connect slots_0.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[0].wakeup_ports[2].bits.uop.is_rocc connect slots_0.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_0.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[0].wakeup_ports[2].bits.uop.is_eret connect slots_0.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[0].wakeup_ports[2].bits.uop.is_amo connect slots_0.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[0].wakeup_ports[2].bits.uop.is_sfence connect slots_0.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[0].wakeup_ports[2].bits.uop.is_fencei connect slots_0.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[0].wakeup_ports[2].bits.uop.is_fence connect slots_0.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[0].wakeup_ports[2].bits.uop.is_sfb connect slots_0.io.wakeup_ports[2].bits.uop.br_type, issue_slots[0].wakeup_ports[2].bits.uop.br_type connect slots_0.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[0].wakeup_ports[2].bits.uop.br_tag connect slots_0.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[0].wakeup_ports[2].bits.uop.br_mask connect slots_0.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[2].bits.uop.dis_col_sel connect slots_0.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_0.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_0.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_0.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_0.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_0.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_0.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_0.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[0].wakeup_ports[2].bits.uop.iw_issued connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[0] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[1] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[2] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[3] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[4] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[5] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[6] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[7] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[8] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[9] connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[0] connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[1] connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[2] connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[3] connect slots_0.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[0].wakeup_ports[2].bits.uop.debug_pc connect slots_0.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[0].wakeup_ports[2].bits.uop.is_rvc connect slots_0.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[0].wakeup_ports[2].bits.uop.debug_inst connect slots_0.io.wakeup_ports[2].bits.uop.inst, issue_slots[0].wakeup_ports[2].bits.uop.inst connect slots_0.io.wakeup_ports[2].valid, issue_slots[0].wakeup_ports[2].valid connect slots_0.io.wakeup_ports[3].bits.rebusy, issue_slots[0].wakeup_ports[3].bits.rebusy connect slots_0.io.wakeup_ports[3].bits.speculative_mask, issue_slots[0].wakeup_ports[3].bits.speculative_mask connect slots_0.io.wakeup_ports[3].bits.bypassable, issue_slots[0].wakeup_ports[3].bits.bypassable connect slots_0.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[3].bits.uop.debug_tsrc connect slots_0.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[3].bits.uop.debug_fsrc connect slots_0.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_0.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[3].bits.uop.bp_debug_if connect slots_0.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_0.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_0.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_0.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[0].wakeup_ports[3].bits.uop.fp_typ connect slots_0.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[0].wakeup_ports[3].bits.uop.fp_rm connect slots_0.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[0].wakeup_ports[3].bits.uop.fp_val connect slots_0.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[0].wakeup_ports[3].bits.uop.fcn_op connect slots_0.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[3].bits.uop.fcn_dw connect slots_0.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[0].wakeup_ports[3].bits.uop.frs3_en connect slots_0.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_0.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_0.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[3].bits.uop.dst_rtype connect slots_0.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[0].wakeup_ports[3].bits.uop.lrs3 connect slots_0.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[0].wakeup_ports[3].bits.uop.lrs2 connect slots_0.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[0].wakeup_ports[3].bits.uop.lrs1 connect slots_0.io.wakeup_ports[3].bits.uop.ldst, issue_slots[0].wakeup_ports[3].bits.uop.ldst connect slots_0.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_0.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[3].bits.uop.csr_cmd connect slots_0.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[3].bits.uop.flush_on_commit connect slots_0.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[0].wakeup_ports[3].bits.uop.is_unique connect slots_0.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[0].wakeup_ports[3].bits.uop.uses_stq connect slots_0.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[3].bits.uop.uses_ldq connect slots_0.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[0].wakeup_ports[3].bits.uop.mem_signed connect slots_0.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[0].wakeup_ports[3].bits.uop.mem_size connect slots_0.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[3].bits.uop.mem_cmd connect slots_0.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[0].wakeup_ports[3].bits.uop.exc_cause connect slots_0.io.wakeup_ports[3].bits.uop.exception, issue_slots[0].wakeup_ports[3].bits.uop.exception connect slots_0.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[3].bits.uop.stale_pdst connect slots_0.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[3].bits.uop.ppred_busy connect slots_0.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[3].bits.uop.prs3_busy connect slots_0.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[3].bits.uop.prs2_busy connect slots_0.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[3].bits.uop.prs1_busy connect slots_0.io.wakeup_ports[3].bits.uop.ppred, issue_slots[0].wakeup_ports[3].bits.uop.ppred connect slots_0.io.wakeup_ports[3].bits.uop.prs3, issue_slots[0].wakeup_ports[3].bits.uop.prs3 connect slots_0.io.wakeup_ports[3].bits.uop.prs2, issue_slots[0].wakeup_ports[3].bits.uop.prs2 connect slots_0.io.wakeup_ports[3].bits.uop.prs1, issue_slots[0].wakeup_ports[3].bits.uop.prs1 connect slots_0.io.wakeup_ports[3].bits.uop.pdst, issue_slots[0].wakeup_ports[3].bits.uop.pdst connect slots_0.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[3].bits.uop.rxq_idx connect slots_0.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[0].wakeup_ports[3].bits.uop.stq_idx connect slots_0.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[3].bits.uop.ldq_idx connect slots_0.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[0].wakeup_ports[3].bits.uop.rob_idx connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_0.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[0].wakeup_ports[3].bits.uop.op2_sel connect slots_0.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[0].wakeup_ports[3].bits.uop.op1_sel connect slots_0.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[0].wakeup_ports[3].bits.uop.imm_packed connect slots_0.io.wakeup_ports[3].bits.uop.pimm, issue_slots[0].wakeup_ports[3].bits.uop.pimm connect slots_0.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[0].wakeup_ports[3].bits.uop.imm_sel connect slots_0.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[0].wakeup_ports[3].bits.uop.imm_rename connect slots_0.io.wakeup_ports[3].bits.uop.taken, issue_slots[0].wakeup_ports[3].bits.uop.taken connect slots_0.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[0].wakeup_ports[3].bits.uop.pc_lob connect slots_0.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[0].wakeup_ports[3].bits.uop.edge_inst connect slots_0.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[3].bits.uop.ftq_idx connect slots_0.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[0].wakeup_ports[3].bits.uop.is_mov connect slots_0.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[0].wakeup_ports[3].bits.uop.is_rocc connect slots_0.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_0.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[0].wakeup_ports[3].bits.uop.is_eret connect slots_0.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[0].wakeup_ports[3].bits.uop.is_amo connect slots_0.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[0].wakeup_ports[3].bits.uop.is_sfence connect slots_0.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[0].wakeup_ports[3].bits.uop.is_fencei connect slots_0.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[0].wakeup_ports[3].bits.uop.is_fence connect slots_0.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[0].wakeup_ports[3].bits.uop.is_sfb connect slots_0.io.wakeup_ports[3].bits.uop.br_type, issue_slots[0].wakeup_ports[3].bits.uop.br_type connect slots_0.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[0].wakeup_ports[3].bits.uop.br_tag connect slots_0.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[0].wakeup_ports[3].bits.uop.br_mask connect slots_0.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[3].bits.uop.dis_col_sel connect slots_0.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_0.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_0.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_0.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_0.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_0.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_0.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_0.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[0].wakeup_ports[3].bits.uop.iw_issued connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[0] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[1] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[2] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[3] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[4] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[5] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[6] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[7] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[8] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[9] connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[0] connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[1] connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[2] connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[3] connect slots_0.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[0].wakeup_ports[3].bits.uop.debug_pc connect slots_0.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[0].wakeup_ports[3].bits.uop.is_rvc connect slots_0.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[0].wakeup_ports[3].bits.uop.debug_inst connect slots_0.io.wakeup_ports[3].bits.uop.inst, issue_slots[0].wakeup_ports[3].bits.uop.inst connect slots_0.io.wakeup_ports[3].valid, issue_slots[0].wakeup_ports[3].valid connect slots_0.io.wakeup_ports[4].bits.rebusy, issue_slots[0].wakeup_ports[4].bits.rebusy connect slots_0.io.wakeup_ports[4].bits.speculative_mask, issue_slots[0].wakeup_ports[4].bits.speculative_mask connect slots_0.io.wakeup_ports[4].bits.bypassable, issue_slots[0].wakeup_ports[4].bits.bypassable connect slots_0.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[4].bits.uop.debug_tsrc connect slots_0.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[4].bits.uop.debug_fsrc connect slots_0.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_0.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[4].bits.uop.bp_debug_if connect slots_0.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_0.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_0.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_0.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[0].wakeup_ports[4].bits.uop.fp_typ connect slots_0.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[0].wakeup_ports[4].bits.uop.fp_rm connect slots_0.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[0].wakeup_ports[4].bits.uop.fp_val connect slots_0.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[0].wakeup_ports[4].bits.uop.fcn_op connect slots_0.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[4].bits.uop.fcn_dw connect slots_0.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[0].wakeup_ports[4].bits.uop.frs3_en connect slots_0.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_0.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_0.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[4].bits.uop.dst_rtype connect slots_0.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[0].wakeup_ports[4].bits.uop.lrs3 connect slots_0.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[0].wakeup_ports[4].bits.uop.lrs2 connect slots_0.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[0].wakeup_ports[4].bits.uop.lrs1 connect slots_0.io.wakeup_ports[4].bits.uop.ldst, issue_slots[0].wakeup_ports[4].bits.uop.ldst connect slots_0.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_0.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[4].bits.uop.csr_cmd connect slots_0.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[4].bits.uop.flush_on_commit connect slots_0.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[0].wakeup_ports[4].bits.uop.is_unique connect slots_0.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[0].wakeup_ports[4].bits.uop.uses_stq connect slots_0.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[4].bits.uop.uses_ldq connect slots_0.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[0].wakeup_ports[4].bits.uop.mem_signed connect slots_0.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[0].wakeup_ports[4].bits.uop.mem_size connect slots_0.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[4].bits.uop.mem_cmd connect slots_0.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[0].wakeup_ports[4].bits.uop.exc_cause connect slots_0.io.wakeup_ports[4].bits.uop.exception, issue_slots[0].wakeup_ports[4].bits.uop.exception connect slots_0.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[4].bits.uop.stale_pdst connect slots_0.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[4].bits.uop.ppred_busy connect slots_0.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[4].bits.uop.prs3_busy connect slots_0.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[4].bits.uop.prs2_busy connect slots_0.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[4].bits.uop.prs1_busy connect slots_0.io.wakeup_ports[4].bits.uop.ppred, issue_slots[0].wakeup_ports[4].bits.uop.ppred connect slots_0.io.wakeup_ports[4].bits.uop.prs3, issue_slots[0].wakeup_ports[4].bits.uop.prs3 connect slots_0.io.wakeup_ports[4].bits.uop.prs2, issue_slots[0].wakeup_ports[4].bits.uop.prs2 connect slots_0.io.wakeup_ports[4].bits.uop.prs1, issue_slots[0].wakeup_ports[4].bits.uop.prs1 connect slots_0.io.wakeup_ports[4].bits.uop.pdst, issue_slots[0].wakeup_ports[4].bits.uop.pdst connect slots_0.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[4].bits.uop.rxq_idx connect slots_0.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[0].wakeup_ports[4].bits.uop.stq_idx connect slots_0.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[4].bits.uop.ldq_idx connect slots_0.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[0].wakeup_ports[4].bits.uop.rob_idx connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_0.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[0].wakeup_ports[4].bits.uop.op2_sel connect slots_0.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[0].wakeup_ports[4].bits.uop.op1_sel connect slots_0.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[0].wakeup_ports[4].bits.uop.imm_packed connect slots_0.io.wakeup_ports[4].bits.uop.pimm, issue_slots[0].wakeup_ports[4].bits.uop.pimm connect slots_0.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[0].wakeup_ports[4].bits.uop.imm_sel connect slots_0.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[0].wakeup_ports[4].bits.uop.imm_rename connect slots_0.io.wakeup_ports[4].bits.uop.taken, issue_slots[0].wakeup_ports[4].bits.uop.taken connect slots_0.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[0].wakeup_ports[4].bits.uop.pc_lob connect slots_0.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[0].wakeup_ports[4].bits.uop.edge_inst connect slots_0.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[4].bits.uop.ftq_idx connect slots_0.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[0].wakeup_ports[4].bits.uop.is_mov connect slots_0.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[0].wakeup_ports[4].bits.uop.is_rocc connect slots_0.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_0.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[0].wakeup_ports[4].bits.uop.is_eret connect slots_0.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[0].wakeup_ports[4].bits.uop.is_amo connect slots_0.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[0].wakeup_ports[4].bits.uop.is_sfence connect slots_0.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[0].wakeup_ports[4].bits.uop.is_fencei connect slots_0.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[0].wakeup_ports[4].bits.uop.is_fence connect slots_0.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[0].wakeup_ports[4].bits.uop.is_sfb connect slots_0.io.wakeup_ports[4].bits.uop.br_type, issue_slots[0].wakeup_ports[4].bits.uop.br_type connect slots_0.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[0].wakeup_ports[4].bits.uop.br_tag connect slots_0.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[0].wakeup_ports[4].bits.uop.br_mask connect slots_0.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[4].bits.uop.dis_col_sel connect slots_0.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_0.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_0.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_0.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_0.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_0.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_0.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_0.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[0].wakeup_ports[4].bits.uop.iw_issued connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[0] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[1] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[2] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[3] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[4] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[5] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[6] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[7] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[8] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[9] connect slots_0.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[4].bits.uop.iq_type[0] connect slots_0.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[4].bits.uop.iq_type[1] connect slots_0.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[4].bits.uop.iq_type[2] connect slots_0.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[4].bits.uop.iq_type[3] connect slots_0.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[0].wakeup_ports[4].bits.uop.debug_pc connect slots_0.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[0].wakeup_ports[4].bits.uop.is_rvc connect slots_0.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[0].wakeup_ports[4].bits.uop.debug_inst connect slots_0.io.wakeup_ports[4].bits.uop.inst, issue_slots[0].wakeup_ports[4].bits.uop.inst connect slots_0.io.wakeup_ports[4].valid, issue_slots[0].wakeup_ports[4].valid connect slots_0.io.squash_grant, issue_slots[0].squash_grant connect slots_0.io.clear, issue_slots[0].clear connect slots_0.io.kill, issue_slots[0].kill connect slots_0.io.brupdate.b2.target_offset, issue_slots[0].brupdate.b2.target_offset connect slots_0.io.brupdate.b2.jalr_target, issue_slots[0].brupdate.b2.jalr_target connect slots_0.io.brupdate.b2.pc_sel, issue_slots[0].brupdate.b2.pc_sel connect slots_0.io.brupdate.b2.cfi_type, issue_slots[0].brupdate.b2.cfi_type connect slots_0.io.brupdate.b2.taken, issue_slots[0].brupdate.b2.taken connect slots_0.io.brupdate.b2.mispredict, issue_slots[0].brupdate.b2.mispredict connect slots_0.io.brupdate.b2.uop.debug_tsrc, issue_slots[0].brupdate.b2.uop.debug_tsrc connect slots_0.io.brupdate.b2.uop.debug_fsrc, issue_slots[0].brupdate.b2.uop.debug_fsrc connect slots_0.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[0].brupdate.b2.uop.bp_xcpt_if connect slots_0.io.brupdate.b2.uop.bp_debug_if, issue_slots[0].brupdate.b2.uop.bp_debug_if connect slots_0.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[0].brupdate.b2.uop.xcpt_ma_if connect slots_0.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[0].brupdate.b2.uop.xcpt_ae_if connect slots_0.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[0].brupdate.b2.uop.xcpt_pf_if connect slots_0.io.brupdate.b2.uop.fp_typ, issue_slots[0].brupdate.b2.uop.fp_typ connect slots_0.io.brupdate.b2.uop.fp_rm, issue_slots[0].brupdate.b2.uop.fp_rm connect slots_0.io.brupdate.b2.uop.fp_val, issue_slots[0].brupdate.b2.uop.fp_val connect slots_0.io.brupdate.b2.uop.fcn_op, issue_slots[0].brupdate.b2.uop.fcn_op connect slots_0.io.brupdate.b2.uop.fcn_dw, issue_slots[0].brupdate.b2.uop.fcn_dw connect slots_0.io.brupdate.b2.uop.frs3_en, issue_slots[0].brupdate.b2.uop.frs3_en connect slots_0.io.brupdate.b2.uop.lrs2_rtype, issue_slots[0].brupdate.b2.uop.lrs2_rtype connect slots_0.io.brupdate.b2.uop.lrs1_rtype, issue_slots[0].brupdate.b2.uop.lrs1_rtype connect slots_0.io.brupdate.b2.uop.dst_rtype, issue_slots[0].brupdate.b2.uop.dst_rtype connect slots_0.io.brupdate.b2.uop.lrs3, issue_slots[0].brupdate.b2.uop.lrs3 connect slots_0.io.brupdate.b2.uop.lrs2, issue_slots[0].brupdate.b2.uop.lrs2 connect slots_0.io.brupdate.b2.uop.lrs1, issue_slots[0].brupdate.b2.uop.lrs1 connect slots_0.io.brupdate.b2.uop.ldst, issue_slots[0].brupdate.b2.uop.ldst connect slots_0.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[0].brupdate.b2.uop.ldst_is_rs1 connect slots_0.io.brupdate.b2.uop.csr_cmd, issue_slots[0].brupdate.b2.uop.csr_cmd connect slots_0.io.brupdate.b2.uop.flush_on_commit, issue_slots[0].brupdate.b2.uop.flush_on_commit connect slots_0.io.brupdate.b2.uop.is_unique, issue_slots[0].brupdate.b2.uop.is_unique connect slots_0.io.brupdate.b2.uop.uses_stq, issue_slots[0].brupdate.b2.uop.uses_stq connect slots_0.io.brupdate.b2.uop.uses_ldq, issue_slots[0].brupdate.b2.uop.uses_ldq connect slots_0.io.brupdate.b2.uop.mem_signed, issue_slots[0].brupdate.b2.uop.mem_signed connect slots_0.io.brupdate.b2.uop.mem_size, issue_slots[0].brupdate.b2.uop.mem_size connect slots_0.io.brupdate.b2.uop.mem_cmd, issue_slots[0].brupdate.b2.uop.mem_cmd connect slots_0.io.brupdate.b2.uop.exc_cause, issue_slots[0].brupdate.b2.uop.exc_cause connect slots_0.io.brupdate.b2.uop.exception, issue_slots[0].brupdate.b2.uop.exception connect slots_0.io.brupdate.b2.uop.stale_pdst, issue_slots[0].brupdate.b2.uop.stale_pdst connect slots_0.io.brupdate.b2.uop.ppred_busy, issue_slots[0].brupdate.b2.uop.ppred_busy connect slots_0.io.brupdate.b2.uop.prs3_busy, issue_slots[0].brupdate.b2.uop.prs3_busy connect slots_0.io.brupdate.b2.uop.prs2_busy, issue_slots[0].brupdate.b2.uop.prs2_busy connect slots_0.io.brupdate.b2.uop.prs1_busy, issue_slots[0].brupdate.b2.uop.prs1_busy connect slots_0.io.brupdate.b2.uop.ppred, issue_slots[0].brupdate.b2.uop.ppred connect slots_0.io.brupdate.b2.uop.prs3, issue_slots[0].brupdate.b2.uop.prs3 connect slots_0.io.brupdate.b2.uop.prs2, issue_slots[0].brupdate.b2.uop.prs2 connect slots_0.io.brupdate.b2.uop.prs1, issue_slots[0].brupdate.b2.uop.prs1 connect slots_0.io.brupdate.b2.uop.pdst, issue_slots[0].brupdate.b2.uop.pdst connect slots_0.io.brupdate.b2.uop.rxq_idx, issue_slots[0].brupdate.b2.uop.rxq_idx connect slots_0.io.brupdate.b2.uop.stq_idx, issue_slots[0].brupdate.b2.uop.stq_idx connect slots_0.io.brupdate.b2.uop.ldq_idx, issue_slots[0].brupdate.b2.uop.ldq_idx connect slots_0.io.brupdate.b2.uop.rob_idx, issue_slots[0].brupdate.b2.uop.rob_idx connect slots_0.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[0].brupdate.b2.uop.fp_ctrl.vec connect slots_0.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[0].brupdate.b2.uop.fp_ctrl.wflags connect slots_0.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[0].brupdate.b2.uop.fp_ctrl.sqrt connect slots_0.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[0].brupdate.b2.uop.fp_ctrl.div connect slots_0.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[0].brupdate.b2.uop.fp_ctrl.fma connect slots_0.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[0].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_0.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[0].brupdate.b2.uop.fp_ctrl.toint connect slots_0.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[0].brupdate.b2.uop.fp_ctrl.fromint connect slots_0.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_0.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_0.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[0].brupdate.b2.uop.fp_ctrl.swap23 connect slots_0.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[0].brupdate.b2.uop.fp_ctrl.swap12 connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren3 connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren2 connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren1 connect slots_0.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[0].brupdate.b2.uop.fp_ctrl.wen connect slots_0.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[0].brupdate.b2.uop.fp_ctrl.ldst connect slots_0.io.brupdate.b2.uop.op2_sel, issue_slots[0].brupdate.b2.uop.op2_sel connect slots_0.io.brupdate.b2.uop.op1_sel, issue_slots[0].brupdate.b2.uop.op1_sel connect slots_0.io.brupdate.b2.uop.imm_packed, issue_slots[0].brupdate.b2.uop.imm_packed connect slots_0.io.brupdate.b2.uop.pimm, issue_slots[0].brupdate.b2.uop.pimm connect slots_0.io.brupdate.b2.uop.imm_sel, issue_slots[0].brupdate.b2.uop.imm_sel connect slots_0.io.brupdate.b2.uop.imm_rename, issue_slots[0].brupdate.b2.uop.imm_rename connect slots_0.io.brupdate.b2.uop.taken, issue_slots[0].brupdate.b2.uop.taken connect slots_0.io.brupdate.b2.uop.pc_lob, issue_slots[0].brupdate.b2.uop.pc_lob connect slots_0.io.brupdate.b2.uop.edge_inst, issue_slots[0].brupdate.b2.uop.edge_inst connect slots_0.io.brupdate.b2.uop.ftq_idx, issue_slots[0].brupdate.b2.uop.ftq_idx connect slots_0.io.brupdate.b2.uop.is_mov, issue_slots[0].brupdate.b2.uop.is_mov connect slots_0.io.brupdate.b2.uop.is_rocc, issue_slots[0].brupdate.b2.uop.is_rocc connect slots_0.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[0].brupdate.b2.uop.is_sys_pc2epc connect slots_0.io.brupdate.b2.uop.is_eret, issue_slots[0].brupdate.b2.uop.is_eret connect slots_0.io.brupdate.b2.uop.is_amo, issue_slots[0].brupdate.b2.uop.is_amo connect slots_0.io.brupdate.b2.uop.is_sfence, issue_slots[0].brupdate.b2.uop.is_sfence connect slots_0.io.brupdate.b2.uop.is_fencei, issue_slots[0].brupdate.b2.uop.is_fencei connect slots_0.io.brupdate.b2.uop.is_fence, issue_slots[0].brupdate.b2.uop.is_fence connect slots_0.io.brupdate.b2.uop.is_sfb, issue_slots[0].brupdate.b2.uop.is_sfb connect slots_0.io.brupdate.b2.uop.br_type, issue_slots[0].brupdate.b2.uop.br_type connect slots_0.io.brupdate.b2.uop.br_tag, issue_slots[0].brupdate.b2.uop.br_tag connect slots_0.io.brupdate.b2.uop.br_mask, issue_slots[0].brupdate.b2.uop.br_mask connect slots_0.io.brupdate.b2.uop.dis_col_sel, issue_slots[0].brupdate.b2.uop.dis_col_sel connect slots_0.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p3_bypass_hint connect slots_0.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p2_bypass_hint connect slots_0.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p1_bypass_hint connect slots_0.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[0].brupdate.b2.uop.iw_p2_speculative_child connect slots_0.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[0].brupdate.b2.uop.iw_p1_speculative_child connect slots_0.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[0].brupdate.b2.uop.iw_issued_partial_dgen connect slots_0.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[0].brupdate.b2.uop.iw_issued_partial_agen connect slots_0.io.brupdate.b2.uop.iw_issued, issue_slots[0].brupdate.b2.uop.iw_issued connect slots_0.io.brupdate.b2.uop.fu_code[0], issue_slots[0].brupdate.b2.uop.fu_code[0] connect slots_0.io.brupdate.b2.uop.fu_code[1], issue_slots[0].brupdate.b2.uop.fu_code[1] connect slots_0.io.brupdate.b2.uop.fu_code[2], issue_slots[0].brupdate.b2.uop.fu_code[2] connect slots_0.io.brupdate.b2.uop.fu_code[3], issue_slots[0].brupdate.b2.uop.fu_code[3] connect slots_0.io.brupdate.b2.uop.fu_code[4], issue_slots[0].brupdate.b2.uop.fu_code[4] connect slots_0.io.brupdate.b2.uop.fu_code[5], issue_slots[0].brupdate.b2.uop.fu_code[5] connect slots_0.io.brupdate.b2.uop.fu_code[6], issue_slots[0].brupdate.b2.uop.fu_code[6] connect slots_0.io.brupdate.b2.uop.fu_code[7], issue_slots[0].brupdate.b2.uop.fu_code[7] connect slots_0.io.brupdate.b2.uop.fu_code[8], issue_slots[0].brupdate.b2.uop.fu_code[8] connect slots_0.io.brupdate.b2.uop.fu_code[9], issue_slots[0].brupdate.b2.uop.fu_code[9] connect slots_0.io.brupdate.b2.uop.iq_type[0], issue_slots[0].brupdate.b2.uop.iq_type[0] connect slots_0.io.brupdate.b2.uop.iq_type[1], issue_slots[0].brupdate.b2.uop.iq_type[1] connect slots_0.io.brupdate.b2.uop.iq_type[2], issue_slots[0].brupdate.b2.uop.iq_type[2] connect slots_0.io.brupdate.b2.uop.iq_type[3], issue_slots[0].brupdate.b2.uop.iq_type[3] connect slots_0.io.brupdate.b2.uop.debug_pc, issue_slots[0].brupdate.b2.uop.debug_pc connect slots_0.io.brupdate.b2.uop.is_rvc, issue_slots[0].brupdate.b2.uop.is_rvc connect slots_0.io.brupdate.b2.uop.debug_inst, issue_slots[0].brupdate.b2.uop.debug_inst connect slots_0.io.brupdate.b2.uop.inst, issue_slots[0].brupdate.b2.uop.inst connect slots_0.io.brupdate.b1.mispredict_mask, issue_slots[0].brupdate.b1.mispredict_mask connect slots_0.io.brupdate.b1.resolve_mask, issue_slots[0].brupdate.b1.resolve_mask connect issue_slots[0].out_uop.debug_tsrc, slots_0.io.out_uop.debug_tsrc connect issue_slots[0].out_uop.debug_fsrc, slots_0.io.out_uop.debug_fsrc connect issue_slots[0].out_uop.bp_xcpt_if, slots_0.io.out_uop.bp_xcpt_if connect issue_slots[0].out_uop.bp_debug_if, slots_0.io.out_uop.bp_debug_if connect issue_slots[0].out_uop.xcpt_ma_if, slots_0.io.out_uop.xcpt_ma_if connect issue_slots[0].out_uop.xcpt_ae_if, slots_0.io.out_uop.xcpt_ae_if connect issue_slots[0].out_uop.xcpt_pf_if, slots_0.io.out_uop.xcpt_pf_if connect issue_slots[0].out_uop.fp_typ, slots_0.io.out_uop.fp_typ connect issue_slots[0].out_uop.fp_rm, slots_0.io.out_uop.fp_rm connect issue_slots[0].out_uop.fp_val, slots_0.io.out_uop.fp_val connect issue_slots[0].out_uop.fcn_op, slots_0.io.out_uop.fcn_op connect issue_slots[0].out_uop.fcn_dw, slots_0.io.out_uop.fcn_dw connect issue_slots[0].out_uop.frs3_en, slots_0.io.out_uop.frs3_en connect issue_slots[0].out_uop.lrs2_rtype, slots_0.io.out_uop.lrs2_rtype connect issue_slots[0].out_uop.lrs1_rtype, slots_0.io.out_uop.lrs1_rtype connect issue_slots[0].out_uop.dst_rtype, slots_0.io.out_uop.dst_rtype connect issue_slots[0].out_uop.lrs3, slots_0.io.out_uop.lrs3 connect issue_slots[0].out_uop.lrs2, slots_0.io.out_uop.lrs2 connect issue_slots[0].out_uop.lrs1, slots_0.io.out_uop.lrs1 connect issue_slots[0].out_uop.ldst, slots_0.io.out_uop.ldst connect issue_slots[0].out_uop.ldst_is_rs1, slots_0.io.out_uop.ldst_is_rs1 connect issue_slots[0].out_uop.csr_cmd, slots_0.io.out_uop.csr_cmd connect issue_slots[0].out_uop.flush_on_commit, slots_0.io.out_uop.flush_on_commit connect issue_slots[0].out_uop.is_unique, slots_0.io.out_uop.is_unique connect issue_slots[0].out_uop.uses_stq, slots_0.io.out_uop.uses_stq connect issue_slots[0].out_uop.uses_ldq, slots_0.io.out_uop.uses_ldq connect issue_slots[0].out_uop.mem_signed, slots_0.io.out_uop.mem_signed connect issue_slots[0].out_uop.mem_size, slots_0.io.out_uop.mem_size connect issue_slots[0].out_uop.mem_cmd, slots_0.io.out_uop.mem_cmd connect issue_slots[0].out_uop.exc_cause, slots_0.io.out_uop.exc_cause connect issue_slots[0].out_uop.exception, slots_0.io.out_uop.exception connect issue_slots[0].out_uop.stale_pdst, slots_0.io.out_uop.stale_pdst connect issue_slots[0].out_uop.ppred_busy, slots_0.io.out_uop.ppred_busy connect issue_slots[0].out_uop.prs3_busy, slots_0.io.out_uop.prs3_busy connect issue_slots[0].out_uop.prs2_busy, slots_0.io.out_uop.prs2_busy connect issue_slots[0].out_uop.prs1_busy, slots_0.io.out_uop.prs1_busy connect issue_slots[0].out_uop.ppred, slots_0.io.out_uop.ppred connect issue_slots[0].out_uop.prs3, slots_0.io.out_uop.prs3 connect issue_slots[0].out_uop.prs2, slots_0.io.out_uop.prs2 connect issue_slots[0].out_uop.prs1, slots_0.io.out_uop.prs1 connect issue_slots[0].out_uop.pdst, slots_0.io.out_uop.pdst connect issue_slots[0].out_uop.rxq_idx, slots_0.io.out_uop.rxq_idx connect issue_slots[0].out_uop.stq_idx, slots_0.io.out_uop.stq_idx connect issue_slots[0].out_uop.ldq_idx, slots_0.io.out_uop.ldq_idx connect issue_slots[0].out_uop.rob_idx, slots_0.io.out_uop.rob_idx connect issue_slots[0].out_uop.fp_ctrl.vec, slots_0.io.out_uop.fp_ctrl.vec connect issue_slots[0].out_uop.fp_ctrl.wflags, slots_0.io.out_uop.fp_ctrl.wflags connect issue_slots[0].out_uop.fp_ctrl.sqrt, slots_0.io.out_uop.fp_ctrl.sqrt connect issue_slots[0].out_uop.fp_ctrl.div, slots_0.io.out_uop.fp_ctrl.div connect issue_slots[0].out_uop.fp_ctrl.fma, slots_0.io.out_uop.fp_ctrl.fma connect issue_slots[0].out_uop.fp_ctrl.fastpipe, slots_0.io.out_uop.fp_ctrl.fastpipe connect issue_slots[0].out_uop.fp_ctrl.toint, slots_0.io.out_uop.fp_ctrl.toint connect issue_slots[0].out_uop.fp_ctrl.fromint, slots_0.io.out_uop.fp_ctrl.fromint connect issue_slots[0].out_uop.fp_ctrl.typeTagOut, slots_0.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[0].out_uop.fp_ctrl.typeTagIn, slots_0.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[0].out_uop.fp_ctrl.swap23, slots_0.io.out_uop.fp_ctrl.swap23 connect issue_slots[0].out_uop.fp_ctrl.swap12, slots_0.io.out_uop.fp_ctrl.swap12 connect issue_slots[0].out_uop.fp_ctrl.ren3, slots_0.io.out_uop.fp_ctrl.ren3 connect issue_slots[0].out_uop.fp_ctrl.ren2, slots_0.io.out_uop.fp_ctrl.ren2 connect issue_slots[0].out_uop.fp_ctrl.ren1, slots_0.io.out_uop.fp_ctrl.ren1 connect issue_slots[0].out_uop.fp_ctrl.wen, slots_0.io.out_uop.fp_ctrl.wen connect issue_slots[0].out_uop.fp_ctrl.ldst, slots_0.io.out_uop.fp_ctrl.ldst connect issue_slots[0].out_uop.op2_sel, slots_0.io.out_uop.op2_sel connect issue_slots[0].out_uop.op1_sel, slots_0.io.out_uop.op1_sel connect issue_slots[0].out_uop.imm_packed, slots_0.io.out_uop.imm_packed connect issue_slots[0].out_uop.pimm, slots_0.io.out_uop.pimm connect issue_slots[0].out_uop.imm_sel, slots_0.io.out_uop.imm_sel connect issue_slots[0].out_uop.imm_rename, slots_0.io.out_uop.imm_rename connect issue_slots[0].out_uop.taken, slots_0.io.out_uop.taken connect issue_slots[0].out_uop.pc_lob, slots_0.io.out_uop.pc_lob connect issue_slots[0].out_uop.edge_inst, slots_0.io.out_uop.edge_inst connect issue_slots[0].out_uop.ftq_idx, slots_0.io.out_uop.ftq_idx connect issue_slots[0].out_uop.is_mov, slots_0.io.out_uop.is_mov connect issue_slots[0].out_uop.is_rocc, slots_0.io.out_uop.is_rocc connect issue_slots[0].out_uop.is_sys_pc2epc, slots_0.io.out_uop.is_sys_pc2epc connect issue_slots[0].out_uop.is_eret, slots_0.io.out_uop.is_eret connect issue_slots[0].out_uop.is_amo, slots_0.io.out_uop.is_amo connect issue_slots[0].out_uop.is_sfence, slots_0.io.out_uop.is_sfence connect issue_slots[0].out_uop.is_fencei, slots_0.io.out_uop.is_fencei connect issue_slots[0].out_uop.is_fence, slots_0.io.out_uop.is_fence connect issue_slots[0].out_uop.is_sfb, slots_0.io.out_uop.is_sfb connect issue_slots[0].out_uop.br_type, slots_0.io.out_uop.br_type connect issue_slots[0].out_uop.br_tag, slots_0.io.out_uop.br_tag connect issue_slots[0].out_uop.br_mask, slots_0.io.out_uop.br_mask connect issue_slots[0].out_uop.dis_col_sel, slots_0.io.out_uop.dis_col_sel connect issue_slots[0].out_uop.iw_p3_bypass_hint, slots_0.io.out_uop.iw_p3_bypass_hint connect issue_slots[0].out_uop.iw_p2_bypass_hint, slots_0.io.out_uop.iw_p2_bypass_hint connect issue_slots[0].out_uop.iw_p1_bypass_hint, slots_0.io.out_uop.iw_p1_bypass_hint connect issue_slots[0].out_uop.iw_p2_speculative_child, slots_0.io.out_uop.iw_p2_speculative_child connect issue_slots[0].out_uop.iw_p1_speculative_child, slots_0.io.out_uop.iw_p1_speculative_child connect issue_slots[0].out_uop.iw_issued_partial_dgen, slots_0.io.out_uop.iw_issued_partial_dgen connect issue_slots[0].out_uop.iw_issued_partial_agen, slots_0.io.out_uop.iw_issued_partial_agen connect issue_slots[0].out_uop.iw_issued, slots_0.io.out_uop.iw_issued connect issue_slots[0].out_uop.fu_code[0], slots_0.io.out_uop.fu_code[0] connect issue_slots[0].out_uop.fu_code[1], slots_0.io.out_uop.fu_code[1] connect issue_slots[0].out_uop.fu_code[2], slots_0.io.out_uop.fu_code[2] connect issue_slots[0].out_uop.fu_code[3], slots_0.io.out_uop.fu_code[3] connect issue_slots[0].out_uop.fu_code[4], slots_0.io.out_uop.fu_code[4] connect issue_slots[0].out_uop.fu_code[5], slots_0.io.out_uop.fu_code[5] connect issue_slots[0].out_uop.fu_code[6], slots_0.io.out_uop.fu_code[6] connect issue_slots[0].out_uop.fu_code[7], slots_0.io.out_uop.fu_code[7] connect issue_slots[0].out_uop.fu_code[8], slots_0.io.out_uop.fu_code[8] connect issue_slots[0].out_uop.fu_code[9], slots_0.io.out_uop.fu_code[9] connect issue_slots[0].out_uop.iq_type[0], slots_0.io.out_uop.iq_type[0] connect issue_slots[0].out_uop.iq_type[1], slots_0.io.out_uop.iq_type[1] connect issue_slots[0].out_uop.iq_type[2], slots_0.io.out_uop.iq_type[2] connect issue_slots[0].out_uop.iq_type[3], slots_0.io.out_uop.iq_type[3] connect issue_slots[0].out_uop.debug_pc, slots_0.io.out_uop.debug_pc connect issue_slots[0].out_uop.is_rvc, slots_0.io.out_uop.is_rvc connect issue_slots[0].out_uop.debug_inst, slots_0.io.out_uop.debug_inst connect issue_slots[0].out_uop.inst, slots_0.io.out_uop.inst connect slots_0.io.in_uop.bits.debug_tsrc, issue_slots[0].in_uop.bits.debug_tsrc connect slots_0.io.in_uop.bits.debug_fsrc, issue_slots[0].in_uop.bits.debug_fsrc connect slots_0.io.in_uop.bits.bp_xcpt_if, issue_slots[0].in_uop.bits.bp_xcpt_if connect slots_0.io.in_uop.bits.bp_debug_if, issue_slots[0].in_uop.bits.bp_debug_if connect slots_0.io.in_uop.bits.xcpt_ma_if, issue_slots[0].in_uop.bits.xcpt_ma_if connect slots_0.io.in_uop.bits.xcpt_ae_if, issue_slots[0].in_uop.bits.xcpt_ae_if connect slots_0.io.in_uop.bits.xcpt_pf_if, issue_slots[0].in_uop.bits.xcpt_pf_if connect slots_0.io.in_uop.bits.fp_typ, issue_slots[0].in_uop.bits.fp_typ connect slots_0.io.in_uop.bits.fp_rm, issue_slots[0].in_uop.bits.fp_rm connect slots_0.io.in_uop.bits.fp_val, issue_slots[0].in_uop.bits.fp_val connect slots_0.io.in_uop.bits.fcn_op, issue_slots[0].in_uop.bits.fcn_op connect slots_0.io.in_uop.bits.fcn_dw, issue_slots[0].in_uop.bits.fcn_dw connect slots_0.io.in_uop.bits.frs3_en, issue_slots[0].in_uop.bits.frs3_en connect slots_0.io.in_uop.bits.lrs2_rtype, issue_slots[0].in_uop.bits.lrs2_rtype connect slots_0.io.in_uop.bits.lrs1_rtype, issue_slots[0].in_uop.bits.lrs1_rtype connect slots_0.io.in_uop.bits.dst_rtype, issue_slots[0].in_uop.bits.dst_rtype connect slots_0.io.in_uop.bits.lrs3, issue_slots[0].in_uop.bits.lrs3 connect slots_0.io.in_uop.bits.lrs2, issue_slots[0].in_uop.bits.lrs2 connect slots_0.io.in_uop.bits.lrs1, issue_slots[0].in_uop.bits.lrs1 connect slots_0.io.in_uop.bits.ldst, issue_slots[0].in_uop.bits.ldst connect slots_0.io.in_uop.bits.ldst_is_rs1, issue_slots[0].in_uop.bits.ldst_is_rs1 connect slots_0.io.in_uop.bits.csr_cmd, issue_slots[0].in_uop.bits.csr_cmd connect slots_0.io.in_uop.bits.flush_on_commit, issue_slots[0].in_uop.bits.flush_on_commit connect slots_0.io.in_uop.bits.is_unique, issue_slots[0].in_uop.bits.is_unique connect slots_0.io.in_uop.bits.uses_stq, issue_slots[0].in_uop.bits.uses_stq connect slots_0.io.in_uop.bits.uses_ldq, issue_slots[0].in_uop.bits.uses_ldq connect slots_0.io.in_uop.bits.mem_signed, issue_slots[0].in_uop.bits.mem_signed connect slots_0.io.in_uop.bits.mem_size, issue_slots[0].in_uop.bits.mem_size connect slots_0.io.in_uop.bits.mem_cmd, issue_slots[0].in_uop.bits.mem_cmd connect slots_0.io.in_uop.bits.exc_cause, issue_slots[0].in_uop.bits.exc_cause connect slots_0.io.in_uop.bits.exception, issue_slots[0].in_uop.bits.exception connect slots_0.io.in_uop.bits.stale_pdst, issue_slots[0].in_uop.bits.stale_pdst connect slots_0.io.in_uop.bits.ppred_busy, issue_slots[0].in_uop.bits.ppred_busy connect slots_0.io.in_uop.bits.prs3_busy, issue_slots[0].in_uop.bits.prs3_busy connect slots_0.io.in_uop.bits.prs2_busy, issue_slots[0].in_uop.bits.prs2_busy connect slots_0.io.in_uop.bits.prs1_busy, issue_slots[0].in_uop.bits.prs1_busy connect slots_0.io.in_uop.bits.ppred, issue_slots[0].in_uop.bits.ppred connect slots_0.io.in_uop.bits.prs3, issue_slots[0].in_uop.bits.prs3 connect slots_0.io.in_uop.bits.prs2, issue_slots[0].in_uop.bits.prs2 connect slots_0.io.in_uop.bits.prs1, issue_slots[0].in_uop.bits.prs1 connect slots_0.io.in_uop.bits.pdst, issue_slots[0].in_uop.bits.pdst connect slots_0.io.in_uop.bits.rxq_idx, issue_slots[0].in_uop.bits.rxq_idx connect slots_0.io.in_uop.bits.stq_idx, issue_slots[0].in_uop.bits.stq_idx connect slots_0.io.in_uop.bits.ldq_idx, issue_slots[0].in_uop.bits.ldq_idx connect slots_0.io.in_uop.bits.rob_idx, issue_slots[0].in_uop.bits.rob_idx connect slots_0.io.in_uop.bits.fp_ctrl.vec, issue_slots[0].in_uop.bits.fp_ctrl.vec connect slots_0.io.in_uop.bits.fp_ctrl.wflags, issue_slots[0].in_uop.bits.fp_ctrl.wflags connect slots_0.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[0].in_uop.bits.fp_ctrl.sqrt connect slots_0.io.in_uop.bits.fp_ctrl.div, issue_slots[0].in_uop.bits.fp_ctrl.div connect slots_0.io.in_uop.bits.fp_ctrl.fma, issue_slots[0].in_uop.bits.fp_ctrl.fma connect slots_0.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[0].in_uop.bits.fp_ctrl.fastpipe connect slots_0.io.in_uop.bits.fp_ctrl.toint, issue_slots[0].in_uop.bits.fp_ctrl.toint connect slots_0.io.in_uop.bits.fp_ctrl.fromint, issue_slots[0].in_uop.bits.fp_ctrl.fromint connect slots_0.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut connect slots_0.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn connect slots_0.io.in_uop.bits.fp_ctrl.swap23, issue_slots[0].in_uop.bits.fp_ctrl.swap23 connect slots_0.io.in_uop.bits.fp_ctrl.swap12, issue_slots[0].in_uop.bits.fp_ctrl.swap12 connect slots_0.io.in_uop.bits.fp_ctrl.ren3, issue_slots[0].in_uop.bits.fp_ctrl.ren3 connect slots_0.io.in_uop.bits.fp_ctrl.ren2, issue_slots[0].in_uop.bits.fp_ctrl.ren2 connect slots_0.io.in_uop.bits.fp_ctrl.ren1, issue_slots[0].in_uop.bits.fp_ctrl.ren1 connect slots_0.io.in_uop.bits.fp_ctrl.wen, issue_slots[0].in_uop.bits.fp_ctrl.wen connect slots_0.io.in_uop.bits.fp_ctrl.ldst, issue_slots[0].in_uop.bits.fp_ctrl.ldst connect slots_0.io.in_uop.bits.op2_sel, issue_slots[0].in_uop.bits.op2_sel connect slots_0.io.in_uop.bits.op1_sel, issue_slots[0].in_uop.bits.op1_sel connect slots_0.io.in_uop.bits.imm_packed, issue_slots[0].in_uop.bits.imm_packed connect slots_0.io.in_uop.bits.pimm, issue_slots[0].in_uop.bits.pimm connect slots_0.io.in_uop.bits.imm_sel, issue_slots[0].in_uop.bits.imm_sel connect slots_0.io.in_uop.bits.imm_rename, issue_slots[0].in_uop.bits.imm_rename connect slots_0.io.in_uop.bits.taken, issue_slots[0].in_uop.bits.taken connect slots_0.io.in_uop.bits.pc_lob, issue_slots[0].in_uop.bits.pc_lob connect slots_0.io.in_uop.bits.edge_inst, issue_slots[0].in_uop.bits.edge_inst connect slots_0.io.in_uop.bits.ftq_idx, issue_slots[0].in_uop.bits.ftq_idx connect slots_0.io.in_uop.bits.is_mov, issue_slots[0].in_uop.bits.is_mov connect slots_0.io.in_uop.bits.is_rocc, issue_slots[0].in_uop.bits.is_rocc connect slots_0.io.in_uop.bits.is_sys_pc2epc, issue_slots[0].in_uop.bits.is_sys_pc2epc connect slots_0.io.in_uop.bits.is_eret, issue_slots[0].in_uop.bits.is_eret connect slots_0.io.in_uop.bits.is_amo, issue_slots[0].in_uop.bits.is_amo connect slots_0.io.in_uop.bits.is_sfence, issue_slots[0].in_uop.bits.is_sfence connect slots_0.io.in_uop.bits.is_fencei, issue_slots[0].in_uop.bits.is_fencei connect slots_0.io.in_uop.bits.is_fence, issue_slots[0].in_uop.bits.is_fence connect slots_0.io.in_uop.bits.is_sfb, issue_slots[0].in_uop.bits.is_sfb connect slots_0.io.in_uop.bits.br_type, issue_slots[0].in_uop.bits.br_type connect slots_0.io.in_uop.bits.br_tag, issue_slots[0].in_uop.bits.br_tag connect slots_0.io.in_uop.bits.br_mask, issue_slots[0].in_uop.bits.br_mask connect slots_0.io.in_uop.bits.dis_col_sel, issue_slots[0].in_uop.bits.dis_col_sel connect slots_0.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[0].in_uop.bits.iw_p3_bypass_hint connect slots_0.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[0].in_uop.bits.iw_p2_bypass_hint connect slots_0.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[0].in_uop.bits.iw_p1_bypass_hint connect slots_0.io.in_uop.bits.iw_p2_speculative_child, issue_slots[0].in_uop.bits.iw_p2_speculative_child connect slots_0.io.in_uop.bits.iw_p1_speculative_child, issue_slots[0].in_uop.bits.iw_p1_speculative_child connect slots_0.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[0].in_uop.bits.iw_issued_partial_dgen connect slots_0.io.in_uop.bits.iw_issued_partial_agen, issue_slots[0].in_uop.bits.iw_issued_partial_agen connect slots_0.io.in_uop.bits.iw_issued, issue_slots[0].in_uop.bits.iw_issued connect slots_0.io.in_uop.bits.fu_code[0], issue_slots[0].in_uop.bits.fu_code[0] connect slots_0.io.in_uop.bits.fu_code[1], issue_slots[0].in_uop.bits.fu_code[1] connect slots_0.io.in_uop.bits.fu_code[2], issue_slots[0].in_uop.bits.fu_code[2] connect slots_0.io.in_uop.bits.fu_code[3], issue_slots[0].in_uop.bits.fu_code[3] connect slots_0.io.in_uop.bits.fu_code[4], issue_slots[0].in_uop.bits.fu_code[4] connect slots_0.io.in_uop.bits.fu_code[5], issue_slots[0].in_uop.bits.fu_code[5] connect slots_0.io.in_uop.bits.fu_code[6], issue_slots[0].in_uop.bits.fu_code[6] connect slots_0.io.in_uop.bits.fu_code[7], issue_slots[0].in_uop.bits.fu_code[7] connect slots_0.io.in_uop.bits.fu_code[8], issue_slots[0].in_uop.bits.fu_code[8] connect slots_0.io.in_uop.bits.fu_code[9], issue_slots[0].in_uop.bits.fu_code[9] connect slots_0.io.in_uop.bits.iq_type[0], issue_slots[0].in_uop.bits.iq_type[0] connect slots_0.io.in_uop.bits.iq_type[1], issue_slots[0].in_uop.bits.iq_type[1] connect slots_0.io.in_uop.bits.iq_type[2], issue_slots[0].in_uop.bits.iq_type[2] connect slots_0.io.in_uop.bits.iq_type[3], issue_slots[0].in_uop.bits.iq_type[3] connect slots_0.io.in_uop.bits.debug_pc, issue_slots[0].in_uop.bits.debug_pc connect slots_0.io.in_uop.bits.is_rvc, issue_slots[0].in_uop.bits.is_rvc connect slots_0.io.in_uop.bits.debug_inst, issue_slots[0].in_uop.bits.debug_inst connect slots_0.io.in_uop.bits.inst, issue_slots[0].in_uop.bits.inst connect slots_0.io.in_uop.valid, issue_slots[0].in_uop.valid connect issue_slots[0].iss_uop.debug_tsrc, slots_0.io.iss_uop.debug_tsrc connect issue_slots[0].iss_uop.debug_fsrc, slots_0.io.iss_uop.debug_fsrc connect issue_slots[0].iss_uop.bp_xcpt_if, slots_0.io.iss_uop.bp_xcpt_if connect issue_slots[0].iss_uop.bp_debug_if, slots_0.io.iss_uop.bp_debug_if connect issue_slots[0].iss_uop.xcpt_ma_if, slots_0.io.iss_uop.xcpt_ma_if connect issue_slots[0].iss_uop.xcpt_ae_if, slots_0.io.iss_uop.xcpt_ae_if connect issue_slots[0].iss_uop.xcpt_pf_if, slots_0.io.iss_uop.xcpt_pf_if connect issue_slots[0].iss_uop.fp_typ, slots_0.io.iss_uop.fp_typ connect issue_slots[0].iss_uop.fp_rm, slots_0.io.iss_uop.fp_rm connect issue_slots[0].iss_uop.fp_val, slots_0.io.iss_uop.fp_val connect issue_slots[0].iss_uop.fcn_op, slots_0.io.iss_uop.fcn_op connect issue_slots[0].iss_uop.fcn_dw, slots_0.io.iss_uop.fcn_dw connect issue_slots[0].iss_uop.frs3_en, slots_0.io.iss_uop.frs3_en connect issue_slots[0].iss_uop.lrs2_rtype, slots_0.io.iss_uop.lrs2_rtype connect issue_slots[0].iss_uop.lrs1_rtype, slots_0.io.iss_uop.lrs1_rtype connect issue_slots[0].iss_uop.dst_rtype, slots_0.io.iss_uop.dst_rtype connect issue_slots[0].iss_uop.lrs3, slots_0.io.iss_uop.lrs3 connect issue_slots[0].iss_uop.lrs2, slots_0.io.iss_uop.lrs2 connect issue_slots[0].iss_uop.lrs1, slots_0.io.iss_uop.lrs1 connect issue_slots[0].iss_uop.ldst, slots_0.io.iss_uop.ldst connect issue_slots[0].iss_uop.ldst_is_rs1, slots_0.io.iss_uop.ldst_is_rs1 connect issue_slots[0].iss_uop.csr_cmd, slots_0.io.iss_uop.csr_cmd connect issue_slots[0].iss_uop.flush_on_commit, slots_0.io.iss_uop.flush_on_commit connect issue_slots[0].iss_uop.is_unique, slots_0.io.iss_uop.is_unique connect issue_slots[0].iss_uop.uses_stq, slots_0.io.iss_uop.uses_stq connect issue_slots[0].iss_uop.uses_ldq, slots_0.io.iss_uop.uses_ldq connect issue_slots[0].iss_uop.mem_signed, slots_0.io.iss_uop.mem_signed connect issue_slots[0].iss_uop.mem_size, slots_0.io.iss_uop.mem_size connect issue_slots[0].iss_uop.mem_cmd, slots_0.io.iss_uop.mem_cmd connect issue_slots[0].iss_uop.exc_cause, slots_0.io.iss_uop.exc_cause connect issue_slots[0].iss_uop.exception, slots_0.io.iss_uop.exception connect issue_slots[0].iss_uop.stale_pdst, slots_0.io.iss_uop.stale_pdst connect issue_slots[0].iss_uop.ppred_busy, slots_0.io.iss_uop.ppred_busy connect issue_slots[0].iss_uop.prs3_busy, slots_0.io.iss_uop.prs3_busy connect issue_slots[0].iss_uop.prs2_busy, slots_0.io.iss_uop.prs2_busy connect issue_slots[0].iss_uop.prs1_busy, slots_0.io.iss_uop.prs1_busy connect issue_slots[0].iss_uop.ppred, slots_0.io.iss_uop.ppred connect issue_slots[0].iss_uop.prs3, slots_0.io.iss_uop.prs3 connect issue_slots[0].iss_uop.prs2, slots_0.io.iss_uop.prs2 connect issue_slots[0].iss_uop.prs1, slots_0.io.iss_uop.prs1 connect issue_slots[0].iss_uop.pdst, slots_0.io.iss_uop.pdst connect issue_slots[0].iss_uop.rxq_idx, slots_0.io.iss_uop.rxq_idx connect issue_slots[0].iss_uop.stq_idx, slots_0.io.iss_uop.stq_idx connect issue_slots[0].iss_uop.ldq_idx, slots_0.io.iss_uop.ldq_idx connect issue_slots[0].iss_uop.rob_idx, slots_0.io.iss_uop.rob_idx connect issue_slots[0].iss_uop.fp_ctrl.vec, slots_0.io.iss_uop.fp_ctrl.vec connect issue_slots[0].iss_uop.fp_ctrl.wflags, slots_0.io.iss_uop.fp_ctrl.wflags connect issue_slots[0].iss_uop.fp_ctrl.sqrt, slots_0.io.iss_uop.fp_ctrl.sqrt connect issue_slots[0].iss_uop.fp_ctrl.div, slots_0.io.iss_uop.fp_ctrl.div connect issue_slots[0].iss_uop.fp_ctrl.fma, slots_0.io.iss_uop.fp_ctrl.fma connect issue_slots[0].iss_uop.fp_ctrl.fastpipe, slots_0.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[0].iss_uop.fp_ctrl.toint, slots_0.io.iss_uop.fp_ctrl.toint connect issue_slots[0].iss_uop.fp_ctrl.fromint, slots_0.io.iss_uop.fp_ctrl.fromint connect issue_slots[0].iss_uop.fp_ctrl.typeTagOut, slots_0.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[0].iss_uop.fp_ctrl.typeTagIn, slots_0.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[0].iss_uop.fp_ctrl.swap23, slots_0.io.iss_uop.fp_ctrl.swap23 connect issue_slots[0].iss_uop.fp_ctrl.swap12, slots_0.io.iss_uop.fp_ctrl.swap12 connect issue_slots[0].iss_uop.fp_ctrl.ren3, slots_0.io.iss_uop.fp_ctrl.ren3 connect issue_slots[0].iss_uop.fp_ctrl.ren2, slots_0.io.iss_uop.fp_ctrl.ren2 connect issue_slots[0].iss_uop.fp_ctrl.ren1, slots_0.io.iss_uop.fp_ctrl.ren1 connect issue_slots[0].iss_uop.fp_ctrl.wen, slots_0.io.iss_uop.fp_ctrl.wen connect issue_slots[0].iss_uop.fp_ctrl.ldst, slots_0.io.iss_uop.fp_ctrl.ldst connect issue_slots[0].iss_uop.op2_sel, slots_0.io.iss_uop.op2_sel connect issue_slots[0].iss_uop.op1_sel, slots_0.io.iss_uop.op1_sel connect issue_slots[0].iss_uop.imm_packed, slots_0.io.iss_uop.imm_packed connect issue_slots[0].iss_uop.pimm, slots_0.io.iss_uop.pimm connect issue_slots[0].iss_uop.imm_sel, slots_0.io.iss_uop.imm_sel connect issue_slots[0].iss_uop.imm_rename, slots_0.io.iss_uop.imm_rename connect issue_slots[0].iss_uop.taken, slots_0.io.iss_uop.taken connect issue_slots[0].iss_uop.pc_lob, slots_0.io.iss_uop.pc_lob connect issue_slots[0].iss_uop.edge_inst, slots_0.io.iss_uop.edge_inst connect issue_slots[0].iss_uop.ftq_idx, slots_0.io.iss_uop.ftq_idx connect issue_slots[0].iss_uop.is_mov, slots_0.io.iss_uop.is_mov connect issue_slots[0].iss_uop.is_rocc, slots_0.io.iss_uop.is_rocc connect issue_slots[0].iss_uop.is_sys_pc2epc, slots_0.io.iss_uop.is_sys_pc2epc connect issue_slots[0].iss_uop.is_eret, slots_0.io.iss_uop.is_eret connect issue_slots[0].iss_uop.is_amo, slots_0.io.iss_uop.is_amo connect issue_slots[0].iss_uop.is_sfence, slots_0.io.iss_uop.is_sfence connect issue_slots[0].iss_uop.is_fencei, slots_0.io.iss_uop.is_fencei connect issue_slots[0].iss_uop.is_fence, slots_0.io.iss_uop.is_fence connect issue_slots[0].iss_uop.is_sfb, slots_0.io.iss_uop.is_sfb connect issue_slots[0].iss_uop.br_type, slots_0.io.iss_uop.br_type connect issue_slots[0].iss_uop.br_tag, slots_0.io.iss_uop.br_tag connect issue_slots[0].iss_uop.br_mask, slots_0.io.iss_uop.br_mask connect issue_slots[0].iss_uop.dis_col_sel, slots_0.io.iss_uop.dis_col_sel connect issue_slots[0].iss_uop.iw_p3_bypass_hint, slots_0.io.iss_uop.iw_p3_bypass_hint connect issue_slots[0].iss_uop.iw_p2_bypass_hint, slots_0.io.iss_uop.iw_p2_bypass_hint connect issue_slots[0].iss_uop.iw_p1_bypass_hint, slots_0.io.iss_uop.iw_p1_bypass_hint connect issue_slots[0].iss_uop.iw_p2_speculative_child, slots_0.io.iss_uop.iw_p2_speculative_child connect issue_slots[0].iss_uop.iw_p1_speculative_child, slots_0.io.iss_uop.iw_p1_speculative_child connect issue_slots[0].iss_uop.iw_issued_partial_dgen, slots_0.io.iss_uop.iw_issued_partial_dgen connect issue_slots[0].iss_uop.iw_issued_partial_agen, slots_0.io.iss_uop.iw_issued_partial_agen connect issue_slots[0].iss_uop.iw_issued, slots_0.io.iss_uop.iw_issued connect issue_slots[0].iss_uop.fu_code[0], slots_0.io.iss_uop.fu_code[0] connect issue_slots[0].iss_uop.fu_code[1], slots_0.io.iss_uop.fu_code[1] connect issue_slots[0].iss_uop.fu_code[2], slots_0.io.iss_uop.fu_code[2] connect issue_slots[0].iss_uop.fu_code[3], slots_0.io.iss_uop.fu_code[3] connect issue_slots[0].iss_uop.fu_code[4], slots_0.io.iss_uop.fu_code[4] connect issue_slots[0].iss_uop.fu_code[5], slots_0.io.iss_uop.fu_code[5] connect issue_slots[0].iss_uop.fu_code[6], slots_0.io.iss_uop.fu_code[6] connect issue_slots[0].iss_uop.fu_code[7], slots_0.io.iss_uop.fu_code[7] connect issue_slots[0].iss_uop.fu_code[8], slots_0.io.iss_uop.fu_code[8] connect issue_slots[0].iss_uop.fu_code[9], slots_0.io.iss_uop.fu_code[9] connect issue_slots[0].iss_uop.iq_type[0], slots_0.io.iss_uop.iq_type[0] connect issue_slots[0].iss_uop.iq_type[1], slots_0.io.iss_uop.iq_type[1] connect issue_slots[0].iss_uop.iq_type[2], slots_0.io.iss_uop.iq_type[2] connect issue_slots[0].iss_uop.iq_type[3], slots_0.io.iss_uop.iq_type[3] connect issue_slots[0].iss_uop.debug_pc, slots_0.io.iss_uop.debug_pc connect issue_slots[0].iss_uop.is_rvc, slots_0.io.iss_uop.is_rvc connect issue_slots[0].iss_uop.debug_inst, slots_0.io.iss_uop.debug_inst connect issue_slots[0].iss_uop.inst, slots_0.io.iss_uop.inst connect slots_0.io.grant, issue_slots[0].grant connect issue_slots[0].request, slots_0.io.request connect issue_slots[0].will_be_valid, slots_0.io.will_be_valid connect issue_slots[0].valid, slots_0.io.valid connect slots_1.io.child_rebusys, issue_slots[1].child_rebusys connect slots_1.io.pred_wakeup_port.bits, issue_slots[1].pred_wakeup_port.bits connect slots_1.io.pred_wakeup_port.valid, issue_slots[1].pred_wakeup_port.valid connect slots_1.io.wakeup_ports[0].bits.rebusy, issue_slots[1].wakeup_ports[0].bits.rebusy connect slots_1.io.wakeup_ports[0].bits.speculative_mask, issue_slots[1].wakeup_ports[0].bits.speculative_mask connect slots_1.io.wakeup_ports[0].bits.bypassable, issue_slots[1].wakeup_ports[0].bits.bypassable connect slots_1.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[0].bits.uop.debug_tsrc connect slots_1.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[0].bits.uop.debug_fsrc connect slots_1.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_1.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[0].bits.uop.bp_debug_if connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_1.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[1].wakeup_ports[0].bits.uop.fp_typ connect slots_1.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[1].wakeup_ports[0].bits.uop.fp_rm connect slots_1.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[1].wakeup_ports[0].bits.uop.fp_val connect slots_1.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[1].wakeup_ports[0].bits.uop.fcn_op connect slots_1.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[0].bits.uop.fcn_dw connect slots_1.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[1].wakeup_ports[0].bits.uop.frs3_en connect slots_1.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_1.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_1.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[0].bits.uop.dst_rtype connect slots_1.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[1].wakeup_ports[0].bits.uop.lrs3 connect slots_1.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[1].wakeup_ports[0].bits.uop.lrs2 connect slots_1.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[1].wakeup_ports[0].bits.uop.lrs1 connect slots_1.io.wakeup_ports[0].bits.uop.ldst, issue_slots[1].wakeup_ports[0].bits.uop.ldst connect slots_1.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_1.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[0].bits.uop.csr_cmd connect slots_1.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[0].bits.uop.flush_on_commit connect slots_1.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[1].wakeup_ports[0].bits.uop.is_unique connect slots_1.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[1].wakeup_ports[0].bits.uop.uses_stq connect slots_1.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[0].bits.uop.uses_ldq connect slots_1.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[1].wakeup_ports[0].bits.uop.mem_signed connect slots_1.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[1].wakeup_ports[0].bits.uop.mem_size connect slots_1.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[0].bits.uop.mem_cmd connect slots_1.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[1].wakeup_ports[0].bits.uop.exc_cause connect slots_1.io.wakeup_ports[0].bits.uop.exception, issue_slots[1].wakeup_ports[0].bits.uop.exception connect slots_1.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[0].bits.uop.stale_pdst connect slots_1.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[0].bits.uop.ppred_busy connect slots_1.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs3_busy connect slots_1.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs2_busy connect slots_1.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs1_busy connect slots_1.io.wakeup_ports[0].bits.uop.ppred, issue_slots[1].wakeup_ports[0].bits.uop.ppred connect slots_1.io.wakeup_ports[0].bits.uop.prs3, issue_slots[1].wakeup_ports[0].bits.uop.prs3 connect slots_1.io.wakeup_ports[0].bits.uop.prs2, issue_slots[1].wakeup_ports[0].bits.uop.prs2 connect slots_1.io.wakeup_ports[0].bits.uop.prs1, issue_slots[1].wakeup_ports[0].bits.uop.prs1 connect slots_1.io.wakeup_ports[0].bits.uop.pdst, issue_slots[1].wakeup_ports[0].bits.uop.pdst connect slots_1.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[0].bits.uop.rxq_idx connect slots_1.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[1].wakeup_ports[0].bits.uop.stq_idx connect slots_1.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[0].bits.uop.ldq_idx connect slots_1.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[1].wakeup_ports[0].bits.uop.rob_idx connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_1.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[1].wakeup_ports[0].bits.uop.op2_sel connect slots_1.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[1].wakeup_ports[0].bits.uop.op1_sel connect slots_1.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[1].wakeup_ports[0].bits.uop.imm_packed connect slots_1.io.wakeup_ports[0].bits.uop.pimm, issue_slots[1].wakeup_ports[0].bits.uop.pimm connect slots_1.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[1].wakeup_ports[0].bits.uop.imm_sel connect slots_1.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[1].wakeup_ports[0].bits.uop.imm_rename connect slots_1.io.wakeup_ports[0].bits.uop.taken, issue_slots[1].wakeup_ports[0].bits.uop.taken connect slots_1.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[1].wakeup_ports[0].bits.uop.pc_lob connect slots_1.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[1].wakeup_ports[0].bits.uop.edge_inst connect slots_1.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[0].bits.uop.ftq_idx connect slots_1.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[1].wakeup_ports[0].bits.uop.is_mov connect slots_1.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[1].wakeup_ports[0].bits.uop.is_rocc connect slots_1.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_1.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[1].wakeup_ports[0].bits.uop.is_eret connect slots_1.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[1].wakeup_ports[0].bits.uop.is_amo connect slots_1.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[1].wakeup_ports[0].bits.uop.is_sfence connect slots_1.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[1].wakeup_ports[0].bits.uop.is_fencei connect slots_1.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[1].wakeup_ports[0].bits.uop.is_fence connect slots_1.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[1].wakeup_ports[0].bits.uop.is_sfb connect slots_1.io.wakeup_ports[0].bits.uop.br_type, issue_slots[1].wakeup_ports[0].bits.uop.br_type connect slots_1.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[1].wakeup_ports[0].bits.uop.br_tag connect slots_1.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[1].wakeup_ports[0].bits.uop.br_mask connect slots_1.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[0].bits.uop.dis_col_sel connect slots_1.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_1.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_1.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_1.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_1.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[0] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[1] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[2] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[3] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[4] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[5] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[6] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[7] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[8] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[9] connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[0] connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[1] connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[2] connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[3] connect slots_1.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[1].wakeup_ports[0].bits.uop.debug_pc connect slots_1.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[1].wakeup_ports[0].bits.uop.is_rvc connect slots_1.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[1].wakeup_ports[0].bits.uop.debug_inst connect slots_1.io.wakeup_ports[0].bits.uop.inst, issue_slots[1].wakeup_ports[0].bits.uop.inst connect slots_1.io.wakeup_ports[0].valid, issue_slots[1].wakeup_ports[0].valid connect slots_1.io.wakeup_ports[1].bits.rebusy, issue_slots[1].wakeup_ports[1].bits.rebusy connect slots_1.io.wakeup_ports[1].bits.speculative_mask, issue_slots[1].wakeup_ports[1].bits.speculative_mask connect slots_1.io.wakeup_ports[1].bits.bypassable, issue_slots[1].wakeup_ports[1].bits.bypassable connect slots_1.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[1].bits.uop.debug_tsrc connect slots_1.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[1].bits.uop.debug_fsrc connect slots_1.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_1.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[1].bits.uop.bp_debug_if connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_1.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[1].wakeup_ports[1].bits.uop.fp_typ connect slots_1.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[1].wakeup_ports[1].bits.uop.fp_rm connect slots_1.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[1].wakeup_ports[1].bits.uop.fp_val connect slots_1.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[1].wakeup_ports[1].bits.uop.fcn_op connect slots_1.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[1].bits.uop.fcn_dw connect slots_1.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[1].wakeup_ports[1].bits.uop.frs3_en connect slots_1.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_1.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_1.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[1].bits.uop.dst_rtype connect slots_1.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[1].wakeup_ports[1].bits.uop.lrs3 connect slots_1.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[1].wakeup_ports[1].bits.uop.lrs2 connect slots_1.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[1].wakeup_ports[1].bits.uop.lrs1 connect slots_1.io.wakeup_ports[1].bits.uop.ldst, issue_slots[1].wakeup_ports[1].bits.uop.ldst connect slots_1.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_1.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[1].bits.uop.csr_cmd connect slots_1.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[1].bits.uop.flush_on_commit connect slots_1.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[1].wakeup_ports[1].bits.uop.is_unique connect slots_1.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[1].wakeup_ports[1].bits.uop.uses_stq connect slots_1.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[1].bits.uop.uses_ldq connect slots_1.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[1].wakeup_ports[1].bits.uop.mem_signed connect slots_1.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[1].wakeup_ports[1].bits.uop.mem_size connect slots_1.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[1].bits.uop.mem_cmd connect slots_1.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[1].wakeup_ports[1].bits.uop.exc_cause connect slots_1.io.wakeup_ports[1].bits.uop.exception, issue_slots[1].wakeup_ports[1].bits.uop.exception connect slots_1.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[1].bits.uop.stale_pdst connect slots_1.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[1].bits.uop.ppred_busy connect slots_1.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs3_busy connect slots_1.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs2_busy connect slots_1.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs1_busy connect slots_1.io.wakeup_ports[1].bits.uop.ppred, issue_slots[1].wakeup_ports[1].bits.uop.ppred connect slots_1.io.wakeup_ports[1].bits.uop.prs3, issue_slots[1].wakeup_ports[1].bits.uop.prs3 connect slots_1.io.wakeup_ports[1].bits.uop.prs2, issue_slots[1].wakeup_ports[1].bits.uop.prs2 connect slots_1.io.wakeup_ports[1].bits.uop.prs1, issue_slots[1].wakeup_ports[1].bits.uop.prs1 connect slots_1.io.wakeup_ports[1].bits.uop.pdst, issue_slots[1].wakeup_ports[1].bits.uop.pdst connect slots_1.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[1].bits.uop.rxq_idx connect slots_1.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[1].wakeup_ports[1].bits.uop.stq_idx connect slots_1.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[1].bits.uop.ldq_idx connect slots_1.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[1].wakeup_ports[1].bits.uop.rob_idx connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_1.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[1].wakeup_ports[1].bits.uop.op2_sel connect slots_1.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[1].wakeup_ports[1].bits.uop.op1_sel connect slots_1.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[1].wakeup_ports[1].bits.uop.imm_packed connect slots_1.io.wakeup_ports[1].bits.uop.pimm, issue_slots[1].wakeup_ports[1].bits.uop.pimm connect slots_1.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[1].wakeup_ports[1].bits.uop.imm_sel connect slots_1.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[1].wakeup_ports[1].bits.uop.imm_rename connect slots_1.io.wakeup_ports[1].bits.uop.taken, issue_slots[1].wakeup_ports[1].bits.uop.taken connect slots_1.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[1].wakeup_ports[1].bits.uop.pc_lob connect slots_1.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[1].wakeup_ports[1].bits.uop.edge_inst connect slots_1.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[1].bits.uop.ftq_idx connect slots_1.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[1].wakeup_ports[1].bits.uop.is_mov connect slots_1.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[1].wakeup_ports[1].bits.uop.is_rocc connect slots_1.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_1.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[1].wakeup_ports[1].bits.uop.is_eret connect slots_1.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[1].wakeup_ports[1].bits.uop.is_amo connect slots_1.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[1].wakeup_ports[1].bits.uop.is_sfence connect slots_1.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[1].wakeup_ports[1].bits.uop.is_fencei connect slots_1.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[1].wakeup_ports[1].bits.uop.is_fence connect slots_1.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[1].wakeup_ports[1].bits.uop.is_sfb connect slots_1.io.wakeup_ports[1].bits.uop.br_type, issue_slots[1].wakeup_ports[1].bits.uop.br_type connect slots_1.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[1].wakeup_ports[1].bits.uop.br_tag connect slots_1.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[1].wakeup_ports[1].bits.uop.br_mask connect slots_1.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[1].bits.uop.dis_col_sel connect slots_1.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_1.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_1.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_1.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_1.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[0] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[1] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[2] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[3] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[4] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[5] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[6] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[7] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[8] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[9] connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[0] connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[1] connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[2] connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[3] connect slots_1.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[1].wakeup_ports[1].bits.uop.debug_pc connect slots_1.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[1].wakeup_ports[1].bits.uop.is_rvc connect slots_1.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[1].wakeup_ports[1].bits.uop.debug_inst connect slots_1.io.wakeup_ports[1].bits.uop.inst, issue_slots[1].wakeup_ports[1].bits.uop.inst connect slots_1.io.wakeup_ports[1].valid, issue_slots[1].wakeup_ports[1].valid connect slots_1.io.wakeup_ports[2].bits.rebusy, issue_slots[1].wakeup_ports[2].bits.rebusy connect slots_1.io.wakeup_ports[2].bits.speculative_mask, issue_slots[1].wakeup_ports[2].bits.speculative_mask connect slots_1.io.wakeup_ports[2].bits.bypassable, issue_slots[1].wakeup_ports[2].bits.bypassable connect slots_1.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[2].bits.uop.debug_tsrc connect slots_1.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[2].bits.uop.debug_fsrc connect slots_1.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_1.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[2].bits.uop.bp_debug_if connect slots_1.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_1.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_1.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_1.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[1].wakeup_ports[2].bits.uop.fp_typ connect slots_1.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[1].wakeup_ports[2].bits.uop.fp_rm connect slots_1.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[1].wakeup_ports[2].bits.uop.fp_val connect slots_1.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[1].wakeup_ports[2].bits.uop.fcn_op connect slots_1.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[2].bits.uop.fcn_dw connect slots_1.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[1].wakeup_ports[2].bits.uop.frs3_en connect slots_1.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_1.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_1.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[2].bits.uop.dst_rtype connect slots_1.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[1].wakeup_ports[2].bits.uop.lrs3 connect slots_1.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[1].wakeup_ports[2].bits.uop.lrs2 connect slots_1.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[1].wakeup_ports[2].bits.uop.lrs1 connect slots_1.io.wakeup_ports[2].bits.uop.ldst, issue_slots[1].wakeup_ports[2].bits.uop.ldst connect slots_1.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_1.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[2].bits.uop.csr_cmd connect slots_1.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[2].bits.uop.flush_on_commit connect slots_1.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[1].wakeup_ports[2].bits.uop.is_unique connect slots_1.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[1].wakeup_ports[2].bits.uop.uses_stq connect slots_1.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[2].bits.uop.uses_ldq connect slots_1.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[1].wakeup_ports[2].bits.uop.mem_signed connect slots_1.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[1].wakeup_ports[2].bits.uop.mem_size connect slots_1.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[2].bits.uop.mem_cmd connect slots_1.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[1].wakeup_ports[2].bits.uop.exc_cause connect slots_1.io.wakeup_ports[2].bits.uop.exception, issue_slots[1].wakeup_ports[2].bits.uop.exception connect slots_1.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[2].bits.uop.stale_pdst connect slots_1.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[2].bits.uop.ppred_busy connect slots_1.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[2].bits.uop.prs3_busy connect slots_1.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[2].bits.uop.prs2_busy connect slots_1.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[2].bits.uop.prs1_busy connect slots_1.io.wakeup_ports[2].bits.uop.ppred, issue_slots[1].wakeup_ports[2].bits.uop.ppred connect slots_1.io.wakeup_ports[2].bits.uop.prs3, issue_slots[1].wakeup_ports[2].bits.uop.prs3 connect slots_1.io.wakeup_ports[2].bits.uop.prs2, issue_slots[1].wakeup_ports[2].bits.uop.prs2 connect slots_1.io.wakeup_ports[2].bits.uop.prs1, issue_slots[1].wakeup_ports[2].bits.uop.prs1 connect slots_1.io.wakeup_ports[2].bits.uop.pdst, issue_slots[1].wakeup_ports[2].bits.uop.pdst connect slots_1.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[2].bits.uop.rxq_idx connect slots_1.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[1].wakeup_ports[2].bits.uop.stq_idx connect slots_1.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[2].bits.uop.ldq_idx connect slots_1.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[1].wakeup_ports[2].bits.uop.rob_idx connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_1.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[1].wakeup_ports[2].bits.uop.op2_sel connect slots_1.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[1].wakeup_ports[2].bits.uop.op1_sel connect slots_1.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[1].wakeup_ports[2].bits.uop.imm_packed connect slots_1.io.wakeup_ports[2].bits.uop.pimm, issue_slots[1].wakeup_ports[2].bits.uop.pimm connect slots_1.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[1].wakeup_ports[2].bits.uop.imm_sel connect slots_1.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[1].wakeup_ports[2].bits.uop.imm_rename connect slots_1.io.wakeup_ports[2].bits.uop.taken, issue_slots[1].wakeup_ports[2].bits.uop.taken connect slots_1.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[1].wakeup_ports[2].bits.uop.pc_lob connect slots_1.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[1].wakeup_ports[2].bits.uop.edge_inst connect slots_1.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[2].bits.uop.ftq_idx connect slots_1.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[1].wakeup_ports[2].bits.uop.is_mov connect slots_1.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[1].wakeup_ports[2].bits.uop.is_rocc connect slots_1.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_1.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[1].wakeup_ports[2].bits.uop.is_eret connect slots_1.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[1].wakeup_ports[2].bits.uop.is_amo connect slots_1.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[1].wakeup_ports[2].bits.uop.is_sfence connect slots_1.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[1].wakeup_ports[2].bits.uop.is_fencei connect slots_1.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[1].wakeup_ports[2].bits.uop.is_fence connect slots_1.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[1].wakeup_ports[2].bits.uop.is_sfb connect slots_1.io.wakeup_ports[2].bits.uop.br_type, issue_slots[1].wakeup_ports[2].bits.uop.br_type connect slots_1.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[1].wakeup_ports[2].bits.uop.br_tag connect slots_1.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[1].wakeup_ports[2].bits.uop.br_mask connect slots_1.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[2].bits.uop.dis_col_sel connect slots_1.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_1.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_1.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_1.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_1.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_1.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_1.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_1.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[1].wakeup_ports[2].bits.uop.iw_issued connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[0] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[1] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[2] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[3] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[4] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[5] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[6] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[7] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[8] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[9] connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[0] connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[1] connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[2] connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[3] connect slots_1.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[1].wakeup_ports[2].bits.uop.debug_pc connect slots_1.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[1].wakeup_ports[2].bits.uop.is_rvc connect slots_1.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[1].wakeup_ports[2].bits.uop.debug_inst connect slots_1.io.wakeup_ports[2].bits.uop.inst, issue_slots[1].wakeup_ports[2].bits.uop.inst connect slots_1.io.wakeup_ports[2].valid, issue_slots[1].wakeup_ports[2].valid connect slots_1.io.wakeup_ports[3].bits.rebusy, issue_slots[1].wakeup_ports[3].bits.rebusy connect slots_1.io.wakeup_ports[3].bits.speculative_mask, issue_slots[1].wakeup_ports[3].bits.speculative_mask connect slots_1.io.wakeup_ports[3].bits.bypassable, issue_slots[1].wakeup_ports[3].bits.bypassable connect slots_1.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[3].bits.uop.debug_tsrc connect slots_1.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[3].bits.uop.debug_fsrc connect slots_1.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_1.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[3].bits.uop.bp_debug_if connect slots_1.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_1.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_1.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_1.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[1].wakeup_ports[3].bits.uop.fp_typ connect slots_1.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[1].wakeup_ports[3].bits.uop.fp_rm connect slots_1.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[1].wakeup_ports[3].bits.uop.fp_val connect slots_1.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[1].wakeup_ports[3].bits.uop.fcn_op connect slots_1.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[3].bits.uop.fcn_dw connect slots_1.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[1].wakeup_ports[3].bits.uop.frs3_en connect slots_1.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_1.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_1.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[3].bits.uop.dst_rtype connect slots_1.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[1].wakeup_ports[3].bits.uop.lrs3 connect slots_1.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[1].wakeup_ports[3].bits.uop.lrs2 connect slots_1.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[1].wakeup_ports[3].bits.uop.lrs1 connect slots_1.io.wakeup_ports[3].bits.uop.ldst, issue_slots[1].wakeup_ports[3].bits.uop.ldst connect slots_1.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_1.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[3].bits.uop.csr_cmd connect slots_1.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[3].bits.uop.flush_on_commit connect slots_1.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[1].wakeup_ports[3].bits.uop.is_unique connect slots_1.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[1].wakeup_ports[3].bits.uop.uses_stq connect slots_1.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[3].bits.uop.uses_ldq connect slots_1.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[1].wakeup_ports[3].bits.uop.mem_signed connect slots_1.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[1].wakeup_ports[3].bits.uop.mem_size connect slots_1.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[3].bits.uop.mem_cmd connect slots_1.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[1].wakeup_ports[3].bits.uop.exc_cause connect slots_1.io.wakeup_ports[3].bits.uop.exception, issue_slots[1].wakeup_ports[3].bits.uop.exception connect slots_1.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[3].bits.uop.stale_pdst connect slots_1.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[3].bits.uop.ppred_busy connect slots_1.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[3].bits.uop.prs3_busy connect slots_1.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[3].bits.uop.prs2_busy connect slots_1.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[3].bits.uop.prs1_busy connect slots_1.io.wakeup_ports[3].bits.uop.ppred, issue_slots[1].wakeup_ports[3].bits.uop.ppred connect slots_1.io.wakeup_ports[3].bits.uop.prs3, issue_slots[1].wakeup_ports[3].bits.uop.prs3 connect slots_1.io.wakeup_ports[3].bits.uop.prs2, issue_slots[1].wakeup_ports[3].bits.uop.prs2 connect slots_1.io.wakeup_ports[3].bits.uop.prs1, issue_slots[1].wakeup_ports[3].bits.uop.prs1 connect slots_1.io.wakeup_ports[3].bits.uop.pdst, issue_slots[1].wakeup_ports[3].bits.uop.pdst connect slots_1.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[3].bits.uop.rxq_idx connect slots_1.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[1].wakeup_ports[3].bits.uop.stq_idx connect slots_1.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[3].bits.uop.ldq_idx connect slots_1.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[1].wakeup_ports[3].bits.uop.rob_idx connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_1.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[1].wakeup_ports[3].bits.uop.op2_sel connect slots_1.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[1].wakeup_ports[3].bits.uop.op1_sel connect slots_1.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[1].wakeup_ports[3].bits.uop.imm_packed connect slots_1.io.wakeup_ports[3].bits.uop.pimm, issue_slots[1].wakeup_ports[3].bits.uop.pimm connect slots_1.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[1].wakeup_ports[3].bits.uop.imm_sel connect slots_1.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[1].wakeup_ports[3].bits.uop.imm_rename connect slots_1.io.wakeup_ports[3].bits.uop.taken, issue_slots[1].wakeup_ports[3].bits.uop.taken connect slots_1.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[1].wakeup_ports[3].bits.uop.pc_lob connect slots_1.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[1].wakeup_ports[3].bits.uop.edge_inst connect slots_1.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[3].bits.uop.ftq_idx connect slots_1.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[1].wakeup_ports[3].bits.uop.is_mov connect slots_1.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[1].wakeup_ports[3].bits.uop.is_rocc connect slots_1.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_1.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[1].wakeup_ports[3].bits.uop.is_eret connect slots_1.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[1].wakeup_ports[3].bits.uop.is_amo connect slots_1.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[1].wakeup_ports[3].bits.uop.is_sfence connect slots_1.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[1].wakeup_ports[3].bits.uop.is_fencei connect slots_1.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[1].wakeup_ports[3].bits.uop.is_fence connect slots_1.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[1].wakeup_ports[3].bits.uop.is_sfb connect slots_1.io.wakeup_ports[3].bits.uop.br_type, issue_slots[1].wakeup_ports[3].bits.uop.br_type connect slots_1.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[1].wakeup_ports[3].bits.uop.br_tag connect slots_1.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[1].wakeup_ports[3].bits.uop.br_mask connect slots_1.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[3].bits.uop.dis_col_sel connect slots_1.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_1.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_1.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_1.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_1.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_1.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_1.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_1.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[1].wakeup_ports[3].bits.uop.iw_issued connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[0] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[1] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[2] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[3] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[4] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[5] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[6] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[7] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[8] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[9] connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[0] connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[1] connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[2] connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[3] connect slots_1.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[1].wakeup_ports[3].bits.uop.debug_pc connect slots_1.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[1].wakeup_ports[3].bits.uop.is_rvc connect slots_1.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[1].wakeup_ports[3].bits.uop.debug_inst connect slots_1.io.wakeup_ports[3].bits.uop.inst, issue_slots[1].wakeup_ports[3].bits.uop.inst connect slots_1.io.wakeup_ports[3].valid, issue_slots[1].wakeup_ports[3].valid connect slots_1.io.wakeup_ports[4].bits.rebusy, issue_slots[1].wakeup_ports[4].bits.rebusy connect slots_1.io.wakeup_ports[4].bits.speculative_mask, issue_slots[1].wakeup_ports[4].bits.speculative_mask connect slots_1.io.wakeup_ports[4].bits.bypassable, issue_slots[1].wakeup_ports[4].bits.bypassable connect slots_1.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[4].bits.uop.debug_tsrc connect slots_1.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[4].bits.uop.debug_fsrc connect slots_1.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_1.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[4].bits.uop.bp_debug_if connect slots_1.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_1.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_1.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_1.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[1].wakeup_ports[4].bits.uop.fp_typ connect slots_1.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[1].wakeup_ports[4].bits.uop.fp_rm connect slots_1.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[1].wakeup_ports[4].bits.uop.fp_val connect slots_1.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[1].wakeup_ports[4].bits.uop.fcn_op connect slots_1.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[4].bits.uop.fcn_dw connect slots_1.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[1].wakeup_ports[4].bits.uop.frs3_en connect slots_1.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_1.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_1.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[4].bits.uop.dst_rtype connect slots_1.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[1].wakeup_ports[4].bits.uop.lrs3 connect slots_1.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[1].wakeup_ports[4].bits.uop.lrs2 connect slots_1.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[1].wakeup_ports[4].bits.uop.lrs1 connect slots_1.io.wakeup_ports[4].bits.uop.ldst, issue_slots[1].wakeup_ports[4].bits.uop.ldst connect slots_1.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_1.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[4].bits.uop.csr_cmd connect slots_1.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[4].bits.uop.flush_on_commit connect slots_1.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[1].wakeup_ports[4].bits.uop.is_unique connect slots_1.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[1].wakeup_ports[4].bits.uop.uses_stq connect slots_1.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[4].bits.uop.uses_ldq connect slots_1.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[1].wakeup_ports[4].bits.uop.mem_signed connect slots_1.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[1].wakeup_ports[4].bits.uop.mem_size connect slots_1.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[4].bits.uop.mem_cmd connect slots_1.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[1].wakeup_ports[4].bits.uop.exc_cause connect slots_1.io.wakeup_ports[4].bits.uop.exception, issue_slots[1].wakeup_ports[4].bits.uop.exception connect slots_1.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[4].bits.uop.stale_pdst connect slots_1.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[4].bits.uop.ppred_busy connect slots_1.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[4].bits.uop.prs3_busy connect slots_1.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[4].bits.uop.prs2_busy connect slots_1.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[4].bits.uop.prs1_busy connect slots_1.io.wakeup_ports[4].bits.uop.ppred, issue_slots[1].wakeup_ports[4].bits.uop.ppred connect slots_1.io.wakeup_ports[4].bits.uop.prs3, issue_slots[1].wakeup_ports[4].bits.uop.prs3 connect slots_1.io.wakeup_ports[4].bits.uop.prs2, issue_slots[1].wakeup_ports[4].bits.uop.prs2 connect slots_1.io.wakeup_ports[4].bits.uop.prs1, issue_slots[1].wakeup_ports[4].bits.uop.prs1 connect slots_1.io.wakeup_ports[4].bits.uop.pdst, issue_slots[1].wakeup_ports[4].bits.uop.pdst connect slots_1.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[4].bits.uop.rxq_idx connect slots_1.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[1].wakeup_ports[4].bits.uop.stq_idx connect slots_1.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[4].bits.uop.ldq_idx connect slots_1.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[1].wakeup_ports[4].bits.uop.rob_idx connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_1.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[1].wakeup_ports[4].bits.uop.op2_sel connect slots_1.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[1].wakeup_ports[4].bits.uop.op1_sel connect slots_1.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[1].wakeup_ports[4].bits.uop.imm_packed connect slots_1.io.wakeup_ports[4].bits.uop.pimm, issue_slots[1].wakeup_ports[4].bits.uop.pimm connect slots_1.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[1].wakeup_ports[4].bits.uop.imm_sel connect slots_1.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[1].wakeup_ports[4].bits.uop.imm_rename connect slots_1.io.wakeup_ports[4].bits.uop.taken, issue_slots[1].wakeup_ports[4].bits.uop.taken connect slots_1.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[1].wakeup_ports[4].bits.uop.pc_lob connect slots_1.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[1].wakeup_ports[4].bits.uop.edge_inst connect slots_1.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[4].bits.uop.ftq_idx connect slots_1.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[1].wakeup_ports[4].bits.uop.is_mov connect slots_1.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[1].wakeup_ports[4].bits.uop.is_rocc connect slots_1.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_1.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[1].wakeup_ports[4].bits.uop.is_eret connect slots_1.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[1].wakeup_ports[4].bits.uop.is_amo connect slots_1.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[1].wakeup_ports[4].bits.uop.is_sfence connect slots_1.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[1].wakeup_ports[4].bits.uop.is_fencei connect slots_1.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[1].wakeup_ports[4].bits.uop.is_fence connect slots_1.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[1].wakeup_ports[4].bits.uop.is_sfb connect slots_1.io.wakeup_ports[4].bits.uop.br_type, issue_slots[1].wakeup_ports[4].bits.uop.br_type connect slots_1.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[1].wakeup_ports[4].bits.uop.br_tag connect slots_1.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[1].wakeup_ports[4].bits.uop.br_mask connect slots_1.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[4].bits.uop.dis_col_sel connect slots_1.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_1.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_1.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_1.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_1.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_1.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_1.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_1.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[1].wakeup_ports[4].bits.uop.iw_issued connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[0] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[1] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[2] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[3] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[4] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[5] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[6] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[7] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[8] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[9] connect slots_1.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[4].bits.uop.iq_type[0] connect slots_1.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[4].bits.uop.iq_type[1] connect slots_1.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[4].bits.uop.iq_type[2] connect slots_1.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[4].bits.uop.iq_type[3] connect slots_1.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[1].wakeup_ports[4].bits.uop.debug_pc connect slots_1.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[1].wakeup_ports[4].bits.uop.is_rvc connect slots_1.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[1].wakeup_ports[4].bits.uop.debug_inst connect slots_1.io.wakeup_ports[4].bits.uop.inst, issue_slots[1].wakeup_ports[4].bits.uop.inst connect slots_1.io.wakeup_ports[4].valid, issue_slots[1].wakeup_ports[4].valid connect slots_1.io.squash_grant, issue_slots[1].squash_grant connect slots_1.io.clear, issue_slots[1].clear connect slots_1.io.kill, issue_slots[1].kill connect slots_1.io.brupdate.b2.target_offset, issue_slots[1].brupdate.b2.target_offset connect slots_1.io.brupdate.b2.jalr_target, issue_slots[1].brupdate.b2.jalr_target connect slots_1.io.brupdate.b2.pc_sel, issue_slots[1].brupdate.b2.pc_sel connect slots_1.io.brupdate.b2.cfi_type, issue_slots[1].brupdate.b2.cfi_type connect slots_1.io.brupdate.b2.taken, issue_slots[1].brupdate.b2.taken connect slots_1.io.brupdate.b2.mispredict, issue_slots[1].brupdate.b2.mispredict connect slots_1.io.brupdate.b2.uop.debug_tsrc, issue_slots[1].brupdate.b2.uop.debug_tsrc connect slots_1.io.brupdate.b2.uop.debug_fsrc, issue_slots[1].brupdate.b2.uop.debug_fsrc connect slots_1.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[1].brupdate.b2.uop.bp_xcpt_if connect slots_1.io.brupdate.b2.uop.bp_debug_if, issue_slots[1].brupdate.b2.uop.bp_debug_if connect slots_1.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[1].brupdate.b2.uop.xcpt_ma_if connect slots_1.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[1].brupdate.b2.uop.xcpt_ae_if connect slots_1.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[1].brupdate.b2.uop.xcpt_pf_if connect slots_1.io.brupdate.b2.uop.fp_typ, issue_slots[1].brupdate.b2.uop.fp_typ connect slots_1.io.brupdate.b2.uop.fp_rm, issue_slots[1].brupdate.b2.uop.fp_rm connect slots_1.io.brupdate.b2.uop.fp_val, issue_slots[1].brupdate.b2.uop.fp_val connect slots_1.io.brupdate.b2.uop.fcn_op, issue_slots[1].brupdate.b2.uop.fcn_op connect slots_1.io.brupdate.b2.uop.fcn_dw, issue_slots[1].brupdate.b2.uop.fcn_dw connect slots_1.io.brupdate.b2.uop.frs3_en, issue_slots[1].brupdate.b2.uop.frs3_en connect slots_1.io.brupdate.b2.uop.lrs2_rtype, issue_slots[1].brupdate.b2.uop.lrs2_rtype connect slots_1.io.brupdate.b2.uop.lrs1_rtype, issue_slots[1].brupdate.b2.uop.lrs1_rtype connect slots_1.io.brupdate.b2.uop.dst_rtype, issue_slots[1].brupdate.b2.uop.dst_rtype connect slots_1.io.brupdate.b2.uop.lrs3, issue_slots[1].brupdate.b2.uop.lrs3 connect slots_1.io.brupdate.b2.uop.lrs2, issue_slots[1].brupdate.b2.uop.lrs2 connect slots_1.io.brupdate.b2.uop.lrs1, issue_slots[1].brupdate.b2.uop.lrs1 connect slots_1.io.brupdate.b2.uop.ldst, issue_slots[1].brupdate.b2.uop.ldst connect slots_1.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[1].brupdate.b2.uop.ldst_is_rs1 connect slots_1.io.brupdate.b2.uop.csr_cmd, issue_slots[1].brupdate.b2.uop.csr_cmd connect slots_1.io.brupdate.b2.uop.flush_on_commit, issue_slots[1].brupdate.b2.uop.flush_on_commit connect slots_1.io.brupdate.b2.uop.is_unique, issue_slots[1].brupdate.b2.uop.is_unique connect slots_1.io.brupdate.b2.uop.uses_stq, issue_slots[1].brupdate.b2.uop.uses_stq connect slots_1.io.brupdate.b2.uop.uses_ldq, issue_slots[1].brupdate.b2.uop.uses_ldq connect slots_1.io.brupdate.b2.uop.mem_signed, issue_slots[1].brupdate.b2.uop.mem_signed connect slots_1.io.brupdate.b2.uop.mem_size, issue_slots[1].brupdate.b2.uop.mem_size connect slots_1.io.brupdate.b2.uop.mem_cmd, issue_slots[1].brupdate.b2.uop.mem_cmd connect slots_1.io.brupdate.b2.uop.exc_cause, issue_slots[1].brupdate.b2.uop.exc_cause connect slots_1.io.brupdate.b2.uop.exception, issue_slots[1].brupdate.b2.uop.exception connect slots_1.io.brupdate.b2.uop.stale_pdst, issue_slots[1].brupdate.b2.uop.stale_pdst connect slots_1.io.brupdate.b2.uop.ppred_busy, issue_slots[1].brupdate.b2.uop.ppred_busy connect slots_1.io.brupdate.b2.uop.prs3_busy, issue_slots[1].brupdate.b2.uop.prs3_busy connect slots_1.io.brupdate.b2.uop.prs2_busy, issue_slots[1].brupdate.b2.uop.prs2_busy connect slots_1.io.brupdate.b2.uop.prs1_busy, issue_slots[1].brupdate.b2.uop.prs1_busy connect slots_1.io.brupdate.b2.uop.ppred, issue_slots[1].brupdate.b2.uop.ppred connect slots_1.io.brupdate.b2.uop.prs3, issue_slots[1].brupdate.b2.uop.prs3 connect slots_1.io.brupdate.b2.uop.prs2, issue_slots[1].brupdate.b2.uop.prs2 connect slots_1.io.brupdate.b2.uop.prs1, issue_slots[1].brupdate.b2.uop.prs1 connect slots_1.io.brupdate.b2.uop.pdst, issue_slots[1].brupdate.b2.uop.pdst connect slots_1.io.brupdate.b2.uop.rxq_idx, issue_slots[1].brupdate.b2.uop.rxq_idx connect slots_1.io.brupdate.b2.uop.stq_idx, issue_slots[1].brupdate.b2.uop.stq_idx connect slots_1.io.brupdate.b2.uop.ldq_idx, issue_slots[1].brupdate.b2.uop.ldq_idx connect slots_1.io.brupdate.b2.uop.rob_idx, issue_slots[1].brupdate.b2.uop.rob_idx connect slots_1.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[1].brupdate.b2.uop.fp_ctrl.vec connect slots_1.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[1].brupdate.b2.uop.fp_ctrl.wflags connect slots_1.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[1].brupdate.b2.uop.fp_ctrl.sqrt connect slots_1.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[1].brupdate.b2.uop.fp_ctrl.div connect slots_1.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[1].brupdate.b2.uop.fp_ctrl.fma connect slots_1.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[1].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_1.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[1].brupdate.b2.uop.fp_ctrl.toint connect slots_1.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[1].brupdate.b2.uop.fp_ctrl.fromint connect slots_1.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_1.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_1.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[1].brupdate.b2.uop.fp_ctrl.swap23 connect slots_1.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[1].brupdate.b2.uop.fp_ctrl.swap12 connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren3 connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren2 connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren1 connect slots_1.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[1].brupdate.b2.uop.fp_ctrl.wen connect slots_1.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[1].brupdate.b2.uop.fp_ctrl.ldst connect slots_1.io.brupdate.b2.uop.op2_sel, issue_slots[1].brupdate.b2.uop.op2_sel connect slots_1.io.brupdate.b2.uop.op1_sel, issue_slots[1].brupdate.b2.uop.op1_sel connect slots_1.io.brupdate.b2.uop.imm_packed, issue_slots[1].brupdate.b2.uop.imm_packed connect slots_1.io.brupdate.b2.uop.pimm, issue_slots[1].brupdate.b2.uop.pimm connect slots_1.io.brupdate.b2.uop.imm_sel, issue_slots[1].brupdate.b2.uop.imm_sel connect slots_1.io.brupdate.b2.uop.imm_rename, issue_slots[1].brupdate.b2.uop.imm_rename connect slots_1.io.brupdate.b2.uop.taken, issue_slots[1].brupdate.b2.uop.taken connect slots_1.io.brupdate.b2.uop.pc_lob, issue_slots[1].brupdate.b2.uop.pc_lob connect slots_1.io.brupdate.b2.uop.edge_inst, issue_slots[1].brupdate.b2.uop.edge_inst connect slots_1.io.brupdate.b2.uop.ftq_idx, issue_slots[1].brupdate.b2.uop.ftq_idx connect slots_1.io.brupdate.b2.uop.is_mov, issue_slots[1].brupdate.b2.uop.is_mov connect slots_1.io.brupdate.b2.uop.is_rocc, issue_slots[1].brupdate.b2.uop.is_rocc connect slots_1.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[1].brupdate.b2.uop.is_sys_pc2epc connect slots_1.io.brupdate.b2.uop.is_eret, issue_slots[1].brupdate.b2.uop.is_eret connect slots_1.io.brupdate.b2.uop.is_amo, issue_slots[1].brupdate.b2.uop.is_amo connect slots_1.io.brupdate.b2.uop.is_sfence, issue_slots[1].brupdate.b2.uop.is_sfence connect slots_1.io.brupdate.b2.uop.is_fencei, issue_slots[1].brupdate.b2.uop.is_fencei connect slots_1.io.brupdate.b2.uop.is_fence, issue_slots[1].brupdate.b2.uop.is_fence connect slots_1.io.brupdate.b2.uop.is_sfb, issue_slots[1].brupdate.b2.uop.is_sfb connect slots_1.io.brupdate.b2.uop.br_type, issue_slots[1].brupdate.b2.uop.br_type connect slots_1.io.brupdate.b2.uop.br_tag, issue_slots[1].brupdate.b2.uop.br_tag connect slots_1.io.brupdate.b2.uop.br_mask, issue_slots[1].brupdate.b2.uop.br_mask connect slots_1.io.brupdate.b2.uop.dis_col_sel, issue_slots[1].brupdate.b2.uop.dis_col_sel connect slots_1.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p3_bypass_hint connect slots_1.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p2_bypass_hint connect slots_1.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p1_bypass_hint connect slots_1.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[1].brupdate.b2.uop.iw_p2_speculative_child connect slots_1.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[1].brupdate.b2.uop.iw_p1_speculative_child connect slots_1.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[1].brupdate.b2.uop.iw_issued_partial_dgen connect slots_1.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[1].brupdate.b2.uop.iw_issued_partial_agen connect slots_1.io.brupdate.b2.uop.iw_issued, issue_slots[1].brupdate.b2.uop.iw_issued connect slots_1.io.brupdate.b2.uop.fu_code[0], issue_slots[1].brupdate.b2.uop.fu_code[0] connect slots_1.io.brupdate.b2.uop.fu_code[1], issue_slots[1].brupdate.b2.uop.fu_code[1] connect slots_1.io.brupdate.b2.uop.fu_code[2], issue_slots[1].brupdate.b2.uop.fu_code[2] connect slots_1.io.brupdate.b2.uop.fu_code[3], issue_slots[1].brupdate.b2.uop.fu_code[3] connect slots_1.io.brupdate.b2.uop.fu_code[4], issue_slots[1].brupdate.b2.uop.fu_code[4] connect slots_1.io.brupdate.b2.uop.fu_code[5], issue_slots[1].brupdate.b2.uop.fu_code[5] connect slots_1.io.brupdate.b2.uop.fu_code[6], issue_slots[1].brupdate.b2.uop.fu_code[6] connect slots_1.io.brupdate.b2.uop.fu_code[7], issue_slots[1].brupdate.b2.uop.fu_code[7] connect slots_1.io.brupdate.b2.uop.fu_code[8], issue_slots[1].brupdate.b2.uop.fu_code[8] connect slots_1.io.brupdate.b2.uop.fu_code[9], issue_slots[1].brupdate.b2.uop.fu_code[9] connect slots_1.io.brupdate.b2.uop.iq_type[0], issue_slots[1].brupdate.b2.uop.iq_type[0] connect slots_1.io.brupdate.b2.uop.iq_type[1], issue_slots[1].brupdate.b2.uop.iq_type[1] connect slots_1.io.brupdate.b2.uop.iq_type[2], issue_slots[1].brupdate.b2.uop.iq_type[2] connect slots_1.io.brupdate.b2.uop.iq_type[3], issue_slots[1].brupdate.b2.uop.iq_type[3] connect slots_1.io.brupdate.b2.uop.debug_pc, issue_slots[1].brupdate.b2.uop.debug_pc connect slots_1.io.brupdate.b2.uop.is_rvc, issue_slots[1].brupdate.b2.uop.is_rvc connect slots_1.io.brupdate.b2.uop.debug_inst, issue_slots[1].brupdate.b2.uop.debug_inst connect slots_1.io.brupdate.b2.uop.inst, issue_slots[1].brupdate.b2.uop.inst connect slots_1.io.brupdate.b1.mispredict_mask, issue_slots[1].brupdate.b1.mispredict_mask connect slots_1.io.brupdate.b1.resolve_mask, issue_slots[1].brupdate.b1.resolve_mask connect issue_slots[1].out_uop.debug_tsrc, slots_1.io.out_uop.debug_tsrc connect issue_slots[1].out_uop.debug_fsrc, slots_1.io.out_uop.debug_fsrc connect issue_slots[1].out_uop.bp_xcpt_if, slots_1.io.out_uop.bp_xcpt_if connect issue_slots[1].out_uop.bp_debug_if, slots_1.io.out_uop.bp_debug_if connect issue_slots[1].out_uop.xcpt_ma_if, slots_1.io.out_uop.xcpt_ma_if connect issue_slots[1].out_uop.xcpt_ae_if, slots_1.io.out_uop.xcpt_ae_if connect issue_slots[1].out_uop.xcpt_pf_if, slots_1.io.out_uop.xcpt_pf_if connect issue_slots[1].out_uop.fp_typ, slots_1.io.out_uop.fp_typ connect issue_slots[1].out_uop.fp_rm, slots_1.io.out_uop.fp_rm connect issue_slots[1].out_uop.fp_val, slots_1.io.out_uop.fp_val connect issue_slots[1].out_uop.fcn_op, slots_1.io.out_uop.fcn_op connect issue_slots[1].out_uop.fcn_dw, slots_1.io.out_uop.fcn_dw connect issue_slots[1].out_uop.frs3_en, slots_1.io.out_uop.frs3_en connect issue_slots[1].out_uop.lrs2_rtype, slots_1.io.out_uop.lrs2_rtype connect issue_slots[1].out_uop.lrs1_rtype, slots_1.io.out_uop.lrs1_rtype connect issue_slots[1].out_uop.dst_rtype, slots_1.io.out_uop.dst_rtype connect issue_slots[1].out_uop.lrs3, slots_1.io.out_uop.lrs3 connect issue_slots[1].out_uop.lrs2, slots_1.io.out_uop.lrs2 connect issue_slots[1].out_uop.lrs1, slots_1.io.out_uop.lrs1 connect issue_slots[1].out_uop.ldst, slots_1.io.out_uop.ldst connect issue_slots[1].out_uop.ldst_is_rs1, slots_1.io.out_uop.ldst_is_rs1 connect issue_slots[1].out_uop.csr_cmd, slots_1.io.out_uop.csr_cmd connect issue_slots[1].out_uop.flush_on_commit, slots_1.io.out_uop.flush_on_commit connect issue_slots[1].out_uop.is_unique, slots_1.io.out_uop.is_unique connect issue_slots[1].out_uop.uses_stq, slots_1.io.out_uop.uses_stq connect issue_slots[1].out_uop.uses_ldq, slots_1.io.out_uop.uses_ldq connect issue_slots[1].out_uop.mem_signed, slots_1.io.out_uop.mem_signed connect issue_slots[1].out_uop.mem_size, slots_1.io.out_uop.mem_size connect issue_slots[1].out_uop.mem_cmd, slots_1.io.out_uop.mem_cmd connect issue_slots[1].out_uop.exc_cause, slots_1.io.out_uop.exc_cause connect issue_slots[1].out_uop.exception, slots_1.io.out_uop.exception connect issue_slots[1].out_uop.stale_pdst, slots_1.io.out_uop.stale_pdst connect issue_slots[1].out_uop.ppred_busy, slots_1.io.out_uop.ppred_busy connect issue_slots[1].out_uop.prs3_busy, slots_1.io.out_uop.prs3_busy connect issue_slots[1].out_uop.prs2_busy, slots_1.io.out_uop.prs2_busy connect issue_slots[1].out_uop.prs1_busy, slots_1.io.out_uop.prs1_busy connect issue_slots[1].out_uop.ppred, slots_1.io.out_uop.ppred connect issue_slots[1].out_uop.prs3, slots_1.io.out_uop.prs3 connect issue_slots[1].out_uop.prs2, slots_1.io.out_uop.prs2 connect issue_slots[1].out_uop.prs1, slots_1.io.out_uop.prs1 connect issue_slots[1].out_uop.pdst, slots_1.io.out_uop.pdst connect issue_slots[1].out_uop.rxq_idx, slots_1.io.out_uop.rxq_idx connect issue_slots[1].out_uop.stq_idx, slots_1.io.out_uop.stq_idx connect issue_slots[1].out_uop.ldq_idx, slots_1.io.out_uop.ldq_idx connect issue_slots[1].out_uop.rob_idx, slots_1.io.out_uop.rob_idx connect issue_slots[1].out_uop.fp_ctrl.vec, slots_1.io.out_uop.fp_ctrl.vec connect issue_slots[1].out_uop.fp_ctrl.wflags, slots_1.io.out_uop.fp_ctrl.wflags connect issue_slots[1].out_uop.fp_ctrl.sqrt, slots_1.io.out_uop.fp_ctrl.sqrt connect issue_slots[1].out_uop.fp_ctrl.div, slots_1.io.out_uop.fp_ctrl.div connect issue_slots[1].out_uop.fp_ctrl.fma, slots_1.io.out_uop.fp_ctrl.fma connect issue_slots[1].out_uop.fp_ctrl.fastpipe, slots_1.io.out_uop.fp_ctrl.fastpipe connect issue_slots[1].out_uop.fp_ctrl.toint, slots_1.io.out_uop.fp_ctrl.toint connect issue_slots[1].out_uop.fp_ctrl.fromint, slots_1.io.out_uop.fp_ctrl.fromint connect issue_slots[1].out_uop.fp_ctrl.typeTagOut, slots_1.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[1].out_uop.fp_ctrl.typeTagIn, slots_1.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[1].out_uop.fp_ctrl.swap23, slots_1.io.out_uop.fp_ctrl.swap23 connect issue_slots[1].out_uop.fp_ctrl.swap12, slots_1.io.out_uop.fp_ctrl.swap12 connect issue_slots[1].out_uop.fp_ctrl.ren3, slots_1.io.out_uop.fp_ctrl.ren3 connect issue_slots[1].out_uop.fp_ctrl.ren2, slots_1.io.out_uop.fp_ctrl.ren2 connect issue_slots[1].out_uop.fp_ctrl.ren1, slots_1.io.out_uop.fp_ctrl.ren1 connect issue_slots[1].out_uop.fp_ctrl.wen, slots_1.io.out_uop.fp_ctrl.wen connect issue_slots[1].out_uop.fp_ctrl.ldst, slots_1.io.out_uop.fp_ctrl.ldst connect issue_slots[1].out_uop.op2_sel, slots_1.io.out_uop.op2_sel connect issue_slots[1].out_uop.op1_sel, slots_1.io.out_uop.op1_sel connect issue_slots[1].out_uop.imm_packed, slots_1.io.out_uop.imm_packed connect issue_slots[1].out_uop.pimm, slots_1.io.out_uop.pimm connect issue_slots[1].out_uop.imm_sel, slots_1.io.out_uop.imm_sel connect issue_slots[1].out_uop.imm_rename, slots_1.io.out_uop.imm_rename connect issue_slots[1].out_uop.taken, slots_1.io.out_uop.taken connect issue_slots[1].out_uop.pc_lob, slots_1.io.out_uop.pc_lob connect issue_slots[1].out_uop.edge_inst, slots_1.io.out_uop.edge_inst connect issue_slots[1].out_uop.ftq_idx, slots_1.io.out_uop.ftq_idx connect issue_slots[1].out_uop.is_mov, slots_1.io.out_uop.is_mov connect issue_slots[1].out_uop.is_rocc, slots_1.io.out_uop.is_rocc connect issue_slots[1].out_uop.is_sys_pc2epc, slots_1.io.out_uop.is_sys_pc2epc connect issue_slots[1].out_uop.is_eret, slots_1.io.out_uop.is_eret connect issue_slots[1].out_uop.is_amo, slots_1.io.out_uop.is_amo connect issue_slots[1].out_uop.is_sfence, slots_1.io.out_uop.is_sfence connect issue_slots[1].out_uop.is_fencei, slots_1.io.out_uop.is_fencei connect issue_slots[1].out_uop.is_fence, slots_1.io.out_uop.is_fence connect issue_slots[1].out_uop.is_sfb, slots_1.io.out_uop.is_sfb connect issue_slots[1].out_uop.br_type, slots_1.io.out_uop.br_type connect issue_slots[1].out_uop.br_tag, slots_1.io.out_uop.br_tag connect issue_slots[1].out_uop.br_mask, slots_1.io.out_uop.br_mask connect issue_slots[1].out_uop.dis_col_sel, slots_1.io.out_uop.dis_col_sel connect issue_slots[1].out_uop.iw_p3_bypass_hint, slots_1.io.out_uop.iw_p3_bypass_hint connect issue_slots[1].out_uop.iw_p2_bypass_hint, slots_1.io.out_uop.iw_p2_bypass_hint connect issue_slots[1].out_uop.iw_p1_bypass_hint, slots_1.io.out_uop.iw_p1_bypass_hint connect issue_slots[1].out_uop.iw_p2_speculative_child, slots_1.io.out_uop.iw_p2_speculative_child connect issue_slots[1].out_uop.iw_p1_speculative_child, slots_1.io.out_uop.iw_p1_speculative_child connect issue_slots[1].out_uop.iw_issued_partial_dgen, slots_1.io.out_uop.iw_issued_partial_dgen connect issue_slots[1].out_uop.iw_issued_partial_agen, slots_1.io.out_uop.iw_issued_partial_agen connect issue_slots[1].out_uop.iw_issued, slots_1.io.out_uop.iw_issued connect issue_slots[1].out_uop.fu_code[0], slots_1.io.out_uop.fu_code[0] connect issue_slots[1].out_uop.fu_code[1], slots_1.io.out_uop.fu_code[1] connect issue_slots[1].out_uop.fu_code[2], slots_1.io.out_uop.fu_code[2] connect issue_slots[1].out_uop.fu_code[3], slots_1.io.out_uop.fu_code[3] connect issue_slots[1].out_uop.fu_code[4], slots_1.io.out_uop.fu_code[4] connect issue_slots[1].out_uop.fu_code[5], slots_1.io.out_uop.fu_code[5] connect issue_slots[1].out_uop.fu_code[6], slots_1.io.out_uop.fu_code[6] connect issue_slots[1].out_uop.fu_code[7], slots_1.io.out_uop.fu_code[7] connect issue_slots[1].out_uop.fu_code[8], slots_1.io.out_uop.fu_code[8] connect issue_slots[1].out_uop.fu_code[9], slots_1.io.out_uop.fu_code[9] connect issue_slots[1].out_uop.iq_type[0], slots_1.io.out_uop.iq_type[0] connect issue_slots[1].out_uop.iq_type[1], slots_1.io.out_uop.iq_type[1] connect issue_slots[1].out_uop.iq_type[2], slots_1.io.out_uop.iq_type[2] connect issue_slots[1].out_uop.iq_type[3], slots_1.io.out_uop.iq_type[3] connect issue_slots[1].out_uop.debug_pc, slots_1.io.out_uop.debug_pc connect issue_slots[1].out_uop.is_rvc, slots_1.io.out_uop.is_rvc connect issue_slots[1].out_uop.debug_inst, slots_1.io.out_uop.debug_inst connect issue_slots[1].out_uop.inst, slots_1.io.out_uop.inst connect slots_1.io.in_uop.bits.debug_tsrc, issue_slots[1].in_uop.bits.debug_tsrc connect slots_1.io.in_uop.bits.debug_fsrc, issue_slots[1].in_uop.bits.debug_fsrc connect slots_1.io.in_uop.bits.bp_xcpt_if, issue_slots[1].in_uop.bits.bp_xcpt_if connect slots_1.io.in_uop.bits.bp_debug_if, issue_slots[1].in_uop.bits.bp_debug_if connect slots_1.io.in_uop.bits.xcpt_ma_if, issue_slots[1].in_uop.bits.xcpt_ma_if connect slots_1.io.in_uop.bits.xcpt_ae_if, issue_slots[1].in_uop.bits.xcpt_ae_if connect slots_1.io.in_uop.bits.xcpt_pf_if, issue_slots[1].in_uop.bits.xcpt_pf_if connect slots_1.io.in_uop.bits.fp_typ, issue_slots[1].in_uop.bits.fp_typ connect slots_1.io.in_uop.bits.fp_rm, issue_slots[1].in_uop.bits.fp_rm connect slots_1.io.in_uop.bits.fp_val, issue_slots[1].in_uop.bits.fp_val connect slots_1.io.in_uop.bits.fcn_op, issue_slots[1].in_uop.bits.fcn_op connect slots_1.io.in_uop.bits.fcn_dw, issue_slots[1].in_uop.bits.fcn_dw connect slots_1.io.in_uop.bits.frs3_en, issue_slots[1].in_uop.bits.frs3_en connect slots_1.io.in_uop.bits.lrs2_rtype, issue_slots[1].in_uop.bits.lrs2_rtype connect slots_1.io.in_uop.bits.lrs1_rtype, issue_slots[1].in_uop.bits.lrs1_rtype connect slots_1.io.in_uop.bits.dst_rtype, issue_slots[1].in_uop.bits.dst_rtype connect slots_1.io.in_uop.bits.lrs3, issue_slots[1].in_uop.bits.lrs3 connect slots_1.io.in_uop.bits.lrs2, issue_slots[1].in_uop.bits.lrs2 connect slots_1.io.in_uop.bits.lrs1, issue_slots[1].in_uop.bits.lrs1 connect slots_1.io.in_uop.bits.ldst, issue_slots[1].in_uop.bits.ldst connect slots_1.io.in_uop.bits.ldst_is_rs1, issue_slots[1].in_uop.bits.ldst_is_rs1 connect slots_1.io.in_uop.bits.csr_cmd, issue_slots[1].in_uop.bits.csr_cmd connect slots_1.io.in_uop.bits.flush_on_commit, issue_slots[1].in_uop.bits.flush_on_commit connect slots_1.io.in_uop.bits.is_unique, issue_slots[1].in_uop.bits.is_unique connect slots_1.io.in_uop.bits.uses_stq, issue_slots[1].in_uop.bits.uses_stq connect slots_1.io.in_uop.bits.uses_ldq, issue_slots[1].in_uop.bits.uses_ldq connect slots_1.io.in_uop.bits.mem_signed, issue_slots[1].in_uop.bits.mem_signed connect slots_1.io.in_uop.bits.mem_size, issue_slots[1].in_uop.bits.mem_size connect slots_1.io.in_uop.bits.mem_cmd, issue_slots[1].in_uop.bits.mem_cmd connect slots_1.io.in_uop.bits.exc_cause, issue_slots[1].in_uop.bits.exc_cause connect slots_1.io.in_uop.bits.exception, issue_slots[1].in_uop.bits.exception connect slots_1.io.in_uop.bits.stale_pdst, issue_slots[1].in_uop.bits.stale_pdst connect slots_1.io.in_uop.bits.ppred_busy, issue_slots[1].in_uop.bits.ppred_busy connect slots_1.io.in_uop.bits.prs3_busy, issue_slots[1].in_uop.bits.prs3_busy connect slots_1.io.in_uop.bits.prs2_busy, issue_slots[1].in_uop.bits.prs2_busy connect slots_1.io.in_uop.bits.prs1_busy, issue_slots[1].in_uop.bits.prs1_busy connect slots_1.io.in_uop.bits.ppred, issue_slots[1].in_uop.bits.ppred connect slots_1.io.in_uop.bits.prs3, issue_slots[1].in_uop.bits.prs3 connect slots_1.io.in_uop.bits.prs2, issue_slots[1].in_uop.bits.prs2 connect slots_1.io.in_uop.bits.prs1, issue_slots[1].in_uop.bits.prs1 connect slots_1.io.in_uop.bits.pdst, issue_slots[1].in_uop.bits.pdst connect slots_1.io.in_uop.bits.rxq_idx, issue_slots[1].in_uop.bits.rxq_idx connect slots_1.io.in_uop.bits.stq_idx, issue_slots[1].in_uop.bits.stq_idx connect slots_1.io.in_uop.bits.ldq_idx, issue_slots[1].in_uop.bits.ldq_idx connect slots_1.io.in_uop.bits.rob_idx, issue_slots[1].in_uop.bits.rob_idx connect slots_1.io.in_uop.bits.fp_ctrl.vec, issue_slots[1].in_uop.bits.fp_ctrl.vec connect slots_1.io.in_uop.bits.fp_ctrl.wflags, issue_slots[1].in_uop.bits.fp_ctrl.wflags connect slots_1.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[1].in_uop.bits.fp_ctrl.sqrt connect slots_1.io.in_uop.bits.fp_ctrl.div, issue_slots[1].in_uop.bits.fp_ctrl.div connect slots_1.io.in_uop.bits.fp_ctrl.fma, issue_slots[1].in_uop.bits.fp_ctrl.fma connect slots_1.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].in_uop.bits.fp_ctrl.fastpipe connect slots_1.io.in_uop.bits.fp_ctrl.toint, issue_slots[1].in_uop.bits.fp_ctrl.toint connect slots_1.io.in_uop.bits.fp_ctrl.fromint, issue_slots[1].in_uop.bits.fp_ctrl.fromint connect slots_1.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut connect slots_1.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn connect slots_1.io.in_uop.bits.fp_ctrl.swap23, issue_slots[1].in_uop.bits.fp_ctrl.swap23 connect slots_1.io.in_uop.bits.fp_ctrl.swap12, issue_slots[1].in_uop.bits.fp_ctrl.swap12 connect slots_1.io.in_uop.bits.fp_ctrl.ren3, issue_slots[1].in_uop.bits.fp_ctrl.ren3 connect slots_1.io.in_uop.bits.fp_ctrl.ren2, issue_slots[1].in_uop.bits.fp_ctrl.ren2 connect slots_1.io.in_uop.bits.fp_ctrl.ren1, issue_slots[1].in_uop.bits.fp_ctrl.ren1 connect slots_1.io.in_uop.bits.fp_ctrl.wen, issue_slots[1].in_uop.bits.fp_ctrl.wen connect slots_1.io.in_uop.bits.fp_ctrl.ldst, issue_slots[1].in_uop.bits.fp_ctrl.ldst connect slots_1.io.in_uop.bits.op2_sel, issue_slots[1].in_uop.bits.op2_sel connect slots_1.io.in_uop.bits.op1_sel, issue_slots[1].in_uop.bits.op1_sel connect slots_1.io.in_uop.bits.imm_packed, issue_slots[1].in_uop.bits.imm_packed connect slots_1.io.in_uop.bits.pimm, issue_slots[1].in_uop.bits.pimm connect slots_1.io.in_uop.bits.imm_sel, issue_slots[1].in_uop.bits.imm_sel connect slots_1.io.in_uop.bits.imm_rename, issue_slots[1].in_uop.bits.imm_rename connect slots_1.io.in_uop.bits.taken, issue_slots[1].in_uop.bits.taken connect slots_1.io.in_uop.bits.pc_lob, issue_slots[1].in_uop.bits.pc_lob connect slots_1.io.in_uop.bits.edge_inst, issue_slots[1].in_uop.bits.edge_inst connect slots_1.io.in_uop.bits.ftq_idx, issue_slots[1].in_uop.bits.ftq_idx connect slots_1.io.in_uop.bits.is_mov, issue_slots[1].in_uop.bits.is_mov connect slots_1.io.in_uop.bits.is_rocc, issue_slots[1].in_uop.bits.is_rocc connect slots_1.io.in_uop.bits.is_sys_pc2epc, issue_slots[1].in_uop.bits.is_sys_pc2epc connect slots_1.io.in_uop.bits.is_eret, issue_slots[1].in_uop.bits.is_eret connect slots_1.io.in_uop.bits.is_amo, issue_slots[1].in_uop.bits.is_amo connect slots_1.io.in_uop.bits.is_sfence, issue_slots[1].in_uop.bits.is_sfence connect slots_1.io.in_uop.bits.is_fencei, issue_slots[1].in_uop.bits.is_fencei connect slots_1.io.in_uop.bits.is_fence, issue_slots[1].in_uop.bits.is_fence connect slots_1.io.in_uop.bits.is_sfb, issue_slots[1].in_uop.bits.is_sfb connect slots_1.io.in_uop.bits.br_type, issue_slots[1].in_uop.bits.br_type connect slots_1.io.in_uop.bits.br_tag, issue_slots[1].in_uop.bits.br_tag connect slots_1.io.in_uop.bits.br_mask, issue_slots[1].in_uop.bits.br_mask connect slots_1.io.in_uop.bits.dis_col_sel, issue_slots[1].in_uop.bits.dis_col_sel connect slots_1.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[1].in_uop.bits.iw_p3_bypass_hint connect slots_1.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[1].in_uop.bits.iw_p2_bypass_hint connect slots_1.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[1].in_uop.bits.iw_p1_bypass_hint connect slots_1.io.in_uop.bits.iw_p2_speculative_child, issue_slots[1].in_uop.bits.iw_p2_speculative_child connect slots_1.io.in_uop.bits.iw_p1_speculative_child, issue_slots[1].in_uop.bits.iw_p1_speculative_child connect slots_1.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[1].in_uop.bits.iw_issued_partial_dgen connect slots_1.io.in_uop.bits.iw_issued_partial_agen, issue_slots[1].in_uop.bits.iw_issued_partial_agen connect slots_1.io.in_uop.bits.iw_issued, issue_slots[1].in_uop.bits.iw_issued connect slots_1.io.in_uop.bits.fu_code[0], issue_slots[1].in_uop.bits.fu_code[0] connect slots_1.io.in_uop.bits.fu_code[1], issue_slots[1].in_uop.bits.fu_code[1] connect slots_1.io.in_uop.bits.fu_code[2], issue_slots[1].in_uop.bits.fu_code[2] connect slots_1.io.in_uop.bits.fu_code[3], issue_slots[1].in_uop.bits.fu_code[3] connect slots_1.io.in_uop.bits.fu_code[4], issue_slots[1].in_uop.bits.fu_code[4] connect slots_1.io.in_uop.bits.fu_code[5], issue_slots[1].in_uop.bits.fu_code[5] connect slots_1.io.in_uop.bits.fu_code[6], issue_slots[1].in_uop.bits.fu_code[6] connect slots_1.io.in_uop.bits.fu_code[7], issue_slots[1].in_uop.bits.fu_code[7] connect slots_1.io.in_uop.bits.fu_code[8], issue_slots[1].in_uop.bits.fu_code[8] connect slots_1.io.in_uop.bits.fu_code[9], issue_slots[1].in_uop.bits.fu_code[9] connect slots_1.io.in_uop.bits.iq_type[0], issue_slots[1].in_uop.bits.iq_type[0] connect slots_1.io.in_uop.bits.iq_type[1], issue_slots[1].in_uop.bits.iq_type[1] connect slots_1.io.in_uop.bits.iq_type[2], issue_slots[1].in_uop.bits.iq_type[2] connect slots_1.io.in_uop.bits.iq_type[3], issue_slots[1].in_uop.bits.iq_type[3] connect slots_1.io.in_uop.bits.debug_pc, issue_slots[1].in_uop.bits.debug_pc connect slots_1.io.in_uop.bits.is_rvc, issue_slots[1].in_uop.bits.is_rvc connect slots_1.io.in_uop.bits.debug_inst, issue_slots[1].in_uop.bits.debug_inst connect slots_1.io.in_uop.bits.inst, issue_slots[1].in_uop.bits.inst connect slots_1.io.in_uop.valid, issue_slots[1].in_uop.valid connect issue_slots[1].iss_uop.debug_tsrc, slots_1.io.iss_uop.debug_tsrc connect issue_slots[1].iss_uop.debug_fsrc, slots_1.io.iss_uop.debug_fsrc connect issue_slots[1].iss_uop.bp_xcpt_if, slots_1.io.iss_uop.bp_xcpt_if connect issue_slots[1].iss_uop.bp_debug_if, slots_1.io.iss_uop.bp_debug_if connect issue_slots[1].iss_uop.xcpt_ma_if, slots_1.io.iss_uop.xcpt_ma_if connect issue_slots[1].iss_uop.xcpt_ae_if, slots_1.io.iss_uop.xcpt_ae_if connect issue_slots[1].iss_uop.xcpt_pf_if, slots_1.io.iss_uop.xcpt_pf_if connect issue_slots[1].iss_uop.fp_typ, slots_1.io.iss_uop.fp_typ connect issue_slots[1].iss_uop.fp_rm, slots_1.io.iss_uop.fp_rm connect issue_slots[1].iss_uop.fp_val, slots_1.io.iss_uop.fp_val connect issue_slots[1].iss_uop.fcn_op, slots_1.io.iss_uop.fcn_op connect issue_slots[1].iss_uop.fcn_dw, slots_1.io.iss_uop.fcn_dw connect issue_slots[1].iss_uop.frs3_en, slots_1.io.iss_uop.frs3_en connect issue_slots[1].iss_uop.lrs2_rtype, slots_1.io.iss_uop.lrs2_rtype connect issue_slots[1].iss_uop.lrs1_rtype, slots_1.io.iss_uop.lrs1_rtype connect issue_slots[1].iss_uop.dst_rtype, slots_1.io.iss_uop.dst_rtype connect issue_slots[1].iss_uop.lrs3, slots_1.io.iss_uop.lrs3 connect issue_slots[1].iss_uop.lrs2, slots_1.io.iss_uop.lrs2 connect issue_slots[1].iss_uop.lrs1, slots_1.io.iss_uop.lrs1 connect issue_slots[1].iss_uop.ldst, slots_1.io.iss_uop.ldst connect issue_slots[1].iss_uop.ldst_is_rs1, slots_1.io.iss_uop.ldst_is_rs1 connect issue_slots[1].iss_uop.csr_cmd, slots_1.io.iss_uop.csr_cmd connect issue_slots[1].iss_uop.flush_on_commit, slots_1.io.iss_uop.flush_on_commit connect issue_slots[1].iss_uop.is_unique, slots_1.io.iss_uop.is_unique connect issue_slots[1].iss_uop.uses_stq, slots_1.io.iss_uop.uses_stq connect issue_slots[1].iss_uop.uses_ldq, slots_1.io.iss_uop.uses_ldq connect issue_slots[1].iss_uop.mem_signed, slots_1.io.iss_uop.mem_signed connect issue_slots[1].iss_uop.mem_size, slots_1.io.iss_uop.mem_size connect issue_slots[1].iss_uop.mem_cmd, slots_1.io.iss_uop.mem_cmd connect issue_slots[1].iss_uop.exc_cause, slots_1.io.iss_uop.exc_cause connect issue_slots[1].iss_uop.exception, slots_1.io.iss_uop.exception connect issue_slots[1].iss_uop.stale_pdst, slots_1.io.iss_uop.stale_pdst connect issue_slots[1].iss_uop.ppred_busy, slots_1.io.iss_uop.ppred_busy connect issue_slots[1].iss_uop.prs3_busy, slots_1.io.iss_uop.prs3_busy connect issue_slots[1].iss_uop.prs2_busy, slots_1.io.iss_uop.prs2_busy connect issue_slots[1].iss_uop.prs1_busy, slots_1.io.iss_uop.prs1_busy connect issue_slots[1].iss_uop.ppred, slots_1.io.iss_uop.ppred connect issue_slots[1].iss_uop.prs3, slots_1.io.iss_uop.prs3 connect issue_slots[1].iss_uop.prs2, slots_1.io.iss_uop.prs2 connect issue_slots[1].iss_uop.prs1, slots_1.io.iss_uop.prs1 connect issue_slots[1].iss_uop.pdst, slots_1.io.iss_uop.pdst connect issue_slots[1].iss_uop.rxq_idx, slots_1.io.iss_uop.rxq_idx connect issue_slots[1].iss_uop.stq_idx, slots_1.io.iss_uop.stq_idx connect issue_slots[1].iss_uop.ldq_idx, slots_1.io.iss_uop.ldq_idx connect issue_slots[1].iss_uop.rob_idx, slots_1.io.iss_uop.rob_idx connect issue_slots[1].iss_uop.fp_ctrl.vec, slots_1.io.iss_uop.fp_ctrl.vec connect issue_slots[1].iss_uop.fp_ctrl.wflags, slots_1.io.iss_uop.fp_ctrl.wflags connect issue_slots[1].iss_uop.fp_ctrl.sqrt, slots_1.io.iss_uop.fp_ctrl.sqrt connect issue_slots[1].iss_uop.fp_ctrl.div, slots_1.io.iss_uop.fp_ctrl.div connect issue_slots[1].iss_uop.fp_ctrl.fma, slots_1.io.iss_uop.fp_ctrl.fma connect issue_slots[1].iss_uop.fp_ctrl.fastpipe, slots_1.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[1].iss_uop.fp_ctrl.toint, slots_1.io.iss_uop.fp_ctrl.toint connect issue_slots[1].iss_uop.fp_ctrl.fromint, slots_1.io.iss_uop.fp_ctrl.fromint connect issue_slots[1].iss_uop.fp_ctrl.typeTagOut, slots_1.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[1].iss_uop.fp_ctrl.typeTagIn, slots_1.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[1].iss_uop.fp_ctrl.swap23, slots_1.io.iss_uop.fp_ctrl.swap23 connect issue_slots[1].iss_uop.fp_ctrl.swap12, slots_1.io.iss_uop.fp_ctrl.swap12 connect issue_slots[1].iss_uop.fp_ctrl.ren3, slots_1.io.iss_uop.fp_ctrl.ren3 connect issue_slots[1].iss_uop.fp_ctrl.ren2, slots_1.io.iss_uop.fp_ctrl.ren2 connect issue_slots[1].iss_uop.fp_ctrl.ren1, slots_1.io.iss_uop.fp_ctrl.ren1 connect issue_slots[1].iss_uop.fp_ctrl.wen, slots_1.io.iss_uop.fp_ctrl.wen connect issue_slots[1].iss_uop.fp_ctrl.ldst, slots_1.io.iss_uop.fp_ctrl.ldst connect issue_slots[1].iss_uop.op2_sel, slots_1.io.iss_uop.op2_sel connect issue_slots[1].iss_uop.op1_sel, slots_1.io.iss_uop.op1_sel connect issue_slots[1].iss_uop.imm_packed, slots_1.io.iss_uop.imm_packed connect issue_slots[1].iss_uop.pimm, slots_1.io.iss_uop.pimm connect issue_slots[1].iss_uop.imm_sel, slots_1.io.iss_uop.imm_sel connect issue_slots[1].iss_uop.imm_rename, slots_1.io.iss_uop.imm_rename connect issue_slots[1].iss_uop.taken, slots_1.io.iss_uop.taken connect issue_slots[1].iss_uop.pc_lob, slots_1.io.iss_uop.pc_lob connect issue_slots[1].iss_uop.edge_inst, slots_1.io.iss_uop.edge_inst connect issue_slots[1].iss_uop.ftq_idx, slots_1.io.iss_uop.ftq_idx connect issue_slots[1].iss_uop.is_mov, slots_1.io.iss_uop.is_mov connect issue_slots[1].iss_uop.is_rocc, slots_1.io.iss_uop.is_rocc connect issue_slots[1].iss_uop.is_sys_pc2epc, slots_1.io.iss_uop.is_sys_pc2epc connect issue_slots[1].iss_uop.is_eret, slots_1.io.iss_uop.is_eret connect issue_slots[1].iss_uop.is_amo, slots_1.io.iss_uop.is_amo connect issue_slots[1].iss_uop.is_sfence, slots_1.io.iss_uop.is_sfence connect issue_slots[1].iss_uop.is_fencei, slots_1.io.iss_uop.is_fencei connect issue_slots[1].iss_uop.is_fence, slots_1.io.iss_uop.is_fence connect issue_slots[1].iss_uop.is_sfb, slots_1.io.iss_uop.is_sfb connect issue_slots[1].iss_uop.br_type, slots_1.io.iss_uop.br_type connect issue_slots[1].iss_uop.br_tag, slots_1.io.iss_uop.br_tag connect issue_slots[1].iss_uop.br_mask, slots_1.io.iss_uop.br_mask connect issue_slots[1].iss_uop.dis_col_sel, slots_1.io.iss_uop.dis_col_sel connect issue_slots[1].iss_uop.iw_p3_bypass_hint, slots_1.io.iss_uop.iw_p3_bypass_hint connect issue_slots[1].iss_uop.iw_p2_bypass_hint, slots_1.io.iss_uop.iw_p2_bypass_hint connect issue_slots[1].iss_uop.iw_p1_bypass_hint, slots_1.io.iss_uop.iw_p1_bypass_hint connect issue_slots[1].iss_uop.iw_p2_speculative_child, slots_1.io.iss_uop.iw_p2_speculative_child connect issue_slots[1].iss_uop.iw_p1_speculative_child, slots_1.io.iss_uop.iw_p1_speculative_child connect issue_slots[1].iss_uop.iw_issued_partial_dgen, slots_1.io.iss_uop.iw_issued_partial_dgen connect issue_slots[1].iss_uop.iw_issued_partial_agen, slots_1.io.iss_uop.iw_issued_partial_agen connect issue_slots[1].iss_uop.iw_issued, slots_1.io.iss_uop.iw_issued connect issue_slots[1].iss_uop.fu_code[0], slots_1.io.iss_uop.fu_code[0] connect issue_slots[1].iss_uop.fu_code[1], slots_1.io.iss_uop.fu_code[1] connect issue_slots[1].iss_uop.fu_code[2], slots_1.io.iss_uop.fu_code[2] connect issue_slots[1].iss_uop.fu_code[3], slots_1.io.iss_uop.fu_code[3] connect issue_slots[1].iss_uop.fu_code[4], slots_1.io.iss_uop.fu_code[4] connect issue_slots[1].iss_uop.fu_code[5], slots_1.io.iss_uop.fu_code[5] connect issue_slots[1].iss_uop.fu_code[6], slots_1.io.iss_uop.fu_code[6] connect issue_slots[1].iss_uop.fu_code[7], slots_1.io.iss_uop.fu_code[7] connect issue_slots[1].iss_uop.fu_code[8], slots_1.io.iss_uop.fu_code[8] connect issue_slots[1].iss_uop.fu_code[9], slots_1.io.iss_uop.fu_code[9] connect issue_slots[1].iss_uop.iq_type[0], slots_1.io.iss_uop.iq_type[0] connect issue_slots[1].iss_uop.iq_type[1], slots_1.io.iss_uop.iq_type[1] connect issue_slots[1].iss_uop.iq_type[2], slots_1.io.iss_uop.iq_type[2] connect issue_slots[1].iss_uop.iq_type[3], slots_1.io.iss_uop.iq_type[3] connect issue_slots[1].iss_uop.debug_pc, slots_1.io.iss_uop.debug_pc connect issue_slots[1].iss_uop.is_rvc, slots_1.io.iss_uop.is_rvc connect issue_slots[1].iss_uop.debug_inst, slots_1.io.iss_uop.debug_inst connect issue_slots[1].iss_uop.inst, slots_1.io.iss_uop.inst connect slots_1.io.grant, issue_slots[1].grant connect issue_slots[1].request, slots_1.io.request connect issue_slots[1].will_be_valid, slots_1.io.will_be_valid connect issue_slots[1].valid, slots_1.io.valid connect slots_2.io.child_rebusys, issue_slots[2].child_rebusys connect slots_2.io.pred_wakeup_port.bits, issue_slots[2].pred_wakeup_port.bits connect slots_2.io.pred_wakeup_port.valid, issue_slots[2].pred_wakeup_port.valid connect slots_2.io.wakeup_ports[0].bits.rebusy, issue_slots[2].wakeup_ports[0].bits.rebusy connect slots_2.io.wakeup_ports[0].bits.speculative_mask, issue_slots[2].wakeup_ports[0].bits.speculative_mask connect slots_2.io.wakeup_ports[0].bits.bypassable, issue_slots[2].wakeup_ports[0].bits.bypassable connect slots_2.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[0].bits.uop.debug_tsrc connect slots_2.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[0].bits.uop.debug_fsrc connect slots_2.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_2.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[0].bits.uop.bp_debug_if connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_2.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[2].wakeup_ports[0].bits.uop.fp_typ connect slots_2.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[2].wakeup_ports[0].bits.uop.fp_rm connect slots_2.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[2].wakeup_ports[0].bits.uop.fp_val connect slots_2.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[2].wakeup_ports[0].bits.uop.fcn_op connect slots_2.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[0].bits.uop.fcn_dw connect slots_2.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[2].wakeup_ports[0].bits.uop.frs3_en connect slots_2.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_2.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_2.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[0].bits.uop.dst_rtype connect slots_2.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[2].wakeup_ports[0].bits.uop.lrs3 connect slots_2.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[2].wakeup_ports[0].bits.uop.lrs2 connect slots_2.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[2].wakeup_ports[0].bits.uop.lrs1 connect slots_2.io.wakeup_ports[0].bits.uop.ldst, issue_slots[2].wakeup_ports[0].bits.uop.ldst connect slots_2.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_2.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[0].bits.uop.csr_cmd connect slots_2.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[0].bits.uop.flush_on_commit connect slots_2.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[2].wakeup_ports[0].bits.uop.is_unique connect slots_2.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[2].wakeup_ports[0].bits.uop.uses_stq connect slots_2.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[0].bits.uop.uses_ldq connect slots_2.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[2].wakeup_ports[0].bits.uop.mem_signed connect slots_2.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[2].wakeup_ports[0].bits.uop.mem_size connect slots_2.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[0].bits.uop.mem_cmd connect slots_2.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[2].wakeup_ports[0].bits.uop.exc_cause connect slots_2.io.wakeup_ports[0].bits.uop.exception, issue_slots[2].wakeup_ports[0].bits.uop.exception connect slots_2.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[0].bits.uop.stale_pdst connect slots_2.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[0].bits.uop.ppred_busy connect slots_2.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs3_busy connect slots_2.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs2_busy connect slots_2.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs1_busy connect slots_2.io.wakeup_ports[0].bits.uop.ppred, issue_slots[2].wakeup_ports[0].bits.uop.ppred connect slots_2.io.wakeup_ports[0].bits.uop.prs3, issue_slots[2].wakeup_ports[0].bits.uop.prs3 connect slots_2.io.wakeup_ports[0].bits.uop.prs2, issue_slots[2].wakeup_ports[0].bits.uop.prs2 connect slots_2.io.wakeup_ports[0].bits.uop.prs1, issue_slots[2].wakeup_ports[0].bits.uop.prs1 connect slots_2.io.wakeup_ports[0].bits.uop.pdst, issue_slots[2].wakeup_ports[0].bits.uop.pdst connect slots_2.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[0].bits.uop.rxq_idx connect slots_2.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[2].wakeup_ports[0].bits.uop.stq_idx connect slots_2.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[0].bits.uop.ldq_idx connect slots_2.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[2].wakeup_ports[0].bits.uop.rob_idx connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_2.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[2].wakeup_ports[0].bits.uop.op2_sel connect slots_2.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[2].wakeup_ports[0].bits.uop.op1_sel connect slots_2.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[2].wakeup_ports[0].bits.uop.imm_packed connect slots_2.io.wakeup_ports[0].bits.uop.pimm, issue_slots[2].wakeup_ports[0].bits.uop.pimm connect slots_2.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[2].wakeup_ports[0].bits.uop.imm_sel connect slots_2.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[2].wakeup_ports[0].bits.uop.imm_rename connect slots_2.io.wakeup_ports[0].bits.uop.taken, issue_slots[2].wakeup_ports[0].bits.uop.taken connect slots_2.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[2].wakeup_ports[0].bits.uop.pc_lob connect slots_2.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[2].wakeup_ports[0].bits.uop.edge_inst connect slots_2.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[0].bits.uop.ftq_idx connect slots_2.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[2].wakeup_ports[0].bits.uop.is_mov connect slots_2.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[2].wakeup_ports[0].bits.uop.is_rocc connect slots_2.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_2.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[2].wakeup_ports[0].bits.uop.is_eret connect slots_2.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[2].wakeup_ports[0].bits.uop.is_amo connect slots_2.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[2].wakeup_ports[0].bits.uop.is_sfence connect slots_2.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[2].wakeup_ports[0].bits.uop.is_fencei connect slots_2.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[2].wakeup_ports[0].bits.uop.is_fence connect slots_2.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[2].wakeup_ports[0].bits.uop.is_sfb connect slots_2.io.wakeup_ports[0].bits.uop.br_type, issue_slots[2].wakeup_ports[0].bits.uop.br_type connect slots_2.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[2].wakeup_ports[0].bits.uop.br_tag connect slots_2.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[2].wakeup_ports[0].bits.uop.br_mask connect slots_2.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[0].bits.uop.dis_col_sel connect slots_2.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_2.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_2.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_2.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_2.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[0] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[1] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[2] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[3] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[4] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[5] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[6] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[7] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[8] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[9] connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[0] connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[1] connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[2] connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[3] connect slots_2.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[2].wakeup_ports[0].bits.uop.debug_pc connect slots_2.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[2].wakeup_ports[0].bits.uop.is_rvc connect slots_2.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[2].wakeup_ports[0].bits.uop.debug_inst connect slots_2.io.wakeup_ports[0].bits.uop.inst, issue_slots[2].wakeup_ports[0].bits.uop.inst connect slots_2.io.wakeup_ports[0].valid, issue_slots[2].wakeup_ports[0].valid connect slots_2.io.wakeup_ports[1].bits.rebusy, issue_slots[2].wakeup_ports[1].bits.rebusy connect slots_2.io.wakeup_ports[1].bits.speculative_mask, issue_slots[2].wakeup_ports[1].bits.speculative_mask connect slots_2.io.wakeup_ports[1].bits.bypassable, issue_slots[2].wakeup_ports[1].bits.bypassable connect slots_2.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[1].bits.uop.debug_tsrc connect slots_2.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[1].bits.uop.debug_fsrc connect slots_2.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_2.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[1].bits.uop.bp_debug_if connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_2.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[2].wakeup_ports[1].bits.uop.fp_typ connect slots_2.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[2].wakeup_ports[1].bits.uop.fp_rm connect slots_2.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[2].wakeup_ports[1].bits.uop.fp_val connect slots_2.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[2].wakeup_ports[1].bits.uop.fcn_op connect slots_2.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[1].bits.uop.fcn_dw connect slots_2.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[2].wakeup_ports[1].bits.uop.frs3_en connect slots_2.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_2.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_2.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[1].bits.uop.dst_rtype connect slots_2.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[2].wakeup_ports[1].bits.uop.lrs3 connect slots_2.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[2].wakeup_ports[1].bits.uop.lrs2 connect slots_2.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[2].wakeup_ports[1].bits.uop.lrs1 connect slots_2.io.wakeup_ports[1].bits.uop.ldst, issue_slots[2].wakeup_ports[1].bits.uop.ldst connect slots_2.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_2.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[1].bits.uop.csr_cmd connect slots_2.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[1].bits.uop.flush_on_commit connect slots_2.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[2].wakeup_ports[1].bits.uop.is_unique connect slots_2.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[2].wakeup_ports[1].bits.uop.uses_stq connect slots_2.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[1].bits.uop.uses_ldq connect slots_2.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[2].wakeup_ports[1].bits.uop.mem_signed connect slots_2.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[2].wakeup_ports[1].bits.uop.mem_size connect slots_2.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[1].bits.uop.mem_cmd connect slots_2.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[2].wakeup_ports[1].bits.uop.exc_cause connect slots_2.io.wakeup_ports[1].bits.uop.exception, issue_slots[2].wakeup_ports[1].bits.uop.exception connect slots_2.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[1].bits.uop.stale_pdst connect slots_2.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[1].bits.uop.ppred_busy connect slots_2.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs3_busy connect slots_2.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs2_busy connect slots_2.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs1_busy connect slots_2.io.wakeup_ports[1].bits.uop.ppred, issue_slots[2].wakeup_ports[1].bits.uop.ppred connect slots_2.io.wakeup_ports[1].bits.uop.prs3, issue_slots[2].wakeup_ports[1].bits.uop.prs3 connect slots_2.io.wakeup_ports[1].bits.uop.prs2, issue_slots[2].wakeup_ports[1].bits.uop.prs2 connect slots_2.io.wakeup_ports[1].bits.uop.prs1, issue_slots[2].wakeup_ports[1].bits.uop.prs1 connect slots_2.io.wakeup_ports[1].bits.uop.pdst, issue_slots[2].wakeup_ports[1].bits.uop.pdst connect slots_2.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[1].bits.uop.rxq_idx connect slots_2.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[2].wakeup_ports[1].bits.uop.stq_idx connect slots_2.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[1].bits.uop.ldq_idx connect slots_2.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[2].wakeup_ports[1].bits.uop.rob_idx connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_2.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[2].wakeup_ports[1].bits.uop.op2_sel connect slots_2.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[2].wakeup_ports[1].bits.uop.op1_sel connect slots_2.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[2].wakeup_ports[1].bits.uop.imm_packed connect slots_2.io.wakeup_ports[1].bits.uop.pimm, issue_slots[2].wakeup_ports[1].bits.uop.pimm connect slots_2.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[2].wakeup_ports[1].bits.uop.imm_sel connect slots_2.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[2].wakeup_ports[1].bits.uop.imm_rename connect slots_2.io.wakeup_ports[1].bits.uop.taken, issue_slots[2].wakeup_ports[1].bits.uop.taken connect slots_2.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[2].wakeup_ports[1].bits.uop.pc_lob connect slots_2.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[2].wakeup_ports[1].bits.uop.edge_inst connect slots_2.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[1].bits.uop.ftq_idx connect slots_2.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[2].wakeup_ports[1].bits.uop.is_mov connect slots_2.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[2].wakeup_ports[1].bits.uop.is_rocc connect slots_2.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_2.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[2].wakeup_ports[1].bits.uop.is_eret connect slots_2.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[2].wakeup_ports[1].bits.uop.is_amo connect slots_2.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[2].wakeup_ports[1].bits.uop.is_sfence connect slots_2.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[2].wakeup_ports[1].bits.uop.is_fencei connect slots_2.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[2].wakeup_ports[1].bits.uop.is_fence connect slots_2.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[2].wakeup_ports[1].bits.uop.is_sfb connect slots_2.io.wakeup_ports[1].bits.uop.br_type, issue_slots[2].wakeup_ports[1].bits.uop.br_type connect slots_2.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[2].wakeup_ports[1].bits.uop.br_tag connect slots_2.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[2].wakeup_ports[1].bits.uop.br_mask connect slots_2.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[1].bits.uop.dis_col_sel connect slots_2.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_2.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_2.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_2.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_2.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[0] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[1] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[2] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[3] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[4] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[5] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[6] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[7] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[8] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[9] connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[0] connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[1] connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[2] connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[3] connect slots_2.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[2].wakeup_ports[1].bits.uop.debug_pc connect slots_2.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[2].wakeup_ports[1].bits.uop.is_rvc connect slots_2.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[2].wakeup_ports[1].bits.uop.debug_inst connect slots_2.io.wakeup_ports[1].bits.uop.inst, issue_slots[2].wakeup_ports[1].bits.uop.inst connect slots_2.io.wakeup_ports[1].valid, issue_slots[2].wakeup_ports[1].valid connect slots_2.io.wakeup_ports[2].bits.rebusy, issue_slots[2].wakeup_ports[2].bits.rebusy connect slots_2.io.wakeup_ports[2].bits.speculative_mask, issue_slots[2].wakeup_ports[2].bits.speculative_mask connect slots_2.io.wakeup_ports[2].bits.bypassable, issue_slots[2].wakeup_ports[2].bits.bypassable connect slots_2.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[2].bits.uop.debug_tsrc connect slots_2.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[2].bits.uop.debug_fsrc connect slots_2.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_2.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[2].bits.uop.bp_debug_if connect slots_2.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_2.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_2.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_2.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[2].wakeup_ports[2].bits.uop.fp_typ connect slots_2.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[2].wakeup_ports[2].bits.uop.fp_rm connect slots_2.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[2].wakeup_ports[2].bits.uop.fp_val connect slots_2.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[2].wakeup_ports[2].bits.uop.fcn_op connect slots_2.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[2].bits.uop.fcn_dw connect slots_2.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[2].wakeup_ports[2].bits.uop.frs3_en connect slots_2.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_2.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_2.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[2].bits.uop.dst_rtype connect slots_2.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[2].wakeup_ports[2].bits.uop.lrs3 connect slots_2.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[2].wakeup_ports[2].bits.uop.lrs2 connect slots_2.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[2].wakeup_ports[2].bits.uop.lrs1 connect slots_2.io.wakeup_ports[2].bits.uop.ldst, issue_slots[2].wakeup_ports[2].bits.uop.ldst connect slots_2.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_2.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[2].bits.uop.csr_cmd connect slots_2.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[2].bits.uop.flush_on_commit connect slots_2.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[2].wakeup_ports[2].bits.uop.is_unique connect slots_2.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[2].wakeup_ports[2].bits.uop.uses_stq connect slots_2.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[2].bits.uop.uses_ldq connect slots_2.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[2].wakeup_ports[2].bits.uop.mem_signed connect slots_2.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[2].wakeup_ports[2].bits.uop.mem_size connect slots_2.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[2].bits.uop.mem_cmd connect slots_2.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[2].wakeup_ports[2].bits.uop.exc_cause connect slots_2.io.wakeup_ports[2].bits.uop.exception, issue_slots[2].wakeup_ports[2].bits.uop.exception connect slots_2.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[2].bits.uop.stale_pdst connect slots_2.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[2].bits.uop.ppred_busy connect slots_2.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[2].bits.uop.prs3_busy connect slots_2.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[2].bits.uop.prs2_busy connect slots_2.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[2].bits.uop.prs1_busy connect slots_2.io.wakeup_ports[2].bits.uop.ppred, issue_slots[2].wakeup_ports[2].bits.uop.ppred connect slots_2.io.wakeup_ports[2].bits.uop.prs3, issue_slots[2].wakeup_ports[2].bits.uop.prs3 connect slots_2.io.wakeup_ports[2].bits.uop.prs2, issue_slots[2].wakeup_ports[2].bits.uop.prs2 connect slots_2.io.wakeup_ports[2].bits.uop.prs1, issue_slots[2].wakeup_ports[2].bits.uop.prs1 connect slots_2.io.wakeup_ports[2].bits.uop.pdst, issue_slots[2].wakeup_ports[2].bits.uop.pdst connect slots_2.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[2].bits.uop.rxq_idx connect slots_2.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[2].wakeup_ports[2].bits.uop.stq_idx connect slots_2.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[2].bits.uop.ldq_idx connect slots_2.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[2].wakeup_ports[2].bits.uop.rob_idx connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_2.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[2].wakeup_ports[2].bits.uop.op2_sel connect slots_2.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[2].wakeup_ports[2].bits.uop.op1_sel connect slots_2.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[2].wakeup_ports[2].bits.uop.imm_packed connect slots_2.io.wakeup_ports[2].bits.uop.pimm, issue_slots[2].wakeup_ports[2].bits.uop.pimm connect slots_2.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[2].wakeup_ports[2].bits.uop.imm_sel connect slots_2.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[2].wakeup_ports[2].bits.uop.imm_rename connect slots_2.io.wakeup_ports[2].bits.uop.taken, issue_slots[2].wakeup_ports[2].bits.uop.taken connect slots_2.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[2].wakeup_ports[2].bits.uop.pc_lob connect slots_2.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[2].wakeup_ports[2].bits.uop.edge_inst connect slots_2.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[2].bits.uop.ftq_idx connect slots_2.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[2].wakeup_ports[2].bits.uop.is_mov connect slots_2.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[2].wakeup_ports[2].bits.uop.is_rocc connect slots_2.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_2.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[2].wakeup_ports[2].bits.uop.is_eret connect slots_2.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[2].wakeup_ports[2].bits.uop.is_amo connect slots_2.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[2].wakeup_ports[2].bits.uop.is_sfence connect slots_2.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[2].wakeup_ports[2].bits.uop.is_fencei connect slots_2.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[2].wakeup_ports[2].bits.uop.is_fence connect slots_2.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[2].wakeup_ports[2].bits.uop.is_sfb connect slots_2.io.wakeup_ports[2].bits.uop.br_type, issue_slots[2].wakeup_ports[2].bits.uop.br_type connect slots_2.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[2].wakeup_ports[2].bits.uop.br_tag connect slots_2.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[2].wakeup_ports[2].bits.uop.br_mask connect slots_2.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[2].bits.uop.dis_col_sel connect slots_2.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_2.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_2.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_2.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_2.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_2.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_2.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_2.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[2].wakeup_ports[2].bits.uop.iw_issued connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[0] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[1] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[2] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[3] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[4] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[5] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[6] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[7] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[8] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[9] connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[0] connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[1] connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[2] connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[3] connect slots_2.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[2].wakeup_ports[2].bits.uop.debug_pc connect slots_2.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[2].wakeup_ports[2].bits.uop.is_rvc connect slots_2.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[2].wakeup_ports[2].bits.uop.debug_inst connect slots_2.io.wakeup_ports[2].bits.uop.inst, issue_slots[2].wakeup_ports[2].bits.uop.inst connect slots_2.io.wakeup_ports[2].valid, issue_slots[2].wakeup_ports[2].valid connect slots_2.io.wakeup_ports[3].bits.rebusy, issue_slots[2].wakeup_ports[3].bits.rebusy connect slots_2.io.wakeup_ports[3].bits.speculative_mask, issue_slots[2].wakeup_ports[3].bits.speculative_mask connect slots_2.io.wakeup_ports[3].bits.bypassable, issue_slots[2].wakeup_ports[3].bits.bypassable connect slots_2.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[3].bits.uop.debug_tsrc connect slots_2.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[3].bits.uop.debug_fsrc connect slots_2.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_2.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[3].bits.uop.bp_debug_if connect slots_2.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_2.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_2.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_2.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[2].wakeup_ports[3].bits.uop.fp_typ connect slots_2.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[2].wakeup_ports[3].bits.uop.fp_rm connect slots_2.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[2].wakeup_ports[3].bits.uop.fp_val connect slots_2.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[2].wakeup_ports[3].bits.uop.fcn_op connect slots_2.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[3].bits.uop.fcn_dw connect slots_2.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[2].wakeup_ports[3].bits.uop.frs3_en connect slots_2.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_2.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_2.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[3].bits.uop.dst_rtype connect slots_2.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[2].wakeup_ports[3].bits.uop.lrs3 connect slots_2.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[2].wakeup_ports[3].bits.uop.lrs2 connect slots_2.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[2].wakeup_ports[3].bits.uop.lrs1 connect slots_2.io.wakeup_ports[3].bits.uop.ldst, issue_slots[2].wakeup_ports[3].bits.uop.ldst connect slots_2.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_2.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[3].bits.uop.csr_cmd connect slots_2.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[3].bits.uop.flush_on_commit connect slots_2.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[2].wakeup_ports[3].bits.uop.is_unique connect slots_2.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[2].wakeup_ports[3].bits.uop.uses_stq connect slots_2.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[3].bits.uop.uses_ldq connect slots_2.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[2].wakeup_ports[3].bits.uop.mem_signed connect slots_2.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[2].wakeup_ports[3].bits.uop.mem_size connect slots_2.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[3].bits.uop.mem_cmd connect slots_2.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[2].wakeup_ports[3].bits.uop.exc_cause connect slots_2.io.wakeup_ports[3].bits.uop.exception, issue_slots[2].wakeup_ports[3].bits.uop.exception connect slots_2.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[3].bits.uop.stale_pdst connect slots_2.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[3].bits.uop.ppred_busy connect slots_2.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[3].bits.uop.prs3_busy connect slots_2.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[3].bits.uop.prs2_busy connect slots_2.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[3].bits.uop.prs1_busy connect slots_2.io.wakeup_ports[3].bits.uop.ppred, issue_slots[2].wakeup_ports[3].bits.uop.ppred connect slots_2.io.wakeup_ports[3].bits.uop.prs3, issue_slots[2].wakeup_ports[3].bits.uop.prs3 connect slots_2.io.wakeup_ports[3].bits.uop.prs2, issue_slots[2].wakeup_ports[3].bits.uop.prs2 connect slots_2.io.wakeup_ports[3].bits.uop.prs1, issue_slots[2].wakeup_ports[3].bits.uop.prs1 connect slots_2.io.wakeup_ports[3].bits.uop.pdst, issue_slots[2].wakeup_ports[3].bits.uop.pdst connect slots_2.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[3].bits.uop.rxq_idx connect slots_2.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[2].wakeup_ports[3].bits.uop.stq_idx connect slots_2.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[3].bits.uop.ldq_idx connect slots_2.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[2].wakeup_ports[3].bits.uop.rob_idx connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_2.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[2].wakeup_ports[3].bits.uop.op2_sel connect slots_2.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[2].wakeup_ports[3].bits.uop.op1_sel connect slots_2.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[2].wakeup_ports[3].bits.uop.imm_packed connect slots_2.io.wakeup_ports[3].bits.uop.pimm, issue_slots[2].wakeup_ports[3].bits.uop.pimm connect slots_2.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[2].wakeup_ports[3].bits.uop.imm_sel connect slots_2.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[2].wakeup_ports[3].bits.uop.imm_rename connect slots_2.io.wakeup_ports[3].bits.uop.taken, issue_slots[2].wakeup_ports[3].bits.uop.taken connect slots_2.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[2].wakeup_ports[3].bits.uop.pc_lob connect slots_2.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[2].wakeup_ports[3].bits.uop.edge_inst connect slots_2.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[3].bits.uop.ftq_idx connect slots_2.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[2].wakeup_ports[3].bits.uop.is_mov connect slots_2.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[2].wakeup_ports[3].bits.uop.is_rocc connect slots_2.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_2.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[2].wakeup_ports[3].bits.uop.is_eret connect slots_2.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[2].wakeup_ports[3].bits.uop.is_amo connect slots_2.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[2].wakeup_ports[3].bits.uop.is_sfence connect slots_2.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[2].wakeup_ports[3].bits.uop.is_fencei connect slots_2.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[2].wakeup_ports[3].bits.uop.is_fence connect slots_2.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[2].wakeup_ports[3].bits.uop.is_sfb connect slots_2.io.wakeup_ports[3].bits.uop.br_type, issue_slots[2].wakeup_ports[3].bits.uop.br_type connect slots_2.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[2].wakeup_ports[3].bits.uop.br_tag connect slots_2.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[2].wakeup_ports[3].bits.uop.br_mask connect slots_2.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[3].bits.uop.dis_col_sel connect slots_2.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_2.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_2.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_2.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_2.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_2.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_2.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_2.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[2].wakeup_ports[3].bits.uop.iw_issued connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[0] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[1] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[2] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[3] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[4] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[5] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[6] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[7] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[8] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[9] connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[0] connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[1] connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[2] connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[3] connect slots_2.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[2].wakeup_ports[3].bits.uop.debug_pc connect slots_2.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[2].wakeup_ports[3].bits.uop.is_rvc connect slots_2.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[2].wakeup_ports[3].bits.uop.debug_inst connect slots_2.io.wakeup_ports[3].bits.uop.inst, issue_slots[2].wakeup_ports[3].bits.uop.inst connect slots_2.io.wakeup_ports[3].valid, issue_slots[2].wakeup_ports[3].valid connect slots_2.io.wakeup_ports[4].bits.rebusy, issue_slots[2].wakeup_ports[4].bits.rebusy connect slots_2.io.wakeup_ports[4].bits.speculative_mask, issue_slots[2].wakeup_ports[4].bits.speculative_mask connect slots_2.io.wakeup_ports[4].bits.bypassable, issue_slots[2].wakeup_ports[4].bits.bypassable connect slots_2.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[4].bits.uop.debug_tsrc connect slots_2.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[4].bits.uop.debug_fsrc connect slots_2.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_2.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[4].bits.uop.bp_debug_if connect slots_2.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_2.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_2.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_2.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[2].wakeup_ports[4].bits.uop.fp_typ connect slots_2.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[2].wakeup_ports[4].bits.uop.fp_rm connect slots_2.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[2].wakeup_ports[4].bits.uop.fp_val connect slots_2.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[2].wakeup_ports[4].bits.uop.fcn_op connect slots_2.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[4].bits.uop.fcn_dw connect slots_2.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[2].wakeup_ports[4].bits.uop.frs3_en connect slots_2.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_2.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_2.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[4].bits.uop.dst_rtype connect slots_2.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[2].wakeup_ports[4].bits.uop.lrs3 connect slots_2.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[2].wakeup_ports[4].bits.uop.lrs2 connect slots_2.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[2].wakeup_ports[4].bits.uop.lrs1 connect slots_2.io.wakeup_ports[4].bits.uop.ldst, issue_slots[2].wakeup_ports[4].bits.uop.ldst connect slots_2.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_2.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[4].bits.uop.csr_cmd connect slots_2.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[4].bits.uop.flush_on_commit connect slots_2.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[2].wakeup_ports[4].bits.uop.is_unique connect slots_2.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[2].wakeup_ports[4].bits.uop.uses_stq connect slots_2.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[4].bits.uop.uses_ldq connect slots_2.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[2].wakeup_ports[4].bits.uop.mem_signed connect slots_2.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[2].wakeup_ports[4].bits.uop.mem_size connect slots_2.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[4].bits.uop.mem_cmd connect slots_2.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[2].wakeup_ports[4].bits.uop.exc_cause connect slots_2.io.wakeup_ports[4].bits.uop.exception, issue_slots[2].wakeup_ports[4].bits.uop.exception connect slots_2.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[4].bits.uop.stale_pdst connect slots_2.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[4].bits.uop.ppred_busy connect slots_2.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[4].bits.uop.prs3_busy connect slots_2.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[4].bits.uop.prs2_busy connect slots_2.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[4].bits.uop.prs1_busy connect slots_2.io.wakeup_ports[4].bits.uop.ppred, issue_slots[2].wakeup_ports[4].bits.uop.ppred connect slots_2.io.wakeup_ports[4].bits.uop.prs3, issue_slots[2].wakeup_ports[4].bits.uop.prs3 connect slots_2.io.wakeup_ports[4].bits.uop.prs2, issue_slots[2].wakeup_ports[4].bits.uop.prs2 connect slots_2.io.wakeup_ports[4].bits.uop.prs1, issue_slots[2].wakeup_ports[4].bits.uop.prs1 connect slots_2.io.wakeup_ports[4].bits.uop.pdst, issue_slots[2].wakeup_ports[4].bits.uop.pdst connect slots_2.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[4].bits.uop.rxq_idx connect slots_2.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[2].wakeup_ports[4].bits.uop.stq_idx connect slots_2.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[4].bits.uop.ldq_idx connect slots_2.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[2].wakeup_ports[4].bits.uop.rob_idx connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_2.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[2].wakeup_ports[4].bits.uop.op2_sel connect slots_2.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[2].wakeup_ports[4].bits.uop.op1_sel connect slots_2.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[2].wakeup_ports[4].bits.uop.imm_packed connect slots_2.io.wakeup_ports[4].bits.uop.pimm, issue_slots[2].wakeup_ports[4].bits.uop.pimm connect slots_2.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[2].wakeup_ports[4].bits.uop.imm_sel connect slots_2.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[2].wakeup_ports[4].bits.uop.imm_rename connect slots_2.io.wakeup_ports[4].bits.uop.taken, issue_slots[2].wakeup_ports[4].bits.uop.taken connect slots_2.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[2].wakeup_ports[4].bits.uop.pc_lob connect slots_2.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[2].wakeup_ports[4].bits.uop.edge_inst connect slots_2.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[4].bits.uop.ftq_idx connect slots_2.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[2].wakeup_ports[4].bits.uop.is_mov connect slots_2.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[2].wakeup_ports[4].bits.uop.is_rocc connect slots_2.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_2.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[2].wakeup_ports[4].bits.uop.is_eret connect slots_2.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[2].wakeup_ports[4].bits.uop.is_amo connect slots_2.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[2].wakeup_ports[4].bits.uop.is_sfence connect slots_2.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[2].wakeup_ports[4].bits.uop.is_fencei connect slots_2.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[2].wakeup_ports[4].bits.uop.is_fence connect slots_2.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[2].wakeup_ports[4].bits.uop.is_sfb connect slots_2.io.wakeup_ports[4].bits.uop.br_type, issue_slots[2].wakeup_ports[4].bits.uop.br_type connect slots_2.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[2].wakeup_ports[4].bits.uop.br_tag connect slots_2.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[2].wakeup_ports[4].bits.uop.br_mask connect slots_2.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[4].bits.uop.dis_col_sel connect slots_2.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_2.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_2.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_2.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_2.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_2.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_2.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_2.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[2].wakeup_ports[4].bits.uop.iw_issued connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[0] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[1] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[2] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[3] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[4] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[5] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[6] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[7] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[8] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[9] connect slots_2.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[4].bits.uop.iq_type[0] connect slots_2.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[4].bits.uop.iq_type[1] connect slots_2.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[4].bits.uop.iq_type[2] connect slots_2.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[4].bits.uop.iq_type[3] connect slots_2.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[2].wakeup_ports[4].bits.uop.debug_pc connect slots_2.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[2].wakeup_ports[4].bits.uop.is_rvc connect slots_2.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[2].wakeup_ports[4].bits.uop.debug_inst connect slots_2.io.wakeup_ports[4].bits.uop.inst, issue_slots[2].wakeup_ports[4].bits.uop.inst connect slots_2.io.wakeup_ports[4].valid, issue_slots[2].wakeup_ports[4].valid connect slots_2.io.squash_grant, issue_slots[2].squash_grant connect slots_2.io.clear, issue_slots[2].clear connect slots_2.io.kill, issue_slots[2].kill connect slots_2.io.brupdate.b2.target_offset, issue_slots[2].brupdate.b2.target_offset connect slots_2.io.brupdate.b2.jalr_target, issue_slots[2].brupdate.b2.jalr_target connect slots_2.io.brupdate.b2.pc_sel, issue_slots[2].brupdate.b2.pc_sel connect slots_2.io.brupdate.b2.cfi_type, issue_slots[2].brupdate.b2.cfi_type connect slots_2.io.brupdate.b2.taken, issue_slots[2].brupdate.b2.taken connect slots_2.io.brupdate.b2.mispredict, issue_slots[2].brupdate.b2.mispredict connect slots_2.io.brupdate.b2.uop.debug_tsrc, issue_slots[2].brupdate.b2.uop.debug_tsrc connect slots_2.io.brupdate.b2.uop.debug_fsrc, issue_slots[2].brupdate.b2.uop.debug_fsrc connect slots_2.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[2].brupdate.b2.uop.bp_xcpt_if connect slots_2.io.brupdate.b2.uop.bp_debug_if, issue_slots[2].brupdate.b2.uop.bp_debug_if connect slots_2.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[2].brupdate.b2.uop.xcpt_ma_if connect slots_2.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[2].brupdate.b2.uop.xcpt_ae_if connect slots_2.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[2].brupdate.b2.uop.xcpt_pf_if connect slots_2.io.brupdate.b2.uop.fp_typ, issue_slots[2].brupdate.b2.uop.fp_typ connect slots_2.io.brupdate.b2.uop.fp_rm, issue_slots[2].brupdate.b2.uop.fp_rm connect slots_2.io.brupdate.b2.uop.fp_val, issue_slots[2].brupdate.b2.uop.fp_val connect slots_2.io.brupdate.b2.uop.fcn_op, issue_slots[2].brupdate.b2.uop.fcn_op connect slots_2.io.brupdate.b2.uop.fcn_dw, issue_slots[2].brupdate.b2.uop.fcn_dw connect slots_2.io.brupdate.b2.uop.frs3_en, issue_slots[2].brupdate.b2.uop.frs3_en connect slots_2.io.brupdate.b2.uop.lrs2_rtype, issue_slots[2].brupdate.b2.uop.lrs2_rtype connect slots_2.io.brupdate.b2.uop.lrs1_rtype, issue_slots[2].brupdate.b2.uop.lrs1_rtype connect slots_2.io.brupdate.b2.uop.dst_rtype, issue_slots[2].brupdate.b2.uop.dst_rtype connect slots_2.io.brupdate.b2.uop.lrs3, issue_slots[2].brupdate.b2.uop.lrs3 connect slots_2.io.brupdate.b2.uop.lrs2, issue_slots[2].brupdate.b2.uop.lrs2 connect slots_2.io.brupdate.b2.uop.lrs1, issue_slots[2].brupdate.b2.uop.lrs1 connect slots_2.io.brupdate.b2.uop.ldst, issue_slots[2].brupdate.b2.uop.ldst connect slots_2.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[2].brupdate.b2.uop.ldst_is_rs1 connect slots_2.io.brupdate.b2.uop.csr_cmd, issue_slots[2].brupdate.b2.uop.csr_cmd connect slots_2.io.brupdate.b2.uop.flush_on_commit, issue_slots[2].brupdate.b2.uop.flush_on_commit connect slots_2.io.brupdate.b2.uop.is_unique, issue_slots[2].brupdate.b2.uop.is_unique connect slots_2.io.brupdate.b2.uop.uses_stq, issue_slots[2].brupdate.b2.uop.uses_stq connect slots_2.io.brupdate.b2.uop.uses_ldq, issue_slots[2].brupdate.b2.uop.uses_ldq connect slots_2.io.brupdate.b2.uop.mem_signed, issue_slots[2].brupdate.b2.uop.mem_signed connect slots_2.io.brupdate.b2.uop.mem_size, issue_slots[2].brupdate.b2.uop.mem_size connect slots_2.io.brupdate.b2.uop.mem_cmd, issue_slots[2].brupdate.b2.uop.mem_cmd connect slots_2.io.brupdate.b2.uop.exc_cause, issue_slots[2].brupdate.b2.uop.exc_cause connect slots_2.io.brupdate.b2.uop.exception, issue_slots[2].brupdate.b2.uop.exception connect slots_2.io.brupdate.b2.uop.stale_pdst, issue_slots[2].brupdate.b2.uop.stale_pdst connect slots_2.io.brupdate.b2.uop.ppred_busy, issue_slots[2].brupdate.b2.uop.ppred_busy connect slots_2.io.brupdate.b2.uop.prs3_busy, issue_slots[2].brupdate.b2.uop.prs3_busy connect slots_2.io.brupdate.b2.uop.prs2_busy, issue_slots[2].brupdate.b2.uop.prs2_busy connect slots_2.io.brupdate.b2.uop.prs1_busy, issue_slots[2].brupdate.b2.uop.prs1_busy connect slots_2.io.brupdate.b2.uop.ppred, issue_slots[2].brupdate.b2.uop.ppred connect slots_2.io.brupdate.b2.uop.prs3, issue_slots[2].brupdate.b2.uop.prs3 connect slots_2.io.brupdate.b2.uop.prs2, issue_slots[2].brupdate.b2.uop.prs2 connect slots_2.io.brupdate.b2.uop.prs1, issue_slots[2].brupdate.b2.uop.prs1 connect slots_2.io.brupdate.b2.uop.pdst, issue_slots[2].brupdate.b2.uop.pdst connect slots_2.io.brupdate.b2.uop.rxq_idx, issue_slots[2].brupdate.b2.uop.rxq_idx connect slots_2.io.brupdate.b2.uop.stq_idx, issue_slots[2].brupdate.b2.uop.stq_idx connect slots_2.io.brupdate.b2.uop.ldq_idx, issue_slots[2].brupdate.b2.uop.ldq_idx connect slots_2.io.brupdate.b2.uop.rob_idx, issue_slots[2].brupdate.b2.uop.rob_idx connect slots_2.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[2].brupdate.b2.uop.fp_ctrl.vec connect slots_2.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[2].brupdate.b2.uop.fp_ctrl.wflags connect slots_2.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[2].brupdate.b2.uop.fp_ctrl.sqrt connect slots_2.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[2].brupdate.b2.uop.fp_ctrl.div connect slots_2.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[2].brupdate.b2.uop.fp_ctrl.fma connect slots_2.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[2].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_2.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[2].brupdate.b2.uop.fp_ctrl.toint connect slots_2.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[2].brupdate.b2.uop.fp_ctrl.fromint connect slots_2.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_2.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_2.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[2].brupdate.b2.uop.fp_ctrl.swap23 connect slots_2.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[2].brupdate.b2.uop.fp_ctrl.swap12 connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren3 connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren2 connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren1 connect slots_2.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[2].brupdate.b2.uop.fp_ctrl.wen connect slots_2.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[2].brupdate.b2.uop.fp_ctrl.ldst connect slots_2.io.brupdate.b2.uop.op2_sel, issue_slots[2].brupdate.b2.uop.op2_sel connect slots_2.io.brupdate.b2.uop.op1_sel, issue_slots[2].brupdate.b2.uop.op1_sel connect slots_2.io.brupdate.b2.uop.imm_packed, issue_slots[2].brupdate.b2.uop.imm_packed connect slots_2.io.brupdate.b2.uop.pimm, issue_slots[2].brupdate.b2.uop.pimm connect slots_2.io.brupdate.b2.uop.imm_sel, issue_slots[2].brupdate.b2.uop.imm_sel connect slots_2.io.brupdate.b2.uop.imm_rename, issue_slots[2].brupdate.b2.uop.imm_rename connect slots_2.io.brupdate.b2.uop.taken, issue_slots[2].brupdate.b2.uop.taken connect slots_2.io.brupdate.b2.uop.pc_lob, issue_slots[2].brupdate.b2.uop.pc_lob connect slots_2.io.brupdate.b2.uop.edge_inst, issue_slots[2].brupdate.b2.uop.edge_inst connect slots_2.io.brupdate.b2.uop.ftq_idx, issue_slots[2].brupdate.b2.uop.ftq_idx connect slots_2.io.brupdate.b2.uop.is_mov, issue_slots[2].brupdate.b2.uop.is_mov connect slots_2.io.brupdate.b2.uop.is_rocc, issue_slots[2].brupdate.b2.uop.is_rocc connect slots_2.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[2].brupdate.b2.uop.is_sys_pc2epc connect slots_2.io.brupdate.b2.uop.is_eret, issue_slots[2].brupdate.b2.uop.is_eret connect slots_2.io.brupdate.b2.uop.is_amo, issue_slots[2].brupdate.b2.uop.is_amo connect slots_2.io.brupdate.b2.uop.is_sfence, issue_slots[2].brupdate.b2.uop.is_sfence connect slots_2.io.brupdate.b2.uop.is_fencei, issue_slots[2].brupdate.b2.uop.is_fencei connect slots_2.io.brupdate.b2.uop.is_fence, issue_slots[2].brupdate.b2.uop.is_fence connect slots_2.io.brupdate.b2.uop.is_sfb, issue_slots[2].brupdate.b2.uop.is_sfb connect slots_2.io.brupdate.b2.uop.br_type, issue_slots[2].brupdate.b2.uop.br_type connect slots_2.io.brupdate.b2.uop.br_tag, issue_slots[2].brupdate.b2.uop.br_tag connect slots_2.io.brupdate.b2.uop.br_mask, issue_slots[2].brupdate.b2.uop.br_mask connect slots_2.io.brupdate.b2.uop.dis_col_sel, issue_slots[2].brupdate.b2.uop.dis_col_sel connect slots_2.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p3_bypass_hint connect slots_2.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p2_bypass_hint connect slots_2.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p1_bypass_hint connect slots_2.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[2].brupdate.b2.uop.iw_p2_speculative_child connect slots_2.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[2].brupdate.b2.uop.iw_p1_speculative_child connect slots_2.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[2].brupdate.b2.uop.iw_issued_partial_dgen connect slots_2.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[2].brupdate.b2.uop.iw_issued_partial_agen connect slots_2.io.brupdate.b2.uop.iw_issued, issue_slots[2].brupdate.b2.uop.iw_issued connect slots_2.io.brupdate.b2.uop.fu_code[0], issue_slots[2].brupdate.b2.uop.fu_code[0] connect slots_2.io.brupdate.b2.uop.fu_code[1], issue_slots[2].brupdate.b2.uop.fu_code[1] connect slots_2.io.brupdate.b2.uop.fu_code[2], issue_slots[2].brupdate.b2.uop.fu_code[2] connect slots_2.io.brupdate.b2.uop.fu_code[3], issue_slots[2].brupdate.b2.uop.fu_code[3] connect slots_2.io.brupdate.b2.uop.fu_code[4], issue_slots[2].brupdate.b2.uop.fu_code[4] connect slots_2.io.brupdate.b2.uop.fu_code[5], issue_slots[2].brupdate.b2.uop.fu_code[5] connect slots_2.io.brupdate.b2.uop.fu_code[6], issue_slots[2].brupdate.b2.uop.fu_code[6] connect slots_2.io.brupdate.b2.uop.fu_code[7], issue_slots[2].brupdate.b2.uop.fu_code[7] connect slots_2.io.brupdate.b2.uop.fu_code[8], issue_slots[2].brupdate.b2.uop.fu_code[8] connect slots_2.io.brupdate.b2.uop.fu_code[9], issue_slots[2].brupdate.b2.uop.fu_code[9] connect slots_2.io.brupdate.b2.uop.iq_type[0], issue_slots[2].brupdate.b2.uop.iq_type[0] connect slots_2.io.brupdate.b2.uop.iq_type[1], issue_slots[2].brupdate.b2.uop.iq_type[1] connect slots_2.io.brupdate.b2.uop.iq_type[2], issue_slots[2].brupdate.b2.uop.iq_type[2] connect slots_2.io.brupdate.b2.uop.iq_type[3], issue_slots[2].brupdate.b2.uop.iq_type[3] connect slots_2.io.brupdate.b2.uop.debug_pc, issue_slots[2].brupdate.b2.uop.debug_pc connect slots_2.io.brupdate.b2.uop.is_rvc, issue_slots[2].brupdate.b2.uop.is_rvc connect slots_2.io.brupdate.b2.uop.debug_inst, issue_slots[2].brupdate.b2.uop.debug_inst connect slots_2.io.brupdate.b2.uop.inst, issue_slots[2].brupdate.b2.uop.inst connect slots_2.io.brupdate.b1.mispredict_mask, issue_slots[2].brupdate.b1.mispredict_mask connect slots_2.io.brupdate.b1.resolve_mask, issue_slots[2].brupdate.b1.resolve_mask connect issue_slots[2].out_uop.debug_tsrc, slots_2.io.out_uop.debug_tsrc connect issue_slots[2].out_uop.debug_fsrc, slots_2.io.out_uop.debug_fsrc connect issue_slots[2].out_uop.bp_xcpt_if, slots_2.io.out_uop.bp_xcpt_if connect issue_slots[2].out_uop.bp_debug_if, slots_2.io.out_uop.bp_debug_if connect issue_slots[2].out_uop.xcpt_ma_if, slots_2.io.out_uop.xcpt_ma_if connect issue_slots[2].out_uop.xcpt_ae_if, slots_2.io.out_uop.xcpt_ae_if connect issue_slots[2].out_uop.xcpt_pf_if, slots_2.io.out_uop.xcpt_pf_if connect issue_slots[2].out_uop.fp_typ, slots_2.io.out_uop.fp_typ connect issue_slots[2].out_uop.fp_rm, slots_2.io.out_uop.fp_rm connect issue_slots[2].out_uop.fp_val, slots_2.io.out_uop.fp_val connect issue_slots[2].out_uop.fcn_op, slots_2.io.out_uop.fcn_op connect issue_slots[2].out_uop.fcn_dw, slots_2.io.out_uop.fcn_dw connect issue_slots[2].out_uop.frs3_en, slots_2.io.out_uop.frs3_en connect issue_slots[2].out_uop.lrs2_rtype, slots_2.io.out_uop.lrs2_rtype connect issue_slots[2].out_uop.lrs1_rtype, slots_2.io.out_uop.lrs1_rtype connect issue_slots[2].out_uop.dst_rtype, slots_2.io.out_uop.dst_rtype connect issue_slots[2].out_uop.lrs3, slots_2.io.out_uop.lrs3 connect issue_slots[2].out_uop.lrs2, slots_2.io.out_uop.lrs2 connect issue_slots[2].out_uop.lrs1, slots_2.io.out_uop.lrs1 connect issue_slots[2].out_uop.ldst, slots_2.io.out_uop.ldst connect issue_slots[2].out_uop.ldst_is_rs1, slots_2.io.out_uop.ldst_is_rs1 connect issue_slots[2].out_uop.csr_cmd, slots_2.io.out_uop.csr_cmd connect issue_slots[2].out_uop.flush_on_commit, slots_2.io.out_uop.flush_on_commit connect issue_slots[2].out_uop.is_unique, slots_2.io.out_uop.is_unique connect issue_slots[2].out_uop.uses_stq, slots_2.io.out_uop.uses_stq connect issue_slots[2].out_uop.uses_ldq, slots_2.io.out_uop.uses_ldq connect issue_slots[2].out_uop.mem_signed, slots_2.io.out_uop.mem_signed connect issue_slots[2].out_uop.mem_size, slots_2.io.out_uop.mem_size connect issue_slots[2].out_uop.mem_cmd, slots_2.io.out_uop.mem_cmd connect issue_slots[2].out_uop.exc_cause, slots_2.io.out_uop.exc_cause connect issue_slots[2].out_uop.exception, slots_2.io.out_uop.exception connect issue_slots[2].out_uop.stale_pdst, slots_2.io.out_uop.stale_pdst connect issue_slots[2].out_uop.ppred_busy, slots_2.io.out_uop.ppred_busy connect issue_slots[2].out_uop.prs3_busy, slots_2.io.out_uop.prs3_busy connect issue_slots[2].out_uop.prs2_busy, slots_2.io.out_uop.prs2_busy connect issue_slots[2].out_uop.prs1_busy, slots_2.io.out_uop.prs1_busy connect issue_slots[2].out_uop.ppred, slots_2.io.out_uop.ppred connect issue_slots[2].out_uop.prs3, slots_2.io.out_uop.prs3 connect issue_slots[2].out_uop.prs2, slots_2.io.out_uop.prs2 connect issue_slots[2].out_uop.prs1, slots_2.io.out_uop.prs1 connect issue_slots[2].out_uop.pdst, slots_2.io.out_uop.pdst connect issue_slots[2].out_uop.rxq_idx, slots_2.io.out_uop.rxq_idx connect issue_slots[2].out_uop.stq_idx, slots_2.io.out_uop.stq_idx connect issue_slots[2].out_uop.ldq_idx, slots_2.io.out_uop.ldq_idx connect issue_slots[2].out_uop.rob_idx, slots_2.io.out_uop.rob_idx connect issue_slots[2].out_uop.fp_ctrl.vec, slots_2.io.out_uop.fp_ctrl.vec connect issue_slots[2].out_uop.fp_ctrl.wflags, slots_2.io.out_uop.fp_ctrl.wflags connect issue_slots[2].out_uop.fp_ctrl.sqrt, slots_2.io.out_uop.fp_ctrl.sqrt connect issue_slots[2].out_uop.fp_ctrl.div, slots_2.io.out_uop.fp_ctrl.div connect issue_slots[2].out_uop.fp_ctrl.fma, slots_2.io.out_uop.fp_ctrl.fma connect issue_slots[2].out_uop.fp_ctrl.fastpipe, slots_2.io.out_uop.fp_ctrl.fastpipe connect issue_slots[2].out_uop.fp_ctrl.toint, slots_2.io.out_uop.fp_ctrl.toint connect issue_slots[2].out_uop.fp_ctrl.fromint, slots_2.io.out_uop.fp_ctrl.fromint connect issue_slots[2].out_uop.fp_ctrl.typeTagOut, slots_2.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[2].out_uop.fp_ctrl.typeTagIn, slots_2.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[2].out_uop.fp_ctrl.swap23, slots_2.io.out_uop.fp_ctrl.swap23 connect issue_slots[2].out_uop.fp_ctrl.swap12, slots_2.io.out_uop.fp_ctrl.swap12 connect issue_slots[2].out_uop.fp_ctrl.ren3, slots_2.io.out_uop.fp_ctrl.ren3 connect issue_slots[2].out_uop.fp_ctrl.ren2, slots_2.io.out_uop.fp_ctrl.ren2 connect issue_slots[2].out_uop.fp_ctrl.ren1, slots_2.io.out_uop.fp_ctrl.ren1 connect issue_slots[2].out_uop.fp_ctrl.wen, slots_2.io.out_uop.fp_ctrl.wen connect issue_slots[2].out_uop.fp_ctrl.ldst, slots_2.io.out_uop.fp_ctrl.ldst connect issue_slots[2].out_uop.op2_sel, slots_2.io.out_uop.op2_sel connect issue_slots[2].out_uop.op1_sel, slots_2.io.out_uop.op1_sel connect issue_slots[2].out_uop.imm_packed, slots_2.io.out_uop.imm_packed connect issue_slots[2].out_uop.pimm, slots_2.io.out_uop.pimm connect issue_slots[2].out_uop.imm_sel, slots_2.io.out_uop.imm_sel connect issue_slots[2].out_uop.imm_rename, slots_2.io.out_uop.imm_rename connect issue_slots[2].out_uop.taken, slots_2.io.out_uop.taken connect issue_slots[2].out_uop.pc_lob, slots_2.io.out_uop.pc_lob connect issue_slots[2].out_uop.edge_inst, slots_2.io.out_uop.edge_inst connect issue_slots[2].out_uop.ftq_idx, slots_2.io.out_uop.ftq_idx connect issue_slots[2].out_uop.is_mov, slots_2.io.out_uop.is_mov connect issue_slots[2].out_uop.is_rocc, slots_2.io.out_uop.is_rocc connect issue_slots[2].out_uop.is_sys_pc2epc, slots_2.io.out_uop.is_sys_pc2epc connect issue_slots[2].out_uop.is_eret, slots_2.io.out_uop.is_eret connect issue_slots[2].out_uop.is_amo, slots_2.io.out_uop.is_amo connect issue_slots[2].out_uop.is_sfence, slots_2.io.out_uop.is_sfence connect issue_slots[2].out_uop.is_fencei, slots_2.io.out_uop.is_fencei connect issue_slots[2].out_uop.is_fence, slots_2.io.out_uop.is_fence connect issue_slots[2].out_uop.is_sfb, slots_2.io.out_uop.is_sfb connect issue_slots[2].out_uop.br_type, slots_2.io.out_uop.br_type connect issue_slots[2].out_uop.br_tag, slots_2.io.out_uop.br_tag connect issue_slots[2].out_uop.br_mask, slots_2.io.out_uop.br_mask connect issue_slots[2].out_uop.dis_col_sel, slots_2.io.out_uop.dis_col_sel connect issue_slots[2].out_uop.iw_p3_bypass_hint, slots_2.io.out_uop.iw_p3_bypass_hint connect issue_slots[2].out_uop.iw_p2_bypass_hint, slots_2.io.out_uop.iw_p2_bypass_hint connect issue_slots[2].out_uop.iw_p1_bypass_hint, slots_2.io.out_uop.iw_p1_bypass_hint connect issue_slots[2].out_uop.iw_p2_speculative_child, slots_2.io.out_uop.iw_p2_speculative_child connect issue_slots[2].out_uop.iw_p1_speculative_child, slots_2.io.out_uop.iw_p1_speculative_child connect issue_slots[2].out_uop.iw_issued_partial_dgen, slots_2.io.out_uop.iw_issued_partial_dgen connect issue_slots[2].out_uop.iw_issued_partial_agen, slots_2.io.out_uop.iw_issued_partial_agen connect issue_slots[2].out_uop.iw_issued, slots_2.io.out_uop.iw_issued connect issue_slots[2].out_uop.fu_code[0], slots_2.io.out_uop.fu_code[0] connect issue_slots[2].out_uop.fu_code[1], slots_2.io.out_uop.fu_code[1] connect issue_slots[2].out_uop.fu_code[2], slots_2.io.out_uop.fu_code[2] connect issue_slots[2].out_uop.fu_code[3], slots_2.io.out_uop.fu_code[3] connect issue_slots[2].out_uop.fu_code[4], slots_2.io.out_uop.fu_code[4] connect issue_slots[2].out_uop.fu_code[5], slots_2.io.out_uop.fu_code[5] connect issue_slots[2].out_uop.fu_code[6], slots_2.io.out_uop.fu_code[6] connect issue_slots[2].out_uop.fu_code[7], slots_2.io.out_uop.fu_code[7] connect issue_slots[2].out_uop.fu_code[8], slots_2.io.out_uop.fu_code[8] connect issue_slots[2].out_uop.fu_code[9], slots_2.io.out_uop.fu_code[9] connect issue_slots[2].out_uop.iq_type[0], slots_2.io.out_uop.iq_type[0] connect issue_slots[2].out_uop.iq_type[1], slots_2.io.out_uop.iq_type[1] connect issue_slots[2].out_uop.iq_type[2], slots_2.io.out_uop.iq_type[2] connect issue_slots[2].out_uop.iq_type[3], slots_2.io.out_uop.iq_type[3] connect issue_slots[2].out_uop.debug_pc, slots_2.io.out_uop.debug_pc connect issue_slots[2].out_uop.is_rvc, slots_2.io.out_uop.is_rvc connect issue_slots[2].out_uop.debug_inst, slots_2.io.out_uop.debug_inst connect issue_slots[2].out_uop.inst, slots_2.io.out_uop.inst connect slots_2.io.in_uop.bits.debug_tsrc, issue_slots[2].in_uop.bits.debug_tsrc connect slots_2.io.in_uop.bits.debug_fsrc, issue_slots[2].in_uop.bits.debug_fsrc connect slots_2.io.in_uop.bits.bp_xcpt_if, issue_slots[2].in_uop.bits.bp_xcpt_if connect slots_2.io.in_uop.bits.bp_debug_if, issue_slots[2].in_uop.bits.bp_debug_if connect slots_2.io.in_uop.bits.xcpt_ma_if, issue_slots[2].in_uop.bits.xcpt_ma_if connect slots_2.io.in_uop.bits.xcpt_ae_if, issue_slots[2].in_uop.bits.xcpt_ae_if connect slots_2.io.in_uop.bits.xcpt_pf_if, issue_slots[2].in_uop.bits.xcpt_pf_if connect slots_2.io.in_uop.bits.fp_typ, issue_slots[2].in_uop.bits.fp_typ connect slots_2.io.in_uop.bits.fp_rm, issue_slots[2].in_uop.bits.fp_rm connect slots_2.io.in_uop.bits.fp_val, issue_slots[2].in_uop.bits.fp_val connect slots_2.io.in_uop.bits.fcn_op, issue_slots[2].in_uop.bits.fcn_op connect slots_2.io.in_uop.bits.fcn_dw, issue_slots[2].in_uop.bits.fcn_dw connect slots_2.io.in_uop.bits.frs3_en, issue_slots[2].in_uop.bits.frs3_en connect slots_2.io.in_uop.bits.lrs2_rtype, issue_slots[2].in_uop.bits.lrs2_rtype connect slots_2.io.in_uop.bits.lrs1_rtype, issue_slots[2].in_uop.bits.lrs1_rtype connect slots_2.io.in_uop.bits.dst_rtype, issue_slots[2].in_uop.bits.dst_rtype connect slots_2.io.in_uop.bits.lrs3, issue_slots[2].in_uop.bits.lrs3 connect slots_2.io.in_uop.bits.lrs2, issue_slots[2].in_uop.bits.lrs2 connect slots_2.io.in_uop.bits.lrs1, issue_slots[2].in_uop.bits.lrs1 connect slots_2.io.in_uop.bits.ldst, issue_slots[2].in_uop.bits.ldst connect slots_2.io.in_uop.bits.ldst_is_rs1, issue_slots[2].in_uop.bits.ldst_is_rs1 connect slots_2.io.in_uop.bits.csr_cmd, issue_slots[2].in_uop.bits.csr_cmd connect slots_2.io.in_uop.bits.flush_on_commit, issue_slots[2].in_uop.bits.flush_on_commit connect slots_2.io.in_uop.bits.is_unique, issue_slots[2].in_uop.bits.is_unique connect slots_2.io.in_uop.bits.uses_stq, issue_slots[2].in_uop.bits.uses_stq connect slots_2.io.in_uop.bits.uses_ldq, issue_slots[2].in_uop.bits.uses_ldq connect slots_2.io.in_uop.bits.mem_signed, issue_slots[2].in_uop.bits.mem_signed connect slots_2.io.in_uop.bits.mem_size, issue_slots[2].in_uop.bits.mem_size connect slots_2.io.in_uop.bits.mem_cmd, issue_slots[2].in_uop.bits.mem_cmd connect slots_2.io.in_uop.bits.exc_cause, issue_slots[2].in_uop.bits.exc_cause connect slots_2.io.in_uop.bits.exception, issue_slots[2].in_uop.bits.exception connect slots_2.io.in_uop.bits.stale_pdst, issue_slots[2].in_uop.bits.stale_pdst connect slots_2.io.in_uop.bits.ppred_busy, issue_slots[2].in_uop.bits.ppred_busy connect slots_2.io.in_uop.bits.prs3_busy, issue_slots[2].in_uop.bits.prs3_busy connect slots_2.io.in_uop.bits.prs2_busy, issue_slots[2].in_uop.bits.prs2_busy connect slots_2.io.in_uop.bits.prs1_busy, issue_slots[2].in_uop.bits.prs1_busy connect slots_2.io.in_uop.bits.ppred, issue_slots[2].in_uop.bits.ppred connect slots_2.io.in_uop.bits.prs3, issue_slots[2].in_uop.bits.prs3 connect slots_2.io.in_uop.bits.prs2, issue_slots[2].in_uop.bits.prs2 connect slots_2.io.in_uop.bits.prs1, issue_slots[2].in_uop.bits.prs1 connect slots_2.io.in_uop.bits.pdst, issue_slots[2].in_uop.bits.pdst connect slots_2.io.in_uop.bits.rxq_idx, issue_slots[2].in_uop.bits.rxq_idx connect slots_2.io.in_uop.bits.stq_idx, issue_slots[2].in_uop.bits.stq_idx connect slots_2.io.in_uop.bits.ldq_idx, issue_slots[2].in_uop.bits.ldq_idx connect slots_2.io.in_uop.bits.rob_idx, issue_slots[2].in_uop.bits.rob_idx connect slots_2.io.in_uop.bits.fp_ctrl.vec, issue_slots[2].in_uop.bits.fp_ctrl.vec connect slots_2.io.in_uop.bits.fp_ctrl.wflags, issue_slots[2].in_uop.bits.fp_ctrl.wflags connect slots_2.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[2].in_uop.bits.fp_ctrl.sqrt connect slots_2.io.in_uop.bits.fp_ctrl.div, issue_slots[2].in_uop.bits.fp_ctrl.div connect slots_2.io.in_uop.bits.fp_ctrl.fma, issue_slots[2].in_uop.bits.fp_ctrl.fma connect slots_2.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].in_uop.bits.fp_ctrl.fastpipe connect slots_2.io.in_uop.bits.fp_ctrl.toint, issue_slots[2].in_uop.bits.fp_ctrl.toint connect slots_2.io.in_uop.bits.fp_ctrl.fromint, issue_slots[2].in_uop.bits.fp_ctrl.fromint connect slots_2.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut connect slots_2.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn connect slots_2.io.in_uop.bits.fp_ctrl.swap23, issue_slots[2].in_uop.bits.fp_ctrl.swap23 connect slots_2.io.in_uop.bits.fp_ctrl.swap12, issue_slots[2].in_uop.bits.fp_ctrl.swap12 connect slots_2.io.in_uop.bits.fp_ctrl.ren3, issue_slots[2].in_uop.bits.fp_ctrl.ren3 connect slots_2.io.in_uop.bits.fp_ctrl.ren2, issue_slots[2].in_uop.bits.fp_ctrl.ren2 connect slots_2.io.in_uop.bits.fp_ctrl.ren1, issue_slots[2].in_uop.bits.fp_ctrl.ren1 connect slots_2.io.in_uop.bits.fp_ctrl.wen, issue_slots[2].in_uop.bits.fp_ctrl.wen connect slots_2.io.in_uop.bits.fp_ctrl.ldst, issue_slots[2].in_uop.bits.fp_ctrl.ldst connect slots_2.io.in_uop.bits.op2_sel, issue_slots[2].in_uop.bits.op2_sel connect slots_2.io.in_uop.bits.op1_sel, issue_slots[2].in_uop.bits.op1_sel connect slots_2.io.in_uop.bits.imm_packed, issue_slots[2].in_uop.bits.imm_packed connect slots_2.io.in_uop.bits.pimm, issue_slots[2].in_uop.bits.pimm connect slots_2.io.in_uop.bits.imm_sel, issue_slots[2].in_uop.bits.imm_sel connect slots_2.io.in_uop.bits.imm_rename, issue_slots[2].in_uop.bits.imm_rename connect slots_2.io.in_uop.bits.taken, issue_slots[2].in_uop.bits.taken connect slots_2.io.in_uop.bits.pc_lob, issue_slots[2].in_uop.bits.pc_lob connect slots_2.io.in_uop.bits.edge_inst, issue_slots[2].in_uop.bits.edge_inst connect slots_2.io.in_uop.bits.ftq_idx, issue_slots[2].in_uop.bits.ftq_idx connect slots_2.io.in_uop.bits.is_mov, issue_slots[2].in_uop.bits.is_mov connect slots_2.io.in_uop.bits.is_rocc, issue_slots[2].in_uop.bits.is_rocc connect slots_2.io.in_uop.bits.is_sys_pc2epc, issue_slots[2].in_uop.bits.is_sys_pc2epc connect slots_2.io.in_uop.bits.is_eret, issue_slots[2].in_uop.bits.is_eret connect slots_2.io.in_uop.bits.is_amo, issue_slots[2].in_uop.bits.is_amo connect slots_2.io.in_uop.bits.is_sfence, issue_slots[2].in_uop.bits.is_sfence connect slots_2.io.in_uop.bits.is_fencei, issue_slots[2].in_uop.bits.is_fencei connect slots_2.io.in_uop.bits.is_fence, issue_slots[2].in_uop.bits.is_fence connect slots_2.io.in_uop.bits.is_sfb, issue_slots[2].in_uop.bits.is_sfb connect slots_2.io.in_uop.bits.br_type, issue_slots[2].in_uop.bits.br_type connect slots_2.io.in_uop.bits.br_tag, issue_slots[2].in_uop.bits.br_tag connect slots_2.io.in_uop.bits.br_mask, issue_slots[2].in_uop.bits.br_mask connect slots_2.io.in_uop.bits.dis_col_sel, issue_slots[2].in_uop.bits.dis_col_sel connect slots_2.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[2].in_uop.bits.iw_p3_bypass_hint connect slots_2.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[2].in_uop.bits.iw_p2_bypass_hint connect slots_2.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[2].in_uop.bits.iw_p1_bypass_hint connect slots_2.io.in_uop.bits.iw_p2_speculative_child, issue_slots[2].in_uop.bits.iw_p2_speculative_child connect slots_2.io.in_uop.bits.iw_p1_speculative_child, issue_slots[2].in_uop.bits.iw_p1_speculative_child connect slots_2.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[2].in_uop.bits.iw_issued_partial_dgen connect slots_2.io.in_uop.bits.iw_issued_partial_agen, issue_slots[2].in_uop.bits.iw_issued_partial_agen connect slots_2.io.in_uop.bits.iw_issued, issue_slots[2].in_uop.bits.iw_issued connect slots_2.io.in_uop.bits.fu_code[0], issue_slots[2].in_uop.bits.fu_code[0] connect slots_2.io.in_uop.bits.fu_code[1], issue_slots[2].in_uop.bits.fu_code[1] connect slots_2.io.in_uop.bits.fu_code[2], issue_slots[2].in_uop.bits.fu_code[2] connect slots_2.io.in_uop.bits.fu_code[3], issue_slots[2].in_uop.bits.fu_code[3] connect slots_2.io.in_uop.bits.fu_code[4], issue_slots[2].in_uop.bits.fu_code[4] connect slots_2.io.in_uop.bits.fu_code[5], issue_slots[2].in_uop.bits.fu_code[5] connect slots_2.io.in_uop.bits.fu_code[6], issue_slots[2].in_uop.bits.fu_code[6] connect slots_2.io.in_uop.bits.fu_code[7], issue_slots[2].in_uop.bits.fu_code[7] connect slots_2.io.in_uop.bits.fu_code[8], issue_slots[2].in_uop.bits.fu_code[8] connect slots_2.io.in_uop.bits.fu_code[9], issue_slots[2].in_uop.bits.fu_code[9] connect slots_2.io.in_uop.bits.iq_type[0], issue_slots[2].in_uop.bits.iq_type[0] connect slots_2.io.in_uop.bits.iq_type[1], issue_slots[2].in_uop.bits.iq_type[1] connect slots_2.io.in_uop.bits.iq_type[2], issue_slots[2].in_uop.bits.iq_type[2] connect slots_2.io.in_uop.bits.iq_type[3], issue_slots[2].in_uop.bits.iq_type[3] connect slots_2.io.in_uop.bits.debug_pc, issue_slots[2].in_uop.bits.debug_pc connect slots_2.io.in_uop.bits.is_rvc, issue_slots[2].in_uop.bits.is_rvc connect slots_2.io.in_uop.bits.debug_inst, issue_slots[2].in_uop.bits.debug_inst connect slots_2.io.in_uop.bits.inst, issue_slots[2].in_uop.bits.inst connect slots_2.io.in_uop.valid, issue_slots[2].in_uop.valid connect issue_slots[2].iss_uop.debug_tsrc, slots_2.io.iss_uop.debug_tsrc connect issue_slots[2].iss_uop.debug_fsrc, slots_2.io.iss_uop.debug_fsrc connect issue_slots[2].iss_uop.bp_xcpt_if, slots_2.io.iss_uop.bp_xcpt_if connect issue_slots[2].iss_uop.bp_debug_if, slots_2.io.iss_uop.bp_debug_if connect issue_slots[2].iss_uop.xcpt_ma_if, slots_2.io.iss_uop.xcpt_ma_if connect issue_slots[2].iss_uop.xcpt_ae_if, slots_2.io.iss_uop.xcpt_ae_if connect issue_slots[2].iss_uop.xcpt_pf_if, slots_2.io.iss_uop.xcpt_pf_if connect issue_slots[2].iss_uop.fp_typ, slots_2.io.iss_uop.fp_typ connect issue_slots[2].iss_uop.fp_rm, slots_2.io.iss_uop.fp_rm connect issue_slots[2].iss_uop.fp_val, slots_2.io.iss_uop.fp_val connect issue_slots[2].iss_uop.fcn_op, slots_2.io.iss_uop.fcn_op connect issue_slots[2].iss_uop.fcn_dw, slots_2.io.iss_uop.fcn_dw connect issue_slots[2].iss_uop.frs3_en, slots_2.io.iss_uop.frs3_en connect issue_slots[2].iss_uop.lrs2_rtype, slots_2.io.iss_uop.lrs2_rtype connect issue_slots[2].iss_uop.lrs1_rtype, slots_2.io.iss_uop.lrs1_rtype connect issue_slots[2].iss_uop.dst_rtype, slots_2.io.iss_uop.dst_rtype connect issue_slots[2].iss_uop.lrs3, slots_2.io.iss_uop.lrs3 connect issue_slots[2].iss_uop.lrs2, slots_2.io.iss_uop.lrs2 connect issue_slots[2].iss_uop.lrs1, slots_2.io.iss_uop.lrs1 connect issue_slots[2].iss_uop.ldst, slots_2.io.iss_uop.ldst connect issue_slots[2].iss_uop.ldst_is_rs1, slots_2.io.iss_uop.ldst_is_rs1 connect issue_slots[2].iss_uop.csr_cmd, slots_2.io.iss_uop.csr_cmd connect issue_slots[2].iss_uop.flush_on_commit, slots_2.io.iss_uop.flush_on_commit connect issue_slots[2].iss_uop.is_unique, slots_2.io.iss_uop.is_unique connect issue_slots[2].iss_uop.uses_stq, slots_2.io.iss_uop.uses_stq connect issue_slots[2].iss_uop.uses_ldq, slots_2.io.iss_uop.uses_ldq connect issue_slots[2].iss_uop.mem_signed, slots_2.io.iss_uop.mem_signed connect issue_slots[2].iss_uop.mem_size, slots_2.io.iss_uop.mem_size connect issue_slots[2].iss_uop.mem_cmd, slots_2.io.iss_uop.mem_cmd connect issue_slots[2].iss_uop.exc_cause, slots_2.io.iss_uop.exc_cause connect issue_slots[2].iss_uop.exception, slots_2.io.iss_uop.exception connect issue_slots[2].iss_uop.stale_pdst, slots_2.io.iss_uop.stale_pdst connect issue_slots[2].iss_uop.ppred_busy, slots_2.io.iss_uop.ppred_busy connect issue_slots[2].iss_uop.prs3_busy, slots_2.io.iss_uop.prs3_busy connect issue_slots[2].iss_uop.prs2_busy, slots_2.io.iss_uop.prs2_busy connect issue_slots[2].iss_uop.prs1_busy, slots_2.io.iss_uop.prs1_busy connect issue_slots[2].iss_uop.ppred, slots_2.io.iss_uop.ppred connect issue_slots[2].iss_uop.prs3, slots_2.io.iss_uop.prs3 connect issue_slots[2].iss_uop.prs2, slots_2.io.iss_uop.prs2 connect issue_slots[2].iss_uop.prs1, slots_2.io.iss_uop.prs1 connect issue_slots[2].iss_uop.pdst, slots_2.io.iss_uop.pdst connect issue_slots[2].iss_uop.rxq_idx, slots_2.io.iss_uop.rxq_idx connect issue_slots[2].iss_uop.stq_idx, slots_2.io.iss_uop.stq_idx connect issue_slots[2].iss_uop.ldq_idx, slots_2.io.iss_uop.ldq_idx connect issue_slots[2].iss_uop.rob_idx, slots_2.io.iss_uop.rob_idx connect issue_slots[2].iss_uop.fp_ctrl.vec, slots_2.io.iss_uop.fp_ctrl.vec connect issue_slots[2].iss_uop.fp_ctrl.wflags, slots_2.io.iss_uop.fp_ctrl.wflags connect issue_slots[2].iss_uop.fp_ctrl.sqrt, slots_2.io.iss_uop.fp_ctrl.sqrt connect issue_slots[2].iss_uop.fp_ctrl.div, slots_2.io.iss_uop.fp_ctrl.div connect issue_slots[2].iss_uop.fp_ctrl.fma, slots_2.io.iss_uop.fp_ctrl.fma connect issue_slots[2].iss_uop.fp_ctrl.fastpipe, slots_2.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[2].iss_uop.fp_ctrl.toint, slots_2.io.iss_uop.fp_ctrl.toint connect issue_slots[2].iss_uop.fp_ctrl.fromint, slots_2.io.iss_uop.fp_ctrl.fromint connect issue_slots[2].iss_uop.fp_ctrl.typeTagOut, slots_2.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[2].iss_uop.fp_ctrl.typeTagIn, slots_2.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[2].iss_uop.fp_ctrl.swap23, slots_2.io.iss_uop.fp_ctrl.swap23 connect issue_slots[2].iss_uop.fp_ctrl.swap12, slots_2.io.iss_uop.fp_ctrl.swap12 connect issue_slots[2].iss_uop.fp_ctrl.ren3, slots_2.io.iss_uop.fp_ctrl.ren3 connect issue_slots[2].iss_uop.fp_ctrl.ren2, slots_2.io.iss_uop.fp_ctrl.ren2 connect issue_slots[2].iss_uop.fp_ctrl.ren1, slots_2.io.iss_uop.fp_ctrl.ren1 connect issue_slots[2].iss_uop.fp_ctrl.wen, slots_2.io.iss_uop.fp_ctrl.wen connect issue_slots[2].iss_uop.fp_ctrl.ldst, slots_2.io.iss_uop.fp_ctrl.ldst connect issue_slots[2].iss_uop.op2_sel, slots_2.io.iss_uop.op2_sel connect issue_slots[2].iss_uop.op1_sel, slots_2.io.iss_uop.op1_sel connect issue_slots[2].iss_uop.imm_packed, slots_2.io.iss_uop.imm_packed connect issue_slots[2].iss_uop.pimm, slots_2.io.iss_uop.pimm connect issue_slots[2].iss_uop.imm_sel, slots_2.io.iss_uop.imm_sel connect issue_slots[2].iss_uop.imm_rename, slots_2.io.iss_uop.imm_rename connect issue_slots[2].iss_uop.taken, slots_2.io.iss_uop.taken connect issue_slots[2].iss_uop.pc_lob, slots_2.io.iss_uop.pc_lob connect issue_slots[2].iss_uop.edge_inst, slots_2.io.iss_uop.edge_inst connect issue_slots[2].iss_uop.ftq_idx, slots_2.io.iss_uop.ftq_idx connect issue_slots[2].iss_uop.is_mov, slots_2.io.iss_uop.is_mov connect issue_slots[2].iss_uop.is_rocc, slots_2.io.iss_uop.is_rocc connect issue_slots[2].iss_uop.is_sys_pc2epc, slots_2.io.iss_uop.is_sys_pc2epc connect issue_slots[2].iss_uop.is_eret, slots_2.io.iss_uop.is_eret connect issue_slots[2].iss_uop.is_amo, slots_2.io.iss_uop.is_amo connect issue_slots[2].iss_uop.is_sfence, slots_2.io.iss_uop.is_sfence connect issue_slots[2].iss_uop.is_fencei, slots_2.io.iss_uop.is_fencei connect issue_slots[2].iss_uop.is_fence, slots_2.io.iss_uop.is_fence connect issue_slots[2].iss_uop.is_sfb, slots_2.io.iss_uop.is_sfb connect issue_slots[2].iss_uop.br_type, slots_2.io.iss_uop.br_type connect issue_slots[2].iss_uop.br_tag, slots_2.io.iss_uop.br_tag connect issue_slots[2].iss_uop.br_mask, slots_2.io.iss_uop.br_mask connect issue_slots[2].iss_uop.dis_col_sel, slots_2.io.iss_uop.dis_col_sel connect issue_slots[2].iss_uop.iw_p3_bypass_hint, slots_2.io.iss_uop.iw_p3_bypass_hint connect issue_slots[2].iss_uop.iw_p2_bypass_hint, slots_2.io.iss_uop.iw_p2_bypass_hint connect issue_slots[2].iss_uop.iw_p1_bypass_hint, slots_2.io.iss_uop.iw_p1_bypass_hint connect issue_slots[2].iss_uop.iw_p2_speculative_child, slots_2.io.iss_uop.iw_p2_speculative_child connect issue_slots[2].iss_uop.iw_p1_speculative_child, slots_2.io.iss_uop.iw_p1_speculative_child connect issue_slots[2].iss_uop.iw_issued_partial_dgen, slots_2.io.iss_uop.iw_issued_partial_dgen connect issue_slots[2].iss_uop.iw_issued_partial_agen, slots_2.io.iss_uop.iw_issued_partial_agen connect issue_slots[2].iss_uop.iw_issued, slots_2.io.iss_uop.iw_issued connect issue_slots[2].iss_uop.fu_code[0], slots_2.io.iss_uop.fu_code[0] connect issue_slots[2].iss_uop.fu_code[1], slots_2.io.iss_uop.fu_code[1] connect issue_slots[2].iss_uop.fu_code[2], slots_2.io.iss_uop.fu_code[2] connect issue_slots[2].iss_uop.fu_code[3], slots_2.io.iss_uop.fu_code[3] connect issue_slots[2].iss_uop.fu_code[4], slots_2.io.iss_uop.fu_code[4] connect issue_slots[2].iss_uop.fu_code[5], slots_2.io.iss_uop.fu_code[5] connect issue_slots[2].iss_uop.fu_code[6], slots_2.io.iss_uop.fu_code[6] connect issue_slots[2].iss_uop.fu_code[7], slots_2.io.iss_uop.fu_code[7] connect issue_slots[2].iss_uop.fu_code[8], slots_2.io.iss_uop.fu_code[8] connect issue_slots[2].iss_uop.fu_code[9], slots_2.io.iss_uop.fu_code[9] connect issue_slots[2].iss_uop.iq_type[0], slots_2.io.iss_uop.iq_type[0] connect issue_slots[2].iss_uop.iq_type[1], slots_2.io.iss_uop.iq_type[1] connect issue_slots[2].iss_uop.iq_type[2], slots_2.io.iss_uop.iq_type[2] connect issue_slots[2].iss_uop.iq_type[3], slots_2.io.iss_uop.iq_type[3] connect issue_slots[2].iss_uop.debug_pc, slots_2.io.iss_uop.debug_pc connect issue_slots[2].iss_uop.is_rvc, slots_2.io.iss_uop.is_rvc connect issue_slots[2].iss_uop.debug_inst, slots_2.io.iss_uop.debug_inst connect issue_slots[2].iss_uop.inst, slots_2.io.iss_uop.inst connect slots_2.io.grant, issue_slots[2].grant connect issue_slots[2].request, slots_2.io.request connect issue_slots[2].will_be_valid, slots_2.io.will_be_valid connect issue_slots[2].valid, slots_2.io.valid connect slots_3.io.child_rebusys, issue_slots[3].child_rebusys connect slots_3.io.pred_wakeup_port.bits, issue_slots[3].pred_wakeup_port.bits connect slots_3.io.pred_wakeup_port.valid, issue_slots[3].pred_wakeup_port.valid connect slots_3.io.wakeup_ports[0].bits.rebusy, issue_slots[3].wakeup_ports[0].bits.rebusy connect slots_3.io.wakeup_ports[0].bits.speculative_mask, issue_slots[3].wakeup_ports[0].bits.speculative_mask connect slots_3.io.wakeup_ports[0].bits.bypassable, issue_slots[3].wakeup_ports[0].bits.bypassable connect slots_3.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[0].bits.uop.debug_tsrc connect slots_3.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[0].bits.uop.debug_fsrc connect slots_3.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_3.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[0].bits.uop.bp_debug_if connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_3.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[3].wakeup_ports[0].bits.uop.fp_typ connect slots_3.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[3].wakeup_ports[0].bits.uop.fp_rm connect slots_3.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[3].wakeup_ports[0].bits.uop.fp_val connect slots_3.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[3].wakeup_ports[0].bits.uop.fcn_op connect slots_3.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[0].bits.uop.fcn_dw connect slots_3.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[3].wakeup_ports[0].bits.uop.frs3_en connect slots_3.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_3.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_3.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[0].bits.uop.dst_rtype connect slots_3.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[3].wakeup_ports[0].bits.uop.lrs3 connect slots_3.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[3].wakeup_ports[0].bits.uop.lrs2 connect slots_3.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[3].wakeup_ports[0].bits.uop.lrs1 connect slots_3.io.wakeup_ports[0].bits.uop.ldst, issue_slots[3].wakeup_ports[0].bits.uop.ldst connect slots_3.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_3.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[0].bits.uop.csr_cmd connect slots_3.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[0].bits.uop.flush_on_commit connect slots_3.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[3].wakeup_ports[0].bits.uop.is_unique connect slots_3.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[3].wakeup_ports[0].bits.uop.uses_stq connect slots_3.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[0].bits.uop.uses_ldq connect slots_3.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[3].wakeup_ports[0].bits.uop.mem_signed connect slots_3.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[3].wakeup_ports[0].bits.uop.mem_size connect slots_3.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[0].bits.uop.mem_cmd connect slots_3.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[3].wakeup_ports[0].bits.uop.exc_cause connect slots_3.io.wakeup_ports[0].bits.uop.exception, issue_slots[3].wakeup_ports[0].bits.uop.exception connect slots_3.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[0].bits.uop.stale_pdst connect slots_3.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[0].bits.uop.ppred_busy connect slots_3.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs3_busy connect slots_3.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs2_busy connect slots_3.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs1_busy connect slots_3.io.wakeup_ports[0].bits.uop.ppred, issue_slots[3].wakeup_ports[0].bits.uop.ppred connect slots_3.io.wakeup_ports[0].bits.uop.prs3, issue_slots[3].wakeup_ports[0].bits.uop.prs3 connect slots_3.io.wakeup_ports[0].bits.uop.prs2, issue_slots[3].wakeup_ports[0].bits.uop.prs2 connect slots_3.io.wakeup_ports[0].bits.uop.prs1, issue_slots[3].wakeup_ports[0].bits.uop.prs1 connect slots_3.io.wakeup_ports[0].bits.uop.pdst, issue_slots[3].wakeup_ports[0].bits.uop.pdst connect slots_3.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[0].bits.uop.rxq_idx connect slots_3.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[3].wakeup_ports[0].bits.uop.stq_idx connect slots_3.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[0].bits.uop.ldq_idx connect slots_3.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[3].wakeup_ports[0].bits.uop.rob_idx connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_3.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[3].wakeup_ports[0].bits.uop.op2_sel connect slots_3.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[3].wakeup_ports[0].bits.uop.op1_sel connect slots_3.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[3].wakeup_ports[0].bits.uop.imm_packed connect slots_3.io.wakeup_ports[0].bits.uop.pimm, issue_slots[3].wakeup_ports[0].bits.uop.pimm connect slots_3.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[3].wakeup_ports[0].bits.uop.imm_sel connect slots_3.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[3].wakeup_ports[0].bits.uop.imm_rename connect slots_3.io.wakeup_ports[0].bits.uop.taken, issue_slots[3].wakeup_ports[0].bits.uop.taken connect slots_3.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[3].wakeup_ports[0].bits.uop.pc_lob connect slots_3.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[3].wakeup_ports[0].bits.uop.edge_inst connect slots_3.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[0].bits.uop.ftq_idx connect slots_3.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[3].wakeup_ports[0].bits.uop.is_mov connect slots_3.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[3].wakeup_ports[0].bits.uop.is_rocc connect slots_3.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_3.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[3].wakeup_ports[0].bits.uop.is_eret connect slots_3.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[3].wakeup_ports[0].bits.uop.is_amo connect slots_3.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[3].wakeup_ports[0].bits.uop.is_sfence connect slots_3.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[3].wakeup_ports[0].bits.uop.is_fencei connect slots_3.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[3].wakeup_ports[0].bits.uop.is_fence connect slots_3.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[3].wakeup_ports[0].bits.uop.is_sfb connect slots_3.io.wakeup_ports[0].bits.uop.br_type, issue_slots[3].wakeup_ports[0].bits.uop.br_type connect slots_3.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[3].wakeup_ports[0].bits.uop.br_tag connect slots_3.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[3].wakeup_ports[0].bits.uop.br_mask connect slots_3.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[0].bits.uop.dis_col_sel connect slots_3.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_3.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_3.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_3.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_3.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[0] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[1] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[2] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[3] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[4] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[5] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[6] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[7] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[8] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[9] connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[0] connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[1] connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[2] connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[3] connect slots_3.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[3].wakeup_ports[0].bits.uop.debug_pc connect slots_3.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[3].wakeup_ports[0].bits.uop.is_rvc connect slots_3.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[3].wakeup_ports[0].bits.uop.debug_inst connect slots_3.io.wakeup_ports[0].bits.uop.inst, issue_slots[3].wakeup_ports[0].bits.uop.inst connect slots_3.io.wakeup_ports[0].valid, issue_slots[3].wakeup_ports[0].valid connect slots_3.io.wakeup_ports[1].bits.rebusy, issue_slots[3].wakeup_ports[1].bits.rebusy connect slots_3.io.wakeup_ports[1].bits.speculative_mask, issue_slots[3].wakeup_ports[1].bits.speculative_mask connect slots_3.io.wakeup_ports[1].bits.bypassable, issue_slots[3].wakeup_ports[1].bits.bypassable connect slots_3.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[1].bits.uop.debug_tsrc connect slots_3.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[1].bits.uop.debug_fsrc connect slots_3.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_3.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[1].bits.uop.bp_debug_if connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_3.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[3].wakeup_ports[1].bits.uop.fp_typ connect slots_3.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[3].wakeup_ports[1].bits.uop.fp_rm connect slots_3.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[3].wakeup_ports[1].bits.uop.fp_val connect slots_3.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[3].wakeup_ports[1].bits.uop.fcn_op connect slots_3.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[1].bits.uop.fcn_dw connect slots_3.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[3].wakeup_ports[1].bits.uop.frs3_en connect slots_3.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_3.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_3.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[1].bits.uop.dst_rtype connect slots_3.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[3].wakeup_ports[1].bits.uop.lrs3 connect slots_3.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[3].wakeup_ports[1].bits.uop.lrs2 connect slots_3.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[3].wakeup_ports[1].bits.uop.lrs1 connect slots_3.io.wakeup_ports[1].bits.uop.ldst, issue_slots[3].wakeup_ports[1].bits.uop.ldst connect slots_3.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_3.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[1].bits.uop.csr_cmd connect slots_3.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[1].bits.uop.flush_on_commit connect slots_3.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[3].wakeup_ports[1].bits.uop.is_unique connect slots_3.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[3].wakeup_ports[1].bits.uop.uses_stq connect slots_3.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[1].bits.uop.uses_ldq connect slots_3.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[3].wakeup_ports[1].bits.uop.mem_signed connect slots_3.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[3].wakeup_ports[1].bits.uop.mem_size connect slots_3.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[1].bits.uop.mem_cmd connect slots_3.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[3].wakeup_ports[1].bits.uop.exc_cause connect slots_3.io.wakeup_ports[1].bits.uop.exception, issue_slots[3].wakeup_ports[1].bits.uop.exception connect slots_3.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[1].bits.uop.stale_pdst connect slots_3.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[1].bits.uop.ppred_busy connect slots_3.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs3_busy connect slots_3.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs2_busy connect slots_3.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs1_busy connect slots_3.io.wakeup_ports[1].bits.uop.ppred, issue_slots[3].wakeup_ports[1].bits.uop.ppred connect slots_3.io.wakeup_ports[1].bits.uop.prs3, issue_slots[3].wakeup_ports[1].bits.uop.prs3 connect slots_3.io.wakeup_ports[1].bits.uop.prs2, issue_slots[3].wakeup_ports[1].bits.uop.prs2 connect slots_3.io.wakeup_ports[1].bits.uop.prs1, issue_slots[3].wakeup_ports[1].bits.uop.prs1 connect slots_3.io.wakeup_ports[1].bits.uop.pdst, issue_slots[3].wakeup_ports[1].bits.uop.pdst connect slots_3.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[1].bits.uop.rxq_idx connect slots_3.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[3].wakeup_ports[1].bits.uop.stq_idx connect slots_3.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[1].bits.uop.ldq_idx connect slots_3.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[3].wakeup_ports[1].bits.uop.rob_idx connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_3.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[3].wakeup_ports[1].bits.uop.op2_sel connect slots_3.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[3].wakeup_ports[1].bits.uop.op1_sel connect slots_3.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[3].wakeup_ports[1].bits.uop.imm_packed connect slots_3.io.wakeup_ports[1].bits.uop.pimm, issue_slots[3].wakeup_ports[1].bits.uop.pimm connect slots_3.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[3].wakeup_ports[1].bits.uop.imm_sel connect slots_3.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[3].wakeup_ports[1].bits.uop.imm_rename connect slots_3.io.wakeup_ports[1].bits.uop.taken, issue_slots[3].wakeup_ports[1].bits.uop.taken connect slots_3.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[3].wakeup_ports[1].bits.uop.pc_lob connect slots_3.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[3].wakeup_ports[1].bits.uop.edge_inst connect slots_3.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[1].bits.uop.ftq_idx connect slots_3.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[3].wakeup_ports[1].bits.uop.is_mov connect slots_3.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[3].wakeup_ports[1].bits.uop.is_rocc connect slots_3.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_3.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[3].wakeup_ports[1].bits.uop.is_eret connect slots_3.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[3].wakeup_ports[1].bits.uop.is_amo connect slots_3.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[3].wakeup_ports[1].bits.uop.is_sfence connect slots_3.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[3].wakeup_ports[1].bits.uop.is_fencei connect slots_3.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[3].wakeup_ports[1].bits.uop.is_fence connect slots_3.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[3].wakeup_ports[1].bits.uop.is_sfb connect slots_3.io.wakeup_ports[1].bits.uop.br_type, issue_slots[3].wakeup_ports[1].bits.uop.br_type connect slots_3.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[3].wakeup_ports[1].bits.uop.br_tag connect slots_3.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[3].wakeup_ports[1].bits.uop.br_mask connect slots_3.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[1].bits.uop.dis_col_sel connect slots_3.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_3.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_3.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_3.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_3.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[0] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[1] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[2] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[3] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[4] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[5] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[6] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[7] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[8] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[9] connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[0] connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[1] connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[2] connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[3] connect slots_3.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[3].wakeup_ports[1].bits.uop.debug_pc connect slots_3.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[3].wakeup_ports[1].bits.uop.is_rvc connect slots_3.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[3].wakeup_ports[1].bits.uop.debug_inst connect slots_3.io.wakeup_ports[1].bits.uop.inst, issue_slots[3].wakeup_ports[1].bits.uop.inst connect slots_3.io.wakeup_ports[1].valid, issue_slots[3].wakeup_ports[1].valid connect slots_3.io.wakeup_ports[2].bits.rebusy, issue_slots[3].wakeup_ports[2].bits.rebusy connect slots_3.io.wakeup_ports[2].bits.speculative_mask, issue_slots[3].wakeup_ports[2].bits.speculative_mask connect slots_3.io.wakeup_ports[2].bits.bypassable, issue_slots[3].wakeup_ports[2].bits.bypassable connect slots_3.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[2].bits.uop.debug_tsrc connect slots_3.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[2].bits.uop.debug_fsrc connect slots_3.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_3.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[2].bits.uop.bp_debug_if connect slots_3.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_3.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_3.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_3.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[3].wakeup_ports[2].bits.uop.fp_typ connect slots_3.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[3].wakeup_ports[2].bits.uop.fp_rm connect slots_3.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[3].wakeup_ports[2].bits.uop.fp_val connect slots_3.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[3].wakeup_ports[2].bits.uop.fcn_op connect slots_3.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[2].bits.uop.fcn_dw connect slots_3.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[3].wakeup_ports[2].bits.uop.frs3_en connect slots_3.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_3.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_3.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[2].bits.uop.dst_rtype connect slots_3.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[3].wakeup_ports[2].bits.uop.lrs3 connect slots_3.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[3].wakeup_ports[2].bits.uop.lrs2 connect slots_3.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[3].wakeup_ports[2].bits.uop.lrs1 connect slots_3.io.wakeup_ports[2].bits.uop.ldst, issue_slots[3].wakeup_ports[2].bits.uop.ldst connect slots_3.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_3.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[2].bits.uop.csr_cmd connect slots_3.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[2].bits.uop.flush_on_commit connect slots_3.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[3].wakeup_ports[2].bits.uop.is_unique connect slots_3.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[3].wakeup_ports[2].bits.uop.uses_stq connect slots_3.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[2].bits.uop.uses_ldq connect slots_3.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[3].wakeup_ports[2].bits.uop.mem_signed connect slots_3.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[3].wakeup_ports[2].bits.uop.mem_size connect slots_3.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[2].bits.uop.mem_cmd connect slots_3.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[3].wakeup_ports[2].bits.uop.exc_cause connect slots_3.io.wakeup_ports[2].bits.uop.exception, issue_slots[3].wakeup_ports[2].bits.uop.exception connect slots_3.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[2].bits.uop.stale_pdst connect slots_3.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[2].bits.uop.ppred_busy connect slots_3.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[2].bits.uop.prs3_busy connect slots_3.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[2].bits.uop.prs2_busy connect slots_3.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[2].bits.uop.prs1_busy connect slots_3.io.wakeup_ports[2].bits.uop.ppred, issue_slots[3].wakeup_ports[2].bits.uop.ppred connect slots_3.io.wakeup_ports[2].bits.uop.prs3, issue_slots[3].wakeup_ports[2].bits.uop.prs3 connect slots_3.io.wakeup_ports[2].bits.uop.prs2, issue_slots[3].wakeup_ports[2].bits.uop.prs2 connect slots_3.io.wakeup_ports[2].bits.uop.prs1, issue_slots[3].wakeup_ports[2].bits.uop.prs1 connect slots_3.io.wakeup_ports[2].bits.uop.pdst, issue_slots[3].wakeup_ports[2].bits.uop.pdst connect slots_3.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[2].bits.uop.rxq_idx connect slots_3.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[3].wakeup_ports[2].bits.uop.stq_idx connect slots_3.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[2].bits.uop.ldq_idx connect slots_3.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[3].wakeup_ports[2].bits.uop.rob_idx connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_3.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[3].wakeup_ports[2].bits.uop.op2_sel connect slots_3.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[3].wakeup_ports[2].bits.uop.op1_sel connect slots_3.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[3].wakeup_ports[2].bits.uop.imm_packed connect slots_3.io.wakeup_ports[2].bits.uop.pimm, issue_slots[3].wakeup_ports[2].bits.uop.pimm connect slots_3.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[3].wakeup_ports[2].bits.uop.imm_sel connect slots_3.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[3].wakeup_ports[2].bits.uop.imm_rename connect slots_3.io.wakeup_ports[2].bits.uop.taken, issue_slots[3].wakeup_ports[2].bits.uop.taken connect slots_3.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[3].wakeup_ports[2].bits.uop.pc_lob connect slots_3.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[3].wakeup_ports[2].bits.uop.edge_inst connect slots_3.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[2].bits.uop.ftq_idx connect slots_3.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[3].wakeup_ports[2].bits.uop.is_mov connect slots_3.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[3].wakeup_ports[2].bits.uop.is_rocc connect slots_3.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_3.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[3].wakeup_ports[2].bits.uop.is_eret connect slots_3.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[3].wakeup_ports[2].bits.uop.is_amo connect slots_3.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[3].wakeup_ports[2].bits.uop.is_sfence connect slots_3.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[3].wakeup_ports[2].bits.uop.is_fencei connect slots_3.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[3].wakeup_ports[2].bits.uop.is_fence connect slots_3.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[3].wakeup_ports[2].bits.uop.is_sfb connect slots_3.io.wakeup_ports[2].bits.uop.br_type, issue_slots[3].wakeup_ports[2].bits.uop.br_type connect slots_3.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[3].wakeup_ports[2].bits.uop.br_tag connect slots_3.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[3].wakeup_ports[2].bits.uop.br_mask connect slots_3.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[2].bits.uop.dis_col_sel connect slots_3.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_3.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_3.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_3.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_3.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_3.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_3.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_3.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[3].wakeup_ports[2].bits.uop.iw_issued connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[0] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[1] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[2] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[3] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[4] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[5] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[6] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[7] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[8] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[9] connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[0] connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[1] connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[2] connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[3] connect slots_3.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[3].wakeup_ports[2].bits.uop.debug_pc connect slots_3.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[3].wakeup_ports[2].bits.uop.is_rvc connect slots_3.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[3].wakeup_ports[2].bits.uop.debug_inst connect slots_3.io.wakeup_ports[2].bits.uop.inst, issue_slots[3].wakeup_ports[2].bits.uop.inst connect slots_3.io.wakeup_ports[2].valid, issue_slots[3].wakeup_ports[2].valid connect slots_3.io.wakeup_ports[3].bits.rebusy, issue_slots[3].wakeup_ports[3].bits.rebusy connect slots_3.io.wakeup_ports[3].bits.speculative_mask, issue_slots[3].wakeup_ports[3].bits.speculative_mask connect slots_3.io.wakeup_ports[3].bits.bypassable, issue_slots[3].wakeup_ports[3].bits.bypassable connect slots_3.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[3].bits.uop.debug_tsrc connect slots_3.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[3].bits.uop.debug_fsrc connect slots_3.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_3.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[3].bits.uop.bp_debug_if connect slots_3.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_3.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_3.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_3.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[3].wakeup_ports[3].bits.uop.fp_typ connect slots_3.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[3].wakeup_ports[3].bits.uop.fp_rm connect slots_3.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[3].wakeup_ports[3].bits.uop.fp_val connect slots_3.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[3].wakeup_ports[3].bits.uop.fcn_op connect slots_3.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[3].bits.uop.fcn_dw connect slots_3.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[3].wakeup_ports[3].bits.uop.frs3_en connect slots_3.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_3.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_3.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[3].bits.uop.dst_rtype connect slots_3.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[3].wakeup_ports[3].bits.uop.lrs3 connect slots_3.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[3].wakeup_ports[3].bits.uop.lrs2 connect slots_3.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[3].wakeup_ports[3].bits.uop.lrs1 connect slots_3.io.wakeup_ports[3].bits.uop.ldst, issue_slots[3].wakeup_ports[3].bits.uop.ldst connect slots_3.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_3.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[3].bits.uop.csr_cmd connect slots_3.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[3].bits.uop.flush_on_commit connect slots_3.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[3].wakeup_ports[3].bits.uop.is_unique connect slots_3.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[3].wakeup_ports[3].bits.uop.uses_stq connect slots_3.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[3].bits.uop.uses_ldq connect slots_3.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[3].wakeup_ports[3].bits.uop.mem_signed connect slots_3.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[3].wakeup_ports[3].bits.uop.mem_size connect slots_3.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[3].bits.uop.mem_cmd connect slots_3.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[3].wakeup_ports[3].bits.uop.exc_cause connect slots_3.io.wakeup_ports[3].bits.uop.exception, issue_slots[3].wakeup_ports[3].bits.uop.exception connect slots_3.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[3].bits.uop.stale_pdst connect slots_3.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[3].bits.uop.ppred_busy connect slots_3.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[3].bits.uop.prs3_busy connect slots_3.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[3].bits.uop.prs2_busy connect slots_3.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[3].bits.uop.prs1_busy connect slots_3.io.wakeup_ports[3].bits.uop.ppred, issue_slots[3].wakeup_ports[3].bits.uop.ppred connect slots_3.io.wakeup_ports[3].bits.uop.prs3, issue_slots[3].wakeup_ports[3].bits.uop.prs3 connect slots_3.io.wakeup_ports[3].bits.uop.prs2, issue_slots[3].wakeup_ports[3].bits.uop.prs2 connect slots_3.io.wakeup_ports[3].bits.uop.prs1, issue_slots[3].wakeup_ports[3].bits.uop.prs1 connect slots_3.io.wakeup_ports[3].bits.uop.pdst, issue_slots[3].wakeup_ports[3].bits.uop.pdst connect slots_3.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[3].bits.uop.rxq_idx connect slots_3.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[3].wakeup_ports[3].bits.uop.stq_idx connect slots_3.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[3].bits.uop.ldq_idx connect slots_3.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[3].wakeup_ports[3].bits.uop.rob_idx connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_3.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[3].wakeup_ports[3].bits.uop.op2_sel connect slots_3.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[3].wakeup_ports[3].bits.uop.op1_sel connect slots_3.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[3].wakeup_ports[3].bits.uop.imm_packed connect slots_3.io.wakeup_ports[3].bits.uop.pimm, issue_slots[3].wakeup_ports[3].bits.uop.pimm connect slots_3.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[3].wakeup_ports[3].bits.uop.imm_sel connect slots_3.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[3].wakeup_ports[3].bits.uop.imm_rename connect slots_3.io.wakeup_ports[3].bits.uop.taken, issue_slots[3].wakeup_ports[3].bits.uop.taken connect slots_3.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[3].wakeup_ports[3].bits.uop.pc_lob connect slots_3.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[3].wakeup_ports[3].bits.uop.edge_inst connect slots_3.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[3].bits.uop.ftq_idx connect slots_3.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[3].wakeup_ports[3].bits.uop.is_mov connect slots_3.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[3].wakeup_ports[3].bits.uop.is_rocc connect slots_3.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_3.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[3].wakeup_ports[3].bits.uop.is_eret connect slots_3.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[3].wakeup_ports[3].bits.uop.is_amo connect slots_3.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[3].wakeup_ports[3].bits.uop.is_sfence connect slots_3.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[3].wakeup_ports[3].bits.uop.is_fencei connect slots_3.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[3].wakeup_ports[3].bits.uop.is_fence connect slots_3.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[3].wakeup_ports[3].bits.uop.is_sfb connect slots_3.io.wakeup_ports[3].bits.uop.br_type, issue_slots[3].wakeup_ports[3].bits.uop.br_type connect slots_3.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[3].wakeup_ports[3].bits.uop.br_tag connect slots_3.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[3].wakeup_ports[3].bits.uop.br_mask connect slots_3.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[3].bits.uop.dis_col_sel connect slots_3.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_3.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_3.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_3.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_3.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_3.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_3.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_3.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[3].wakeup_ports[3].bits.uop.iw_issued connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[0] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[1] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[2] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[3] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[4] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[5] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[6] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[7] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[8] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[9] connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[0] connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[1] connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[2] connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[3] connect slots_3.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[3].wakeup_ports[3].bits.uop.debug_pc connect slots_3.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[3].wakeup_ports[3].bits.uop.is_rvc connect slots_3.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[3].wakeup_ports[3].bits.uop.debug_inst connect slots_3.io.wakeup_ports[3].bits.uop.inst, issue_slots[3].wakeup_ports[3].bits.uop.inst connect slots_3.io.wakeup_ports[3].valid, issue_slots[3].wakeup_ports[3].valid connect slots_3.io.wakeup_ports[4].bits.rebusy, issue_slots[3].wakeup_ports[4].bits.rebusy connect slots_3.io.wakeup_ports[4].bits.speculative_mask, issue_slots[3].wakeup_ports[4].bits.speculative_mask connect slots_3.io.wakeup_ports[4].bits.bypassable, issue_slots[3].wakeup_ports[4].bits.bypassable connect slots_3.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[4].bits.uop.debug_tsrc connect slots_3.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[4].bits.uop.debug_fsrc connect slots_3.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_3.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[4].bits.uop.bp_debug_if connect slots_3.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_3.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_3.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_3.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[3].wakeup_ports[4].bits.uop.fp_typ connect slots_3.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[3].wakeup_ports[4].bits.uop.fp_rm connect slots_3.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[3].wakeup_ports[4].bits.uop.fp_val connect slots_3.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[3].wakeup_ports[4].bits.uop.fcn_op connect slots_3.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[4].bits.uop.fcn_dw connect slots_3.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[3].wakeup_ports[4].bits.uop.frs3_en connect slots_3.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_3.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_3.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[4].bits.uop.dst_rtype connect slots_3.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[3].wakeup_ports[4].bits.uop.lrs3 connect slots_3.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[3].wakeup_ports[4].bits.uop.lrs2 connect slots_3.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[3].wakeup_ports[4].bits.uop.lrs1 connect slots_3.io.wakeup_ports[4].bits.uop.ldst, issue_slots[3].wakeup_ports[4].bits.uop.ldst connect slots_3.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_3.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[4].bits.uop.csr_cmd connect slots_3.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[4].bits.uop.flush_on_commit connect slots_3.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[3].wakeup_ports[4].bits.uop.is_unique connect slots_3.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[3].wakeup_ports[4].bits.uop.uses_stq connect slots_3.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[4].bits.uop.uses_ldq connect slots_3.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[3].wakeup_ports[4].bits.uop.mem_signed connect slots_3.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[3].wakeup_ports[4].bits.uop.mem_size connect slots_3.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[4].bits.uop.mem_cmd connect slots_3.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[3].wakeup_ports[4].bits.uop.exc_cause connect slots_3.io.wakeup_ports[4].bits.uop.exception, issue_slots[3].wakeup_ports[4].bits.uop.exception connect slots_3.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[4].bits.uop.stale_pdst connect slots_3.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[4].bits.uop.ppred_busy connect slots_3.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[4].bits.uop.prs3_busy connect slots_3.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[4].bits.uop.prs2_busy connect slots_3.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[4].bits.uop.prs1_busy connect slots_3.io.wakeup_ports[4].bits.uop.ppred, issue_slots[3].wakeup_ports[4].bits.uop.ppred connect slots_3.io.wakeup_ports[4].bits.uop.prs3, issue_slots[3].wakeup_ports[4].bits.uop.prs3 connect slots_3.io.wakeup_ports[4].bits.uop.prs2, issue_slots[3].wakeup_ports[4].bits.uop.prs2 connect slots_3.io.wakeup_ports[4].bits.uop.prs1, issue_slots[3].wakeup_ports[4].bits.uop.prs1 connect slots_3.io.wakeup_ports[4].bits.uop.pdst, issue_slots[3].wakeup_ports[4].bits.uop.pdst connect slots_3.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[4].bits.uop.rxq_idx connect slots_3.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[3].wakeup_ports[4].bits.uop.stq_idx connect slots_3.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[4].bits.uop.ldq_idx connect slots_3.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[3].wakeup_ports[4].bits.uop.rob_idx connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_3.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[3].wakeup_ports[4].bits.uop.op2_sel connect slots_3.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[3].wakeup_ports[4].bits.uop.op1_sel connect slots_3.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[3].wakeup_ports[4].bits.uop.imm_packed connect slots_3.io.wakeup_ports[4].bits.uop.pimm, issue_slots[3].wakeup_ports[4].bits.uop.pimm connect slots_3.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[3].wakeup_ports[4].bits.uop.imm_sel connect slots_3.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[3].wakeup_ports[4].bits.uop.imm_rename connect slots_3.io.wakeup_ports[4].bits.uop.taken, issue_slots[3].wakeup_ports[4].bits.uop.taken connect slots_3.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[3].wakeup_ports[4].bits.uop.pc_lob connect slots_3.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[3].wakeup_ports[4].bits.uop.edge_inst connect slots_3.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[4].bits.uop.ftq_idx connect slots_3.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[3].wakeup_ports[4].bits.uop.is_mov connect slots_3.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[3].wakeup_ports[4].bits.uop.is_rocc connect slots_3.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_3.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[3].wakeup_ports[4].bits.uop.is_eret connect slots_3.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[3].wakeup_ports[4].bits.uop.is_amo connect slots_3.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[3].wakeup_ports[4].bits.uop.is_sfence connect slots_3.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[3].wakeup_ports[4].bits.uop.is_fencei connect slots_3.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[3].wakeup_ports[4].bits.uop.is_fence connect slots_3.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[3].wakeup_ports[4].bits.uop.is_sfb connect slots_3.io.wakeup_ports[4].bits.uop.br_type, issue_slots[3].wakeup_ports[4].bits.uop.br_type connect slots_3.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[3].wakeup_ports[4].bits.uop.br_tag connect slots_3.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[3].wakeup_ports[4].bits.uop.br_mask connect slots_3.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[4].bits.uop.dis_col_sel connect slots_3.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_3.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_3.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_3.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_3.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_3.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_3.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_3.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[3].wakeup_ports[4].bits.uop.iw_issued connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[0] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[1] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[2] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[3] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[4] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[5] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[6] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[7] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[8] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[9] connect slots_3.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[4].bits.uop.iq_type[0] connect slots_3.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[4].bits.uop.iq_type[1] connect slots_3.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[4].bits.uop.iq_type[2] connect slots_3.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[4].bits.uop.iq_type[3] connect slots_3.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[3].wakeup_ports[4].bits.uop.debug_pc connect slots_3.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[3].wakeup_ports[4].bits.uop.is_rvc connect slots_3.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[3].wakeup_ports[4].bits.uop.debug_inst connect slots_3.io.wakeup_ports[4].bits.uop.inst, issue_slots[3].wakeup_ports[4].bits.uop.inst connect slots_3.io.wakeup_ports[4].valid, issue_slots[3].wakeup_ports[4].valid connect slots_3.io.squash_grant, issue_slots[3].squash_grant connect slots_3.io.clear, issue_slots[3].clear connect slots_3.io.kill, issue_slots[3].kill connect slots_3.io.brupdate.b2.target_offset, issue_slots[3].brupdate.b2.target_offset connect slots_3.io.brupdate.b2.jalr_target, issue_slots[3].brupdate.b2.jalr_target connect slots_3.io.brupdate.b2.pc_sel, issue_slots[3].brupdate.b2.pc_sel connect slots_3.io.brupdate.b2.cfi_type, issue_slots[3].brupdate.b2.cfi_type connect slots_3.io.brupdate.b2.taken, issue_slots[3].brupdate.b2.taken connect slots_3.io.brupdate.b2.mispredict, issue_slots[3].brupdate.b2.mispredict connect slots_3.io.brupdate.b2.uop.debug_tsrc, issue_slots[3].brupdate.b2.uop.debug_tsrc connect slots_3.io.brupdate.b2.uop.debug_fsrc, issue_slots[3].brupdate.b2.uop.debug_fsrc connect slots_3.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[3].brupdate.b2.uop.bp_xcpt_if connect slots_3.io.brupdate.b2.uop.bp_debug_if, issue_slots[3].brupdate.b2.uop.bp_debug_if connect slots_3.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[3].brupdate.b2.uop.xcpt_ma_if connect slots_3.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[3].brupdate.b2.uop.xcpt_ae_if connect slots_3.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[3].brupdate.b2.uop.xcpt_pf_if connect slots_3.io.brupdate.b2.uop.fp_typ, issue_slots[3].brupdate.b2.uop.fp_typ connect slots_3.io.brupdate.b2.uop.fp_rm, issue_slots[3].brupdate.b2.uop.fp_rm connect slots_3.io.brupdate.b2.uop.fp_val, issue_slots[3].brupdate.b2.uop.fp_val connect slots_3.io.brupdate.b2.uop.fcn_op, issue_slots[3].brupdate.b2.uop.fcn_op connect slots_3.io.brupdate.b2.uop.fcn_dw, issue_slots[3].brupdate.b2.uop.fcn_dw connect slots_3.io.brupdate.b2.uop.frs3_en, issue_slots[3].brupdate.b2.uop.frs3_en connect slots_3.io.brupdate.b2.uop.lrs2_rtype, issue_slots[3].brupdate.b2.uop.lrs2_rtype connect slots_3.io.brupdate.b2.uop.lrs1_rtype, issue_slots[3].brupdate.b2.uop.lrs1_rtype connect slots_3.io.brupdate.b2.uop.dst_rtype, issue_slots[3].brupdate.b2.uop.dst_rtype connect slots_3.io.brupdate.b2.uop.lrs3, issue_slots[3].brupdate.b2.uop.lrs3 connect slots_3.io.brupdate.b2.uop.lrs2, issue_slots[3].brupdate.b2.uop.lrs2 connect slots_3.io.brupdate.b2.uop.lrs1, issue_slots[3].brupdate.b2.uop.lrs1 connect slots_3.io.brupdate.b2.uop.ldst, issue_slots[3].brupdate.b2.uop.ldst connect slots_3.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[3].brupdate.b2.uop.ldst_is_rs1 connect slots_3.io.brupdate.b2.uop.csr_cmd, issue_slots[3].brupdate.b2.uop.csr_cmd connect slots_3.io.brupdate.b2.uop.flush_on_commit, issue_slots[3].brupdate.b2.uop.flush_on_commit connect slots_3.io.brupdate.b2.uop.is_unique, issue_slots[3].brupdate.b2.uop.is_unique connect slots_3.io.brupdate.b2.uop.uses_stq, issue_slots[3].brupdate.b2.uop.uses_stq connect slots_3.io.brupdate.b2.uop.uses_ldq, issue_slots[3].brupdate.b2.uop.uses_ldq connect slots_3.io.brupdate.b2.uop.mem_signed, issue_slots[3].brupdate.b2.uop.mem_signed connect slots_3.io.brupdate.b2.uop.mem_size, issue_slots[3].brupdate.b2.uop.mem_size connect slots_3.io.brupdate.b2.uop.mem_cmd, issue_slots[3].brupdate.b2.uop.mem_cmd connect slots_3.io.brupdate.b2.uop.exc_cause, issue_slots[3].brupdate.b2.uop.exc_cause connect slots_3.io.brupdate.b2.uop.exception, issue_slots[3].brupdate.b2.uop.exception connect slots_3.io.brupdate.b2.uop.stale_pdst, issue_slots[3].brupdate.b2.uop.stale_pdst connect slots_3.io.brupdate.b2.uop.ppred_busy, issue_slots[3].brupdate.b2.uop.ppred_busy connect slots_3.io.brupdate.b2.uop.prs3_busy, issue_slots[3].brupdate.b2.uop.prs3_busy connect slots_3.io.brupdate.b2.uop.prs2_busy, issue_slots[3].brupdate.b2.uop.prs2_busy connect slots_3.io.brupdate.b2.uop.prs1_busy, issue_slots[3].brupdate.b2.uop.prs1_busy connect slots_3.io.brupdate.b2.uop.ppred, issue_slots[3].brupdate.b2.uop.ppred connect slots_3.io.brupdate.b2.uop.prs3, issue_slots[3].brupdate.b2.uop.prs3 connect slots_3.io.brupdate.b2.uop.prs2, issue_slots[3].brupdate.b2.uop.prs2 connect slots_3.io.brupdate.b2.uop.prs1, issue_slots[3].brupdate.b2.uop.prs1 connect slots_3.io.brupdate.b2.uop.pdst, issue_slots[3].brupdate.b2.uop.pdst connect slots_3.io.brupdate.b2.uop.rxq_idx, issue_slots[3].brupdate.b2.uop.rxq_idx connect slots_3.io.brupdate.b2.uop.stq_idx, issue_slots[3].brupdate.b2.uop.stq_idx connect slots_3.io.brupdate.b2.uop.ldq_idx, issue_slots[3].brupdate.b2.uop.ldq_idx connect slots_3.io.brupdate.b2.uop.rob_idx, issue_slots[3].brupdate.b2.uop.rob_idx connect slots_3.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[3].brupdate.b2.uop.fp_ctrl.vec connect slots_3.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[3].brupdate.b2.uop.fp_ctrl.wflags connect slots_3.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[3].brupdate.b2.uop.fp_ctrl.sqrt connect slots_3.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[3].brupdate.b2.uop.fp_ctrl.div connect slots_3.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[3].brupdate.b2.uop.fp_ctrl.fma connect slots_3.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[3].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_3.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[3].brupdate.b2.uop.fp_ctrl.toint connect slots_3.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[3].brupdate.b2.uop.fp_ctrl.fromint connect slots_3.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_3.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_3.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[3].brupdate.b2.uop.fp_ctrl.swap23 connect slots_3.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[3].brupdate.b2.uop.fp_ctrl.swap12 connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren3 connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren2 connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren1 connect slots_3.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[3].brupdate.b2.uop.fp_ctrl.wen connect slots_3.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[3].brupdate.b2.uop.fp_ctrl.ldst connect slots_3.io.brupdate.b2.uop.op2_sel, issue_slots[3].brupdate.b2.uop.op2_sel connect slots_3.io.brupdate.b2.uop.op1_sel, issue_slots[3].brupdate.b2.uop.op1_sel connect slots_3.io.brupdate.b2.uop.imm_packed, issue_slots[3].brupdate.b2.uop.imm_packed connect slots_3.io.brupdate.b2.uop.pimm, issue_slots[3].brupdate.b2.uop.pimm connect slots_3.io.brupdate.b2.uop.imm_sel, issue_slots[3].brupdate.b2.uop.imm_sel connect slots_3.io.brupdate.b2.uop.imm_rename, issue_slots[3].brupdate.b2.uop.imm_rename connect slots_3.io.brupdate.b2.uop.taken, issue_slots[3].brupdate.b2.uop.taken connect slots_3.io.brupdate.b2.uop.pc_lob, issue_slots[3].brupdate.b2.uop.pc_lob connect slots_3.io.brupdate.b2.uop.edge_inst, issue_slots[3].brupdate.b2.uop.edge_inst connect slots_3.io.brupdate.b2.uop.ftq_idx, issue_slots[3].brupdate.b2.uop.ftq_idx connect slots_3.io.brupdate.b2.uop.is_mov, issue_slots[3].brupdate.b2.uop.is_mov connect slots_3.io.brupdate.b2.uop.is_rocc, issue_slots[3].brupdate.b2.uop.is_rocc connect slots_3.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[3].brupdate.b2.uop.is_sys_pc2epc connect slots_3.io.brupdate.b2.uop.is_eret, issue_slots[3].brupdate.b2.uop.is_eret connect slots_3.io.brupdate.b2.uop.is_amo, issue_slots[3].brupdate.b2.uop.is_amo connect slots_3.io.brupdate.b2.uop.is_sfence, issue_slots[3].brupdate.b2.uop.is_sfence connect slots_3.io.brupdate.b2.uop.is_fencei, issue_slots[3].brupdate.b2.uop.is_fencei connect slots_3.io.brupdate.b2.uop.is_fence, issue_slots[3].brupdate.b2.uop.is_fence connect slots_3.io.brupdate.b2.uop.is_sfb, issue_slots[3].brupdate.b2.uop.is_sfb connect slots_3.io.brupdate.b2.uop.br_type, issue_slots[3].brupdate.b2.uop.br_type connect slots_3.io.brupdate.b2.uop.br_tag, issue_slots[3].brupdate.b2.uop.br_tag connect slots_3.io.brupdate.b2.uop.br_mask, issue_slots[3].brupdate.b2.uop.br_mask connect slots_3.io.brupdate.b2.uop.dis_col_sel, issue_slots[3].brupdate.b2.uop.dis_col_sel connect slots_3.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p3_bypass_hint connect slots_3.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p2_bypass_hint connect slots_3.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p1_bypass_hint connect slots_3.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[3].brupdate.b2.uop.iw_p2_speculative_child connect slots_3.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[3].brupdate.b2.uop.iw_p1_speculative_child connect slots_3.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[3].brupdate.b2.uop.iw_issued_partial_dgen connect slots_3.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[3].brupdate.b2.uop.iw_issued_partial_agen connect slots_3.io.brupdate.b2.uop.iw_issued, issue_slots[3].brupdate.b2.uop.iw_issued connect slots_3.io.brupdate.b2.uop.fu_code[0], issue_slots[3].brupdate.b2.uop.fu_code[0] connect slots_3.io.brupdate.b2.uop.fu_code[1], issue_slots[3].brupdate.b2.uop.fu_code[1] connect slots_3.io.brupdate.b2.uop.fu_code[2], issue_slots[3].brupdate.b2.uop.fu_code[2] connect slots_3.io.brupdate.b2.uop.fu_code[3], issue_slots[3].brupdate.b2.uop.fu_code[3] connect slots_3.io.brupdate.b2.uop.fu_code[4], issue_slots[3].brupdate.b2.uop.fu_code[4] connect slots_3.io.brupdate.b2.uop.fu_code[5], issue_slots[3].brupdate.b2.uop.fu_code[5] connect slots_3.io.brupdate.b2.uop.fu_code[6], issue_slots[3].brupdate.b2.uop.fu_code[6] connect slots_3.io.brupdate.b2.uop.fu_code[7], issue_slots[3].brupdate.b2.uop.fu_code[7] connect slots_3.io.brupdate.b2.uop.fu_code[8], issue_slots[3].brupdate.b2.uop.fu_code[8] connect slots_3.io.brupdate.b2.uop.fu_code[9], issue_slots[3].brupdate.b2.uop.fu_code[9] connect slots_3.io.brupdate.b2.uop.iq_type[0], issue_slots[3].brupdate.b2.uop.iq_type[0] connect slots_3.io.brupdate.b2.uop.iq_type[1], issue_slots[3].brupdate.b2.uop.iq_type[1] connect slots_3.io.brupdate.b2.uop.iq_type[2], issue_slots[3].brupdate.b2.uop.iq_type[2] connect slots_3.io.brupdate.b2.uop.iq_type[3], issue_slots[3].brupdate.b2.uop.iq_type[3] connect slots_3.io.brupdate.b2.uop.debug_pc, issue_slots[3].brupdate.b2.uop.debug_pc connect slots_3.io.brupdate.b2.uop.is_rvc, issue_slots[3].brupdate.b2.uop.is_rvc connect slots_3.io.brupdate.b2.uop.debug_inst, issue_slots[3].brupdate.b2.uop.debug_inst connect slots_3.io.brupdate.b2.uop.inst, issue_slots[3].brupdate.b2.uop.inst connect slots_3.io.brupdate.b1.mispredict_mask, issue_slots[3].brupdate.b1.mispredict_mask connect slots_3.io.brupdate.b1.resolve_mask, issue_slots[3].brupdate.b1.resolve_mask connect issue_slots[3].out_uop.debug_tsrc, slots_3.io.out_uop.debug_tsrc connect issue_slots[3].out_uop.debug_fsrc, slots_3.io.out_uop.debug_fsrc connect issue_slots[3].out_uop.bp_xcpt_if, slots_3.io.out_uop.bp_xcpt_if connect issue_slots[3].out_uop.bp_debug_if, slots_3.io.out_uop.bp_debug_if connect issue_slots[3].out_uop.xcpt_ma_if, slots_3.io.out_uop.xcpt_ma_if connect issue_slots[3].out_uop.xcpt_ae_if, slots_3.io.out_uop.xcpt_ae_if connect issue_slots[3].out_uop.xcpt_pf_if, slots_3.io.out_uop.xcpt_pf_if connect issue_slots[3].out_uop.fp_typ, slots_3.io.out_uop.fp_typ connect issue_slots[3].out_uop.fp_rm, slots_3.io.out_uop.fp_rm connect issue_slots[3].out_uop.fp_val, slots_3.io.out_uop.fp_val connect issue_slots[3].out_uop.fcn_op, slots_3.io.out_uop.fcn_op connect issue_slots[3].out_uop.fcn_dw, slots_3.io.out_uop.fcn_dw connect issue_slots[3].out_uop.frs3_en, slots_3.io.out_uop.frs3_en connect issue_slots[3].out_uop.lrs2_rtype, slots_3.io.out_uop.lrs2_rtype connect issue_slots[3].out_uop.lrs1_rtype, slots_3.io.out_uop.lrs1_rtype connect issue_slots[3].out_uop.dst_rtype, slots_3.io.out_uop.dst_rtype connect issue_slots[3].out_uop.lrs3, slots_3.io.out_uop.lrs3 connect issue_slots[3].out_uop.lrs2, slots_3.io.out_uop.lrs2 connect issue_slots[3].out_uop.lrs1, slots_3.io.out_uop.lrs1 connect issue_slots[3].out_uop.ldst, slots_3.io.out_uop.ldst connect issue_slots[3].out_uop.ldst_is_rs1, slots_3.io.out_uop.ldst_is_rs1 connect issue_slots[3].out_uop.csr_cmd, slots_3.io.out_uop.csr_cmd connect issue_slots[3].out_uop.flush_on_commit, slots_3.io.out_uop.flush_on_commit connect issue_slots[3].out_uop.is_unique, slots_3.io.out_uop.is_unique connect issue_slots[3].out_uop.uses_stq, slots_3.io.out_uop.uses_stq connect issue_slots[3].out_uop.uses_ldq, slots_3.io.out_uop.uses_ldq connect issue_slots[3].out_uop.mem_signed, slots_3.io.out_uop.mem_signed connect issue_slots[3].out_uop.mem_size, slots_3.io.out_uop.mem_size connect issue_slots[3].out_uop.mem_cmd, slots_3.io.out_uop.mem_cmd connect issue_slots[3].out_uop.exc_cause, slots_3.io.out_uop.exc_cause connect issue_slots[3].out_uop.exception, slots_3.io.out_uop.exception connect issue_slots[3].out_uop.stale_pdst, slots_3.io.out_uop.stale_pdst connect issue_slots[3].out_uop.ppred_busy, slots_3.io.out_uop.ppred_busy connect issue_slots[3].out_uop.prs3_busy, slots_3.io.out_uop.prs3_busy connect issue_slots[3].out_uop.prs2_busy, slots_3.io.out_uop.prs2_busy connect issue_slots[3].out_uop.prs1_busy, slots_3.io.out_uop.prs1_busy connect issue_slots[3].out_uop.ppred, slots_3.io.out_uop.ppred connect issue_slots[3].out_uop.prs3, slots_3.io.out_uop.prs3 connect issue_slots[3].out_uop.prs2, slots_3.io.out_uop.prs2 connect issue_slots[3].out_uop.prs1, slots_3.io.out_uop.prs1 connect issue_slots[3].out_uop.pdst, slots_3.io.out_uop.pdst connect issue_slots[3].out_uop.rxq_idx, slots_3.io.out_uop.rxq_idx connect issue_slots[3].out_uop.stq_idx, slots_3.io.out_uop.stq_idx connect issue_slots[3].out_uop.ldq_idx, slots_3.io.out_uop.ldq_idx connect issue_slots[3].out_uop.rob_idx, slots_3.io.out_uop.rob_idx connect issue_slots[3].out_uop.fp_ctrl.vec, slots_3.io.out_uop.fp_ctrl.vec connect issue_slots[3].out_uop.fp_ctrl.wflags, slots_3.io.out_uop.fp_ctrl.wflags connect issue_slots[3].out_uop.fp_ctrl.sqrt, slots_3.io.out_uop.fp_ctrl.sqrt connect issue_slots[3].out_uop.fp_ctrl.div, slots_3.io.out_uop.fp_ctrl.div connect issue_slots[3].out_uop.fp_ctrl.fma, slots_3.io.out_uop.fp_ctrl.fma connect issue_slots[3].out_uop.fp_ctrl.fastpipe, slots_3.io.out_uop.fp_ctrl.fastpipe connect issue_slots[3].out_uop.fp_ctrl.toint, slots_3.io.out_uop.fp_ctrl.toint connect issue_slots[3].out_uop.fp_ctrl.fromint, slots_3.io.out_uop.fp_ctrl.fromint connect issue_slots[3].out_uop.fp_ctrl.typeTagOut, slots_3.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[3].out_uop.fp_ctrl.typeTagIn, slots_3.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[3].out_uop.fp_ctrl.swap23, slots_3.io.out_uop.fp_ctrl.swap23 connect issue_slots[3].out_uop.fp_ctrl.swap12, slots_3.io.out_uop.fp_ctrl.swap12 connect issue_slots[3].out_uop.fp_ctrl.ren3, slots_3.io.out_uop.fp_ctrl.ren3 connect issue_slots[3].out_uop.fp_ctrl.ren2, slots_3.io.out_uop.fp_ctrl.ren2 connect issue_slots[3].out_uop.fp_ctrl.ren1, slots_3.io.out_uop.fp_ctrl.ren1 connect issue_slots[3].out_uop.fp_ctrl.wen, slots_3.io.out_uop.fp_ctrl.wen connect issue_slots[3].out_uop.fp_ctrl.ldst, slots_3.io.out_uop.fp_ctrl.ldst connect issue_slots[3].out_uop.op2_sel, slots_3.io.out_uop.op2_sel connect issue_slots[3].out_uop.op1_sel, slots_3.io.out_uop.op1_sel connect issue_slots[3].out_uop.imm_packed, slots_3.io.out_uop.imm_packed connect issue_slots[3].out_uop.pimm, slots_3.io.out_uop.pimm connect issue_slots[3].out_uop.imm_sel, slots_3.io.out_uop.imm_sel connect issue_slots[3].out_uop.imm_rename, slots_3.io.out_uop.imm_rename connect issue_slots[3].out_uop.taken, slots_3.io.out_uop.taken connect issue_slots[3].out_uop.pc_lob, slots_3.io.out_uop.pc_lob connect issue_slots[3].out_uop.edge_inst, slots_3.io.out_uop.edge_inst connect issue_slots[3].out_uop.ftq_idx, slots_3.io.out_uop.ftq_idx connect issue_slots[3].out_uop.is_mov, slots_3.io.out_uop.is_mov connect issue_slots[3].out_uop.is_rocc, slots_3.io.out_uop.is_rocc connect issue_slots[3].out_uop.is_sys_pc2epc, slots_3.io.out_uop.is_sys_pc2epc connect issue_slots[3].out_uop.is_eret, slots_3.io.out_uop.is_eret connect issue_slots[3].out_uop.is_amo, slots_3.io.out_uop.is_amo connect issue_slots[3].out_uop.is_sfence, slots_3.io.out_uop.is_sfence connect issue_slots[3].out_uop.is_fencei, slots_3.io.out_uop.is_fencei connect issue_slots[3].out_uop.is_fence, slots_3.io.out_uop.is_fence connect issue_slots[3].out_uop.is_sfb, slots_3.io.out_uop.is_sfb connect issue_slots[3].out_uop.br_type, slots_3.io.out_uop.br_type connect issue_slots[3].out_uop.br_tag, slots_3.io.out_uop.br_tag connect issue_slots[3].out_uop.br_mask, slots_3.io.out_uop.br_mask connect issue_slots[3].out_uop.dis_col_sel, slots_3.io.out_uop.dis_col_sel connect issue_slots[3].out_uop.iw_p3_bypass_hint, slots_3.io.out_uop.iw_p3_bypass_hint connect issue_slots[3].out_uop.iw_p2_bypass_hint, slots_3.io.out_uop.iw_p2_bypass_hint connect issue_slots[3].out_uop.iw_p1_bypass_hint, slots_3.io.out_uop.iw_p1_bypass_hint connect issue_slots[3].out_uop.iw_p2_speculative_child, slots_3.io.out_uop.iw_p2_speculative_child connect issue_slots[3].out_uop.iw_p1_speculative_child, slots_3.io.out_uop.iw_p1_speculative_child connect issue_slots[3].out_uop.iw_issued_partial_dgen, slots_3.io.out_uop.iw_issued_partial_dgen connect issue_slots[3].out_uop.iw_issued_partial_agen, slots_3.io.out_uop.iw_issued_partial_agen connect issue_slots[3].out_uop.iw_issued, slots_3.io.out_uop.iw_issued connect issue_slots[3].out_uop.fu_code[0], slots_3.io.out_uop.fu_code[0] connect issue_slots[3].out_uop.fu_code[1], slots_3.io.out_uop.fu_code[1] connect issue_slots[3].out_uop.fu_code[2], slots_3.io.out_uop.fu_code[2] connect issue_slots[3].out_uop.fu_code[3], slots_3.io.out_uop.fu_code[3] connect issue_slots[3].out_uop.fu_code[4], slots_3.io.out_uop.fu_code[4] connect issue_slots[3].out_uop.fu_code[5], slots_3.io.out_uop.fu_code[5] connect issue_slots[3].out_uop.fu_code[6], slots_3.io.out_uop.fu_code[6] connect issue_slots[3].out_uop.fu_code[7], slots_3.io.out_uop.fu_code[7] connect issue_slots[3].out_uop.fu_code[8], slots_3.io.out_uop.fu_code[8] connect issue_slots[3].out_uop.fu_code[9], slots_3.io.out_uop.fu_code[9] connect issue_slots[3].out_uop.iq_type[0], slots_3.io.out_uop.iq_type[0] connect issue_slots[3].out_uop.iq_type[1], slots_3.io.out_uop.iq_type[1] connect issue_slots[3].out_uop.iq_type[2], slots_3.io.out_uop.iq_type[2] connect issue_slots[3].out_uop.iq_type[3], slots_3.io.out_uop.iq_type[3] connect issue_slots[3].out_uop.debug_pc, slots_3.io.out_uop.debug_pc connect issue_slots[3].out_uop.is_rvc, slots_3.io.out_uop.is_rvc connect issue_slots[3].out_uop.debug_inst, slots_3.io.out_uop.debug_inst connect issue_slots[3].out_uop.inst, slots_3.io.out_uop.inst connect slots_3.io.in_uop.bits.debug_tsrc, issue_slots[3].in_uop.bits.debug_tsrc connect slots_3.io.in_uop.bits.debug_fsrc, issue_slots[3].in_uop.bits.debug_fsrc connect slots_3.io.in_uop.bits.bp_xcpt_if, issue_slots[3].in_uop.bits.bp_xcpt_if connect slots_3.io.in_uop.bits.bp_debug_if, issue_slots[3].in_uop.bits.bp_debug_if connect slots_3.io.in_uop.bits.xcpt_ma_if, issue_slots[3].in_uop.bits.xcpt_ma_if connect slots_3.io.in_uop.bits.xcpt_ae_if, issue_slots[3].in_uop.bits.xcpt_ae_if connect slots_3.io.in_uop.bits.xcpt_pf_if, issue_slots[3].in_uop.bits.xcpt_pf_if connect slots_3.io.in_uop.bits.fp_typ, issue_slots[3].in_uop.bits.fp_typ connect slots_3.io.in_uop.bits.fp_rm, issue_slots[3].in_uop.bits.fp_rm connect slots_3.io.in_uop.bits.fp_val, issue_slots[3].in_uop.bits.fp_val connect slots_3.io.in_uop.bits.fcn_op, issue_slots[3].in_uop.bits.fcn_op connect slots_3.io.in_uop.bits.fcn_dw, issue_slots[3].in_uop.bits.fcn_dw connect slots_3.io.in_uop.bits.frs3_en, issue_slots[3].in_uop.bits.frs3_en connect slots_3.io.in_uop.bits.lrs2_rtype, issue_slots[3].in_uop.bits.lrs2_rtype connect slots_3.io.in_uop.bits.lrs1_rtype, issue_slots[3].in_uop.bits.lrs1_rtype connect slots_3.io.in_uop.bits.dst_rtype, issue_slots[3].in_uop.bits.dst_rtype connect slots_3.io.in_uop.bits.lrs3, issue_slots[3].in_uop.bits.lrs3 connect slots_3.io.in_uop.bits.lrs2, issue_slots[3].in_uop.bits.lrs2 connect slots_3.io.in_uop.bits.lrs1, issue_slots[3].in_uop.bits.lrs1 connect slots_3.io.in_uop.bits.ldst, issue_slots[3].in_uop.bits.ldst connect slots_3.io.in_uop.bits.ldst_is_rs1, issue_slots[3].in_uop.bits.ldst_is_rs1 connect slots_3.io.in_uop.bits.csr_cmd, issue_slots[3].in_uop.bits.csr_cmd connect slots_3.io.in_uop.bits.flush_on_commit, issue_slots[3].in_uop.bits.flush_on_commit connect slots_3.io.in_uop.bits.is_unique, issue_slots[3].in_uop.bits.is_unique connect slots_3.io.in_uop.bits.uses_stq, issue_slots[3].in_uop.bits.uses_stq connect slots_3.io.in_uop.bits.uses_ldq, issue_slots[3].in_uop.bits.uses_ldq connect slots_3.io.in_uop.bits.mem_signed, issue_slots[3].in_uop.bits.mem_signed connect slots_3.io.in_uop.bits.mem_size, issue_slots[3].in_uop.bits.mem_size connect slots_3.io.in_uop.bits.mem_cmd, issue_slots[3].in_uop.bits.mem_cmd connect slots_3.io.in_uop.bits.exc_cause, issue_slots[3].in_uop.bits.exc_cause connect slots_3.io.in_uop.bits.exception, issue_slots[3].in_uop.bits.exception connect slots_3.io.in_uop.bits.stale_pdst, issue_slots[3].in_uop.bits.stale_pdst connect slots_3.io.in_uop.bits.ppred_busy, issue_slots[3].in_uop.bits.ppred_busy connect slots_3.io.in_uop.bits.prs3_busy, issue_slots[3].in_uop.bits.prs3_busy connect slots_3.io.in_uop.bits.prs2_busy, issue_slots[3].in_uop.bits.prs2_busy connect slots_3.io.in_uop.bits.prs1_busy, issue_slots[3].in_uop.bits.prs1_busy connect slots_3.io.in_uop.bits.ppred, issue_slots[3].in_uop.bits.ppred connect slots_3.io.in_uop.bits.prs3, issue_slots[3].in_uop.bits.prs3 connect slots_3.io.in_uop.bits.prs2, issue_slots[3].in_uop.bits.prs2 connect slots_3.io.in_uop.bits.prs1, issue_slots[3].in_uop.bits.prs1 connect slots_3.io.in_uop.bits.pdst, issue_slots[3].in_uop.bits.pdst connect slots_3.io.in_uop.bits.rxq_idx, issue_slots[3].in_uop.bits.rxq_idx connect slots_3.io.in_uop.bits.stq_idx, issue_slots[3].in_uop.bits.stq_idx connect slots_3.io.in_uop.bits.ldq_idx, issue_slots[3].in_uop.bits.ldq_idx connect slots_3.io.in_uop.bits.rob_idx, issue_slots[3].in_uop.bits.rob_idx connect slots_3.io.in_uop.bits.fp_ctrl.vec, issue_slots[3].in_uop.bits.fp_ctrl.vec connect slots_3.io.in_uop.bits.fp_ctrl.wflags, issue_slots[3].in_uop.bits.fp_ctrl.wflags connect slots_3.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[3].in_uop.bits.fp_ctrl.sqrt connect slots_3.io.in_uop.bits.fp_ctrl.div, issue_slots[3].in_uop.bits.fp_ctrl.div connect slots_3.io.in_uop.bits.fp_ctrl.fma, issue_slots[3].in_uop.bits.fp_ctrl.fma connect slots_3.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].in_uop.bits.fp_ctrl.fastpipe connect slots_3.io.in_uop.bits.fp_ctrl.toint, issue_slots[3].in_uop.bits.fp_ctrl.toint connect slots_3.io.in_uop.bits.fp_ctrl.fromint, issue_slots[3].in_uop.bits.fp_ctrl.fromint connect slots_3.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut connect slots_3.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn connect slots_3.io.in_uop.bits.fp_ctrl.swap23, issue_slots[3].in_uop.bits.fp_ctrl.swap23 connect slots_3.io.in_uop.bits.fp_ctrl.swap12, issue_slots[3].in_uop.bits.fp_ctrl.swap12 connect slots_3.io.in_uop.bits.fp_ctrl.ren3, issue_slots[3].in_uop.bits.fp_ctrl.ren3 connect slots_3.io.in_uop.bits.fp_ctrl.ren2, issue_slots[3].in_uop.bits.fp_ctrl.ren2 connect slots_3.io.in_uop.bits.fp_ctrl.ren1, issue_slots[3].in_uop.bits.fp_ctrl.ren1 connect slots_3.io.in_uop.bits.fp_ctrl.wen, issue_slots[3].in_uop.bits.fp_ctrl.wen connect slots_3.io.in_uop.bits.fp_ctrl.ldst, issue_slots[3].in_uop.bits.fp_ctrl.ldst connect slots_3.io.in_uop.bits.op2_sel, issue_slots[3].in_uop.bits.op2_sel connect slots_3.io.in_uop.bits.op1_sel, issue_slots[3].in_uop.bits.op1_sel connect slots_3.io.in_uop.bits.imm_packed, issue_slots[3].in_uop.bits.imm_packed connect slots_3.io.in_uop.bits.pimm, issue_slots[3].in_uop.bits.pimm connect slots_3.io.in_uop.bits.imm_sel, issue_slots[3].in_uop.bits.imm_sel connect slots_3.io.in_uop.bits.imm_rename, issue_slots[3].in_uop.bits.imm_rename connect slots_3.io.in_uop.bits.taken, issue_slots[3].in_uop.bits.taken connect slots_3.io.in_uop.bits.pc_lob, issue_slots[3].in_uop.bits.pc_lob connect slots_3.io.in_uop.bits.edge_inst, issue_slots[3].in_uop.bits.edge_inst connect slots_3.io.in_uop.bits.ftq_idx, issue_slots[3].in_uop.bits.ftq_idx connect slots_3.io.in_uop.bits.is_mov, issue_slots[3].in_uop.bits.is_mov connect slots_3.io.in_uop.bits.is_rocc, issue_slots[3].in_uop.bits.is_rocc connect slots_3.io.in_uop.bits.is_sys_pc2epc, issue_slots[3].in_uop.bits.is_sys_pc2epc connect slots_3.io.in_uop.bits.is_eret, issue_slots[3].in_uop.bits.is_eret connect slots_3.io.in_uop.bits.is_amo, issue_slots[3].in_uop.bits.is_amo connect slots_3.io.in_uop.bits.is_sfence, issue_slots[3].in_uop.bits.is_sfence connect slots_3.io.in_uop.bits.is_fencei, issue_slots[3].in_uop.bits.is_fencei connect slots_3.io.in_uop.bits.is_fence, issue_slots[3].in_uop.bits.is_fence connect slots_3.io.in_uop.bits.is_sfb, issue_slots[3].in_uop.bits.is_sfb connect slots_3.io.in_uop.bits.br_type, issue_slots[3].in_uop.bits.br_type connect slots_3.io.in_uop.bits.br_tag, issue_slots[3].in_uop.bits.br_tag connect slots_3.io.in_uop.bits.br_mask, issue_slots[3].in_uop.bits.br_mask connect slots_3.io.in_uop.bits.dis_col_sel, issue_slots[3].in_uop.bits.dis_col_sel connect slots_3.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[3].in_uop.bits.iw_p3_bypass_hint connect slots_3.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[3].in_uop.bits.iw_p2_bypass_hint connect slots_3.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[3].in_uop.bits.iw_p1_bypass_hint connect slots_3.io.in_uop.bits.iw_p2_speculative_child, issue_slots[3].in_uop.bits.iw_p2_speculative_child connect slots_3.io.in_uop.bits.iw_p1_speculative_child, issue_slots[3].in_uop.bits.iw_p1_speculative_child connect slots_3.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[3].in_uop.bits.iw_issued_partial_dgen connect slots_3.io.in_uop.bits.iw_issued_partial_agen, issue_slots[3].in_uop.bits.iw_issued_partial_agen connect slots_3.io.in_uop.bits.iw_issued, issue_slots[3].in_uop.bits.iw_issued connect slots_3.io.in_uop.bits.fu_code[0], issue_slots[3].in_uop.bits.fu_code[0] connect slots_3.io.in_uop.bits.fu_code[1], issue_slots[3].in_uop.bits.fu_code[1] connect slots_3.io.in_uop.bits.fu_code[2], issue_slots[3].in_uop.bits.fu_code[2] connect slots_3.io.in_uop.bits.fu_code[3], issue_slots[3].in_uop.bits.fu_code[3] connect slots_3.io.in_uop.bits.fu_code[4], issue_slots[3].in_uop.bits.fu_code[4] connect slots_3.io.in_uop.bits.fu_code[5], issue_slots[3].in_uop.bits.fu_code[5] connect slots_3.io.in_uop.bits.fu_code[6], issue_slots[3].in_uop.bits.fu_code[6] connect slots_3.io.in_uop.bits.fu_code[7], issue_slots[3].in_uop.bits.fu_code[7] connect slots_3.io.in_uop.bits.fu_code[8], issue_slots[3].in_uop.bits.fu_code[8] connect slots_3.io.in_uop.bits.fu_code[9], issue_slots[3].in_uop.bits.fu_code[9] connect slots_3.io.in_uop.bits.iq_type[0], issue_slots[3].in_uop.bits.iq_type[0] connect slots_3.io.in_uop.bits.iq_type[1], issue_slots[3].in_uop.bits.iq_type[1] connect slots_3.io.in_uop.bits.iq_type[2], issue_slots[3].in_uop.bits.iq_type[2] connect slots_3.io.in_uop.bits.iq_type[3], issue_slots[3].in_uop.bits.iq_type[3] connect slots_3.io.in_uop.bits.debug_pc, issue_slots[3].in_uop.bits.debug_pc connect slots_3.io.in_uop.bits.is_rvc, issue_slots[3].in_uop.bits.is_rvc connect slots_3.io.in_uop.bits.debug_inst, issue_slots[3].in_uop.bits.debug_inst connect slots_3.io.in_uop.bits.inst, issue_slots[3].in_uop.bits.inst connect slots_3.io.in_uop.valid, issue_slots[3].in_uop.valid connect issue_slots[3].iss_uop.debug_tsrc, slots_3.io.iss_uop.debug_tsrc connect issue_slots[3].iss_uop.debug_fsrc, slots_3.io.iss_uop.debug_fsrc connect issue_slots[3].iss_uop.bp_xcpt_if, slots_3.io.iss_uop.bp_xcpt_if connect issue_slots[3].iss_uop.bp_debug_if, slots_3.io.iss_uop.bp_debug_if connect issue_slots[3].iss_uop.xcpt_ma_if, slots_3.io.iss_uop.xcpt_ma_if connect issue_slots[3].iss_uop.xcpt_ae_if, slots_3.io.iss_uop.xcpt_ae_if connect issue_slots[3].iss_uop.xcpt_pf_if, slots_3.io.iss_uop.xcpt_pf_if connect issue_slots[3].iss_uop.fp_typ, slots_3.io.iss_uop.fp_typ connect issue_slots[3].iss_uop.fp_rm, slots_3.io.iss_uop.fp_rm connect issue_slots[3].iss_uop.fp_val, slots_3.io.iss_uop.fp_val connect issue_slots[3].iss_uop.fcn_op, slots_3.io.iss_uop.fcn_op connect issue_slots[3].iss_uop.fcn_dw, slots_3.io.iss_uop.fcn_dw connect issue_slots[3].iss_uop.frs3_en, slots_3.io.iss_uop.frs3_en connect issue_slots[3].iss_uop.lrs2_rtype, slots_3.io.iss_uop.lrs2_rtype connect issue_slots[3].iss_uop.lrs1_rtype, slots_3.io.iss_uop.lrs1_rtype connect issue_slots[3].iss_uop.dst_rtype, slots_3.io.iss_uop.dst_rtype connect issue_slots[3].iss_uop.lrs3, slots_3.io.iss_uop.lrs3 connect issue_slots[3].iss_uop.lrs2, slots_3.io.iss_uop.lrs2 connect issue_slots[3].iss_uop.lrs1, slots_3.io.iss_uop.lrs1 connect issue_slots[3].iss_uop.ldst, slots_3.io.iss_uop.ldst connect issue_slots[3].iss_uop.ldst_is_rs1, slots_3.io.iss_uop.ldst_is_rs1 connect issue_slots[3].iss_uop.csr_cmd, slots_3.io.iss_uop.csr_cmd connect issue_slots[3].iss_uop.flush_on_commit, slots_3.io.iss_uop.flush_on_commit connect issue_slots[3].iss_uop.is_unique, slots_3.io.iss_uop.is_unique connect issue_slots[3].iss_uop.uses_stq, slots_3.io.iss_uop.uses_stq connect issue_slots[3].iss_uop.uses_ldq, slots_3.io.iss_uop.uses_ldq connect issue_slots[3].iss_uop.mem_signed, slots_3.io.iss_uop.mem_signed connect issue_slots[3].iss_uop.mem_size, slots_3.io.iss_uop.mem_size connect issue_slots[3].iss_uop.mem_cmd, slots_3.io.iss_uop.mem_cmd connect issue_slots[3].iss_uop.exc_cause, slots_3.io.iss_uop.exc_cause connect issue_slots[3].iss_uop.exception, slots_3.io.iss_uop.exception connect issue_slots[3].iss_uop.stale_pdst, slots_3.io.iss_uop.stale_pdst connect issue_slots[3].iss_uop.ppred_busy, slots_3.io.iss_uop.ppred_busy connect issue_slots[3].iss_uop.prs3_busy, slots_3.io.iss_uop.prs3_busy connect issue_slots[3].iss_uop.prs2_busy, slots_3.io.iss_uop.prs2_busy connect issue_slots[3].iss_uop.prs1_busy, slots_3.io.iss_uop.prs1_busy connect issue_slots[3].iss_uop.ppred, slots_3.io.iss_uop.ppred connect issue_slots[3].iss_uop.prs3, slots_3.io.iss_uop.prs3 connect issue_slots[3].iss_uop.prs2, slots_3.io.iss_uop.prs2 connect issue_slots[3].iss_uop.prs1, slots_3.io.iss_uop.prs1 connect issue_slots[3].iss_uop.pdst, slots_3.io.iss_uop.pdst connect issue_slots[3].iss_uop.rxq_idx, slots_3.io.iss_uop.rxq_idx connect issue_slots[3].iss_uop.stq_idx, slots_3.io.iss_uop.stq_idx connect issue_slots[3].iss_uop.ldq_idx, slots_3.io.iss_uop.ldq_idx connect issue_slots[3].iss_uop.rob_idx, slots_3.io.iss_uop.rob_idx connect issue_slots[3].iss_uop.fp_ctrl.vec, slots_3.io.iss_uop.fp_ctrl.vec connect issue_slots[3].iss_uop.fp_ctrl.wflags, slots_3.io.iss_uop.fp_ctrl.wflags connect issue_slots[3].iss_uop.fp_ctrl.sqrt, slots_3.io.iss_uop.fp_ctrl.sqrt connect issue_slots[3].iss_uop.fp_ctrl.div, slots_3.io.iss_uop.fp_ctrl.div connect issue_slots[3].iss_uop.fp_ctrl.fma, slots_3.io.iss_uop.fp_ctrl.fma connect issue_slots[3].iss_uop.fp_ctrl.fastpipe, slots_3.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[3].iss_uop.fp_ctrl.toint, slots_3.io.iss_uop.fp_ctrl.toint connect issue_slots[3].iss_uop.fp_ctrl.fromint, slots_3.io.iss_uop.fp_ctrl.fromint connect issue_slots[3].iss_uop.fp_ctrl.typeTagOut, slots_3.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[3].iss_uop.fp_ctrl.typeTagIn, slots_3.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[3].iss_uop.fp_ctrl.swap23, slots_3.io.iss_uop.fp_ctrl.swap23 connect issue_slots[3].iss_uop.fp_ctrl.swap12, slots_3.io.iss_uop.fp_ctrl.swap12 connect issue_slots[3].iss_uop.fp_ctrl.ren3, slots_3.io.iss_uop.fp_ctrl.ren3 connect issue_slots[3].iss_uop.fp_ctrl.ren2, slots_3.io.iss_uop.fp_ctrl.ren2 connect issue_slots[3].iss_uop.fp_ctrl.ren1, slots_3.io.iss_uop.fp_ctrl.ren1 connect issue_slots[3].iss_uop.fp_ctrl.wen, slots_3.io.iss_uop.fp_ctrl.wen connect issue_slots[3].iss_uop.fp_ctrl.ldst, slots_3.io.iss_uop.fp_ctrl.ldst connect issue_slots[3].iss_uop.op2_sel, slots_3.io.iss_uop.op2_sel connect issue_slots[3].iss_uop.op1_sel, slots_3.io.iss_uop.op1_sel connect issue_slots[3].iss_uop.imm_packed, slots_3.io.iss_uop.imm_packed connect issue_slots[3].iss_uop.pimm, slots_3.io.iss_uop.pimm connect issue_slots[3].iss_uop.imm_sel, slots_3.io.iss_uop.imm_sel connect issue_slots[3].iss_uop.imm_rename, slots_3.io.iss_uop.imm_rename connect issue_slots[3].iss_uop.taken, slots_3.io.iss_uop.taken connect issue_slots[3].iss_uop.pc_lob, slots_3.io.iss_uop.pc_lob connect issue_slots[3].iss_uop.edge_inst, slots_3.io.iss_uop.edge_inst connect issue_slots[3].iss_uop.ftq_idx, slots_3.io.iss_uop.ftq_idx connect issue_slots[3].iss_uop.is_mov, slots_3.io.iss_uop.is_mov connect issue_slots[3].iss_uop.is_rocc, slots_3.io.iss_uop.is_rocc connect issue_slots[3].iss_uop.is_sys_pc2epc, slots_3.io.iss_uop.is_sys_pc2epc connect issue_slots[3].iss_uop.is_eret, slots_3.io.iss_uop.is_eret connect issue_slots[3].iss_uop.is_amo, slots_3.io.iss_uop.is_amo connect issue_slots[3].iss_uop.is_sfence, slots_3.io.iss_uop.is_sfence connect issue_slots[3].iss_uop.is_fencei, slots_3.io.iss_uop.is_fencei connect issue_slots[3].iss_uop.is_fence, slots_3.io.iss_uop.is_fence connect issue_slots[3].iss_uop.is_sfb, slots_3.io.iss_uop.is_sfb connect issue_slots[3].iss_uop.br_type, slots_3.io.iss_uop.br_type connect issue_slots[3].iss_uop.br_tag, slots_3.io.iss_uop.br_tag connect issue_slots[3].iss_uop.br_mask, slots_3.io.iss_uop.br_mask connect issue_slots[3].iss_uop.dis_col_sel, slots_3.io.iss_uop.dis_col_sel connect issue_slots[3].iss_uop.iw_p3_bypass_hint, slots_3.io.iss_uop.iw_p3_bypass_hint connect issue_slots[3].iss_uop.iw_p2_bypass_hint, slots_3.io.iss_uop.iw_p2_bypass_hint connect issue_slots[3].iss_uop.iw_p1_bypass_hint, slots_3.io.iss_uop.iw_p1_bypass_hint connect issue_slots[3].iss_uop.iw_p2_speculative_child, slots_3.io.iss_uop.iw_p2_speculative_child connect issue_slots[3].iss_uop.iw_p1_speculative_child, slots_3.io.iss_uop.iw_p1_speculative_child connect issue_slots[3].iss_uop.iw_issued_partial_dgen, slots_3.io.iss_uop.iw_issued_partial_dgen connect issue_slots[3].iss_uop.iw_issued_partial_agen, slots_3.io.iss_uop.iw_issued_partial_agen connect issue_slots[3].iss_uop.iw_issued, slots_3.io.iss_uop.iw_issued connect issue_slots[3].iss_uop.fu_code[0], slots_3.io.iss_uop.fu_code[0] connect issue_slots[3].iss_uop.fu_code[1], slots_3.io.iss_uop.fu_code[1] connect issue_slots[3].iss_uop.fu_code[2], slots_3.io.iss_uop.fu_code[2] connect issue_slots[3].iss_uop.fu_code[3], slots_3.io.iss_uop.fu_code[3] connect issue_slots[3].iss_uop.fu_code[4], slots_3.io.iss_uop.fu_code[4] connect issue_slots[3].iss_uop.fu_code[5], slots_3.io.iss_uop.fu_code[5] connect issue_slots[3].iss_uop.fu_code[6], slots_3.io.iss_uop.fu_code[6] connect issue_slots[3].iss_uop.fu_code[7], slots_3.io.iss_uop.fu_code[7] connect issue_slots[3].iss_uop.fu_code[8], slots_3.io.iss_uop.fu_code[8] connect issue_slots[3].iss_uop.fu_code[9], slots_3.io.iss_uop.fu_code[9] connect issue_slots[3].iss_uop.iq_type[0], slots_3.io.iss_uop.iq_type[0] connect issue_slots[3].iss_uop.iq_type[1], slots_3.io.iss_uop.iq_type[1] connect issue_slots[3].iss_uop.iq_type[2], slots_3.io.iss_uop.iq_type[2] connect issue_slots[3].iss_uop.iq_type[3], slots_3.io.iss_uop.iq_type[3] connect issue_slots[3].iss_uop.debug_pc, slots_3.io.iss_uop.debug_pc connect issue_slots[3].iss_uop.is_rvc, slots_3.io.iss_uop.is_rvc connect issue_slots[3].iss_uop.debug_inst, slots_3.io.iss_uop.debug_inst connect issue_slots[3].iss_uop.inst, slots_3.io.iss_uop.inst connect slots_3.io.grant, issue_slots[3].grant connect issue_slots[3].request, slots_3.io.request connect issue_slots[3].will_be_valid, slots_3.io.will_be_valid connect issue_slots[3].valid, slots_3.io.valid connect slots_4.io.child_rebusys, issue_slots[4].child_rebusys connect slots_4.io.pred_wakeup_port.bits, issue_slots[4].pred_wakeup_port.bits connect slots_4.io.pred_wakeup_port.valid, issue_slots[4].pred_wakeup_port.valid connect slots_4.io.wakeup_ports[0].bits.rebusy, issue_slots[4].wakeup_ports[0].bits.rebusy connect slots_4.io.wakeup_ports[0].bits.speculative_mask, issue_slots[4].wakeup_ports[0].bits.speculative_mask connect slots_4.io.wakeup_ports[0].bits.bypassable, issue_slots[4].wakeup_ports[0].bits.bypassable connect slots_4.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[0].bits.uop.debug_tsrc connect slots_4.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[0].bits.uop.debug_fsrc connect slots_4.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_4.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[0].bits.uop.bp_debug_if connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_4.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[4].wakeup_ports[0].bits.uop.fp_typ connect slots_4.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[4].wakeup_ports[0].bits.uop.fp_rm connect slots_4.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[4].wakeup_ports[0].bits.uop.fp_val connect slots_4.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[4].wakeup_ports[0].bits.uop.fcn_op connect slots_4.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[0].bits.uop.fcn_dw connect slots_4.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[4].wakeup_ports[0].bits.uop.frs3_en connect slots_4.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_4.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_4.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[0].bits.uop.dst_rtype connect slots_4.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[4].wakeup_ports[0].bits.uop.lrs3 connect slots_4.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[4].wakeup_ports[0].bits.uop.lrs2 connect slots_4.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[4].wakeup_ports[0].bits.uop.lrs1 connect slots_4.io.wakeup_ports[0].bits.uop.ldst, issue_slots[4].wakeup_ports[0].bits.uop.ldst connect slots_4.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_4.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[0].bits.uop.csr_cmd connect slots_4.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[0].bits.uop.flush_on_commit connect slots_4.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[4].wakeup_ports[0].bits.uop.is_unique connect slots_4.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[4].wakeup_ports[0].bits.uop.uses_stq connect slots_4.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[0].bits.uop.uses_ldq connect slots_4.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[4].wakeup_ports[0].bits.uop.mem_signed connect slots_4.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[4].wakeup_ports[0].bits.uop.mem_size connect slots_4.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[0].bits.uop.mem_cmd connect slots_4.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[4].wakeup_ports[0].bits.uop.exc_cause connect slots_4.io.wakeup_ports[0].bits.uop.exception, issue_slots[4].wakeup_ports[0].bits.uop.exception connect slots_4.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[0].bits.uop.stale_pdst connect slots_4.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[0].bits.uop.ppred_busy connect slots_4.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs3_busy connect slots_4.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs2_busy connect slots_4.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs1_busy connect slots_4.io.wakeup_ports[0].bits.uop.ppred, issue_slots[4].wakeup_ports[0].bits.uop.ppred connect slots_4.io.wakeup_ports[0].bits.uop.prs3, issue_slots[4].wakeup_ports[0].bits.uop.prs3 connect slots_4.io.wakeup_ports[0].bits.uop.prs2, issue_slots[4].wakeup_ports[0].bits.uop.prs2 connect slots_4.io.wakeup_ports[0].bits.uop.prs1, issue_slots[4].wakeup_ports[0].bits.uop.prs1 connect slots_4.io.wakeup_ports[0].bits.uop.pdst, issue_slots[4].wakeup_ports[0].bits.uop.pdst connect slots_4.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[0].bits.uop.rxq_idx connect slots_4.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[4].wakeup_ports[0].bits.uop.stq_idx connect slots_4.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[0].bits.uop.ldq_idx connect slots_4.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[4].wakeup_ports[0].bits.uop.rob_idx connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_4.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[4].wakeup_ports[0].bits.uop.op2_sel connect slots_4.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[4].wakeup_ports[0].bits.uop.op1_sel connect slots_4.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[4].wakeup_ports[0].bits.uop.imm_packed connect slots_4.io.wakeup_ports[0].bits.uop.pimm, issue_slots[4].wakeup_ports[0].bits.uop.pimm connect slots_4.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[4].wakeup_ports[0].bits.uop.imm_sel connect slots_4.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[4].wakeup_ports[0].bits.uop.imm_rename connect slots_4.io.wakeup_ports[0].bits.uop.taken, issue_slots[4].wakeup_ports[0].bits.uop.taken connect slots_4.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[4].wakeup_ports[0].bits.uop.pc_lob connect slots_4.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[4].wakeup_ports[0].bits.uop.edge_inst connect slots_4.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[0].bits.uop.ftq_idx connect slots_4.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[4].wakeup_ports[0].bits.uop.is_mov connect slots_4.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[4].wakeup_ports[0].bits.uop.is_rocc connect slots_4.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_4.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[4].wakeup_ports[0].bits.uop.is_eret connect slots_4.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[4].wakeup_ports[0].bits.uop.is_amo connect slots_4.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[4].wakeup_ports[0].bits.uop.is_sfence connect slots_4.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[4].wakeup_ports[0].bits.uop.is_fencei connect slots_4.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[4].wakeup_ports[0].bits.uop.is_fence connect slots_4.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[4].wakeup_ports[0].bits.uop.is_sfb connect slots_4.io.wakeup_ports[0].bits.uop.br_type, issue_slots[4].wakeup_ports[0].bits.uop.br_type connect slots_4.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[4].wakeup_ports[0].bits.uop.br_tag connect slots_4.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[4].wakeup_ports[0].bits.uop.br_mask connect slots_4.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[0].bits.uop.dis_col_sel connect slots_4.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_4.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_4.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_4.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_4.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[0] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[1] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[2] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[3] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[4] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[5] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[6] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[7] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[8] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[9] connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[0] connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[1] connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[2] connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[3] connect slots_4.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[4].wakeup_ports[0].bits.uop.debug_pc connect slots_4.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[4].wakeup_ports[0].bits.uop.is_rvc connect slots_4.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[4].wakeup_ports[0].bits.uop.debug_inst connect slots_4.io.wakeup_ports[0].bits.uop.inst, issue_slots[4].wakeup_ports[0].bits.uop.inst connect slots_4.io.wakeup_ports[0].valid, issue_slots[4].wakeup_ports[0].valid connect slots_4.io.wakeup_ports[1].bits.rebusy, issue_slots[4].wakeup_ports[1].bits.rebusy connect slots_4.io.wakeup_ports[1].bits.speculative_mask, issue_slots[4].wakeup_ports[1].bits.speculative_mask connect slots_4.io.wakeup_ports[1].bits.bypassable, issue_slots[4].wakeup_ports[1].bits.bypassable connect slots_4.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[1].bits.uop.debug_tsrc connect slots_4.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[1].bits.uop.debug_fsrc connect slots_4.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_4.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[1].bits.uop.bp_debug_if connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_4.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[4].wakeup_ports[1].bits.uop.fp_typ connect slots_4.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[4].wakeup_ports[1].bits.uop.fp_rm connect slots_4.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[4].wakeup_ports[1].bits.uop.fp_val connect slots_4.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[4].wakeup_ports[1].bits.uop.fcn_op connect slots_4.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[1].bits.uop.fcn_dw connect slots_4.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[4].wakeup_ports[1].bits.uop.frs3_en connect slots_4.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_4.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_4.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[1].bits.uop.dst_rtype connect slots_4.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[4].wakeup_ports[1].bits.uop.lrs3 connect slots_4.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[4].wakeup_ports[1].bits.uop.lrs2 connect slots_4.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[4].wakeup_ports[1].bits.uop.lrs1 connect slots_4.io.wakeup_ports[1].bits.uop.ldst, issue_slots[4].wakeup_ports[1].bits.uop.ldst connect slots_4.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_4.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[1].bits.uop.csr_cmd connect slots_4.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[1].bits.uop.flush_on_commit connect slots_4.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[4].wakeup_ports[1].bits.uop.is_unique connect slots_4.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[4].wakeup_ports[1].bits.uop.uses_stq connect slots_4.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[1].bits.uop.uses_ldq connect slots_4.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[4].wakeup_ports[1].bits.uop.mem_signed connect slots_4.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[4].wakeup_ports[1].bits.uop.mem_size connect slots_4.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[1].bits.uop.mem_cmd connect slots_4.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[4].wakeup_ports[1].bits.uop.exc_cause connect slots_4.io.wakeup_ports[1].bits.uop.exception, issue_slots[4].wakeup_ports[1].bits.uop.exception connect slots_4.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[1].bits.uop.stale_pdst connect slots_4.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[1].bits.uop.ppred_busy connect slots_4.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs3_busy connect slots_4.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs2_busy connect slots_4.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs1_busy connect slots_4.io.wakeup_ports[1].bits.uop.ppred, issue_slots[4].wakeup_ports[1].bits.uop.ppred connect slots_4.io.wakeup_ports[1].bits.uop.prs3, issue_slots[4].wakeup_ports[1].bits.uop.prs3 connect slots_4.io.wakeup_ports[1].bits.uop.prs2, issue_slots[4].wakeup_ports[1].bits.uop.prs2 connect slots_4.io.wakeup_ports[1].bits.uop.prs1, issue_slots[4].wakeup_ports[1].bits.uop.prs1 connect slots_4.io.wakeup_ports[1].bits.uop.pdst, issue_slots[4].wakeup_ports[1].bits.uop.pdst connect slots_4.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[1].bits.uop.rxq_idx connect slots_4.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[4].wakeup_ports[1].bits.uop.stq_idx connect slots_4.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[1].bits.uop.ldq_idx connect slots_4.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[4].wakeup_ports[1].bits.uop.rob_idx connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_4.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[4].wakeup_ports[1].bits.uop.op2_sel connect slots_4.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[4].wakeup_ports[1].bits.uop.op1_sel connect slots_4.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[4].wakeup_ports[1].bits.uop.imm_packed connect slots_4.io.wakeup_ports[1].bits.uop.pimm, issue_slots[4].wakeup_ports[1].bits.uop.pimm connect slots_4.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[4].wakeup_ports[1].bits.uop.imm_sel connect slots_4.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[4].wakeup_ports[1].bits.uop.imm_rename connect slots_4.io.wakeup_ports[1].bits.uop.taken, issue_slots[4].wakeup_ports[1].bits.uop.taken connect slots_4.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[4].wakeup_ports[1].bits.uop.pc_lob connect slots_4.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[4].wakeup_ports[1].bits.uop.edge_inst connect slots_4.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[1].bits.uop.ftq_idx connect slots_4.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[4].wakeup_ports[1].bits.uop.is_mov connect slots_4.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[4].wakeup_ports[1].bits.uop.is_rocc connect slots_4.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_4.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[4].wakeup_ports[1].bits.uop.is_eret connect slots_4.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[4].wakeup_ports[1].bits.uop.is_amo connect slots_4.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[4].wakeup_ports[1].bits.uop.is_sfence connect slots_4.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[4].wakeup_ports[1].bits.uop.is_fencei connect slots_4.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[4].wakeup_ports[1].bits.uop.is_fence connect slots_4.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[4].wakeup_ports[1].bits.uop.is_sfb connect slots_4.io.wakeup_ports[1].bits.uop.br_type, issue_slots[4].wakeup_ports[1].bits.uop.br_type connect slots_4.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[4].wakeup_ports[1].bits.uop.br_tag connect slots_4.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[4].wakeup_ports[1].bits.uop.br_mask connect slots_4.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[1].bits.uop.dis_col_sel connect slots_4.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_4.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_4.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_4.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_4.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[0] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[1] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[2] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[3] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[4] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[5] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[6] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[7] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[8] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[9] connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[0] connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[1] connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[2] connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[3] connect slots_4.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[4].wakeup_ports[1].bits.uop.debug_pc connect slots_4.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[4].wakeup_ports[1].bits.uop.is_rvc connect slots_4.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[4].wakeup_ports[1].bits.uop.debug_inst connect slots_4.io.wakeup_ports[1].bits.uop.inst, issue_slots[4].wakeup_ports[1].bits.uop.inst connect slots_4.io.wakeup_ports[1].valid, issue_slots[4].wakeup_ports[1].valid connect slots_4.io.wakeup_ports[2].bits.rebusy, issue_slots[4].wakeup_ports[2].bits.rebusy connect slots_4.io.wakeup_ports[2].bits.speculative_mask, issue_slots[4].wakeup_ports[2].bits.speculative_mask connect slots_4.io.wakeup_ports[2].bits.bypassable, issue_slots[4].wakeup_ports[2].bits.bypassable connect slots_4.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[2].bits.uop.debug_tsrc connect slots_4.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[2].bits.uop.debug_fsrc connect slots_4.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_4.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[2].bits.uop.bp_debug_if connect slots_4.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_4.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_4.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_4.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[4].wakeup_ports[2].bits.uop.fp_typ connect slots_4.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[4].wakeup_ports[2].bits.uop.fp_rm connect slots_4.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[4].wakeup_ports[2].bits.uop.fp_val connect slots_4.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[4].wakeup_ports[2].bits.uop.fcn_op connect slots_4.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[2].bits.uop.fcn_dw connect slots_4.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[4].wakeup_ports[2].bits.uop.frs3_en connect slots_4.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_4.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_4.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[2].bits.uop.dst_rtype connect slots_4.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[4].wakeup_ports[2].bits.uop.lrs3 connect slots_4.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[4].wakeup_ports[2].bits.uop.lrs2 connect slots_4.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[4].wakeup_ports[2].bits.uop.lrs1 connect slots_4.io.wakeup_ports[2].bits.uop.ldst, issue_slots[4].wakeup_ports[2].bits.uop.ldst connect slots_4.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_4.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[2].bits.uop.csr_cmd connect slots_4.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[2].bits.uop.flush_on_commit connect slots_4.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[4].wakeup_ports[2].bits.uop.is_unique connect slots_4.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[4].wakeup_ports[2].bits.uop.uses_stq connect slots_4.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[2].bits.uop.uses_ldq connect slots_4.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[4].wakeup_ports[2].bits.uop.mem_signed connect slots_4.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[4].wakeup_ports[2].bits.uop.mem_size connect slots_4.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[2].bits.uop.mem_cmd connect slots_4.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[4].wakeup_ports[2].bits.uop.exc_cause connect slots_4.io.wakeup_ports[2].bits.uop.exception, issue_slots[4].wakeup_ports[2].bits.uop.exception connect slots_4.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[2].bits.uop.stale_pdst connect slots_4.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[2].bits.uop.ppred_busy connect slots_4.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[2].bits.uop.prs3_busy connect slots_4.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[2].bits.uop.prs2_busy connect slots_4.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[2].bits.uop.prs1_busy connect slots_4.io.wakeup_ports[2].bits.uop.ppred, issue_slots[4].wakeup_ports[2].bits.uop.ppred connect slots_4.io.wakeup_ports[2].bits.uop.prs3, issue_slots[4].wakeup_ports[2].bits.uop.prs3 connect slots_4.io.wakeup_ports[2].bits.uop.prs2, issue_slots[4].wakeup_ports[2].bits.uop.prs2 connect slots_4.io.wakeup_ports[2].bits.uop.prs1, issue_slots[4].wakeup_ports[2].bits.uop.prs1 connect slots_4.io.wakeup_ports[2].bits.uop.pdst, issue_slots[4].wakeup_ports[2].bits.uop.pdst connect slots_4.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[2].bits.uop.rxq_idx connect slots_4.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[4].wakeup_ports[2].bits.uop.stq_idx connect slots_4.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[2].bits.uop.ldq_idx connect slots_4.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[4].wakeup_ports[2].bits.uop.rob_idx connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_4.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[4].wakeup_ports[2].bits.uop.op2_sel connect slots_4.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[4].wakeup_ports[2].bits.uop.op1_sel connect slots_4.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[4].wakeup_ports[2].bits.uop.imm_packed connect slots_4.io.wakeup_ports[2].bits.uop.pimm, issue_slots[4].wakeup_ports[2].bits.uop.pimm connect slots_4.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[4].wakeup_ports[2].bits.uop.imm_sel connect slots_4.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[4].wakeup_ports[2].bits.uop.imm_rename connect slots_4.io.wakeup_ports[2].bits.uop.taken, issue_slots[4].wakeup_ports[2].bits.uop.taken connect slots_4.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[4].wakeup_ports[2].bits.uop.pc_lob connect slots_4.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[4].wakeup_ports[2].bits.uop.edge_inst connect slots_4.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[2].bits.uop.ftq_idx connect slots_4.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[4].wakeup_ports[2].bits.uop.is_mov connect slots_4.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[4].wakeup_ports[2].bits.uop.is_rocc connect slots_4.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_4.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[4].wakeup_ports[2].bits.uop.is_eret connect slots_4.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[4].wakeup_ports[2].bits.uop.is_amo connect slots_4.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[4].wakeup_ports[2].bits.uop.is_sfence connect slots_4.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[4].wakeup_ports[2].bits.uop.is_fencei connect slots_4.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[4].wakeup_ports[2].bits.uop.is_fence connect slots_4.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[4].wakeup_ports[2].bits.uop.is_sfb connect slots_4.io.wakeup_ports[2].bits.uop.br_type, issue_slots[4].wakeup_ports[2].bits.uop.br_type connect slots_4.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[4].wakeup_ports[2].bits.uop.br_tag connect slots_4.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[4].wakeup_ports[2].bits.uop.br_mask connect slots_4.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[2].bits.uop.dis_col_sel connect slots_4.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_4.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_4.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_4.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_4.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_4.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_4.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_4.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[4].wakeup_ports[2].bits.uop.iw_issued connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[0] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[1] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[2] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[3] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[4] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[5] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[6] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[7] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[8] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[9] connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[0] connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[1] connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[2] connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[3] connect slots_4.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[4].wakeup_ports[2].bits.uop.debug_pc connect slots_4.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[4].wakeup_ports[2].bits.uop.is_rvc connect slots_4.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[4].wakeup_ports[2].bits.uop.debug_inst connect slots_4.io.wakeup_ports[2].bits.uop.inst, issue_slots[4].wakeup_ports[2].bits.uop.inst connect slots_4.io.wakeup_ports[2].valid, issue_slots[4].wakeup_ports[2].valid connect slots_4.io.wakeup_ports[3].bits.rebusy, issue_slots[4].wakeup_ports[3].bits.rebusy connect slots_4.io.wakeup_ports[3].bits.speculative_mask, issue_slots[4].wakeup_ports[3].bits.speculative_mask connect slots_4.io.wakeup_ports[3].bits.bypassable, issue_slots[4].wakeup_ports[3].bits.bypassable connect slots_4.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[3].bits.uop.debug_tsrc connect slots_4.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[3].bits.uop.debug_fsrc connect slots_4.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_4.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[3].bits.uop.bp_debug_if connect slots_4.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_4.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_4.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_4.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[4].wakeup_ports[3].bits.uop.fp_typ connect slots_4.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[4].wakeup_ports[3].bits.uop.fp_rm connect slots_4.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[4].wakeup_ports[3].bits.uop.fp_val connect slots_4.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[4].wakeup_ports[3].bits.uop.fcn_op connect slots_4.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[3].bits.uop.fcn_dw connect slots_4.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[4].wakeup_ports[3].bits.uop.frs3_en connect slots_4.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_4.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_4.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[3].bits.uop.dst_rtype connect slots_4.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[4].wakeup_ports[3].bits.uop.lrs3 connect slots_4.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[4].wakeup_ports[3].bits.uop.lrs2 connect slots_4.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[4].wakeup_ports[3].bits.uop.lrs1 connect slots_4.io.wakeup_ports[3].bits.uop.ldst, issue_slots[4].wakeup_ports[3].bits.uop.ldst connect slots_4.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_4.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[3].bits.uop.csr_cmd connect slots_4.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[3].bits.uop.flush_on_commit connect slots_4.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[4].wakeup_ports[3].bits.uop.is_unique connect slots_4.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[4].wakeup_ports[3].bits.uop.uses_stq connect slots_4.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[3].bits.uop.uses_ldq connect slots_4.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[4].wakeup_ports[3].bits.uop.mem_signed connect slots_4.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[4].wakeup_ports[3].bits.uop.mem_size connect slots_4.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[3].bits.uop.mem_cmd connect slots_4.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[4].wakeup_ports[3].bits.uop.exc_cause connect slots_4.io.wakeup_ports[3].bits.uop.exception, issue_slots[4].wakeup_ports[3].bits.uop.exception connect slots_4.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[3].bits.uop.stale_pdst connect slots_4.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[3].bits.uop.ppred_busy connect slots_4.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[3].bits.uop.prs3_busy connect slots_4.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[3].bits.uop.prs2_busy connect slots_4.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[3].bits.uop.prs1_busy connect slots_4.io.wakeup_ports[3].bits.uop.ppred, issue_slots[4].wakeup_ports[3].bits.uop.ppred connect slots_4.io.wakeup_ports[3].bits.uop.prs3, issue_slots[4].wakeup_ports[3].bits.uop.prs3 connect slots_4.io.wakeup_ports[3].bits.uop.prs2, issue_slots[4].wakeup_ports[3].bits.uop.prs2 connect slots_4.io.wakeup_ports[3].bits.uop.prs1, issue_slots[4].wakeup_ports[3].bits.uop.prs1 connect slots_4.io.wakeup_ports[3].bits.uop.pdst, issue_slots[4].wakeup_ports[3].bits.uop.pdst connect slots_4.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[3].bits.uop.rxq_idx connect slots_4.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[4].wakeup_ports[3].bits.uop.stq_idx connect slots_4.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[3].bits.uop.ldq_idx connect slots_4.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[4].wakeup_ports[3].bits.uop.rob_idx connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_4.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[4].wakeup_ports[3].bits.uop.op2_sel connect slots_4.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[4].wakeup_ports[3].bits.uop.op1_sel connect slots_4.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[4].wakeup_ports[3].bits.uop.imm_packed connect slots_4.io.wakeup_ports[3].bits.uop.pimm, issue_slots[4].wakeup_ports[3].bits.uop.pimm connect slots_4.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[4].wakeup_ports[3].bits.uop.imm_sel connect slots_4.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[4].wakeup_ports[3].bits.uop.imm_rename connect slots_4.io.wakeup_ports[3].bits.uop.taken, issue_slots[4].wakeup_ports[3].bits.uop.taken connect slots_4.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[4].wakeup_ports[3].bits.uop.pc_lob connect slots_4.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[4].wakeup_ports[3].bits.uop.edge_inst connect slots_4.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[3].bits.uop.ftq_idx connect slots_4.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[4].wakeup_ports[3].bits.uop.is_mov connect slots_4.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[4].wakeup_ports[3].bits.uop.is_rocc connect slots_4.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_4.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[4].wakeup_ports[3].bits.uop.is_eret connect slots_4.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[4].wakeup_ports[3].bits.uop.is_amo connect slots_4.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[4].wakeup_ports[3].bits.uop.is_sfence connect slots_4.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[4].wakeup_ports[3].bits.uop.is_fencei connect slots_4.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[4].wakeup_ports[3].bits.uop.is_fence connect slots_4.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[4].wakeup_ports[3].bits.uop.is_sfb connect slots_4.io.wakeup_ports[3].bits.uop.br_type, issue_slots[4].wakeup_ports[3].bits.uop.br_type connect slots_4.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[4].wakeup_ports[3].bits.uop.br_tag connect slots_4.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[4].wakeup_ports[3].bits.uop.br_mask connect slots_4.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[3].bits.uop.dis_col_sel connect slots_4.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_4.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_4.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_4.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_4.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_4.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_4.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_4.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[4].wakeup_ports[3].bits.uop.iw_issued connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[0] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[1] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[2] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[3] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[4] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[5] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[6] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[7] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[8] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[9] connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[0] connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[1] connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[2] connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[3] connect slots_4.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[4].wakeup_ports[3].bits.uop.debug_pc connect slots_4.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[4].wakeup_ports[3].bits.uop.is_rvc connect slots_4.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[4].wakeup_ports[3].bits.uop.debug_inst connect slots_4.io.wakeup_ports[3].bits.uop.inst, issue_slots[4].wakeup_ports[3].bits.uop.inst connect slots_4.io.wakeup_ports[3].valid, issue_slots[4].wakeup_ports[3].valid connect slots_4.io.wakeup_ports[4].bits.rebusy, issue_slots[4].wakeup_ports[4].bits.rebusy connect slots_4.io.wakeup_ports[4].bits.speculative_mask, issue_slots[4].wakeup_ports[4].bits.speculative_mask connect slots_4.io.wakeup_ports[4].bits.bypassable, issue_slots[4].wakeup_ports[4].bits.bypassable connect slots_4.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[4].bits.uop.debug_tsrc connect slots_4.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[4].bits.uop.debug_fsrc connect slots_4.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_4.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[4].bits.uop.bp_debug_if connect slots_4.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_4.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_4.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_4.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[4].wakeup_ports[4].bits.uop.fp_typ connect slots_4.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[4].wakeup_ports[4].bits.uop.fp_rm connect slots_4.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[4].wakeup_ports[4].bits.uop.fp_val connect slots_4.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[4].wakeup_ports[4].bits.uop.fcn_op connect slots_4.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[4].bits.uop.fcn_dw connect slots_4.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[4].wakeup_ports[4].bits.uop.frs3_en connect slots_4.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_4.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_4.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[4].bits.uop.dst_rtype connect slots_4.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[4].wakeup_ports[4].bits.uop.lrs3 connect slots_4.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[4].wakeup_ports[4].bits.uop.lrs2 connect slots_4.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[4].wakeup_ports[4].bits.uop.lrs1 connect slots_4.io.wakeup_ports[4].bits.uop.ldst, issue_slots[4].wakeup_ports[4].bits.uop.ldst connect slots_4.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_4.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[4].bits.uop.csr_cmd connect slots_4.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[4].bits.uop.flush_on_commit connect slots_4.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[4].wakeup_ports[4].bits.uop.is_unique connect slots_4.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[4].wakeup_ports[4].bits.uop.uses_stq connect slots_4.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[4].bits.uop.uses_ldq connect slots_4.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[4].wakeup_ports[4].bits.uop.mem_signed connect slots_4.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[4].wakeup_ports[4].bits.uop.mem_size connect slots_4.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[4].bits.uop.mem_cmd connect slots_4.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[4].wakeup_ports[4].bits.uop.exc_cause connect slots_4.io.wakeup_ports[4].bits.uop.exception, issue_slots[4].wakeup_ports[4].bits.uop.exception connect slots_4.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[4].bits.uop.stale_pdst connect slots_4.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[4].bits.uop.ppred_busy connect slots_4.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[4].bits.uop.prs3_busy connect slots_4.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[4].bits.uop.prs2_busy connect slots_4.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[4].bits.uop.prs1_busy connect slots_4.io.wakeup_ports[4].bits.uop.ppred, issue_slots[4].wakeup_ports[4].bits.uop.ppred connect slots_4.io.wakeup_ports[4].bits.uop.prs3, issue_slots[4].wakeup_ports[4].bits.uop.prs3 connect slots_4.io.wakeup_ports[4].bits.uop.prs2, issue_slots[4].wakeup_ports[4].bits.uop.prs2 connect slots_4.io.wakeup_ports[4].bits.uop.prs1, issue_slots[4].wakeup_ports[4].bits.uop.prs1 connect slots_4.io.wakeup_ports[4].bits.uop.pdst, issue_slots[4].wakeup_ports[4].bits.uop.pdst connect slots_4.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[4].bits.uop.rxq_idx connect slots_4.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[4].wakeup_ports[4].bits.uop.stq_idx connect slots_4.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[4].bits.uop.ldq_idx connect slots_4.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[4].wakeup_ports[4].bits.uop.rob_idx connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_4.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[4].wakeup_ports[4].bits.uop.op2_sel connect slots_4.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[4].wakeup_ports[4].bits.uop.op1_sel connect slots_4.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[4].wakeup_ports[4].bits.uop.imm_packed connect slots_4.io.wakeup_ports[4].bits.uop.pimm, issue_slots[4].wakeup_ports[4].bits.uop.pimm connect slots_4.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[4].wakeup_ports[4].bits.uop.imm_sel connect slots_4.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[4].wakeup_ports[4].bits.uop.imm_rename connect slots_4.io.wakeup_ports[4].bits.uop.taken, issue_slots[4].wakeup_ports[4].bits.uop.taken connect slots_4.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[4].wakeup_ports[4].bits.uop.pc_lob connect slots_4.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[4].wakeup_ports[4].bits.uop.edge_inst connect slots_4.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[4].bits.uop.ftq_idx connect slots_4.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[4].wakeup_ports[4].bits.uop.is_mov connect slots_4.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[4].wakeup_ports[4].bits.uop.is_rocc connect slots_4.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_4.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[4].wakeup_ports[4].bits.uop.is_eret connect slots_4.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[4].wakeup_ports[4].bits.uop.is_amo connect slots_4.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[4].wakeup_ports[4].bits.uop.is_sfence connect slots_4.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[4].wakeup_ports[4].bits.uop.is_fencei connect slots_4.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[4].wakeup_ports[4].bits.uop.is_fence connect slots_4.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[4].wakeup_ports[4].bits.uop.is_sfb connect slots_4.io.wakeup_ports[4].bits.uop.br_type, issue_slots[4].wakeup_ports[4].bits.uop.br_type connect slots_4.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[4].wakeup_ports[4].bits.uop.br_tag connect slots_4.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[4].wakeup_ports[4].bits.uop.br_mask connect slots_4.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[4].bits.uop.dis_col_sel connect slots_4.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_4.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_4.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_4.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_4.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_4.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_4.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_4.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[4].wakeup_ports[4].bits.uop.iw_issued connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[0] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[1] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[2] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[3] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[4] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[5] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[6] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[7] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[8] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[9] connect slots_4.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[4].bits.uop.iq_type[0] connect slots_4.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[4].bits.uop.iq_type[1] connect slots_4.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[4].bits.uop.iq_type[2] connect slots_4.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[4].bits.uop.iq_type[3] connect slots_4.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[4].wakeup_ports[4].bits.uop.debug_pc connect slots_4.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[4].wakeup_ports[4].bits.uop.is_rvc connect slots_4.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[4].wakeup_ports[4].bits.uop.debug_inst connect slots_4.io.wakeup_ports[4].bits.uop.inst, issue_slots[4].wakeup_ports[4].bits.uop.inst connect slots_4.io.wakeup_ports[4].valid, issue_slots[4].wakeup_ports[4].valid connect slots_4.io.squash_grant, issue_slots[4].squash_grant connect slots_4.io.clear, issue_slots[4].clear connect slots_4.io.kill, issue_slots[4].kill connect slots_4.io.brupdate.b2.target_offset, issue_slots[4].brupdate.b2.target_offset connect slots_4.io.brupdate.b2.jalr_target, issue_slots[4].brupdate.b2.jalr_target connect slots_4.io.brupdate.b2.pc_sel, issue_slots[4].brupdate.b2.pc_sel connect slots_4.io.brupdate.b2.cfi_type, issue_slots[4].brupdate.b2.cfi_type connect slots_4.io.brupdate.b2.taken, issue_slots[4].brupdate.b2.taken connect slots_4.io.brupdate.b2.mispredict, issue_slots[4].brupdate.b2.mispredict connect slots_4.io.brupdate.b2.uop.debug_tsrc, issue_slots[4].brupdate.b2.uop.debug_tsrc connect slots_4.io.brupdate.b2.uop.debug_fsrc, issue_slots[4].brupdate.b2.uop.debug_fsrc connect slots_4.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[4].brupdate.b2.uop.bp_xcpt_if connect slots_4.io.brupdate.b2.uop.bp_debug_if, issue_slots[4].brupdate.b2.uop.bp_debug_if connect slots_4.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[4].brupdate.b2.uop.xcpt_ma_if connect slots_4.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[4].brupdate.b2.uop.xcpt_ae_if connect slots_4.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[4].brupdate.b2.uop.xcpt_pf_if connect slots_4.io.brupdate.b2.uop.fp_typ, issue_slots[4].brupdate.b2.uop.fp_typ connect slots_4.io.brupdate.b2.uop.fp_rm, issue_slots[4].brupdate.b2.uop.fp_rm connect slots_4.io.brupdate.b2.uop.fp_val, issue_slots[4].brupdate.b2.uop.fp_val connect slots_4.io.brupdate.b2.uop.fcn_op, issue_slots[4].brupdate.b2.uop.fcn_op connect slots_4.io.brupdate.b2.uop.fcn_dw, issue_slots[4].brupdate.b2.uop.fcn_dw connect slots_4.io.brupdate.b2.uop.frs3_en, issue_slots[4].brupdate.b2.uop.frs3_en connect slots_4.io.brupdate.b2.uop.lrs2_rtype, issue_slots[4].brupdate.b2.uop.lrs2_rtype connect slots_4.io.brupdate.b2.uop.lrs1_rtype, issue_slots[4].brupdate.b2.uop.lrs1_rtype connect slots_4.io.brupdate.b2.uop.dst_rtype, issue_slots[4].brupdate.b2.uop.dst_rtype connect slots_4.io.brupdate.b2.uop.lrs3, issue_slots[4].brupdate.b2.uop.lrs3 connect slots_4.io.brupdate.b2.uop.lrs2, issue_slots[4].brupdate.b2.uop.lrs2 connect slots_4.io.brupdate.b2.uop.lrs1, issue_slots[4].brupdate.b2.uop.lrs1 connect slots_4.io.brupdate.b2.uop.ldst, issue_slots[4].brupdate.b2.uop.ldst connect slots_4.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[4].brupdate.b2.uop.ldst_is_rs1 connect slots_4.io.brupdate.b2.uop.csr_cmd, issue_slots[4].brupdate.b2.uop.csr_cmd connect slots_4.io.brupdate.b2.uop.flush_on_commit, issue_slots[4].brupdate.b2.uop.flush_on_commit connect slots_4.io.brupdate.b2.uop.is_unique, issue_slots[4].brupdate.b2.uop.is_unique connect slots_4.io.brupdate.b2.uop.uses_stq, issue_slots[4].brupdate.b2.uop.uses_stq connect slots_4.io.brupdate.b2.uop.uses_ldq, issue_slots[4].brupdate.b2.uop.uses_ldq connect slots_4.io.brupdate.b2.uop.mem_signed, issue_slots[4].brupdate.b2.uop.mem_signed connect slots_4.io.brupdate.b2.uop.mem_size, issue_slots[4].brupdate.b2.uop.mem_size connect slots_4.io.brupdate.b2.uop.mem_cmd, issue_slots[4].brupdate.b2.uop.mem_cmd connect slots_4.io.brupdate.b2.uop.exc_cause, issue_slots[4].brupdate.b2.uop.exc_cause connect slots_4.io.brupdate.b2.uop.exception, issue_slots[4].brupdate.b2.uop.exception connect slots_4.io.brupdate.b2.uop.stale_pdst, issue_slots[4].brupdate.b2.uop.stale_pdst connect slots_4.io.brupdate.b2.uop.ppred_busy, issue_slots[4].brupdate.b2.uop.ppred_busy connect slots_4.io.brupdate.b2.uop.prs3_busy, issue_slots[4].brupdate.b2.uop.prs3_busy connect slots_4.io.brupdate.b2.uop.prs2_busy, issue_slots[4].brupdate.b2.uop.prs2_busy connect slots_4.io.brupdate.b2.uop.prs1_busy, issue_slots[4].brupdate.b2.uop.prs1_busy connect slots_4.io.brupdate.b2.uop.ppred, issue_slots[4].brupdate.b2.uop.ppred connect slots_4.io.brupdate.b2.uop.prs3, issue_slots[4].brupdate.b2.uop.prs3 connect slots_4.io.brupdate.b2.uop.prs2, issue_slots[4].brupdate.b2.uop.prs2 connect slots_4.io.brupdate.b2.uop.prs1, issue_slots[4].brupdate.b2.uop.prs1 connect slots_4.io.brupdate.b2.uop.pdst, issue_slots[4].brupdate.b2.uop.pdst connect slots_4.io.brupdate.b2.uop.rxq_idx, issue_slots[4].brupdate.b2.uop.rxq_idx connect slots_4.io.brupdate.b2.uop.stq_idx, issue_slots[4].brupdate.b2.uop.stq_idx connect slots_4.io.brupdate.b2.uop.ldq_idx, issue_slots[4].brupdate.b2.uop.ldq_idx connect slots_4.io.brupdate.b2.uop.rob_idx, issue_slots[4].brupdate.b2.uop.rob_idx connect slots_4.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[4].brupdate.b2.uop.fp_ctrl.vec connect slots_4.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[4].brupdate.b2.uop.fp_ctrl.wflags connect slots_4.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[4].brupdate.b2.uop.fp_ctrl.sqrt connect slots_4.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[4].brupdate.b2.uop.fp_ctrl.div connect slots_4.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[4].brupdate.b2.uop.fp_ctrl.fma connect slots_4.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[4].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_4.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[4].brupdate.b2.uop.fp_ctrl.toint connect slots_4.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[4].brupdate.b2.uop.fp_ctrl.fromint connect slots_4.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_4.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_4.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[4].brupdate.b2.uop.fp_ctrl.swap23 connect slots_4.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[4].brupdate.b2.uop.fp_ctrl.swap12 connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren3 connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren2 connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren1 connect slots_4.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[4].brupdate.b2.uop.fp_ctrl.wen connect slots_4.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[4].brupdate.b2.uop.fp_ctrl.ldst connect slots_4.io.brupdate.b2.uop.op2_sel, issue_slots[4].brupdate.b2.uop.op2_sel connect slots_4.io.brupdate.b2.uop.op1_sel, issue_slots[4].brupdate.b2.uop.op1_sel connect slots_4.io.brupdate.b2.uop.imm_packed, issue_slots[4].brupdate.b2.uop.imm_packed connect slots_4.io.brupdate.b2.uop.pimm, issue_slots[4].brupdate.b2.uop.pimm connect slots_4.io.brupdate.b2.uop.imm_sel, issue_slots[4].brupdate.b2.uop.imm_sel connect slots_4.io.brupdate.b2.uop.imm_rename, issue_slots[4].brupdate.b2.uop.imm_rename connect slots_4.io.brupdate.b2.uop.taken, issue_slots[4].brupdate.b2.uop.taken connect slots_4.io.brupdate.b2.uop.pc_lob, issue_slots[4].brupdate.b2.uop.pc_lob connect slots_4.io.brupdate.b2.uop.edge_inst, issue_slots[4].brupdate.b2.uop.edge_inst connect slots_4.io.brupdate.b2.uop.ftq_idx, issue_slots[4].brupdate.b2.uop.ftq_idx connect slots_4.io.brupdate.b2.uop.is_mov, issue_slots[4].brupdate.b2.uop.is_mov connect slots_4.io.brupdate.b2.uop.is_rocc, issue_slots[4].brupdate.b2.uop.is_rocc connect slots_4.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[4].brupdate.b2.uop.is_sys_pc2epc connect slots_4.io.brupdate.b2.uop.is_eret, issue_slots[4].brupdate.b2.uop.is_eret connect slots_4.io.brupdate.b2.uop.is_amo, issue_slots[4].brupdate.b2.uop.is_amo connect slots_4.io.brupdate.b2.uop.is_sfence, issue_slots[4].brupdate.b2.uop.is_sfence connect slots_4.io.brupdate.b2.uop.is_fencei, issue_slots[4].brupdate.b2.uop.is_fencei connect slots_4.io.brupdate.b2.uop.is_fence, issue_slots[4].brupdate.b2.uop.is_fence connect slots_4.io.brupdate.b2.uop.is_sfb, issue_slots[4].brupdate.b2.uop.is_sfb connect slots_4.io.brupdate.b2.uop.br_type, issue_slots[4].brupdate.b2.uop.br_type connect slots_4.io.brupdate.b2.uop.br_tag, issue_slots[4].brupdate.b2.uop.br_tag connect slots_4.io.brupdate.b2.uop.br_mask, issue_slots[4].brupdate.b2.uop.br_mask connect slots_4.io.brupdate.b2.uop.dis_col_sel, issue_slots[4].brupdate.b2.uop.dis_col_sel connect slots_4.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p3_bypass_hint connect slots_4.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p2_bypass_hint connect slots_4.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p1_bypass_hint connect slots_4.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[4].brupdate.b2.uop.iw_p2_speculative_child connect slots_4.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[4].brupdate.b2.uop.iw_p1_speculative_child connect slots_4.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[4].brupdate.b2.uop.iw_issued_partial_dgen connect slots_4.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[4].brupdate.b2.uop.iw_issued_partial_agen connect slots_4.io.brupdate.b2.uop.iw_issued, issue_slots[4].brupdate.b2.uop.iw_issued connect slots_4.io.brupdate.b2.uop.fu_code[0], issue_slots[4].brupdate.b2.uop.fu_code[0] connect slots_4.io.brupdate.b2.uop.fu_code[1], issue_slots[4].brupdate.b2.uop.fu_code[1] connect slots_4.io.brupdate.b2.uop.fu_code[2], issue_slots[4].brupdate.b2.uop.fu_code[2] connect slots_4.io.brupdate.b2.uop.fu_code[3], issue_slots[4].brupdate.b2.uop.fu_code[3] connect slots_4.io.brupdate.b2.uop.fu_code[4], issue_slots[4].brupdate.b2.uop.fu_code[4] connect slots_4.io.brupdate.b2.uop.fu_code[5], issue_slots[4].brupdate.b2.uop.fu_code[5] connect slots_4.io.brupdate.b2.uop.fu_code[6], issue_slots[4].brupdate.b2.uop.fu_code[6] connect slots_4.io.brupdate.b2.uop.fu_code[7], issue_slots[4].brupdate.b2.uop.fu_code[7] connect slots_4.io.brupdate.b2.uop.fu_code[8], issue_slots[4].brupdate.b2.uop.fu_code[8] connect slots_4.io.brupdate.b2.uop.fu_code[9], issue_slots[4].brupdate.b2.uop.fu_code[9] connect slots_4.io.brupdate.b2.uop.iq_type[0], issue_slots[4].brupdate.b2.uop.iq_type[0] connect slots_4.io.brupdate.b2.uop.iq_type[1], issue_slots[4].brupdate.b2.uop.iq_type[1] connect slots_4.io.brupdate.b2.uop.iq_type[2], issue_slots[4].brupdate.b2.uop.iq_type[2] connect slots_4.io.brupdate.b2.uop.iq_type[3], issue_slots[4].brupdate.b2.uop.iq_type[3] connect slots_4.io.brupdate.b2.uop.debug_pc, issue_slots[4].brupdate.b2.uop.debug_pc connect slots_4.io.brupdate.b2.uop.is_rvc, issue_slots[4].brupdate.b2.uop.is_rvc connect slots_4.io.brupdate.b2.uop.debug_inst, issue_slots[4].brupdate.b2.uop.debug_inst connect slots_4.io.brupdate.b2.uop.inst, issue_slots[4].brupdate.b2.uop.inst connect slots_4.io.brupdate.b1.mispredict_mask, issue_slots[4].brupdate.b1.mispredict_mask connect slots_4.io.brupdate.b1.resolve_mask, issue_slots[4].brupdate.b1.resolve_mask connect issue_slots[4].out_uop.debug_tsrc, slots_4.io.out_uop.debug_tsrc connect issue_slots[4].out_uop.debug_fsrc, slots_4.io.out_uop.debug_fsrc connect issue_slots[4].out_uop.bp_xcpt_if, slots_4.io.out_uop.bp_xcpt_if connect issue_slots[4].out_uop.bp_debug_if, slots_4.io.out_uop.bp_debug_if connect issue_slots[4].out_uop.xcpt_ma_if, slots_4.io.out_uop.xcpt_ma_if connect issue_slots[4].out_uop.xcpt_ae_if, slots_4.io.out_uop.xcpt_ae_if connect issue_slots[4].out_uop.xcpt_pf_if, slots_4.io.out_uop.xcpt_pf_if connect issue_slots[4].out_uop.fp_typ, slots_4.io.out_uop.fp_typ connect issue_slots[4].out_uop.fp_rm, slots_4.io.out_uop.fp_rm connect issue_slots[4].out_uop.fp_val, slots_4.io.out_uop.fp_val connect issue_slots[4].out_uop.fcn_op, slots_4.io.out_uop.fcn_op connect issue_slots[4].out_uop.fcn_dw, slots_4.io.out_uop.fcn_dw connect issue_slots[4].out_uop.frs3_en, slots_4.io.out_uop.frs3_en connect issue_slots[4].out_uop.lrs2_rtype, slots_4.io.out_uop.lrs2_rtype connect issue_slots[4].out_uop.lrs1_rtype, slots_4.io.out_uop.lrs1_rtype connect issue_slots[4].out_uop.dst_rtype, slots_4.io.out_uop.dst_rtype connect issue_slots[4].out_uop.lrs3, slots_4.io.out_uop.lrs3 connect issue_slots[4].out_uop.lrs2, slots_4.io.out_uop.lrs2 connect issue_slots[4].out_uop.lrs1, slots_4.io.out_uop.lrs1 connect issue_slots[4].out_uop.ldst, slots_4.io.out_uop.ldst connect issue_slots[4].out_uop.ldst_is_rs1, slots_4.io.out_uop.ldst_is_rs1 connect issue_slots[4].out_uop.csr_cmd, slots_4.io.out_uop.csr_cmd connect issue_slots[4].out_uop.flush_on_commit, slots_4.io.out_uop.flush_on_commit connect issue_slots[4].out_uop.is_unique, slots_4.io.out_uop.is_unique connect issue_slots[4].out_uop.uses_stq, slots_4.io.out_uop.uses_stq connect issue_slots[4].out_uop.uses_ldq, slots_4.io.out_uop.uses_ldq connect issue_slots[4].out_uop.mem_signed, slots_4.io.out_uop.mem_signed connect issue_slots[4].out_uop.mem_size, slots_4.io.out_uop.mem_size connect issue_slots[4].out_uop.mem_cmd, slots_4.io.out_uop.mem_cmd connect issue_slots[4].out_uop.exc_cause, slots_4.io.out_uop.exc_cause connect issue_slots[4].out_uop.exception, slots_4.io.out_uop.exception connect issue_slots[4].out_uop.stale_pdst, slots_4.io.out_uop.stale_pdst connect issue_slots[4].out_uop.ppred_busy, slots_4.io.out_uop.ppred_busy connect issue_slots[4].out_uop.prs3_busy, slots_4.io.out_uop.prs3_busy connect issue_slots[4].out_uop.prs2_busy, slots_4.io.out_uop.prs2_busy connect issue_slots[4].out_uop.prs1_busy, slots_4.io.out_uop.prs1_busy connect issue_slots[4].out_uop.ppred, slots_4.io.out_uop.ppred connect issue_slots[4].out_uop.prs3, slots_4.io.out_uop.prs3 connect issue_slots[4].out_uop.prs2, slots_4.io.out_uop.prs2 connect issue_slots[4].out_uop.prs1, slots_4.io.out_uop.prs1 connect issue_slots[4].out_uop.pdst, slots_4.io.out_uop.pdst connect issue_slots[4].out_uop.rxq_idx, slots_4.io.out_uop.rxq_idx connect issue_slots[4].out_uop.stq_idx, slots_4.io.out_uop.stq_idx connect issue_slots[4].out_uop.ldq_idx, slots_4.io.out_uop.ldq_idx connect issue_slots[4].out_uop.rob_idx, slots_4.io.out_uop.rob_idx connect issue_slots[4].out_uop.fp_ctrl.vec, slots_4.io.out_uop.fp_ctrl.vec connect issue_slots[4].out_uop.fp_ctrl.wflags, slots_4.io.out_uop.fp_ctrl.wflags connect issue_slots[4].out_uop.fp_ctrl.sqrt, slots_4.io.out_uop.fp_ctrl.sqrt connect issue_slots[4].out_uop.fp_ctrl.div, slots_4.io.out_uop.fp_ctrl.div connect issue_slots[4].out_uop.fp_ctrl.fma, slots_4.io.out_uop.fp_ctrl.fma connect issue_slots[4].out_uop.fp_ctrl.fastpipe, slots_4.io.out_uop.fp_ctrl.fastpipe connect issue_slots[4].out_uop.fp_ctrl.toint, slots_4.io.out_uop.fp_ctrl.toint connect issue_slots[4].out_uop.fp_ctrl.fromint, slots_4.io.out_uop.fp_ctrl.fromint connect issue_slots[4].out_uop.fp_ctrl.typeTagOut, slots_4.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[4].out_uop.fp_ctrl.typeTagIn, slots_4.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[4].out_uop.fp_ctrl.swap23, slots_4.io.out_uop.fp_ctrl.swap23 connect issue_slots[4].out_uop.fp_ctrl.swap12, slots_4.io.out_uop.fp_ctrl.swap12 connect issue_slots[4].out_uop.fp_ctrl.ren3, slots_4.io.out_uop.fp_ctrl.ren3 connect issue_slots[4].out_uop.fp_ctrl.ren2, slots_4.io.out_uop.fp_ctrl.ren2 connect issue_slots[4].out_uop.fp_ctrl.ren1, slots_4.io.out_uop.fp_ctrl.ren1 connect issue_slots[4].out_uop.fp_ctrl.wen, slots_4.io.out_uop.fp_ctrl.wen connect issue_slots[4].out_uop.fp_ctrl.ldst, slots_4.io.out_uop.fp_ctrl.ldst connect issue_slots[4].out_uop.op2_sel, slots_4.io.out_uop.op2_sel connect issue_slots[4].out_uop.op1_sel, slots_4.io.out_uop.op1_sel connect issue_slots[4].out_uop.imm_packed, slots_4.io.out_uop.imm_packed connect issue_slots[4].out_uop.pimm, slots_4.io.out_uop.pimm connect issue_slots[4].out_uop.imm_sel, slots_4.io.out_uop.imm_sel connect issue_slots[4].out_uop.imm_rename, slots_4.io.out_uop.imm_rename connect issue_slots[4].out_uop.taken, slots_4.io.out_uop.taken connect issue_slots[4].out_uop.pc_lob, slots_4.io.out_uop.pc_lob connect issue_slots[4].out_uop.edge_inst, slots_4.io.out_uop.edge_inst connect issue_slots[4].out_uop.ftq_idx, slots_4.io.out_uop.ftq_idx connect issue_slots[4].out_uop.is_mov, slots_4.io.out_uop.is_mov connect issue_slots[4].out_uop.is_rocc, slots_4.io.out_uop.is_rocc connect issue_slots[4].out_uop.is_sys_pc2epc, slots_4.io.out_uop.is_sys_pc2epc connect issue_slots[4].out_uop.is_eret, slots_4.io.out_uop.is_eret connect issue_slots[4].out_uop.is_amo, slots_4.io.out_uop.is_amo connect issue_slots[4].out_uop.is_sfence, slots_4.io.out_uop.is_sfence connect issue_slots[4].out_uop.is_fencei, slots_4.io.out_uop.is_fencei connect issue_slots[4].out_uop.is_fence, slots_4.io.out_uop.is_fence connect issue_slots[4].out_uop.is_sfb, slots_4.io.out_uop.is_sfb connect issue_slots[4].out_uop.br_type, slots_4.io.out_uop.br_type connect issue_slots[4].out_uop.br_tag, slots_4.io.out_uop.br_tag connect issue_slots[4].out_uop.br_mask, slots_4.io.out_uop.br_mask connect issue_slots[4].out_uop.dis_col_sel, slots_4.io.out_uop.dis_col_sel connect issue_slots[4].out_uop.iw_p3_bypass_hint, slots_4.io.out_uop.iw_p3_bypass_hint connect issue_slots[4].out_uop.iw_p2_bypass_hint, slots_4.io.out_uop.iw_p2_bypass_hint connect issue_slots[4].out_uop.iw_p1_bypass_hint, slots_4.io.out_uop.iw_p1_bypass_hint connect issue_slots[4].out_uop.iw_p2_speculative_child, slots_4.io.out_uop.iw_p2_speculative_child connect issue_slots[4].out_uop.iw_p1_speculative_child, slots_4.io.out_uop.iw_p1_speculative_child connect issue_slots[4].out_uop.iw_issued_partial_dgen, slots_4.io.out_uop.iw_issued_partial_dgen connect issue_slots[4].out_uop.iw_issued_partial_agen, slots_4.io.out_uop.iw_issued_partial_agen connect issue_slots[4].out_uop.iw_issued, slots_4.io.out_uop.iw_issued connect issue_slots[4].out_uop.fu_code[0], slots_4.io.out_uop.fu_code[0] connect issue_slots[4].out_uop.fu_code[1], slots_4.io.out_uop.fu_code[1] connect issue_slots[4].out_uop.fu_code[2], slots_4.io.out_uop.fu_code[2] connect issue_slots[4].out_uop.fu_code[3], slots_4.io.out_uop.fu_code[3] connect issue_slots[4].out_uop.fu_code[4], slots_4.io.out_uop.fu_code[4] connect issue_slots[4].out_uop.fu_code[5], slots_4.io.out_uop.fu_code[5] connect issue_slots[4].out_uop.fu_code[6], slots_4.io.out_uop.fu_code[6] connect issue_slots[4].out_uop.fu_code[7], slots_4.io.out_uop.fu_code[7] connect issue_slots[4].out_uop.fu_code[8], slots_4.io.out_uop.fu_code[8] connect issue_slots[4].out_uop.fu_code[9], slots_4.io.out_uop.fu_code[9] connect issue_slots[4].out_uop.iq_type[0], slots_4.io.out_uop.iq_type[0] connect issue_slots[4].out_uop.iq_type[1], slots_4.io.out_uop.iq_type[1] connect issue_slots[4].out_uop.iq_type[2], slots_4.io.out_uop.iq_type[2] connect issue_slots[4].out_uop.iq_type[3], slots_4.io.out_uop.iq_type[3] connect issue_slots[4].out_uop.debug_pc, slots_4.io.out_uop.debug_pc connect issue_slots[4].out_uop.is_rvc, slots_4.io.out_uop.is_rvc connect issue_slots[4].out_uop.debug_inst, slots_4.io.out_uop.debug_inst connect issue_slots[4].out_uop.inst, slots_4.io.out_uop.inst connect slots_4.io.in_uop.bits.debug_tsrc, issue_slots[4].in_uop.bits.debug_tsrc connect slots_4.io.in_uop.bits.debug_fsrc, issue_slots[4].in_uop.bits.debug_fsrc connect slots_4.io.in_uop.bits.bp_xcpt_if, issue_slots[4].in_uop.bits.bp_xcpt_if connect slots_4.io.in_uop.bits.bp_debug_if, issue_slots[4].in_uop.bits.bp_debug_if connect slots_4.io.in_uop.bits.xcpt_ma_if, issue_slots[4].in_uop.bits.xcpt_ma_if connect slots_4.io.in_uop.bits.xcpt_ae_if, issue_slots[4].in_uop.bits.xcpt_ae_if connect slots_4.io.in_uop.bits.xcpt_pf_if, issue_slots[4].in_uop.bits.xcpt_pf_if connect slots_4.io.in_uop.bits.fp_typ, issue_slots[4].in_uop.bits.fp_typ connect slots_4.io.in_uop.bits.fp_rm, issue_slots[4].in_uop.bits.fp_rm connect slots_4.io.in_uop.bits.fp_val, issue_slots[4].in_uop.bits.fp_val connect slots_4.io.in_uop.bits.fcn_op, issue_slots[4].in_uop.bits.fcn_op connect slots_4.io.in_uop.bits.fcn_dw, issue_slots[4].in_uop.bits.fcn_dw connect slots_4.io.in_uop.bits.frs3_en, issue_slots[4].in_uop.bits.frs3_en connect slots_4.io.in_uop.bits.lrs2_rtype, issue_slots[4].in_uop.bits.lrs2_rtype connect slots_4.io.in_uop.bits.lrs1_rtype, issue_slots[4].in_uop.bits.lrs1_rtype connect slots_4.io.in_uop.bits.dst_rtype, issue_slots[4].in_uop.bits.dst_rtype connect slots_4.io.in_uop.bits.lrs3, issue_slots[4].in_uop.bits.lrs3 connect slots_4.io.in_uop.bits.lrs2, issue_slots[4].in_uop.bits.lrs2 connect slots_4.io.in_uop.bits.lrs1, issue_slots[4].in_uop.bits.lrs1 connect slots_4.io.in_uop.bits.ldst, issue_slots[4].in_uop.bits.ldst connect slots_4.io.in_uop.bits.ldst_is_rs1, issue_slots[4].in_uop.bits.ldst_is_rs1 connect slots_4.io.in_uop.bits.csr_cmd, issue_slots[4].in_uop.bits.csr_cmd connect slots_4.io.in_uop.bits.flush_on_commit, issue_slots[4].in_uop.bits.flush_on_commit connect slots_4.io.in_uop.bits.is_unique, issue_slots[4].in_uop.bits.is_unique connect slots_4.io.in_uop.bits.uses_stq, issue_slots[4].in_uop.bits.uses_stq connect slots_4.io.in_uop.bits.uses_ldq, issue_slots[4].in_uop.bits.uses_ldq connect slots_4.io.in_uop.bits.mem_signed, issue_slots[4].in_uop.bits.mem_signed connect slots_4.io.in_uop.bits.mem_size, issue_slots[4].in_uop.bits.mem_size connect slots_4.io.in_uop.bits.mem_cmd, issue_slots[4].in_uop.bits.mem_cmd connect slots_4.io.in_uop.bits.exc_cause, issue_slots[4].in_uop.bits.exc_cause connect slots_4.io.in_uop.bits.exception, issue_slots[4].in_uop.bits.exception connect slots_4.io.in_uop.bits.stale_pdst, issue_slots[4].in_uop.bits.stale_pdst connect slots_4.io.in_uop.bits.ppred_busy, issue_slots[4].in_uop.bits.ppred_busy connect slots_4.io.in_uop.bits.prs3_busy, issue_slots[4].in_uop.bits.prs3_busy connect slots_4.io.in_uop.bits.prs2_busy, issue_slots[4].in_uop.bits.prs2_busy connect slots_4.io.in_uop.bits.prs1_busy, issue_slots[4].in_uop.bits.prs1_busy connect slots_4.io.in_uop.bits.ppred, issue_slots[4].in_uop.bits.ppred connect slots_4.io.in_uop.bits.prs3, issue_slots[4].in_uop.bits.prs3 connect slots_4.io.in_uop.bits.prs2, issue_slots[4].in_uop.bits.prs2 connect slots_4.io.in_uop.bits.prs1, issue_slots[4].in_uop.bits.prs1 connect slots_4.io.in_uop.bits.pdst, issue_slots[4].in_uop.bits.pdst connect slots_4.io.in_uop.bits.rxq_idx, issue_slots[4].in_uop.bits.rxq_idx connect slots_4.io.in_uop.bits.stq_idx, issue_slots[4].in_uop.bits.stq_idx connect slots_4.io.in_uop.bits.ldq_idx, issue_slots[4].in_uop.bits.ldq_idx connect slots_4.io.in_uop.bits.rob_idx, issue_slots[4].in_uop.bits.rob_idx connect slots_4.io.in_uop.bits.fp_ctrl.vec, issue_slots[4].in_uop.bits.fp_ctrl.vec connect slots_4.io.in_uop.bits.fp_ctrl.wflags, issue_slots[4].in_uop.bits.fp_ctrl.wflags connect slots_4.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[4].in_uop.bits.fp_ctrl.sqrt connect slots_4.io.in_uop.bits.fp_ctrl.div, issue_slots[4].in_uop.bits.fp_ctrl.div connect slots_4.io.in_uop.bits.fp_ctrl.fma, issue_slots[4].in_uop.bits.fp_ctrl.fma connect slots_4.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].in_uop.bits.fp_ctrl.fastpipe connect slots_4.io.in_uop.bits.fp_ctrl.toint, issue_slots[4].in_uop.bits.fp_ctrl.toint connect slots_4.io.in_uop.bits.fp_ctrl.fromint, issue_slots[4].in_uop.bits.fp_ctrl.fromint connect slots_4.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut connect slots_4.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn connect slots_4.io.in_uop.bits.fp_ctrl.swap23, issue_slots[4].in_uop.bits.fp_ctrl.swap23 connect slots_4.io.in_uop.bits.fp_ctrl.swap12, issue_slots[4].in_uop.bits.fp_ctrl.swap12 connect slots_4.io.in_uop.bits.fp_ctrl.ren3, issue_slots[4].in_uop.bits.fp_ctrl.ren3 connect slots_4.io.in_uop.bits.fp_ctrl.ren2, issue_slots[4].in_uop.bits.fp_ctrl.ren2 connect slots_4.io.in_uop.bits.fp_ctrl.ren1, issue_slots[4].in_uop.bits.fp_ctrl.ren1 connect slots_4.io.in_uop.bits.fp_ctrl.wen, issue_slots[4].in_uop.bits.fp_ctrl.wen connect slots_4.io.in_uop.bits.fp_ctrl.ldst, issue_slots[4].in_uop.bits.fp_ctrl.ldst connect slots_4.io.in_uop.bits.op2_sel, issue_slots[4].in_uop.bits.op2_sel connect slots_4.io.in_uop.bits.op1_sel, issue_slots[4].in_uop.bits.op1_sel connect slots_4.io.in_uop.bits.imm_packed, issue_slots[4].in_uop.bits.imm_packed connect slots_4.io.in_uop.bits.pimm, issue_slots[4].in_uop.bits.pimm connect slots_4.io.in_uop.bits.imm_sel, issue_slots[4].in_uop.bits.imm_sel connect slots_4.io.in_uop.bits.imm_rename, issue_slots[4].in_uop.bits.imm_rename connect slots_4.io.in_uop.bits.taken, issue_slots[4].in_uop.bits.taken connect slots_4.io.in_uop.bits.pc_lob, issue_slots[4].in_uop.bits.pc_lob connect slots_4.io.in_uop.bits.edge_inst, issue_slots[4].in_uop.bits.edge_inst connect slots_4.io.in_uop.bits.ftq_idx, issue_slots[4].in_uop.bits.ftq_idx connect slots_4.io.in_uop.bits.is_mov, issue_slots[4].in_uop.bits.is_mov connect slots_4.io.in_uop.bits.is_rocc, issue_slots[4].in_uop.bits.is_rocc connect slots_4.io.in_uop.bits.is_sys_pc2epc, issue_slots[4].in_uop.bits.is_sys_pc2epc connect slots_4.io.in_uop.bits.is_eret, issue_slots[4].in_uop.bits.is_eret connect slots_4.io.in_uop.bits.is_amo, issue_slots[4].in_uop.bits.is_amo connect slots_4.io.in_uop.bits.is_sfence, issue_slots[4].in_uop.bits.is_sfence connect slots_4.io.in_uop.bits.is_fencei, issue_slots[4].in_uop.bits.is_fencei connect slots_4.io.in_uop.bits.is_fence, issue_slots[4].in_uop.bits.is_fence connect slots_4.io.in_uop.bits.is_sfb, issue_slots[4].in_uop.bits.is_sfb connect slots_4.io.in_uop.bits.br_type, issue_slots[4].in_uop.bits.br_type connect slots_4.io.in_uop.bits.br_tag, issue_slots[4].in_uop.bits.br_tag connect slots_4.io.in_uop.bits.br_mask, issue_slots[4].in_uop.bits.br_mask connect slots_4.io.in_uop.bits.dis_col_sel, issue_slots[4].in_uop.bits.dis_col_sel connect slots_4.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[4].in_uop.bits.iw_p3_bypass_hint connect slots_4.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[4].in_uop.bits.iw_p2_bypass_hint connect slots_4.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[4].in_uop.bits.iw_p1_bypass_hint connect slots_4.io.in_uop.bits.iw_p2_speculative_child, issue_slots[4].in_uop.bits.iw_p2_speculative_child connect slots_4.io.in_uop.bits.iw_p1_speculative_child, issue_slots[4].in_uop.bits.iw_p1_speculative_child connect slots_4.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[4].in_uop.bits.iw_issued_partial_dgen connect slots_4.io.in_uop.bits.iw_issued_partial_agen, issue_slots[4].in_uop.bits.iw_issued_partial_agen connect slots_4.io.in_uop.bits.iw_issued, issue_slots[4].in_uop.bits.iw_issued connect slots_4.io.in_uop.bits.fu_code[0], issue_slots[4].in_uop.bits.fu_code[0] connect slots_4.io.in_uop.bits.fu_code[1], issue_slots[4].in_uop.bits.fu_code[1] connect slots_4.io.in_uop.bits.fu_code[2], issue_slots[4].in_uop.bits.fu_code[2] connect slots_4.io.in_uop.bits.fu_code[3], issue_slots[4].in_uop.bits.fu_code[3] connect slots_4.io.in_uop.bits.fu_code[4], issue_slots[4].in_uop.bits.fu_code[4] connect slots_4.io.in_uop.bits.fu_code[5], issue_slots[4].in_uop.bits.fu_code[5] connect slots_4.io.in_uop.bits.fu_code[6], issue_slots[4].in_uop.bits.fu_code[6] connect slots_4.io.in_uop.bits.fu_code[7], issue_slots[4].in_uop.bits.fu_code[7] connect slots_4.io.in_uop.bits.fu_code[8], issue_slots[4].in_uop.bits.fu_code[8] connect slots_4.io.in_uop.bits.fu_code[9], issue_slots[4].in_uop.bits.fu_code[9] connect slots_4.io.in_uop.bits.iq_type[0], issue_slots[4].in_uop.bits.iq_type[0] connect slots_4.io.in_uop.bits.iq_type[1], issue_slots[4].in_uop.bits.iq_type[1] connect slots_4.io.in_uop.bits.iq_type[2], issue_slots[4].in_uop.bits.iq_type[2] connect slots_4.io.in_uop.bits.iq_type[3], issue_slots[4].in_uop.bits.iq_type[3] connect slots_4.io.in_uop.bits.debug_pc, issue_slots[4].in_uop.bits.debug_pc connect slots_4.io.in_uop.bits.is_rvc, issue_slots[4].in_uop.bits.is_rvc connect slots_4.io.in_uop.bits.debug_inst, issue_slots[4].in_uop.bits.debug_inst connect slots_4.io.in_uop.bits.inst, issue_slots[4].in_uop.bits.inst connect slots_4.io.in_uop.valid, issue_slots[4].in_uop.valid connect issue_slots[4].iss_uop.debug_tsrc, slots_4.io.iss_uop.debug_tsrc connect issue_slots[4].iss_uop.debug_fsrc, slots_4.io.iss_uop.debug_fsrc connect issue_slots[4].iss_uop.bp_xcpt_if, slots_4.io.iss_uop.bp_xcpt_if connect issue_slots[4].iss_uop.bp_debug_if, slots_4.io.iss_uop.bp_debug_if connect issue_slots[4].iss_uop.xcpt_ma_if, slots_4.io.iss_uop.xcpt_ma_if connect issue_slots[4].iss_uop.xcpt_ae_if, slots_4.io.iss_uop.xcpt_ae_if connect issue_slots[4].iss_uop.xcpt_pf_if, slots_4.io.iss_uop.xcpt_pf_if connect issue_slots[4].iss_uop.fp_typ, slots_4.io.iss_uop.fp_typ connect issue_slots[4].iss_uop.fp_rm, slots_4.io.iss_uop.fp_rm connect issue_slots[4].iss_uop.fp_val, slots_4.io.iss_uop.fp_val connect issue_slots[4].iss_uop.fcn_op, slots_4.io.iss_uop.fcn_op connect issue_slots[4].iss_uop.fcn_dw, slots_4.io.iss_uop.fcn_dw connect issue_slots[4].iss_uop.frs3_en, slots_4.io.iss_uop.frs3_en connect issue_slots[4].iss_uop.lrs2_rtype, slots_4.io.iss_uop.lrs2_rtype connect issue_slots[4].iss_uop.lrs1_rtype, slots_4.io.iss_uop.lrs1_rtype connect issue_slots[4].iss_uop.dst_rtype, slots_4.io.iss_uop.dst_rtype connect issue_slots[4].iss_uop.lrs3, slots_4.io.iss_uop.lrs3 connect issue_slots[4].iss_uop.lrs2, slots_4.io.iss_uop.lrs2 connect issue_slots[4].iss_uop.lrs1, slots_4.io.iss_uop.lrs1 connect issue_slots[4].iss_uop.ldst, slots_4.io.iss_uop.ldst connect issue_slots[4].iss_uop.ldst_is_rs1, slots_4.io.iss_uop.ldst_is_rs1 connect issue_slots[4].iss_uop.csr_cmd, slots_4.io.iss_uop.csr_cmd connect issue_slots[4].iss_uop.flush_on_commit, slots_4.io.iss_uop.flush_on_commit connect issue_slots[4].iss_uop.is_unique, slots_4.io.iss_uop.is_unique connect issue_slots[4].iss_uop.uses_stq, slots_4.io.iss_uop.uses_stq connect issue_slots[4].iss_uop.uses_ldq, slots_4.io.iss_uop.uses_ldq connect issue_slots[4].iss_uop.mem_signed, slots_4.io.iss_uop.mem_signed connect issue_slots[4].iss_uop.mem_size, slots_4.io.iss_uop.mem_size connect issue_slots[4].iss_uop.mem_cmd, slots_4.io.iss_uop.mem_cmd connect issue_slots[4].iss_uop.exc_cause, slots_4.io.iss_uop.exc_cause connect issue_slots[4].iss_uop.exception, slots_4.io.iss_uop.exception connect issue_slots[4].iss_uop.stale_pdst, slots_4.io.iss_uop.stale_pdst connect issue_slots[4].iss_uop.ppred_busy, slots_4.io.iss_uop.ppred_busy connect issue_slots[4].iss_uop.prs3_busy, slots_4.io.iss_uop.prs3_busy connect issue_slots[4].iss_uop.prs2_busy, slots_4.io.iss_uop.prs2_busy connect issue_slots[4].iss_uop.prs1_busy, slots_4.io.iss_uop.prs1_busy connect issue_slots[4].iss_uop.ppred, slots_4.io.iss_uop.ppred connect issue_slots[4].iss_uop.prs3, slots_4.io.iss_uop.prs3 connect issue_slots[4].iss_uop.prs2, slots_4.io.iss_uop.prs2 connect issue_slots[4].iss_uop.prs1, slots_4.io.iss_uop.prs1 connect issue_slots[4].iss_uop.pdst, slots_4.io.iss_uop.pdst connect issue_slots[4].iss_uop.rxq_idx, slots_4.io.iss_uop.rxq_idx connect issue_slots[4].iss_uop.stq_idx, slots_4.io.iss_uop.stq_idx connect issue_slots[4].iss_uop.ldq_idx, slots_4.io.iss_uop.ldq_idx connect issue_slots[4].iss_uop.rob_idx, slots_4.io.iss_uop.rob_idx connect issue_slots[4].iss_uop.fp_ctrl.vec, slots_4.io.iss_uop.fp_ctrl.vec connect issue_slots[4].iss_uop.fp_ctrl.wflags, slots_4.io.iss_uop.fp_ctrl.wflags connect issue_slots[4].iss_uop.fp_ctrl.sqrt, slots_4.io.iss_uop.fp_ctrl.sqrt connect issue_slots[4].iss_uop.fp_ctrl.div, slots_4.io.iss_uop.fp_ctrl.div connect issue_slots[4].iss_uop.fp_ctrl.fma, slots_4.io.iss_uop.fp_ctrl.fma connect issue_slots[4].iss_uop.fp_ctrl.fastpipe, slots_4.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[4].iss_uop.fp_ctrl.toint, slots_4.io.iss_uop.fp_ctrl.toint connect issue_slots[4].iss_uop.fp_ctrl.fromint, slots_4.io.iss_uop.fp_ctrl.fromint connect issue_slots[4].iss_uop.fp_ctrl.typeTagOut, slots_4.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[4].iss_uop.fp_ctrl.typeTagIn, slots_4.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[4].iss_uop.fp_ctrl.swap23, slots_4.io.iss_uop.fp_ctrl.swap23 connect issue_slots[4].iss_uop.fp_ctrl.swap12, slots_4.io.iss_uop.fp_ctrl.swap12 connect issue_slots[4].iss_uop.fp_ctrl.ren3, slots_4.io.iss_uop.fp_ctrl.ren3 connect issue_slots[4].iss_uop.fp_ctrl.ren2, slots_4.io.iss_uop.fp_ctrl.ren2 connect issue_slots[4].iss_uop.fp_ctrl.ren1, slots_4.io.iss_uop.fp_ctrl.ren1 connect issue_slots[4].iss_uop.fp_ctrl.wen, slots_4.io.iss_uop.fp_ctrl.wen connect issue_slots[4].iss_uop.fp_ctrl.ldst, slots_4.io.iss_uop.fp_ctrl.ldst connect issue_slots[4].iss_uop.op2_sel, slots_4.io.iss_uop.op2_sel connect issue_slots[4].iss_uop.op1_sel, slots_4.io.iss_uop.op1_sel connect issue_slots[4].iss_uop.imm_packed, slots_4.io.iss_uop.imm_packed connect issue_slots[4].iss_uop.pimm, slots_4.io.iss_uop.pimm connect issue_slots[4].iss_uop.imm_sel, slots_4.io.iss_uop.imm_sel connect issue_slots[4].iss_uop.imm_rename, slots_4.io.iss_uop.imm_rename connect issue_slots[4].iss_uop.taken, slots_4.io.iss_uop.taken connect issue_slots[4].iss_uop.pc_lob, slots_4.io.iss_uop.pc_lob connect issue_slots[4].iss_uop.edge_inst, slots_4.io.iss_uop.edge_inst connect issue_slots[4].iss_uop.ftq_idx, slots_4.io.iss_uop.ftq_idx connect issue_slots[4].iss_uop.is_mov, slots_4.io.iss_uop.is_mov connect issue_slots[4].iss_uop.is_rocc, slots_4.io.iss_uop.is_rocc connect issue_slots[4].iss_uop.is_sys_pc2epc, slots_4.io.iss_uop.is_sys_pc2epc connect issue_slots[4].iss_uop.is_eret, slots_4.io.iss_uop.is_eret connect issue_slots[4].iss_uop.is_amo, slots_4.io.iss_uop.is_amo connect issue_slots[4].iss_uop.is_sfence, slots_4.io.iss_uop.is_sfence connect issue_slots[4].iss_uop.is_fencei, slots_4.io.iss_uop.is_fencei connect issue_slots[4].iss_uop.is_fence, slots_4.io.iss_uop.is_fence connect issue_slots[4].iss_uop.is_sfb, slots_4.io.iss_uop.is_sfb connect issue_slots[4].iss_uop.br_type, slots_4.io.iss_uop.br_type connect issue_slots[4].iss_uop.br_tag, slots_4.io.iss_uop.br_tag connect issue_slots[4].iss_uop.br_mask, slots_4.io.iss_uop.br_mask connect issue_slots[4].iss_uop.dis_col_sel, slots_4.io.iss_uop.dis_col_sel connect issue_slots[4].iss_uop.iw_p3_bypass_hint, slots_4.io.iss_uop.iw_p3_bypass_hint connect issue_slots[4].iss_uop.iw_p2_bypass_hint, slots_4.io.iss_uop.iw_p2_bypass_hint connect issue_slots[4].iss_uop.iw_p1_bypass_hint, slots_4.io.iss_uop.iw_p1_bypass_hint connect issue_slots[4].iss_uop.iw_p2_speculative_child, slots_4.io.iss_uop.iw_p2_speculative_child connect issue_slots[4].iss_uop.iw_p1_speculative_child, slots_4.io.iss_uop.iw_p1_speculative_child connect issue_slots[4].iss_uop.iw_issued_partial_dgen, slots_4.io.iss_uop.iw_issued_partial_dgen connect issue_slots[4].iss_uop.iw_issued_partial_agen, slots_4.io.iss_uop.iw_issued_partial_agen connect issue_slots[4].iss_uop.iw_issued, slots_4.io.iss_uop.iw_issued connect issue_slots[4].iss_uop.fu_code[0], slots_4.io.iss_uop.fu_code[0] connect issue_slots[4].iss_uop.fu_code[1], slots_4.io.iss_uop.fu_code[1] connect issue_slots[4].iss_uop.fu_code[2], slots_4.io.iss_uop.fu_code[2] connect issue_slots[4].iss_uop.fu_code[3], slots_4.io.iss_uop.fu_code[3] connect issue_slots[4].iss_uop.fu_code[4], slots_4.io.iss_uop.fu_code[4] connect issue_slots[4].iss_uop.fu_code[5], slots_4.io.iss_uop.fu_code[5] connect issue_slots[4].iss_uop.fu_code[6], slots_4.io.iss_uop.fu_code[6] connect issue_slots[4].iss_uop.fu_code[7], slots_4.io.iss_uop.fu_code[7] connect issue_slots[4].iss_uop.fu_code[8], slots_4.io.iss_uop.fu_code[8] connect issue_slots[4].iss_uop.fu_code[9], slots_4.io.iss_uop.fu_code[9] connect issue_slots[4].iss_uop.iq_type[0], slots_4.io.iss_uop.iq_type[0] connect issue_slots[4].iss_uop.iq_type[1], slots_4.io.iss_uop.iq_type[1] connect issue_slots[4].iss_uop.iq_type[2], slots_4.io.iss_uop.iq_type[2] connect issue_slots[4].iss_uop.iq_type[3], slots_4.io.iss_uop.iq_type[3] connect issue_slots[4].iss_uop.debug_pc, slots_4.io.iss_uop.debug_pc connect issue_slots[4].iss_uop.is_rvc, slots_4.io.iss_uop.is_rvc connect issue_slots[4].iss_uop.debug_inst, slots_4.io.iss_uop.debug_inst connect issue_slots[4].iss_uop.inst, slots_4.io.iss_uop.inst connect slots_4.io.grant, issue_slots[4].grant connect issue_slots[4].request, slots_4.io.request connect issue_slots[4].will_be_valid, slots_4.io.will_be_valid connect issue_slots[4].valid, slots_4.io.valid connect slots_5.io.child_rebusys, issue_slots[5].child_rebusys connect slots_5.io.pred_wakeup_port.bits, issue_slots[5].pred_wakeup_port.bits connect slots_5.io.pred_wakeup_port.valid, issue_slots[5].pred_wakeup_port.valid connect slots_5.io.wakeup_ports[0].bits.rebusy, issue_slots[5].wakeup_ports[0].bits.rebusy connect slots_5.io.wakeup_ports[0].bits.speculative_mask, issue_slots[5].wakeup_ports[0].bits.speculative_mask connect slots_5.io.wakeup_ports[0].bits.bypassable, issue_slots[5].wakeup_ports[0].bits.bypassable connect slots_5.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[0].bits.uop.debug_tsrc connect slots_5.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[0].bits.uop.debug_fsrc connect slots_5.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_5.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[0].bits.uop.bp_debug_if connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_5.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[5].wakeup_ports[0].bits.uop.fp_typ connect slots_5.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[5].wakeup_ports[0].bits.uop.fp_rm connect slots_5.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[5].wakeup_ports[0].bits.uop.fp_val connect slots_5.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[5].wakeup_ports[0].bits.uop.fcn_op connect slots_5.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[0].bits.uop.fcn_dw connect slots_5.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[5].wakeup_ports[0].bits.uop.frs3_en connect slots_5.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_5.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_5.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[0].bits.uop.dst_rtype connect slots_5.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[5].wakeup_ports[0].bits.uop.lrs3 connect slots_5.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[5].wakeup_ports[0].bits.uop.lrs2 connect slots_5.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[5].wakeup_ports[0].bits.uop.lrs1 connect slots_5.io.wakeup_ports[0].bits.uop.ldst, issue_slots[5].wakeup_ports[0].bits.uop.ldst connect slots_5.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_5.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[0].bits.uop.csr_cmd connect slots_5.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[0].bits.uop.flush_on_commit connect slots_5.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[5].wakeup_ports[0].bits.uop.is_unique connect slots_5.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[5].wakeup_ports[0].bits.uop.uses_stq connect slots_5.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[0].bits.uop.uses_ldq connect slots_5.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[5].wakeup_ports[0].bits.uop.mem_signed connect slots_5.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[5].wakeup_ports[0].bits.uop.mem_size connect slots_5.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[0].bits.uop.mem_cmd connect slots_5.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[5].wakeup_ports[0].bits.uop.exc_cause connect slots_5.io.wakeup_ports[0].bits.uop.exception, issue_slots[5].wakeup_ports[0].bits.uop.exception connect slots_5.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[0].bits.uop.stale_pdst connect slots_5.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[0].bits.uop.ppred_busy connect slots_5.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs3_busy connect slots_5.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs2_busy connect slots_5.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs1_busy connect slots_5.io.wakeup_ports[0].bits.uop.ppred, issue_slots[5].wakeup_ports[0].bits.uop.ppred connect slots_5.io.wakeup_ports[0].bits.uop.prs3, issue_slots[5].wakeup_ports[0].bits.uop.prs3 connect slots_5.io.wakeup_ports[0].bits.uop.prs2, issue_slots[5].wakeup_ports[0].bits.uop.prs2 connect slots_5.io.wakeup_ports[0].bits.uop.prs1, issue_slots[5].wakeup_ports[0].bits.uop.prs1 connect slots_5.io.wakeup_ports[0].bits.uop.pdst, issue_slots[5].wakeup_ports[0].bits.uop.pdst connect slots_5.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[0].bits.uop.rxq_idx connect slots_5.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[5].wakeup_ports[0].bits.uop.stq_idx connect slots_5.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[0].bits.uop.ldq_idx connect slots_5.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[5].wakeup_ports[0].bits.uop.rob_idx connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_5.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[5].wakeup_ports[0].bits.uop.op2_sel connect slots_5.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[5].wakeup_ports[0].bits.uop.op1_sel connect slots_5.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[5].wakeup_ports[0].bits.uop.imm_packed connect slots_5.io.wakeup_ports[0].bits.uop.pimm, issue_slots[5].wakeup_ports[0].bits.uop.pimm connect slots_5.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[5].wakeup_ports[0].bits.uop.imm_sel connect slots_5.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[5].wakeup_ports[0].bits.uop.imm_rename connect slots_5.io.wakeup_ports[0].bits.uop.taken, issue_slots[5].wakeup_ports[0].bits.uop.taken connect slots_5.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[5].wakeup_ports[0].bits.uop.pc_lob connect slots_5.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[5].wakeup_ports[0].bits.uop.edge_inst connect slots_5.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[0].bits.uop.ftq_idx connect slots_5.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[5].wakeup_ports[0].bits.uop.is_mov connect slots_5.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[5].wakeup_ports[0].bits.uop.is_rocc connect slots_5.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_5.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[5].wakeup_ports[0].bits.uop.is_eret connect slots_5.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[5].wakeup_ports[0].bits.uop.is_amo connect slots_5.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[5].wakeup_ports[0].bits.uop.is_sfence connect slots_5.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[5].wakeup_ports[0].bits.uop.is_fencei connect slots_5.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[5].wakeup_ports[0].bits.uop.is_fence connect slots_5.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[5].wakeup_ports[0].bits.uop.is_sfb connect slots_5.io.wakeup_ports[0].bits.uop.br_type, issue_slots[5].wakeup_ports[0].bits.uop.br_type connect slots_5.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[5].wakeup_ports[0].bits.uop.br_tag connect slots_5.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[5].wakeup_ports[0].bits.uop.br_mask connect slots_5.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[0].bits.uop.dis_col_sel connect slots_5.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_5.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_5.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_5.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_5.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[0] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[1] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[2] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[3] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[4] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[5] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[6] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[7] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[8] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[9] connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[0] connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[1] connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[2] connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[3] connect slots_5.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[5].wakeup_ports[0].bits.uop.debug_pc connect slots_5.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[5].wakeup_ports[0].bits.uop.is_rvc connect slots_5.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[5].wakeup_ports[0].bits.uop.debug_inst connect slots_5.io.wakeup_ports[0].bits.uop.inst, issue_slots[5].wakeup_ports[0].bits.uop.inst connect slots_5.io.wakeup_ports[0].valid, issue_slots[5].wakeup_ports[0].valid connect slots_5.io.wakeup_ports[1].bits.rebusy, issue_slots[5].wakeup_ports[1].bits.rebusy connect slots_5.io.wakeup_ports[1].bits.speculative_mask, issue_slots[5].wakeup_ports[1].bits.speculative_mask connect slots_5.io.wakeup_ports[1].bits.bypassable, issue_slots[5].wakeup_ports[1].bits.bypassable connect slots_5.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[1].bits.uop.debug_tsrc connect slots_5.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[1].bits.uop.debug_fsrc connect slots_5.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_5.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[1].bits.uop.bp_debug_if connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_5.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[5].wakeup_ports[1].bits.uop.fp_typ connect slots_5.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[5].wakeup_ports[1].bits.uop.fp_rm connect slots_5.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[5].wakeup_ports[1].bits.uop.fp_val connect slots_5.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[5].wakeup_ports[1].bits.uop.fcn_op connect slots_5.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[1].bits.uop.fcn_dw connect slots_5.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[5].wakeup_ports[1].bits.uop.frs3_en connect slots_5.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_5.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_5.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[1].bits.uop.dst_rtype connect slots_5.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[5].wakeup_ports[1].bits.uop.lrs3 connect slots_5.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[5].wakeup_ports[1].bits.uop.lrs2 connect slots_5.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[5].wakeup_ports[1].bits.uop.lrs1 connect slots_5.io.wakeup_ports[1].bits.uop.ldst, issue_slots[5].wakeup_ports[1].bits.uop.ldst connect slots_5.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_5.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[1].bits.uop.csr_cmd connect slots_5.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[1].bits.uop.flush_on_commit connect slots_5.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[5].wakeup_ports[1].bits.uop.is_unique connect slots_5.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[5].wakeup_ports[1].bits.uop.uses_stq connect slots_5.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[1].bits.uop.uses_ldq connect slots_5.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[5].wakeup_ports[1].bits.uop.mem_signed connect slots_5.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[5].wakeup_ports[1].bits.uop.mem_size connect slots_5.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[1].bits.uop.mem_cmd connect slots_5.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[5].wakeup_ports[1].bits.uop.exc_cause connect slots_5.io.wakeup_ports[1].bits.uop.exception, issue_slots[5].wakeup_ports[1].bits.uop.exception connect slots_5.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[1].bits.uop.stale_pdst connect slots_5.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[1].bits.uop.ppred_busy connect slots_5.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs3_busy connect slots_5.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs2_busy connect slots_5.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs1_busy connect slots_5.io.wakeup_ports[1].bits.uop.ppred, issue_slots[5].wakeup_ports[1].bits.uop.ppred connect slots_5.io.wakeup_ports[1].bits.uop.prs3, issue_slots[5].wakeup_ports[1].bits.uop.prs3 connect slots_5.io.wakeup_ports[1].bits.uop.prs2, issue_slots[5].wakeup_ports[1].bits.uop.prs2 connect slots_5.io.wakeup_ports[1].bits.uop.prs1, issue_slots[5].wakeup_ports[1].bits.uop.prs1 connect slots_5.io.wakeup_ports[1].bits.uop.pdst, issue_slots[5].wakeup_ports[1].bits.uop.pdst connect slots_5.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[1].bits.uop.rxq_idx connect slots_5.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[5].wakeup_ports[1].bits.uop.stq_idx connect slots_5.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[1].bits.uop.ldq_idx connect slots_5.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[5].wakeup_ports[1].bits.uop.rob_idx connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_5.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[5].wakeup_ports[1].bits.uop.op2_sel connect slots_5.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[5].wakeup_ports[1].bits.uop.op1_sel connect slots_5.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[5].wakeup_ports[1].bits.uop.imm_packed connect slots_5.io.wakeup_ports[1].bits.uop.pimm, issue_slots[5].wakeup_ports[1].bits.uop.pimm connect slots_5.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[5].wakeup_ports[1].bits.uop.imm_sel connect slots_5.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[5].wakeup_ports[1].bits.uop.imm_rename connect slots_5.io.wakeup_ports[1].bits.uop.taken, issue_slots[5].wakeup_ports[1].bits.uop.taken connect slots_5.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[5].wakeup_ports[1].bits.uop.pc_lob connect slots_5.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[5].wakeup_ports[1].bits.uop.edge_inst connect slots_5.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[1].bits.uop.ftq_idx connect slots_5.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[5].wakeup_ports[1].bits.uop.is_mov connect slots_5.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[5].wakeup_ports[1].bits.uop.is_rocc connect slots_5.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_5.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[5].wakeup_ports[1].bits.uop.is_eret connect slots_5.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[5].wakeup_ports[1].bits.uop.is_amo connect slots_5.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[5].wakeup_ports[1].bits.uop.is_sfence connect slots_5.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[5].wakeup_ports[1].bits.uop.is_fencei connect slots_5.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[5].wakeup_ports[1].bits.uop.is_fence connect slots_5.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[5].wakeup_ports[1].bits.uop.is_sfb connect slots_5.io.wakeup_ports[1].bits.uop.br_type, issue_slots[5].wakeup_ports[1].bits.uop.br_type connect slots_5.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[5].wakeup_ports[1].bits.uop.br_tag connect slots_5.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[5].wakeup_ports[1].bits.uop.br_mask connect slots_5.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[1].bits.uop.dis_col_sel connect slots_5.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_5.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_5.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_5.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_5.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[0] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[1] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[2] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[3] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[4] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[5] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[6] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[7] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[8] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[9] connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[0] connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[1] connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[2] connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[3] connect slots_5.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[5].wakeup_ports[1].bits.uop.debug_pc connect slots_5.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[5].wakeup_ports[1].bits.uop.is_rvc connect slots_5.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[5].wakeup_ports[1].bits.uop.debug_inst connect slots_5.io.wakeup_ports[1].bits.uop.inst, issue_slots[5].wakeup_ports[1].bits.uop.inst connect slots_5.io.wakeup_ports[1].valid, issue_slots[5].wakeup_ports[1].valid connect slots_5.io.wakeup_ports[2].bits.rebusy, issue_slots[5].wakeup_ports[2].bits.rebusy connect slots_5.io.wakeup_ports[2].bits.speculative_mask, issue_slots[5].wakeup_ports[2].bits.speculative_mask connect slots_5.io.wakeup_ports[2].bits.bypassable, issue_slots[5].wakeup_ports[2].bits.bypassable connect slots_5.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[2].bits.uop.debug_tsrc connect slots_5.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[2].bits.uop.debug_fsrc connect slots_5.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_5.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[2].bits.uop.bp_debug_if connect slots_5.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_5.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_5.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_5.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[5].wakeup_ports[2].bits.uop.fp_typ connect slots_5.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[5].wakeup_ports[2].bits.uop.fp_rm connect slots_5.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[5].wakeup_ports[2].bits.uop.fp_val connect slots_5.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[5].wakeup_ports[2].bits.uop.fcn_op connect slots_5.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[2].bits.uop.fcn_dw connect slots_5.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[5].wakeup_ports[2].bits.uop.frs3_en connect slots_5.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_5.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_5.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[2].bits.uop.dst_rtype connect slots_5.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[5].wakeup_ports[2].bits.uop.lrs3 connect slots_5.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[5].wakeup_ports[2].bits.uop.lrs2 connect slots_5.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[5].wakeup_ports[2].bits.uop.lrs1 connect slots_5.io.wakeup_ports[2].bits.uop.ldst, issue_slots[5].wakeup_ports[2].bits.uop.ldst connect slots_5.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_5.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[2].bits.uop.csr_cmd connect slots_5.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[2].bits.uop.flush_on_commit connect slots_5.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[5].wakeup_ports[2].bits.uop.is_unique connect slots_5.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[5].wakeup_ports[2].bits.uop.uses_stq connect slots_5.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[2].bits.uop.uses_ldq connect slots_5.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[5].wakeup_ports[2].bits.uop.mem_signed connect slots_5.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[5].wakeup_ports[2].bits.uop.mem_size connect slots_5.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[2].bits.uop.mem_cmd connect slots_5.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[5].wakeup_ports[2].bits.uop.exc_cause connect slots_5.io.wakeup_ports[2].bits.uop.exception, issue_slots[5].wakeup_ports[2].bits.uop.exception connect slots_5.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[2].bits.uop.stale_pdst connect slots_5.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[2].bits.uop.ppred_busy connect slots_5.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[2].bits.uop.prs3_busy connect slots_5.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[2].bits.uop.prs2_busy connect slots_5.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[2].bits.uop.prs1_busy connect slots_5.io.wakeup_ports[2].bits.uop.ppred, issue_slots[5].wakeup_ports[2].bits.uop.ppred connect slots_5.io.wakeup_ports[2].bits.uop.prs3, issue_slots[5].wakeup_ports[2].bits.uop.prs3 connect slots_5.io.wakeup_ports[2].bits.uop.prs2, issue_slots[5].wakeup_ports[2].bits.uop.prs2 connect slots_5.io.wakeup_ports[2].bits.uop.prs1, issue_slots[5].wakeup_ports[2].bits.uop.prs1 connect slots_5.io.wakeup_ports[2].bits.uop.pdst, issue_slots[5].wakeup_ports[2].bits.uop.pdst connect slots_5.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[2].bits.uop.rxq_idx connect slots_5.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[5].wakeup_ports[2].bits.uop.stq_idx connect slots_5.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[2].bits.uop.ldq_idx connect slots_5.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[5].wakeup_ports[2].bits.uop.rob_idx connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_5.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[5].wakeup_ports[2].bits.uop.op2_sel connect slots_5.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[5].wakeup_ports[2].bits.uop.op1_sel connect slots_5.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[5].wakeup_ports[2].bits.uop.imm_packed connect slots_5.io.wakeup_ports[2].bits.uop.pimm, issue_slots[5].wakeup_ports[2].bits.uop.pimm connect slots_5.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[5].wakeup_ports[2].bits.uop.imm_sel connect slots_5.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[5].wakeup_ports[2].bits.uop.imm_rename connect slots_5.io.wakeup_ports[2].bits.uop.taken, issue_slots[5].wakeup_ports[2].bits.uop.taken connect slots_5.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[5].wakeup_ports[2].bits.uop.pc_lob connect slots_5.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[5].wakeup_ports[2].bits.uop.edge_inst connect slots_5.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[2].bits.uop.ftq_idx connect slots_5.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[5].wakeup_ports[2].bits.uop.is_mov connect slots_5.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[5].wakeup_ports[2].bits.uop.is_rocc connect slots_5.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_5.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[5].wakeup_ports[2].bits.uop.is_eret connect slots_5.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[5].wakeup_ports[2].bits.uop.is_amo connect slots_5.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[5].wakeup_ports[2].bits.uop.is_sfence connect slots_5.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[5].wakeup_ports[2].bits.uop.is_fencei connect slots_5.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[5].wakeup_ports[2].bits.uop.is_fence connect slots_5.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[5].wakeup_ports[2].bits.uop.is_sfb connect slots_5.io.wakeup_ports[2].bits.uop.br_type, issue_slots[5].wakeup_ports[2].bits.uop.br_type connect slots_5.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[5].wakeup_ports[2].bits.uop.br_tag connect slots_5.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[5].wakeup_ports[2].bits.uop.br_mask connect slots_5.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[2].bits.uop.dis_col_sel connect slots_5.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_5.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_5.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_5.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_5.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_5.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_5.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_5.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[5].wakeup_ports[2].bits.uop.iw_issued connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[0] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[1] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[2] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[3] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[4] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[5] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[6] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[7] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[8] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[9] connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[0] connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[1] connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[2] connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[3] connect slots_5.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[5].wakeup_ports[2].bits.uop.debug_pc connect slots_5.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[5].wakeup_ports[2].bits.uop.is_rvc connect slots_5.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[5].wakeup_ports[2].bits.uop.debug_inst connect slots_5.io.wakeup_ports[2].bits.uop.inst, issue_slots[5].wakeup_ports[2].bits.uop.inst connect slots_5.io.wakeup_ports[2].valid, issue_slots[5].wakeup_ports[2].valid connect slots_5.io.wakeup_ports[3].bits.rebusy, issue_slots[5].wakeup_ports[3].bits.rebusy connect slots_5.io.wakeup_ports[3].bits.speculative_mask, issue_slots[5].wakeup_ports[3].bits.speculative_mask connect slots_5.io.wakeup_ports[3].bits.bypassable, issue_slots[5].wakeup_ports[3].bits.bypassable connect slots_5.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[3].bits.uop.debug_tsrc connect slots_5.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[3].bits.uop.debug_fsrc connect slots_5.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_5.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[3].bits.uop.bp_debug_if connect slots_5.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_5.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_5.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_5.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[5].wakeup_ports[3].bits.uop.fp_typ connect slots_5.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[5].wakeup_ports[3].bits.uop.fp_rm connect slots_5.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[5].wakeup_ports[3].bits.uop.fp_val connect slots_5.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[5].wakeup_ports[3].bits.uop.fcn_op connect slots_5.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[3].bits.uop.fcn_dw connect slots_5.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[5].wakeup_ports[3].bits.uop.frs3_en connect slots_5.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_5.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_5.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[3].bits.uop.dst_rtype connect slots_5.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[5].wakeup_ports[3].bits.uop.lrs3 connect slots_5.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[5].wakeup_ports[3].bits.uop.lrs2 connect slots_5.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[5].wakeup_ports[3].bits.uop.lrs1 connect slots_5.io.wakeup_ports[3].bits.uop.ldst, issue_slots[5].wakeup_ports[3].bits.uop.ldst connect slots_5.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_5.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[3].bits.uop.csr_cmd connect slots_5.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[3].bits.uop.flush_on_commit connect slots_5.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[5].wakeup_ports[3].bits.uop.is_unique connect slots_5.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[5].wakeup_ports[3].bits.uop.uses_stq connect slots_5.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[3].bits.uop.uses_ldq connect slots_5.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[5].wakeup_ports[3].bits.uop.mem_signed connect slots_5.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[5].wakeup_ports[3].bits.uop.mem_size connect slots_5.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[3].bits.uop.mem_cmd connect slots_5.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[5].wakeup_ports[3].bits.uop.exc_cause connect slots_5.io.wakeup_ports[3].bits.uop.exception, issue_slots[5].wakeup_ports[3].bits.uop.exception connect slots_5.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[3].bits.uop.stale_pdst connect slots_5.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[3].bits.uop.ppred_busy connect slots_5.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[3].bits.uop.prs3_busy connect slots_5.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[3].bits.uop.prs2_busy connect slots_5.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[3].bits.uop.prs1_busy connect slots_5.io.wakeup_ports[3].bits.uop.ppred, issue_slots[5].wakeup_ports[3].bits.uop.ppred connect slots_5.io.wakeup_ports[3].bits.uop.prs3, issue_slots[5].wakeup_ports[3].bits.uop.prs3 connect slots_5.io.wakeup_ports[3].bits.uop.prs2, issue_slots[5].wakeup_ports[3].bits.uop.prs2 connect slots_5.io.wakeup_ports[3].bits.uop.prs1, issue_slots[5].wakeup_ports[3].bits.uop.prs1 connect slots_5.io.wakeup_ports[3].bits.uop.pdst, issue_slots[5].wakeup_ports[3].bits.uop.pdst connect slots_5.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[3].bits.uop.rxq_idx connect slots_5.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[5].wakeup_ports[3].bits.uop.stq_idx connect slots_5.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[3].bits.uop.ldq_idx connect slots_5.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[5].wakeup_ports[3].bits.uop.rob_idx connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_5.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[5].wakeup_ports[3].bits.uop.op2_sel connect slots_5.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[5].wakeup_ports[3].bits.uop.op1_sel connect slots_5.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[5].wakeup_ports[3].bits.uop.imm_packed connect slots_5.io.wakeup_ports[3].bits.uop.pimm, issue_slots[5].wakeup_ports[3].bits.uop.pimm connect slots_5.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[5].wakeup_ports[3].bits.uop.imm_sel connect slots_5.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[5].wakeup_ports[3].bits.uop.imm_rename connect slots_5.io.wakeup_ports[3].bits.uop.taken, issue_slots[5].wakeup_ports[3].bits.uop.taken connect slots_5.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[5].wakeup_ports[3].bits.uop.pc_lob connect slots_5.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[5].wakeup_ports[3].bits.uop.edge_inst connect slots_5.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[3].bits.uop.ftq_idx connect slots_5.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[5].wakeup_ports[3].bits.uop.is_mov connect slots_5.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[5].wakeup_ports[3].bits.uop.is_rocc connect slots_5.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_5.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[5].wakeup_ports[3].bits.uop.is_eret connect slots_5.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[5].wakeup_ports[3].bits.uop.is_amo connect slots_5.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[5].wakeup_ports[3].bits.uop.is_sfence connect slots_5.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[5].wakeup_ports[3].bits.uop.is_fencei connect slots_5.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[5].wakeup_ports[3].bits.uop.is_fence connect slots_5.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[5].wakeup_ports[3].bits.uop.is_sfb connect slots_5.io.wakeup_ports[3].bits.uop.br_type, issue_slots[5].wakeup_ports[3].bits.uop.br_type connect slots_5.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[5].wakeup_ports[3].bits.uop.br_tag connect slots_5.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[5].wakeup_ports[3].bits.uop.br_mask connect slots_5.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[3].bits.uop.dis_col_sel connect slots_5.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_5.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_5.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_5.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_5.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_5.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_5.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_5.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[5].wakeup_ports[3].bits.uop.iw_issued connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[0] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[1] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[2] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[3] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[4] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[5] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[6] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[7] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[8] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[9] connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[0] connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[1] connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[2] connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[3] connect slots_5.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[5].wakeup_ports[3].bits.uop.debug_pc connect slots_5.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[5].wakeup_ports[3].bits.uop.is_rvc connect slots_5.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[5].wakeup_ports[3].bits.uop.debug_inst connect slots_5.io.wakeup_ports[3].bits.uop.inst, issue_slots[5].wakeup_ports[3].bits.uop.inst connect slots_5.io.wakeup_ports[3].valid, issue_slots[5].wakeup_ports[3].valid connect slots_5.io.wakeup_ports[4].bits.rebusy, issue_slots[5].wakeup_ports[4].bits.rebusy connect slots_5.io.wakeup_ports[4].bits.speculative_mask, issue_slots[5].wakeup_ports[4].bits.speculative_mask connect slots_5.io.wakeup_ports[4].bits.bypassable, issue_slots[5].wakeup_ports[4].bits.bypassable connect slots_5.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[4].bits.uop.debug_tsrc connect slots_5.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[4].bits.uop.debug_fsrc connect slots_5.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_5.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[4].bits.uop.bp_debug_if connect slots_5.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_5.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_5.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_5.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[5].wakeup_ports[4].bits.uop.fp_typ connect slots_5.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[5].wakeup_ports[4].bits.uop.fp_rm connect slots_5.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[5].wakeup_ports[4].bits.uop.fp_val connect slots_5.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[5].wakeup_ports[4].bits.uop.fcn_op connect slots_5.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[4].bits.uop.fcn_dw connect slots_5.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[5].wakeup_ports[4].bits.uop.frs3_en connect slots_5.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_5.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_5.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[4].bits.uop.dst_rtype connect slots_5.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[5].wakeup_ports[4].bits.uop.lrs3 connect slots_5.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[5].wakeup_ports[4].bits.uop.lrs2 connect slots_5.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[5].wakeup_ports[4].bits.uop.lrs1 connect slots_5.io.wakeup_ports[4].bits.uop.ldst, issue_slots[5].wakeup_ports[4].bits.uop.ldst connect slots_5.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_5.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[4].bits.uop.csr_cmd connect slots_5.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[4].bits.uop.flush_on_commit connect slots_5.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[5].wakeup_ports[4].bits.uop.is_unique connect slots_5.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[5].wakeup_ports[4].bits.uop.uses_stq connect slots_5.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[4].bits.uop.uses_ldq connect slots_5.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[5].wakeup_ports[4].bits.uop.mem_signed connect slots_5.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[5].wakeup_ports[4].bits.uop.mem_size connect slots_5.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[4].bits.uop.mem_cmd connect slots_5.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[5].wakeup_ports[4].bits.uop.exc_cause connect slots_5.io.wakeup_ports[4].bits.uop.exception, issue_slots[5].wakeup_ports[4].bits.uop.exception connect slots_5.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[4].bits.uop.stale_pdst connect slots_5.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[4].bits.uop.ppred_busy connect slots_5.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[4].bits.uop.prs3_busy connect slots_5.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[4].bits.uop.prs2_busy connect slots_5.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[4].bits.uop.prs1_busy connect slots_5.io.wakeup_ports[4].bits.uop.ppred, issue_slots[5].wakeup_ports[4].bits.uop.ppred connect slots_5.io.wakeup_ports[4].bits.uop.prs3, issue_slots[5].wakeup_ports[4].bits.uop.prs3 connect slots_5.io.wakeup_ports[4].bits.uop.prs2, issue_slots[5].wakeup_ports[4].bits.uop.prs2 connect slots_5.io.wakeup_ports[4].bits.uop.prs1, issue_slots[5].wakeup_ports[4].bits.uop.prs1 connect slots_5.io.wakeup_ports[4].bits.uop.pdst, issue_slots[5].wakeup_ports[4].bits.uop.pdst connect slots_5.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[4].bits.uop.rxq_idx connect slots_5.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[5].wakeup_ports[4].bits.uop.stq_idx connect slots_5.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[4].bits.uop.ldq_idx connect slots_5.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[5].wakeup_ports[4].bits.uop.rob_idx connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_5.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[5].wakeup_ports[4].bits.uop.op2_sel connect slots_5.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[5].wakeup_ports[4].bits.uop.op1_sel connect slots_5.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[5].wakeup_ports[4].bits.uop.imm_packed connect slots_5.io.wakeup_ports[4].bits.uop.pimm, issue_slots[5].wakeup_ports[4].bits.uop.pimm connect slots_5.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[5].wakeup_ports[4].bits.uop.imm_sel connect slots_5.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[5].wakeup_ports[4].bits.uop.imm_rename connect slots_5.io.wakeup_ports[4].bits.uop.taken, issue_slots[5].wakeup_ports[4].bits.uop.taken connect slots_5.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[5].wakeup_ports[4].bits.uop.pc_lob connect slots_5.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[5].wakeup_ports[4].bits.uop.edge_inst connect slots_5.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[4].bits.uop.ftq_idx connect slots_5.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[5].wakeup_ports[4].bits.uop.is_mov connect slots_5.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[5].wakeup_ports[4].bits.uop.is_rocc connect slots_5.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_5.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[5].wakeup_ports[4].bits.uop.is_eret connect slots_5.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[5].wakeup_ports[4].bits.uop.is_amo connect slots_5.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[5].wakeup_ports[4].bits.uop.is_sfence connect slots_5.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[5].wakeup_ports[4].bits.uop.is_fencei connect slots_5.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[5].wakeup_ports[4].bits.uop.is_fence connect slots_5.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[5].wakeup_ports[4].bits.uop.is_sfb connect slots_5.io.wakeup_ports[4].bits.uop.br_type, issue_slots[5].wakeup_ports[4].bits.uop.br_type connect slots_5.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[5].wakeup_ports[4].bits.uop.br_tag connect slots_5.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[5].wakeup_ports[4].bits.uop.br_mask connect slots_5.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[4].bits.uop.dis_col_sel connect slots_5.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_5.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_5.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_5.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_5.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_5.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_5.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_5.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[5].wakeup_ports[4].bits.uop.iw_issued connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[0] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[1] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[2] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[3] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[4] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[5] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[6] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[7] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[8] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[9] connect slots_5.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[4].bits.uop.iq_type[0] connect slots_5.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[4].bits.uop.iq_type[1] connect slots_5.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[4].bits.uop.iq_type[2] connect slots_5.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[4].bits.uop.iq_type[3] connect slots_5.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[5].wakeup_ports[4].bits.uop.debug_pc connect slots_5.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[5].wakeup_ports[4].bits.uop.is_rvc connect slots_5.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[5].wakeup_ports[4].bits.uop.debug_inst connect slots_5.io.wakeup_ports[4].bits.uop.inst, issue_slots[5].wakeup_ports[4].bits.uop.inst connect slots_5.io.wakeup_ports[4].valid, issue_slots[5].wakeup_ports[4].valid connect slots_5.io.squash_grant, issue_slots[5].squash_grant connect slots_5.io.clear, issue_slots[5].clear connect slots_5.io.kill, issue_slots[5].kill connect slots_5.io.brupdate.b2.target_offset, issue_slots[5].brupdate.b2.target_offset connect slots_5.io.brupdate.b2.jalr_target, issue_slots[5].brupdate.b2.jalr_target connect slots_5.io.brupdate.b2.pc_sel, issue_slots[5].brupdate.b2.pc_sel connect slots_5.io.brupdate.b2.cfi_type, issue_slots[5].brupdate.b2.cfi_type connect slots_5.io.brupdate.b2.taken, issue_slots[5].brupdate.b2.taken connect slots_5.io.brupdate.b2.mispredict, issue_slots[5].brupdate.b2.mispredict connect slots_5.io.brupdate.b2.uop.debug_tsrc, issue_slots[5].brupdate.b2.uop.debug_tsrc connect slots_5.io.brupdate.b2.uop.debug_fsrc, issue_slots[5].brupdate.b2.uop.debug_fsrc connect slots_5.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[5].brupdate.b2.uop.bp_xcpt_if connect slots_5.io.brupdate.b2.uop.bp_debug_if, issue_slots[5].brupdate.b2.uop.bp_debug_if connect slots_5.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[5].brupdate.b2.uop.xcpt_ma_if connect slots_5.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[5].brupdate.b2.uop.xcpt_ae_if connect slots_5.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[5].brupdate.b2.uop.xcpt_pf_if connect slots_5.io.brupdate.b2.uop.fp_typ, issue_slots[5].brupdate.b2.uop.fp_typ connect slots_5.io.brupdate.b2.uop.fp_rm, issue_slots[5].brupdate.b2.uop.fp_rm connect slots_5.io.brupdate.b2.uop.fp_val, issue_slots[5].brupdate.b2.uop.fp_val connect slots_5.io.brupdate.b2.uop.fcn_op, issue_slots[5].brupdate.b2.uop.fcn_op connect slots_5.io.brupdate.b2.uop.fcn_dw, issue_slots[5].brupdate.b2.uop.fcn_dw connect slots_5.io.brupdate.b2.uop.frs3_en, issue_slots[5].brupdate.b2.uop.frs3_en connect slots_5.io.brupdate.b2.uop.lrs2_rtype, issue_slots[5].brupdate.b2.uop.lrs2_rtype connect slots_5.io.brupdate.b2.uop.lrs1_rtype, issue_slots[5].brupdate.b2.uop.lrs1_rtype connect slots_5.io.brupdate.b2.uop.dst_rtype, issue_slots[5].brupdate.b2.uop.dst_rtype connect slots_5.io.brupdate.b2.uop.lrs3, issue_slots[5].brupdate.b2.uop.lrs3 connect slots_5.io.brupdate.b2.uop.lrs2, issue_slots[5].brupdate.b2.uop.lrs2 connect slots_5.io.brupdate.b2.uop.lrs1, issue_slots[5].brupdate.b2.uop.lrs1 connect slots_5.io.brupdate.b2.uop.ldst, issue_slots[5].brupdate.b2.uop.ldst connect slots_5.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[5].brupdate.b2.uop.ldst_is_rs1 connect slots_5.io.brupdate.b2.uop.csr_cmd, issue_slots[5].brupdate.b2.uop.csr_cmd connect slots_5.io.brupdate.b2.uop.flush_on_commit, issue_slots[5].brupdate.b2.uop.flush_on_commit connect slots_5.io.brupdate.b2.uop.is_unique, issue_slots[5].brupdate.b2.uop.is_unique connect slots_5.io.brupdate.b2.uop.uses_stq, issue_slots[5].brupdate.b2.uop.uses_stq connect slots_5.io.brupdate.b2.uop.uses_ldq, issue_slots[5].brupdate.b2.uop.uses_ldq connect slots_5.io.brupdate.b2.uop.mem_signed, issue_slots[5].brupdate.b2.uop.mem_signed connect slots_5.io.brupdate.b2.uop.mem_size, issue_slots[5].brupdate.b2.uop.mem_size connect slots_5.io.brupdate.b2.uop.mem_cmd, issue_slots[5].brupdate.b2.uop.mem_cmd connect slots_5.io.brupdate.b2.uop.exc_cause, issue_slots[5].brupdate.b2.uop.exc_cause connect slots_5.io.brupdate.b2.uop.exception, issue_slots[5].brupdate.b2.uop.exception connect slots_5.io.brupdate.b2.uop.stale_pdst, issue_slots[5].brupdate.b2.uop.stale_pdst connect slots_5.io.brupdate.b2.uop.ppred_busy, issue_slots[5].brupdate.b2.uop.ppred_busy connect slots_5.io.brupdate.b2.uop.prs3_busy, issue_slots[5].brupdate.b2.uop.prs3_busy connect slots_5.io.brupdate.b2.uop.prs2_busy, issue_slots[5].brupdate.b2.uop.prs2_busy connect slots_5.io.brupdate.b2.uop.prs1_busy, issue_slots[5].brupdate.b2.uop.prs1_busy connect slots_5.io.brupdate.b2.uop.ppred, issue_slots[5].brupdate.b2.uop.ppred connect slots_5.io.brupdate.b2.uop.prs3, issue_slots[5].brupdate.b2.uop.prs3 connect slots_5.io.brupdate.b2.uop.prs2, issue_slots[5].brupdate.b2.uop.prs2 connect slots_5.io.brupdate.b2.uop.prs1, issue_slots[5].brupdate.b2.uop.prs1 connect slots_5.io.brupdate.b2.uop.pdst, issue_slots[5].brupdate.b2.uop.pdst connect slots_5.io.brupdate.b2.uop.rxq_idx, issue_slots[5].brupdate.b2.uop.rxq_idx connect slots_5.io.brupdate.b2.uop.stq_idx, issue_slots[5].brupdate.b2.uop.stq_idx connect slots_5.io.brupdate.b2.uop.ldq_idx, issue_slots[5].brupdate.b2.uop.ldq_idx connect slots_5.io.brupdate.b2.uop.rob_idx, issue_slots[5].brupdate.b2.uop.rob_idx connect slots_5.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[5].brupdate.b2.uop.fp_ctrl.vec connect slots_5.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[5].brupdate.b2.uop.fp_ctrl.wflags connect slots_5.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[5].brupdate.b2.uop.fp_ctrl.sqrt connect slots_5.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[5].brupdate.b2.uop.fp_ctrl.div connect slots_5.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[5].brupdate.b2.uop.fp_ctrl.fma connect slots_5.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[5].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_5.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[5].brupdate.b2.uop.fp_ctrl.toint connect slots_5.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[5].brupdate.b2.uop.fp_ctrl.fromint connect slots_5.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_5.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_5.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[5].brupdate.b2.uop.fp_ctrl.swap23 connect slots_5.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[5].brupdate.b2.uop.fp_ctrl.swap12 connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren3 connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren2 connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren1 connect slots_5.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[5].brupdate.b2.uop.fp_ctrl.wen connect slots_5.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[5].brupdate.b2.uop.fp_ctrl.ldst connect slots_5.io.brupdate.b2.uop.op2_sel, issue_slots[5].brupdate.b2.uop.op2_sel connect slots_5.io.brupdate.b2.uop.op1_sel, issue_slots[5].brupdate.b2.uop.op1_sel connect slots_5.io.brupdate.b2.uop.imm_packed, issue_slots[5].brupdate.b2.uop.imm_packed connect slots_5.io.brupdate.b2.uop.pimm, issue_slots[5].brupdate.b2.uop.pimm connect slots_5.io.brupdate.b2.uop.imm_sel, issue_slots[5].brupdate.b2.uop.imm_sel connect slots_5.io.brupdate.b2.uop.imm_rename, issue_slots[5].brupdate.b2.uop.imm_rename connect slots_5.io.brupdate.b2.uop.taken, issue_slots[5].brupdate.b2.uop.taken connect slots_5.io.brupdate.b2.uop.pc_lob, issue_slots[5].brupdate.b2.uop.pc_lob connect slots_5.io.brupdate.b2.uop.edge_inst, issue_slots[5].brupdate.b2.uop.edge_inst connect slots_5.io.brupdate.b2.uop.ftq_idx, issue_slots[5].brupdate.b2.uop.ftq_idx connect slots_5.io.brupdate.b2.uop.is_mov, issue_slots[5].brupdate.b2.uop.is_mov connect slots_5.io.brupdate.b2.uop.is_rocc, issue_slots[5].brupdate.b2.uop.is_rocc connect slots_5.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[5].brupdate.b2.uop.is_sys_pc2epc connect slots_5.io.brupdate.b2.uop.is_eret, issue_slots[5].brupdate.b2.uop.is_eret connect slots_5.io.brupdate.b2.uop.is_amo, issue_slots[5].brupdate.b2.uop.is_amo connect slots_5.io.brupdate.b2.uop.is_sfence, issue_slots[5].brupdate.b2.uop.is_sfence connect slots_5.io.brupdate.b2.uop.is_fencei, issue_slots[5].brupdate.b2.uop.is_fencei connect slots_5.io.brupdate.b2.uop.is_fence, issue_slots[5].brupdate.b2.uop.is_fence connect slots_5.io.brupdate.b2.uop.is_sfb, issue_slots[5].brupdate.b2.uop.is_sfb connect slots_5.io.brupdate.b2.uop.br_type, issue_slots[5].brupdate.b2.uop.br_type connect slots_5.io.brupdate.b2.uop.br_tag, issue_slots[5].brupdate.b2.uop.br_tag connect slots_5.io.brupdate.b2.uop.br_mask, issue_slots[5].brupdate.b2.uop.br_mask connect slots_5.io.brupdate.b2.uop.dis_col_sel, issue_slots[5].brupdate.b2.uop.dis_col_sel connect slots_5.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p3_bypass_hint connect slots_5.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p2_bypass_hint connect slots_5.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p1_bypass_hint connect slots_5.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[5].brupdate.b2.uop.iw_p2_speculative_child connect slots_5.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[5].brupdate.b2.uop.iw_p1_speculative_child connect slots_5.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[5].brupdate.b2.uop.iw_issued_partial_dgen connect slots_5.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[5].brupdate.b2.uop.iw_issued_partial_agen connect slots_5.io.brupdate.b2.uop.iw_issued, issue_slots[5].brupdate.b2.uop.iw_issued connect slots_5.io.brupdate.b2.uop.fu_code[0], issue_slots[5].brupdate.b2.uop.fu_code[0] connect slots_5.io.brupdate.b2.uop.fu_code[1], issue_slots[5].brupdate.b2.uop.fu_code[1] connect slots_5.io.brupdate.b2.uop.fu_code[2], issue_slots[5].brupdate.b2.uop.fu_code[2] connect slots_5.io.brupdate.b2.uop.fu_code[3], issue_slots[5].brupdate.b2.uop.fu_code[3] connect slots_5.io.brupdate.b2.uop.fu_code[4], issue_slots[5].brupdate.b2.uop.fu_code[4] connect slots_5.io.brupdate.b2.uop.fu_code[5], issue_slots[5].brupdate.b2.uop.fu_code[5] connect slots_5.io.brupdate.b2.uop.fu_code[6], issue_slots[5].brupdate.b2.uop.fu_code[6] connect slots_5.io.brupdate.b2.uop.fu_code[7], issue_slots[5].brupdate.b2.uop.fu_code[7] connect slots_5.io.brupdate.b2.uop.fu_code[8], issue_slots[5].brupdate.b2.uop.fu_code[8] connect slots_5.io.brupdate.b2.uop.fu_code[9], issue_slots[5].brupdate.b2.uop.fu_code[9] connect slots_5.io.brupdate.b2.uop.iq_type[0], issue_slots[5].brupdate.b2.uop.iq_type[0] connect slots_5.io.brupdate.b2.uop.iq_type[1], issue_slots[5].brupdate.b2.uop.iq_type[1] connect slots_5.io.brupdate.b2.uop.iq_type[2], issue_slots[5].brupdate.b2.uop.iq_type[2] connect slots_5.io.brupdate.b2.uop.iq_type[3], issue_slots[5].brupdate.b2.uop.iq_type[3] connect slots_5.io.brupdate.b2.uop.debug_pc, issue_slots[5].brupdate.b2.uop.debug_pc connect slots_5.io.brupdate.b2.uop.is_rvc, issue_slots[5].brupdate.b2.uop.is_rvc connect slots_5.io.brupdate.b2.uop.debug_inst, issue_slots[5].brupdate.b2.uop.debug_inst connect slots_5.io.brupdate.b2.uop.inst, issue_slots[5].brupdate.b2.uop.inst connect slots_5.io.brupdate.b1.mispredict_mask, issue_slots[5].brupdate.b1.mispredict_mask connect slots_5.io.brupdate.b1.resolve_mask, issue_slots[5].brupdate.b1.resolve_mask connect issue_slots[5].out_uop.debug_tsrc, slots_5.io.out_uop.debug_tsrc connect issue_slots[5].out_uop.debug_fsrc, slots_5.io.out_uop.debug_fsrc connect issue_slots[5].out_uop.bp_xcpt_if, slots_5.io.out_uop.bp_xcpt_if connect issue_slots[5].out_uop.bp_debug_if, slots_5.io.out_uop.bp_debug_if connect issue_slots[5].out_uop.xcpt_ma_if, slots_5.io.out_uop.xcpt_ma_if connect issue_slots[5].out_uop.xcpt_ae_if, slots_5.io.out_uop.xcpt_ae_if connect issue_slots[5].out_uop.xcpt_pf_if, slots_5.io.out_uop.xcpt_pf_if connect issue_slots[5].out_uop.fp_typ, slots_5.io.out_uop.fp_typ connect issue_slots[5].out_uop.fp_rm, slots_5.io.out_uop.fp_rm connect issue_slots[5].out_uop.fp_val, slots_5.io.out_uop.fp_val connect issue_slots[5].out_uop.fcn_op, slots_5.io.out_uop.fcn_op connect issue_slots[5].out_uop.fcn_dw, slots_5.io.out_uop.fcn_dw connect issue_slots[5].out_uop.frs3_en, slots_5.io.out_uop.frs3_en connect issue_slots[5].out_uop.lrs2_rtype, slots_5.io.out_uop.lrs2_rtype connect issue_slots[5].out_uop.lrs1_rtype, slots_5.io.out_uop.lrs1_rtype connect issue_slots[5].out_uop.dst_rtype, slots_5.io.out_uop.dst_rtype connect issue_slots[5].out_uop.lrs3, slots_5.io.out_uop.lrs3 connect issue_slots[5].out_uop.lrs2, slots_5.io.out_uop.lrs2 connect issue_slots[5].out_uop.lrs1, slots_5.io.out_uop.lrs1 connect issue_slots[5].out_uop.ldst, slots_5.io.out_uop.ldst connect issue_slots[5].out_uop.ldst_is_rs1, slots_5.io.out_uop.ldst_is_rs1 connect issue_slots[5].out_uop.csr_cmd, slots_5.io.out_uop.csr_cmd connect issue_slots[5].out_uop.flush_on_commit, slots_5.io.out_uop.flush_on_commit connect issue_slots[5].out_uop.is_unique, slots_5.io.out_uop.is_unique connect issue_slots[5].out_uop.uses_stq, slots_5.io.out_uop.uses_stq connect issue_slots[5].out_uop.uses_ldq, slots_5.io.out_uop.uses_ldq connect issue_slots[5].out_uop.mem_signed, slots_5.io.out_uop.mem_signed connect issue_slots[5].out_uop.mem_size, slots_5.io.out_uop.mem_size connect issue_slots[5].out_uop.mem_cmd, slots_5.io.out_uop.mem_cmd connect issue_slots[5].out_uop.exc_cause, slots_5.io.out_uop.exc_cause connect issue_slots[5].out_uop.exception, slots_5.io.out_uop.exception connect issue_slots[5].out_uop.stale_pdst, slots_5.io.out_uop.stale_pdst connect issue_slots[5].out_uop.ppred_busy, slots_5.io.out_uop.ppred_busy connect issue_slots[5].out_uop.prs3_busy, slots_5.io.out_uop.prs3_busy connect issue_slots[5].out_uop.prs2_busy, slots_5.io.out_uop.prs2_busy connect issue_slots[5].out_uop.prs1_busy, slots_5.io.out_uop.prs1_busy connect issue_slots[5].out_uop.ppred, slots_5.io.out_uop.ppred connect issue_slots[5].out_uop.prs3, slots_5.io.out_uop.prs3 connect issue_slots[5].out_uop.prs2, slots_5.io.out_uop.prs2 connect issue_slots[5].out_uop.prs1, slots_5.io.out_uop.prs1 connect issue_slots[5].out_uop.pdst, slots_5.io.out_uop.pdst connect issue_slots[5].out_uop.rxq_idx, slots_5.io.out_uop.rxq_idx connect issue_slots[5].out_uop.stq_idx, slots_5.io.out_uop.stq_idx connect issue_slots[5].out_uop.ldq_idx, slots_5.io.out_uop.ldq_idx connect issue_slots[5].out_uop.rob_idx, slots_5.io.out_uop.rob_idx connect issue_slots[5].out_uop.fp_ctrl.vec, slots_5.io.out_uop.fp_ctrl.vec connect issue_slots[5].out_uop.fp_ctrl.wflags, slots_5.io.out_uop.fp_ctrl.wflags connect issue_slots[5].out_uop.fp_ctrl.sqrt, slots_5.io.out_uop.fp_ctrl.sqrt connect issue_slots[5].out_uop.fp_ctrl.div, slots_5.io.out_uop.fp_ctrl.div connect issue_slots[5].out_uop.fp_ctrl.fma, slots_5.io.out_uop.fp_ctrl.fma connect issue_slots[5].out_uop.fp_ctrl.fastpipe, slots_5.io.out_uop.fp_ctrl.fastpipe connect issue_slots[5].out_uop.fp_ctrl.toint, slots_5.io.out_uop.fp_ctrl.toint connect issue_slots[5].out_uop.fp_ctrl.fromint, slots_5.io.out_uop.fp_ctrl.fromint connect issue_slots[5].out_uop.fp_ctrl.typeTagOut, slots_5.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[5].out_uop.fp_ctrl.typeTagIn, slots_5.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[5].out_uop.fp_ctrl.swap23, slots_5.io.out_uop.fp_ctrl.swap23 connect issue_slots[5].out_uop.fp_ctrl.swap12, slots_5.io.out_uop.fp_ctrl.swap12 connect issue_slots[5].out_uop.fp_ctrl.ren3, slots_5.io.out_uop.fp_ctrl.ren3 connect issue_slots[5].out_uop.fp_ctrl.ren2, slots_5.io.out_uop.fp_ctrl.ren2 connect issue_slots[5].out_uop.fp_ctrl.ren1, slots_5.io.out_uop.fp_ctrl.ren1 connect issue_slots[5].out_uop.fp_ctrl.wen, slots_5.io.out_uop.fp_ctrl.wen connect issue_slots[5].out_uop.fp_ctrl.ldst, slots_5.io.out_uop.fp_ctrl.ldst connect issue_slots[5].out_uop.op2_sel, slots_5.io.out_uop.op2_sel connect issue_slots[5].out_uop.op1_sel, slots_5.io.out_uop.op1_sel connect issue_slots[5].out_uop.imm_packed, slots_5.io.out_uop.imm_packed connect issue_slots[5].out_uop.pimm, slots_5.io.out_uop.pimm connect issue_slots[5].out_uop.imm_sel, slots_5.io.out_uop.imm_sel connect issue_slots[5].out_uop.imm_rename, slots_5.io.out_uop.imm_rename connect issue_slots[5].out_uop.taken, slots_5.io.out_uop.taken connect issue_slots[5].out_uop.pc_lob, slots_5.io.out_uop.pc_lob connect issue_slots[5].out_uop.edge_inst, slots_5.io.out_uop.edge_inst connect issue_slots[5].out_uop.ftq_idx, slots_5.io.out_uop.ftq_idx connect issue_slots[5].out_uop.is_mov, slots_5.io.out_uop.is_mov connect issue_slots[5].out_uop.is_rocc, slots_5.io.out_uop.is_rocc connect issue_slots[5].out_uop.is_sys_pc2epc, slots_5.io.out_uop.is_sys_pc2epc connect issue_slots[5].out_uop.is_eret, slots_5.io.out_uop.is_eret connect issue_slots[5].out_uop.is_amo, slots_5.io.out_uop.is_amo connect issue_slots[5].out_uop.is_sfence, slots_5.io.out_uop.is_sfence connect issue_slots[5].out_uop.is_fencei, slots_5.io.out_uop.is_fencei connect issue_slots[5].out_uop.is_fence, slots_5.io.out_uop.is_fence connect issue_slots[5].out_uop.is_sfb, slots_5.io.out_uop.is_sfb connect issue_slots[5].out_uop.br_type, slots_5.io.out_uop.br_type connect issue_slots[5].out_uop.br_tag, slots_5.io.out_uop.br_tag connect issue_slots[5].out_uop.br_mask, slots_5.io.out_uop.br_mask connect issue_slots[5].out_uop.dis_col_sel, slots_5.io.out_uop.dis_col_sel connect issue_slots[5].out_uop.iw_p3_bypass_hint, slots_5.io.out_uop.iw_p3_bypass_hint connect issue_slots[5].out_uop.iw_p2_bypass_hint, slots_5.io.out_uop.iw_p2_bypass_hint connect issue_slots[5].out_uop.iw_p1_bypass_hint, slots_5.io.out_uop.iw_p1_bypass_hint connect issue_slots[5].out_uop.iw_p2_speculative_child, slots_5.io.out_uop.iw_p2_speculative_child connect issue_slots[5].out_uop.iw_p1_speculative_child, slots_5.io.out_uop.iw_p1_speculative_child connect issue_slots[5].out_uop.iw_issued_partial_dgen, slots_5.io.out_uop.iw_issued_partial_dgen connect issue_slots[5].out_uop.iw_issued_partial_agen, slots_5.io.out_uop.iw_issued_partial_agen connect issue_slots[5].out_uop.iw_issued, slots_5.io.out_uop.iw_issued connect issue_slots[5].out_uop.fu_code[0], slots_5.io.out_uop.fu_code[0] connect issue_slots[5].out_uop.fu_code[1], slots_5.io.out_uop.fu_code[1] connect issue_slots[5].out_uop.fu_code[2], slots_5.io.out_uop.fu_code[2] connect issue_slots[5].out_uop.fu_code[3], slots_5.io.out_uop.fu_code[3] connect issue_slots[5].out_uop.fu_code[4], slots_5.io.out_uop.fu_code[4] connect issue_slots[5].out_uop.fu_code[5], slots_5.io.out_uop.fu_code[5] connect issue_slots[5].out_uop.fu_code[6], slots_5.io.out_uop.fu_code[6] connect issue_slots[5].out_uop.fu_code[7], slots_5.io.out_uop.fu_code[7] connect issue_slots[5].out_uop.fu_code[8], slots_5.io.out_uop.fu_code[8] connect issue_slots[5].out_uop.fu_code[9], slots_5.io.out_uop.fu_code[9] connect issue_slots[5].out_uop.iq_type[0], slots_5.io.out_uop.iq_type[0] connect issue_slots[5].out_uop.iq_type[1], slots_5.io.out_uop.iq_type[1] connect issue_slots[5].out_uop.iq_type[2], slots_5.io.out_uop.iq_type[2] connect issue_slots[5].out_uop.iq_type[3], slots_5.io.out_uop.iq_type[3] connect issue_slots[5].out_uop.debug_pc, slots_5.io.out_uop.debug_pc connect issue_slots[5].out_uop.is_rvc, slots_5.io.out_uop.is_rvc connect issue_slots[5].out_uop.debug_inst, slots_5.io.out_uop.debug_inst connect issue_slots[5].out_uop.inst, slots_5.io.out_uop.inst connect slots_5.io.in_uop.bits.debug_tsrc, issue_slots[5].in_uop.bits.debug_tsrc connect slots_5.io.in_uop.bits.debug_fsrc, issue_slots[5].in_uop.bits.debug_fsrc connect slots_5.io.in_uop.bits.bp_xcpt_if, issue_slots[5].in_uop.bits.bp_xcpt_if connect slots_5.io.in_uop.bits.bp_debug_if, issue_slots[5].in_uop.bits.bp_debug_if connect slots_5.io.in_uop.bits.xcpt_ma_if, issue_slots[5].in_uop.bits.xcpt_ma_if connect slots_5.io.in_uop.bits.xcpt_ae_if, issue_slots[5].in_uop.bits.xcpt_ae_if connect slots_5.io.in_uop.bits.xcpt_pf_if, issue_slots[5].in_uop.bits.xcpt_pf_if connect slots_5.io.in_uop.bits.fp_typ, issue_slots[5].in_uop.bits.fp_typ connect slots_5.io.in_uop.bits.fp_rm, issue_slots[5].in_uop.bits.fp_rm connect slots_5.io.in_uop.bits.fp_val, issue_slots[5].in_uop.bits.fp_val connect slots_5.io.in_uop.bits.fcn_op, issue_slots[5].in_uop.bits.fcn_op connect slots_5.io.in_uop.bits.fcn_dw, issue_slots[5].in_uop.bits.fcn_dw connect slots_5.io.in_uop.bits.frs3_en, issue_slots[5].in_uop.bits.frs3_en connect slots_5.io.in_uop.bits.lrs2_rtype, issue_slots[5].in_uop.bits.lrs2_rtype connect slots_5.io.in_uop.bits.lrs1_rtype, issue_slots[5].in_uop.bits.lrs1_rtype connect slots_5.io.in_uop.bits.dst_rtype, issue_slots[5].in_uop.bits.dst_rtype connect slots_5.io.in_uop.bits.lrs3, issue_slots[5].in_uop.bits.lrs3 connect slots_5.io.in_uop.bits.lrs2, issue_slots[5].in_uop.bits.lrs2 connect slots_5.io.in_uop.bits.lrs1, issue_slots[5].in_uop.bits.lrs1 connect slots_5.io.in_uop.bits.ldst, issue_slots[5].in_uop.bits.ldst connect slots_5.io.in_uop.bits.ldst_is_rs1, issue_slots[5].in_uop.bits.ldst_is_rs1 connect slots_5.io.in_uop.bits.csr_cmd, issue_slots[5].in_uop.bits.csr_cmd connect slots_5.io.in_uop.bits.flush_on_commit, issue_slots[5].in_uop.bits.flush_on_commit connect slots_5.io.in_uop.bits.is_unique, issue_slots[5].in_uop.bits.is_unique connect slots_5.io.in_uop.bits.uses_stq, issue_slots[5].in_uop.bits.uses_stq connect slots_5.io.in_uop.bits.uses_ldq, issue_slots[5].in_uop.bits.uses_ldq connect slots_5.io.in_uop.bits.mem_signed, issue_slots[5].in_uop.bits.mem_signed connect slots_5.io.in_uop.bits.mem_size, issue_slots[5].in_uop.bits.mem_size connect slots_5.io.in_uop.bits.mem_cmd, issue_slots[5].in_uop.bits.mem_cmd connect slots_5.io.in_uop.bits.exc_cause, issue_slots[5].in_uop.bits.exc_cause connect slots_5.io.in_uop.bits.exception, issue_slots[5].in_uop.bits.exception connect slots_5.io.in_uop.bits.stale_pdst, issue_slots[5].in_uop.bits.stale_pdst connect slots_5.io.in_uop.bits.ppred_busy, issue_slots[5].in_uop.bits.ppred_busy connect slots_5.io.in_uop.bits.prs3_busy, issue_slots[5].in_uop.bits.prs3_busy connect slots_5.io.in_uop.bits.prs2_busy, issue_slots[5].in_uop.bits.prs2_busy connect slots_5.io.in_uop.bits.prs1_busy, issue_slots[5].in_uop.bits.prs1_busy connect slots_5.io.in_uop.bits.ppred, issue_slots[5].in_uop.bits.ppred connect slots_5.io.in_uop.bits.prs3, issue_slots[5].in_uop.bits.prs3 connect slots_5.io.in_uop.bits.prs2, issue_slots[5].in_uop.bits.prs2 connect slots_5.io.in_uop.bits.prs1, issue_slots[5].in_uop.bits.prs1 connect slots_5.io.in_uop.bits.pdst, issue_slots[5].in_uop.bits.pdst connect slots_5.io.in_uop.bits.rxq_idx, issue_slots[5].in_uop.bits.rxq_idx connect slots_5.io.in_uop.bits.stq_idx, issue_slots[5].in_uop.bits.stq_idx connect slots_5.io.in_uop.bits.ldq_idx, issue_slots[5].in_uop.bits.ldq_idx connect slots_5.io.in_uop.bits.rob_idx, issue_slots[5].in_uop.bits.rob_idx connect slots_5.io.in_uop.bits.fp_ctrl.vec, issue_slots[5].in_uop.bits.fp_ctrl.vec connect slots_5.io.in_uop.bits.fp_ctrl.wflags, issue_slots[5].in_uop.bits.fp_ctrl.wflags connect slots_5.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[5].in_uop.bits.fp_ctrl.sqrt connect slots_5.io.in_uop.bits.fp_ctrl.div, issue_slots[5].in_uop.bits.fp_ctrl.div connect slots_5.io.in_uop.bits.fp_ctrl.fma, issue_slots[5].in_uop.bits.fp_ctrl.fma connect slots_5.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].in_uop.bits.fp_ctrl.fastpipe connect slots_5.io.in_uop.bits.fp_ctrl.toint, issue_slots[5].in_uop.bits.fp_ctrl.toint connect slots_5.io.in_uop.bits.fp_ctrl.fromint, issue_slots[5].in_uop.bits.fp_ctrl.fromint connect slots_5.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut connect slots_5.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn connect slots_5.io.in_uop.bits.fp_ctrl.swap23, issue_slots[5].in_uop.bits.fp_ctrl.swap23 connect slots_5.io.in_uop.bits.fp_ctrl.swap12, issue_slots[5].in_uop.bits.fp_ctrl.swap12 connect slots_5.io.in_uop.bits.fp_ctrl.ren3, issue_slots[5].in_uop.bits.fp_ctrl.ren3 connect slots_5.io.in_uop.bits.fp_ctrl.ren2, issue_slots[5].in_uop.bits.fp_ctrl.ren2 connect slots_5.io.in_uop.bits.fp_ctrl.ren1, issue_slots[5].in_uop.bits.fp_ctrl.ren1 connect slots_5.io.in_uop.bits.fp_ctrl.wen, issue_slots[5].in_uop.bits.fp_ctrl.wen connect slots_5.io.in_uop.bits.fp_ctrl.ldst, issue_slots[5].in_uop.bits.fp_ctrl.ldst connect slots_5.io.in_uop.bits.op2_sel, issue_slots[5].in_uop.bits.op2_sel connect slots_5.io.in_uop.bits.op1_sel, issue_slots[5].in_uop.bits.op1_sel connect slots_5.io.in_uop.bits.imm_packed, issue_slots[5].in_uop.bits.imm_packed connect slots_5.io.in_uop.bits.pimm, issue_slots[5].in_uop.bits.pimm connect slots_5.io.in_uop.bits.imm_sel, issue_slots[5].in_uop.bits.imm_sel connect slots_5.io.in_uop.bits.imm_rename, issue_slots[5].in_uop.bits.imm_rename connect slots_5.io.in_uop.bits.taken, issue_slots[5].in_uop.bits.taken connect slots_5.io.in_uop.bits.pc_lob, issue_slots[5].in_uop.bits.pc_lob connect slots_5.io.in_uop.bits.edge_inst, issue_slots[5].in_uop.bits.edge_inst connect slots_5.io.in_uop.bits.ftq_idx, issue_slots[5].in_uop.bits.ftq_idx connect slots_5.io.in_uop.bits.is_mov, issue_slots[5].in_uop.bits.is_mov connect slots_5.io.in_uop.bits.is_rocc, issue_slots[5].in_uop.bits.is_rocc connect slots_5.io.in_uop.bits.is_sys_pc2epc, issue_slots[5].in_uop.bits.is_sys_pc2epc connect slots_5.io.in_uop.bits.is_eret, issue_slots[5].in_uop.bits.is_eret connect slots_5.io.in_uop.bits.is_amo, issue_slots[5].in_uop.bits.is_amo connect slots_5.io.in_uop.bits.is_sfence, issue_slots[5].in_uop.bits.is_sfence connect slots_5.io.in_uop.bits.is_fencei, issue_slots[5].in_uop.bits.is_fencei connect slots_5.io.in_uop.bits.is_fence, issue_slots[5].in_uop.bits.is_fence connect slots_5.io.in_uop.bits.is_sfb, issue_slots[5].in_uop.bits.is_sfb connect slots_5.io.in_uop.bits.br_type, issue_slots[5].in_uop.bits.br_type connect slots_5.io.in_uop.bits.br_tag, issue_slots[5].in_uop.bits.br_tag connect slots_5.io.in_uop.bits.br_mask, issue_slots[5].in_uop.bits.br_mask connect slots_5.io.in_uop.bits.dis_col_sel, issue_slots[5].in_uop.bits.dis_col_sel connect slots_5.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[5].in_uop.bits.iw_p3_bypass_hint connect slots_5.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[5].in_uop.bits.iw_p2_bypass_hint connect slots_5.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[5].in_uop.bits.iw_p1_bypass_hint connect slots_5.io.in_uop.bits.iw_p2_speculative_child, issue_slots[5].in_uop.bits.iw_p2_speculative_child connect slots_5.io.in_uop.bits.iw_p1_speculative_child, issue_slots[5].in_uop.bits.iw_p1_speculative_child connect slots_5.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[5].in_uop.bits.iw_issued_partial_dgen connect slots_5.io.in_uop.bits.iw_issued_partial_agen, issue_slots[5].in_uop.bits.iw_issued_partial_agen connect slots_5.io.in_uop.bits.iw_issued, issue_slots[5].in_uop.bits.iw_issued connect slots_5.io.in_uop.bits.fu_code[0], issue_slots[5].in_uop.bits.fu_code[0] connect slots_5.io.in_uop.bits.fu_code[1], issue_slots[5].in_uop.bits.fu_code[1] connect slots_5.io.in_uop.bits.fu_code[2], issue_slots[5].in_uop.bits.fu_code[2] connect slots_5.io.in_uop.bits.fu_code[3], issue_slots[5].in_uop.bits.fu_code[3] connect slots_5.io.in_uop.bits.fu_code[4], issue_slots[5].in_uop.bits.fu_code[4] connect slots_5.io.in_uop.bits.fu_code[5], issue_slots[5].in_uop.bits.fu_code[5] connect slots_5.io.in_uop.bits.fu_code[6], issue_slots[5].in_uop.bits.fu_code[6] connect slots_5.io.in_uop.bits.fu_code[7], issue_slots[5].in_uop.bits.fu_code[7] connect slots_5.io.in_uop.bits.fu_code[8], issue_slots[5].in_uop.bits.fu_code[8] connect slots_5.io.in_uop.bits.fu_code[9], issue_slots[5].in_uop.bits.fu_code[9] connect slots_5.io.in_uop.bits.iq_type[0], issue_slots[5].in_uop.bits.iq_type[0] connect slots_5.io.in_uop.bits.iq_type[1], issue_slots[5].in_uop.bits.iq_type[1] connect slots_5.io.in_uop.bits.iq_type[2], issue_slots[5].in_uop.bits.iq_type[2] connect slots_5.io.in_uop.bits.iq_type[3], issue_slots[5].in_uop.bits.iq_type[3] connect slots_5.io.in_uop.bits.debug_pc, issue_slots[5].in_uop.bits.debug_pc connect slots_5.io.in_uop.bits.is_rvc, issue_slots[5].in_uop.bits.is_rvc connect slots_5.io.in_uop.bits.debug_inst, issue_slots[5].in_uop.bits.debug_inst connect slots_5.io.in_uop.bits.inst, issue_slots[5].in_uop.bits.inst connect slots_5.io.in_uop.valid, issue_slots[5].in_uop.valid connect issue_slots[5].iss_uop.debug_tsrc, slots_5.io.iss_uop.debug_tsrc connect issue_slots[5].iss_uop.debug_fsrc, slots_5.io.iss_uop.debug_fsrc connect issue_slots[5].iss_uop.bp_xcpt_if, slots_5.io.iss_uop.bp_xcpt_if connect issue_slots[5].iss_uop.bp_debug_if, slots_5.io.iss_uop.bp_debug_if connect issue_slots[5].iss_uop.xcpt_ma_if, slots_5.io.iss_uop.xcpt_ma_if connect issue_slots[5].iss_uop.xcpt_ae_if, slots_5.io.iss_uop.xcpt_ae_if connect issue_slots[5].iss_uop.xcpt_pf_if, slots_5.io.iss_uop.xcpt_pf_if connect issue_slots[5].iss_uop.fp_typ, slots_5.io.iss_uop.fp_typ connect issue_slots[5].iss_uop.fp_rm, slots_5.io.iss_uop.fp_rm connect issue_slots[5].iss_uop.fp_val, slots_5.io.iss_uop.fp_val connect issue_slots[5].iss_uop.fcn_op, slots_5.io.iss_uop.fcn_op connect issue_slots[5].iss_uop.fcn_dw, slots_5.io.iss_uop.fcn_dw connect issue_slots[5].iss_uop.frs3_en, slots_5.io.iss_uop.frs3_en connect issue_slots[5].iss_uop.lrs2_rtype, slots_5.io.iss_uop.lrs2_rtype connect issue_slots[5].iss_uop.lrs1_rtype, slots_5.io.iss_uop.lrs1_rtype connect issue_slots[5].iss_uop.dst_rtype, slots_5.io.iss_uop.dst_rtype connect issue_slots[5].iss_uop.lrs3, slots_5.io.iss_uop.lrs3 connect issue_slots[5].iss_uop.lrs2, slots_5.io.iss_uop.lrs2 connect issue_slots[5].iss_uop.lrs1, slots_5.io.iss_uop.lrs1 connect issue_slots[5].iss_uop.ldst, slots_5.io.iss_uop.ldst connect issue_slots[5].iss_uop.ldst_is_rs1, slots_5.io.iss_uop.ldst_is_rs1 connect issue_slots[5].iss_uop.csr_cmd, slots_5.io.iss_uop.csr_cmd connect issue_slots[5].iss_uop.flush_on_commit, slots_5.io.iss_uop.flush_on_commit connect issue_slots[5].iss_uop.is_unique, slots_5.io.iss_uop.is_unique connect issue_slots[5].iss_uop.uses_stq, slots_5.io.iss_uop.uses_stq connect issue_slots[5].iss_uop.uses_ldq, slots_5.io.iss_uop.uses_ldq connect issue_slots[5].iss_uop.mem_signed, slots_5.io.iss_uop.mem_signed connect issue_slots[5].iss_uop.mem_size, slots_5.io.iss_uop.mem_size connect issue_slots[5].iss_uop.mem_cmd, slots_5.io.iss_uop.mem_cmd connect issue_slots[5].iss_uop.exc_cause, slots_5.io.iss_uop.exc_cause connect issue_slots[5].iss_uop.exception, slots_5.io.iss_uop.exception connect issue_slots[5].iss_uop.stale_pdst, slots_5.io.iss_uop.stale_pdst connect issue_slots[5].iss_uop.ppred_busy, slots_5.io.iss_uop.ppred_busy connect issue_slots[5].iss_uop.prs3_busy, slots_5.io.iss_uop.prs3_busy connect issue_slots[5].iss_uop.prs2_busy, slots_5.io.iss_uop.prs2_busy connect issue_slots[5].iss_uop.prs1_busy, slots_5.io.iss_uop.prs1_busy connect issue_slots[5].iss_uop.ppred, slots_5.io.iss_uop.ppred connect issue_slots[5].iss_uop.prs3, slots_5.io.iss_uop.prs3 connect issue_slots[5].iss_uop.prs2, slots_5.io.iss_uop.prs2 connect issue_slots[5].iss_uop.prs1, slots_5.io.iss_uop.prs1 connect issue_slots[5].iss_uop.pdst, slots_5.io.iss_uop.pdst connect issue_slots[5].iss_uop.rxq_idx, slots_5.io.iss_uop.rxq_idx connect issue_slots[5].iss_uop.stq_idx, slots_5.io.iss_uop.stq_idx connect issue_slots[5].iss_uop.ldq_idx, slots_5.io.iss_uop.ldq_idx connect issue_slots[5].iss_uop.rob_idx, slots_5.io.iss_uop.rob_idx connect issue_slots[5].iss_uop.fp_ctrl.vec, slots_5.io.iss_uop.fp_ctrl.vec connect issue_slots[5].iss_uop.fp_ctrl.wflags, slots_5.io.iss_uop.fp_ctrl.wflags connect issue_slots[5].iss_uop.fp_ctrl.sqrt, slots_5.io.iss_uop.fp_ctrl.sqrt connect issue_slots[5].iss_uop.fp_ctrl.div, slots_5.io.iss_uop.fp_ctrl.div connect issue_slots[5].iss_uop.fp_ctrl.fma, slots_5.io.iss_uop.fp_ctrl.fma connect issue_slots[5].iss_uop.fp_ctrl.fastpipe, slots_5.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[5].iss_uop.fp_ctrl.toint, slots_5.io.iss_uop.fp_ctrl.toint connect issue_slots[5].iss_uop.fp_ctrl.fromint, slots_5.io.iss_uop.fp_ctrl.fromint connect issue_slots[5].iss_uop.fp_ctrl.typeTagOut, slots_5.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[5].iss_uop.fp_ctrl.typeTagIn, slots_5.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[5].iss_uop.fp_ctrl.swap23, slots_5.io.iss_uop.fp_ctrl.swap23 connect issue_slots[5].iss_uop.fp_ctrl.swap12, slots_5.io.iss_uop.fp_ctrl.swap12 connect issue_slots[5].iss_uop.fp_ctrl.ren3, slots_5.io.iss_uop.fp_ctrl.ren3 connect issue_slots[5].iss_uop.fp_ctrl.ren2, slots_5.io.iss_uop.fp_ctrl.ren2 connect issue_slots[5].iss_uop.fp_ctrl.ren1, slots_5.io.iss_uop.fp_ctrl.ren1 connect issue_slots[5].iss_uop.fp_ctrl.wen, slots_5.io.iss_uop.fp_ctrl.wen connect issue_slots[5].iss_uop.fp_ctrl.ldst, slots_5.io.iss_uop.fp_ctrl.ldst connect issue_slots[5].iss_uop.op2_sel, slots_5.io.iss_uop.op2_sel connect issue_slots[5].iss_uop.op1_sel, slots_5.io.iss_uop.op1_sel connect issue_slots[5].iss_uop.imm_packed, slots_5.io.iss_uop.imm_packed connect issue_slots[5].iss_uop.pimm, slots_5.io.iss_uop.pimm connect issue_slots[5].iss_uop.imm_sel, slots_5.io.iss_uop.imm_sel connect issue_slots[5].iss_uop.imm_rename, slots_5.io.iss_uop.imm_rename connect issue_slots[5].iss_uop.taken, slots_5.io.iss_uop.taken connect issue_slots[5].iss_uop.pc_lob, slots_5.io.iss_uop.pc_lob connect issue_slots[5].iss_uop.edge_inst, slots_5.io.iss_uop.edge_inst connect issue_slots[5].iss_uop.ftq_idx, slots_5.io.iss_uop.ftq_idx connect issue_slots[5].iss_uop.is_mov, slots_5.io.iss_uop.is_mov connect issue_slots[5].iss_uop.is_rocc, slots_5.io.iss_uop.is_rocc connect issue_slots[5].iss_uop.is_sys_pc2epc, slots_5.io.iss_uop.is_sys_pc2epc connect issue_slots[5].iss_uop.is_eret, slots_5.io.iss_uop.is_eret connect issue_slots[5].iss_uop.is_amo, slots_5.io.iss_uop.is_amo connect issue_slots[5].iss_uop.is_sfence, slots_5.io.iss_uop.is_sfence connect issue_slots[5].iss_uop.is_fencei, slots_5.io.iss_uop.is_fencei connect issue_slots[5].iss_uop.is_fence, slots_5.io.iss_uop.is_fence connect issue_slots[5].iss_uop.is_sfb, slots_5.io.iss_uop.is_sfb connect issue_slots[5].iss_uop.br_type, slots_5.io.iss_uop.br_type connect issue_slots[5].iss_uop.br_tag, slots_5.io.iss_uop.br_tag connect issue_slots[5].iss_uop.br_mask, slots_5.io.iss_uop.br_mask connect issue_slots[5].iss_uop.dis_col_sel, slots_5.io.iss_uop.dis_col_sel connect issue_slots[5].iss_uop.iw_p3_bypass_hint, slots_5.io.iss_uop.iw_p3_bypass_hint connect issue_slots[5].iss_uop.iw_p2_bypass_hint, slots_5.io.iss_uop.iw_p2_bypass_hint connect issue_slots[5].iss_uop.iw_p1_bypass_hint, slots_5.io.iss_uop.iw_p1_bypass_hint connect issue_slots[5].iss_uop.iw_p2_speculative_child, slots_5.io.iss_uop.iw_p2_speculative_child connect issue_slots[5].iss_uop.iw_p1_speculative_child, slots_5.io.iss_uop.iw_p1_speculative_child connect issue_slots[5].iss_uop.iw_issued_partial_dgen, slots_5.io.iss_uop.iw_issued_partial_dgen connect issue_slots[5].iss_uop.iw_issued_partial_agen, slots_5.io.iss_uop.iw_issued_partial_agen connect issue_slots[5].iss_uop.iw_issued, slots_5.io.iss_uop.iw_issued connect issue_slots[5].iss_uop.fu_code[0], slots_5.io.iss_uop.fu_code[0] connect issue_slots[5].iss_uop.fu_code[1], slots_5.io.iss_uop.fu_code[1] connect issue_slots[5].iss_uop.fu_code[2], slots_5.io.iss_uop.fu_code[2] connect issue_slots[5].iss_uop.fu_code[3], slots_5.io.iss_uop.fu_code[3] connect issue_slots[5].iss_uop.fu_code[4], slots_5.io.iss_uop.fu_code[4] connect issue_slots[5].iss_uop.fu_code[5], slots_5.io.iss_uop.fu_code[5] connect issue_slots[5].iss_uop.fu_code[6], slots_5.io.iss_uop.fu_code[6] connect issue_slots[5].iss_uop.fu_code[7], slots_5.io.iss_uop.fu_code[7] connect issue_slots[5].iss_uop.fu_code[8], slots_5.io.iss_uop.fu_code[8] connect issue_slots[5].iss_uop.fu_code[9], slots_5.io.iss_uop.fu_code[9] connect issue_slots[5].iss_uop.iq_type[0], slots_5.io.iss_uop.iq_type[0] connect issue_slots[5].iss_uop.iq_type[1], slots_5.io.iss_uop.iq_type[1] connect issue_slots[5].iss_uop.iq_type[2], slots_5.io.iss_uop.iq_type[2] connect issue_slots[5].iss_uop.iq_type[3], slots_5.io.iss_uop.iq_type[3] connect issue_slots[5].iss_uop.debug_pc, slots_5.io.iss_uop.debug_pc connect issue_slots[5].iss_uop.is_rvc, slots_5.io.iss_uop.is_rvc connect issue_slots[5].iss_uop.debug_inst, slots_5.io.iss_uop.debug_inst connect issue_slots[5].iss_uop.inst, slots_5.io.iss_uop.inst connect slots_5.io.grant, issue_slots[5].grant connect issue_slots[5].request, slots_5.io.request connect issue_slots[5].will_be_valid, slots_5.io.will_be_valid connect issue_slots[5].valid, slots_5.io.valid connect slots_6.io.child_rebusys, issue_slots[6].child_rebusys connect slots_6.io.pred_wakeup_port.bits, issue_slots[6].pred_wakeup_port.bits connect slots_6.io.pred_wakeup_port.valid, issue_slots[6].pred_wakeup_port.valid connect slots_6.io.wakeup_ports[0].bits.rebusy, issue_slots[6].wakeup_ports[0].bits.rebusy connect slots_6.io.wakeup_ports[0].bits.speculative_mask, issue_slots[6].wakeup_ports[0].bits.speculative_mask connect slots_6.io.wakeup_ports[0].bits.bypassable, issue_slots[6].wakeup_ports[0].bits.bypassable connect slots_6.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[0].bits.uop.debug_tsrc connect slots_6.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[0].bits.uop.debug_fsrc connect slots_6.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_6.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[0].bits.uop.bp_debug_if connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_6.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[6].wakeup_ports[0].bits.uop.fp_typ connect slots_6.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[6].wakeup_ports[0].bits.uop.fp_rm connect slots_6.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[6].wakeup_ports[0].bits.uop.fp_val connect slots_6.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[6].wakeup_ports[0].bits.uop.fcn_op connect slots_6.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[0].bits.uop.fcn_dw connect slots_6.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[6].wakeup_ports[0].bits.uop.frs3_en connect slots_6.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_6.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_6.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[0].bits.uop.dst_rtype connect slots_6.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[6].wakeup_ports[0].bits.uop.lrs3 connect slots_6.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[6].wakeup_ports[0].bits.uop.lrs2 connect slots_6.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[6].wakeup_ports[0].bits.uop.lrs1 connect slots_6.io.wakeup_ports[0].bits.uop.ldst, issue_slots[6].wakeup_ports[0].bits.uop.ldst connect slots_6.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_6.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[0].bits.uop.csr_cmd connect slots_6.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[0].bits.uop.flush_on_commit connect slots_6.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[6].wakeup_ports[0].bits.uop.is_unique connect slots_6.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[6].wakeup_ports[0].bits.uop.uses_stq connect slots_6.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[0].bits.uop.uses_ldq connect slots_6.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[6].wakeup_ports[0].bits.uop.mem_signed connect slots_6.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[6].wakeup_ports[0].bits.uop.mem_size connect slots_6.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[0].bits.uop.mem_cmd connect slots_6.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[6].wakeup_ports[0].bits.uop.exc_cause connect slots_6.io.wakeup_ports[0].bits.uop.exception, issue_slots[6].wakeup_ports[0].bits.uop.exception connect slots_6.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[0].bits.uop.stale_pdst connect slots_6.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[0].bits.uop.ppred_busy connect slots_6.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs3_busy connect slots_6.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs2_busy connect slots_6.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs1_busy connect slots_6.io.wakeup_ports[0].bits.uop.ppred, issue_slots[6].wakeup_ports[0].bits.uop.ppred connect slots_6.io.wakeup_ports[0].bits.uop.prs3, issue_slots[6].wakeup_ports[0].bits.uop.prs3 connect slots_6.io.wakeup_ports[0].bits.uop.prs2, issue_slots[6].wakeup_ports[0].bits.uop.prs2 connect slots_6.io.wakeup_ports[0].bits.uop.prs1, issue_slots[6].wakeup_ports[0].bits.uop.prs1 connect slots_6.io.wakeup_ports[0].bits.uop.pdst, issue_slots[6].wakeup_ports[0].bits.uop.pdst connect slots_6.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[0].bits.uop.rxq_idx connect slots_6.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[6].wakeup_ports[0].bits.uop.stq_idx connect slots_6.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[0].bits.uop.ldq_idx connect slots_6.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[6].wakeup_ports[0].bits.uop.rob_idx connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_6.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[6].wakeup_ports[0].bits.uop.op2_sel connect slots_6.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[6].wakeup_ports[0].bits.uop.op1_sel connect slots_6.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[6].wakeup_ports[0].bits.uop.imm_packed connect slots_6.io.wakeup_ports[0].bits.uop.pimm, issue_slots[6].wakeup_ports[0].bits.uop.pimm connect slots_6.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[6].wakeup_ports[0].bits.uop.imm_sel connect slots_6.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[6].wakeup_ports[0].bits.uop.imm_rename connect slots_6.io.wakeup_ports[0].bits.uop.taken, issue_slots[6].wakeup_ports[0].bits.uop.taken connect slots_6.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[6].wakeup_ports[0].bits.uop.pc_lob connect slots_6.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[6].wakeup_ports[0].bits.uop.edge_inst connect slots_6.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[0].bits.uop.ftq_idx connect slots_6.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[6].wakeup_ports[0].bits.uop.is_mov connect slots_6.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[6].wakeup_ports[0].bits.uop.is_rocc connect slots_6.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_6.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[6].wakeup_ports[0].bits.uop.is_eret connect slots_6.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[6].wakeup_ports[0].bits.uop.is_amo connect slots_6.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[6].wakeup_ports[0].bits.uop.is_sfence connect slots_6.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[6].wakeup_ports[0].bits.uop.is_fencei connect slots_6.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[6].wakeup_ports[0].bits.uop.is_fence connect slots_6.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[6].wakeup_ports[0].bits.uop.is_sfb connect slots_6.io.wakeup_ports[0].bits.uop.br_type, issue_slots[6].wakeup_ports[0].bits.uop.br_type connect slots_6.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[6].wakeup_ports[0].bits.uop.br_tag connect slots_6.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[6].wakeup_ports[0].bits.uop.br_mask connect slots_6.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[0].bits.uop.dis_col_sel connect slots_6.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_6.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_6.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_6.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_6.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[0] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[1] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[2] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[3] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[4] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[5] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[6] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[7] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[8] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[9] connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[0] connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[1] connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[2] connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[3] connect slots_6.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[6].wakeup_ports[0].bits.uop.debug_pc connect slots_6.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[6].wakeup_ports[0].bits.uop.is_rvc connect slots_6.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[6].wakeup_ports[0].bits.uop.debug_inst connect slots_6.io.wakeup_ports[0].bits.uop.inst, issue_slots[6].wakeup_ports[0].bits.uop.inst connect slots_6.io.wakeup_ports[0].valid, issue_slots[6].wakeup_ports[0].valid connect slots_6.io.wakeup_ports[1].bits.rebusy, issue_slots[6].wakeup_ports[1].bits.rebusy connect slots_6.io.wakeup_ports[1].bits.speculative_mask, issue_slots[6].wakeup_ports[1].bits.speculative_mask connect slots_6.io.wakeup_ports[1].bits.bypassable, issue_slots[6].wakeup_ports[1].bits.bypassable connect slots_6.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[1].bits.uop.debug_tsrc connect slots_6.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[1].bits.uop.debug_fsrc connect slots_6.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_6.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[1].bits.uop.bp_debug_if connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_6.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[6].wakeup_ports[1].bits.uop.fp_typ connect slots_6.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[6].wakeup_ports[1].bits.uop.fp_rm connect slots_6.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[6].wakeup_ports[1].bits.uop.fp_val connect slots_6.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[6].wakeup_ports[1].bits.uop.fcn_op connect slots_6.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[1].bits.uop.fcn_dw connect slots_6.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[6].wakeup_ports[1].bits.uop.frs3_en connect slots_6.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_6.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_6.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[1].bits.uop.dst_rtype connect slots_6.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[6].wakeup_ports[1].bits.uop.lrs3 connect slots_6.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[6].wakeup_ports[1].bits.uop.lrs2 connect slots_6.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[6].wakeup_ports[1].bits.uop.lrs1 connect slots_6.io.wakeup_ports[1].bits.uop.ldst, issue_slots[6].wakeup_ports[1].bits.uop.ldst connect slots_6.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_6.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[1].bits.uop.csr_cmd connect slots_6.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[1].bits.uop.flush_on_commit connect slots_6.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[6].wakeup_ports[1].bits.uop.is_unique connect slots_6.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[6].wakeup_ports[1].bits.uop.uses_stq connect slots_6.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[1].bits.uop.uses_ldq connect slots_6.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[6].wakeup_ports[1].bits.uop.mem_signed connect slots_6.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[6].wakeup_ports[1].bits.uop.mem_size connect slots_6.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[1].bits.uop.mem_cmd connect slots_6.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[6].wakeup_ports[1].bits.uop.exc_cause connect slots_6.io.wakeup_ports[1].bits.uop.exception, issue_slots[6].wakeup_ports[1].bits.uop.exception connect slots_6.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[1].bits.uop.stale_pdst connect slots_6.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[1].bits.uop.ppred_busy connect slots_6.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs3_busy connect slots_6.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs2_busy connect slots_6.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs1_busy connect slots_6.io.wakeup_ports[1].bits.uop.ppred, issue_slots[6].wakeup_ports[1].bits.uop.ppred connect slots_6.io.wakeup_ports[1].bits.uop.prs3, issue_slots[6].wakeup_ports[1].bits.uop.prs3 connect slots_6.io.wakeup_ports[1].bits.uop.prs2, issue_slots[6].wakeup_ports[1].bits.uop.prs2 connect slots_6.io.wakeup_ports[1].bits.uop.prs1, issue_slots[6].wakeup_ports[1].bits.uop.prs1 connect slots_6.io.wakeup_ports[1].bits.uop.pdst, issue_slots[6].wakeup_ports[1].bits.uop.pdst connect slots_6.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[1].bits.uop.rxq_idx connect slots_6.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[6].wakeup_ports[1].bits.uop.stq_idx connect slots_6.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[1].bits.uop.ldq_idx connect slots_6.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[6].wakeup_ports[1].bits.uop.rob_idx connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_6.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[6].wakeup_ports[1].bits.uop.op2_sel connect slots_6.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[6].wakeup_ports[1].bits.uop.op1_sel connect slots_6.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[6].wakeup_ports[1].bits.uop.imm_packed connect slots_6.io.wakeup_ports[1].bits.uop.pimm, issue_slots[6].wakeup_ports[1].bits.uop.pimm connect slots_6.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[6].wakeup_ports[1].bits.uop.imm_sel connect slots_6.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[6].wakeup_ports[1].bits.uop.imm_rename connect slots_6.io.wakeup_ports[1].bits.uop.taken, issue_slots[6].wakeup_ports[1].bits.uop.taken connect slots_6.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[6].wakeup_ports[1].bits.uop.pc_lob connect slots_6.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[6].wakeup_ports[1].bits.uop.edge_inst connect slots_6.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[1].bits.uop.ftq_idx connect slots_6.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[6].wakeup_ports[1].bits.uop.is_mov connect slots_6.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[6].wakeup_ports[1].bits.uop.is_rocc connect slots_6.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_6.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[6].wakeup_ports[1].bits.uop.is_eret connect slots_6.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[6].wakeup_ports[1].bits.uop.is_amo connect slots_6.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[6].wakeup_ports[1].bits.uop.is_sfence connect slots_6.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[6].wakeup_ports[1].bits.uop.is_fencei connect slots_6.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[6].wakeup_ports[1].bits.uop.is_fence connect slots_6.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[6].wakeup_ports[1].bits.uop.is_sfb connect slots_6.io.wakeup_ports[1].bits.uop.br_type, issue_slots[6].wakeup_ports[1].bits.uop.br_type connect slots_6.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[6].wakeup_ports[1].bits.uop.br_tag connect slots_6.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[6].wakeup_ports[1].bits.uop.br_mask connect slots_6.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[1].bits.uop.dis_col_sel connect slots_6.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_6.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_6.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_6.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_6.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[0] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[1] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[2] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[3] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[4] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[5] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[6] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[7] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[8] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[9] connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[0] connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[1] connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[2] connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[3] connect slots_6.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[6].wakeup_ports[1].bits.uop.debug_pc connect slots_6.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[6].wakeup_ports[1].bits.uop.is_rvc connect slots_6.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[6].wakeup_ports[1].bits.uop.debug_inst connect slots_6.io.wakeup_ports[1].bits.uop.inst, issue_slots[6].wakeup_ports[1].bits.uop.inst connect slots_6.io.wakeup_ports[1].valid, issue_slots[6].wakeup_ports[1].valid connect slots_6.io.wakeup_ports[2].bits.rebusy, issue_slots[6].wakeup_ports[2].bits.rebusy connect slots_6.io.wakeup_ports[2].bits.speculative_mask, issue_slots[6].wakeup_ports[2].bits.speculative_mask connect slots_6.io.wakeup_ports[2].bits.bypassable, issue_slots[6].wakeup_ports[2].bits.bypassable connect slots_6.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[2].bits.uop.debug_tsrc connect slots_6.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[2].bits.uop.debug_fsrc connect slots_6.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_6.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[2].bits.uop.bp_debug_if connect slots_6.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_6.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_6.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_6.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[6].wakeup_ports[2].bits.uop.fp_typ connect slots_6.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[6].wakeup_ports[2].bits.uop.fp_rm connect slots_6.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[6].wakeup_ports[2].bits.uop.fp_val connect slots_6.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[6].wakeup_ports[2].bits.uop.fcn_op connect slots_6.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[2].bits.uop.fcn_dw connect slots_6.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[6].wakeup_ports[2].bits.uop.frs3_en connect slots_6.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_6.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_6.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[2].bits.uop.dst_rtype connect slots_6.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[6].wakeup_ports[2].bits.uop.lrs3 connect slots_6.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[6].wakeup_ports[2].bits.uop.lrs2 connect slots_6.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[6].wakeup_ports[2].bits.uop.lrs1 connect slots_6.io.wakeup_ports[2].bits.uop.ldst, issue_slots[6].wakeup_ports[2].bits.uop.ldst connect slots_6.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_6.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[2].bits.uop.csr_cmd connect slots_6.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[2].bits.uop.flush_on_commit connect slots_6.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[6].wakeup_ports[2].bits.uop.is_unique connect slots_6.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[6].wakeup_ports[2].bits.uop.uses_stq connect slots_6.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[2].bits.uop.uses_ldq connect slots_6.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[6].wakeup_ports[2].bits.uop.mem_signed connect slots_6.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[6].wakeup_ports[2].bits.uop.mem_size connect slots_6.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[2].bits.uop.mem_cmd connect slots_6.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[6].wakeup_ports[2].bits.uop.exc_cause connect slots_6.io.wakeup_ports[2].bits.uop.exception, issue_slots[6].wakeup_ports[2].bits.uop.exception connect slots_6.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[2].bits.uop.stale_pdst connect slots_6.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[2].bits.uop.ppred_busy connect slots_6.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[2].bits.uop.prs3_busy connect slots_6.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[2].bits.uop.prs2_busy connect slots_6.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[2].bits.uop.prs1_busy connect slots_6.io.wakeup_ports[2].bits.uop.ppred, issue_slots[6].wakeup_ports[2].bits.uop.ppred connect slots_6.io.wakeup_ports[2].bits.uop.prs3, issue_slots[6].wakeup_ports[2].bits.uop.prs3 connect slots_6.io.wakeup_ports[2].bits.uop.prs2, issue_slots[6].wakeup_ports[2].bits.uop.prs2 connect slots_6.io.wakeup_ports[2].bits.uop.prs1, issue_slots[6].wakeup_ports[2].bits.uop.prs1 connect slots_6.io.wakeup_ports[2].bits.uop.pdst, issue_slots[6].wakeup_ports[2].bits.uop.pdst connect slots_6.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[2].bits.uop.rxq_idx connect slots_6.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[6].wakeup_ports[2].bits.uop.stq_idx connect slots_6.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[2].bits.uop.ldq_idx connect slots_6.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[6].wakeup_ports[2].bits.uop.rob_idx connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_6.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[6].wakeup_ports[2].bits.uop.op2_sel connect slots_6.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[6].wakeup_ports[2].bits.uop.op1_sel connect slots_6.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[6].wakeup_ports[2].bits.uop.imm_packed connect slots_6.io.wakeup_ports[2].bits.uop.pimm, issue_slots[6].wakeup_ports[2].bits.uop.pimm connect slots_6.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[6].wakeup_ports[2].bits.uop.imm_sel connect slots_6.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[6].wakeup_ports[2].bits.uop.imm_rename connect slots_6.io.wakeup_ports[2].bits.uop.taken, issue_slots[6].wakeup_ports[2].bits.uop.taken connect slots_6.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[6].wakeup_ports[2].bits.uop.pc_lob connect slots_6.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[6].wakeup_ports[2].bits.uop.edge_inst connect slots_6.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[2].bits.uop.ftq_idx connect slots_6.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[6].wakeup_ports[2].bits.uop.is_mov connect slots_6.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[6].wakeup_ports[2].bits.uop.is_rocc connect slots_6.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_6.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[6].wakeup_ports[2].bits.uop.is_eret connect slots_6.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[6].wakeup_ports[2].bits.uop.is_amo connect slots_6.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[6].wakeup_ports[2].bits.uop.is_sfence connect slots_6.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[6].wakeup_ports[2].bits.uop.is_fencei connect slots_6.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[6].wakeup_ports[2].bits.uop.is_fence connect slots_6.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[6].wakeup_ports[2].bits.uop.is_sfb connect slots_6.io.wakeup_ports[2].bits.uop.br_type, issue_slots[6].wakeup_ports[2].bits.uop.br_type connect slots_6.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[6].wakeup_ports[2].bits.uop.br_tag connect slots_6.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[6].wakeup_ports[2].bits.uop.br_mask connect slots_6.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[2].bits.uop.dis_col_sel connect slots_6.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_6.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_6.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_6.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_6.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_6.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_6.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_6.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[6].wakeup_ports[2].bits.uop.iw_issued connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[0] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[1] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[2] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[3] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[4] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[5] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[6] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[7] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[8] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[9] connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[0] connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[1] connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[2] connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[3] connect slots_6.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[6].wakeup_ports[2].bits.uop.debug_pc connect slots_6.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[6].wakeup_ports[2].bits.uop.is_rvc connect slots_6.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[6].wakeup_ports[2].bits.uop.debug_inst connect slots_6.io.wakeup_ports[2].bits.uop.inst, issue_slots[6].wakeup_ports[2].bits.uop.inst connect slots_6.io.wakeup_ports[2].valid, issue_slots[6].wakeup_ports[2].valid connect slots_6.io.wakeup_ports[3].bits.rebusy, issue_slots[6].wakeup_ports[3].bits.rebusy connect slots_6.io.wakeup_ports[3].bits.speculative_mask, issue_slots[6].wakeup_ports[3].bits.speculative_mask connect slots_6.io.wakeup_ports[3].bits.bypassable, issue_slots[6].wakeup_ports[3].bits.bypassable connect slots_6.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[3].bits.uop.debug_tsrc connect slots_6.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[3].bits.uop.debug_fsrc connect slots_6.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_6.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[3].bits.uop.bp_debug_if connect slots_6.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_6.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_6.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_6.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[6].wakeup_ports[3].bits.uop.fp_typ connect slots_6.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[6].wakeup_ports[3].bits.uop.fp_rm connect slots_6.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[6].wakeup_ports[3].bits.uop.fp_val connect slots_6.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[6].wakeup_ports[3].bits.uop.fcn_op connect slots_6.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[3].bits.uop.fcn_dw connect slots_6.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[6].wakeup_ports[3].bits.uop.frs3_en connect slots_6.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_6.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_6.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[3].bits.uop.dst_rtype connect slots_6.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[6].wakeup_ports[3].bits.uop.lrs3 connect slots_6.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[6].wakeup_ports[3].bits.uop.lrs2 connect slots_6.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[6].wakeup_ports[3].bits.uop.lrs1 connect slots_6.io.wakeup_ports[3].bits.uop.ldst, issue_slots[6].wakeup_ports[3].bits.uop.ldst connect slots_6.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_6.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[3].bits.uop.csr_cmd connect slots_6.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[3].bits.uop.flush_on_commit connect slots_6.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[6].wakeup_ports[3].bits.uop.is_unique connect slots_6.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[6].wakeup_ports[3].bits.uop.uses_stq connect slots_6.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[3].bits.uop.uses_ldq connect slots_6.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[6].wakeup_ports[3].bits.uop.mem_signed connect slots_6.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[6].wakeup_ports[3].bits.uop.mem_size connect slots_6.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[3].bits.uop.mem_cmd connect slots_6.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[6].wakeup_ports[3].bits.uop.exc_cause connect slots_6.io.wakeup_ports[3].bits.uop.exception, issue_slots[6].wakeup_ports[3].bits.uop.exception connect slots_6.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[3].bits.uop.stale_pdst connect slots_6.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[3].bits.uop.ppred_busy connect slots_6.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[3].bits.uop.prs3_busy connect slots_6.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[3].bits.uop.prs2_busy connect slots_6.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[3].bits.uop.prs1_busy connect slots_6.io.wakeup_ports[3].bits.uop.ppred, issue_slots[6].wakeup_ports[3].bits.uop.ppred connect slots_6.io.wakeup_ports[3].bits.uop.prs3, issue_slots[6].wakeup_ports[3].bits.uop.prs3 connect slots_6.io.wakeup_ports[3].bits.uop.prs2, issue_slots[6].wakeup_ports[3].bits.uop.prs2 connect slots_6.io.wakeup_ports[3].bits.uop.prs1, issue_slots[6].wakeup_ports[3].bits.uop.prs1 connect slots_6.io.wakeup_ports[3].bits.uop.pdst, issue_slots[6].wakeup_ports[3].bits.uop.pdst connect slots_6.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[3].bits.uop.rxq_idx connect slots_6.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[6].wakeup_ports[3].bits.uop.stq_idx connect slots_6.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[3].bits.uop.ldq_idx connect slots_6.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[6].wakeup_ports[3].bits.uop.rob_idx connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_6.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[6].wakeup_ports[3].bits.uop.op2_sel connect slots_6.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[6].wakeup_ports[3].bits.uop.op1_sel connect slots_6.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[6].wakeup_ports[3].bits.uop.imm_packed connect slots_6.io.wakeup_ports[3].bits.uop.pimm, issue_slots[6].wakeup_ports[3].bits.uop.pimm connect slots_6.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[6].wakeup_ports[3].bits.uop.imm_sel connect slots_6.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[6].wakeup_ports[3].bits.uop.imm_rename connect slots_6.io.wakeup_ports[3].bits.uop.taken, issue_slots[6].wakeup_ports[3].bits.uop.taken connect slots_6.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[6].wakeup_ports[3].bits.uop.pc_lob connect slots_6.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[6].wakeup_ports[3].bits.uop.edge_inst connect slots_6.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[3].bits.uop.ftq_idx connect slots_6.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[6].wakeup_ports[3].bits.uop.is_mov connect slots_6.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[6].wakeup_ports[3].bits.uop.is_rocc connect slots_6.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_6.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[6].wakeup_ports[3].bits.uop.is_eret connect slots_6.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[6].wakeup_ports[3].bits.uop.is_amo connect slots_6.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[6].wakeup_ports[3].bits.uop.is_sfence connect slots_6.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[6].wakeup_ports[3].bits.uop.is_fencei connect slots_6.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[6].wakeup_ports[3].bits.uop.is_fence connect slots_6.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[6].wakeup_ports[3].bits.uop.is_sfb connect slots_6.io.wakeup_ports[3].bits.uop.br_type, issue_slots[6].wakeup_ports[3].bits.uop.br_type connect slots_6.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[6].wakeup_ports[3].bits.uop.br_tag connect slots_6.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[6].wakeup_ports[3].bits.uop.br_mask connect slots_6.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[3].bits.uop.dis_col_sel connect slots_6.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_6.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_6.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_6.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_6.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_6.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_6.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_6.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[6].wakeup_ports[3].bits.uop.iw_issued connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[0] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[1] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[2] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[3] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[4] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[5] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[6] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[7] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[8] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[9] connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[0] connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[1] connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[2] connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[3] connect slots_6.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[6].wakeup_ports[3].bits.uop.debug_pc connect slots_6.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[6].wakeup_ports[3].bits.uop.is_rvc connect slots_6.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[6].wakeup_ports[3].bits.uop.debug_inst connect slots_6.io.wakeup_ports[3].bits.uop.inst, issue_slots[6].wakeup_ports[3].bits.uop.inst connect slots_6.io.wakeup_ports[3].valid, issue_slots[6].wakeup_ports[3].valid connect slots_6.io.wakeup_ports[4].bits.rebusy, issue_slots[6].wakeup_ports[4].bits.rebusy connect slots_6.io.wakeup_ports[4].bits.speculative_mask, issue_slots[6].wakeup_ports[4].bits.speculative_mask connect slots_6.io.wakeup_ports[4].bits.bypassable, issue_slots[6].wakeup_ports[4].bits.bypassable connect slots_6.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[4].bits.uop.debug_tsrc connect slots_6.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[4].bits.uop.debug_fsrc connect slots_6.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_6.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[4].bits.uop.bp_debug_if connect slots_6.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_6.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_6.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_6.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[6].wakeup_ports[4].bits.uop.fp_typ connect slots_6.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[6].wakeup_ports[4].bits.uop.fp_rm connect slots_6.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[6].wakeup_ports[4].bits.uop.fp_val connect slots_6.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[6].wakeup_ports[4].bits.uop.fcn_op connect slots_6.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[4].bits.uop.fcn_dw connect slots_6.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[6].wakeup_ports[4].bits.uop.frs3_en connect slots_6.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_6.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_6.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[4].bits.uop.dst_rtype connect slots_6.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[6].wakeup_ports[4].bits.uop.lrs3 connect slots_6.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[6].wakeup_ports[4].bits.uop.lrs2 connect slots_6.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[6].wakeup_ports[4].bits.uop.lrs1 connect slots_6.io.wakeup_ports[4].bits.uop.ldst, issue_slots[6].wakeup_ports[4].bits.uop.ldst connect slots_6.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_6.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[4].bits.uop.csr_cmd connect slots_6.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[4].bits.uop.flush_on_commit connect slots_6.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[6].wakeup_ports[4].bits.uop.is_unique connect slots_6.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[6].wakeup_ports[4].bits.uop.uses_stq connect slots_6.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[4].bits.uop.uses_ldq connect slots_6.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[6].wakeup_ports[4].bits.uop.mem_signed connect slots_6.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[6].wakeup_ports[4].bits.uop.mem_size connect slots_6.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[4].bits.uop.mem_cmd connect slots_6.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[6].wakeup_ports[4].bits.uop.exc_cause connect slots_6.io.wakeup_ports[4].bits.uop.exception, issue_slots[6].wakeup_ports[4].bits.uop.exception connect slots_6.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[4].bits.uop.stale_pdst connect slots_6.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[4].bits.uop.ppred_busy connect slots_6.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[4].bits.uop.prs3_busy connect slots_6.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[4].bits.uop.prs2_busy connect slots_6.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[4].bits.uop.prs1_busy connect slots_6.io.wakeup_ports[4].bits.uop.ppred, issue_slots[6].wakeup_ports[4].bits.uop.ppred connect slots_6.io.wakeup_ports[4].bits.uop.prs3, issue_slots[6].wakeup_ports[4].bits.uop.prs3 connect slots_6.io.wakeup_ports[4].bits.uop.prs2, issue_slots[6].wakeup_ports[4].bits.uop.prs2 connect slots_6.io.wakeup_ports[4].bits.uop.prs1, issue_slots[6].wakeup_ports[4].bits.uop.prs1 connect slots_6.io.wakeup_ports[4].bits.uop.pdst, issue_slots[6].wakeup_ports[4].bits.uop.pdst connect slots_6.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[4].bits.uop.rxq_idx connect slots_6.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[6].wakeup_ports[4].bits.uop.stq_idx connect slots_6.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[4].bits.uop.ldq_idx connect slots_6.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[6].wakeup_ports[4].bits.uop.rob_idx connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_6.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[6].wakeup_ports[4].bits.uop.op2_sel connect slots_6.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[6].wakeup_ports[4].bits.uop.op1_sel connect slots_6.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[6].wakeup_ports[4].bits.uop.imm_packed connect slots_6.io.wakeup_ports[4].bits.uop.pimm, issue_slots[6].wakeup_ports[4].bits.uop.pimm connect slots_6.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[6].wakeup_ports[4].bits.uop.imm_sel connect slots_6.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[6].wakeup_ports[4].bits.uop.imm_rename connect slots_6.io.wakeup_ports[4].bits.uop.taken, issue_slots[6].wakeup_ports[4].bits.uop.taken connect slots_6.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[6].wakeup_ports[4].bits.uop.pc_lob connect slots_6.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[6].wakeup_ports[4].bits.uop.edge_inst connect slots_6.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[4].bits.uop.ftq_idx connect slots_6.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[6].wakeup_ports[4].bits.uop.is_mov connect slots_6.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[6].wakeup_ports[4].bits.uop.is_rocc connect slots_6.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_6.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[6].wakeup_ports[4].bits.uop.is_eret connect slots_6.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[6].wakeup_ports[4].bits.uop.is_amo connect slots_6.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[6].wakeup_ports[4].bits.uop.is_sfence connect slots_6.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[6].wakeup_ports[4].bits.uop.is_fencei connect slots_6.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[6].wakeup_ports[4].bits.uop.is_fence connect slots_6.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[6].wakeup_ports[4].bits.uop.is_sfb connect slots_6.io.wakeup_ports[4].bits.uop.br_type, issue_slots[6].wakeup_ports[4].bits.uop.br_type connect slots_6.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[6].wakeup_ports[4].bits.uop.br_tag connect slots_6.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[6].wakeup_ports[4].bits.uop.br_mask connect slots_6.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[4].bits.uop.dis_col_sel connect slots_6.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_6.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_6.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_6.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_6.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_6.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_6.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_6.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[6].wakeup_ports[4].bits.uop.iw_issued connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[0] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[1] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[2] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[3] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[4] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[5] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[6] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[7] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[8] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[9] connect slots_6.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[4].bits.uop.iq_type[0] connect slots_6.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[4].bits.uop.iq_type[1] connect slots_6.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[4].bits.uop.iq_type[2] connect slots_6.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[4].bits.uop.iq_type[3] connect slots_6.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[6].wakeup_ports[4].bits.uop.debug_pc connect slots_6.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[6].wakeup_ports[4].bits.uop.is_rvc connect slots_6.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[6].wakeup_ports[4].bits.uop.debug_inst connect slots_6.io.wakeup_ports[4].bits.uop.inst, issue_slots[6].wakeup_ports[4].bits.uop.inst connect slots_6.io.wakeup_ports[4].valid, issue_slots[6].wakeup_ports[4].valid connect slots_6.io.squash_grant, issue_slots[6].squash_grant connect slots_6.io.clear, issue_slots[6].clear connect slots_6.io.kill, issue_slots[6].kill connect slots_6.io.brupdate.b2.target_offset, issue_slots[6].brupdate.b2.target_offset connect slots_6.io.brupdate.b2.jalr_target, issue_slots[6].brupdate.b2.jalr_target connect slots_6.io.brupdate.b2.pc_sel, issue_slots[6].brupdate.b2.pc_sel connect slots_6.io.brupdate.b2.cfi_type, issue_slots[6].brupdate.b2.cfi_type connect slots_6.io.brupdate.b2.taken, issue_slots[6].brupdate.b2.taken connect slots_6.io.brupdate.b2.mispredict, issue_slots[6].brupdate.b2.mispredict connect slots_6.io.brupdate.b2.uop.debug_tsrc, issue_slots[6].brupdate.b2.uop.debug_tsrc connect slots_6.io.brupdate.b2.uop.debug_fsrc, issue_slots[6].brupdate.b2.uop.debug_fsrc connect slots_6.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[6].brupdate.b2.uop.bp_xcpt_if connect slots_6.io.brupdate.b2.uop.bp_debug_if, issue_slots[6].brupdate.b2.uop.bp_debug_if connect slots_6.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[6].brupdate.b2.uop.xcpt_ma_if connect slots_6.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[6].brupdate.b2.uop.xcpt_ae_if connect slots_6.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[6].brupdate.b2.uop.xcpt_pf_if connect slots_6.io.brupdate.b2.uop.fp_typ, issue_slots[6].brupdate.b2.uop.fp_typ connect slots_6.io.brupdate.b2.uop.fp_rm, issue_slots[6].brupdate.b2.uop.fp_rm connect slots_6.io.brupdate.b2.uop.fp_val, issue_slots[6].brupdate.b2.uop.fp_val connect slots_6.io.brupdate.b2.uop.fcn_op, issue_slots[6].brupdate.b2.uop.fcn_op connect slots_6.io.brupdate.b2.uop.fcn_dw, issue_slots[6].brupdate.b2.uop.fcn_dw connect slots_6.io.brupdate.b2.uop.frs3_en, issue_slots[6].brupdate.b2.uop.frs3_en connect slots_6.io.brupdate.b2.uop.lrs2_rtype, issue_slots[6].brupdate.b2.uop.lrs2_rtype connect slots_6.io.brupdate.b2.uop.lrs1_rtype, issue_slots[6].brupdate.b2.uop.lrs1_rtype connect slots_6.io.brupdate.b2.uop.dst_rtype, issue_slots[6].brupdate.b2.uop.dst_rtype connect slots_6.io.brupdate.b2.uop.lrs3, issue_slots[6].brupdate.b2.uop.lrs3 connect slots_6.io.brupdate.b2.uop.lrs2, issue_slots[6].brupdate.b2.uop.lrs2 connect slots_6.io.brupdate.b2.uop.lrs1, issue_slots[6].brupdate.b2.uop.lrs1 connect slots_6.io.brupdate.b2.uop.ldst, issue_slots[6].brupdate.b2.uop.ldst connect slots_6.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[6].brupdate.b2.uop.ldst_is_rs1 connect slots_6.io.brupdate.b2.uop.csr_cmd, issue_slots[6].brupdate.b2.uop.csr_cmd connect slots_6.io.brupdate.b2.uop.flush_on_commit, issue_slots[6].brupdate.b2.uop.flush_on_commit connect slots_6.io.brupdate.b2.uop.is_unique, issue_slots[6].brupdate.b2.uop.is_unique connect slots_6.io.brupdate.b2.uop.uses_stq, issue_slots[6].brupdate.b2.uop.uses_stq connect slots_6.io.brupdate.b2.uop.uses_ldq, issue_slots[6].brupdate.b2.uop.uses_ldq connect slots_6.io.brupdate.b2.uop.mem_signed, issue_slots[6].brupdate.b2.uop.mem_signed connect slots_6.io.brupdate.b2.uop.mem_size, issue_slots[6].brupdate.b2.uop.mem_size connect slots_6.io.brupdate.b2.uop.mem_cmd, issue_slots[6].brupdate.b2.uop.mem_cmd connect slots_6.io.brupdate.b2.uop.exc_cause, issue_slots[6].brupdate.b2.uop.exc_cause connect slots_6.io.brupdate.b2.uop.exception, issue_slots[6].brupdate.b2.uop.exception connect slots_6.io.brupdate.b2.uop.stale_pdst, issue_slots[6].brupdate.b2.uop.stale_pdst connect slots_6.io.brupdate.b2.uop.ppred_busy, issue_slots[6].brupdate.b2.uop.ppred_busy connect slots_6.io.brupdate.b2.uop.prs3_busy, issue_slots[6].brupdate.b2.uop.prs3_busy connect slots_6.io.brupdate.b2.uop.prs2_busy, issue_slots[6].brupdate.b2.uop.prs2_busy connect slots_6.io.brupdate.b2.uop.prs1_busy, issue_slots[6].brupdate.b2.uop.prs1_busy connect slots_6.io.brupdate.b2.uop.ppred, issue_slots[6].brupdate.b2.uop.ppred connect slots_6.io.brupdate.b2.uop.prs3, issue_slots[6].brupdate.b2.uop.prs3 connect slots_6.io.brupdate.b2.uop.prs2, issue_slots[6].brupdate.b2.uop.prs2 connect slots_6.io.brupdate.b2.uop.prs1, issue_slots[6].brupdate.b2.uop.prs1 connect slots_6.io.brupdate.b2.uop.pdst, issue_slots[6].brupdate.b2.uop.pdst connect slots_6.io.brupdate.b2.uop.rxq_idx, issue_slots[6].brupdate.b2.uop.rxq_idx connect slots_6.io.brupdate.b2.uop.stq_idx, issue_slots[6].brupdate.b2.uop.stq_idx connect slots_6.io.brupdate.b2.uop.ldq_idx, issue_slots[6].brupdate.b2.uop.ldq_idx connect slots_6.io.brupdate.b2.uop.rob_idx, issue_slots[6].brupdate.b2.uop.rob_idx connect slots_6.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[6].brupdate.b2.uop.fp_ctrl.vec connect slots_6.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[6].brupdate.b2.uop.fp_ctrl.wflags connect slots_6.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[6].brupdate.b2.uop.fp_ctrl.sqrt connect slots_6.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[6].brupdate.b2.uop.fp_ctrl.div connect slots_6.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[6].brupdate.b2.uop.fp_ctrl.fma connect slots_6.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[6].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_6.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[6].brupdate.b2.uop.fp_ctrl.toint connect slots_6.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[6].brupdate.b2.uop.fp_ctrl.fromint connect slots_6.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_6.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_6.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[6].brupdate.b2.uop.fp_ctrl.swap23 connect slots_6.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[6].brupdate.b2.uop.fp_ctrl.swap12 connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren3 connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren2 connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren1 connect slots_6.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[6].brupdate.b2.uop.fp_ctrl.wen connect slots_6.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[6].brupdate.b2.uop.fp_ctrl.ldst connect slots_6.io.brupdate.b2.uop.op2_sel, issue_slots[6].brupdate.b2.uop.op2_sel connect slots_6.io.brupdate.b2.uop.op1_sel, issue_slots[6].brupdate.b2.uop.op1_sel connect slots_6.io.brupdate.b2.uop.imm_packed, issue_slots[6].brupdate.b2.uop.imm_packed connect slots_6.io.brupdate.b2.uop.pimm, issue_slots[6].brupdate.b2.uop.pimm connect slots_6.io.brupdate.b2.uop.imm_sel, issue_slots[6].brupdate.b2.uop.imm_sel connect slots_6.io.brupdate.b2.uop.imm_rename, issue_slots[6].brupdate.b2.uop.imm_rename connect slots_6.io.brupdate.b2.uop.taken, issue_slots[6].brupdate.b2.uop.taken connect slots_6.io.brupdate.b2.uop.pc_lob, issue_slots[6].brupdate.b2.uop.pc_lob connect slots_6.io.brupdate.b2.uop.edge_inst, issue_slots[6].brupdate.b2.uop.edge_inst connect slots_6.io.brupdate.b2.uop.ftq_idx, issue_slots[6].brupdate.b2.uop.ftq_idx connect slots_6.io.brupdate.b2.uop.is_mov, issue_slots[6].brupdate.b2.uop.is_mov connect slots_6.io.brupdate.b2.uop.is_rocc, issue_slots[6].brupdate.b2.uop.is_rocc connect slots_6.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[6].brupdate.b2.uop.is_sys_pc2epc connect slots_6.io.brupdate.b2.uop.is_eret, issue_slots[6].brupdate.b2.uop.is_eret connect slots_6.io.brupdate.b2.uop.is_amo, issue_slots[6].brupdate.b2.uop.is_amo connect slots_6.io.brupdate.b2.uop.is_sfence, issue_slots[6].brupdate.b2.uop.is_sfence connect slots_6.io.brupdate.b2.uop.is_fencei, issue_slots[6].brupdate.b2.uop.is_fencei connect slots_6.io.brupdate.b2.uop.is_fence, issue_slots[6].brupdate.b2.uop.is_fence connect slots_6.io.brupdate.b2.uop.is_sfb, issue_slots[6].brupdate.b2.uop.is_sfb connect slots_6.io.brupdate.b2.uop.br_type, issue_slots[6].brupdate.b2.uop.br_type connect slots_6.io.brupdate.b2.uop.br_tag, issue_slots[6].brupdate.b2.uop.br_tag connect slots_6.io.brupdate.b2.uop.br_mask, issue_slots[6].brupdate.b2.uop.br_mask connect slots_6.io.brupdate.b2.uop.dis_col_sel, issue_slots[6].brupdate.b2.uop.dis_col_sel connect slots_6.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p3_bypass_hint connect slots_6.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p2_bypass_hint connect slots_6.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p1_bypass_hint connect slots_6.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[6].brupdate.b2.uop.iw_p2_speculative_child connect slots_6.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[6].brupdate.b2.uop.iw_p1_speculative_child connect slots_6.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[6].brupdate.b2.uop.iw_issued_partial_dgen connect slots_6.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[6].brupdate.b2.uop.iw_issued_partial_agen connect slots_6.io.brupdate.b2.uop.iw_issued, issue_slots[6].brupdate.b2.uop.iw_issued connect slots_6.io.brupdate.b2.uop.fu_code[0], issue_slots[6].brupdate.b2.uop.fu_code[0] connect slots_6.io.brupdate.b2.uop.fu_code[1], issue_slots[6].brupdate.b2.uop.fu_code[1] connect slots_6.io.brupdate.b2.uop.fu_code[2], issue_slots[6].brupdate.b2.uop.fu_code[2] connect slots_6.io.brupdate.b2.uop.fu_code[3], issue_slots[6].brupdate.b2.uop.fu_code[3] connect slots_6.io.brupdate.b2.uop.fu_code[4], issue_slots[6].brupdate.b2.uop.fu_code[4] connect slots_6.io.brupdate.b2.uop.fu_code[5], issue_slots[6].brupdate.b2.uop.fu_code[5] connect slots_6.io.brupdate.b2.uop.fu_code[6], issue_slots[6].brupdate.b2.uop.fu_code[6] connect slots_6.io.brupdate.b2.uop.fu_code[7], issue_slots[6].brupdate.b2.uop.fu_code[7] connect slots_6.io.brupdate.b2.uop.fu_code[8], issue_slots[6].brupdate.b2.uop.fu_code[8] connect slots_6.io.brupdate.b2.uop.fu_code[9], issue_slots[6].brupdate.b2.uop.fu_code[9] connect slots_6.io.brupdate.b2.uop.iq_type[0], issue_slots[6].brupdate.b2.uop.iq_type[0] connect slots_6.io.brupdate.b2.uop.iq_type[1], issue_slots[6].brupdate.b2.uop.iq_type[1] connect slots_6.io.brupdate.b2.uop.iq_type[2], issue_slots[6].brupdate.b2.uop.iq_type[2] connect slots_6.io.brupdate.b2.uop.iq_type[3], issue_slots[6].brupdate.b2.uop.iq_type[3] connect slots_6.io.brupdate.b2.uop.debug_pc, issue_slots[6].brupdate.b2.uop.debug_pc connect slots_6.io.brupdate.b2.uop.is_rvc, issue_slots[6].brupdate.b2.uop.is_rvc connect slots_6.io.brupdate.b2.uop.debug_inst, issue_slots[6].brupdate.b2.uop.debug_inst connect slots_6.io.brupdate.b2.uop.inst, issue_slots[6].brupdate.b2.uop.inst connect slots_6.io.brupdate.b1.mispredict_mask, issue_slots[6].brupdate.b1.mispredict_mask connect slots_6.io.brupdate.b1.resolve_mask, issue_slots[6].brupdate.b1.resolve_mask connect issue_slots[6].out_uop.debug_tsrc, slots_6.io.out_uop.debug_tsrc connect issue_slots[6].out_uop.debug_fsrc, slots_6.io.out_uop.debug_fsrc connect issue_slots[6].out_uop.bp_xcpt_if, slots_6.io.out_uop.bp_xcpt_if connect issue_slots[6].out_uop.bp_debug_if, slots_6.io.out_uop.bp_debug_if connect issue_slots[6].out_uop.xcpt_ma_if, slots_6.io.out_uop.xcpt_ma_if connect issue_slots[6].out_uop.xcpt_ae_if, slots_6.io.out_uop.xcpt_ae_if connect issue_slots[6].out_uop.xcpt_pf_if, slots_6.io.out_uop.xcpt_pf_if connect issue_slots[6].out_uop.fp_typ, slots_6.io.out_uop.fp_typ connect issue_slots[6].out_uop.fp_rm, slots_6.io.out_uop.fp_rm connect issue_slots[6].out_uop.fp_val, slots_6.io.out_uop.fp_val connect issue_slots[6].out_uop.fcn_op, slots_6.io.out_uop.fcn_op connect issue_slots[6].out_uop.fcn_dw, slots_6.io.out_uop.fcn_dw connect issue_slots[6].out_uop.frs3_en, slots_6.io.out_uop.frs3_en connect issue_slots[6].out_uop.lrs2_rtype, slots_6.io.out_uop.lrs2_rtype connect issue_slots[6].out_uop.lrs1_rtype, slots_6.io.out_uop.lrs1_rtype connect issue_slots[6].out_uop.dst_rtype, slots_6.io.out_uop.dst_rtype connect issue_slots[6].out_uop.lrs3, slots_6.io.out_uop.lrs3 connect issue_slots[6].out_uop.lrs2, slots_6.io.out_uop.lrs2 connect issue_slots[6].out_uop.lrs1, slots_6.io.out_uop.lrs1 connect issue_slots[6].out_uop.ldst, slots_6.io.out_uop.ldst connect issue_slots[6].out_uop.ldst_is_rs1, slots_6.io.out_uop.ldst_is_rs1 connect issue_slots[6].out_uop.csr_cmd, slots_6.io.out_uop.csr_cmd connect issue_slots[6].out_uop.flush_on_commit, slots_6.io.out_uop.flush_on_commit connect issue_slots[6].out_uop.is_unique, slots_6.io.out_uop.is_unique connect issue_slots[6].out_uop.uses_stq, slots_6.io.out_uop.uses_stq connect issue_slots[6].out_uop.uses_ldq, slots_6.io.out_uop.uses_ldq connect issue_slots[6].out_uop.mem_signed, slots_6.io.out_uop.mem_signed connect issue_slots[6].out_uop.mem_size, slots_6.io.out_uop.mem_size connect issue_slots[6].out_uop.mem_cmd, slots_6.io.out_uop.mem_cmd connect issue_slots[6].out_uop.exc_cause, slots_6.io.out_uop.exc_cause connect issue_slots[6].out_uop.exception, slots_6.io.out_uop.exception connect issue_slots[6].out_uop.stale_pdst, slots_6.io.out_uop.stale_pdst connect issue_slots[6].out_uop.ppred_busy, slots_6.io.out_uop.ppred_busy connect issue_slots[6].out_uop.prs3_busy, slots_6.io.out_uop.prs3_busy connect issue_slots[6].out_uop.prs2_busy, slots_6.io.out_uop.prs2_busy connect issue_slots[6].out_uop.prs1_busy, slots_6.io.out_uop.prs1_busy connect issue_slots[6].out_uop.ppred, slots_6.io.out_uop.ppred connect issue_slots[6].out_uop.prs3, slots_6.io.out_uop.prs3 connect issue_slots[6].out_uop.prs2, slots_6.io.out_uop.prs2 connect issue_slots[6].out_uop.prs1, slots_6.io.out_uop.prs1 connect issue_slots[6].out_uop.pdst, slots_6.io.out_uop.pdst connect issue_slots[6].out_uop.rxq_idx, slots_6.io.out_uop.rxq_idx connect issue_slots[6].out_uop.stq_idx, slots_6.io.out_uop.stq_idx connect issue_slots[6].out_uop.ldq_idx, slots_6.io.out_uop.ldq_idx connect issue_slots[6].out_uop.rob_idx, slots_6.io.out_uop.rob_idx connect issue_slots[6].out_uop.fp_ctrl.vec, slots_6.io.out_uop.fp_ctrl.vec connect issue_slots[6].out_uop.fp_ctrl.wflags, slots_6.io.out_uop.fp_ctrl.wflags connect issue_slots[6].out_uop.fp_ctrl.sqrt, slots_6.io.out_uop.fp_ctrl.sqrt connect issue_slots[6].out_uop.fp_ctrl.div, slots_6.io.out_uop.fp_ctrl.div connect issue_slots[6].out_uop.fp_ctrl.fma, slots_6.io.out_uop.fp_ctrl.fma connect issue_slots[6].out_uop.fp_ctrl.fastpipe, slots_6.io.out_uop.fp_ctrl.fastpipe connect issue_slots[6].out_uop.fp_ctrl.toint, slots_6.io.out_uop.fp_ctrl.toint connect issue_slots[6].out_uop.fp_ctrl.fromint, slots_6.io.out_uop.fp_ctrl.fromint connect issue_slots[6].out_uop.fp_ctrl.typeTagOut, slots_6.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[6].out_uop.fp_ctrl.typeTagIn, slots_6.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[6].out_uop.fp_ctrl.swap23, slots_6.io.out_uop.fp_ctrl.swap23 connect issue_slots[6].out_uop.fp_ctrl.swap12, slots_6.io.out_uop.fp_ctrl.swap12 connect issue_slots[6].out_uop.fp_ctrl.ren3, slots_6.io.out_uop.fp_ctrl.ren3 connect issue_slots[6].out_uop.fp_ctrl.ren2, slots_6.io.out_uop.fp_ctrl.ren2 connect issue_slots[6].out_uop.fp_ctrl.ren1, slots_6.io.out_uop.fp_ctrl.ren1 connect issue_slots[6].out_uop.fp_ctrl.wen, slots_6.io.out_uop.fp_ctrl.wen connect issue_slots[6].out_uop.fp_ctrl.ldst, slots_6.io.out_uop.fp_ctrl.ldst connect issue_slots[6].out_uop.op2_sel, slots_6.io.out_uop.op2_sel connect issue_slots[6].out_uop.op1_sel, slots_6.io.out_uop.op1_sel connect issue_slots[6].out_uop.imm_packed, slots_6.io.out_uop.imm_packed connect issue_slots[6].out_uop.pimm, slots_6.io.out_uop.pimm connect issue_slots[6].out_uop.imm_sel, slots_6.io.out_uop.imm_sel connect issue_slots[6].out_uop.imm_rename, slots_6.io.out_uop.imm_rename connect issue_slots[6].out_uop.taken, slots_6.io.out_uop.taken connect issue_slots[6].out_uop.pc_lob, slots_6.io.out_uop.pc_lob connect issue_slots[6].out_uop.edge_inst, slots_6.io.out_uop.edge_inst connect issue_slots[6].out_uop.ftq_idx, slots_6.io.out_uop.ftq_idx connect issue_slots[6].out_uop.is_mov, slots_6.io.out_uop.is_mov connect issue_slots[6].out_uop.is_rocc, slots_6.io.out_uop.is_rocc connect issue_slots[6].out_uop.is_sys_pc2epc, slots_6.io.out_uop.is_sys_pc2epc connect issue_slots[6].out_uop.is_eret, slots_6.io.out_uop.is_eret connect issue_slots[6].out_uop.is_amo, slots_6.io.out_uop.is_amo connect issue_slots[6].out_uop.is_sfence, slots_6.io.out_uop.is_sfence connect issue_slots[6].out_uop.is_fencei, slots_6.io.out_uop.is_fencei connect issue_slots[6].out_uop.is_fence, slots_6.io.out_uop.is_fence connect issue_slots[6].out_uop.is_sfb, slots_6.io.out_uop.is_sfb connect issue_slots[6].out_uop.br_type, slots_6.io.out_uop.br_type connect issue_slots[6].out_uop.br_tag, slots_6.io.out_uop.br_tag connect issue_slots[6].out_uop.br_mask, slots_6.io.out_uop.br_mask connect issue_slots[6].out_uop.dis_col_sel, slots_6.io.out_uop.dis_col_sel connect issue_slots[6].out_uop.iw_p3_bypass_hint, slots_6.io.out_uop.iw_p3_bypass_hint connect issue_slots[6].out_uop.iw_p2_bypass_hint, slots_6.io.out_uop.iw_p2_bypass_hint connect issue_slots[6].out_uop.iw_p1_bypass_hint, slots_6.io.out_uop.iw_p1_bypass_hint connect issue_slots[6].out_uop.iw_p2_speculative_child, slots_6.io.out_uop.iw_p2_speculative_child connect issue_slots[6].out_uop.iw_p1_speculative_child, slots_6.io.out_uop.iw_p1_speculative_child connect issue_slots[6].out_uop.iw_issued_partial_dgen, slots_6.io.out_uop.iw_issued_partial_dgen connect issue_slots[6].out_uop.iw_issued_partial_agen, slots_6.io.out_uop.iw_issued_partial_agen connect issue_slots[6].out_uop.iw_issued, slots_6.io.out_uop.iw_issued connect issue_slots[6].out_uop.fu_code[0], slots_6.io.out_uop.fu_code[0] connect issue_slots[6].out_uop.fu_code[1], slots_6.io.out_uop.fu_code[1] connect issue_slots[6].out_uop.fu_code[2], slots_6.io.out_uop.fu_code[2] connect issue_slots[6].out_uop.fu_code[3], slots_6.io.out_uop.fu_code[3] connect issue_slots[6].out_uop.fu_code[4], slots_6.io.out_uop.fu_code[4] connect issue_slots[6].out_uop.fu_code[5], slots_6.io.out_uop.fu_code[5] connect issue_slots[6].out_uop.fu_code[6], slots_6.io.out_uop.fu_code[6] connect issue_slots[6].out_uop.fu_code[7], slots_6.io.out_uop.fu_code[7] connect issue_slots[6].out_uop.fu_code[8], slots_6.io.out_uop.fu_code[8] connect issue_slots[6].out_uop.fu_code[9], slots_6.io.out_uop.fu_code[9] connect issue_slots[6].out_uop.iq_type[0], slots_6.io.out_uop.iq_type[0] connect issue_slots[6].out_uop.iq_type[1], slots_6.io.out_uop.iq_type[1] connect issue_slots[6].out_uop.iq_type[2], slots_6.io.out_uop.iq_type[2] connect issue_slots[6].out_uop.iq_type[3], slots_6.io.out_uop.iq_type[3] connect issue_slots[6].out_uop.debug_pc, slots_6.io.out_uop.debug_pc connect issue_slots[6].out_uop.is_rvc, slots_6.io.out_uop.is_rvc connect issue_slots[6].out_uop.debug_inst, slots_6.io.out_uop.debug_inst connect issue_slots[6].out_uop.inst, slots_6.io.out_uop.inst connect slots_6.io.in_uop.bits.debug_tsrc, issue_slots[6].in_uop.bits.debug_tsrc connect slots_6.io.in_uop.bits.debug_fsrc, issue_slots[6].in_uop.bits.debug_fsrc connect slots_6.io.in_uop.bits.bp_xcpt_if, issue_slots[6].in_uop.bits.bp_xcpt_if connect slots_6.io.in_uop.bits.bp_debug_if, issue_slots[6].in_uop.bits.bp_debug_if connect slots_6.io.in_uop.bits.xcpt_ma_if, issue_slots[6].in_uop.bits.xcpt_ma_if connect slots_6.io.in_uop.bits.xcpt_ae_if, issue_slots[6].in_uop.bits.xcpt_ae_if connect slots_6.io.in_uop.bits.xcpt_pf_if, issue_slots[6].in_uop.bits.xcpt_pf_if connect slots_6.io.in_uop.bits.fp_typ, issue_slots[6].in_uop.bits.fp_typ connect slots_6.io.in_uop.bits.fp_rm, issue_slots[6].in_uop.bits.fp_rm connect slots_6.io.in_uop.bits.fp_val, issue_slots[6].in_uop.bits.fp_val connect slots_6.io.in_uop.bits.fcn_op, issue_slots[6].in_uop.bits.fcn_op connect slots_6.io.in_uop.bits.fcn_dw, issue_slots[6].in_uop.bits.fcn_dw connect slots_6.io.in_uop.bits.frs3_en, issue_slots[6].in_uop.bits.frs3_en connect slots_6.io.in_uop.bits.lrs2_rtype, issue_slots[6].in_uop.bits.lrs2_rtype connect slots_6.io.in_uop.bits.lrs1_rtype, issue_slots[6].in_uop.bits.lrs1_rtype connect slots_6.io.in_uop.bits.dst_rtype, issue_slots[6].in_uop.bits.dst_rtype connect slots_6.io.in_uop.bits.lrs3, issue_slots[6].in_uop.bits.lrs3 connect slots_6.io.in_uop.bits.lrs2, issue_slots[6].in_uop.bits.lrs2 connect slots_6.io.in_uop.bits.lrs1, issue_slots[6].in_uop.bits.lrs1 connect slots_6.io.in_uop.bits.ldst, issue_slots[6].in_uop.bits.ldst connect slots_6.io.in_uop.bits.ldst_is_rs1, issue_slots[6].in_uop.bits.ldst_is_rs1 connect slots_6.io.in_uop.bits.csr_cmd, issue_slots[6].in_uop.bits.csr_cmd connect slots_6.io.in_uop.bits.flush_on_commit, issue_slots[6].in_uop.bits.flush_on_commit connect slots_6.io.in_uop.bits.is_unique, issue_slots[6].in_uop.bits.is_unique connect slots_6.io.in_uop.bits.uses_stq, issue_slots[6].in_uop.bits.uses_stq connect slots_6.io.in_uop.bits.uses_ldq, issue_slots[6].in_uop.bits.uses_ldq connect slots_6.io.in_uop.bits.mem_signed, issue_slots[6].in_uop.bits.mem_signed connect slots_6.io.in_uop.bits.mem_size, issue_slots[6].in_uop.bits.mem_size connect slots_6.io.in_uop.bits.mem_cmd, issue_slots[6].in_uop.bits.mem_cmd connect slots_6.io.in_uop.bits.exc_cause, issue_slots[6].in_uop.bits.exc_cause connect slots_6.io.in_uop.bits.exception, issue_slots[6].in_uop.bits.exception connect slots_6.io.in_uop.bits.stale_pdst, issue_slots[6].in_uop.bits.stale_pdst connect slots_6.io.in_uop.bits.ppred_busy, issue_slots[6].in_uop.bits.ppred_busy connect slots_6.io.in_uop.bits.prs3_busy, issue_slots[6].in_uop.bits.prs3_busy connect slots_6.io.in_uop.bits.prs2_busy, issue_slots[6].in_uop.bits.prs2_busy connect slots_6.io.in_uop.bits.prs1_busy, issue_slots[6].in_uop.bits.prs1_busy connect slots_6.io.in_uop.bits.ppred, issue_slots[6].in_uop.bits.ppred connect slots_6.io.in_uop.bits.prs3, issue_slots[6].in_uop.bits.prs3 connect slots_6.io.in_uop.bits.prs2, issue_slots[6].in_uop.bits.prs2 connect slots_6.io.in_uop.bits.prs1, issue_slots[6].in_uop.bits.prs1 connect slots_6.io.in_uop.bits.pdst, issue_slots[6].in_uop.bits.pdst connect slots_6.io.in_uop.bits.rxq_idx, issue_slots[6].in_uop.bits.rxq_idx connect slots_6.io.in_uop.bits.stq_idx, issue_slots[6].in_uop.bits.stq_idx connect slots_6.io.in_uop.bits.ldq_idx, issue_slots[6].in_uop.bits.ldq_idx connect slots_6.io.in_uop.bits.rob_idx, issue_slots[6].in_uop.bits.rob_idx connect slots_6.io.in_uop.bits.fp_ctrl.vec, issue_slots[6].in_uop.bits.fp_ctrl.vec connect slots_6.io.in_uop.bits.fp_ctrl.wflags, issue_slots[6].in_uop.bits.fp_ctrl.wflags connect slots_6.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[6].in_uop.bits.fp_ctrl.sqrt connect slots_6.io.in_uop.bits.fp_ctrl.div, issue_slots[6].in_uop.bits.fp_ctrl.div connect slots_6.io.in_uop.bits.fp_ctrl.fma, issue_slots[6].in_uop.bits.fp_ctrl.fma connect slots_6.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].in_uop.bits.fp_ctrl.fastpipe connect slots_6.io.in_uop.bits.fp_ctrl.toint, issue_slots[6].in_uop.bits.fp_ctrl.toint connect slots_6.io.in_uop.bits.fp_ctrl.fromint, issue_slots[6].in_uop.bits.fp_ctrl.fromint connect slots_6.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut connect slots_6.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn connect slots_6.io.in_uop.bits.fp_ctrl.swap23, issue_slots[6].in_uop.bits.fp_ctrl.swap23 connect slots_6.io.in_uop.bits.fp_ctrl.swap12, issue_slots[6].in_uop.bits.fp_ctrl.swap12 connect slots_6.io.in_uop.bits.fp_ctrl.ren3, issue_slots[6].in_uop.bits.fp_ctrl.ren3 connect slots_6.io.in_uop.bits.fp_ctrl.ren2, issue_slots[6].in_uop.bits.fp_ctrl.ren2 connect slots_6.io.in_uop.bits.fp_ctrl.ren1, issue_slots[6].in_uop.bits.fp_ctrl.ren1 connect slots_6.io.in_uop.bits.fp_ctrl.wen, issue_slots[6].in_uop.bits.fp_ctrl.wen connect slots_6.io.in_uop.bits.fp_ctrl.ldst, issue_slots[6].in_uop.bits.fp_ctrl.ldst connect slots_6.io.in_uop.bits.op2_sel, issue_slots[6].in_uop.bits.op2_sel connect slots_6.io.in_uop.bits.op1_sel, issue_slots[6].in_uop.bits.op1_sel connect slots_6.io.in_uop.bits.imm_packed, issue_slots[6].in_uop.bits.imm_packed connect slots_6.io.in_uop.bits.pimm, issue_slots[6].in_uop.bits.pimm connect slots_6.io.in_uop.bits.imm_sel, issue_slots[6].in_uop.bits.imm_sel connect slots_6.io.in_uop.bits.imm_rename, issue_slots[6].in_uop.bits.imm_rename connect slots_6.io.in_uop.bits.taken, issue_slots[6].in_uop.bits.taken connect slots_6.io.in_uop.bits.pc_lob, issue_slots[6].in_uop.bits.pc_lob connect slots_6.io.in_uop.bits.edge_inst, issue_slots[6].in_uop.bits.edge_inst connect slots_6.io.in_uop.bits.ftq_idx, issue_slots[6].in_uop.bits.ftq_idx connect slots_6.io.in_uop.bits.is_mov, issue_slots[6].in_uop.bits.is_mov connect slots_6.io.in_uop.bits.is_rocc, issue_slots[6].in_uop.bits.is_rocc connect slots_6.io.in_uop.bits.is_sys_pc2epc, issue_slots[6].in_uop.bits.is_sys_pc2epc connect slots_6.io.in_uop.bits.is_eret, issue_slots[6].in_uop.bits.is_eret connect slots_6.io.in_uop.bits.is_amo, issue_slots[6].in_uop.bits.is_amo connect slots_6.io.in_uop.bits.is_sfence, issue_slots[6].in_uop.bits.is_sfence connect slots_6.io.in_uop.bits.is_fencei, issue_slots[6].in_uop.bits.is_fencei connect slots_6.io.in_uop.bits.is_fence, issue_slots[6].in_uop.bits.is_fence connect slots_6.io.in_uop.bits.is_sfb, issue_slots[6].in_uop.bits.is_sfb connect slots_6.io.in_uop.bits.br_type, issue_slots[6].in_uop.bits.br_type connect slots_6.io.in_uop.bits.br_tag, issue_slots[6].in_uop.bits.br_tag connect slots_6.io.in_uop.bits.br_mask, issue_slots[6].in_uop.bits.br_mask connect slots_6.io.in_uop.bits.dis_col_sel, issue_slots[6].in_uop.bits.dis_col_sel connect slots_6.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[6].in_uop.bits.iw_p3_bypass_hint connect slots_6.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[6].in_uop.bits.iw_p2_bypass_hint connect slots_6.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[6].in_uop.bits.iw_p1_bypass_hint connect slots_6.io.in_uop.bits.iw_p2_speculative_child, issue_slots[6].in_uop.bits.iw_p2_speculative_child connect slots_6.io.in_uop.bits.iw_p1_speculative_child, issue_slots[6].in_uop.bits.iw_p1_speculative_child connect slots_6.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[6].in_uop.bits.iw_issued_partial_dgen connect slots_6.io.in_uop.bits.iw_issued_partial_agen, issue_slots[6].in_uop.bits.iw_issued_partial_agen connect slots_6.io.in_uop.bits.iw_issued, issue_slots[6].in_uop.bits.iw_issued connect slots_6.io.in_uop.bits.fu_code[0], issue_slots[6].in_uop.bits.fu_code[0] connect slots_6.io.in_uop.bits.fu_code[1], issue_slots[6].in_uop.bits.fu_code[1] connect slots_6.io.in_uop.bits.fu_code[2], issue_slots[6].in_uop.bits.fu_code[2] connect slots_6.io.in_uop.bits.fu_code[3], issue_slots[6].in_uop.bits.fu_code[3] connect slots_6.io.in_uop.bits.fu_code[4], issue_slots[6].in_uop.bits.fu_code[4] connect slots_6.io.in_uop.bits.fu_code[5], issue_slots[6].in_uop.bits.fu_code[5] connect slots_6.io.in_uop.bits.fu_code[6], issue_slots[6].in_uop.bits.fu_code[6] connect slots_6.io.in_uop.bits.fu_code[7], issue_slots[6].in_uop.bits.fu_code[7] connect slots_6.io.in_uop.bits.fu_code[8], issue_slots[6].in_uop.bits.fu_code[8] connect slots_6.io.in_uop.bits.fu_code[9], issue_slots[6].in_uop.bits.fu_code[9] connect slots_6.io.in_uop.bits.iq_type[0], issue_slots[6].in_uop.bits.iq_type[0] connect slots_6.io.in_uop.bits.iq_type[1], issue_slots[6].in_uop.bits.iq_type[1] connect slots_6.io.in_uop.bits.iq_type[2], issue_slots[6].in_uop.bits.iq_type[2] connect slots_6.io.in_uop.bits.iq_type[3], issue_slots[6].in_uop.bits.iq_type[3] connect slots_6.io.in_uop.bits.debug_pc, issue_slots[6].in_uop.bits.debug_pc connect slots_6.io.in_uop.bits.is_rvc, issue_slots[6].in_uop.bits.is_rvc connect slots_6.io.in_uop.bits.debug_inst, issue_slots[6].in_uop.bits.debug_inst connect slots_6.io.in_uop.bits.inst, issue_slots[6].in_uop.bits.inst connect slots_6.io.in_uop.valid, issue_slots[6].in_uop.valid connect issue_slots[6].iss_uop.debug_tsrc, slots_6.io.iss_uop.debug_tsrc connect issue_slots[6].iss_uop.debug_fsrc, slots_6.io.iss_uop.debug_fsrc connect issue_slots[6].iss_uop.bp_xcpt_if, slots_6.io.iss_uop.bp_xcpt_if connect issue_slots[6].iss_uop.bp_debug_if, slots_6.io.iss_uop.bp_debug_if connect issue_slots[6].iss_uop.xcpt_ma_if, slots_6.io.iss_uop.xcpt_ma_if connect issue_slots[6].iss_uop.xcpt_ae_if, slots_6.io.iss_uop.xcpt_ae_if connect issue_slots[6].iss_uop.xcpt_pf_if, slots_6.io.iss_uop.xcpt_pf_if connect issue_slots[6].iss_uop.fp_typ, slots_6.io.iss_uop.fp_typ connect issue_slots[6].iss_uop.fp_rm, slots_6.io.iss_uop.fp_rm connect issue_slots[6].iss_uop.fp_val, slots_6.io.iss_uop.fp_val connect issue_slots[6].iss_uop.fcn_op, slots_6.io.iss_uop.fcn_op connect issue_slots[6].iss_uop.fcn_dw, slots_6.io.iss_uop.fcn_dw connect issue_slots[6].iss_uop.frs3_en, slots_6.io.iss_uop.frs3_en connect issue_slots[6].iss_uop.lrs2_rtype, slots_6.io.iss_uop.lrs2_rtype connect issue_slots[6].iss_uop.lrs1_rtype, slots_6.io.iss_uop.lrs1_rtype connect issue_slots[6].iss_uop.dst_rtype, slots_6.io.iss_uop.dst_rtype connect issue_slots[6].iss_uop.lrs3, slots_6.io.iss_uop.lrs3 connect issue_slots[6].iss_uop.lrs2, slots_6.io.iss_uop.lrs2 connect issue_slots[6].iss_uop.lrs1, slots_6.io.iss_uop.lrs1 connect issue_slots[6].iss_uop.ldst, slots_6.io.iss_uop.ldst connect issue_slots[6].iss_uop.ldst_is_rs1, slots_6.io.iss_uop.ldst_is_rs1 connect issue_slots[6].iss_uop.csr_cmd, slots_6.io.iss_uop.csr_cmd connect issue_slots[6].iss_uop.flush_on_commit, slots_6.io.iss_uop.flush_on_commit connect issue_slots[6].iss_uop.is_unique, slots_6.io.iss_uop.is_unique connect issue_slots[6].iss_uop.uses_stq, slots_6.io.iss_uop.uses_stq connect issue_slots[6].iss_uop.uses_ldq, slots_6.io.iss_uop.uses_ldq connect issue_slots[6].iss_uop.mem_signed, slots_6.io.iss_uop.mem_signed connect issue_slots[6].iss_uop.mem_size, slots_6.io.iss_uop.mem_size connect issue_slots[6].iss_uop.mem_cmd, slots_6.io.iss_uop.mem_cmd connect issue_slots[6].iss_uop.exc_cause, slots_6.io.iss_uop.exc_cause connect issue_slots[6].iss_uop.exception, slots_6.io.iss_uop.exception connect issue_slots[6].iss_uop.stale_pdst, slots_6.io.iss_uop.stale_pdst connect issue_slots[6].iss_uop.ppred_busy, slots_6.io.iss_uop.ppred_busy connect issue_slots[6].iss_uop.prs3_busy, slots_6.io.iss_uop.prs3_busy connect issue_slots[6].iss_uop.prs2_busy, slots_6.io.iss_uop.prs2_busy connect issue_slots[6].iss_uop.prs1_busy, slots_6.io.iss_uop.prs1_busy connect issue_slots[6].iss_uop.ppred, slots_6.io.iss_uop.ppred connect issue_slots[6].iss_uop.prs3, slots_6.io.iss_uop.prs3 connect issue_slots[6].iss_uop.prs2, slots_6.io.iss_uop.prs2 connect issue_slots[6].iss_uop.prs1, slots_6.io.iss_uop.prs1 connect issue_slots[6].iss_uop.pdst, slots_6.io.iss_uop.pdst connect issue_slots[6].iss_uop.rxq_idx, slots_6.io.iss_uop.rxq_idx connect issue_slots[6].iss_uop.stq_idx, slots_6.io.iss_uop.stq_idx connect issue_slots[6].iss_uop.ldq_idx, slots_6.io.iss_uop.ldq_idx connect issue_slots[6].iss_uop.rob_idx, slots_6.io.iss_uop.rob_idx connect issue_slots[6].iss_uop.fp_ctrl.vec, slots_6.io.iss_uop.fp_ctrl.vec connect issue_slots[6].iss_uop.fp_ctrl.wflags, slots_6.io.iss_uop.fp_ctrl.wflags connect issue_slots[6].iss_uop.fp_ctrl.sqrt, slots_6.io.iss_uop.fp_ctrl.sqrt connect issue_slots[6].iss_uop.fp_ctrl.div, slots_6.io.iss_uop.fp_ctrl.div connect issue_slots[6].iss_uop.fp_ctrl.fma, slots_6.io.iss_uop.fp_ctrl.fma connect issue_slots[6].iss_uop.fp_ctrl.fastpipe, slots_6.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[6].iss_uop.fp_ctrl.toint, slots_6.io.iss_uop.fp_ctrl.toint connect issue_slots[6].iss_uop.fp_ctrl.fromint, slots_6.io.iss_uop.fp_ctrl.fromint connect issue_slots[6].iss_uop.fp_ctrl.typeTagOut, slots_6.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[6].iss_uop.fp_ctrl.typeTagIn, slots_6.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[6].iss_uop.fp_ctrl.swap23, slots_6.io.iss_uop.fp_ctrl.swap23 connect issue_slots[6].iss_uop.fp_ctrl.swap12, slots_6.io.iss_uop.fp_ctrl.swap12 connect issue_slots[6].iss_uop.fp_ctrl.ren3, slots_6.io.iss_uop.fp_ctrl.ren3 connect issue_slots[6].iss_uop.fp_ctrl.ren2, slots_6.io.iss_uop.fp_ctrl.ren2 connect issue_slots[6].iss_uop.fp_ctrl.ren1, slots_6.io.iss_uop.fp_ctrl.ren1 connect issue_slots[6].iss_uop.fp_ctrl.wen, slots_6.io.iss_uop.fp_ctrl.wen connect issue_slots[6].iss_uop.fp_ctrl.ldst, slots_6.io.iss_uop.fp_ctrl.ldst connect issue_slots[6].iss_uop.op2_sel, slots_6.io.iss_uop.op2_sel connect issue_slots[6].iss_uop.op1_sel, slots_6.io.iss_uop.op1_sel connect issue_slots[6].iss_uop.imm_packed, slots_6.io.iss_uop.imm_packed connect issue_slots[6].iss_uop.pimm, slots_6.io.iss_uop.pimm connect issue_slots[6].iss_uop.imm_sel, slots_6.io.iss_uop.imm_sel connect issue_slots[6].iss_uop.imm_rename, slots_6.io.iss_uop.imm_rename connect issue_slots[6].iss_uop.taken, slots_6.io.iss_uop.taken connect issue_slots[6].iss_uop.pc_lob, slots_6.io.iss_uop.pc_lob connect issue_slots[6].iss_uop.edge_inst, slots_6.io.iss_uop.edge_inst connect issue_slots[6].iss_uop.ftq_idx, slots_6.io.iss_uop.ftq_idx connect issue_slots[6].iss_uop.is_mov, slots_6.io.iss_uop.is_mov connect issue_slots[6].iss_uop.is_rocc, slots_6.io.iss_uop.is_rocc connect issue_slots[6].iss_uop.is_sys_pc2epc, slots_6.io.iss_uop.is_sys_pc2epc connect issue_slots[6].iss_uop.is_eret, slots_6.io.iss_uop.is_eret connect issue_slots[6].iss_uop.is_amo, slots_6.io.iss_uop.is_amo connect issue_slots[6].iss_uop.is_sfence, slots_6.io.iss_uop.is_sfence connect issue_slots[6].iss_uop.is_fencei, slots_6.io.iss_uop.is_fencei connect issue_slots[6].iss_uop.is_fence, slots_6.io.iss_uop.is_fence connect issue_slots[6].iss_uop.is_sfb, slots_6.io.iss_uop.is_sfb connect issue_slots[6].iss_uop.br_type, slots_6.io.iss_uop.br_type connect issue_slots[6].iss_uop.br_tag, slots_6.io.iss_uop.br_tag connect issue_slots[6].iss_uop.br_mask, slots_6.io.iss_uop.br_mask connect issue_slots[6].iss_uop.dis_col_sel, slots_6.io.iss_uop.dis_col_sel connect issue_slots[6].iss_uop.iw_p3_bypass_hint, slots_6.io.iss_uop.iw_p3_bypass_hint connect issue_slots[6].iss_uop.iw_p2_bypass_hint, slots_6.io.iss_uop.iw_p2_bypass_hint connect issue_slots[6].iss_uop.iw_p1_bypass_hint, slots_6.io.iss_uop.iw_p1_bypass_hint connect issue_slots[6].iss_uop.iw_p2_speculative_child, slots_6.io.iss_uop.iw_p2_speculative_child connect issue_slots[6].iss_uop.iw_p1_speculative_child, slots_6.io.iss_uop.iw_p1_speculative_child connect issue_slots[6].iss_uop.iw_issued_partial_dgen, slots_6.io.iss_uop.iw_issued_partial_dgen connect issue_slots[6].iss_uop.iw_issued_partial_agen, slots_6.io.iss_uop.iw_issued_partial_agen connect issue_slots[6].iss_uop.iw_issued, slots_6.io.iss_uop.iw_issued connect issue_slots[6].iss_uop.fu_code[0], slots_6.io.iss_uop.fu_code[0] connect issue_slots[6].iss_uop.fu_code[1], slots_6.io.iss_uop.fu_code[1] connect issue_slots[6].iss_uop.fu_code[2], slots_6.io.iss_uop.fu_code[2] connect issue_slots[6].iss_uop.fu_code[3], slots_6.io.iss_uop.fu_code[3] connect issue_slots[6].iss_uop.fu_code[4], slots_6.io.iss_uop.fu_code[4] connect issue_slots[6].iss_uop.fu_code[5], slots_6.io.iss_uop.fu_code[5] connect issue_slots[6].iss_uop.fu_code[6], slots_6.io.iss_uop.fu_code[6] connect issue_slots[6].iss_uop.fu_code[7], slots_6.io.iss_uop.fu_code[7] connect issue_slots[6].iss_uop.fu_code[8], slots_6.io.iss_uop.fu_code[8] connect issue_slots[6].iss_uop.fu_code[9], slots_6.io.iss_uop.fu_code[9] connect issue_slots[6].iss_uop.iq_type[0], slots_6.io.iss_uop.iq_type[0] connect issue_slots[6].iss_uop.iq_type[1], slots_6.io.iss_uop.iq_type[1] connect issue_slots[6].iss_uop.iq_type[2], slots_6.io.iss_uop.iq_type[2] connect issue_slots[6].iss_uop.iq_type[3], slots_6.io.iss_uop.iq_type[3] connect issue_slots[6].iss_uop.debug_pc, slots_6.io.iss_uop.debug_pc connect issue_slots[6].iss_uop.is_rvc, slots_6.io.iss_uop.is_rvc connect issue_slots[6].iss_uop.debug_inst, slots_6.io.iss_uop.debug_inst connect issue_slots[6].iss_uop.inst, slots_6.io.iss_uop.inst connect slots_6.io.grant, issue_slots[6].grant connect issue_slots[6].request, slots_6.io.request connect issue_slots[6].will_be_valid, slots_6.io.will_be_valid connect issue_slots[6].valid, slots_6.io.valid connect slots_7.io.child_rebusys, issue_slots[7].child_rebusys connect slots_7.io.pred_wakeup_port.bits, issue_slots[7].pred_wakeup_port.bits connect slots_7.io.pred_wakeup_port.valid, issue_slots[7].pred_wakeup_port.valid connect slots_7.io.wakeup_ports[0].bits.rebusy, issue_slots[7].wakeup_ports[0].bits.rebusy connect slots_7.io.wakeup_ports[0].bits.speculative_mask, issue_slots[7].wakeup_ports[0].bits.speculative_mask connect slots_7.io.wakeup_ports[0].bits.bypassable, issue_slots[7].wakeup_ports[0].bits.bypassable connect slots_7.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[0].bits.uop.debug_tsrc connect slots_7.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[0].bits.uop.debug_fsrc connect slots_7.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_7.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[0].bits.uop.bp_debug_if connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_7.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[7].wakeup_ports[0].bits.uop.fp_typ connect slots_7.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[7].wakeup_ports[0].bits.uop.fp_rm connect slots_7.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[7].wakeup_ports[0].bits.uop.fp_val connect slots_7.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[7].wakeup_ports[0].bits.uop.fcn_op connect slots_7.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[0].bits.uop.fcn_dw connect slots_7.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[7].wakeup_ports[0].bits.uop.frs3_en connect slots_7.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_7.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_7.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[0].bits.uop.dst_rtype connect slots_7.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[7].wakeup_ports[0].bits.uop.lrs3 connect slots_7.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[7].wakeup_ports[0].bits.uop.lrs2 connect slots_7.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[7].wakeup_ports[0].bits.uop.lrs1 connect slots_7.io.wakeup_ports[0].bits.uop.ldst, issue_slots[7].wakeup_ports[0].bits.uop.ldst connect slots_7.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_7.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[0].bits.uop.csr_cmd connect slots_7.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[0].bits.uop.flush_on_commit connect slots_7.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[7].wakeup_ports[0].bits.uop.is_unique connect slots_7.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[7].wakeup_ports[0].bits.uop.uses_stq connect slots_7.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[0].bits.uop.uses_ldq connect slots_7.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[7].wakeup_ports[0].bits.uop.mem_signed connect slots_7.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[7].wakeup_ports[0].bits.uop.mem_size connect slots_7.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[0].bits.uop.mem_cmd connect slots_7.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[7].wakeup_ports[0].bits.uop.exc_cause connect slots_7.io.wakeup_ports[0].bits.uop.exception, issue_slots[7].wakeup_ports[0].bits.uop.exception connect slots_7.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[0].bits.uop.stale_pdst connect slots_7.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[0].bits.uop.ppred_busy connect slots_7.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs3_busy connect slots_7.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs2_busy connect slots_7.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs1_busy connect slots_7.io.wakeup_ports[0].bits.uop.ppred, issue_slots[7].wakeup_ports[0].bits.uop.ppred connect slots_7.io.wakeup_ports[0].bits.uop.prs3, issue_slots[7].wakeup_ports[0].bits.uop.prs3 connect slots_7.io.wakeup_ports[0].bits.uop.prs2, issue_slots[7].wakeup_ports[0].bits.uop.prs2 connect slots_7.io.wakeup_ports[0].bits.uop.prs1, issue_slots[7].wakeup_ports[0].bits.uop.prs1 connect slots_7.io.wakeup_ports[0].bits.uop.pdst, issue_slots[7].wakeup_ports[0].bits.uop.pdst connect slots_7.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[0].bits.uop.rxq_idx connect slots_7.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[7].wakeup_ports[0].bits.uop.stq_idx connect slots_7.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[0].bits.uop.ldq_idx connect slots_7.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[7].wakeup_ports[0].bits.uop.rob_idx connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_7.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[7].wakeup_ports[0].bits.uop.op2_sel connect slots_7.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[7].wakeup_ports[0].bits.uop.op1_sel connect slots_7.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[7].wakeup_ports[0].bits.uop.imm_packed connect slots_7.io.wakeup_ports[0].bits.uop.pimm, issue_slots[7].wakeup_ports[0].bits.uop.pimm connect slots_7.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[7].wakeup_ports[0].bits.uop.imm_sel connect slots_7.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[7].wakeup_ports[0].bits.uop.imm_rename connect slots_7.io.wakeup_ports[0].bits.uop.taken, issue_slots[7].wakeup_ports[0].bits.uop.taken connect slots_7.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[7].wakeup_ports[0].bits.uop.pc_lob connect slots_7.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[7].wakeup_ports[0].bits.uop.edge_inst connect slots_7.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[0].bits.uop.ftq_idx connect slots_7.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[7].wakeup_ports[0].bits.uop.is_mov connect slots_7.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[7].wakeup_ports[0].bits.uop.is_rocc connect slots_7.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_7.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[7].wakeup_ports[0].bits.uop.is_eret connect slots_7.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[7].wakeup_ports[0].bits.uop.is_amo connect slots_7.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[7].wakeup_ports[0].bits.uop.is_sfence connect slots_7.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[7].wakeup_ports[0].bits.uop.is_fencei connect slots_7.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[7].wakeup_ports[0].bits.uop.is_fence connect slots_7.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[7].wakeup_ports[0].bits.uop.is_sfb connect slots_7.io.wakeup_ports[0].bits.uop.br_type, issue_slots[7].wakeup_ports[0].bits.uop.br_type connect slots_7.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[7].wakeup_ports[0].bits.uop.br_tag connect slots_7.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[7].wakeup_ports[0].bits.uop.br_mask connect slots_7.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[0].bits.uop.dis_col_sel connect slots_7.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_7.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_7.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_7.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_7.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[0] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[1] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[2] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[3] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[4] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[5] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[6] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[7] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[8] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[9] connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[0] connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[1] connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[2] connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[3] connect slots_7.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[7].wakeup_ports[0].bits.uop.debug_pc connect slots_7.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[7].wakeup_ports[0].bits.uop.is_rvc connect slots_7.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[7].wakeup_ports[0].bits.uop.debug_inst connect slots_7.io.wakeup_ports[0].bits.uop.inst, issue_slots[7].wakeup_ports[0].bits.uop.inst connect slots_7.io.wakeup_ports[0].valid, issue_slots[7].wakeup_ports[0].valid connect slots_7.io.wakeup_ports[1].bits.rebusy, issue_slots[7].wakeup_ports[1].bits.rebusy connect slots_7.io.wakeup_ports[1].bits.speculative_mask, issue_slots[7].wakeup_ports[1].bits.speculative_mask connect slots_7.io.wakeup_ports[1].bits.bypassable, issue_slots[7].wakeup_ports[1].bits.bypassable connect slots_7.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[1].bits.uop.debug_tsrc connect slots_7.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[1].bits.uop.debug_fsrc connect slots_7.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_7.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[1].bits.uop.bp_debug_if connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_7.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[7].wakeup_ports[1].bits.uop.fp_typ connect slots_7.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[7].wakeup_ports[1].bits.uop.fp_rm connect slots_7.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[7].wakeup_ports[1].bits.uop.fp_val connect slots_7.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[7].wakeup_ports[1].bits.uop.fcn_op connect slots_7.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[1].bits.uop.fcn_dw connect slots_7.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[7].wakeup_ports[1].bits.uop.frs3_en connect slots_7.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_7.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_7.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[1].bits.uop.dst_rtype connect slots_7.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[7].wakeup_ports[1].bits.uop.lrs3 connect slots_7.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[7].wakeup_ports[1].bits.uop.lrs2 connect slots_7.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[7].wakeup_ports[1].bits.uop.lrs1 connect slots_7.io.wakeup_ports[1].bits.uop.ldst, issue_slots[7].wakeup_ports[1].bits.uop.ldst connect slots_7.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_7.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[1].bits.uop.csr_cmd connect slots_7.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[1].bits.uop.flush_on_commit connect slots_7.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[7].wakeup_ports[1].bits.uop.is_unique connect slots_7.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[7].wakeup_ports[1].bits.uop.uses_stq connect slots_7.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[1].bits.uop.uses_ldq connect slots_7.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[7].wakeup_ports[1].bits.uop.mem_signed connect slots_7.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[7].wakeup_ports[1].bits.uop.mem_size connect slots_7.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[1].bits.uop.mem_cmd connect slots_7.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[7].wakeup_ports[1].bits.uop.exc_cause connect slots_7.io.wakeup_ports[1].bits.uop.exception, issue_slots[7].wakeup_ports[1].bits.uop.exception connect slots_7.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[1].bits.uop.stale_pdst connect slots_7.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[1].bits.uop.ppred_busy connect slots_7.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs3_busy connect slots_7.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs2_busy connect slots_7.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs1_busy connect slots_7.io.wakeup_ports[1].bits.uop.ppred, issue_slots[7].wakeup_ports[1].bits.uop.ppred connect slots_7.io.wakeup_ports[1].bits.uop.prs3, issue_slots[7].wakeup_ports[1].bits.uop.prs3 connect slots_7.io.wakeup_ports[1].bits.uop.prs2, issue_slots[7].wakeup_ports[1].bits.uop.prs2 connect slots_7.io.wakeup_ports[1].bits.uop.prs1, issue_slots[7].wakeup_ports[1].bits.uop.prs1 connect slots_7.io.wakeup_ports[1].bits.uop.pdst, issue_slots[7].wakeup_ports[1].bits.uop.pdst connect slots_7.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[1].bits.uop.rxq_idx connect slots_7.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[7].wakeup_ports[1].bits.uop.stq_idx connect slots_7.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[1].bits.uop.ldq_idx connect slots_7.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[7].wakeup_ports[1].bits.uop.rob_idx connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_7.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[7].wakeup_ports[1].bits.uop.op2_sel connect slots_7.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[7].wakeup_ports[1].bits.uop.op1_sel connect slots_7.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[7].wakeup_ports[1].bits.uop.imm_packed connect slots_7.io.wakeup_ports[1].bits.uop.pimm, issue_slots[7].wakeup_ports[1].bits.uop.pimm connect slots_7.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[7].wakeup_ports[1].bits.uop.imm_sel connect slots_7.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[7].wakeup_ports[1].bits.uop.imm_rename connect slots_7.io.wakeup_ports[1].bits.uop.taken, issue_slots[7].wakeup_ports[1].bits.uop.taken connect slots_7.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[7].wakeup_ports[1].bits.uop.pc_lob connect slots_7.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[7].wakeup_ports[1].bits.uop.edge_inst connect slots_7.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[1].bits.uop.ftq_idx connect slots_7.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[7].wakeup_ports[1].bits.uop.is_mov connect slots_7.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[7].wakeup_ports[1].bits.uop.is_rocc connect slots_7.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_7.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[7].wakeup_ports[1].bits.uop.is_eret connect slots_7.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[7].wakeup_ports[1].bits.uop.is_amo connect slots_7.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[7].wakeup_ports[1].bits.uop.is_sfence connect slots_7.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[7].wakeup_ports[1].bits.uop.is_fencei connect slots_7.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[7].wakeup_ports[1].bits.uop.is_fence connect slots_7.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[7].wakeup_ports[1].bits.uop.is_sfb connect slots_7.io.wakeup_ports[1].bits.uop.br_type, issue_slots[7].wakeup_ports[1].bits.uop.br_type connect slots_7.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[7].wakeup_ports[1].bits.uop.br_tag connect slots_7.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[7].wakeup_ports[1].bits.uop.br_mask connect slots_7.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[1].bits.uop.dis_col_sel connect slots_7.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_7.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_7.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_7.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_7.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[0] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[1] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[2] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[3] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[4] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[5] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[6] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[7] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[8] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[9] connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[0] connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[1] connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[2] connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[3] connect slots_7.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[7].wakeup_ports[1].bits.uop.debug_pc connect slots_7.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[7].wakeup_ports[1].bits.uop.is_rvc connect slots_7.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[7].wakeup_ports[1].bits.uop.debug_inst connect slots_7.io.wakeup_ports[1].bits.uop.inst, issue_slots[7].wakeup_ports[1].bits.uop.inst connect slots_7.io.wakeup_ports[1].valid, issue_slots[7].wakeup_ports[1].valid connect slots_7.io.wakeup_ports[2].bits.rebusy, issue_slots[7].wakeup_ports[2].bits.rebusy connect slots_7.io.wakeup_ports[2].bits.speculative_mask, issue_slots[7].wakeup_ports[2].bits.speculative_mask connect slots_7.io.wakeup_ports[2].bits.bypassable, issue_slots[7].wakeup_ports[2].bits.bypassable connect slots_7.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[2].bits.uop.debug_tsrc connect slots_7.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[2].bits.uop.debug_fsrc connect slots_7.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_7.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[2].bits.uop.bp_debug_if connect slots_7.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_7.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_7.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_7.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[7].wakeup_ports[2].bits.uop.fp_typ connect slots_7.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[7].wakeup_ports[2].bits.uop.fp_rm connect slots_7.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[7].wakeup_ports[2].bits.uop.fp_val connect slots_7.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[7].wakeup_ports[2].bits.uop.fcn_op connect slots_7.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[2].bits.uop.fcn_dw connect slots_7.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[7].wakeup_ports[2].bits.uop.frs3_en connect slots_7.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_7.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_7.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[2].bits.uop.dst_rtype connect slots_7.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[7].wakeup_ports[2].bits.uop.lrs3 connect slots_7.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[7].wakeup_ports[2].bits.uop.lrs2 connect slots_7.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[7].wakeup_ports[2].bits.uop.lrs1 connect slots_7.io.wakeup_ports[2].bits.uop.ldst, issue_slots[7].wakeup_ports[2].bits.uop.ldst connect slots_7.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_7.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[2].bits.uop.csr_cmd connect slots_7.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[2].bits.uop.flush_on_commit connect slots_7.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[7].wakeup_ports[2].bits.uop.is_unique connect slots_7.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[7].wakeup_ports[2].bits.uop.uses_stq connect slots_7.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[2].bits.uop.uses_ldq connect slots_7.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[7].wakeup_ports[2].bits.uop.mem_signed connect slots_7.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[7].wakeup_ports[2].bits.uop.mem_size connect slots_7.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[2].bits.uop.mem_cmd connect slots_7.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[7].wakeup_ports[2].bits.uop.exc_cause connect slots_7.io.wakeup_ports[2].bits.uop.exception, issue_slots[7].wakeup_ports[2].bits.uop.exception connect slots_7.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[2].bits.uop.stale_pdst connect slots_7.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[2].bits.uop.ppred_busy connect slots_7.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[2].bits.uop.prs3_busy connect slots_7.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[2].bits.uop.prs2_busy connect slots_7.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[2].bits.uop.prs1_busy connect slots_7.io.wakeup_ports[2].bits.uop.ppred, issue_slots[7].wakeup_ports[2].bits.uop.ppred connect slots_7.io.wakeup_ports[2].bits.uop.prs3, issue_slots[7].wakeup_ports[2].bits.uop.prs3 connect slots_7.io.wakeup_ports[2].bits.uop.prs2, issue_slots[7].wakeup_ports[2].bits.uop.prs2 connect slots_7.io.wakeup_ports[2].bits.uop.prs1, issue_slots[7].wakeup_ports[2].bits.uop.prs1 connect slots_7.io.wakeup_ports[2].bits.uop.pdst, issue_slots[7].wakeup_ports[2].bits.uop.pdst connect slots_7.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[2].bits.uop.rxq_idx connect slots_7.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[7].wakeup_ports[2].bits.uop.stq_idx connect slots_7.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[2].bits.uop.ldq_idx connect slots_7.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[7].wakeup_ports[2].bits.uop.rob_idx connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_7.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[7].wakeup_ports[2].bits.uop.op2_sel connect slots_7.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[7].wakeup_ports[2].bits.uop.op1_sel connect slots_7.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[7].wakeup_ports[2].bits.uop.imm_packed connect slots_7.io.wakeup_ports[2].bits.uop.pimm, issue_slots[7].wakeup_ports[2].bits.uop.pimm connect slots_7.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[7].wakeup_ports[2].bits.uop.imm_sel connect slots_7.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[7].wakeup_ports[2].bits.uop.imm_rename connect slots_7.io.wakeup_ports[2].bits.uop.taken, issue_slots[7].wakeup_ports[2].bits.uop.taken connect slots_7.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[7].wakeup_ports[2].bits.uop.pc_lob connect slots_7.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[7].wakeup_ports[2].bits.uop.edge_inst connect slots_7.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[2].bits.uop.ftq_idx connect slots_7.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[7].wakeup_ports[2].bits.uop.is_mov connect slots_7.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[7].wakeup_ports[2].bits.uop.is_rocc connect slots_7.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_7.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[7].wakeup_ports[2].bits.uop.is_eret connect slots_7.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[7].wakeup_ports[2].bits.uop.is_amo connect slots_7.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[7].wakeup_ports[2].bits.uop.is_sfence connect slots_7.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[7].wakeup_ports[2].bits.uop.is_fencei connect slots_7.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[7].wakeup_ports[2].bits.uop.is_fence connect slots_7.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[7].wakeup_ports[2].bits.uop.is_sfb connect slots_7.io.wakeup_ports[2].bits.uop.br_type, issue_slots[7].wakeup_ports[2].bits.uop.br_type connect slots_7.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[7].wakeup_ports[2].bits.uop.br_tag connect slots_7.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[7].wakeup_ports[2].bits.uop.br_mask connect slots_7.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[2].bits.uop.dis_col_sel connect slots_7.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_7.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_7.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_7.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_7.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_7.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_7.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_7.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[7].wakeup_ports[2].bits.uop.iw_issued connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[0] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[1] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[2] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[3] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[4] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[5] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[6] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[7] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[8] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[9] connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[0] connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[1] connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[2] connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[3] connect slots_7.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[7].wakeup_ports[2].bits.uop.debug_pc connect slots_7.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[7].wakeup_ports[2].bits.uop.is_rvc connect slots_7.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[7].wakeup_ports[2].bits.uop.debug_inst connect slots_7.io.wakeup_ports[2].bits.uop.inst, issue_slots[7].wakeup_ports[2].bits.uop.inst connect slots_7.io.wakeup_ports[2].valid, issue_slots[7].wakeup_ports[2].valid connect slots_7.io.wakeup_ports[3].bits.rebusy, issue_slots[7].wakeup_ports[3].bits.rebusy connect slots_7.io.wakeup_ports[3].bits.speculative_mask, issue_slots[7].wakeup_ports[3].bits.speculative_mask connect slots_7.io.wakeup_ports[3].bits.bypassable, issue_slots[7].wakeup_ports[3].bits.bypassable connect slots_7.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[3].bits.uop.debug_tsrc connect slots_7.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[3].bits.uop.debug_fsrc connect slots_7.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_7.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[3].bits.uop.bp_debug_if connect slots_7.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_7.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_7.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_7.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[7].wakeup_ports[3].bits.uop.fp_typ connect slots_7.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[7].wakeup_ports[3].bits.uop.fp_rm connect slots_7.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[7].wakeup_ports[3].bits.uop.fp_val connect slots_7.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[7].wakeup_ports[3].bits.uop.fcn_op connect slots_7.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[3].bits.uop.fcn_dw connect slots_7.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[7].wakeup_ports[3].bits.uop.frs3_en connect slots_7.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_7.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_7.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[3].bits.uop.dst_rtype connect slots_7.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[7].wakeup_ports[3].bits.uop.lrs3 connect slots_7.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[7].wakeup_ports[3].bits.uop.lrs2 connect slots_7.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[7].wakeup_ports[3].bits.uop.lrs1 connect slots_7.io.wakeup_ports[3].bits.uop.ldst, issue_slots[7].wakeup_ports[3].bits.uop.ldst connect slots_7.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_7.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[3].bits.uop.csr_cmd connect slots_7.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[3].bits.uop.flush_on_commit connect slots_7.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[7].wakeup_ports[3].bits.uop.is_unique connect slots_7.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[7].wakeup_ports[3].bits.uop.uses_stq connect slots_7.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[3].bits.uop.uses_ldq connect slots_7.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[7].wakeup_ports[3].bits.uop.mem_signed connect slots_7.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[7].wakeup_ports[3].bits.uop.mem_size connect slots_7.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[3].bits.uop.mem_cmd connect slots_7.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[7].wakeup_ports[3].bits.uop.exc_cause connect slots_7.io.wakeup_ports[3].bits.uop.exception, issue_slots[7].wakeup_ports[3].bits.uop.exception connect slots_7.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[3].bits.uop.stale_pdst connect slots_7.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[3].bits.uop.ppred_busy connect slots_7.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[3].bits.uop.prs3_busy connect slots_7.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[3].bits.uop.prs2_busy connect slots_7.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[3].bits.uop.prs1_busy connect slots_7.io.wakeup_ports[3].bits.uop.ppred, issue_slots[7].wakeup_ports[3].bits.uop.ppred connect slots_7.io.wakeup_ports[3].bits.uop.prs3, issue_slots[7].wakeup_ports[3].bits.uop.prs3 connect slots_7.io.wakeup_ports[3].bits.uop.prs2, issue_slots[7].wakeup_ports[3].bits.uop.prs2 connect slots_7.io.wakeup_ports[3].bits.uop.prs1, issue_slots[7].wakeup_ports[3].bits.uop.prs1 connect slots_7.io.wakeup_ports[3].bits.uop.pdst, issue_slots[7].wakeup_ports[3].bits.uop.pdst connect slots_7.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[3].bits.uop.rxq_idx connect slots_7.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[7].wakeup_ports[3].bits.uop.stq_idx connect slots_7.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[3].bits.uop.ldq_idx connect slots_7.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[7].wakeup_ports[3].bits.uop.rob_idx connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_7.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[7].wakeup_ports[3].bits.uop.op2_sel connect slots_7.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[7].wakeup_ports[3].bits.uop.op1_sel connect slots_7.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[7].wakeup_ports[3].bits.uop.imm_packed connect slots_7.io.wakeup_ports[3].bits.uop.pimm, issue_slots[7].wakeup_ports[3].bits.uop.pimm connect slots_7.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[7].wakeup_ports[3].bits.uop.imm_sel connect slots_7.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[7].wakeup_ports[3].bits.uop.imm_rename connect slots_7.io.wakeup_ports[3].bits.uop.taken, issue_slots[7].wakeup_ports[3].bits.uop.taken connect slots_7.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[7].wakeup_ports[3].bits.uop.pc_lob connect slots_7.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[7].wakeup_ports[3].bits.uop.edge_inst connect slots_7.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[3].bits.uop.ftq_idx connect slots_7.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[7].wakeup_ports[3].bits.uop.is_mov connect slots_7.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[7].wakeup_ports[3].bits.uop.is_rocc connect slots_7.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_7.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[7].wakeup_ports[3].bits.uop.is_eret connect slots_7.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[7].wakeup_ports[3].bits.uop.is_amo connect slots_7.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[7].wakeup_ports[3].bits.uop.is_sfence connect slots_7.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[7].wakeup_ports[3].bits.uop.is_fencei connect slots_7.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[7].wakeup_ports[3].bits.uop.is_fence connect slots_7.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[7].wakeup_ports[3].bits.uop.is_sfb connect slots_7.io.wakeup_ports[3].bits.uop.br_type, issue_slots[7].wakeup_ports[3].bits.uop.br_type connect slots_7.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[7].wakeup_ports[3].bits.uop.br_tag connect slots_7.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[7].wakeup_ports[3].bits.uop.br_mask connect slots_7.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[3].bits.uop.dis_col_sel connect slots_7.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_7.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_7.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_7.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_7.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_7.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_7.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_7.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[7].wakeup_ports[3].bits.uop.iw_issued connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[0] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[1] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[2] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[3] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[4] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[5] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[6] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[7] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[8] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[9] connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[0] connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[1] connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[2] connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[3] connect slots_7.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[7].wakeup_ports[3].bits.uop.debug_pc connect slots_7.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[7].wakeup_ports[3].bits.uop.is_rvc connect slots_7.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[7].wakeup_ports[3].bits.uop.debug_inst connect slots_7.io.wakeup_ports[3].bits.uop.inst, issue_slots[7].wakeup_ports[3].bits.uop.inst connect slots_7.io.wakeup_ports[3].valid, issue_slots[7].wakeup_ports[3].valid connect slots_7.io.wakeup_ports[4].bits.rebusy, issue_slots[7].wakeup_ports[4].bits.rebusy connect slots_7.io.wakeup_ports[4].bits.speculative_mask, issue_slots[7].wakeup_ports[4].bits.speculative_mask connect slots_7.io.wakeup_ports[4].bits.bypassable, issue_slots[7].wakeup_ports[4].bits.bypassable connect slots_7.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[4].bits.uop.debug_tsrc connect slots_7.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[4].bits.uop.debug_fsrc connect slots_7.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_7.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[4].bits.uop.bp_debug_if connect slots_7.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_7.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_7.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_7.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[7].wakeup_ports[4].bits.uop.fp_typ connect slots_7.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[7].wakeup_ports[4].bits.uop.fp_rm connect slots_7.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[7].wakeup_ports[4].bits.uop.fp_val connect slots_7.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[7].wakeup_ports[4].bits.uop.fcn_op connect slots_7.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[4].bits.uop.fcn_dw connect slots_7.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[7].wakeup_ports[4].bits.uop.frs3_en connect slots_7.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_7.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_7.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[4].bits.uop.dst_rtype connect slots_7.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[7].wakeup_ports[4].bits.uop.lrs3 connect slots_7.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[7].wakeup_ports[4].bits.uop.lrs2 connect slots_7.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[7].wakeup_ports[4].bits.uop.lrs1 connect slots_7.io.wakeup_ports[4].bits.uop.ldst, issue_slots[7].wakeup_ports[4].bits.uop.ldst connect slots_7.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_7.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[4].bits.uop.csr_cmd connect slots_7.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[4].bits.uop.flush_on_commit connect slots_7.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[7].wakeup_ports[4].bits.uop.is_unique connect slots_7.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[7].wakeup_ports[4].bits.uop.uses_stq connect slots_7.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[4].bits.uop.uses_ldq connect slots_7.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[7].wakeup_ports[4].bits.uop.mem_signed connect slots_7.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[7].wakeup_ports[4].bits.uop.mem_size connect slots_7.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[4].bits.uop.mem_cmd connect slots_7.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[7].wakeup_ports[4].bits.uop.exc_cause connect slots_7.io.wakeup_ports[4].bits.uop.exception, issue_slots[7].wakeup_ports[4].bits.uop.exception connect slots_7.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[4].bits.uop.stale_pdst connect slots_7.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[4].bits.uop.ppred_busy connect slots_7.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[4].bits.uop.prs3_busy connect slots_7.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[4].bits.uop.prs2_busy connect slots_7.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[4].bits.uop.prs1_busy connect slots_7.io.wakeup_ports[4].bits.uop.ppred, issue_slots[7].wakeup_ports[4].bits.uop.ppred connect slots_7.io.wakeup_ports[4].bits.uop.prs3, issue_slots[7].wakeup_ports[4].bits.uop.prs3 connect slots_7.io.wakeup_ports[4].bits.uop.prs2, issue_slots[7].wakeup_ports[4].bits.uop.prs2 connect slots_7.io.wakeup_ports[4].bits.uop.prs1, issue_slots[7].wakeup_ports[4].bits.uop.prs1 connect slots_7.io.wakeup_ports[4].bits.uop.pdst, issue_slots[7].wakeup_ports[4].bits.uop.pdst connect slots_7.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[4].bits.uop.rxq_idx connect slots_7.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[7].wakeup_ports[4].bits.uop.stq_idx connect slots_7.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[4].bits.uop.ldq_idx connect slots_7.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[7].wakeup_ports[4].bits.uop.rob_idx connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_7.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[7].wakeup_ports[4].bits.uop.op2_sel connect slots_7.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[7].wakeup_ports[4].bits.uop.op1_sel connect slots_7.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[7].wakeup_ports[4].bits.uop.imm_packed connect slots_7.io.wakeup_ports[4].bits.uop.pimm, issue_slots[7].wakeup_ports[4].bits.uop.pimm connect slots_7.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[7].wakeup_ports[4].bits.uop.imm_sel connect slots_7.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[7].wakeup_ports[4].bits.uop.imm_rename connect slots_7.io.wakeup_ports[4].bits.uop.taken, issue_slots[7].wakeup_ports[4].bits.uop.taken connect slots_7.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[7].wakeup_ports[4].bits.uop.pc_lob connect slots_7.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[7].wakeup_ports[4].bits.uop.edge_inst connect slots_7.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[4].bits.uop.ftq_idx connect slots_7.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[7].wakeup_ports[4].bits.uop.is_mov connect slots_7.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[7].wakeup_ports[4].bits.uop.is_rocc connect slots_7.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_7.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[7].wakeup_ports[4].bits.uop.is_eret connect slots_7.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[7].wakeup_ports[4].bits.uop.is_amo connect slots_7.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[7].wakeup_ports[4].bits.uop.is_sfence connect slots_7.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[7].wakeup_ports[4].bits.uop.is_fencei connect slots_7.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[7].wakeup_ports[4].bits.uop.is_fence connect slots_7.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[7].wakeup_ports[4].bits.uop.is_sfb connect slots_7.io.wakeup_ports[4].bits.uop.br_type, issue_slots[7].wakeup_ports[4].bits.uop.br_type connect slots_7.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[7].wakeup_ports[4].bits.uop.br_tag connect slots_7.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[7].wakeup_ports[4].bits.uop.br_mask connect slots_7.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[4].bits.uop.dis_col_sel connect slots_7.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_7.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_7.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_7.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_7.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_7.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_7.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_7.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[7].wakeup_ports[4].bits.uop.iw_issued connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[0] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[1] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[2] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[3] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[4] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[5] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[6] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[7] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[8] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[9] connect slots_7.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[4].bits.uop.iq_type[0] connect slots_7.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[4].bits.uop.iq_type[1] connect slots_7.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[4].bits.uop.iq_type[2] connect slots_7.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[4].bits.uop.iq_type[3] connect slots_7.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[7].wakeup_ports[4].bits.uop.debug_pc connect slots_7.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[7].wakeup_ports[4].bits.uop.is_rvc connect slots_7.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[7].wakeup_ports[4].bits.uop.debug_inst connect slots_7.io.wakeup_ports[4].bits.uop.inst, issue_slots[7].wakeup_ports[4].bits.uop.inst connect slots_7.io.wakeup_ports[4].valid, issue_slots[7].wakeup_ports[4].valid connect slots_7.io.squash_grant, issue_slots[7].squash_grant connect slots_7.io.clear, issue_slots[7].clear connect slots_7.io.kill, issue_slots[7].kill connect slots_7.io.brupdate.b2.target_offset, issue_slots[7].brupdate.b2.target_offset connect slots_7.io.brupdate.b2.jalr_target, issue_slots[7].brupdate.b2.jalr_target connect slots_7.io.brupdate.b2.pc_sel, issue_slots[7].brupdate.b2.pc_sel connect slots_7.io.brupdate.b2.cfi_type, issue_slots[7].brupdate.b2.cfi_type connect slots_7.io.brupdate.b2.taken, issue_slots[7].brupdate.b2.taken connect slots_7.io.brupdate.b2.mispredict, issue_slots[7].brupdate.b2.mispredict connect slots_7.io.brupdate.b2.uop.debug_tsrc, issue_slots[7].brupdate.b2.uop.debug_tsrc connect slots_7.io.brupdate.b2.uop.debug_fsrc, issue_slots[7].brupdate.b2.uop.debug_fsrc connect slots_7.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[7].brupdate.b2.uop.bp_xcpt_if connect slots_7.io.brupdate.b2.uop.bp_debug_if, issue_slots[7].brupdate.b2.uop.bp_debug_if connect slots_7.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[7].brupdate.b2.uop.xcpt_ma_if connect slots_7.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[7].brupdate.b2.uop.xcpt_ae_if connect slots_7.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[7].brupdate.b2.uop.xcpt_pf_if connect slots_7.io.brupdate.b2.uop.fp_typ, issue_slots[7].brupdate.b2.uop.fp_typ connect slots_7.io.brupdate.b2.uop.fp_rm, issue_slots[7].brupdate.b2.uop.fp_rm connect slots_7.io.brupdate.b2.uop.fp_val, issue_slots[7].brupdate.b2.uop.fp_val connect slots_7.io.brupdate.b2.uop.fcn_op, issue_slots[7].brupdate.b2.uop.fcn_op connect slots_7.io.brupdate.b2.uop.fcn_dw, issue_slots[7].brupdate.b2.uop.fcn_dw connect slots_7.io.brupdate.b2.uop.frs3_en, issue_slots[7].brupdate.b2.uop.frs3_en connect slots_7.io.brupdate.b2.uop.lrs2_rtype, issue_slots[7].brupdate.b2.uop.lrs2_rtype connect slots_7.io.brupdate.b2.uop.lrs1_rtype, issue_slots[7].brupdate.b2.uop.lrs1_rtype connect slots_7.io.brupdate.b2.uop.dst_rtype, issue_slots[7].brupdate.b2.uop.dst_rtype connect slots_7.io.brupdate.b2.uop.lrs3, issue_slots[7].brupdate.b2.uop.lrs3 connect slots_7.io.brupdate.b2.uop.lrs2, issue_slots[7].brupdate.b2.uop.lrs2 connect slots_7.io.brupdate.b2.uop.lrs1, issue_slots[7].brupdate.b2.uop.lrs1 connect slots_7.io.brupdate.b2.uop.ldst, issue_slots[7].brupdate.b2.uop.ldst connect slots_7.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[7].brupdate.b2.uop.ldst_is_rs1 connect slots_7.io.brupdate.b2.uop.csr_cmd, issue_slots[7].brupdate.b2.uop.csr_cmd connect slots_7.io.brupdate.b2.uop.flush_on_commit, issue_slots[7].brupdate.b2.uop.flush_on_commit connect slots_7.io.brupdate.b2.uop.is_unique, issue_slots[7].brupdate.b2.uop.is_unique connect slots_7.io.brupdate.b2.uop.uses_stq, issue_slots[7].brupdate.b2.uop.uses_stq connect slots_7.io.brupdate.b2.uop.uses_ldq, issue_slots[7].brupdate.b2.uop.uses_ldq connect slots_7.io.brupdate.b2.uop.mem_signed, issue_slots[7].brupdate.b2.uop.mem_signed connect slots_7.io.brupdate.b2.uop.mem_size, issue_slots[7].brupdate.b2.uop.mem_size connect slots_7.io.brupdate.b2.uop.mem_cmd, issue_slots[7].brupdate.b2.uop.mem_cmd connect slots_7.io.brupdate.b2.uop.exc_cause, issue_slots[7].brupdate.b2.uop.exc_cause connect slots_7.io.brupdate.b2.uop.exception, issue_slots[7].brupdate.b2.uop.exception connect slots_7.io.brupdate.b2.uop.stale_pdst, issue_slots[7].brupdate.b2.uop.stale_pdst connect slots_7.io.brupdate.b2.uop.ppred_busy, issue_slots[7].brupdate.b2.uop.ppred_busy connect slots_7.io.brupdate.b2.uop.prs3_busy, issue_slots[7].brupdate.b2.uop.prs3_busy connect slots_7.io.brupdate.b2.uop.prs2_busy, issue_slots[7].brupdate.b2.uop.prs2_busy connect slots_7.io.brupdate.b2.uop.prs1_busy, issue_slots[7].brupdate.b2.uop.prs1_busy connect slots_7.io.brupdate.b2.uop.ppred, issue_slots[7].brupdate.b2.uop.ppred connect slots_7.io.brupdate.b2.uop.prs3, issue_slots[7].brupdate.b2.uop.prs3 connect slots_7.io.brupdate.b2.uop.prs2, issue_slots[7].brupdate.b2.uop.prs2 connect slots_7.io.brupdate.b2.uop.prs1, issue_slots[7].brupdate.b2.uop.prs1 connect slots_7.io.brupdate.b2.uop.pdst, issue_slots[7].brupdate.b2.uop.pdst connect slots_7.io.brupdate.b2.uop.rxq_idx, issue_slots[7].brupdate.b2.uop.rxq_idx connect slots_7.io.brupdate.b2.uop.stq_idx, issue_slots[7].brupdate.b2.uop.stq_idx connect slots_7.io.brupdate.b2.uop.ldq_idx, issue_slots[7].brupdate.b2.uop.ldq_idx connect slots_7.io.brupdate.b2.uop.rob_idx, issue_slots[7].brupdate.b2.uop.rob_idx connect slots_7.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[7].brupdate.b2.uop.fp_ctrl.vec connect slots_7.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[7].brupdate.b2.uop.fp_ctrl.wflags connect slots_7.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[7].brupdate.b2.uop.fp_ctrl.sqrt connect slots_7.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[7].brupdate.b2.uop.fp_ctrl.div connect slots_7.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[7].brupdate.b2.uop.fp_ctrl.fma connect slots_7.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[7].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_7.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[7].brupdate.b2.uop.fp_ctrl.toint connect slots_7.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[7].brupdate.b2.uop.fp_ctrl.fromint connect slots_7.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_7.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_7.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[7].brupdate.b2.uop.fp_ctrl.swap23 connect slots_7.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[7].brupdate.b2.uop.fp_ctrl.swap12 connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren3 connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren2 connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren1 connect slots_7.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[7].brupdate.b2.uop.fp_ctrl.wen connect slots_7.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[7].brupdate.b2.uop.fp_ctrl.ldst connect slots_7.io.brupdate.b2.uop.op2_sel, issue_slots[7].brupdate.b2.uop.op2_sel connect slots_7.io.brupdate.b2.uop.op1_sel, issue_slots[7].brupdate.b2.uop.op1_sel connect slots_7.io.brupdate.b2.uop.imm_packed, issue_slots[7].brupdate.b2.uop.imm_packed connect slots_7.io.brupdate.b2.uop.pimm, issue_slots[7].brupdate.b2.uop.pimm connect slots_7.io.brupdate.b2.uop.imm_sel, issue_slots[7].brupdate.b2.uop.imm_sel connect slots_7.io.brupdate.b2.uop.imm_rename, issue_slots[7].brupdate.b2.uop.imm_rename connect slots_7.io.brupdate.b2.uop.taken, issue_slots[7].brupdate.b2.uop.taken connect slots_7.io.brupdate.b2.uop.pc_lob, issue_slots[7].brupdate.b2.uop.pc_lob connect slots_7.io.brupdate.b2.uop.edge_inst, issue_slots[7].brupdate.b2.uop.edge_inst connect slots_7.io.brupdate.b2.uop.ftq_idx, issue_slots[7].brupdate.b2.uop.ftq_idx connect slots_7.io.brupdate.b2.uop.is_mov, issue_slots[7].brupdate.b2.uop.is_mov connect slots_7.io.brupdate.b2.uop.is_rocc, issue_slots[7].brupdate.b2.uop.is_rocc connect slots_7.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[7].brupdate.b2.uop.is_sys_pc2epc connect slots_7.io.brupdate.b2.uop.is_eret, issue_slots[7].brupdate.b2.uop.is_eret connect slots_7.io.brupdate.b2.uop.is_amo, issue_slots[7].brupdate.b2.uop.is_amo connect slots_7.io.brupdate.b2.uop.is_sfence, issue_slots[7].brupdate.b2.uop.is_sfence connect slots_7.io.brupdate.b2.uop.is_fencei, issue_slots[7].brupdate.b2.uop.is_fencei connect slots_7.io.brupdate.b2.uop.is_fence, issue_slots[7].brupdate.b2.uop.is_fence connect slots_7.io.brupdate.b2.uop.is_sfb, issue_slots[7].brupdate.b2.uop.is_sfb connect slots_7.io.brupdate.b2.uop.br_type, issue_slots[7].brupdate.b2.uop.br_type connect slots_7.io.brupdate.b2.uop.br_tag, issue_slots[7].brupdate.b2.uop.br_tag connect slots_7.io.brupdate.b2.uop.br_mask, issue_slots[7].brupdate.b2.uop.br_mask connect slots_7.io.brupdate.b2.uop.dis_col_sel, issue_slots[7].brupdate.b2.uop.dis_col_sel connect slots_7.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p3_bypass_hint connect slots_7.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p2_bypass_hint connect slots_7.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p1_bypass_hint connect slots_7.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[7].brupdate.b2.uop.iw_p2_speculative_child connect slots_7.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[7].brupdate.b2.uop.iw_p1_speculative_child connect slots_7.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[7].brupdate.b2.uop.iw_issued_partial_dgen connect slots_7.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[7].brupdate.b2.uop.iw_issued_partial_agen connect slots_7.io.brupdate.b2.uop.iw_issued, issue_slots[7].brupdate.b2.uop.iw_issued connect slots_7.io.brupdate.b2.uop.fu_code[0], issue_slots[7].brupdate.b2.uop.fu_code[0] connect slots_7.io.brupdate.b2.uop.fu_code[1], issue_slots[7].brupdate.b2.uop.fu_code[1] connect slots_7.io.brupdate.b2.uop.fu_code[2], issue_slots[7].brupdate.b2.uop.fu_code[2] connect slots_7.io.brupdate.b2.uop.fu_code[3], issue_slots[7].brupdate.b2.uop.fu_code[3] connect slots_7.io.brupdate.b2.uop.fu_code[4], issue_slots[7].brupdate.b2.uop.fu_code[4] connect slots_7.io.brupdate.b2.uop.fu_code[5], issue_slots[7].brupdate.b2.uop.fu_code[5] connect slots_7.io.brupdate.b2.uop.fu_code[6], issue_slots[7].brupdate.b2.uop.fu_code[6] connect slots_7.io.brupdate.b2.uop.fu_code[7], issue_slots[7].brupdate.b2.uop.fu_code[7] connect slots_7.io.brupdate.b2.uop.fu_code[8], issue_slots[7].brupdate.b2.uop.fu_code[8] connect slots_7.io.brupdate.b2.uop.fu_code[9], issue_slots[7].brupdate.b2.uop.fu_code[9] connect slots_7.io.brupdate.b2.uop.iq_type[0], issue_slots[7].brupdate.b2.uop.iq_type[0] connect slots_7.io.brupdate.b2.uop.iq_type[1], issue_slots[7].brupdate.b2.uop.iq_type[1] connect slots_7.io.brupdate.b2.uop.iq_type[2], issue_slots[7].brupdate.b2.uop.iq_type[2] connect slots_7.io.brupdate.b2.uop.iq_type[3], issue_slots[7].brupdate.b2.uop.iq_type[3] connect slots_7.io.brupdate.b2.uop.debug_pc, issue_slots[7].brupdate.b2.uop.debug_pc connect slots_7.io.brupdate.b2.uop.is_rvc, issue_slots[7].brupdate.b2.uop.is_rvc connect slots_7.io.brupdate.b2.uop.debug_inst, issue_slots[7].brupdate.b2.uop.debug_inst connect slots_7.io.brupdate.b2.uop.inst, issue_slots[7].brupdate.b2.uop.inst connect slots_7.io.brupdate.b1.mispredict_mask, issue_slots[7].brupdate.b1.mispredict_mask connect slots_7.io.brupdate.b1.resolve_mask, issue_slots[7].brupdate.b1.resolve_mask connect issue_slots[7].out_uop.debug_tsrc, slots_7.io.out_uop.debug_tsrc connect issue_slots[7].out_uop.debug_fsrc, slots_7.io.out_uop.debug_fsrc connect issue_slots[7].out_uop.bp_xcpt_if, slots_7.io.out_uop.bp_xcpt_if connect issue_slots[7].out_uop.bp_debug_if, slots_7.io.out_uop.bp_debug_if connect issue_slots[7].out_uop.xcpt_ma_if, slots_7.io.out_uop.xcpt_ma_if connect issue_slots[7].out_uop.xcpt_ae_if, slots_7.io.out_uop.xcpt_ae_if connect issue_slots[7].out_uop.xcpt_pf_if, slots_7.io.out_uop.xcpt_pf_if connect issue_slots[7].out_uop.fp_typ, slots_7.io.out_uop.fp_typ connect issue_slots[7].out_uop.fp_rm, slots_7.io.out_uop.fp_rm connect issue_slots[7].out_uop.fp_val, slots_7.io.out_uop.fp_val connect issue_slots[7].out_uop.fcn_op, slots_7.io.out_uop.fcn_op connect issue_slots[7].out_uop.fcn_dw, slots_7.io.out_uop.fcn_dw connect issue_slots[7].out_uop.frs3_en, slots_7.io.out_uop.frs3_en connect issue_slots[7].out_uop.lrs2_rtype, slots_7.io.out_uop.lrs2_rtype connect issue_slots[7].out_uop.lrs1_rtype, slots_7.io.out_uop.lrs1_rtype connect issue_slots[7].out_uop.dst_rtype, slots_7.io.out_uop.dst_rtype connect issue_slots[7].out_uop.lrs3, slots_7.io.out_uop.lrs3 connect issue_slots[7].out_uop.lrs2, slots_7.io.out_uop.lrs2 connect issue_slots[7].out_uop.lrs1, slots_7.io.out_uop.lrs1 connect issue_slots[7].out_uop.ldst, slots_7.io.out_uop.ldst connect issue_slots[7].out_uop.ldst_is_rs1, slots_7.io.out_uop.ldst_is_rs1 connect issue_slots[7].out_uop.csr_cmd, slots_7.io.out_uop.csr_cmd connect issue_slots[7].out_uop.flush_on_commit, slots_7.io.out_uop.flush_on_commit connect issue_slots[7].out_uop.is_unique, slots_7.io.out_uop.is_unique connect issue_slots[7].out_uop.uses_stq, slots_7.io.out_uop.uses_stq connect issue_slots[7].out_uop.uses_ldq, slots_7.io.out_uop.uses_ldq connect issue_slots[7].out_uop.mem_signed, slots_7.io.out_uop.mem_signed connect issue_slots[7].out_uop.mem_size, slots_7.io.out_uop.mem_size connect issue_slots[7].out_uop.mem_cmd, slots_7.io.out_uop.mem_cmd connect issue_slots[7].out_uop.exc_cause, slots_7.io.out_uop.exc_cause connect issue_slots[7].out_uop.exception, slots_7.io.out_uop.exception connect issue_slots[7].out_uop.stale_pdst, slots_7.io.out_uop.stale_pdst connect issue_slots[7].out_uop.ppred_busy, slots_7.io.out_uop.ppred_busy connect issue_slots[7].out_uop.prs3_busy, slots_7.io.out_uop.prs3_busy connect issue_slots[7].out_uop.prs2_busy, slots_7.io.out_uop.prs2_busy connect issue_slots[7].out_uop.prs1_busy, slots_7.io.out_uop.prs1_busy connect issue_slots[7].out_uop.ppred, slots_7.io.out_uop.ppred connect issue_slots[7].out_uop.prs3, slots_7.io.out_uop.prs3 connect issue_slots[7].out_uop.prs2, slots_7.io.out_uop.prs2 connect issue_slots[7].out_uop.prs1, slots_7.io.out_uop.prs1 connect issue_slots[7].out_uop.pdst, slots_7.io.out_uop.pdst connect issue_slots[7].out_uop.rxq_idx, slots_7.io.out_uop.rxq_idx connect issue_slots[7].out_uop.stq_idx, slots_7.io.out_uop.stq_idx connect issue_slots[7].out_uop.ldq_idx, slots_7.io.out_uop.ldq_idx connect issue_slots[7].out_uop.rob_idx, slots_7.io.out_uop.rob_idx connect issue_slots[7].out_uop.fp_ctrl.vec, slots_7.io.out_uop.fp_ctrl.vec connect issue_slots[7].out_uop.fp_ctrl.wflags, slots_7.io.out_uop.fp_ctrl.wflags connect issue_slots[7].out_uop.fp_ctrl.sqrt, slots_7.io.out_uop.fp_ctrl.sqrt connect issue_slots[7].out_uop.fp_ctrl.div, slots_7.io.out_uop.fp_ctrl.div connect issue_slots[7].out_uop.fp_ctrl.fma, slots_7.io.out_uop.fp_ctrl.fma connect issue_slots[7].out_uop.fp_ctrl.fastpipe, slots_7.io.out_uop.fp_ctrl.fastpipe connect issue_slots[7].out_uop.fp_ctrl.toint, slots_7.io.out_uop.fp_ctrl.toint connect issue_slots[7].out_uop.fp_ctrl.fromint, slots_7.io.out_uop.fp_ctrl.fromint connect issue_slots[7].out_uop.fp_ctrl.typeTagOut, slots_7.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[7].out_uop.fp_ctrl.typeTagIn, slots_7.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[7].out_uop.fp_ctrl.swap23, slots_7.io.out_uop.fp_ctrl.swap23 connect issue_slots[7].out_uop.fp_ctrl.swap12, slots_7.io.out_uop.fp_ctrl.swap12 connect issue_slots[7].out_uop.fp_ctrl.ren3, slots_7.io.out_uop.fp_ctrl.ren3 connect issue_slots[7].out_uop.fp_ctrl.ren2, slots_7.io.out_uop.fp_ctrl.ren2 connect issue_slots[7].out_uop.fp_ctrl.ren1, slots_7.io.out_uop.fp_ctrl.ren1 connect issue_slots[7].out_uop.fp_ctrl.wen, slots_7.io.out_uop.fp_ctrl.wen connect issue_slots[7].out_uop.fp_ctrl.ldst, slots_7.io.out_uop.fp_ctrl.ldst connect issue_slots[7].out_uop.op2_sel, slots_7.io.out_uop.op2_sel connect issue_slots[7].out_uop.op1_sel, slots_7.io.out_uop.op1_sel connect issue_slots[7].out_uop.imm_packed, slots_7.io.out_uop.imm_packed connect issue_slots[7].out_uop.pimm, slots_7.io.out_uop.pimm connect issue_slots[7].out_uop.imm_sel, slots_7.io.out_uop.imm_sel connect issue_slots[7].out_uop.imm_rename, slots_7.io.out_uop.imm_rename connect issue_slots[7].out_uop.taken, slots_7.io.out_uop.taken connect issue_slots[7].out_uop.pc_lob, slots_7.io.out_uop.pc_lob connect issue_slots[7].out_uop.edge_inst, slots_7.io.out_uop.edge_inst connect issue_slots[7].out_uop.ftq_idx, slots_7.io.out_uop.ftq_idx connect issue_slots[7].out_uop.is_mov, slots_7.io.out_uop.is_mov connect issue_slots[7].out_uop.is_rocc, slots_7.io.out_uop.is_rocc connect issue_slots[7].out_uop.is_sys_pc2epc, slots_7.io.out_uop.is_sys_pc2epc connect issue_slots[7].out_uop.is_eret, slots_7.io.out_uop.is_eret connect issue_slots[7].out_uop.is_amo, slots_7.io.out_uop.is_amo connect issue_slots[7].out_uop.is_sfence, slots_7.io.out_uop.is_sfence connect issue_slots[7].out_uop.is_fencei, slots_7.io.out_uop.is_fencei connect issue_slots[7].out_uop.is_fence, slots_7.io.out_uop.is_fence connect issue_slots[7].out_uop.is_sfb, slots_7.io.out_uop.is_sfb connect issue_slots[7].out_uop.br_type, slots_7.io.out_uop.br_type connect issue_slots[7].out_uop.br_tag, slots_7.io.out_uop.br_tag connect issue_slots[7].out_uop.br_mask, slots_7.io.out_uop.br_mask connect issue_slots[7].out_uop.dis_col_sel, slots_7.io.out_uop.dis_col_sel connect issue_slots[7].out_uop.iw_p3_bypass_hint, slots_7.io.out_uop.iw_p3_bypass_hint connect issue_slots[7].out_uop.iw_p2_bypass_hint, slots_7.io.out_uop.iw_p2_bypass_hint connect issue_slots[7].out_uop.iw_p1_bypass_hint, slots_7.io.out_uop.iw_p1_bypass_hint connect issue_slots[7].out_uop.iw_p2_speculative_child, slots_7.io.out_uop.iw_p2_speculative_child connect issue_slots[7].out_uop.iw_p1_speculative_child, slots_7.io.out_uop.iw_p1_speculative_child connect issue_slots[7].out_uop.iw_issued_partial_dgen, slots_7.io.out_uop.iw_issued_partial_dgen connect issue_slots[7].out_uop.iw_issued_partial_agen, slots_7.io.out_uop.iw_issued_partial_agen connect issue_slots[7].out_uop.iw_issued, slots_7.io.out_uop.iw_issued connect issue_slots[7].out_uop.fu_code[0], slots_7.io.out_uop.fu_code[0] connect issue_slots[7].out_uop.fu_code[1], slots_7.io.out_uop.fu_code[1] connect issue_slots[7].out_uop.fu_code[2], slots_7.io.out_uop.fu_code[2] connect issue_slots[7].out_uop.fu_code[3], slots_7.io.out_uop.fu_code[3] connect issue_slots[7].out_uop.fu_code[4], slots_7.io.out_uop.fu_code[4] connect issue_slots[7].out_uop.fu_code[5], slots_7.io.out_uop.fu_code[5] connect issue_slots[7].out_uop.fu_code[6], slots_7.io.out_uop.fu_code[6] connect issue_slots[7].out_uop.fu_code[7], slots_7.io.out_uop.fu_code[7] connect issue_slots[7].out_uop.fu_code[8], slots_7.io.out_uop.fu_code[8] connect issue_slots[7].out_uop.fu_code[9], slots_7.io.out_uop.fu_code[9] connect issue_slots[7].out_uop.iq_type[0], slots_7.io.out_uop.iq_type[0] connect issue_slots[7].out_uop.iq_type[1], slots_7.io.out_uop.iq_type[1] connect issue_slots[7].out_uop.iq_type[2], slots_7.io.out_uop.iq_type[2] connect issue_slots[7].out_uop.iq_type[3], slots_7.io.out_uop.iq_type[3] connect issue_slots[7].out_uop.debug_pc, slots_7.io.out_uop.debug_pc connect issue_slots[7].out_uop.is_rvc, slots_7.io.out_uop.is_rvc connect issue_slots[7].out_uop.debug_inst, slots_7.io.out_uop.debug_inst connect issue_slots[7].out_uop.inst, slots_7.io.out_uop.inst connect slots_7.io.in_uop.bits.debug_tsrc, issue_slots[7].in_uop.bits.debug_tsrc connect slots_7.io.in_uop.bits.debug_fsrc, issue_slots[7].in_uop.bits.debug_fsrc connect slots_7.io.in_uop.bits.bp_xcpt_if, issue_slots[7].in_uop.bits.bp_xcpt_if connect slots_7.io.in_uop.bits.bp_debug_if, issue_slots[7].in_uop.bits.bp_debug_if connect slots_7.io.in_uop.bits.xcpt_ma_if, issue_slots[7].in_uop.bits.xcpt_ma_if connect slots_7.io.in_uop.bits.xcpt_ae_if, issue_slots[7].in_uop.bits.xcpt_ae_if connect slots_7.io.in_uop.bits.xcpt_pf_if, issue_slots[7].in_uop.bits.xcpt_pf_if connect slots_7.io.in_uop.bits.fp_typ, issue_slots[7].in_uop.bits.fp_typ connect slots_7.io.in_uop.bits.fp_rm, issue_slots[7].in_uop.bits.fp_rm connect slots_7.io.in_uop.bits.fp_val, issue_slots[7].in_uop.bits.fp_val connect slots_7.io.in_uop.bits.fcn_op, issue_slots[7].in_uop.bits.fcn_op connect slots_7.io.in_uop.bits.fcn_dw, issue_slots[7].in_uop.bits.fcn_dw connect slots_7.io.in_uop.bits.frs3_en, issue_slots[7].in_uop.bits.frs3_en connect slots_7.io.in_uop.bits.lrs2_rtype, issue_slots[7].in_uop.bits.lrs2_rtype connect slots_7.io.in_uop.bits.lrs1_rtype, issue_slots[7].in_uop.bits.lrs1_rtype connect slots_7.io.in_uop.bits.dst_rtype, issue_slots[7].in_uop.bits.dst_rtype connect slots_7.io.in_uop.bits.lrs3, issue_slots[7].in_uop.bits.lrs3 connect slots_7.io.in_uop.bits.lrs2, issue_slots[7].in_uop.bits.lrs2 connect slots_7.io.in_uop.bits.lrs1, issue_slots[7].in_uop.bits.lrs1 connect slots_7.io.in_uop.bits.ldst, issue_slots[7].in_uop.bits.ldst connect slots_7.io.in_uop.bits.ldst_is_rs1, issue_slots[7].in_uop.bits.ldst_is_rs1 connect slots_7.io.in_uop.bits.csr_cmd, issue_slots[7].in_uop.bits.csr_cmd connect slots_7.io.in_uop.bits.flush_on_commit, issue_slots[7].in_uop.bits.flush_on_commit connect slots_7.io.in_uop.bits.is_unique, issue_slots[7].in_uop.bits.is_unique connect slots_7.io.in_uop.bits.uses_stq, issue_slots[7].in_uop.bits.uses_stq connect slots_7.io.in_uop.bits.uses_ldq, issue_slots[7].in_uop.bits.uses_ldq connect slots_7.io.in_uop.bits.mem_signed, issue_slots[7].in_uop.bits.mem_signed connect slots_7.io.in_uop.bits.mem_size, issue_slots[7].in_uop.bits.mem_size connect slots_7.io.in_uop.bits.mem_cmd, issue_slots[7].in_uop.bits.mem_cmd connect slots_7.io.in_uop.bits.exc_cause, issue_slots[7].in_uop.bits.exc_cause connect slots_7.io.in_uop.bits.exception, issue_slots[7].in_uop.bits.exception connect slots_7.io.in_uop.bits.stale_pdst, issue_slots[7].in_uop.bits.stale_pdst connect slots_7.io.in_uop.bits.ppred_busy, issue_slots[7].in_uop.bits.ppred_busy connect slots_7.io.in_uop.bits.prs3_busy, issue_slots[7].in_uop.bits.prs3_busy connect slots_7.io.in_uop.bits.prs2_busy, issue_slots[7].in_uop.bits.prs2_busy connect slots_7.io.in_uop.bits.prs1_busy, issue_slots[7].in_uop.bits.prs1_busy connect slots_7.io.in_uop.bits.ppred, issue_slots[7].in_uop.bits.ppred connect slots_7.io.in_uop.bits.prs3, issue_slots[7].in_uop.bits.prs3 connect slots_7.io.in_uop.bits.prs2, issue_slots[7].in_uop.bits.prs2 connect slots_7.io.in_uop.bits.prs1, issue_slots[7].in_uop.bits.prs1 connect slots_7.io.in_uop.bits.pdst, issue_slots[7].in_uop.bits.pdst connect slots_7.io.in_uop.bits.rxq_idx, issue_slots[7].in_uop.bits.rxq_idx connect slots_7.io.in_uop.bits.stq_idx, issue_slots[7].in_uop.bits.stq_idx connect slots_7.io.in_uop.bits.ldq_idx, issue_slots[7].in_uop.bits.ldq_idx connect slots_7.io.in_uop.bits.rob_idx, issue_slots[7].in_uop.bits.rob_idx connect slots_7.io.in_uop.bits.fp_ctrl.vec, issue_slots[7].in_uop.bits.fp_ctrl.vec connect slots_7.io.in_uop.bits.fp_ctrl.wflags, issue_slots[7].in_uop.bits.fp_ctrl.wflags connect slots_7.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[7].in_uop.bits.fp_ctrl.sqrt connect slots_7.io.in_uop.bits.fp_ctrl.div, issue_slots[7].in_uop.bits.fp_ctrl.div connect slots_7.io.in_uop.bits.fp_ctrl.fma, issue_slots[7].in_uop.bits.fp_ctrl.fma connect slots_7.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].in_uop.bits.fp_ctrl.fastpipe connect slots_7.io.in_uop.bits.fp_ctrl.toint, issue_slots[7].in_uop.bits.fp_ctrl.toint connect slots_7.io.in_uop.bits.fp_ctrl.fromint, issue_slots[7].in_uop.bits.fp_ctrl.fromint connect slots_7.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut connect slots_7.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn connect slots_7.io.in_uop.bits.fp_ctrl.swap23, issue_slots[7].in_uop.bits.fp_ctrl.swap23 connect slots_7.io.in_uop.bits.fp_ctrl.swap12, issue_slots[7].in_uop.bits.fp_ctrl.swap12 connect slots_7.io.in_uop.bits.fp_ctrl.ren3, issue_slots[7].in_uop.bits.fp_ctrl.ren3 connect slots_7.io.in_uop.bits.fp_ctrl.ren2, issue_slots[7].in_uop.bits.fp_ctrl.ren2 connect slots_7.io.in_uop.bits.fp_ctrl.ren1, issue_slots[7].in_uop.bits.fp_ctrl.ren1 connect slots_7.io.in_uop.bits.fp_ctrl.wen, issue_slots[7].in_uop.bits.fp_ctrl.wen connect slots_7.io.in_uop.bits.fp_ctrl.ldst, issue_slots[7].in_uop.bits.fp_ctrl.ldst connect slots_7.io.in_uop.bits.op2_sel, issue_slots[7].in_uop.bits.op2_sel connect slots_7.io.in_uop.bits.op1_sel, issue_slots[7].in_uop.bits.op1_sel connect slots_7.io.in_uop.bits.imm_packed, issue_slots[7].in_uop.bits.imm_packed connect slots_7.io.in_uop.bits.pimm, issue_slots[7].in_uop.bits.pimm connect slots_7.io.in_uop.bits.imm_sel, issue_slots[7].in_uop.bits.imm_sel connect slots_7.io.in_uop.bits.imm_rename, issue_slots[7].in_uop.bits.imm_rename connect slots_7.io.in_uop.bits.taken, issue_slots[7].in_uop.bits.taken connect slots_7.io.in_uop.bits.pc_lob, issue_slots[7].in_uop.bits.pc_lob connect slots_7.io.in_uop.bits.edge_inst, issue_slots[7].in_uop.bits.edge_inst connect slots_7.io.in_uop.bits.ftq_idx, issue_slots[7].in_uop.bits.ftq_idx connect slots_7.io.in_uop.bits.is_mov, issue_slots[7].in_uop.bits.is_mov connect slots_7.io.in_uop.bits.is_rocc, issue_slots[7].in_uop.bits.is_rocc connect slots_7.io.in_uop.bits.is_sys_pc2epc, issue_slots[7].in_uop.bits.is_sys_pc2epc connect slots_7.io.in_uop.bits.is_eret, issue_slots[7].in_uop.bits.is_eret connect slots_7.io.in_uop.bits.is_amo, issue_slots[7].in_uop.bits.is_amo connect slots_7.io.in_uop.bits.is_sfence, issue_slots[7].in_uop.bits.is_sfence connect slots_7.io.in_uop.bits.is_fencei, issue_slots[7].in_uop.bits.is_fencei connect slots_7.io.in_uop.bits.is_fence, issue_slots[7].in_uop.bits.is_fence connect slots_7.io.in_uop.bits.is_sfb, issue_slots[7].in_uop.bits.is_sfb connect slots_7.io.in_uop.bits.br_type, issue_slots[7].in_uop.bits.br_type connect slots_7.io.in_uop.bits.br_tag, issue_slots[7].in_uop.bits.br_tag connect slots_7.io.in_uop.bits.br_mask, issue_slots[7].in_uop.bits.br_mask connect slots_7.io.in_uop.bits.dis_col_sel, issue_slots[7].in_uop.bits.dis_col_sel connect slots_7.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[7].in_uop.bits.iw_p3_bypass_hint connect slots_7.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[7].in_uop.bits.iw_p2_bypass_hint connect slots_7.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[7].in_uop.bits.iw_p1_bypass_hint connect slots_7.io.in_uop.bits.iw_p2_speculative_child, issue_slots[7].in_uop.bits.iw_p2_speculative_child connect slots_7.io.in_uop.bits.iw_p1_speculative_child, issue_slots[7].in_uop.bits.iw_p1_speculative_child connect slots_7.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[7].in_uop.bits.iw_issued_partial_dgen connect slots_7.io.in_uop.bits.iw_issued_partial_agen, issue_slots[7].in_uop.bits.iw_issued_partial_agen connect slots_7.io.in_uop.bits.iw_issued, issue_slots[7].in_uop.bits.iw_issued connect slots_7.io.in_uop.bits.fu_code[0], issue_slots[7].in_uop.bits.fu_code[0] connect slots_7.io.in_uop.bits.fu_code[1], issue_slots[7].in_uop.bits.fu_code[1] connect slots_7.io.in_uop.bits.fu_code[2], issue_slots[7].in_uop.bits.fu_code[2] connect slots_7.io.in_uop.bits.fu_code[3], issue_slots[7].in_uop.bits.fu_code[3] connect slots_7.io.in_uop.bits.fu_code[4], issue_slots[7].in_uop.bits.fu_code[4] connect slots_7.io.in_uop.bits.fu_code[5], issue_slots[7].in_uop.bits.fu_code[5] connect slots_7.io.in_uop.bits.fu_code[6], issue_slots[7].in_uop.bits.fu_code[6] connect slots_7.io.in_uop.bits.fu_code[7], issue_slots[7].in_uop.bits.fu_code[7] connect slots_7.io.in_uop.bits.fu_code[8], issue_slots[7].in_uop.bits.fu_code[8] connect slots_7.io.in_uop.bits.fu_code[9], issue_slots[7].in_uop.bits.fu_code[9] connect slots_7.io.in_uop.bits.iq_type[0], issue_slots[7].in_uop.bits.iq_type[0] connect slots_7.io.in_uop.bits.iq_type[1], issue_slots[7].in_uop.bits.iq_type[1] connect slots_7.io.in_uop.bits.iq_type[2], issue_slots[7].in_uop.bits.iq_type[2] connect slots_7.io.in_uop.bits.iq_type[3], issue_slots[7].in_uop.bits.iq_type[3] connect slots_7.io.in_uop.bits.debug_pc, issue_slots[7].in_uop.bits.debug_pc connect slots_7.io.in_uop.bits.is_rvc, issue_slots[7].in_uop.bits.is_rvc connect slots_7.io.in_uop.bits.debug_inst, issue_slots[7].in_uop.bits.debug_inst connect slots_7.io.in_uop.bits.inst, issue_slots[7].in_uop.bits.inst connect slots_7.io.in_uop.valid, issue_slots[7].in_uop.valid connect issue_slots[7].iss_uop.debug_tsrc, slots_7.io.iss_uop.debug_tsrc connect issue_slots[7].iss_uop.debug_fsrc, slots_7.io.iss_uop.debug_fsrc connect issue_slots[7].iss_uop.bp_xcpt_if, slots_7.io.iss_uop.bp_xcpt_if connect issue_slots[7].iss_uop.bp_debug_if, slots_7.io.iss_uop.bp_debug_if connect issue_slots[7].iss_uop.xcpt_ma_if, slots_7.io.iss_uop.xcpt_ma_if connect issue_slots[7].iss_uop.xcpt_ae_if, slots_7.io.iss_uop.xcpt_ae_if connect issue_slots[7].iss_uop.xcpt_pf_if, slots_7.io.iss_uop.xcpt_pf_if connect issue_slots[7].iss_uop.fp_typ, slots_7.io.iss_uop.fp_typ connect issue_slots[7].iss_uop.fp_rm, slots_7.io.iss_uop.fp_rm connect issue_slots[7].iss_uop.fp_val, slots_7.io.iss_uop.fp_val connect issue_slots[7].iss_uop.fcn_op, slots_7.io.iss_uop.fcn_op connect issue_slots[7].iss_uop.fcn_dw, slots_7.io.iss_uop.fcn_dw connect issue_slots[7].iss_uop.frs3_en, slots_7.io.iss_uop.frs3_en connect issue_slots[7].iss_uop.lrs2_rtype, slots_7.io.iss_uop.lrs2_rtype connect issue_slots[7].iss_uop.lrs1_rtype, slots_7.io.iss_uop.lrs1_rtype connect issue_slots[7].iss_uop.dst_rtype, slots_7.io.iss_uop.dst_rtype connect issue_slots[7].iss_uop.lrs3, slots_7.io.iss_uop.lrs3 connect issue_slots[7].iss_uop.lrs2, slots_7.io.iss_uop.lrs2 connect issue_slots[7].iss_uop.lrs1, slots_7.io.iss_uop.lrs1 connect issue_slots[7].iss_uop.ldst, slots_7.io.iss_uop.ldst connect issue_slots[7].iss_uop.ldst_is_rs1, slots_7.io.iss_uop.ldst_is_rs1 connect issue_slots[7].iss_uop.csr_cmd, slots_7.io.iss_uop.csr_cmd connect issue_slots[7].iss_uop.flush_on_commit, slots_7.io.iss_uop.flush_on_commit connect issue_slots[7].iss_uop.is_unique, slots_7.io.iss_uop.is_unique connect issue_slots[7].iss_uop.uses_stq, slots_7.io.iss_uop.uses_stq connect issue_slots[7].iss_uop.uses_ldq, slots_7.io.iss_uop.uses_ldq connect issue_slots[7].iss_uop.mem_signed, slots_7.io.iss_uop.mem_signed connect issue_slots[7].iss_uop.mem_size, slots_7.io.iss_uop.mem_size connect issue_slots[7].iss_uop.mem_cmd, slots_7.io.iss_uop.mem_cmd connect issue_slots[7].iss_uop.exc_cause, slots_7.io.iss_uop.exc_cause connect issue_slots[7].iss_uop.exception, slots_7.io.iss_uop.exception connect issue_slots[7].iss_uop.stale_pdst, slots_7.io.iss_uop.stale_pdst connect issue_slots[7].iss_uop.ppred_busy, slots_7.io.iss_uop.ppred_busy connect issue_slots[7].iss_uop.prs3_busy, slots_7.io.iss_uop.prs3_busy connect issue_slots[7].iss_uop.prs2_busy, slots_7.io.iss_uop.prs2_busy connect issue_slots[7].iss_uop.prs1_busy, slots_7.io.iss_uop.prs1_busy connect issue_slots[7].iss_uop.ppred, slots_7.io.iss_uop.ppred connect issue_slots[7].iss_uop.prs3, slots_7.io.iss_uop.prs3 connect issue_slots[7].iss_uop.prs2, slots_7.io.iss_uop.prs2 connect issue_slots[7].iss_uop.prs1, slots_7.io.iss_uop.prs1 connect issue_slots[7].iss_uop.pdst, slots_7.io.iss_uop.pdst connect issue_slots[7].iss_uop.rxq_idx, slots_7.io.iss_uop.rxq_idx connect issue_slots[7].iss_uop.stq_idx, slots_7.io.iss_uop.stq_idx connect issue_slots[7].iss_uop.ldq_idx, slots_7.io.iss_uop.ldq_idx connect issue_slots[7].iss_uop.rob_idx, slots_7.io.iss_uop.rob_idx connect issue_slots[7].iss_uop.fp_ctrl.vec, slots_7.io.iss_uop.fp_ctrl.vec connect issue_slots[7].iss_uop.fp_ctrl.wflags, slots_7.io.iss_uop.fp_ctrl.wflags connect issue_slots[7].iss_uop.fp_ctrl.sqrt, slots_7.io.iss_uop.fp_ctrl.sqrt connect issue_slots[7].iss_uop.fp_ctrl.div, slots_7.io.iss_uop.fp_ctrl.div connect issue_slots[7].iss_uop.fp_ctrl.fma, slots_7.io.iss_uop.fp_ctrl.fma connect issue_slots[7].iss_uop.fp_ctrl.fastpipe, slots_7.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[7].iss_uop.fp_ctrl.toint, slots_7.io.iss_uop.fp_ctrl.toint connect issue_slots[7].iss_uop.fp_ctrl.fromint, slots_7.io.iss_uop.fp_ctrl.fromint connect issue_slots[7].iss_uop.fp_ctrl.typeTagOut, slots_7.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[7].iss_uop.fp_ctrl.typeTagIn, slots_7.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[7].iss_uop.fp_ctrl.swap23, slots_7.io.iss_uop.fp_ctrl.swap23 connect issue_slots[7].iss_uop.fp_ctrl.swap12, slots_7.io.iss_uop.fp_ctrl.swap12 connect issue_slots[7].iss_uop.fp_ctrl.ren3, slots_7.io.iss_uop.fp_ctrl.ren3 connect issue_slots[7].iss_uop.fp_ctrl.ren2, slots_7.io.iss_uop.fp_ctrl.ren2 connect issue_slots[7].iss_uop.fp_ctrl.ren1, slots_7.io.iss_uop.fp_ctrl.ren1 connect issue_slots[7].iss_uop.fp_ctrl.wen, slots_7.io.iss_uop.fp_ctrl.wen connect issue_slots[7].iss_uop.fp_ctrl.ldst, slots_7.io.iss_uop.fp_ctrl.ldst connect issue_slots[7].iss_uop.op2_sel, slots_7.io.iss_uop.op2_sel connect issue_slots[7].iss_uop.op1_sel, slots_7.io.iss_uop.op1_sel connect issue_slots[7].iss_uop.imm_packed, slots_7.io.iss_uop.imm_packed connect issue_slots[7].iss_uop.pimm, slots_7.io.iss_uop.pimm connect issue_slots[7].iss_uop.imm_sel, slots_7.io.iss_uop.imm_sel connect issue_slots[7].iss_uop.imm_rename, slots_7.io.iss_uop.imm_rename connect issue_slots[7].iss_uop.taken, slots_7.io.iss_uop.taken connect issue_slots[7].iss_uop.pc_lob, slots_7.io.iss_uop.pc_lob connect issue_slots[7].iss_uop.edge_inst, slots_7.io.iss_uop.edge_inst connect issue_slots[7].iss_uop.ftq_idx, slots_7.io.iss_uop.ftq_idx connect issue_slots[7].iss_uop.is_mov, slots_7.io.iss_uop.is_mov connect issue_slots[7].iss_uop.is_rocc, slots_7.io.iss_uop.is_rocc connect issue_slots[7].iss_uop.is_sys_pc2epc, slots_7.io.iss_uop.is_sys_pc2epc connect issue_slots[7].iss_uop.is_eret, slots_7.io.iss_uop.is_eret connect issue_slots[7].iss_uop.is_amo, slots_7.io.iss_uop.is_amo connect issue_slots[7].iss_uop.is_sfence, slots_7.io.iss_uop.is_sfence connect issue_slots[7].iss_uop.is_fencei, slots_7.io.iss_uop.is_fencei connect issue_slots[7].iss_uop.is_fence, slots_7.io.iss_uop.is_fence connect issue_slots[7].iss_uop.is_sfb, slots_7.io.iss_uop.is_sfb connect issue_slots[7].iss_uop.br_type, slots_7.io.iss_uop.br_type connect issue_slots[7].iss_uop.br_tag, slots_7.io.iss_uop.br_tag connect issue_slots[7].iss_uop.br_mask, slots_7.io.iss_uop.br_mask connect issue_slots[7].iss_uop.dis_col_sel, slots_7.io.iss_uop.dis_col_sel connect issue_slots[7].iss_uop.iw_p3_bypass_hint, slots_7.io.iss_uop.iw_p3_bypass_hint connect issue_slots[7].iss_uop.iw_p2_bypass_hint, slots_7.io.iss_uop.iw_p2_bypass_hint connect issue_slots[7].iss_uop.iw_p1_bypass_hint, slots_7.io.iss_uop.iw_p1_bypass_hint connect issue_slots[7].iss_uop.iw_p2_speculative_child, slots_7.io.iss_uop.iw_p2_speculative_child connect issue_slots[7].iss_uop.iw_p1_speculative_child, slots_7.io.iss_uop.iw_p1_speculative_child connect issue_slots[7].iss_uop.iw_issued_partial_dgen, slots_7.io.iss_uop.iw_issued_partial_dgen connect issue_slots[7].iss_uop.iw_issued_partial_agen, slots_7.io.iss_uop.iw_issued_partial_agen connect issue_slots[7].iss_uop.iw_issued, slots_7.io.iss_uop.iw_issued connect issue_slots[7].iss_uop.fu_code[0], slots_7.io.iss_uop.fu_code[0] connect issue_slots[7].iss_uop.fu_code[1], slots_7.io.iss_uop.fu_code[1] connect issue_slots[7].iss_uop.fu_code[2], slots_7.io.iss_uop.fu_code[2] connect issue_slots[7].iss_uop.fu_code[3], slots_7.io.iss_uop.fu_code[3] connect issue_slots[7].iss_uop.fu_code[4], slots_7.io.iss_uop.fu_code[4] connect issue_slots[7].iss_uop.fu_code[5], slots_7.io.iss_uop.fu_code[5] connect issue_slots[7].iss_uop.fu_code[6], slots_7.io.iss_uop.fu_code[6] connect issue_slots[7].iss_uop.fu_code[7], slots_7.io.iss_uop.fu_code[7] connect issue_slots[7].iss_uop.fu_code[8], slots_7.io.iss_uop.fu_code[8] connect issue_slots[7].iss_uop.fu_code[9], slots_7.io.iss_uop.fu_code[9] connect issue_slots[7].iss_uop.iq_type[0], slots_7.io.iss_uop.iq_type[0] connect issue_slots[7].iss_uop.iq_type[1], slots_7.io.iss_uop.iq_type[1] connect issue_slots[7].iss_uop.iq_type[2], slots_7.io.iss_uop.iq_type[2] connect issue_slots[7].iss_uop.iq_type[3], slots_7.io.iss_uop.iq_type[3] connect issue_slots[7].iss_uop.debug_pc, slots_7.io.iss_uop.debug_pc connect issue_slots[7].iss_uop.is_rvc, slots_7.io.iss_uop.is_rvc connect issue_slots[7].iss_uop.debug_inst, slots_7.io.iss_uop.debug_inst connect issue_slots[7].iss_uop.inst, slots_7.io.iss_uop.inst connect slots_7.io.grant, issue_slots[7].grant connect issue_slots[7].request, slots_7.io.request connect issue_slots[7].will_be_valid, slots_7.io.will_be_valid connect issue_slots[7].valid, slots_7.io.valid connect slots_8.io.child_rebusys, issue_slots[8].child_rebusys connect slots_8.io.pred_wakeup_port.bits, issue_slots[8].pred_wakeup_port.bits connect slots_8.io.pred_wakeup_port.valid, issue_slots[8].pred_wakeup_port.valid connect slots_8.io.wakeup_ports[0].bits.rebusy, issue_slots[8].wakeup_ports[0].bits.rebusy connect slots_8.io.wakeup_ports[0].bits.speculative_mask, issue_slots[8].wakeup_ports[0].bits.speculative_mask connect slots_8.io.wakeup_ports[0].bits.bypassable, issue_slots[8].wakeup_ports[0].bits.bypassable connect slots_8.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[0].bits.uop.debug_tsrc connect slots_8.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[0].bits.uop.debug_fsrc connect slots_8.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_8.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[0].bits.uop.bp_debug_if connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_8.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[8].wakeup_ports[0].bits.uop.fp_typ connect slots_8.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[8].wakeup_ports[0].bits.uop.fp_rm connect slots_8.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[8].wakeup_ports[0].bits.uop.fp_val connect slots_8.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[8].wakeup_ports[0].bits.uop.fcn_op connect slots_8.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[0].bits.uop.fcn_dw connect slots_8.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[8].wakeup_ports[0].bits.uop.frs3_en connect slots_8.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_8.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_8.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[0].bits.uop.dst_rtype connect slots_8.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[8].wakeup_ports[0].bits.uop.lrs3 connect slots_8.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[8].wakeup_ports[0].bits.uop.lrs2 connect slots_8.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[8].wakeup_ports[0].bits.uop.lrs1 connect slots_8.io.wakeup_ports[0].bits.uop.ldst, issue_slots[8].wakeup_ports[0].bits.uop.ldst connect slots_8.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_8.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[0].bits.uop.csr_cmd connect slots_8.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[0].bits.uop.flush_on_commit connect slots_8.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[8].wakeup_ports[0].bits.uop.is_unique connect slots_8.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[8].wakeup_ports[0].bits.uop.uses_stq connect slots_8.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[0].bits.uop.uses_ldq connect slots_8.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[8].wakeup_ports[0].bits.uop.mem_signed connect slots_8.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[8].wakeup_ports[0].bits.uop.mem_size connect slots_8.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[0].bits.uop.mem_cmd connect slots_8.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[8].wakeup_ports[0].bits.uop.exc_cause connect slots_8.io.wakeup_ports[0].bits.uop.exception, issue_slots[8].wakeup_ports[0].bits.uop.exception connect slots_8.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[0].bits.uop.stale_pdst connect slots_8.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[0].bits.uop.ppred_busy connect slots_8.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs3_busy connect slots_8.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs2_busy connect slots_8.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs1_busy connect slots_8.io.wakeup_ports[0].bits.uop.ppred, issue_slots[8].wakeup_ports[0].bits.uop.ppred connect slots_8.io.wakeup_ports[0].bits.uop.prs3, issue_slots[8].wakeup_ports[0].bits.uop.prs3 connect slots_8.io.wakeup_ports[0].bits.uop.prs2, issue_slots[8].wakeup_ports[0].bits.uop.prs2 connect slots_8.io.wakeup_ports[0].bits.uop.prs1, issue_slots[8].wakeup_ports[0].bits.uop.prs1 connect slots_8.io.wakeup_ports[0].bits.uop.pdst, issue_slots[8].wakeup_ports[0].bits.uop.pdst connect slots_8.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[0].bits.uop.rxq_idx connect slots_8.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[8].wakeup_ports[0].bits.uop.stq_idx connect slots_8.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[0].bits.uop.ldq_idx connect slots_8.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[8].wakeup_ports[0].bits.uop.rob_idx connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_8.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[8].wakeup_ports[0].bits.uop.op2_sel connect slots_8.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[8].wakeup_ports[0].bits.uop.op1_sel connect slots_8.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[8].wakeup_ports[0].bits.uop.imm_packed connect slots_8.io.wakeup_ports[0].bits.uop.pimm, issue_slots[8].wakeup_ports[0].bits.uop.pimm connect slots_8.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[8].wakeup_ports[0].bits.uop.imm_sel connect slots_8.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[8].wakeup_ports[0].bits.uop.imm_rename connect slots_8.io.wakeup_ports[0].bits.uop.taken, issue_slots[8].wakeup_ports[0].bits.uop.taken connect slots_8.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[8].wakeup_ports[0].bits.uop.pc_lob connect slots_8.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[8].wakeup_ports[0].bits.uop.edge_inst connect slots_8.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[0].bits.uop.ftq_idx connect slots_8.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[8].wakeup_ports[0].bits.uop.is_mov connect slots_8.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[8].wakeup_ports[0].bits.uop.is_rocc connect slots_8.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_8.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[8].wakeup_ports[0].bits.uop.is_eret connect slots_8.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[8].wakeup_ports[0].bits.uop.is_amo connect slots_8.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[8].wakeup_ports[0].bits.uop.is_sfence connect slots_8.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[8].wakeup_ports[0].bits.uop.is_fencei connect slots_8.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[8].wakeup_ports[0].bits.uop.is_fence connect slots_8.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[8].wakeup_ports[0].bits.uop.is_sfb connect slots_8.io.wakeup_ports[0].bits.uop.br_type, issue_slots[8].wakeup_ports[0].bits.uop.br_type connect slots_8.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[8].wakeup_ports[0].bits.uop.br_tag connect slots_8.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[8].wakeup_ports[0].bits.uop.br_mask connect slots_8.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[0].bits.uop.dis_col_sel connect slots_8.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_8.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_8.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_8.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_8.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[0] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[1] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[2] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[3] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[4] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[5] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[6] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[7] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[8] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[9] connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[0] connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[1] connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[2] connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[3] connect slots_8.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[8].wakeup_ports[0].bits.uop.debug_pc connect slots_8.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[8].wakeup_ports[0].bits.uop.is_rvc connect slots_8.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[8].wakeup_ports[0].bits.uop.debug_inst connect slots_8.io.wakeup_ports[0].bits.uop.inst, issue_slots[8].wakeup_ports[0].bits.uop.inst connect slots_8.io.wakeup_ports[0].valid, issue_slots[8].wakeup_ports[0].valid connect slots_8.io.wakeup_ports[1].bits.rebusy, issue_slots[8].wakeup_ports[1].bits.rebusy connect slots_8.io.wakeup_ports[1].bits.speculative_mask, issue_slots[8].wakeup_ports[1].bits.speculative_mask connect slots_8.io.wakeup_ports[1].bits.bypassable, issue_slots[8].wakeup_ports[1].bits.bypassable connect slots_8.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[1].bits.uop.debug_tsrc connect slots_8.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[1].bits.uop.debug_fsrc connect slots_8.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_8.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[1].bits.uop.bp_debug_if connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_8.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[8].wakeup_ports[1].bits.uop.fp_typ connect slots_8.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[8].wakeup_ports[1].bits.uop.fp_rm connect slots_8.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[8].wakeup_ports[1].bits.uop.fp_val connect slots_8.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[8].wakeup_ports[1].bits.uop.fcn_op connect slots_8.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[1].bits.uop.fcn_dw connect slots_8.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[8].wakeup_ports[1].bits.uop.frs3_en connect slots_8.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_8.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_8.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[1].bits.uop.dst_rtype connect slots_8.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[8].wakeup_ports[1].bits.uop.lrs3 connect slots_8.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[8].wakeup_ports[1].bits.uop.lrs2 connect slots_8.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[8].wakeup_ports[1].bits.uop.lrs1 connect slots_8.io.wakeup_ports[1].bits.uop.ldst, issue_slots[8].wakeup_ports[1].bits.uop.ldst connect slots_8.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_8.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[1].bits.uop.csr_cmd connect slots_8.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[1].bits.uop.flush_on_commit connect slots_8.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[8].wakeup_ports[1].bits.uop.is_unique connect slots_8.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[8].wakeup_ports[1].bits.uop.uses_stq connect slots_8.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[1].bits.uop.uses_ldq connect slots_8.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[8].wakeup_ports[1].bits.uop.mem_signed connect slots_8.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[8].wakeup_ports[1].bits.uop.mem_size connect slots_8.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[1].bits.uop.mem_cmd connect slots_8.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[8].wakeup_ports[1].bits.uop.exc_cause connect slots_8.io.wakeup_ports[1].bits.uop.exception, issue_slots[8].wakeup_ports[1].bits.uop.exception connect slots_8.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[1].bits.uop.stale_pdst connect slots_8.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[1].bits.uop.ppred_busy connect slots_8.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs3_busy connect slots_8.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs2_busy connect slots_8.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs1_busy connect slots_8.io.wakeup_ports[1].bits.uop.ppred, issue_slots[8].wakeup_ports[1].bits.uop.ppred connect slots_8.io.wakeup_ports[1].bits.uop.prs3, issue_slots[8].wakeup_ports[1].bits.uop.prs3 connect slots_8.io.wakeup_ports[1].bits.uop.prs2, issue_slots[8].wakeup_ports[1].bits.uop.prs2 connect slots_8.io.wakeup_ports[1].bits.uop.prs1, issue_slots[8].wakeup_ports[1].bits.uop.prs1 connect slots_8.io.wakeup_ports[1].bits.uop.pdst, issue_slots[8].wakeup_ports[1].bits.uop.pdst connect slots_8.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[1].bits.uop.rxq_idx connect slots_8.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[8].wakeup_ports[1].bits.uop.stq_idx connect slots_8.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[1].bits.uop.ldq_idx connect slots_8.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[8].wakeup_ports[1].bits.uop.rob_idx connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_8.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[8].wakeup_ports[1].bits.uop.op2_sel connect slots_8.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[8].wakeup_ports[1].bits.uop.op1_sel connect slots_8.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[8].wakeup_ports[1].bits.uop.imm_packed connect slots_8.io.wakeup_ports[1].bits.uop.pimm, issue_slots[8].wakeup_ports[1].bits.uop.pimm connect slots_8.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[8].wakeup_ports[1].bits.uop.imm_sel connect slots_8.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[8].wakeup_ports[1].bits.uop.imm_rename connect slots_8.io.wakeup_ports[1].bits.uop.taken, issue_slots[8].wakeup_ports[1].bits.uop.taken connect slots_8.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[8].wakeup_ports[1].bits.uop.pc_lob connect slots_8.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[8].wakeup_ports[1].bits.uop.edge_inst connect slots_8.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[1].bits.uop.ftq_idx connect slots_8.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[8].wakeup_ports[1].bits.uop.is_mov connect slots_8.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[8].wakeup_ports[1].bits.uop.is_rocc connect slots_8.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_8.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[8].wakeup_ports[1].bits.uop.is_eret connect slots_8.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[8].wakeup_ports[1].bits.uop.is_amo connect slots_8.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[8].wakeup_ports[1].bits.uop.is_sfence connect slots_8.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[8].wakeup_ports[1].bits.uop.is_fencei connect slots_8.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[8].wakeup_ports[1].bits.uop.is_fence connect slots_8.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[8].wakeup_ports[1].bits.uop.is_sfb connect slots_8.io.wakeup_ports[1].bits.uop.br_type, issue_slots[8].wakeup_ports[1].bits.uop.br_type connect slots_8.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[8].wakeup_ports[1].bits.uop.br_tag connect slots_8.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[8].wakeup_ports[1].bits.uop.br_mask connect slots_8.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[1].bits.uop.dis_col_sel connect slots_8.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_8.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_8.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_8.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_8.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[0] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[1] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[2] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[3] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[4] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[5] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[6] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[7] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[8] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[9] connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[0] connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[1] connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[2] connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[3] connect slots_8.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[8].wakeup_ports[1].bits.uop.debug_pc connect slots_8.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[8].wakeup_ports[1].bits.uop.is_rvc connect slots_8.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[8].wakeup_ports[1].bits.uop.debug_inst connect slots_8.io.wakeup_ports[1].bits.uop.inst, issue_slots[8].wakeup_ports[1].bits.uop.inst connect slots_8.io.wakeup_ports[1].valid, issue_slots[8].wakeup_ports[1].valid connect slots_8.io.wakeup_ports[2].bits.rebusy, issue_slots[8].wakeup_ports[2].bits.rebusy connect slots_8.io.wakeup_ports[2].bits.speculative_mask, issue_slots[8].wakeup_ports[2].bits.speculative_mask connect slots_8.io.wakeup_ports[2].bits.bypassable, issue_slots[8].wakeup_ports[2].bits.bypassable connect slots_8.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[2].bits.uop.debug_tsrc connect slots_8.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[2].bits.uop.debug_fsrc connect slots_8.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_8.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[2].bits.uop.bp_debug_if connect slots_8.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_8.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_8.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_8.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[8].wakeup_ports[2].bits.uop.fp_typ connect slots_8.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[8].wakeup_ports[2].bits.uop.fp_rm connect slots_8.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[8].wakeup_ports[2].bits.uop.fp_val connect slots_8.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[8].wakeup_ports[2].bits.uop.fcn_op connect slots_8.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[2].bits.uop.fcn_dw connect slots_8.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[8].wakeup_ports[2].bits.uop.frs3_en connect slots_8.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_8.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_8.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[2].bits.uop.dst_rtype connect slots_8.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[8].wakeup_ports[2].bits.uop.lrs3 connect slots_8.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[8].wakeup_ports[2].bits.uop.lrs2 connect slots_8.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[8].wakeup_ports[2].bits.uop.lrs1 connect slots_8.io.wakeup_ports[2].bits.uop.ldst, issue_slots[8].wakeup_ports[2].bits.uop.ldst connect slots_8.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_8.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[2].bits.uop.csr_cmd connect slots_8.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[2].bits.uop.flush_on_commit connect slots_8.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[8].wakeup_ports[2].bits.uop.is_unique connect slots_8.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[8].wakeup_ports[2].bits.uop.uses_stq connect slots_8.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[2].bits.uop.uses_ldq connect slots_8.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[8].wakeup_ports[2].bits.uop.mem_signed connect slots_8.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[8].wakeup_ports[2].bits.uop.mem_size connect slots_8.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[2].bits.uop.mem_cmd connect slots_8.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[8].wakeup_ports[2].bits.uop.exc_cause connect slots_8.io.wakeup_ports[2].bits.uop.exception, issue_slots[8].wakeup_ports[2].bits.uop.exception connect slots_8.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[2].bits.uop.stale_pdst connect slots_8.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[2].bits.uop.ppred_busy connect slots_8.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[2].bits.uop.prs3_busy connect slots_8.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[2].bits.uop.prs2_busy connect slots_8.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[2].bits.uop.prs1_busy connect slots_8.io.wakeup_ports[2].bits.uop.ppred, issue_slots[8].wakeup_ports[2].bits.uop.ppred connect slots_8.io.wakeup_ports[2].bits.uop.prs3, issue_slots[8].wakeup_ports[2].bits.uop.prs3 connect slots_8.io.wakeup_ports[2].bits.uop.prs2, issue_slots[8].wakeup_ports[2].bits.uop.prs2 connect slots_8.io.wakeup_ports[2].bits.uop.prs1, issue_slots[8].wakeup_ports[2].bits.uop.prs1 connect slots_8.io.wakeup_ports[2].bits.uop.pdst, issue_slots[8].wakeup_ports[2].bits.uop.pdst connect slots_8.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[2].bits.uop.rxq_idx connect slots_8.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[8].wakeup_ports[2].bits.uop.stq_idx connect slots_8.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[2].bits.uop.ldq_idx connect slots_8.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[8].wakeup_ports[2].bits.uop.rob_idx connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_8.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[8].wakeup_ports[2].bits.uop.op2_sel connect slots_8.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[8].wakeup_ports[2].bits.uop.op1_sel connect slots_8.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[8].wakeup_ports[2].bits.uop.imm_packed connect slots_8.io.wakeup_ports[2].bits.uop.pimm, issue_slots[8].wakeup_ports[2].bits.uop.pimm connect slots_8.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[8].wakeup_ports[2].bits.uop.imm_sel connect slots_8.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[8].wakeup_ports[2].bits.uop.imm_rename connect slots_8.io.wakeup_ports[2].bits.uop.taken, issue_slots[8].wakeup_ports[2].bits.uop.taken connect slots_8.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[8].wakeup_ports[2].bits.uop.pc_lob connect slots_8.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[8].wakeup_ports[2].bits.uop.edge_inst connect slots_8.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[2].bits.uop.ftq_idx connect slots_8.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[8].wakeup_ports[2].bits.uop.is_mov connect slots_8.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[8].wakeup_ports[2].bits.uop.is_rocc connect slots_8.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_8.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[8].wakeup_ports[2].bits.uop.is_eret connect slots_8.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[8].wakeup_ports[2].bits.uop.is_amo connect slots_8.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[8].wakeup_ports[2].bits.uop.is_sfence connect slots_8.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[8].wakeup_ports[2].bits.uop.is_fencei connect slots_8.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[8].wakeup_ports[2].bits.uop.is_fence connect slots_8.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[8].wakeup_ports[2].bits.uop.is_sfb connect slots_8.io.wakeup_ports[2].bits.uop.br_type, issue_slots[8].wakeup_ports[2].bits.uop.br_type connect slots_8.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[8].wakeup_ports[2].bits.uop.br_tag connect slots_8.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[8].wakeup_ports[2].bits.uop.br_mask connect slots_8.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[2].bits.uop.dis_col_sel connect slots_8.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_8.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_8.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_8.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_8.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_8.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_8.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_8.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[8].wakeup_ports[2].bits.uop.iw_issued connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[0] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[1] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[2] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[3] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[4] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[5] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[6] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[7] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[8] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[9] connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[0] connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[1] connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[2] connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[3] connect slots_8.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[8].wakeup_ports[2].bits.uop.debug_pc connect slots_8.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[8].wakeup_ports[2].bits.uop.is_rvc connect slots_8.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[8].wakeup_ports[2].bits.uop.debug_inst connect slots_8.io.wakeup_ports[2].bits.uop.inst, issue_slots[8].wakeup_ports[2].bits.uop.inst connect slots_8.io.wakeup_ports[2].valid, issue_slots[8].wakeup_ports[2].valid connect slots_8.io.wakeup_ports[3].bits.rebusy, issue_slots[8].wakeup_ports[3].bits.rebusy connect slots_8.io.wakeup_ports[3].bits.speculative_mask, issue_slots[8].wakeup_ports[3].bits.speculative_mask connect slots_8.io.wakeup_ports[3].bits.bypassable, issue_slots[8].wakeup_ports[3].bits.bypassable connect slots_8.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[3].bits.uop.debug_tsrc connect slots_8.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[3].bits.uop.debug_fsrc connect slots_8.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_8.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[3].bits.uop.bp_debug_if connect slots_8.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_8.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_8.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_8.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[8].wakeup_ports[3].bits.uop.fp_typ connect slots_8.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[8].wakeup_ports[3].bits.uop.fp_rm connect slots_8.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[8].wakeup_ports[3].bits.uop.fp_val connect slots_8.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[8].wakeup_ports[3].bits.uop.fcn_op connect slots_8.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[3].bits.uop.fcn_dw connect slots_8.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[8].wakeup_ports[3].bits.uop.frs3_en connect slots_8.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_8.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_8.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[3].bits.uop.dst_rtype connect slots_8.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[8].wakeup_ports[3].bits.uop.lrs3 connect slots_8.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[8].wakeup_ports[3].bits.uop.lrs2 connect slots_8.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[8].wakeup_ports[3].bits.uop.lrs1 connect slots_8.io.wakeup_ports[3].bits.uop.ldst, issue_slots[8].wakeup_ports[3].bits.uop.ldst connect slots_8.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_8.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[3].bits.uop.csr_cmd connect slots_8.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[3].bits.uop.flush_on_commit connect slots_8.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[8].wakeup_ports[3].bits.uop.is_unique connect slots_8.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[8].wakeup_ports[3].bits.uop.uses_stq connect slots_8.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[3].bits.uop.uses_ldq connect slots_8.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[8].wakeup_ports[3].bits.uop.mem_signed connect slots_8.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[8].wakeup_ports[3].bits.uop.mem_size connect slots_8.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[3].bits.uop.mem_cmd connect slots_8.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[8].wakeup_ports[3].bits.uop.exc_cause connect slots_8.io.wakeup_ports[3].bits.uop.exception, issue_slots[8].wakeup_ports[3].bits.uop.exception connect slots_8.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[3].bits.uop.stale_pdst connect slots_8.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[3].bits.uop.ppred_busy connect slots_8.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[3].bits.uop.prs3_busy connect slots_8.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[3].bits.uop.prs2_busy connect slots_8.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[3].bits.uop.prs1_busy connect slots_8.io.wakeup_ports[3].bits.uop.ppred, issue_slots[8].wakeup_ports[3].bits.uop.ppred connect slots_8.io.wakeup_ports[3].bits.uop.prs3, issue_slots[8].wakeup_ports[3].bits.uop.prs3 connect slots_8.io.wakeup_ports[3].bits.uop.prs2, issue_slots[8].wakeup_ports[3].bits.uop.prs2 connect slots_8.io.wakeup_ports[3].bits.uop.prs1, issue_slots[8].wakeup_ports[3].bits.uop.prs1 connect slots_8.io.wakeup_ports[3].bits.uop.pdst, issue_slots[8].wakeup_ports[3].bits.uop.pdst connect slots_8.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[3].bits.uop.rxq_idx connect slots_8.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[8].wakeup_ports[3].bits.uop.stq_idx connect slots_8.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[3].bits.uop.ldq_idx connect slots_8.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[8].wakeup_ports[3].bits.uop.rob_idx connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_8.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[8].wakeup_ports[3].bits.uop.op2_sel connect slots_8.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[8].wakeup_ports[3].bits.uop.op1_sel connect slots_8.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[8].wakeup_ports[3].bits.uop.imm_packed connect slots_8.io.wakeup_ports[3].bits.uop.pimm, issue_slots[8].wakeup_ports[3].bits.uop.pimm connect slots_8.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[8].wakeup_ports[3].bits.uop.imm_sel connect slots_8.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[8].wakeup_ports[3].bits.uop.imm_rename connect slots_8.io.wakeup_ports[3].bits.uop.taken, issue_slots[8].wakeup_ports[3].bits.uop.taken connect slots_8.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[8].wakeup_ports[3].bits.uop.pc_lob connect slots_8.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[8].wakeup_ports[3].bits.uop.edge_inst connect slots_8.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[3].bits.uop.ftq_idx connect slots_8.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[8].wakeup_ports[3].bits.uop.is_mov connect slots_8.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[8].wakeup_ports[3].bits.uop.is_rocc connect slots_8.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_8.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[8].wakeup_ports[3].bits.uop.is_eret connect slots_8.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[8].wakeup_ports[3].bits.uop.is_amo connect slots_8.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[8].wakeup_ports[3].bits.uop.is_sfence connect slots_8.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[8].wakeup_ports[3].bits.uop.is_fencei connect slots_8.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[8].wakeup_ports[3].bits.uop.is_fence connect slots_8.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[8].wakeup_ports[3].bits.uop.is_sfb connect slots_8.io.wakeup_ports[3].bits.uop.br_type, issue_slots[8].wakeup_ports[3].bits.uop.br_type connect slots_8.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[8].wakeup_ports[3].bits.uop.br_tag connect slots_8.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[8].wakeup_ports[3].bits.uop.br_mask connect slots_8.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[3].bits.uop.dis_col_sel connect slots_8.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_8.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_8.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_8.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_8.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_8.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_8.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_8.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[8].wakeup_ports[3].bits.uop.iw_issued connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[0] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[1] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[2] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[3] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[4] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[5] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[6] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[7] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[8] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[9] connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[0] connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[1] connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[2] connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[3] connect slots_8.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[8].wakeup_ports[3].bits.uop.debug_pc connect slots_8.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[8].wakeup_ports[3].bits.uop.is_rvc connect slots_8.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[8].wakeup_ports[3].bits.uop.debug_inst connect slots_8.io.wakeup_ports[3].bits.uop.inst, issue_slots[8].wakeup_ports[3].bits.uop.inst connect slots_8.io.wakeup_ports[3].valid, issue_slots[8].wakeup_ports[3].valid connect slots_8.io.wakeup_ports[4].bits.rebusy, issue_slots[8].wakeup_ports[4].bits.rebusy connect slots_8.io.wakeup_ports[4].bits.speculative_mask, issue_slots[8].wakeup_ports[4].bits.speculative_mask connect slots_8.io.wakeup_ports[4].bits.bypassable, issue_slots[8].wakeup_ports[4].bits.bypassable connect slots_8.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[4].bits.uop.debug_tsrc connect slots_8.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[4].bits.uop.debug_fsrc connect slots_8.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_8.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[4].bits.uop.bp_debug_if connect slots_8.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_8.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_8.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_8.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[8].wakeup_ports[4].bits.uop.fp_typ connect slots_8.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[8].wakeup_ports[4].bits.uop.fp_rm connect slots_8.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[8].wakeup_ports[4].bits.uop.fp_val connect slots_8.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[8].wakeup_ports[4].bits.uop.fcn_op connect slots_8.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[4].bits.uop.fcn_dw connect slots_8.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[8].wakeup_ports[4].bits.uop.frs3_en connect slots_8.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_8.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_8.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[4].bits.uop.dst_rtype connect slots_8.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[8].wakeup_ports[4].bits.uop.lrs3 connect slots_8.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[8].wakeup_ports[4].bits.uop.lrs2 connect slots_8.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[8].wakeup_ports[4].bits.uop.lrs1 connect slots_8.io.wakeup_ports[4].bits.uop.ldst, issue_slots[8].wakeup_ports[4].bits.uop.ldst connect slots_8.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_8.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[4].bits.uop.csr_cmd connect slots_8.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[4].bits.uop.flush_on_commit connect slots_8.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[8].wakeup_ports[4].bits.uop.is_unique connect slots_8.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[8].wakeup_ports[4].bits.uop.uses_stq connect slots_8.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[4].bits.uop.uses_ldq connect slots_8.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[8].wakeup_ports[4].bits.uop.mem_signed connect slots_8.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[8].wakeup_ports[4].bits.uop.mem_size connect slots_8.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[4].bits.uop.mem_cmd connect slots_8.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[8].wakeup_ports[4].bits.uop.exc_cause connect slots_8.io.wakeup_ports[4].bits.uop.exception, issue_slots[8].wakeup_ports[4].bits.uop.exception connect slots_8.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[4].bits.uop.stale_pdst connect slots_8.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[4].bits.uop.ppred_busy connect slots_8.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[4].bits.uop.prs3_busy connect slots_8.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[4].bits.uop.prs2_busy connect slots_8.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[4].bits.uop.prs1_busy connect slots_8.io.wakeup_ports[4].bits.uop.ppred, issue_slots[8].wakeup_ports[4].bits.uop.ppred connect slots_8.io.wakeup_ports[4].bits.uop.prs3, issue_slots[8].wakeup_ports[4].bits.uop.prs3 connect slots_8.io.wakeup_ports[4].bits.uop.prs2, issue_slots[8].wakeup_ports[4].bits.uop.prs2 connect slots_8.io.wakeup_ports[4].bits.uop.prs1, issue_slots[8].wakeup_ports[4].bits.uop.prs1 connect slots_8.io.wakeup_ports[4].bits.uop.pdst, issue_slots[8].wakeup_ports[4].bits.uop.pdst connect slots_8.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[4].bits.uop.rxq_idx connect slots_8.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[8].wakeup_ports[4].bits.uop.stq_idx connect slots_8.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[4].bits.uop.ldq_idx connect slots_8.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[8].wakeup_ports[4].bits.uop.rob_idx connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_8.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[8].wakeup_ports[4].bits.uop.op2_sel connect slots_8.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[8].wakeup_ports[4].bits.uop.op1_sel connect slots_8.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[8].wakeup_ports[4].bits.uop.imm_packed connect slots_8.io.wakeup_ports[4].bits.uop.pimm, issue_slots[8].wakeup_ports[4].bits.uop.pimm connect slots_8.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[8].wakeup_ports[4].bits.uop.imm_sel connect slots_8.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[8].wakeup_ports[4].bits.uop.imm_rename connect slots_8.io.wakeup_ports[4].bits.uop.taken, issue_slots[8].wakeup_ports[4].bits.uop.taken connect slots_8.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[8].wakeup_ports[4].bits.uop.pc_lob connect slots_8.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[8].wakeup_ports[4].bits.uop.edge_inst connect slots_8.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[4].bits.uop.ftq_idx connect slots_8.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[8].wakeup_ports[4].bits.uop.is_mov connect slots_8.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[8].wakeup_ports[4].bits.uop.is_rocc connect slots_8.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_8.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[8].wakeup_ports[4].bits.uop.is_eret connect slots_8.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[8].wakeup_ports[4].bits.uop.is_amo connect slots_8.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[8].wakeup_ports[4].bits.uop.is_sfence connect slots_8.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[8].wakeup_ports[4].bits.uop.is_fencei connect slots_8.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[8].wakeup_ports[4].bits.uop.is_fence connect slots_8.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[8].wakeup_ports[4].bits.uop.is_sfb connect slots_8.io.wakeup_ports[4].bits.uop.br_type, issue_slots[8].wakeup_ports[4].bits.uop.br_type connect slots_8.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[8].wakeup_ports[4].bits.uop.br_tag connect slots_8.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[8].wakeup_ports[4].bits.uop.br_mask connect slots_8.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[4].bits.uop.dis_col_sel connect slots_8.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_8.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_8.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_8.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_8.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_8.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_8.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_8.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[8].wakeup_ports[4].bits.uop.iw_issued connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[0] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[1] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[2] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[3] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[4] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[5] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[6] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[7] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[8] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[9] connect slots_8.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[4].bits.uop.iq_type[0] connect slots_8.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[4].bits.uop.iq_type[1] connect slots_8.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[4].bits.uop.iq_type[2] connect slots_8.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[4].bits.uop.iq_type[3] connect slots_8.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[8].wakeup_ports[4].bits.uop.debug_pc connect slots_8.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[8].wakeup_ports[4].bits.uop.is_rvc connect slots_8.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[8].wakeup_ports[4].bits.uop.debug_inst connect slots_8.io.wakeup_ports[4].bits.uop.inst, issue_slots[8].wakeup_ports[4].bits.uop.inst connect slots_8.io.wakeup_ports[4].valid, issue_slots[8].wakeup_ports[4].valid connect slots_8.io.squash_grant, issue_slots[8].squash_grant connect slots_8.io.clear, issue_slots[8].clear connect slots_8.io.kill, issue_slots[8].kill connect slots_8.io.brupdate.b2.target_offset, issue_slots[8].brupdate.b2.target_offset connect slots_8.io.brupdate.b2.jalr_target, issue_slots[8].brupdate.b2.jalr_target connect slots_8.io.brupdate.b2.pc_sel, issue_slots[8].brupdate.b2.pc_sel connect slots_8.io.brupdate.b2.cfi_type, issue_slots[8].brupdate.b2.cfi_type connect slots_8.io.brupdate.b2.taken, issue_slots[8].brupdate.b2.taken connect slots_8.io.brupdate.b2.mispredict, issue_slots[8].brupdate.b2.mispredict connect slots_8.io.brupdate.b2.uop.debug_tsrc, issue_slots[8].brupdate.b2.uop.debug_tsrc connect slots_8.io.brupdate.b2.uop.debug_fsrc, issue_slots[8].brupdate.b2.uop.debug_fsrc connect slots_8.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[8].brupdate.b2.uop.bp_xcpt_if connect slots_8.io.brupdate.b2.uop.bp_debug_if, issue_slots[8].brupdate.b2.uop.bp_debug_if connect slots_8.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[8].brupdate.b2.uop.xcpt_ma_if connect slots_8.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[8].brupdate.b2.uop.xcpt_ae_if connect slots_8.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[8].brupdate.b2.uop.xcpt_pf_if connect slots_8.io.brupdate.b2.uop.fp_typ, issue_slots[8].brupdate.b2.uop.fp_typ connect slots_8.io.brupdate.b2.uop.fp_rm, issue_slots[8].brupdate.b2.uop.fp_rm connect slots_8.io.brupdate.b2.uop.fp_val, issue_slots[8].brupdate.b2.uop.fp_val connect slots_8.io.brupdate.b2.uop.fcn_op, issue_slots[8].brupdate.b2.uop.fcn_op connect slots_8.io.brupdate.b2.uop.fcn_dw, issue_slots[8].brupdate.b2.uop.fcn_dw connect slots_8.io.brupdate.b2.uop.frs3_en, issue_slots[8].brupdate.b2.uop.frs3_en connect slots_8.io.brupdate.b2.uop.lrs2_rtype, issue_slots[8].brupdate.b2.uop.lrs2_rtype connect slots_8.io.brupdate.b2.uop.lrs1_rtype, issue_slots[8].brupdate.b2.uop.lrs1_rtype connect slots_8.io.brupdate.b2.uop.dst_rtype, issue_slots[8].brupdate.b2.uop.dst_rtype connect slots_8.io.brupdate.b2.uop.lrs3, issue_slots[8].brupdate.b2.uop.lrs3 connect slots_8.io.brupdate.b2.uop.lrs2, issue_slots[8].brupdate.b2.uop.lrs2 connect slots_8.io.brupdate.b2.uop.lrs1, issue_slots[8].brupdate.b2.uop.lrs1 connect slots_8.io.brupdate.b2.uop.ldst, issue_slots[8].brupdate.b2.uop.ldst connect slots_8.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[8].brupdate.b2.uop.ldst_is_rs1 connect slots_8.io.brupdate.b2.uop.csr_cmd, issue_slots[8].brupdate.b2.uop.csr_cmd connect slots_8.io.brupdate.b2.uop.flush_on_commit, issue_slots[8].brupdate.b2.uop.flush_on_commit connect slots_8.io.brupdate.b2.uop.is_unique, issue_slots[8].brupdate.b2.uop.is_unique connect slots_8.io.brupdate.b2.uop.uses_stq, issue_slots[8].brupdate.b2.uop.uses_stq connect slots_8.io.brupdate.b2.uop.uses_ldq, issue_slots[8].brupdate.b2.uop.uses_ldq connect slots_8.io.brupdate.b2.uop.mem_signed, issue_slots[8].brupdate.b2.uop.mem_signed connect slots_8.io.brupdate.b2.uop.mem_size, issue_slots[8].brupdate.b2.uop.mem_size connect slots_8.io.brupdate.b2.uop.mem_cmd, issue_slots[8].brupdate.b2.uop.mem_cmd connect slots_8.io.brupdate.b2.uop.exc_cause, issue_slots[8].brupdate.b2.uop.exc_cause connect slots_8.io.brupdate.b2.uop.exception, issue_slots[8].brupdate.b2.uop.exception connect slots_8.io.brupdate.b2.uop.stale_pdst, issue_slots[8].brupdate.b2.uop.stale_pdst connect slots_8.io.brupdate.b2.uop.ppred_busy, issue_slots[8].brupdate.b2.uop.ppred_busy connect slots_8.io.brupdate.b2.uop.prs3_busy, issue_slots[8].brupdate.b2.uop.prs3_busy connect slots_8.io.brupdate.b2.uop.prs2_busy, issue_slots[8].brupdate.b2.uop.prs2_busy connect slots_8.io.brupdate.b2.uop.prs1_busy, issue_slots[8].brupdate.b2.uop.prs1_busy connect slots_8.io.brupdate.b2.uop.ppred, issue_slots[8].brupdate.b2.uop.ppred connect slots_8.io.brupdate.b2.uop.prs3, issue_slots[8].brupdate.b2.uop.prs3 connect slots_8.io.brupdate.b2.uop.prs2, issue_slots[8].brupdate.b2.uop.prs2 connect slots_8.io.brupdate.b2.uop.prs1, issue_slots[8].brupdate.b2.uop.prs1 connect slots_8.io.brupdate.b2.uop.pdst, issue_slots[8].brupdate.b2.uop.pdst connect slots_8.io.brupdate.b2.uop.rxq_idx, issue_slots[8].brupdate.b2.uop.rxq_idx connect slots_8.io.brupdate.b2.uop.stq_idx, issue_slots[8].brupdate.b2.uop.stq_idx connect slots_8.io.brupdate.b2.uop.ldq_idx, issue_slots[8].brupdate.b2.uop.ldq_idx connect slots_8.io.brupdate.b2.uop.rob_idx, issue_slots[8].brupdate.b2.uop.rob_idx connect slots_8.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[8].brupdate.b2.uop.fp_ctrl.vec connect slots_8.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[8].brupdate.b2.uop.fp_ctrl.wflags connect slots_8.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[8].brupdate.b2.uop.fp_ctrl.sqrt connect slots_8.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[8].brupdate.b2.uop.fp_ctrl.div connect slots_8.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[8].brupdate.b2.uop.fp_ctrl.fma connect slots_8.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[8].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_8.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[8].brupdate.b2.uop.fp_ctrl.toint connect slots_8.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[8].brupdate.b2.uop.fp_ctrl.fromint connect slots_8.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_8.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_8.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[8].brupdate.b2.uop.fp_ctrl.swap23 connect slots_8.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[8].brupdate.b2.uop.fp_ctrl.swap12 connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren3 connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren2 connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren1 connect slots_8.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[8].brupdate.b2.uop.fp_ctrl.wen connect slots_8.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[8].brupdate.b2.uop.fp_ctrl.ldst connect slots_8.io.brupdate.b2.uop.op2_sel, issue_slots[8].brupdate.b2.uop.op2_sel connect slots_8.io.brupdate.b2.uop.op1_sel, issue_slots[8].brupdate.b2.uop.op1_sel connect slots_8.io.brupdate.b2.uop.imm_packed, issue_slots[8].brupdate.b2.uop.imm_packed connect slots_8.io.brupdate.b2.uop.pimm, issue_slots[8].brupdate.b2.uop.pimm connect slots_8.io.brupdate.b2.uop.imm_sel, issue_slots[8].brupdate.b2.uop.imm_sel connect slots_8.io.brupdate.b2.uop.imm_rename, issue_slots[8].brupdate.b2.uop.imm_rename connect slots_8.io.brupdate.b2.uop.taken, issue_slots[8].brupdate.b2.uop.taken connect slots_8.io.brupdate.b2.uop.pc_lob, issue_slots[8].brupdate.b2.uop.pc_lob connect slots_8.io.brupdate.b2.uop.edge_inst, issue_slots[8].brupdate.b2.uop.edge_inst connect slots_8.io.brupdate.b2.uop.ftq_idx, issue_slots[8].brupdate.b2.uop.ftq_idx connect slots_8.io.brupdate.b2.uop.is_mov, issue_slots[8].brupdate.b2.uop.is_mov connect slots_8.io.brupdate.b2.uop.is_rocc, issue_slots[8].brupdate.b2.uop.is_rocc connect slots_8.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[8].brupdate.b2.uop.is_sys_pc2epc connect slots_8.io.brupdate.b2.uop.is_eret, issue_slots[8].brupdate.b2.uop.is_eret connect slots_8.io.brupdate.b2.uop.is_amo, issue_slots[8].brupdate.b2.uop.is_amo connect slots_8.io.brupdate.b2.uop.is_sfence, issue_slots[8].brupdate.b2.uop.is_sfence connect slots_8.io.brupdate.b2.uop.is_fencei, issue_slots[8].brupdate.b2.uop.is_fencei connect slots_8.io.brupdate.b2.uop.is_fence, issue_slots[8].brupdate.b2.uop.is_fence connect slots_8.io.brupdate.b2.uop.is_sfb, issue_slots[8].brupdate.b2.uop.is_sfb connect slots_8.io.brupdate.b2.uop.br_type, issue_slots[8].brupdate.b2.uop.br_type connect slots_8.io.brupdate.b2.uop.br_tag, issue_slots[8].brupdate.b2.uop.br_tag connect slots_8.io.brupdate.b2.uop.br_mask, issue_slots[8].brupdate.b2.uop.br_mask connect slots_8.io.brupdate.b2.uop.dis_col_sel, issue_slots[8].brupdate.b2.uop.dis_col_sel connect slots_8.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p3_bypass_hint connect slots_8.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p2_bypass_hint connect slots_8.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p1_bypass_hint connect slots_8.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[8].brupdate.b2.uop.iw_p2_speculative_child connect slots_8.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[8].brupdate.b2.uop.iw_p1_speculative_child connect slots_8.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[8].brupdate.b2.uop.iw_issued_partial_dgen connect slots_8.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[8].brupdate.b2.uop.iw_issued_partial_agen connect slots_8.io.brupdate.b2.uop.iw_issued, issue_slots[8].brupdate.b2.uop.iw_issued connect slots_8.io.brupdate.b2.uop.fu_code[0], issue_slots[8].brupdate.b2.uop.fu_code[0] connect slots_8.io.brupdate.b2.uop.fu_code[1], issue_slots[8].brupdate.b2.uop.fu_code[1] connect slots_8.io.brupdate.b2.uop.fu_code[2], issue_slots[8].brupdate.b2.uop.fu_code[2] connect slots_8.io.brupdate.b2.uop.fu_code[3], issue_slots[8].brupdate.b2.uop.fu_code[3] connect slots_8.io.brupdate.b2.uop.fu_code[4], issue_slots[8].brupdate.b2.uop.fu_code[4] connect slots_8.io.brupdate.b2.uop.fu_code[5], issue_slots[8].brupdate.b2.uop.fu_code[5] connect slots_8.io.brupdate.b2.uop.fu_code[6], issue_slots[8].brupdate.b2.uop.fu_code[6] connect slots_8.io.brupdate.b2.uop.fu_code[7], issue_slots[8].brupdate.b2.uop.fu_code[7] connect slots_8.io.brupdate.b2.uop.fu_code[8], issue_slots[8].brupdate.b2.uop.fu_code[8] connect slots_8.io.brupdate.b2.uop.fu_code[9], issue_slots[8].brupdate.b2.uop.fu_code[9] connect slots_8.io.brupdate.b2.uop.iq_type[0], issue_slots[8].brupdate.b2.uop.iq_type[0] connect slots_8.io.brupdate.b2.uop.iq_type[1], issue_slots[8].brupdate.b2.uop.iq_type[1] connect slots_8.io.brupdate.b2.uop.iq_type[2], issue_slots[8].brupdate.b2.uop.iq_type[2] connect slots_8.io.brupdate.b2.uop.iq_type[3], issue_slots[8].brupdate.b2.uop.iq_type[3] connect slots_8.io.brupdate.b2.uop.debug_pc, issue_slots[8].brupdate.b2.uop.debug_pc connect slots_8.io.brupdate.b2.uop.is_rvc, issue_slots[8].brupdate.b2.uop.is_rvc connect slots_8.io.brupdate.b2.uop.debug_inst, issue_slots[8].brupdate.b2.uop.debug_inst connect slots_8.io.brupdate.b2.uop.inst, issue_slots[8].brupdate.b2.uop.inst connect slots_8.io.brupdate.b1.mispredict_mask, issue_slots[8].brupdate.b1.mispredict_mask connect slots_8.io.brupdate.b1.resolve_mask, issue_slots[8].brupdate.b1.resolve_mask connect issue_slots[8].out_uop.debug_tsrc, slots_8.io.out_uop.debug_tsrc connect issue_slots[8].out_uop.debug_fsrc, slots_8.io.out_uop.debug_fsrc connect issue_slots[8].out_uop.bp_xcpt_if, slots_8.io.out_uop.bp_xcpt_if connect issue_slots[8].out_uop.bp_debug_if, slots_8.io.out_uop.bp_debug_if connect issue_slots[8].out_uop.xcpt_ma_if, slots_8.io.out_uop.xcpt_ma_if connect issue_slots[8].out_uop.xcpt_ae_if, slots_8.io.out_uop.xcpt_ae_if connect issue_slots[8].out_uop.xcpt_pf_if, slots_8.io.out_uop.xcpt_pf_if connect issue_slots[8].out_uop.fp_typ, slots_8.io.out_uop.fp_typ connect issue_slots[8].out_uop.fp_rm, slots_8.io.out_uop.fp_rm connect issue_slots[8].out_uop.fp_val, slots_8.io.out_uop.fp_val connect issue_slots[8].out_uop.fcn_op, slots_8.io.out_uop.fcn_op connect issue_slots[8].out_uop.fcn_dw, slots_8.io.out_uop.fcn_dw connect issue_slots[8].out_uop.frs3_en, slots_8.io.out_uop.frs3_en connect issue_slots[8].out_uop.lrs2_rtype, slots_8.io.out_uop.lrs2_rtype connect issue_slots[8].out_uop.lrs1_rtype, slots_8.io.out_uop.lrs1_rtype connect issue_slots[8].out_uop.dst_rtype, slots_8.io.out_uop.dst_rtype connect issue_slots[8].out_uop.lrs3, slots_8.io.out_uop.lrs3 connect issue_slots[8].out_uop.lrs2, slots_8.io.out_uop.lrs2 connect issue_slots[8].out_uop.lrs1, slots_8.io.out_uop.lrs1 connect issue_slots[8].out_uop.ldst, slots_8.io.out_uop.ldst connect issue_slots[8].out_uop.ldst_is_rs1, slots_8.io.out_uop.ldst_is_rs1 connect issue_slots[8].out_uop.csr_cmd, slots_8.io.out_uop.csr_cmd connect issue_slots[8].out_uop.flush_on_commit, slots_8.io.out_uop.flush_on_commit connect issue_slots[8].out_uop.is_unique, slots_8.io.out_uop.is_unique connect issue_slots[8].out_uop.uses_stq, slots_8.io.out_uop.uses_stq connect issue_slots[8].out_uop.uses_ldq, slots_8.io.out_uop.uses_ldq connect issue_slots[8].out_uop.mem_signed, slots_8.io.out_uop.mem_signed connect issue_slots[8].out_uop.mem_size, slots_8.io.out_uop.mem_size connect issue_slots[8].out_uop.mem_cmd, slots_8.io.out_uop.mem_cmd connect issue_slots[8].out_uop.exc_cause, slots_8.io.out_uop.exc_cause connect issue_slots[8].out_uop.exception, slots_8.io.out_uop.exception connect issue_slots[8].out_uop.stale_pdst, slots_8.io.out_uop.stale_pdst connect issue_slots[8].out_uop.ppred_busy, slots_8.io.out_uop.ppred_busy connect issue_slots[8].out_uop.prs3_busy, slots_8.io.out_uop.prs3_busy connect issue_slots[8].out_uop.prs2_busy, slots_8.io.out_uop.prs2_busy connect issue_slots[8].out_uop.prs1_busy, slots_8.io.out_uop.prs1_busy connect issue_slots[8].out_uop.ppred, slots_8.io.out_uop.ppred connect issue_slots[8].out_uop.prs3, slots_8.io.out_uop.prs3 connect issue_slots[8].out_uop.prs2, slots_8.io.out_uop.prs2 connect issue_slots[8].out_uop.prs1, slots_8.io.out_uop.prs1 connect issue_slots[8].out_uop.pdst, slots_8.io.out_uop.pdst connect issue_slots[8].out_uop.rxq_idx, slots_8.io.out_uop.rxq_idx connect issue_slots[8].out_uop.stq_idx, slots_8.io.out_uop.stq_idx connect issue_slots[8].out_uop.ldq_idx, slots_8.io.out_uop.ldq_idx connect issue_slots[8].out_uop.rob_idx, slots_8.io.out_uop.rob_idx connect issue_slots[8].out_uop.fp_ctrl.vec, slots_8.io.out_uop.fp_ctrl.vec connect issue_slots[8].out_uop.fp_ctrl.wflags, slots_8.io.out_uop.fp_ctrl.wflags connect issue_slots[8].out_uop.fp_ctrl.sqrt, slots_8.io.out_uop.fp_ctrl.sqrt connect issue_slots[8].out_uop.fp_ctrl.div, slots_8.io.out_uop.fp_ctrl.div connect issue_slots[8].out_uop.fp_ctrl.fma, slots_8.io.out_uop.fp_ctrl.fma connect issue_slots[8].out_uop.fp_ctrl.fastpipe, slots_8.io.out_uop.fp_ctrl.fastpipe connect issue_slots[8].out_uop.fp_ctrl.toint, slots_8.io.out_uop.fp_ctrl.toint connect issue_slots[8].out_uop.fp_ctrl.fromint, slots_8.io.out_uop.fp_ctrl.fromint connect issue_slots[8].out_uop.fp_ctrl.typeTagOut, slots_8.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[8].out_uop.fp_ctrl.typeTagIn, slots_8.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[8].out_uop.fp_ctrl.swap23, slots_8.io.out_uop.fp_ctrl.swap23 connect issue_slots[8].out_uop.fp_ctrl.swap12, slots_8.io.out_uop.fp_ctrl.swap12 connect issue_slots[8].out_uop.fp_ctrl.ren3, slots_8.io.out_uop.fp_ctrl.ren3 connect issue_slots[8].out_uop.fp_ctrl.ren2, slots_8.io.out_uop.fp_ctrl.ren2 connect issue_slots[8].out_uop.fp_ctrl.ren1, slots_8.io.out_uop.fp_ctrl.ren1 connect issue_slots[8].out_uop.fp_ctrl.wen, slots_8.io.out_uop.fp_ctrl.wen connect issue_slots[8].out_uop.fp_ctrl.ldst, slots_8.io.out_uop.fp_ctrl.ldst connect issue_slots[8].out_uop.op2_sel, slots_8.io.out_uop.op2_sel connect issue_slots[8].out_uop.op1_sel, slots_8.io.out_uop.op1_sel connect issue_slots[8].out_uop.imm_packed, slots_8.io.out_uop.imm_packed connect issue_slots[8].out_uop.pimm, slots_8.io.out_uop.pimm connect issue_slots[8].out_uop.imm_sel, slots_8.io.out_uop.imm_sel connect issue_slots[8].out_uop.imm_rename, slots_8.io.out_uop.imm_rename connect issue_slots[8].out_uop.taken, slots_8.io.out_uop.taken connect issue_slots[8].out_uop.pc_lob, slots_8.io.out_uop.pc_lob connect issue_slots[8].out_uop.edge_inst, slots_8.io.out_uop.edge_inst connect issue_slots[8].out_uop.ftq_idx, slots_8.io.out_uop.ftq_idx connect issue_slots[8].out_uop.is_mov, slots_8.io.out_uop.is_mov connect issue_slots[8].out_uop.is_rocc, slots_8.io.out_uop.is_rocc connect issue_slots[8].out_uop.is_sys_pc2epc, slots_8.io.out_uop.is_sys_pc2epc connect issue_slots[8].out_uop.is_eret, slots_8.io.out_uop.is_eret connect issue_slots[8].out_uop.is_amo, slots_8.io.out_uop.is_amo connect issue_slots[8].out_uop.is_sfence, slots_8.io.out_uop.is_sfence connect issue_slots[8].out_uop.is_fencei, slots_8.io.out_uop.is_fencei connect issue_slots[8].out_uop.is_fence, slots_8.io.out_uop.is_fence connect issue_slots[8].out_uop.is_sfb, slots_8.io.out_uop.is_sfb connect issue_slots[8].out_uop.br_type, slots_8.io.out_uop.br_type connect issue_slots[8].out_uop.br_tag, slots_8.io.out_uop.br_tag connect issue_slots[8].out_uop.br_mask, slots_8.io.out_uop.br_mask connect issue_slots[8].out_uop.dis_col_sel, slots_8.io.out_uop.dis_col_sel connect issue_slots[8].out_uop.iw_p3_bypass_hint, slots_8.io.out_uop.iw_p3_bypass_hint connect issue_slots[8].out_uop.iw_p2_bypass_hint, slots_8.io.out_uop.iw_p2_bypass_hint connect issue_slots[8].out_uop.iw_p1_bypass_hint, slots_8.io.out_uop.iw_p1_bypass_hint connect issue_slots[8].out_uop.iw_p2_speculative_child, slots_8.io.out_uop.iw_p2_speculative_child connect issue_slots[8].out_uop.iw_p1_speculative_child, slots_8.io.out_uop.iw_p1_speculative_child connect issue_slots[8].out_uop.iw_issued_partial_dgen, slots_8.io.out_uop.iw_issued_partial_dgen connect issue_slots[8].out_uop.iw_issued_partial_agen, slots_8.io.out_uop.iw_issued_partial_agen connect issue_slots[8].out_uop.iw_issued, slots_8.io.out_uop.iw_issued connect issue_slots[8].out_uop.fu_code[0], slots_8.io.out_uop.fu_code[0] connect issue_slots[8].out_uop.fu_code[1], slots_8.io.out_uop.fu_code[1] connect issue_slots[8].out_uop.fu_code[2], slots_8.io.out_uop.fu_code[2] connect issue_slots[8].out_uop.fu_code[3], slots_8.io.out_uop.fu_code[3] connect issue_slots[8].out_uop.fu_code[4], slots_8.io.out_uop.fu_code[4] connect issue_slots[8].out_uop.fu_code[5], slots_8.io.out_uop.fu_code[5] connect issue_slots[8].out_uop.fu_code[6], slots_8.io.out_uop.fu_code[6] connect issue_slots[8].out_uop.fu_code[7], slots_8.io.out_uop.fu_code[7] connect issue_slots[8].out_uop.fu_code[8], slots_8.io.out_uop.fu_code[8] connect issue_slots[8].out_uop.fu_code[9], slots_8.io.out_uop.fu_code[9] connect issue_slots[8].out_uop.iq_type[0], slots_8.io.out_uop.iq_type[0] connect issue_slots[8].out_uop.iq_type[1], slots_8.io.out_uop.iq_type[1] connect issue_slots[8].out_uop.iq_type[2], slots_8.io.out_uop.iq_type[2] connect issue_slots[8].out_uop.iq_type[3], slots_8.io.out_uop.iq_type[3] connect issue_slots[8].out_uop.debug_pc, slots_8.io.out_uop.debug_pc connect issue_slots[8].out_uop.is_rvc, slots_8.io.out_uop.is_rvc connect issue_slots[8].out_uop.debug_inst, slots_8.io.out_uop.debug_inst connect issue_slots[8].out_uop.inst, slots_8.io.out_uop.inst connect slots_8.io.in_uop.bits.debug_tsrc, issue_slots[8].in_uop.bits.debug_tsrc connect slots_8.io.in_uop.bits.debug_fsrc, issue_slots[8].in_uop.bits.debug_fsrc connect slots_8.io.in_uop.bits.bp_xcpt_if, issue_slots[8].in_uop.bits.bp_xcpt_if connect slots_8.io.in_uop.bits.bp_debug_if, issue_slots[8].in_uop.bits.bp_debug_if connect slots_8.io.in_uop.bits.xcpt_ma_if, issue_slots[8].in_uop.bits.xcpt_ma_if connect slots_8.io.in_uop.bits.xcpt_ae_if, issue_slots[8].in_uop.bits.xcpt_ae_if connect slots_8.io.in_uop.bits.xcpt_pf_if, issue_slots[8].in_uop.bits.xcpt_pf_if connect slots_8.io.in_uop.bits.fp_typ, issue_slots[8].in_uop.bits.fp_typ connect slots_8.io.in_uop.bits.fp_rm, issue_slots[8].in_uop.bits.fp_rm connect slots_8.io.in_uop.bits.fp_val, issue_slots[8].in_uop.bits.fp_val connect slots_8.io.in_uop.bits.fcn_op, issue_slots[8].in_uop.bits.fcn_op connect slots_8.io.in_uop.bits.fcn_dw, issue_slots[8].in_uop.bits.fcn_dw connect slots_8.io.in_uop.bits.frs3_en, issue_slots[8].in_uop.bits.frs3_en connect slots_8.io.in_uop.bits.lrs2_rtype, issue_slots[8].in_uop.bits.lrs2_rtype connect slots_8.io.in_uop.bits.lrs1_rtype, issue_slots[8].in_uop.bits.lrs1_rtype connect slots_8.io.in_uop.bits.dst_rtype, issue_slots[8].in_uop.bits.dst_rtype connect slots_8.io.in_uop.bits.lrs3, issue_slots[8].in_uop.bits.lrs3 connect slots_8.io.in_uop.bits.lrs2, issue_slots[8].in_uop.bits.lrs2 connect slots_8.io.in_uop.bits.lrs1, issue_slots[8].in_uop.bits.lrs1 connect slots_8.io.in_uop.bits.ldst, issue_slots[8].in_uop.bits.ldst connect slots_8.io.in_uop.bits.ldst_is_rs1, issue_slots[8].in_uop.bits.ldst_is_rs1 connect slots_8.io.in_uop.bits.csr_cmd, issue_slots[8].in_uop.bits.csr_cmd connect slots_8.io.in_uop.bits.flush_on_commit, issue_slots[8].in_uop.bits.flush_on_commit connect slots_8.io.in_uop.bits.is_unique, issue_slots[8].in_uop.bits.is_unique connect slots_8.io.in_uop.bits.uses_stq, issue_slots[8].in_uop.bits.uses_stq connect slots_8.io.in_uop.bits.uses_ldq, issue_slots[8].in_uop.bits.uses_ldq connect slots_8.io.in_uop.bits.mem_signed, issue_slots[8].in_uop.bits.mem_signed connect slots_8.io.in_uop.bits.mem_size, issue_slots[8].in_uop.bits.mem_size connect slots_8.io.in_uop.bits.mem_cmd, issue_slots[8].in_uop.bits.mem_cmd connect slots_8.io.in_uop.bits.exc_cause, issue_slots[8].in_uop.bits.exc_cause connect slots_8.io.in_uop.bits.exception, issue_slots[8].in_uop.bits.exception connect slots_8.io.in_uop.bits.stale_pdst, issue_slots[8].in_uop.bits.stale_pdst connect slots_8.io.in_uop.bits.ppred_busy, issue_slots[8].in_uop.bits.ppred_busy connect slots_8.io.in_uop.bits.prs3_busy, issue_slots[8].in_uop.bits.prs3_busy connect slots_8.io.in_uop.bits.prs2_busy, issue_slots[8].in_uop.bits.prs2_busy connect slots_8.io.in_uop.bits.prs1_busy, issue_slots[8].in_uop.bits.prs1_busy connect slots_8.io.in_uop.bits.ppred, issue_slots[8].in_uop.bits.ppred connect slots_8.io.in_uop.bits.prs3, issue_slots[8].in_uop.bits.prs3 connect slots_8.io.in_uop.bits.prs2, issue_slots[8].in_uop.bits.prs2 connect slots_8.io.in_uop.bits.prs1, issue_slots[8].in_uop.bits.prs1 connect slots_8.io.in_uop.bits.pdst, issue_slots[8].in_uop.bits.pdst connect slots_8.io.in_uop.bits.rxq_idx, issue_slots[8].in_uop.bits.rxq_idx connect slots_8.io.in_uop.bits.stq_idx, issue_slots[8].in_uop.bits.stq_idx connect slots_8.io.in_uop.bits.ldq_idx, issue_slots[8].in_uop.bits.ldq_idx connect slots_8.io.in_uop.bits.rob_idx, issue_slots[8].in_uop.bits.rob_idx connect slots_8.io.in_uop.bits.fp_ctrl.vec, issue_slots[8].in_uop.bits.fp_ctrl.vec connect slots_8.io.in_uop.bits.fp_ctrl.wflags, issue_slots[8].in_uop.bits.fp_ctrl.wflags connect slots_8.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[8].in_uop.bits.fp_ctrl.sqrt connect slots_8.io.in_uop.bits.fp_ctrl.div, issue_slots[8].in_uop.bits.fp_ctrl.div connect slots_8.io.in_uop.bits.fp_ctrl.fma, issue_slots[8].in_uop.bits.fp_ctrl.fma connect slots_8.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].in_uop.bits.fp_ctrl.fastpipe connect slots_8.io.in_uop.bits.fp_ctrl.toint, issue_slots[8].in_uop.bits.fp_ctrl.toint connect slots_8.io.in_uop.bits.fp_ctrl.fromint, issue_slots[8].in_uop.bits.fp_ctrl.fromint connect slots_8.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut connect slots_8.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn connect slots_8.io.in_uop.bits.fp_ctrl.swap23, issue_slots[8].in_uop.bits.fp_ctrl.swap23 connect slots_8.io.in_uop.bits.fp_ctrl.swap12, issue_slots[8].in_uop.bits.fp_ctrl.swap12 connect slots_8.io.in_uop.bits.fp_ctrl.ren3, issue_slots[8].in_uop.bits.fp_ctrl.ren3 connect slots_8.io.in_uop.bits.fp_ctrl.ren2, issue_slots[8].in_uop.bits.fp_ctrl.ren2 connect slots_8.io.in_uop.bits.fp_ctrl.ren1, issue_slots[8].in_uop.bits.fp_ctrl.ren1 connect slots_8.io.in_uop.bits.fp_ctrl.wen, issue_slots[8].in_uop.bits.fp_ctrl.wen connect slots_8.io.in_uop.bits.fp_ctrl.ldst, issue_slots[8].in_uop.bits.fp_ctrl.ldst connect slots_8.io.in_uop.bits.op2_sel, issue_slots[8].in_uop.bits.op2_sel connect slots_8.io.in_uop.bits.op1_sel, issue_slots[8].in_uop.bits.op1_sel connect slots_8.io.in_uop.bits.imm_packed, issue_slots[8].in_uop.bits.imm_packed connect slots_8.io.in_uop.bits.pimm, issue_slots[8].in_uop.bits.pimm connect slots_8.io.in_uop.bits.imm_sel, issue_slots[8].in_uop.bits.imm_sel connect slots_8.io.in_uop.bits.imm_rename, issue_slots[8].in_uop.bits.imm_rename connect slots_8.io.in_uop.bits.taken, issue_slots[8].in_uop.bits.taken connect slots_8.io.in_uop.bits.pc_lob, issue_slots[8].in_uop.bits.pc_lob connect slots_8.io.in_uop.bits.edge_inst, issue_slots[8].in_uop.bits.edge_inst connect slots_8.io.in_uop.bits.ftq_idx, issue_slots[8].in_uop.bits.ftq_idx connect slots_8.io.in_uop.bits.is_mov, issue_slots[8].in_uop.bits.is_mov connect slots_8.io.in_uop.bits.is_rocc, issue_slots[8].in_uop.bits.is_rocc connect slots_8.io.in_uop.bits.is_sys_pc2epc, issue_slots[8].in_uop.bits.is_sys_pc2epc connect slots_8.io.in_uop.bits.is_eret, issue_slots[8].in_uop.bits.is_eret connect slots_8.io.in_uop.bits.is_amo, issue_slots[8].in_uop.bits.is_amo connect slots_8.io.in_uop.bits.is_sfence, issue_slots[8].in_uop.bits.is_sfence connect slots_8.io.in_uop.bits.is_fencei, issue_slots[8].in_uop.bits.is_fencei connect slots_8.io.in_uop.bits.is_fence, issue_slots[8].in_uop.bits.is_fence connect slots_8.io.in_uop.bits.is_sfb, issue_slots[8].in_uop.bits.is_sfb connect slots_8.io.in_uop.bits.br_type, issue_slots[8].in_uop.bits.br_type connect slots_8.io.in_uop.bits.br_tag, issue_slots[8].in_uop.bits.br_tag connect slots_8.io.in_uop.bits.br_mask, issue_slots[8].in_uop.bits.br_mask connect slots_8.io.in_uop.bits.dis_col_sel, issue_slots[8].in_uop.bits.dis_col_sel connect slots_8.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[8].in_uop.bits.iw_p3_bypass_hint connect slots_8.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[8].in_uop.bits.iw_p2_bypass_hint connect slots_8.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[8].in_uop.bits.iw_p1_bypass_hint connect slots_8.io.in_uop.bits.iw_p2_speculative_child, issue_slots[8].in_uop.bits.iw_p2_speculative_child connect slots_8.io.in_uop.bits.iw_p1_speculative_child, issue_slots[8].in_uop.bits.iw_p1_speculative_child connect slots_8.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[8].in_uop.bits.iw_issued_partial_dgen connect slots_8.io.in_uop.bits.iw_issued_partial_agen, issue_slots[8].in_uop.bits.iw_issued_partial_agen connect slots_8.io.in_uop.bits.iw_issued, issue_slots[8].in_uop.bits.iw_issued connect slots_8.io.in_uop.bits.fu_code[0], issue_slots[8].in_uop.bits.fu_code[0] connect slots_8.io.in_uop.bits.fu_code[1], issue_slots[8].in_uop.bits.fu_code[1] connect slots_8.io.in_uop.bits.fu_code[2], issue_slots[8].in_uop.bits.fu_code[2] connect slots_8.io.in_uop.bits.fu_code[3], issue_slots[8].in_uop.bits.fu_code[3] connect slots_8.io.in_uop.bits.fu_code[4], issue_slots[8].in_uop.bits.fu_code[4] connect slots_8.io.in_uop.bits.fu_code[5], issue_slots[8].in_uop.bits.fu_code[5] connect slots_8.io.in_uop.bits.fu_code[6], issue_slots[8].in_uop.bits.fu_code[6] connect slots_8.io.in_uop.bits.fu_code[7], issue_slots[8].in_uop.bits.fu_code[7] connect slots_8.io.in_uop.bits.fu_code[8], issue_slots[8].in_uop.bits.fu_code[8] connect slots_8.io.in_uop.bits.fu_code[9], issue_slots[8].in_uop.bits.fu_code[9] connect slots_8.io.in_uop.bits.iq_type[0], issue_slots[8].in_uop.bits.iq_type[0] connect slots_8.io.in_uop.bits.iq_type[1], issue_slots[8].in_uop.bits.iq_type[1] connect slots_8.io.in_uop.bits.iq_type[2], issue_slots[8].in_uop.bits.iq_type[2] connect slots_8.io.in_uop.bits.iq_type[3], issue_slots[8].in_uop.bits.iq_type[3] connect slots_8.io.in_uop.bits.debug_pc, issue_slots[8].in_uop.bits.debug_pc connect slots_8.io.in_uop.bits.is_rvc, issue_slots[8].in_uop.bits.is_rvc connect slots_8.io.in_uop.bits.debug_inst, issue_slots[8].in_uop.bits.debug_inst connect slots_8.io.in_uop.bits.inst, issue_slots[8].in_uop.bits.inst connect slots_8.io.in_uop.valid, issue_slots[8].in_uop.valid connect issue_slots[8].iss_uop.debug_tsrc, slots_8.io.iss_uop.debug_tsrc connect issue_slots[8].iss_uop.debug_fsrc, slots_8.io.iss_uop.debug_fsrc connect issue_slots[8].iss_uop.bp_xcpt_if, slots_8.io.iss_uop.bp_xcpt_if connect issue_slots[8].iss_uop.bp_debug_if, slots_8.io.iss_uop.bp_debug_if connect issue_slots[8].iss_uop.xcpt_ma_if, slots_8.io.iss_uop.xcpt_ma_if connect issue_slots[8].iss_uop.xcpt_ae_if, slots_8.io.iss_uop.xcpt_ae_if connect issue_slots[8].iss_uop.xcpt_pf_if, slots_8.io.iss_uop.xcpt_pf_if connect issue_slots[8].iss_uop.fp_typ, slots_8.io.iss_uop.fp_typ connect issue_slots[8].iss_uop.fp_rm, slots_8.io.iss_uop.fp_rm connect issue_slots[8].iss_uop.fp_val, slots_8.io.iss_uop.fp_val connect issue_slots[8].iss_uop.fcn_op, slots_8.io.iss_uop.fcn_op connect issue_slots[8].iss_uop.fcn_dw, slots_8.io.iss_uop.fcn_dw connect issue_slots[8].iss_uop.frs3_en, slots_8.io.iss_uop.frs3_en connect issue_slots[8].iss_uop.lrs2_rtype, slots_8.io.iss_uop.lrs2_rtype connect issue_slots[8].iss_uop.lrs1_rtype, slots_8.io.iss_uop.lrs1_rtype connect issue_slots[8].iss_uop.dst_rtype, slots_8.io.iss_uop.dst_rtype connect issue_slots[8].iss_uop.lrs3, slots_8.io.iss_uop.lrs3 connect issue_slots[8].iss_uop.lrs2, slots_8.io.iss_uop.lrs2 connect issue_slots[8].iss_uop.lrs1, slots_8.io.iss_uop.lrs1 connect issue_slots[8].iss_uop.ldst, slots_8.io.iss_uop.ldst connect issue_slots[8].iss_uop.ldst_is_rs1, slots_8.io.iss_uop.ldst_is_rs1 connect issue_slots[8].iss_uop.csr_cmd, slots_8.io.iss_uop.csr_cmd connect issue_slots[8].iss_uop.flush_on_commit, slots_8.io.iss_uop.flush_on_commit connect issue_slots[8].iss_uop.is_unique, slots_8.io.iss_uop.is_unique connect issue_slots[8].iss_uop.uses_stq, slots_8.io.iss_uop.uses_stq connect issue_slots[8].iss_uop.uses_ldq, slots_8.io.iss_uop.uses_ldq connect issue_slots[8].iss_uop.mem_signed, slots_8.io.iss_uop.mem_signed connect issue_slots[8].iss_uop.mem_size, slots_8.io.iss_uop.mem_size connect issue_slots[8].iss_uop.mem_cmd, slots_8.io.iss_uop.mem_cmd connect issue_slots[8].iss_uop.exc_cause, slots_8.io.iss_uop.exc_cause connect issue_slots[8].iss_uop.exception, slots_8.io.iss_uop.exception connect issue_slots[8].iss_uop.stale_pdst, slots_8.io.iss_uop.stale_pdst connect issue_slots[8].iss_uop.ppred_busy, slots_8.io.iss_uop.ppred_busy connect issue_slots[8].iss_uop.prs3_busy, slots_8.io.iss_uop.prs3_busy connect issue_slots[8].iss_uop.prs2_busy, slots_8.io.iss_uop.prs2_busy connect issue_slots[8].iss_uop.prs1_busy, slots_8.io.iss_uop.prs1_busy connect issue_slots[8].iss_uop.ppred, slots_8.io.iss_uop.ppred connect issue_slots[8].iss_uop.prs3, slots_8.io.iss_uop.prs3 connect issue_slots[8].iss_uop.prs2, slots_8.io.iss_uop.prs2 connect issue_slots[8].iss_uop.prs1, slots_8.io.iss_uop.prs1 connect issue_slots[8].iss_uop.pdst, slots_8.io.iss_uop.pdst connect issue_slots[8].iss_uop.rxq_idx, slots_8.io.iss_uop.rxq_idx connect issue_slots[8].iss_uop.stq_idx, slots_8.io.iss_uop.stq_idx connect issue_slots[8].iss_uop.ldq_idx, slots_8.io.iss_uop.ldq_idx connect issue_slots[8].iss_uop.rob_idx, slots_8.io.iss_uop.rob_idx connect issue_slots[8].iss_uop.fp_ctrl.vec, slots_8.io.iss_uop.fp_ctrl.vec connect issue_slots[8].iss_uop.fp_ctrl.wflags, slots_8.io.iss_uop.fp_ctrl.wflags connect issue_slots[8].iss_uop.fp_ctrl.sqrt, slots_8.io.iss_uop.fp_ctrl.sqrt connect issue_slots[8].iss_uop.fp_ctrl.div, slots_8.io.iss_uop.fp_ctrl.div connect issue_slots[8].iss_uop.fp_ctrl.fma, slots_8.io.iss_uop.fp_ctrl.fma connect issue_slots[8].iss_uop.fp_ctrl.fastpipe, slots_8.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[8].iss_uop.fp_ctrl.toint, slots_8.io.iss_uop.fp_ctrl.toint connect issue_slots[8].iss_uop.fp_ctrl.fromint, slots_8.io.iss_uop.fp_ctrl.fromint connect issue_slots[8].iss_uop.fp_ctrl.typeTagOut, slots_8.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[8].iss_uop.fp_ctrl.typeTagIn, slots_8.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[8].iss_uop.fp_ctrl.swap23, slots_8.io.iss_uop.fp_ctrl.swap23 connect issue_slots[8].iss_uop.fp_ctrl.swap12, slots_8.io.iss_uop.fp_ctrl.swap12 connect issue_slots[8].iss_uop.fp_ctrl.ren3, slots_8.io.iss_uop.fp_ctrl.ren3 connect issue_slots[8].iss_uop.fp_ctrl.ren2, slots_8.io.iss_uop.fp_ctrl.ren2 connect issue_slots[8].iss_uop.fp_ctrl.ren1, slots_8.io.iss_uop.fp_ctrl.ren1 connect issue_slots[8].iss_uop.fp_ctrl.wen, slots_8.io.iss_uop.fp_ctrl.wen connect issue_slots[8].iss_uop.fp_ctrl.ldst, slots_8.io.iss_uop.fp_ctrl.ldst connect issue_slots[8].iss_uop.op2_sel, slots_8.io.iss_uop.op2_sel connect issue_slots[8].iss_uop.op1_sel, slots_8.io.iss_uop.op1_sel connect issue_slots[8].iss_uop.imm_packed, slots_8.io.iss_uop.imm_packed connect issue_slots[8].iss_uop.pimm, slots_8.io.iss_uop.pimm connect issue_slots[8].iss_uop.imm_sel, slots_8.io.iss_uop.imm_sel connect issue_slots[8].iss_uop.imm_rename, slots_8.io.iss_uop.imm_rename connect issue_slots[8].iss_uop.taken, slots_8.io.iss_uop.taken connect issue_slots[8].iss_uop.pc_lob, slots_8.io.iss_uop.pc_lob connect issue_slots[8].iss_uop.edge_inst, slots_8.io.iss_uop.edge_inst connect issue_slots[8].iss_uop.ftq_idx, slots_8.io.iss_uop.ftq_idx connect issue_slots[8].iss_uop.is_mov, slots_8.io.iss_uop.is_mov connect issue_slots[8].iss_uop.is_rocc, slots_8.io.iss_uop.is_rocc connect issue_slots[8].iss_uop.is_sys_pc2epc, slots_8.io.iss_uop.is_sys_pc2epc connect issue_slots[8].iss_uop.is_eret, slots_8.io.iss_uop.is_eret connect issue_slots[8].iss_uop.is_amo, slots_8.io.iss_uop.is_amo connect issue_slots[8].iss_uop.is_sfence, slots_8.io.iss_uop.is_sfence connect issue_slots[8].iss_uop.is_fencei, slots_8.io.iss_uop.is_fencei connect issue_slots[8].iss_uop.is_fence, slots_8.io.iss_uop.is_fence connect issue_slots[8].iss_uop.is_sfb, slots_8.io.iss_uop.is_sfb connect issue_slots[8].iss_uop.br_type, slots_8.io.iss_uop.br_type connect issue_slots[8].iss_uop.br_tag, slots_8.io.iss_uop.br_tag connect issue_slots[8].iss_uop.br_mask, slots_8.io.iss_uop.br_mask connect issue_slots[8].iss_uop.dis_col_sel, slots_8.io.iss_uop.dis_col_sel connect issue_slots[8].iss_uop.iw_p3_bypass_hint, slots_8.io.iss_uop.iw_p3_bypass_hint connect issue_slots[8].iss_uop.iw_p2_bypass_hint, slots_8.io.iss_uop.iw_p2_bypass_hint connect issue_slots[8].iss_uop.iw_p1_bypass_hint, slots_8.io.iss_uop.iw_p1_bypass_hint connect issue_slots[8].iss_uop.iw_p2_speculative_child, slots_8.io.iss_uop.iw_p2_speculative_child connect issue_slots[8].iss_uop.iw_p1_speculative_child, slots_8.io.iss_uop.iw_p1_speculative_child connect issue_slots[8].iss_uop.iw_issued_partial_dgen, slots_8.io.iss_uop.iw_issued_partial_dgen connect issue_slots[8].iss_uop.iw_issued_partial_agen, slots_8.io.iss_uop.iw_issued_partial_agen connect issue_slots[8].iss_uop.iw_issued, slots_8.io.iss_uop.iw_issued connect issue_slots[8].iss_uop.fu_code[0], slots_8.io.iss_uop.fu_code[0] connect issue_slots[8].iss_uop.fu_code[1], slots_8.io.iss_uop.fu_code[1] connect issue_slots[8].iss_uop.fu_code[2], slots_8.io.iss_uop.fu_code[2] connect issue_slots[8].iss_uop.fu_code[3], slots_8.io.iss_uop.fu_code[3] connect issue_slots[8].iss_uop.fu_code[4], slots_8.io.iss_uop.fu_code[4] connect issue_slots[8].iss_uop.fu_code[5], slots_8.io.iss_uop.fu_code[5] connect issue_slots[8].iss_uop.fu_code[6], slots_8.io.iss_uop.fu_code[6] connect issue_slots[8].iss_uop.fu_code[7], slots_8.io.iss_uop.fu_code[7] connect issue_slots[8].iss_uop.fu_code[8], slots_8.io.iss_uop.fu_code[8] connect issue_slots[8].iss_uop.fu_code[9], slots_8.io.iss_uop.fu_code[9] connect issue_slots[8].iss_uop.iq_type[0], slots_8.io.iss_uop.iq_type[0] connect issue_slots[8].iss_uop.iq_type[1], slots_8.io.iss_uop.iq_type[1] connect issue_slots[8].iss_uop.iq_type[2], slots_8.io.iss_uop.iq_type[2] connect issue_slots[8].iss_uop.iq_type[3], slots_8.io.iss_uop.iq_type[3] connect issue_slots[8].iss_uop.debug_pc, slots_8.io.iss_uop.debug_pc connect issue_slots[8].iss_uop.is_rvc, slots_8.io.iss_uop.is_rvc connect issue_slots[8].iss_uop.debug_inst, slots_8.io.iss_uop.debug_inst connect issue_slots[8].iss_uop.inst, slots_8.io.iss_uop.inst connect slots_8.io.grant, issue_slots[8].grant connect issue_slots[8].request, slots_8.io.request connect issue_slots[8].will_be_valid, slots_8.io.will_be_valid connect issue_slots[8].valid, slots_8.io.valid connect slots_9.io.child_rebusys, issue_slots[9].child_rebusys connect slots_9.io.pred_wakeup_port.bits, issue_slots[9].pred_wakeup_port.bits connect slots_9.io.pred_wakeup_port.valid, issue_slots[9].pred_wakeup_port.valid connect slots_9.io.wakeup_ports[0].bits.rebusy, issue_slots[9].wakeup_ports[0].bits.rebusy connect slots_9.io.wakeup_ports[0].bits.speculative_mask, issue_slots[9].wakeup_ports[0].bits.speculative_mask connect slots_9.io.wakeup_ports[0].bits.bypassable, issue_slots[9].wakeup_ports[0].bits.bypassable connect slots_9.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[0].bits.uop.debug_tsrc connect slots_9.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[0].bits.uop.debug_fsrc connect slots_9.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_9.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[0].bits.uop.bp_debug_if connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_9.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[9].wakeup_ports[0].bits.uop.fp_typ connect slots_9.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[9].wakeup_ports[0].bits.uop.fp_rm connect slots_9.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[9].wakeup_ports[0].bits.uop.fp_val connect slots_9.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[9].wakeup_ports[0].bits.uop.fcn_op connect slots_9.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[0].bits.uop.fcn_dw connect slots_9.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[9].wakeup_ports[0].bits.uop.frs3_en connect slots_9.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_9.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_9.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[0].bits.uop.dst_rtype connect slots_9.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[9].wakeup_ports[0].bits.uop.lrs3 connect slots_9.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[9].wakeup_ports[0].bits.uop.lrs2 connect slots_9.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[9].wakeup_ports[0].bits.uop.lrs1 connect slots_9.io.wakeup_ports[0].bits.uop.ldst, issue_slots[9].wakeup_ports[0].bits.uop.ldst connect slots_9.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_9.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[0].bits.uop.csr_cmd connect slots_9.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[0].bits.uop.flush_on_commit connect slots_9.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[9].wakeup_ports[0].bits.uop.is_unique connect slots_9.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[9].wakeup_ports[0].bits.uop.uses_stq connect slots_9.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[0].bits.uop.uses_ldq connect slots_9.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[9].wakeup_ports[0].bits.uop.mem_signed connect slots_9.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[9].wakeup_ports[0].bits.uop.mem_size connect slots_9.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[0].bits.uop.mem_cmd connect slots_9.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[9].wakeup_ports[0].bits.uop.exc_cause connect slots_9.io.wakeup_ports[0].bits.uop.exception, issue_slots[9].wakeup_ports[0].bits.uop.exception connect slots_9.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[0].bits.uop.stale_pdst connect slots_9.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[0].bits.uop.ppred_busy connect slots_9.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs3_busy connect slots_9.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs2_busy connect slots_9.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs1_busy connect slots_9.io.wakeup_ports[0].bits.uop.ppred, issue_slots[9].wakeup_ports[0].bits.uop.ppred connect slots_9.io.wakeup_ports[0].bits.uop.prs3, issue_slots[9].wakeup_ports[0].bits.uop.prs3 connect slots_9.io.wakeup_ports[0].bits.uop.prs2, issue_slots[9].wakeup_ports[0].bits.uop.prs2 connect slots_9.io.wakeup_ports[0].bits.uop.prs1, issue_slots[9].wakeup_ports[0].bits.uop.prs1 connect slots_9.io.wakeup_ports[0].bits.uop.pdst, issue_slots[9].wakeup_ports[0].bits.uop.pdst connect slots_9.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[0].bits.uop.rxq_idx connect slots_9.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[9].wakeup_ports[0].bits.uop.stq_idx connect slots_9.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[0].bits.uop.ldq_idx connect slots_9.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[9].wakeup_ports[0].bits.uop.rob_idx connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_9.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[9].wakeup_ports[0].bits.uop.op2_sel connect slots_9.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[9].wakeup_ports[0].bits.uop.op1_sel connect slots_9.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[9].wakeup_ports[0].bits.uop.imm_packed connect slots_9.io.wakeup_ports[0].bits.uop.pimm, issue_slots[9].wakeup_ports[0].bits.uop.pimm connect slots_9.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[9].wakeup_ports[0].bits.uop.imm_sel connect slots_9.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[9].wakeup_ports[0].bits.uop.imm_rename connect slots_9.io.wakeup_ports[0].bits.uop.taken, issue_slots[9].wakeup_ports[0].bits.uop.taken connect slots_9.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[9].wakeup_ports[0].bits.uop.pc_lob connect slots_9.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[9].wakeup_ports[0].bits.uop.edge_inst connect slots_9.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[0].bits.uop.ftq_idx connect slots_9.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[9].wakeup_ports[0].bits.uop.is_mov connect slots_9.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[9].wakeup_ports[0].bits.uop.is_rocc connect slots_9.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_9.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[9].wakeup_ports[0].bits.uop.is_eret connect slots_9.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[9].wakeup_ports[0].bits.uop.is_amo connect slots_9.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[9].wakeup_ports[0].bits.uop.is_sfence connect slots_9.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[9].wakeup_ports[0].bits.uop.is_fencei connect slots_9.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[9].wakeup_ports[0].bits.uop.is_fence connect slots_9.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[9].wakeup_ports[0].bits.uop.is_sfb connect slots_9.io.wakeup_ports[0].bits.uop.br_type, issue_slots[9].wakeup_ports[0].bits.uop.br_type connect slots_9.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[9].wakeup_ports[0].bits.uop.br_tag connect slots_9.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[9].wakeup_ports[0].bits.uop.br_mask connect slots_9.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[0].bits.uop.dis_col_sel connect slots_9.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_9.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_9.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_9.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_9.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[0] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[1] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[2] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[3] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[4] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[5] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[6] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[7] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[8] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[9] connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[0] connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[1] connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[2] connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[3] connect slots_9.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[9].wakeup_ports[0].bits.uop.debug_pc connect slots_9.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[9].wakeup_ports[0].bits.uop.is_rvc connect slots_9.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[9].wakeup_ports[0].bits.uop.debug_inst connect slots_9.io.wakeup_ports[0].bits.uop.inst, issue_slots[9].wakeup_ports[0].bits.uop.inst connect slots_9.io.wakeup_ports[0].valid, issue_slots[9].wakeup_ports[0].valid connect slots_9.io.wakeup_ports[1].bits.rebusy, issue_slots[9].wakeup_ports[1].bits.rebusy connect slots_9.io.wakeup_ports[1].bits.speculative_mask, issue_slots[9].wakeup_ports[1].bits.speculative_mask connect slots_9.io.wakeup_ports[1].bits.bypassable, issue_slots[9].wakeup_ports[1].bits.bypassable connect slots_9.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[1].bits.uop.debug_tsrc connect slots_9.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[1].bits.uop.debug_fsrc connect slots_9.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_9.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[1].bits.uop.bp_debug_if connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_9.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[9].wakeup_ports[1].bits.uop.fp_typ connect slots_9.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[9].wakeup_ports[1].bits.uop.fp_rm connect slots_9.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[9].wakeup_ports[1].bits.uop.fp_val connect slots_9.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[9].wakeup_ports[1].bits.uop.fcn_op connect slots_9.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[1].bits.uop.fcn_dw connect slots_9.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[9].wakeup_ports[1].bits.uop.frs3_en connect slots_9.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_9.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_9.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[1].bits.uop.dst_rtype connect slots_9.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[9].wakeup_ports[1].bits.uop.lrs3 connect slots_9.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[9].wakeup_ports[1].bits.uop.lrs2 connect slots_9.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[9].wakeup_ports[1].bits.uop.lrs1 connect slots_9.io.wakeup_ports[1].bits.uop.ldst, issue_slots[9].wakeup_ports[1].bits.uop.ldst connect slots_9.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_9.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[1].bits.uop.csr_cmd connect slots_9.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[1].bits.uop.flush_on_commit connect slots_9.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[9].wakeup_ports[1].bits.uop.is_unique connect slots_9.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[9].wakeup_ports[1].bits.uop.uses_stq connect slots_9.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[1].bits.uop.uses_ldq connect slots_9.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[9].wakeup_ports[1].bits.uop.mem_signed connect slots_9.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[9].wakeup_ports[1].bits.uop.mem_size connect slots_9.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[1].bits.uop.mem_cmd connect slots_9.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[9].wakeup_ports[1].bits.uop.exc_cause connect slots_9.io.wakeup_ports[1].bits.uop.exception, issue_slots[9].wakeup_ports[1].bits.uop.exception connect slots_9.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[1].bits.uop.stale_pdst connect slots_9.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[1].bits.uop.ppred_busy connect slots_9.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs3_busy connect slots_9.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs2_busy connect slots_9.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs1_busy connect slots_9.io.wakeup_ports[1].bits.uop.ppred, issue_slots[9].wakeup_ports[1].bits.uop.ppred connect slots_9.io.wakeup_ports[1].bits.uop.prs3, issue_slots[9].wakeup_ports[1].bits.uop.prs3 connect slots_9.io.wakeup_ports[1].bits.uop.prs2, issue_slots[9].wakeup_ports[1].bits.uop.prs2 connect slots_9.io.wakeup_ports[1].bits.uop.prs1, issue_slots[9].wakeup_ports[1].bits.uop.prs1 connect slots_9.io.wakeup_ports[1].bits.uop.pdst, issue_slots[9].wakeup_ports[1].bits.uop.pdst connect slots_9.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[1].bits.uop.rxq_idx connect slots_9.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[9].wakeup_ports[1].bits.uop.stq_idx connect slots_9.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[1].bits.uop.ldq_idx connect slots_9.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[9].wakeup_ports[1].bits.uop.rob_idx connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_9.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[9].wakeup_ports[1].bits.uop.op2_sel connect slots_9.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[9].wakeup_ports[1].bits.uop.op1_sel connect slots_9.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[9].wakeup_ports[1].bits.uop.imm_packed connect slots_9.io.wakeup_ports[1].bits.uop.pimm, issue_slots[9].wakeup_ports[1].bits.uop.pimm connect slots_9.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[9].wakeup_ports[1].bits.uop.imm_sel connect slots_9.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[9].wakeup_ports[1].bits.uop.imm_rename connect slots_9.io.wakeup_ports[1].bits.uop.taken, issue_slots[9].wakeup_ports[1].bits.uop.taken connect slots_9.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[9].wakeup_ports[1].bits.uop.pc_lob connect slots_9.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[9].wakeup_ports[1].bits.uop.edge_inst connect slots_9.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[1].bits.uop.ftq_idx connect slots_9.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[9].wakeup_ports[1].bits.uop.is_mov connect slots_9.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[9].wakeup_ports[1].bits.uop.is_rocc connect slots_9.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_9.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[9].wakeup_ports[1].bits.uop.is_eret connect slots_9.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[9].wakeup_ports[1].bits.uop.is_amo connect slots_9.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[9].wakeup_ports[1].bits.uop.is_sfence connect slots_9.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[9].wakeup_ports[1].bits.uop.is_fencei connect slots_9.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[9].wakeup_ports[1].bits.uop.is_fence connect slots_9.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[9].wakeup_ports[1].bits.uop.is_sfb connect slots_9.io.wakeup_ports[1].bits.uop.br_type, issue_slots[9].wakeup_ports[1].bits.uop.br_type connect slots_9.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[9].wakeup_ports[1].bits.uop.br_tag connect slots_9.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[9].wakeup_ports[1].bits.uop.br_mask connect slots_9.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[1].bits.uop.dis_col_sel connect slots_9.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_9.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_9.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_9.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_9.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[0] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[1] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[2] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[3] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[4] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[5] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[6] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[7] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[8] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[9] connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[0] connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[1] connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[2] connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[3] connect slots_9.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[9].wakeup_ports[1].bits.uop.debug_pc connect slots_9.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[9].wakeup_ports[1].bits.uop.is_rvc connect slots_9.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[9].wakeup_ports[1].bits.uop.debug_inst connect slots_9.io.wakeup_ports[1].bits.uop.inst, issue_slots[9].wakeup_ports[1].bits.uop.inst connect slots_9.io.wakeup_ports[1].valid, issue_slots[9].wakeup_ports[1].valid connect slots_9.io.wakeup_ports[2].bits.rebusy, issue_slots[9].wakeup_ports[2].bits.rebusy connect slots_9.io.wakeup_ports[2].bits.speculative_mask, issue_slots[9].wakeup_ports[2].bits.speculative_mask connect slots_9.io.wakeup_ports[2].bits.bypassable, issue_slots[9].wakeup_ports[2].bits.bypassable connect slots_9.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[2].bits.uop.debug_tsrc connect slots_9.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[2].bits.uop.debug_fsrc connect slots_9.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_9.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[2].bits.uop.bp_debug_if connect slots_9.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_9.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_9.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_9.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[9].wakeup_ports[2].bits.uop.fp_typ connect slots_9.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[9].wakeup_ports[2].bits.uop.fp_rm connect slots_9.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[9].wakeup_ports[2].bits.uop.fp_val connect slots_9.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[9].wakeup_ports[2].bits.uop.fcn_op connect slots_9.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[2].bits.uop.fcn_dw connect slots_9.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[9].wakeup_ports[2].bits.uop.frs3_en connect slots_9.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_9.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_9.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[2].bits.uop.dst_rtype connect slots_9.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[9].wakeup_ports[2].bits.uop.lrs3 connect slots_9.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[9].wakeup_ports[2].bits.uop.lrs2 connect slots_9.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[9].wakeup_ports[2].bits.uop.lrs1 connect slots_9.io.wakeup_ports[2].bits.uop.ldst, issue_slots[9].wakeup_ports[2].bits.uop.ldst connect slots_9.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_9.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[2].bits.uop.csr_cmd connect slots_9.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[2].bits.uop.flush_on_commit connect slots_9.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[9].wakeup_ports[2].bits.uop.is_unique connect slots_9.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[9].wakeup_ports[2].bits.uop.uses_stq connect slots_9.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[2].bits.uop.uses_ldq connect slots_9.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[9].wakeup_ports[2].bits.uop.mem_signed connect slots_9.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[9].wakeup_ports[2].bits.uop.mem_size connect slots_9.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[2].bits.uop.mem_cmd connect slots_9.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[9].wakeup_ports[2].bits.uop.exc_cause connect slots_9.io.wakeup_ports[2].bits.uop.exception, issue_slots[9].wakeup_ports[2].bits.uop.exception connect slots_9.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[2].bits.uop.stale_pdst connect slots_9.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[2].bits.uop.ppred_busy connect slots_9.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[2].bits.uop.prs3_busy connect slots_9.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[2].bits.uop.prs2_busy connect slots_9.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[2].bits.uop.prs1_busy connect slots_9.io.wakeup_ports[2].bits.uop.ppred, issue_slots[9].wakeup_ports[2].bits.uop.ppred connect slots_9.io.wakeup_ports[2].bits.uop.prs3, issue_slots[9].wakeup_ports[2].bits.uop.prs3 connect slots_9.io.wakeup_ports[2].bits.uop.prs2, issue_slots[9].wakeup_ports[2].bits.uop.prs2 connect slots_9.io.wakeup_ports[2].bits.uop.prs1, issue_slots[9].wakeup_ports[2].bits.uop.prs1 connect slots_9.io.wakeup_ports[2].bits.uop.pdst, issue_slots[9].wakeup_ports[2].bits.uop.pdst connect slots_9.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[2].bits.uop.rxq_idx connect slots_9.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[9].wakeup_ports[2].bits.uop.stq_idx connect slots_9.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[2].bits.uop.ldq_idx connect slots_9.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[9].wakeup_ports[2].bits.uop.rob_idx connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_9.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[9].wakeup_ports[2].bits.uop.op2_sel connect slots_9.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[9].wakeup_ports[2].bits.uop.op1_sel connect slots_9.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[9].wakeup_ports[2].bits.uop.imm_packed connect slots_9.io.wakeup_ports[2].bits.uop.pimm, issue_slots[9].wakeup_ports[2].bits.uop.pimm connect slots_9.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[9].wakeup_ports[2].bits.uop.imm_sel connect slots_9.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[9].wakeup_ports[2].bits.uop.imm_rename connect slots_9.io.wakeup_ports[2].bits.uop.taken, issue_slots[9].wakeup_ports[2].bits.uop.taken connect slots_9.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[9].wakeup_ports[2].bits.uop.pc_lob connect slots_9.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[9].wakeup_ports[2].bits.uop.edge_inst connect slots_9.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[2].bits.uop.ftq_idx connect slots_9.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[9].wakeup_ports[2].bits.uop.is_mov connect slots_9.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[9].wakeup_ports[2].bits.uop.is_rocc connect slots_9.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_9.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[9].wakeup_ports[2].bits.uop.is_eret connect slots_9.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[9].wakeup_ports[2].bits.uop.is_amo connect slots_9.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[9].wakeup_ports[2].bits.uop.is_sfence connect slots_9.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[9].wakeup_ports[2].bits.uop.is_fencei connect slots_9.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[9].wakeup_ports[2].bits.uop.is_fence connect slots_9.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[9].wakeup_ports[2].bits.uop.is_sfb connect slots_9.io.wakeup_ports[2].bits.uop.br_type, issue_slots[9].wakeup_ports[2].bits.uop.br_type connect slots_9.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[9].wakeup_ports[2].bits.uop.br_tag connect slots_9.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[9].wakeup_ports[2].bits.uop.br_mask connect slots_9.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[2].bits.uop.dis_col_sel connect slots_9.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_9.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_9.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_9.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_9.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_9.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_9.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_9.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[9].wakeup_ports[2].bits.uop.iw_issued connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[0] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[1] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[2] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[3] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[4] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[5] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[6] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[7] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[8] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[9] connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[0] connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[1] connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[2] connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[3] connect slots_9.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[9].wakeup_ports[2].bits.uop.debug_pc connect slots_9.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[9].wakeup_ports[2].bits.uop.is_rvc connect slots_9.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[9].wakeup_ports[2].bits.uop.debug_inst connect slots_9.io.wakeup_ports[2].bits.uop.inst, issue_slots[9].wakeup_ports[2].bits.uop.inst connect slots_9.io.wakeup_ports[2].valid, issue_slots[9].wakeup_ports[2].valid connect slots_9.io.wakeup_ports[3].bits.rebusy, issue_slots[9].wakeup_ports[3].bits.rebusy connect slots_9.io.wakeup_ports[3].bits.speculative_mask, issue_slots[9].wakeup_ports[3].bits.speculative_mask connect slots_9.io.wakeup_ports[3].bits.bypassable, issue_slots[9].wakeup_ports[3].bits.bypassable connect slots_9.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[3].bits.uop.debug_tsrc connect slots_9.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[3].bits.uop.debug_fsrc connect slots_9.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_9.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[3].bits.uop.bp_debug_if connect slots_9.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_9.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_9.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_9.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[9].wakeup_ports[3].bits.uop.fp_typ connect slots_9.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[9].wakeup_ports[3].bits.uop.fp_rm connect slots_9.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[9].wakeup_ports[3].bits.uop.fp_val connect slots_9.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[9].wakeup_ports[3].bits.uop.fcn_op connect slots_9.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[3].bits.uop.fcn_dw connect slots_9.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[9].wakeup_ports[3].bits.uop.frs3_en connect slots_9.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_9.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_9.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[3].bits.uop.dst_rtype connect slots_9.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[9].wakeup_ports[3].bits.uop.lrs3 connect slots_9.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[9].wakeup_ports[3].bits.uop.lrs2 connect slots_9.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[9].wakeup_ports[3].bits.uop.lrs1 connect slots_9.io.wakeup_ports[3].bits.uop.ldst, issue_slots[9].wakeup_ports[3].bits.uop.ldst connect slots_9.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_9.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[3].bits.uop.csr_cmd connect slots_9.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[3].bits.uop.flush_on_commit connect slots_9.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[9].wakeup_ports[3].bits.uop.is_unique connect slots_9.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[9].wakeup_ports[3].bits.uop.uses_stq connect slots_9.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[3].bits.uop.uses_ldq connect slots_9.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[9].wakeup_ports[3].bits.uop.mem_signed connect slots_9.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[9].wakeup_ports[3].bits.uop.mem_size connect slots_9.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[3].bits.uop.mem_cmd connect slots_9.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[9].wakeup_ports[3].bits.uop.exc_cause connect slots_9.io.wakeup_ports[3].bits.uop.exception, issue_slots[9].wakeup_ports[3].bits.uop.exception connect slots_9.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[3].bits.uop.stale_pdst connect slots_9.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[3].bits.uop.ppred_busy connect slots_9.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[3].bits.uop.prs3_busy connect slots_9.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[3].bits.uop.prs2_busy connect slots_9.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[3].bits.uop.prs1_busy connect slots_9.io.wakeup_ports[3].bits.uop.ppred, issue_slots[9].wakeup_ports[3].bits.uop.ppred connect slots_9.io.wakeup_ports[3].bits.uop.prs3, issue_slots[9].wakeup_ports[3].bits.uop.prs3 connect slots_9.io.wakeup_ports[3].bits.uop.prs2, issue_slots[9].wakeup_ports[3].bits.uop.prs2 connect slots_9.io.wakeup_ports[3].bits.uop.prs1, issue_slots[9].wakeup_ports[3].bits.uop.prs1 connect slots_9.io.wakeup_ports[3].bits.uop.pdst, issue_slots[9].wakeup_ports[3].bits.uop.pdst connect slots_9.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[3].bits.uop.rxq_idx connect slots_9.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[9].wakeup_ports[3].bits.uop.stq_idx connect slots_9.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[3].bits.uop.ldq_idx connect slots_9.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[9].wakeup_ports[3].bits.uop.rob_idx connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_9.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[9].wakeup_ports[3].bits.uop.op2_sel connect slots_9.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[9].wakeup_ports[3].bits.uop.op1_sel connect slots_9.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[9].wakeup_ports[3].bits.uop.imm_packed connect slots_9.io.wakeup_ports[3].bits.uop.pimm, issue_slots[9].wakeup_ports[3].bits.uop.pimm connect slots_9.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[9].wakeup_ports[3].bits.uop.imm_sel connect slots_9.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[9].wakeup_ports[3].bits.uop.imm_rename connect slots_9.io.wakeup_ports[3].bits.uop.taken, issue_slots[9].wakeup_ports[3].bits.uop.taken connect slots_9.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[9].wakeup_ports[3].bits.uop.pc_lob connect slots_9.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[9].wakeup_ports[3].bits.uop.edge_inst connect slots_9.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[3].bits.uop.ftq_idx connect slots_9.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[9].wakeup_ports[3].bits.uop.is_mov connect slots_9.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[9].wakeup_ports[3].bits.uop.is_rocc connect slots_9.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_9.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[9].wakeup_ports[3].bits.uop.is_eret connect slots_9.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[9].wakeup_ports[3].bits.uop.is_amo connect slots_9.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[9].wakeup_ports[3].bits.uop.is_sfence connect slots_9.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[9].wakeup_ports[3].bits.uop.is_fencei connect slots_9.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[9].wakeup_ports[3].bits.uop.is_fence connect slots_9.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[9].wakeup_ports[3].bits.uop.is_sfb connect slots_9.io.wakeup_ports[3].bits.uop.br_type, issue_slots[9].wakeup_ports[3].bits.uop.br_type connect slots_9.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[9].wakeup_ports[3].bits.uop.br_tag connect slots_9.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[9].wakeup_ports[3].bits.uop.br_mask connect slots_9.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[3].bits.uop.dis_col_sel connect slots_9.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_9.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_9.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_9.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_9.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_9.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_9.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_9.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[9].wakeup_ports[3].bits.uop.iw_issued connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[0] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[1] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[2] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[3] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[4] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[5] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[6] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[7] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[8] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[9] connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[0] connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[1] connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[2] connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[3] connect slots_9.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[9].wakeup_ports[3].bits.uop.debug_pc connect slots_9.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[9].wakeup_ports[3].bits.uop.is_rvc connect slots_9.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[9].wakeup_ports[3].bits.uop.debug_inst connect slots_9.io.wakeup_ports[3].bits.uop.inst, issue_slots[9].wakeup_ports[3].bits.uop.inst connect slots_9.io.wakeup_ports[3].valid, issue_slots[9].wakeup_ports[3].valid connect slots_9.io.wakeup_ports[4].bits.rebusy, issue_slots[9].wakeup_ports[4].bits.rebusy connect slots_9.io.wakeup_ports[4].bits.speculative_mask, issue_slots[9].wakeup_ports[4].bits.speculative_mask connect slots_9.io.wakeup_ports[4].bits.bypassable, issue_slots[9].wakeup_ports[4].bits.bypassable connect slots_9.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[4].bits.uop.debug_tsrc connect slots_9.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[4].bits.uop.debug_fsrc connect slots_9.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_9.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[4].bits.uop.bp_debug_if connect slots_9.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_9.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_9.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_9.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[9].wakeup_ports[4].bits.uop.fp_typ connect slots_9.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[9].wakeup_ports[4].bits.uop.fp_rm connect slots_9.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[9].wakeup_ports[4].bits.uop.fp_val connect slots_9.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[9].wakeup_ports[4].bits.uop.fcn_op connect slots_9.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[4].bits.uop.fcn_dw connect slots_9.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[9].wakeup_ports[4].bits.uop.frs3_en connect slots_9.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_9.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_9.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[4].bits.uop.dst_rtype connect slots_9.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[9].wakeup_ports[4].bits.uop.lrs3 connect slots_9.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[9].wakeup_ports[4].bits.uop.lrs2 connect slots_9.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[9].wakeup_ports[4].bits.uop.lrs1 connect slots_9.io.wakeup_ports[4].bits.uop.ldst, issue_slots[9].wakeup_ports[4].bits.uop.ldst connect slots_9.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_9.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[4].bits.uop.csr_cmd connect slots_9.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[4].bits.uop.flush_on_commit connect slots_9.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[9].wakeup_ports[4].bits.uop.is_unique connect slots_9.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[9].wakeup_ports[4].bits.uop.uses_stq connect slots_9.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[4].bits.uop.uses_ldq connect slots_9.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[9].wakeup_ports[4].bits.uop.mem_signed connect slots_9.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[9].wakeup_ports[4].bits.uop.mem_size connect slots_9.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[4].bits.uop.mem_cmd connect slots_9.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[9].wakeup_ports[4].bits.uop.exc_cause connect slots_9.io.wakeup_ports[4].bits.uop.exception, issue_slots[9].wakeup_ports[4].bits.uop.exception connect slots_9.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[4].bits.uop.stale_pdst connect slots_9.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[4].bits.uop.ppred_busy connect slots_9.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[4].bits.uop.prs3_busy connect slots_9.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[4].bits.uop.prs2_busy connect slots_9.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[4].bits.uop.prs1_busy connect slots_9.io.wakeup_ports[4].bits.uop.ppred, issue_slots[9].wakeup_ports[4].bits.uop.ppred connect slots_9.io.wakeup_ports[4].bits.uop.prs3, issue_slots[9].wakeup_ports[4].bits.uop.prs3 connect slots_9.io.wakeup_ports[4].bits.uop.prs2, issue_slots[9].wakeup_ports[4].bits.uop.prs2 connect slots_9.io.wakeup_ports[4].bits.uop.prs1, issue_slots[9].wakeup_ports[4].bits.uop.prs1 connect slots_9.io.wakeup_ports[4].bits.uop.pdst, issue_slots[9].wakeup_ports[4].bits.uop.pdst connect slots_9.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[4].bits.uop.rxq_idx connect slots_9.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[9].wakeup_ports[4].bits.uop.stq_idx connect slots_9.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[4].bits.uop.ldq_idx connect slots_9.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[9].wakeup_ports[4].bits.uop.rob_idx connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_9.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[9].wakeup_ports[4].bits.uop.op2_sel connect slots_9.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[9].wakeup_ports[4].bits.uop.op1_sel connect slots_9.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[9].wakeup_ports[4].bits.uop.imm_packed connect slots_9.io.wakeup_ports[4].bits.uop.pimm, issue_slots[9].wakeup_ports[4].bits.uop.pimm connect slots_9.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[9].wakeup_ports[4].bits.uop.imm_sel connect slots_9.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[9].wakeup_ports[4].bits.uop.imm_rename connect slots_9.io.wakeup_ports[4].bits.uop.taken, issue_slots[9].wakeup_ports[4].bits.uop.taken connect slots_9.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[9].wakeup_ports[4].bits.uop.pc_lob connect slots_9.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[9].wakeup_ports[4].bits.uop.edge_inst connect slots_9.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[4].bits.uop.ftq_idx connect slots_9.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[9].wakeup_ports[4].bits.uop.is_mov connect slots_9.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[9].wakeup_ports[4].bits.uop.is_rocc connect slots_9.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_9.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[9].wakeup_ports[4].bits.uop.is_eret connect slots_9.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[9].wakeup_ports[4].bits.uop.is_amo connect slots_9.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[9].wakeup_ports[4].bits.uop.is_sfence connect slots_9.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[9].wakeup_ports[4].bits.uop.is_fencei connect slots_9.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[9].wakeup_ports[4].bits.uop.is_fence connect slots_9.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[9].wakeup_ports[4].bits.uop.is_sfb connect slots_9.io.wakeup_ports[4].bits.uop.br_type, issue_slots[9].wakeup_ports[4].bits.uop.br_type connect slots_9.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[9].wakeup_ports[4].bits.uop.br_tag connect slots_9.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[9].wakeup_ports[4].bits.uop.br_mask connect slots_9.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[4].bits.uop.dis_col_sel connect slots_9.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_9.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_9.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_9.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_9.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_9.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_9.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_9.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[9].wakeup_ports[4].bits.uop.iw_issued connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[0] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[1] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[2] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[3] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[4] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[5] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[6] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[7] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[8] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[9] connect slots_9.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[4].bits.uop.iq_type[0] connect slots_9.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[4].bits.uop.iq_type[1] connect slots_9.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[4].bits.uop.iq_type[2] connect slots_9.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[4].bits.uop.iq_type[3] connect slots_9.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[9].wakeup_ports[4].bits.uop.debug_pc connect slots_9.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[9].wakeup_ports[4].bits.uop.is_rvc connect slots_9.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[9].wakeup_ports[4].bits.uop.debug_inst connect slots_9.io.wakeup_ports[4].bits.uop.inst, issue_slots[9].wakeup_ports[4].bits.uop.inst connect slots_9.io.wakeup_ports[4].valid, issue_slots[9].wakeup_ports[4].valid connect slots_9.io.squash_grant, issue_slots[9].squash_grant connect slots_9.io.clear, issue_slots[9].clear connect slots_9.io.kill, issue_slots[9].kill connect slots_9.io.brupdate.b2.target_offset, issue_slots[9].brupdate.b2.target_offset connect slots_9.io.brupdate.b2.jalr_target, issue_slots[9].brupdate.b2.jalr_target connect slots_9.io.brupdate.b2.pc_sel, issue_slots[9].brupdate.b2.pc_sel connect slots_9.io.brupdate.b2.cfi_type, issue_slots[9].brupdate.b2.cfi_type connect slots_9.io.brupdate.b2.taken, issue_slots[9].brupdate.b2.taken connect slots_9.io.brupdate.b2.mispredict, issue_slots[9].brupdate.b2.mispredict connect slots_9.io.brupdate.b2.uop.debug_tsrc, issue_slots[9].brupdate.b2.uop.debug_tsrc connect slots_9.io.brupdate.b2.uop.debug_fsrc, issue_slots[9].brupdate.b2.uop.debug_fsrc connect slots_9.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[9].brupdate.b2.uop.bp_xcpt_if connect slots_9.io.brupdate.b2.uop.bp_debug_if, issue_slots[9].brupdate.b2.uop.bp_debug_if connect slots_9.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[9].brupdate.b2.uop.xcpt_ma_if connect slots_9.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[9].brupdate.b2.uop.xcpt_ae_if connect slots_9.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[9].brupdate.b2.uop.xcpt_pf_if connect slots_9.io.brupdate.b2.uop.fp_typ, issue_slots[9].brupdate.b2.uop.fp_typ connect slots_9.io.brupdate.b2.uop.fp_rm, issue_slots[9].brupdate.b2.uop.fp_rm connect slots_9.io.brupdate.b2.uop.fp_val, issue_slots[9].brupdate.b2.uop.fp_val connect slots_9.io.brupdate.b2.uop.fcn_op, issue_slots[9].brupdate.b2.uop.fcn_op connect slots_9.io.brupdate.b2.uop.fcn_dw, issue_slots[9].brupdate.b2.uop.fcn_dw connect slots_9.io.brupdate.b2.uop.frs3_en, issue_slots[9].brupdate.b2.uop.frs3_en connect slots_9.io.brupdate.b2.uop.lrs2_rtype, issue_slots[9].brupdate.b2.uop.lrs2_rtype connect slots_9.io.brupdate.b2.uop.lrs1_rtype, issue_slots[9].brupdate.b2.uop.lrs1_rtype connect slots_9.io.brupdate.b2.uop.dst_rtype, issue_slots[9].brupdate.b2.uop.dst_rtype connect slots_9.io.brupdate.b2.uop.lrs3, issue_slots[9].brupdate.b2.uop.lrs3 connect slots_9.io.brupdate.b2.uop.lrs2, issue_slots[9].brupdate.b2.uop.lrs2 connect slots_9.io.brupdate.b2.uop.lrs1, issue_slots[9].brupdate.b2.uop.lrs1 connect slots_9.io.brupdate.b2.uop.ldst, issue_slots[9].brupdate.b2.uop.ldst connect slots_9.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[9].brupdate.b2.uop.ldst_is_rs1 connect slots_9.io.brupdate.b2.uop.csr_cmd, issue_slots[9].brupdate.b2.uop.csr_cmd connect slots_9.io.brupdate.b2.uop.flush_on_commit, issue_slots[9].brupdate.b2.uop.flush_on_commit connect slots_9.io.brupdate.b2.uop.is_unique, issue_slots[9].brupdate.b2.uop.is_unique connect slots_9.io.brupdate.b2.uop.uses_stq, issue_slots[9].brupdate.b2.uop.uses_stq connect slots_9.io.brupdate.b2.uop.uses_ldq, issue_slots[9].brupdate.b2.uop.uses_ldq connect slots_9.io.brupdate.b2.uop.mem_signed, issue_slots[9].brupdate.b2.uop.mem_signed connect slots_9.io.brupdate.b2.uop.mem_size, issue_slots[9].brupdate.b2.uop.mem_size connect slots_9.io.brupdate.b2.uop.mem_cmd, issue_slots[9].brupdate.b2.uop.mem_cmd connect slots_9.io.brupdate.b2.uop.exc_cause, issue_slots[9].brupdate.b2.uop.exc_cause connect slots_9.io.brupdate.b2.uop.exception, issue_slots[9].brupdate.b2.uop.exception connect slots_9.io.brupdate.b2.uop.stale_pdst, issue_slots[9].brupdate.b2.uop.stale_pdst connect slots_9.io.brupdate.b2.uop.ppred_busy, issue_slots[9].brupdate.b2.uop.ppred_busy connect slots_9.io.brupdate.b2.uop.prs3_busy, issue_slots[9].brupdate.b2.uop.prs3_busy connect slots_9.io.brupdate.b2.uop.prs2_busy, issue_slots[9].brupdate.b2.uop.prs2_busy connect slots_9.io.brupdate.b2.uop.prs1_busy, issue_slots[9].brupdate.b2.uop.prs1_busy connect slots_9.io.brupdate.b2.uop.ppred, issue_slots[9].brupdate.b2.uop.ppred connect slots_9.io.brupdate.b2.uop.prs3, issue_slots[9].brupdate.b2.uop.prs3 connect slots_9.io.brupdate.b2.uop.prs2, issue_slots[9].brupdate.b2.uop.prs2 connect slots_9.io.brupdate.b2.uop.prs1, issue_slots[9].brupdate.b2.uop.prs1 connect slots_9.io.brupdate.b2.uop.pdst, issue_slots[9].brupdate.b2.uop.pdst connect slots_9.io.brupdate.b2.uop.rxq_idx, issue_slots[9].brupdate.b2.uop.rxq_idx connect slots_9.io.brupdate.b2.uop.stq_idx, issue_slots[9].brupdate.b2.uop.stq_idx connect slots_9.io.brupdate.b2.uop.ldq_idx, issue_slots[9].brupdate.b2.uop.ldq_idx connect slots_9.io.brupdate.b2.uop.rob_idx, issue_slots[9].brupdate.b2.uop.rob_idx connect slots_9.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[9].brupdate.b2.uop.fp_ctrl.vec connect slots_9.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[9].brupdate.b2.uop.fp_ctrl.wflags connect slots_9.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[9].brupdate.b2.uop.fp_ctrl.sqrt connect slots_9.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[9].brupdate.b2.uop.fp_ctrl.div connect slots_9.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[9].brupdate.b2.uop.fp_ctrl.fma connect slots_9.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[9].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_9.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[9].brupdate.b2.uop.fp_ctrl.toint connect slots_9.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[9].brupdate.b2.uop.fp_ctrl.fromint connect slots_9.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_9.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_9.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[9].brupdate.b2.uop.fp_ctrl.swap23 connect slots_9.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[9].brupdate.b2.uop.fp_ctrl.swap12 connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren3 connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren2 connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren1 connect slots_9.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[9].brupdate.b2.uop.fp_ctrl.wen connect slots_9.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[9].brupdate.b2.uop.fp_ctrl.ldst connect slots_9.io.brupdate.b2.uop.op2_sel, issue_slots[9].brupdate.b2.uop.op2_sel connect slots_9.io.brupdate.b2.uop.op1_sel, issue_slots[9].brupdate.b2.uop.op1_sel connect slots_9.io.brupdate.b2.uop.imm_packed, issue_slots[9].brupdate.b2.uop.imm_packed connect slots_9.io.brupdate.b2.uop.pimm, issue_slots[9].brupdate.b2.uop.pimm connect slots_9.io.brupdate.b2.uop.imm_sel, issue_slots[9].brupdate.b2.uop.imm_sel connect slots_9.io.brupdate.b2.uop.imm_rename, issue_slots[9].brupdate.b2.uop.imm_rename connect slots_9.io.brupdate.b2.uop.taken, issue_slots[9].brupdate.b2.uop.taken connect slots_9.io.brupdate.b2.uop.pc_lob, issue_slots[9].brupdate.b2.uop.pc_lob connect slots_9.io.brupdate.b2.uop.edge_inst, issue_slots[9].brupdate.b2.uop.edge_inst connect slots_9.io.brupdate.b2.uop.ftq_idx, issue_slots[9].brupdate.b2.uop.ftq_idx connect slots_9.io.brupdate.b2.uop.is_mov, issue_slots[9].brupdate.b2.uop.is_mov connect slots_9.io.brupdate.b2.uop.is_rocc, issue_slots[9].brupdate.b2.uop.is_rocc connect slots_9.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[9].brupdate.b2.uop.is_sys_pc2epc connect slots_9.io.brupdate.b2.uop.is_eret, issue_slots[9].brupdate.b2.uop.is_eret connect slots_9.io.brupdate.b2.uop.is_amo, issue_slots[9].brupdate.b2.uop.is_amo connect slots_9.io.brupdate.b2.uop.is_sfence, issue_slots[9].brupdate.b2.uop.is_sfence connect slots_9.io.brupdate.b2.uop.is_fencei, issue_slots[9].brupdate.b2.uop.is_fencei connect slots_9.io.brupdate.b2.uop.is_fence, issue_slots[9].brupdate.b2.uop.is_fence connect slots_9.io.brupdate.b2.uop.is_sfb, issue_slots[9].brupdate.b2.uop.is_sfb connect slots_9.io.brupdate.b2.uop.br_type, issue_slots[9].brupdate.b2.uop.br_type connect slots_9.io.brupdate.b2.uop.br_tag, issue_slots[9].brupdate.b2.uop.br_tag connect slots_9.io.brupdate.b2.uop.br_mask, issue_slots[9].brupdate.b2.uop.br_mask connect slots_9.io.brupdate.b2.uop.dis_col_sel, issue_slots[9].brupdate.b2.uop.dis_col_sel connect slots_9.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p3_bypass_hint connect slots_9.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p2_bypass_hint connect slots_9.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p1_bypass_hint connect slots_9.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[9].brupdate.b2.uop.iw_p2_speculative_child connect slots_9.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[9].brupdate.b2.uop.iw_p1_speculative_child connect slots_9.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[9].brupdate.b2.uop.iw_issued_partial_dgen connect slots_9.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[9].brupdate.b2.uop.iw_issued_partial_agen connect slots_9.io.brupdate.b2.uop.iw_issued, issue_slots[9].brupdate.b2.uop.iw_issued connect slots_9.io.brupdate.b2.uop.fu_code[0], issue_slots[9].brupdate.b2.uop.fu_code[0] connect slots_9.io.brupdate.b2.uop.fu_code[1], issue_slots[9].brupdate.b2.uop.fu_code[1] connect slots_9.io.brupdate.b2.uop.fu_code[2], issue_slots[9].brupdate.b2.uop.fu_code[2] connect slots_9.io.brupdate.b2.uop.fu_code[3], issue_slots[9].brupdate.b2.uop.fu_code[3] connect slots_9.io.brupdate.b2.uop.fu_code[4], issue_slots[9].brupdate.b2.uop.fu_code[4] connect slots_9.io.brupdate.b2.uop.fu_code[5], issue_slots[9].brupdate.b2.uop.fu_code[5] connect slots_9.io.brupdate.b2.uop.fu_code[6], issue_slots[9].brupdate.b2.uop.fu_code[6] connect slots_9.io.brupdate.b2.uop.fu_code[7], issue_slots[9].brupdate.b2.uop.fu_code[7] connect slots_9.io.brupdate.b2.uop.fu_code[8], issue_slots[9].brupdate.b2.uop.fu_code[8] connect slots_9.io.brupdate.b2.uop.fu_code[9], issue_slots[9].brupdate.b2.uop.fu_code[9] connect slots_9.io.brupdate.b2.uop.iq_type[0], issue_slots[9].brupdate.b2.uop.iq_type[0] connect slots_9.io.brupdate.b2.uop.iq_type[1], issue_slots[9].brupdate.b2.uop.iq_type[1] connect slots_9.io.brupdate.b2.uop.iq_type[2], issue_slots[9].brupdate.b2.uop.iq_type[2] connect slots_9.io.brupdate.b2.uop.iq_type[3], issue_slots[9].brupdate.b2.uop.iq_type[3] connect slots_9.io.brupdate.b2.uop.debug_pc, issue_slots[9].brupdate.b2.uop.debug_pc connect slots_9.io.brupdate.b2.uop.is_rvc, issue_slots[9].brupdate.b2.uop.is_rvc connect slots_9.io.brupdate.b2.uop.debug_inst, issue_slots[9].brupdate.b2.uop.debug_inst connect slots_9.io.brupdate.b2.uop.inst, issue_slots[9].brupdate.b2.uop.inst connect slots_9.io.brupdate.b1.mispredict_mask, issue_slots[9].brupdate.b1.mispredict_mask connect slots_9.io.brupdate.b1.resolve_mask, issue_slots[9].brupdate.b1.resolve_mask connect issue_slots[9].out_uop.debug_tsrc, slots_9.io.out_uop.debug_tsrc connect issue_slots[9].out_uop.debug_fsrc, slots_9.io.out_uop.debug_fsrc connect issue_slots[9].out_uop.bp_xcpt_if, slots_9.io.out_uop.bp_xcpt_if connect issue_slots[9].out_uop.bp_debug_if, slots_9.io.out_uop.bp_debug_if connect issue_slots[9].out_uop.xcpt_ma_if, slots_9.io.out_uop.xcpt_ma_if connect issue_slots[9].out_uop.xcpt_ae_if, slots_9.io.out_uop.xcpt_ae_if connect issue_slots[9].out_uop.xcpt_pf_if, slots_9.io.out_uop.xcpt_pf_if connect issue_slots[9].out_uop.fp_typ, slots_9.io.out_uop.fp_typ connect issue_slots[9].out_uop.fp_rm, slots_9.io.out_uop.fp_rm connect issue_slots[9].out_uop.fp_val, slots_9.io.out_uop.fp_val connect issue_slots[9].out_uop.fcn_op, slots_9.io.out_uop.fcn_op connect issue_slots[9].out_uop.fcn_dw, slots_9.io.out_uop.fcn_dw connect issue_slots[9].out_uop.frs3_en, slots_9.io.out_uop.frs3_en connect issue_slots[9].out_uop.lrs2_rtype, slots_9.io.out_uop.lrs2_rtype connect issue_slots[9].out_uop.lrs1_rtype, slots_9.io.out_uop.lrs1_rtype connect issue_slots[9].out_uop.dst_rtype, slots_9.io.out_uop.dst_rtype connect issue_slots[9].out_uop.lrs3, slots_9.io.out_uop.lrs3 connect issue_slots[9].out_uop.lrs2, slots_9.io.out_uop.lrs2 connect issue_slots[9].out_uop.lrs1, slots_9.io.out_uop.lrs1 connect issue_slots[9].out_uop.ldst, slots_9.io.out_uop.ldst connect issue_slots[9].out_uop.ldst_is_rs1, slots_9.io.out_uop.ldst_is_rs1 connect issue_slots[9].out_uop.csr_cmd, slots_9.io.out_uop.csr_cmd connect issue_slots[9].out_uop.flush_on_commit, slots_9.io.out_uop.flush_on_commit connect issue_slots[9].out_uop.is_unique, slots_9.io.out_uop.is_unique connect issue_slots[9].out_uop.uses_stq, slots_9.io.out_uop.uses_stq connect issue_slots[9].out_uop.uses_ldq, slots_9.io.out_uop.uses_ldq connect issue_slots[9].out_uop.mem_signed, slots_9.io.out_uop.mem_signed connect issue_slots[9].out_uop.mem_size, slots_9.io.out_uop.mem_size connect issue_slots[9].out_uop.mem_cmd, slots_9.io.out_uop.mem_cmd connect issue_slots[9].out_uop.exc_cause, slots_9.io.out_uop.exc_cause connect issue_slots[9].out_uop.exception, slots_9.io.out_uop.exception connect issue_slots[9].out_uop.stale_pdst, slots_9.io.out_uop.stale_pdst connect issue_slots[9].out_uop.ppred_busy, slots_9.io.out_uop.ppred_busy connect issue_slots[9].out_uop.prs3_busy, slots_9.io.out_uop.prs3_busy connect issue_slots[9].out_uop.prs2_busy, slots_9.io.out_uop.prs2_busy connect issue_slots[9].out_uop.prs1_busy, slots_9.io.out_uop.prs1_busy connect issue_slots[9].out_uop.ppred, slots_9.io.out_uop.ppred connect issue_slots[9].out_uop.prs3, slots_9.io.out_uop.prs3 connect issue_slots[9].out_uop.prs2, slots_9.io.out_uop.prs2 connect issue_slots[9].out_uop.prs1, slots_9.io.out_uop.prs1 connect issue_slots[9].out_uop.pdst, slots_9.io.out_uop.pdst connect issue_slots[9].out_uop.rxq_idx, slots_9.io.out_uop.rxq_idx connect issue_slots[9].out_uop.stq_idx, slots_9.io.out_uop.stq_idx connect issue_slots[9].out_uop.ldq_idx, slots_9.io.out_uop.ldq_idx connect issue_slots[9].out_uop.rob_idx, slots_9.io.out_uop.rob_idx connect issue_slots[9].out_uop.fp_ctrl.vec, slots_9.io.out_uop.fp_ctrl.vec connect issue_slots[9].out_uop.fp_ctrl.wflags, slots_9.io.out_uop.fp_ctrl.wflags connect issue_slots[9].out_uop.fp_ctrl.sqrt, slots_9.io.out_uop.fp_ctrl.sqrt connect issue_slots[9].out_uop.fp_ctrl.div, slots_9.io.out_uop.fp_ctrl.div connect issue_slots[9].out_uop.fp_ctrl.fma, slots_9.io.out_uop.fp_ctrl.fma connect issue_slots[9].out_uop.fp_ctrl.fastpipe, slots_9.io.out_uop.fp_ctrl.fastpipe connect issue_slots[9].out_uop.fp_ctrl.toint, slots_9.io.out_uop.fp_ctrl.toint connect issue_slots[9].out_uop.fp_ctrl.fromint, slots_9.io.out_uop.fp_ctrl.fromint connect issue_slots[9].out_uop.fp_ctrl.typeTagOut, slots_9.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[9].out_uop.fp_ctrl.typeTagIn, slots_9.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[9].out_uop.fp_ctrl.swap23, slots_9.io.out_uop.fp_ctrl.swap23 connect issue_slots[9].out_uop.fp_ctrl.swap12, slots_9.io.out_uop.fp_ctrl.swap12 connect issue_slots[9].out_uop.fp_ctrl.ren3, slots_9.io.out_uop.fp_ctrl.ren3 connect issue_slots[9].out_uop.fp_ctrl.ren2, slots_9.io.out_uop.fp_ctrl.ren2 connect issue_slots[9].out_uop.fp_ctrl.ren1, slots_9.io.out_uop.fp_ctrl.ren1 connect issue_slots[9].out_uop.fp_ctrl.wen, slots_9.io.out_uop.fp_ctrl.wen connect issue_slots[9].out_uop.fp_ctrl.ldst, slots_9.io.out_uop.fp_ctrl.ldst connect issue_slots[9].out_uop.op2_sel, slots_9.io.out_uop.op2_sel connect issue_slots[9].out_uop.op1_sel, slots_9.io.out_uop.op1_sel connect issue_slots[9].out_uop.imm_packed, slots_9.io.out_uop.imm_packed connect issue_slots[9].out_uop.pimm, slots_9.io.out_uop.pimm connect issue_slots[9].out_uop.imm_sel, slots_9.io.out_uop.imm_sel connect issue_slots[9].out_uop.imm_rename, slots_9.io.out_uop.imm_rename connect issue_slots[9].out_uop.taken, slots_9.io.out_uop.taken connect issue_slots[9].out_uop.pc_lob, slots_9.io.out_uop.pc_lob connect issue_slots[9].out_uop.edge_inst, slots_9.io.out_uop.edge_inst connect issue_slots[9].out_uop.ftq_idx, slots_9.io.out_uop.ftq_idx connect issue_slots[9].out_uop.is_mov, slots_9.io.out_uop.is_mov connect issue_slots[9].out_uop.is_rocc, slots_9.io.out_uop.is_rocc connect issue_slots[9].out_uop.is_sys_pc2epc, slots_9.io.out_uop.is_sys_pc2epc connect issue_slots[9].out_uop.is_eret, slots_9.io.out_uop.is_eret connect issue_slots[9].out_uop.is_amo, slots_9.io.out_uop.is_amo connect issue_slots[9].out_uop.is_sfence, slots_9.io.out_uop.is_sfence connect issue_slots[9].out_uop.is_fencei, slots_9.io.out_uop.is_fencei connect issue_slots[9].out_uop.is_fence, slots_9.io.out_uop.is_fence connect issue_slots[9].out_uop.is_sfb, slots_9.io.out_uop.is_sfb connect issue_slots[9].out_uop.br_type, slots_9.io.out_uop.br_type connect issue_slots[9].out_uop.br_tag, slots_9.io.out_uop.br_tag connect issue_slots[9].out_uop.br_mask, slots_9.io.out_uop.br_mask connect issue_slots[9].out_uop.dis_col_sel, slots_9.io.out_uop.dis_col_sel connect issue_slots[9].out_uop.iw_p3_bypass_hint, slots_9.io.out_uop.iw_p3_bypass_hint connect issue_slots[9].out_uop.iw_p2_bypass_hint, slots_9.io.out_uop.iw_p2_bypass_hint connect issue_slots[9].out_uop.iw_p1_bypass_hint, slots_9.io.out_uop.iw_p1_bypass_hint connect issue_slots[9].out_uop.iw_p2_speculative_child, slots_9.io.out_uop.iw_p2_speculative_child connect issue_slots[9].out_uop.iw_p1_speculative_child, slots_9.io.out_uop.iw_p1_speculative_child connect issue_slots[9].out_uop.iw_issued_partial_dgen, slots_9.io.out_uop.iw_issued_partial_dgen connect issue_slots[9].out_uop.iw_issued_partial_agen, slots_9.io.out_uop.iw_issued_partial_agen connect issue_slots[9].out_uop.iw_issued, slots_9.io.out_uop.iw_issued connect issue_slots[9].out_uop.fu_code[0], slots_9.io.out_uop.fu_code[0] connect issue_slots[9].out_uop.fu_code[1], slots_9.io.out_uop.fu_code[1] connect issue_slots[9].out_uop.fu_code[2], slots_9.io.out_uop.fu_code[2] connect issue_slots[9].out_uop.fu_code[3], slots_9.io.out_uop.fu_code[3] connect issue_slots[9].out_uop.fu_code[4], slots_9.io.out_uop.fu_code[4] connect issue_slots[9].out_uop.fu_code[5], slots_9.io.out_uop.fu_code[5] connect issue_slots[9].out_uop.fu_code[6], slots_9.io.out_uop.fu_code[6] connect issue_slots[9].out_uop.fu_code[7], slots_9.io.out_uop.fu_code[7] connect issue_slots[9].out_uop.fu_code[8], slots_9.io.out_uop.fu_code[8] connect issue_slots[9].out_uop.fu_code[9], slots_9.io.out_uop.fu_code[9] connect issue_slots[9].out_uop.iq_type[0], slots_9.io.out_uop.iq_type[0] connect issue_slots[9].out_uop.iq_type[1], slots_9.io.out_uop.iq_type[1] connect issue_slots[9].out_uop.iq_type[2], slots_9.io.out_uop.iq_type[2] connect issue_slots[9].out_uop.iq_type[3], slots_9.io.out_uop.iq_type[3] connect issue_slots[9].out_uop.debug_pc, slots_9.io.out_uop.debug_pc connect issue_slots[9].out_uop.is_rvc, slots_9.io.out_uop.is_rvc connect issue_slots[9].out_uop.debug_inst, slots_9.io.out_uop.debug_inst connect issue_slots[9].out_uop.inst, slots_9.io.out_uop.inst connect slots_9.io.in_uop.bits.debug_tsrc, issue_slots[9].in_uop.bits.debug_tsrc connect slots_9.io.in_uop.bits.debug_fsrc, issue_slots[9].in_uop.bits.debug_fsrc connect slots_9.io.in_uop.bits.bp_xcpt_if, issue_slots[9].in_uop.bits.bp_xcpt_if connect slots_9.io.in_uop.bits.bp_debug_if, issue_slots[9].in_uop.bits.bp_debug_if connect slots_9.io.in_uop.bits.xcpt_ma_if, issue_slots[9].in_uop.bits.xcpt_ma_if connect slots_9.io.in_uop.bits.xcpt_ae_if, issue_slots[9].in_uop.bits.xcpt_ae_if connect slots_9.io.in_uop.bits.xcpt_pf_if, issue_slots[9].in_uop.bits.xcpt_pf_if connect slots_9.io.in_uop.bits.fp_typ, issue_slots[9].in_uop.bits.fp_typ connect slots_9.io.in_uop.bits.fp_rm, issue_slots[9].in_uop.bits.fp_rm connect slots_9.io.in_uop.bits.fp_val, issue_slots[9].in_uop.bits.fp_val connect slots_9.io.in_uop.bits.fcn_op, issue_slots[9].in_uop.bits.fcn_op connect slots_9.io.in_uop.bits.fcn_dw, issue_slots[9].in_uop.bits.fcn_dw connect slots_9.io.in_uop.bits.frs3_en, issue_slots[9].in_uop.bits.frs3_en connect slots_9.io.in_uop.bits.lrs2_rtype, issue_slots[9].in_uop.bits.lrs2_rtype connect slots_9.io.in_uop.bits.lrs1_rtype, issue_slots[9].in_uop.bits.lrs1_rtype connect slots_9.io.in_uop.bits.dst_rtype, issue_slots[9].in_uop.bits.dst_rtype connect slots_9.io.in_uop.bits.lrs3, issue_slots[9].in_uop.bits.lrs3 connect slots_9.io.in_uop.bits.lrs2, issue_slots[9].in_uop.bits.lrs2 connect slots_9.io.in_uop.bits.lrs1, issue_slots[9].in_uop.bits.lrs1 connect slots_9.io.in_uop.bits.ldst, issue_slots[9].in_uop.bits.ldst connect slots_9.io.in_uop.bits.ldst_is_rs1, issue_slots[9].in_uop.bits.ldst_is_rs1 connect slots_9.io.in_uop.bits.csr_cmd, issue_slots[9].in_uop.bits.csr_cmd connect slots_9.io.in_uop.bits.flush_on_commit, issue_slots[9].in_uop.bits.flush_on_commit connect slots_9.io.in_uop.bits.is_unique, issue_slots[9].in_uop.bits.is_unique connect slots_9.io.in_uop.bits.uses_stq, issue_slots[9].in_uop.bits.uses_stq connect slots_9.io.in_uop.bits.uses_ldq, issue_slots[9].in_uop.bits.uses_ldq connect slots_9.io.in_uop.bits.mem_signed, issue_slots[9].in_uop.bits.mem_signed connect slots_9.io.in_uop.bits.mem_size, issue_slots[9].in_uop.bits.mem_size connect slots_9.io.in_uop.bits.mem_cmd, issue_slots[9].in_uop.bits.mem_cmd connect slots_9.io.in_uop.bits.exc_cause, issue_slots[9].in_uop.bits.exc_cause connect slots_9.io.in_uop.bits.exception, issue_slots[9].in_uop.bits.exception connect slots_9.io.in_uop.bits.stale_pdst, issue_slots[9].in_uop.bits.stale_pdst connect slots_9.io.in_uop.bits.ppred_busy, issue_slots[9].in_uop.bits.ppred_busy connect slots_9.io.in_uop.bits.prs3_busy, issue_slots[9].in_uop.bits.prs3_busy connect slots_9.io.in_uop.bits.prs2_busy, issue_slots[9].in_uop.bits.prs2_busy connect slots_9.io.in_uop.bits.prs1_busy, issue_slots[9].in_uop.bits.prs1_busy connect slots_9.io.in_uop.bits.ppred, issue_slots[9].in_uop.bits.ppred connect slots_9.io.in_uop.bits.prs3, issue_slots[9].in_uop.bits.prs3 connect slots_9.io.in_uop.bits.prs2, issue_slots[9].in_uop.bits.prs2 connect slots_9.io.in_uop.bits.prs1, issue_slots[9].in_uop.bits.prs1 connect slots_9.io.in_uop.bits.pdst, issue_slots[9].in_uop.bits.pdst connect slots_9.io.in_uop.bits.rxq_idx, issue_slots[9].in_uop.bits.rxq_idx connect slots_9.io.in_uop.bits.stq_idx, issue_slots[9].in_uop.bits.stq_idx connect slots_9.io.in_uop.bits.ldq_idx, issue_slots[9].in_uop.bits.ldq_idx connect slots_9.io.in_uop.bits.rob_idx, issue_slots[9].in_uop.bits.rob_idx connect slots_9.io.in_uop.bits.fp_ctrl.vec, issue_slots[9].in_uop.bits.fp_ctrl.vec connect slots_9.io.in_uop.bits.fp_ctrl.wflags, issue_slots[9].in_uop.bits.fp_ctrl.wflags connect slots_9.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[9].in_uop.bits.fp_ctrl.sqrt connect slots_9.io.in_uop.bits.fp_ctrl.div, issue_slots[9].in_uop.bits.fp_ctrl.div connect slots_9.io.in_uop.bits.fp_ctrl.fma, issue_slots[9].in_uop.bits.fp_ctrl.fma connect slots_9.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].in_uop.bits.fp_ctrl.fastpipe connect slots_9.io.in_uop.bits.fp_ctrl.toint, issue_slots[9].in_uop.bits.fp_ctrl.toint connect slots_9.io.in_uop.bits.fp_ctrl.fromint, issue_slots[9].in_uop.bits.fp_ctrl.fromint connect slots_9.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut connect slots_9.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn connect slots_9.io.in_uop.bits.fp_ctrl.swap23, issue_slots[9].in_uop.bits.fp_ctrl.swap23 connect slots_9.io.in_uop.bits.fp_ctrl.swap12, issue_slots[9].in_uop.bits.fp_ctrl.swap12 connect slots_9.io.in_uop.bits.fp_ctrl.ren3, issue_slots[9].in_uop.bits.fp_ctrl.ren3 connect slots_9.io.in_uop.bits.fp_ctrl.ren2, issue_slots[9].in_uop.bits.fp_ctrl.ren2 connect slots_9.io.in_uop.bits.fp_ctrl.ren1, issue_slots[9].in_uop.bits.fp_ctrl.ren1 connect slots_9.io.in_uop.bits.fp_ctrl.wen, issue_slots[9].in_uop.bits.fp_ctrl.wen connect slots_9.io.in_uop.bits.fp_ctrl.ldst, issue_slots[9].in_uop.bits.fp_ctrl.ldst connect slots_9.io.in_uop.bits.op2_sel, issue_slots[9].in_uop.bits.op2_sel connect slots_9.io.in_uop.bits.op1_sel, issue_slots[9].in_uop.bits.op1_sel connect slots_9.io.in_uop.bits.imm_packed, issue_slots[9].in_uop.bits.imm_packed connect slots_9.io.in_uop.bits.pimm, issue_slots[9].in_uop.bits.pimm connect slots_9.io.in_uop.bits.imm_sel, issue_slots[9].in_uop.bits.imm_sel connect slots_9.io.in_uop.bits.imm_rename, issue_slots[9].in_uop.bits.imm_rename connect slots_9.io.in_uop.bits.taken, issue_slots[9].in_uop.bits.taken connect slots_9.io.in_uop.bits.pc_lob, issue_slots[9].in_uop.bits.pc_lob connect slots_9.io.in_uop.bits.edge_inst, issue_slots[9].in_uop.bits.edge_inst connect slots_9.io.in_uop.bits.ftq_idx, issue_slots[9].in_uop.bits.ftq_idx connect slots_9.io.in_uop.bits.is_mov, issue_slots[9].in_uop.bits.is_mov connect slots_9.io.in_uop.bits.is_rocc, issue_slots[9].in_uop.bits.is_rocc connect slots_9.io.in_uop.bits.is_sys_pc2epc, issue_slots[9].in_uop.bits.is_sys_pc2epc connect slots_9.io.in_uop.bits.is_eret, issue_slots[9].in_uop.bits.is_eret connect slots_9.io.in_uop.bits.is_amo, issue_slots[9].in_uop.bits.is_amo connect slots_9.io.in_uop.bits.is_sfence, issue_slots[9].in_uop.bits.is_sfence connect slots_9.io.in_uop.bits.is_fencei, issue_slots[9].in_uop.bits.is_fencei connect slots_9.io.in_uop.bits.is_fence, issue_slots[9].in_uop.bits.is_fence connect slots_9.io.in_uop.bits.is_sfb, issue_slots[9].in_uop.bits.is_sfb connect slots_9.io.in_uop.bits.br_type, issue_slots[9].in_uop.bits.br_type connect slots_9.io.in_uop.bits.br_tag, issue_slots[9].in_uop.bits.br_tag connect slots_9.io.in_uop.bits.br_mask, issue_slots[9].in_uop.bits.br_mask connect slots_9.io.in_uop.bits.dis_col_sel, issue_slots[9].in_uop.bits.dis_col_sel connect slots_9.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[9].in_uop.bits.iw_p3_bypass_hint connect slots_9.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[9].in_uop.bits.iw_p2_bypass_hint connect slots_9.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[9].in_uop.bits.iw_p1_bypass_hint connect slots_9.io.in_uop.bits.iw_p2_speculative_child, issue_slots[9].in_uop.bits.iw_p2_speculative_child connect slots_9.io.in_uop.bits.iw_p1_speculative_child, issue_slots[9].in_uop.bits.iw_p1_speculative_child connect slots_9.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[9].in_uop.bits.iw_issued_partial_dgen connect slots_9.io.in_uop.bits.iw_issued_partial_agen, issue_slots[9].in_uop.bits.iw_issued_partial_agen connect slots_9.io.in_uop.bits.iw_issued, issue_slots[9].in_uop.bits.iw_issued connect slots_9.io.in_uop.bits.fu_code[0], issue_slots[9].in_uop.bits.fu_code[0] connect slots_9.io.in_uop.bits.fu_code[1], issue_slots[9].in_uop.bits.fu_code[1] connect slots_9.io.in_uop.bits.fu_code[2], issue_slots[9].in_uop.bits.fu_code[2] connect slots_9.io.in_uop.bits.fu_code[3], issue_slots[9].in_uop.bits.fu_code[3] connect slots_9.io.in_uop.bits.fu_code[4], issue_slots[9].in_uop.bits.fu_code[4] connect slots_9.io.in_uop.bits.fu_code[5], issue_slots[9].in_uop.bits.fu_code[5] connect slots_9.io.in_uop.bits.fu_code[6], issue_slots[9].in_uop.bits.fu_code[6] connect slots_9.io.in_uop.bits.fu_code[7], issue_slots[9].in_uop.bits.fu_code[7] connect slots_9.io.in_uop.bits.fu_code[8], issue_slots[9].in_uop.bits.fu_code[8] connect slots_9.io.in_uop.bits.fu_code[9], issue_slots[9].in_uop.bits.fu_code[9] connect slots_9.io.in_uop.bits.iq_type[0], issue_slots[9].in_uop.bits.iq_type[0] connect slots_9.io.in_uop.bits.iq_type[1], issue_slots[9].in_uop.bits.iq_type[1] connect slots_9.io.in_uop.bits.iq_type[2], issue_slots[9].in_uop.bits.iq_type[2] connect slots_9.io.in_uop.bits.iq_type[3], issue_slots[9].in_uop.bits.iq_type[3] connect slots_9.io.in_uop.bits.debug_pc, issue_slots[9].in_uop.bits.debug_pc connect slots_9.io.in_uop.bits.is_rvc, issue_slots[9].in_uop.bits.is_rvc connect slots_9.io.in_uop.bits.debug_inst, issue_slots[9].in_uop.bits.debug_inst connect slots_9.io.in_uop.bits.inst, issue_slots[9].in_uop.bits.inst connect slots_9.io.in_uop.valid, issue_slots[9].in_uop.valid connect issue_slots[9].iss_uop.debug_tsrc, slots_9.io.iss_uop.debug_tsrc connect issue_slots[9].iss_uop.debug_fsrc, slots_9.io.iss_uop.debug_fsrc connect issue_slots[9].iss_uop.bp_xcpt_if, slots_9.io.iss_uop.bp_xcpt_if connect issue_slots[9].iss_uop.bp_debug_if, slots_9.io.iss_uop.bp_debug_if connect issue_slots[9].iss_uop.xcpt_ma_if, slots_9.io.iss_uop.xcpt_ma_if connect issue_slots[9].iss_uop.xcpt_ae_if, slots_9.io.iss_uop.xcpt_ae_if connect issue_slots[9].iss_uop.xcpt_pf_if, slots_9.io.iss_uop.xcpt_pf_if connect issue_slots[9].iss_uop.fp_typ, slots_9.io.iss_uop.fp_typ connect issue_slots[9].iss_uop.fp_rm, slots_9.io.iss_uop.fp_rm connect issue_slots[9].iss_uop.fp_val, slots_9.io.iss_uop.fp_val connect issue_slots[9].iss_uop.fcn_op, slots_9.io.iss_uop.fcn_op connect issue_slots[9].iss_uop.fcn_dw, slots_9.io.iss_uop.fcn_dw connect issue_slots[9].iss_uop.frs3_en, slots_9.io.iss_uop.frs3_en connect issue_slots[9].iss_uop.lrs2_rtype, slots_9.io.iss_uop.lrs2_rtype connect issue_slots[9].iss_uop.lrs1_rtype, slots_9.io.iss_uop.lrs1_rtype connect issue_slots[9].iss_uop.dst_rtype, slots_9.io.iss_uop.dst_rtype connect issue_slots[9].iss_uop.lrs3, slots_9.io.iss_uop.lrs3 connect issue_slots[9].iss_uop.lrs2, slots_9.io.iss_uop.lrs2 connect issue_slots[9].iss_uop.lrs1, slots_9.io.iss_uop.lrs1 connect issue_slots[9].iss_uop.ldst, slots_9.io.iss_uop.ldst connect issue_slots[9].iss_uop.ldst_is_rs1, slots_9.io.iss_uop.ldst_is_rs1 connect issue_slots[9].iss_uop.csr_cmd, slots_9.io.iss_uop.csr_cmd connect issue_slots[9].iss_uop.flush_on_commit, slots_9.io.iss_uop.flush_on_commit connect issue_slots[9].iss_uop.is_unique, slots_9.io.iss_uop.is_unique connect issue_slots[9].iss_uop.uses_stq, slots_9.io.iss_uop.uses_stq connect issue_slots[9].iss_uop.uses_ldq, slots_9.io.iss_uop.uses_ldq connect issue_slots[9].iss_uop.mem_signed, slots_9.io.iss_uop.mem_signed connect issue_slots[9].iss_uop.mem_size, slots_9.io.iss_uop.mem_size connect issue_slots[9].iss_uop.mem_cmd, slots_9.io.iss_uop.mem_cmd connect issue_slots[9].iss_uop.exc_cause, slots_9.io.iss_uop.exc_cause connect issue_slots[9].iss_uop.exception, slots_9.io.iss_uop.exception connect issue_slots[9].iss_uop.stale_pdst, slots_9.io.iss_uop.stale_pdst connect issue_slots[9].iss_uop.ppred_busy, slots_9.io.iss_uop.ppred_busy connect issue_slots[9].iss_uop.prs3_busy, slots_9.io.iss_uop.prs3_busy connect issue_slots[9].iss_uop.prs2_busy, slots_9.io.iss_uop.prs2_busy connect issue_slots[9].iss_uop.prs1_busy, slots_9.io.iss_uop.prs1_busy connect issue_slots[9].iss_uop.ppred, slots_9.io.iss_uop.ppred connect issue_slots[9].iss_uop.prs3, slots_9.io.iss_uop.prs3 connect issue_slots[9].iss_uop.prs2, slots_9.io.iss_uop.prs2 connect issue_slots[9].iss_uop.prs1, slots_9.io.iss_uop.prs1 connect issue_slots[9].iss_uop.pdst, slots_9.io.iss_uop.pdst connect issue_slots[9].iss_uop.rxq_idx, slots_9.io.iss_uop.rxq_idx connect issue_slots[9].iss_uop.stq_idx, slots_9.io.iss_uop.stq_idx connect issue_slots[9].iss_uop.ldq_idx, slots_9.io.iss_uop.ldq_idx connect issue_slots[9].iss_uop.rob_idx, slots_9.io.iss_uop.rob_idx connect issue_slots[9].iss_uop.fp_ctrl.vec, slots_9.io.iss_uop.fp_ctrl.vec connect issue_slots[9].iss_uop.fp_ctrl.wflags, slots_9.io.iss_uop.fp_ctrl.wflags connect issue_slots[9].iss_uop.fp_ctrl.sqrt, slots_9.io.iss_uop.fp_ctrl.sqrt connect issue_slots[9].iss_uop.fp_ctrl.div, slots_9.io.iss_uop.fp_ctrl.div connect issue_slots[9].iss_uop.fp_ctrl.fma, slots_9.io.iss_uop.fp_ctrl.fma connect issue_slots[9].iss_uop.fp_ctrl.fastpipe, slots_9.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[9].iss_uop.fp_ctrl.toint, slots_9.io.iss_uop.fp_ctrl.toint connect issue_slots[9].iss_uop.fp_ctrl.fromint, slots_9.io.iss_uop.fp_ctrl.fromint connect issue_slots[9].iss_uop.fp_ctrl.typeTagOut, slots_9.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[9].iss_uop.fp_ctrl.typeTagIn, slots_9.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[9].iss_uop.fp_ctrl.swap23, slots_9.io.iss_uop.fp_ctrl.swap23 connect issue_slots[9].iss_uop.fp_ctrl.swap12, slots_9.io.iss_uop.fp_ctrl.swap12 connect issue_slots[9].iss_uop.fp_ctrl.ren3, slots_9.io.iss_uop.fp_ctrl.ren3 connect issue_slots[9].iss_uop.fp_ctrl.ren2, slots_9.io.iss_uop.fp_ctrl.ren2 connect issue_slots[9].iss_uop.fp_ctrl.ren1, slots_9.io.iss_uop.fp_ctrl.ren1 connect issue_slots[9].iss_uop.fp_ctrl.wen, slots_9.io.iss_uop.fp_ctrl.wen connect issue_slots[9].iss_uop.fp_ctrl.ldst, slots_9.io.iss_uop.fp_ctrl.ldst connect issue_slots[9].iss_uop.op2_sel, slots_9.io.iss_uop.op2_sel connect issue_slots[9].iss_uop.op1_sel, slots_9.io.iss_uop.op1_sel connect issue_slots[9].iss_uop.imm_packed, slots_9.io.iss_uop.imm_packed connect issue_slots[9].iss_uop.pimm, slots_9.io.iss_uop.pimm connect issue_slots[9].iss_uop.imm_sel, slots_9.io.iss_uop.imm_sel connect issue_slots[9].iss_uop.imm_rename, slots_9.io.iss_uop.imm_rename connect issue_slots[9].iss_uop.taken, slots_9.io.iss_uop.taken connect issue_slots[9].iss_uop.pc_lob, slots_9.io.iss_uop.pc_lob connect issue_slots[9].iss_uop.edge_inst, slots_9.io.iss_uop.edge_inst connect issue_slots[9].iss_uop.ftq_idx, slots_9.io.iss_uop.ftq_idx connect issue_slots[9].iss_uop.is_mov, slots_9.io.iss_uop.is_mov connect issue_slots[9].iss_uop.is_rocc, slots_9.io.iss_uop.is_rocc connect issue_slots[9].iss_uop.is_sys_pc2epc, slots_9.io.iss_uop.is_sys_pc2epc connect issue_slots[9].iss_uop.is_eret, slots_9.io.iss_uop.is_eret connect issue_slots[9].iss_uop.is_amo, slots_9.io.iss_uop.is_amo connect issue_slots[9].iss_uop.is_sfence, slots_9.io.iss_uop.is_sfence connect issue_slots[9].iss_uop.is_fencei, slots_9.io.iss_uop.is_fencei connect issue_slots[9].iss_uop.is_fence, slots_9.io.iss_uop.is_fence connect issue_slots[9].iss_uop.is_sfb, slots_9.io.iss_uop.is_sfb connect issue_slots[9].iss_uop.br_type, slots_9.io.iss_uop.br_type connect issue_slots[9].iss_uop.br_tag, slots_9.io.iss_uop.br_tag connect issue_slots[9].iss_uop.br_mask, slots_9.io.iss_uop.br_mask connect issue_slots[9].iss_uop.dis_col_sel, slots_9.io.iss_uop.dis_col_sel connect issue_slots[9].iss_uop.iw_p3_bypass_hint, slots_9.io.iss_uop.iw_p3_bypass_hint connect issue_slots[9].iss_uop.iw_p2_bypass_hint, slots_9.io.iss_uop.iw_p2_bypass_hint connect issue_slots[9].iss_uop.iw_p1_bypass_hint, slots_9.io.iss_uop.iw_p1_bypass_hint connect issue_slots[9].iss_uop.iw_p2_speculative_child, slots_9.io.iss_uop.iw_p2_speculative_child connect issue_slots[9].iss_uop.iw_p1_speculative_child, slots_9.io.iss_uop.iw_p1_speculative_child connect issue_slots[9].iss_uop.iw_issued_partial_dgen, slots_9.io.iss_uop.iw_issued_partial_dgen connect issue_slots[9].iss_uop.iw_issued_partial_agen, slots_9.io.iss_uop.iw_issued_partial_agen connect issue_slots[9].iss_uop.iw_issued, slots_9.io.iss_uop.iw_issued connect issue_slots[9].iss_uop.fu_code[0], slots_9.io.iss_uop.fu_code[0] connect issue_slots[9].iss_uop.fu_code[1], slots_9.io.iss_uop.fu_code[1] connect issue_slots[9].iss_uop.fu_code[2], slots_9.io.iss_uop.fu_code[2] connect issue_slots[9].iss_uop.fu_code[3], slots_9.io.iss_uop.fu_code[3] connect issue_slots[9].iss_uop.fu_code[4], slots_9.io.iss_uop.fu_code[4] connect issue_slots[9].iss_uop.fu_code[5], slots_9.io.iss_uop.fu_code[5] connect issue_slots[9].iss_uop.fu_code[6], slots_9.io.iss_uop.fu_code[6] connect issue_slots[9].iss_uop.fu_code[7], slots_9.io.iss_uop.fu_code[7] connect issue_slots[9].iss_uop.fu_code[8], slots_9.io.iss_uop.fu_code[8] connect issue_slots[9].iss_uop.fu_code[9], slots_9.io.iss_uop.fu_code[9] connect issue_slots[9].iss_uop.iq_type[0], slots_9.io.iss_uop.iq_type[0] connect issue_slots[9].iss_uop.iq_type[1], slots_9.io.iss_uop.iq_type[1] connect issue_slots[9].iss_uop.iq_type[2], slots_9.io.iss_uop.iq_type[2] connect issue_slots[9].iss_uop.iq_type[3], slots_9.io.iss_uop.iq_type[3] connect issue_slots[9].iss_uop.debug_pc, slots_9.io.iss_uop.debug_pc connect issue_slots[9].iss_uop.is_rvc, slots_9.io.iss_uop.is_rvc connect issue_slots[9].iss_uop.debug_inst, slots_9.io.iss_uop.debug_inst connect issue_slots[9].iss_uop.inst, slots_9.io.iss_uop.inst connect slots_9.io.grant, issue_slots[9].grant connect issue_slots[9].request, slots_9.io.request connect issue_slots[9].will_be_valid, slots_9.io.will_be_valid connect issue_slots[9].valid, slots_9.io.valid connect slots_10.io.child_rebusys, issue_slots[10].child_rebusys connect slots_10.io.pred_wakeup_port.bits, issue_slots[10].pred_wakeup_port.bits connect slots_10.io.pred_wakeup_port.valid, issue_slots[10].pred_wakeup_port.valid connect slots_10.io.wakeup_ports[0].bits.rebusy, issue_slots[10].wakeup_ports[0].bits.rebusy connect slots_10.io.wakeup_ports[0].bits.speculative_mask, issue_slots[10].wakeup_ports[0].bits.speculative_mask connect slots_10.io.wakeup_ports[0].bits.bypassable, issue_slots[10].wakeup_ports[0].bits.bypassable connect slots_10.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[0].bits.uop.debug_tsrc connect slots_10.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[0].bits.uop.debug_fsrc connect slots_10.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_10.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[0].bits.uop.bp_debug_if connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_10.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[10].wakeup_ports[0].bits.uop.fp_typ connect slots_10.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[10].wakeup_ports[0].bits.uop.fp_rm connect slots_10.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[10].wakeup_ports[0].bits.uop.fp_val connect slots_10.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[10].wakeup_ports[0].bits.uop.fcn_op connect slots_10.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[0].bits.uop.fcn_dw connect slots_10.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[10].wakeup_ports[0].bits.uop.frs3_en connect slots_10.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_10.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_10.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[0].bits.uop.dst_rtype connect slots_10.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[10].wakeup_ports[0].bits.uop.lrs3 connect slots_10.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[10].wakeup_ports[0].bits.uop.lrs2 connect slots_10.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[10].wakeup_ports[0].bits.uop.lrs1 connect slots_10.io.wakeup_ports[0].bits.uop.ldst, issue_slots[10].wakeup_ports[0].bits.uop.ldst connect slots_10.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_10.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[0].bits.uop.csr_cmd connect slots_10.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[0].bits.uop.flush_on_commit connect slots_10.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[10].wakeup_ports[0].bits.uop.is_unique connect slots_10.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[10].wakeup_ports[0].bits.uop.uses_stq connect slots_10.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[0].bits.uop.uses_ldq connect slots_10.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[10].wakeup_ports[0].bits.uop.mem_signed connect slots_10.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[10].wakeup_ports[0].bits.uop.mem_size connect slots_10.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[0].bits.uop.mem_cmd connect slots_10.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[10].wakeup_ports[0].bits.uop.exc_cause connect slots_10.io.wakeup_ports[0].bits.uop.exception, issue_slots[10].wakeup_ports[0].bits.uop.exception connect slots_10.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[0].bits.uop.stale_pdst connect slots_10.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[0].bits.uop.ppred_busy connect slots_10.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs3_busy connect slots_10.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs2_busy connect slots_10.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs1_busy connect slots_10.io.wakeup_ports[0].bits.uop.ppred, issue_slots[10].wakeup_ports[0].bits.uop.ppred connect slots_10.io.wakeup_ports[0].bits.uop.prs3, issue_slots[10].wakeup_ports[0].bits.uop.prs3 connect slots_10.io.wakeup_ports[0].bits.uop.prs2, issue_slots[10].wakeup_ports[0].bits.uop.prs2 connect slots_10.io.wakeup_ports[0].bits.uop.prs1, issue_slots[10].wakeup_ports[0].bits.uop.prs1 connect slots_10.io.wakeup_ports[0].bits.uop.pdst, issue_slots[10].wakeup_ports[0].bits.uop.pdst connect slots_10.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[0].bits.uop.rxq_idx connect slots_10.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[10].wakeup_ports[0].bits.uop.stq_idx connect slots_10.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[0].bits.uop.ldq_idx connect slots_10.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[10].wakeup_ports[0].bits.uop.rob_idx connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_10.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[10].wakeup_ports[0].bits.uop.op2_sel connect slots_10.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[10].wakeup_ports[0].bits.uop.op1_sel connect slots_10.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[10].wakeup_ports[0].bits.uop.imm_packed connect slots_10.io.wakeup_ports[0].bits.uop.pimm, issue_slots[10].wakeup_ports[0].bits.uop.pimm connect slots_10.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[10].wakeup_ports[0].bits.uop.imm_sel connect slots_10.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[10].wakeup_ports[0].bits.uop.imm_rename connect slots_10.io.wakeup_ports[0].bits.uop.taken, issue_slots[10].wakeup_ports[0].bits.uop.taken connect slots_10.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[10].wakeup_ports[0].bits.uop.pc_lob connect slots_10.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[10].wakeup_ports[0].bits.uop.edge_inst connect slots_10.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[0].bits.uop.ftq_idx connect slots_10.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[10].wakeup_ports[0].bits.uop.is_mov connect slots_10.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[10].wakeup_ports[0].bits.uop.is_rocc connect slots_10.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_10.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[10].wakeup_ports[0].bits.uop.is_eret connect slots_10.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[10].wakeup_ports[0].bits.uop.is_amo connect slots_10.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[10].wakeup_ports[0].bits.uop.is_sfence connect slots_10.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[10].wakeup_ports[0].bits.uop.is_fencei connect slots_10.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[10].wakeup_ports[0].bits.uop.is_fence connect slots_10.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[10].wakeup_ports[0].bits.uop.is_sfb connect slots_10.io.wakeup_ports[0].bits.uop.br_type, issue_slots[10].wakeup_ports[0].bits.uop.br_type connect slots_10.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[10].wakeup_ports[0].bits.uop.br_tag connect slots_10.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[10].wakeup_ports[0].bits.uop.br_mask connect slots_10.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[0].bits.uop.dis_col_sel connect slots_10.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_10.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_10.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_10.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_10.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[0] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[1] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[2] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[3] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[4] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[5] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[6] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[7] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[8] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[9] connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[0] connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[1] connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[2] connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[3] connect slots_10.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[10].wakeup_ports[0].bits.uop.debug_pc connect slots_10.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[10].wakeup_ports[0].bits.uop.is_rvc connect slots_10.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[10].wakeup_ports[0].bits.uop.debug_inst connect slots_10.io.wakeup_ports[0].bits.uop.inst, issue_slots[10].wakeup_ports[0].bits.uop.inst connect slots_10.io.wakeup_ports[0].valid, issue_slots[10].wakeup_ports[0].valid connect slots_10.io.wakeup_ports[1].bits.rebusy, issue_slots[10].wakeup_ports[1].bits.rebusy connect slots_10.io.wakeup_ports[1].bits.speculative_mask, issue_slots[10].wakeup_ports[1].bits.speculative_mask connect slots_10.io.wakeup_ports[1].bits.bypassable, issue_slots[10].wakeup_ports[1].bits.bypassable connect slots_10.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[1].bits.uop.debug_tsrc connect slots_10.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[1].bits.uop.debug_fsrc connect slots_10.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_10.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[1].bits.uop.bp_debug_if connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_10.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[10].wakeup_ports[1].bits.uop.fp_typ connect slots_10.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[10].wakeup_ports[1].bits.uop.fp_rm connect slots_10.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[10].wakeup_ports[1].bits.uop.fp_val connect slots_10.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[10].wakeup_ports[1].bits.uop.fcn_op connect slots_10.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[1].bits.uop.fcn_dw connect slots_10.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[10].wakeup_ports[1].bits.uop.frs3_en connect slots_10.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_10.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_10.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[1].bits.uop.dst_rtype connect slots_10.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[10].wakeup_ports[1].bits.uop.lrs3 connect slots_10.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[10].wakeup_ports[1].bits.uop.lrs2 connect slots_10.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[10].wakeup_ports[1].bits.uop.lrs1 connect slots_10.io.wakeup_ports[1].bits.uop.ldst, issue_slots[10].wakeup_ports[1].bits.uop.ldst connect slots_10.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_10.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[1].bits.uop.csr_cmd connect slots_10.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[1].bits.uop.flush_on_commit connect slots_10.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[10].wakeup_ports[1].bits.uop.is_unique connect slots_10.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[10].wakeup_ports[1].bits.uop.uses_stq connect slots_10.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[1].bits.uop.uses_ldq connect slots_10.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[10].wakeup_ports[1].bits.uop.mem_signed connect slots_10.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[10].wakeup_ports[1].bits.uop.mem_size connect slots_10.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[1].bits.uop.mem_cmd connect slots_10.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[10].wakeup_ports[1].bits.uop.exc_cause connect slots_10.io.wakeup_ports[1].bits.uop.exception, issue_slots[10].wakeup_ports[1].bits.uop.exception connect slots_10.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[1].bits.uop.stale_pdst connect slots_10.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[1].bits.uop.ppred_busy connect slots_10.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs3_busy connect slots_10.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs2_busy connect slots_10.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs1_busy connect slots_10.io.wakeup_ports[1].bits.uop.ppred, issue_slots[10].wakeup_ports[1].bits.uop.ppred connect slots_10.io.wakeup_ports[1].bits.uop.prs3, issue_slots[10].wakeup_ports[1].bits.uop.prs3 connect slots_10.io.wakeup_ports[1].bits.uop.prs2, issue_slots[10].wakeup_ports[1].bits.uop.prs2 connect slots_10.io.wakeup_ports[1].bits.uop.prs1, issue_slots[10].wakeup_ports[1].bits.uop.prs1 connect slots_10.io.wakeup_ports[1].bits.uop.pdst, issue_slots[10].wakeup_ports[1].bits.uop.pdst connect slots_10.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[1].bits.uop.rxq_idx connect slots_10.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[10].wakeup_ports[1].bits.uop.stq_idx connect slots_10.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[1].bits.uop.ldq_idx connect slots_10.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[10].wakeup_ports[1].bits.uop.rob_idx connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_10.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[10].wakeup_ports[1].bits.uop.op2_sel connect slots_10.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[10].wakeup_ports[1].bits.uop.op1_sel connect slots_10.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[10].wakeup_ports[1].bits.uop.imm_packed connect slots_10.io.wakeup_ports[1].bits.uop.pimm, issue_slots[10].wakeup_ports[1].bits.uop.pimm connect slots_10.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[10].wakeup_ports[1].bits.uop.imm_sel connect slots_10.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[10].wakeup_ports[1].bits.uop.imm_rename connect slots_10.io.wakeup_ports[1].bits.uop.taken, issue_slots[10].wakeup_ports[1].bits.uop.taken connect slots_10.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[10].wakeup_ports[1].bits.uop.pc_lob connect slots_10.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[10].wakeup_ports[1].bits.uop.edge_inst connect slots_10.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[1].bits.uop.ftq_idx connect slots_10.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[10].wakeup_ports[1].bits.uop.is_mov connect slots_10.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[10].wakeup_ports[1].bits.uop.is_rocc connect slots_10.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_10.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[10].wakeup_ports[1].bits.uop.is_eret connect slots_10.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[10].wakeup_ports[1].bits.uop.is_amo connect slots_10.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[10].wakeup_ports[1].bits.uop.is_sfence connect slots_10.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[10].wakeup_ports[1].bits.uop.is_fencei connect slots_10.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[10].wakeup_ports[1].bits.uop.is_fence connect slots_10.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[10].wakeup_ports[1].bits.uop.is_sfb connect slots_10.io.wakeup_ports[1].bits.uop.br_type, issue_slots[10].wakeup_ports[1].bits.uop.br_type connect slots_10.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[10].wakeup_ports[1].bits.uop.br_tag connect slots_10.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[10].wakeup_ports[1].bits.uop.br_mask connect slots_10.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[1].bits.uop.dis_col_sel connect slots_10.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_10.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_10.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_10.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_10.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[0] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[1] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[2] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[3] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[4] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[5] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[6] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[7] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[8] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[9] connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[0] connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[1] connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[2] connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[3] connect slots_10.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[10].wakeup_ports[1].bits.uop.debug_pc connect slots_10.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[10].wakeup_ports[1].bits.uop.is_rvc connect slots_10.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[10].wakeup_ports[1].bits.uop.debug_inst connect slots_10.io.wakeup_ports[1].bits.uop.inst, issue_slots[10].wakeup_ports[1].bits.uop.inst connect slots_10.io.wakeup_ports[1].valid, issue_slots[10].wakeup_ports[1].valid connect slots_10.io.wakeup_ports[2].bits.rebusy, issue_slots[10].wakeup_ports[2].bits.rebusy connect slots_10.io.wakeup_ports[2].bits.speculative_mask, issue_slots[10].wakeup_ports[2].bits.speculative_mask connect slots_10.io.wakeup_ports[2].bits.bypassable, issue_slots[10].wakeup_ports[2].bits.bypassable connect slots_10.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[2].bits.uop.debug_tsrc connect slots_10.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[2].bits.uop.debug_fsrc connect slots_10.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_10.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[2].bits.uop.bp_debug_if connect slots_10.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_10.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_10.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_10.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[10].wakeup_ports[2].bits.uop.fp_typ connect slots_10.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[10].wakeup_ports[2].bits.uop.fp_rm connect slots_10.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[10].wakeup_ports[2].bits.uop.fp_val connect slots_10.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[10].wakeup_ports[2].bits.uop.fcn_op connect slots_10.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[2].bits.uop.fcn_dw connect slots_10.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[10].wakeup_ports[2].bits.uop.frs3_en connect slots_10.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_10.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_10.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[2].bits.uop.dst_rtype connect slots_10.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[10].wakeup_ports[2].bits.uop.lrs3 connect slots_10.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[10].wakeup_ports[2].bits.uop.lrs2 connect slots_10.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[10].wakeup_ports[2].bits.uop.lrs1 connect slots_10.io.wakeup_ports[2].bits.uop.ldst, issue_slots[10].wakeup_ports[2].bits.uop.ldst connect slots_10.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_10.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[2].bits.uop.csr_cmd connect slots_10.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[2].bits.uop.flush_on_commit connect slots_10.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[10].wakeup_ports[2].bits.uop.is_unique connect slots_10.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[10].wakeup_ports[2].bits.uop.uses_stq connect slots_10.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[2].bits.uop.uses_ldq connect slots_10.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[10].wakeup_ports[2].bits.uop.mem_signed connect slots_10.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[10].wakeup_ports[2].bits.uop.mem_size connect slots_10.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[2].bits.uop.mem_cmd connect slots_10.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[10].wakeup_ports[2].bits.uop.exc_cause connect slots_10.io.wakeup_ports[2].bits.uop.exception, issue_slots[10].wakeup_ports[2].bits.uop.exception connect slots_10.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[2].bits.uop.stale_pdst connect slots_10.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[2].bits.uop.ppred_busy connect slots_10.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[2].bits.uop.prs3_busy connect slots_10.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[2].bits.uop.prs2_busy connect slots_10.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[2].bits.uop.prs1_busy connect slots_10.io.wakeup_ports[2].bits.uop.ppred, issue_slots[10].wakeup_ports[2].bits.uop.ppred connect slots_10.io.wakeup_ports[2].bits.uop.prs3, issue_slots[10].wakeup_ports[2].bits.uop.prs3 connect slots_10.io.wakeup_ports[2].bits.uop.prs2, issue_slots[10].wakeup_ports[2].bits.uop.prs2 connect slots_10.io.wakeup_ports[2].bits.uop.prs1, issue_slots[10].wakeup_ports[2].bits.uop.prs1 connect slots_10.io.wakeup_ports[2].bits.uop.pdst, issue_slots[10].wakeup_ports[2].bits.uop.pdst connect slots_10.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[2].bits.uop.rxq_idx connect slots_10.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[10].wakeup_ports[2].bits.uop.stq_idx connect slots_10.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[2].bits.uop.ldq_idx connect slots_10.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[10].wakeup_ports[2].bits.uop.rob_idx connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_10.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[10].wakeup_ports[2].bits.uop.op2_sel connect slots_10.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[10].wakeup_ports[2].bits.uop.op1_sel connect slots_10.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[10].wakeup_ports[2].bits.uop.imm_packed connect slots_10.io.wakeup_ports[2].bits.uop.pimm, issue_slots[10].wakeup_ports[2].bits.uop.pimm connect slots_10.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[10].wakeup_ports[2].bits.uop.imm_sel connect slots_10.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[10].wakeup_ports[2].bits.uop.imm_rename connect slots_10.io.wakeup_ports[2].bits.uop.taken, issue_slots[10].wakeup_ports[2].bits.uop.taken connect slots_10.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[10].wakeup_ports[2].bits.uop.pc_lob connect slots_10.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[10].wakeup_ports[2].bits.uop.edge_inst connect slots_10.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[2].bits.uop.ftq_idx connect slots_10.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[10].wakeup_ports[2].bits.uop.is_mov connect slots_10.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[10].wakeup_ports[2].bits.uop.is_rocc connect slots_10.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_10.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[10].wakeup_ports[2].bits.uop.is_eret connect slots_10.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[10].wakeup_ports[2].bits.uop.is_amo connect slots_10.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[10].wakeup_ports[2].bits.uop.is_sfence connect slots_10.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[10].wakeup_ports[2].bits.uop.is_fencei connect slots_10.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[10].wakeup_ports[2].bits.uop.is_fence connect slots_10.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[10].wakeup_ports[2].bits.uop.is_sfb connect slots_10.io.wakeup_ports[2].bits.uop.br_type, issue_slots[10].wakeup_ports[2].bits.uop.br_type connect slots_10.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[10].wakeup_ports[2].bits.uop.br_tag connect slots_10.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[10].wakeup_ports[2].bits.uop.br_mask connect slots_10.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[2].bits.uop.dis_col_sel connect slots_10.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_10.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_10.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_10.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_10.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_10.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_10.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_10.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[10].wakeup_ports[2].bits.uop.iw_issued connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[0] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[1] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[2] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[3] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[4] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[5] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[6] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[7] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[8] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[9] connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[0] connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[1] connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[2] connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[3] connect slots_10.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[10].wakeup_ports[2].bits.uop.debug_pc connect slots_10.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[10].wakeup_ports[2].bits.uop.is_rvc connect slots_10.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[10].wakeup_ports[2].bits.uop.debug_inst connect slots_10.io.wakeup_ports[2].bits.uop.inst, issue_slots[10].wakeup_ports[2].bits.uop.inst connect slots_10.io.wakeup_ports[2].valid, issue_slots[10].wakeup_ports[2].valid connect slots_10.io.wakeup_ports[3].bits.rebusy, issue_slots[10].wakeup_ports[3].bits.rebusy connect slots_10.io.wakeup_ports[3].bits.speculative_mask, issue_slots[10].wakeup_ports[3].bits.speculative_mask connect slots_10.io.wakeup_ports[3].bits.bypassable, issue_slots[10].wakeup_ports[3].bits.bypassable connect slots_10.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[3].bits.uop.debug_tsrc connect slots_10.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[3].bits.uop.debug_fsrc connect slots_10.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_10.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[3].bits.uop.bp_debug_if connect slots_10.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_10.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_10.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_10.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[10].wakeup_ports[3].bits.uop.fp_typ connect slots_10.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[10].wakeup_ports[3].bits.uop.fp_rm connect slots_10.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[10].wakeup_ports[3].bits.uop.fp_val connect slots_10.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[10].wakeup_ports[3].bits.uop.fcn_op connect slots_10.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[3].bits.uop.fcn_dw connect slots_10.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[10].wakeup_ports[3].bits.uop.frs3_en connect slots_10.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_10.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_10.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[3].bits.uop.dst_rtype connect slots_10.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[10].wakeup_ports[3].bits.uop.lrs3 connect slots_10.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[10].wakeup_ports[3].bits.uop.lrs2 connect slots_10.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[10].wakeup_ports[3].bits.uop.lrs1 connect slots_10.io.wakeup_ports[3].bits.uop.ldst, issue_slots[10].wakeup_ports[3].bits.uop.ldst connect slots_10.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_10.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[3].bits.uop.csr_cmd connect slots_10.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[3].bits.uop.flush_on_commit connect slots_10.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[10].wakeup_ports[3].bits.uop.is_unique connect slots_10.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[10].wakeup_ports[3].bits.uop.uses_stq connect slots_10.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[3].bits.uop.uses_ldq connect slots_10.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[10].wakeup_ports[3].bits.uop.mem_signed connect slots_10.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[10].wakeup_ports[3].bits.uop.mem_size connect slots_10.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[3].bits.uop.mem_cmd connect slots_10.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[10].wakeup_ports[3].bits.uop.exc_cause connect slots_10.io.wakeup_ports[3].bits.uop.exception, issue_slots[10].wakeup_ports[3].bits.uop.exception connect slots_10.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[3].bits.uop.stale_pdst connect slots_10.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[3].bits.uop.ppred_busy connect slots_10.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[3].bits.uop.prs3_busy connect slots_10.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[3].bits.uop.prs2_busy connect slots_10.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[3].bits.uop.prs1_busy connect slots_10.io.wakeup_ports[3].bits.uop.ppred, issue_slots[10].wakeup_ports[3].bits.uop.ppred connect slots_10.io.wakeup_ports[3].bits.uop.prs3, issue_slots[10].wakeup_ports[3].bits.uop.prs3 connect slots_10.io.wakeup_ports[3].bits.uop.prs2, issue_slots[10].wakeup_ports[3].bits.uop.prs2 connect slots_10.io.wakeup_ports[3].bits.uop.prs1, issue_slots[10].wakeup_ports[3].bits.uop.prs1 connect slots_10.io.wakeup_ports[3].bits.uop.pdst, issue_slots[10].wakeup_ports[3].bits.uop.pdst connect slots_10.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[3].bits.uop.rxq_idx connect slots_10.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[10].wakeup_ports[3].bits.uop.stq_idx connect slots_10.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[3].bits.uop.ldq_idx connect slots_10.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[10].wakeup_ports[3].bits.uop.rob_idx connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_10.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[10].wakeup_ports[3].bits.uop.op2_sel connect slots_10.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[10].wakeup_ports[3].bits.uop.op1_sel connect slots_10.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[10].wakeup_ports[3].bits.uop.imm_packed connect slots_10.io.wakeup_ports[3].bits.uop.pimm, issue_slots[10].wakeup_ports[3].bits.uop.pimm connect slots_10.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[10].wakeup_ports[3].bits.uop.imm_sel connect slots_10.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[10].wakeup_ports[3].bits.uop.imm_rename connect slots_10.io.wakeup_ports[3].bits.uop.taken, issue_slots[10].wakeup_ports[3].bits.uop.taken connect slots_10.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[10].wakeup_ports[3].bits.uop.pc_lob connect slots_10.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[10].wakeup_ports[3].bits.uop.edge_inst connect slots_10.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[3].bits.uop.ftq_idx connect slots_10.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[10].wakeup_ports[3].bits.uop.is_mov connect slots_10.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[10].wakeup_ports[3].bits.uop.is_rocc connect slots_10.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_10.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[10].wakeup_ports[3].bits.uop.is_eret connect slots_10.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[10].wakeup_ports[3].bits.uop.is_amo connect slots_10.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[10].wakeup_ports[3].bits.uop.is_sfence connect slots_10.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[10].wakeup_ports[3].bits.uop.is_fencei connect slots_10.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[10].wakeup_ports[3].bits.uop.is_fence connect slots_10.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[10].wakeup_ports[3].bits.uop.is_sfb connect slots_10.io.wakeup_ports[3].bits.uop.br_type, issue_slots[10].wakeup_ports[3].bits.uop.br_type connect slots_10.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[10].wakeup_ports[3].bits.uop.br_tag connect slots_10.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[10].wakeup_ports[3].bits.uop.br_mask connect slots_10.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[3].bits.uop.dis_col_sel connect slots_10.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_10.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_10.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_10.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_10.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_10.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_10.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_10.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[10].wakeup_ports[3].bits.uop.iw_issued connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[0] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[1] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[2] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[3] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[4] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[5] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[6] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[7] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[8] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[9] connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[0] connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[1] connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[2] connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[3] connect slots_10.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[10].wakeup_ports[3].bits.uop.debug_pc connect slots_10.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[10].wakeup_ports[3].bits.uop.is_rvc connect slots_10.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[10].wakeup_ports[3].bits.uop.debug_inst connect slots_10.io.wakeup_ports[3].bits.uop.inst, issue_slots[10].wakeup_ports[3].bits.uop.inst connect slots_10.io.wakeup_ports[3].valid, issue_slots[10].wakeup_ports[3].valid connect slots_10.io.wakeup_ports[4].bits.rebusy, issue_slots[10].wakeup_ports[4].bits.rebusy connect slots_10.io.wakeup_ports[4].bits.speculative_mask, issue_slots[10].wakeup_ports[4].bits.speculative_mask connect slots_10.io.wakeup_ports[4].bits.bypassable, issue_slots[10].wakeup_ports[4].bits.bypassable connect slots_10.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[4].bits.uop.debug_tsrc connect slots_10.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[4].bits.uop.debug_fsrc connect slots_10.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_10.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[4].bits.uop.bp_debug_if connect slots_10.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_10.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_10.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_10.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[10].wakeup_ports[4].bits.uop.fp_typ connect slots_10.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[10].wakeup_ports[4].bits.uop.fp_rm connect slots_10.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[10].wakeup_ports[4].bits.uop.fp_val connect slots_10.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[10].wakeup_ports[4].bits.uop.fcn_op connect slots_10.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[4].bits.uop.fcn_dw connect slots_10.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[10].wakeup_ports[4].bits.uop.frs3_en connect slots_10.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_10.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_10.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[4].bits.uop.dst_rtype connect slots_10.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[10].wakeup_ports[4].bits.uop.lrs3 connect slots_10.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[10].wakeup_ports[4].bits.uop.lrs2 connect slots_10.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[10].wakeup_ports[4].bits.uop.lrs1 connect slots_10.io.wakeup_ports[4].bits.uop.ldst, issue_slots[10].wakeup_ports[4].bits.uop.ldst connect slots_10.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_10.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[4].bits.uop.csr_cmd connect slots_10.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[4].bits.uop.flush_on_commit connect slots_10.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[10].wakeup_ports[4].bits.uop.is_unique connect slots_10.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[10].wakeup_ports[4].bits.uop.uses_stq connect slots_10.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[4].bits.uop.uses_ldq connect slots_10.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[10].wakeup_ports[4].bits.uop.mem_signed connect slots_10.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[10].wakeup_ports[4].bits.uop.mem_size connect slots_10.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[4].bits.uop.mem_cmd connect slots_10.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[10].wakeup_ports[4].bits.uop.exc_cause connect slots_10.io.wakeup_ports[4].bits.uop.exception, issue_slots[10].wakeup_ports[4].bits.uop.exception connect slots_10.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[4].bits.uop.stale_pdst connect slots_10.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[4].bits.uop.ppred_busy connect slots_10.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[4].bits.uop.prs3_busy connect slots_10.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[4].bits.uop.prs2_busy connect slots_10.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[4].bits.uop.prs1_busy connect slots_10.io.wakeup_ports[4].bits.uop.ppred, issue_slots[10].wakeup_ports[4].bits.uop.ppred connect slots_10.io.wakeup_ports[4].bits.uop.prs3, issue_slots[10].wakeup_ports[4].bits.uop.prs3 connect slots_10.io.wakeup_ports[4].bits.uop.prs2, issue_slots[10].wakeup_ports[4].bits.uop.prs2 connect slots_10.io.wakeup_ports[4].bits.uop.prs1, issue_slots[10].wakeup_ports[4].bits.uop.prs1 connect slots_10.io.wakeup_ports[4].bits.uop.pdst, issue_slots[10].wakeup_ports[4].bits.uop.pdst connect slots_10.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[4].bits.uop.rxq_idx connect slots_10.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[10].wakeup_ports[4].bits.uop.stq_idx connect slots_10.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[4].bits.uop.ldq_idx connect slots_10.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[10].wakeup_ports[4].bits.uop.rob_idx connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_10.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[10].wakeup_ports[4].bits.uop.op2_sel connect slots_10.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[10].wakeup_ports[4].bits.uop.op1_sel connect slots_10.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[10].wakeup_ports[4].bits.uop.imm_packed connect slots_10.io.wakeup_ports[4].bits.uop.pimm, issue_slots[10].wakeup_ports[4].bits.uop.pimm connect slots_10.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[10].wakeup_ports[4].bits.uop.imm_sel connect slots_10.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[10].wakeup_ports[4].bits.uop.imm_rename connect slots_10.io.wakeup_ports[4].bits.uop.taken, issue_slots[10].wakeup_ports[4].bits.uop.taken connect slots_10.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[10].wakeup_ports[4].bits.uop.pc_lob connect slots_10.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[10].wakeup_ports[4].bits.uop.edge_inst connect slots_10.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[4].bits.uop.ftq_idx connect slots_10.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[10].wakeup_ports[4].bits.uop.is_mov connect slots_10.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[10].wakeup_ports[4].bits.uop.is_rocc connect slots_10.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_10.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[10].wakeup_ports[4].bits.uop.is_eret connect slots_10.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[10].wakeup_ports[4].bits.uop.is_amo connect slots_10.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[10].wakeup_ports[4].bits.uop.is_sfence connect slots_10.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[10].wakeup_ports[4].bits.uop.is_fencei connect slots_10.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[10].wakeup_ports[4].bits.uop.is_fence connect slots_10.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[10].wakeup_ports[4].bits.uop.is_sfb connect slots_10.io.wakeup_ports[4].bits.uop.br_type, issue_slots[10].wakeup_ports[4].bits.uop.br_type connect slots_10.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[10].wakeup_ports[4].bits.uop.br_tag connect slots_10.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[10].wakeup_ports[4].bits.uop.br_mask connect slots_10.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[4].bits.uop.dis_col_sel connect slots_10.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_10.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_10.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_10.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_10.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_10.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_10.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_10.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[10].wakeup_ports[4].bits.uop.iw_issued connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[0] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[1] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[2] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[3] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[4] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[5] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[6] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[7] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[8] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[9] connect slots_10.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[4].bits.uop.iq_type[0] connect slots_10.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[4].bits.uop.iq_type[1] connect slots_10.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[4].bits.uop.iq_type[2] connect slots_10.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[4].bits.uop.iq_type[3] connect slots_10.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[10].wakeup_ports[4].bits.uop.debug_pc connect slots_10.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[10].wakeup_ports[4].bits.uop.is_rvc connect slots_10.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[10].wakeup_ports[4].bits.uop.debug_inst connect slots_10.io.wakeup_ports[4].bits.uop.inst, issue_slots[10].wakeup_ports[4].bits.uop.inst connect slots_10.io.wakeup_ports[4].valid, issue_slots[10].wakeup_ports[4].valid connect slots_10.io.squash_grant, issue_slots[10].squash_grant connect slots_10.io.clear, issue_slots[10].clear connect slots_10.io.kill, issue_slots[10].kill connect slots_10.io.brupdate.b2.target_offset, issue_slots[10].brupdate.b2.target_offset connect slots_10.io.brupdate.b2.jalr_target, issue_slots[10].brupdate.b2.jalr_target connect slots_10.io.brupdate.b2.pc_sel, issue_slots[10].brupdate.b2.pc_sel connect slots_10.io.brupdate.b2.cfi_type, issue_slots[10].brupdate.b2.cfi_type connect slots_10.io.brupdate.b2.taken, issue_slots[10].brupdate.b2.taken connect slots_10.io.brupdate.b2.mispredict, issue_slots[10].brupdate.b2.mispredict connect slots_10.io.brupdate.b2.uop.debug_tsrc, issue_slots[10].brupdate.b2.uop.debug_tsrc connect slots_10.io.brupdate.b2.uop.debug_fsrc, issue_slots[10].brupdate.b2.uop.debug_fsrc connect slots_10.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[10].brupdate.b2.uop.bp_xcpt_if connect slots_10.io.brupdate.b2.uop.bp_debug_if, issue_slots[10].brupdate.b2.uop.bp_debug_if connect slots_10.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[10].brupdate.b2.uop.xcpt_ma_if connect slots_10.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[10].brupdate.b2.uop.xcpt_ae_if connect slots_10.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[10].brupdate.b2.uop.xcpt_pf_if connect slots_10.io.brupdate.b2.uop.fp_typ, issue_slots[10].brupdate.b2.uop.fp_typ connect slots_10.io.brupdate.b2.uop.fp_rm, issue_slots[10].brupdate.b2.uop.fp_rm connect slots_10.io.brupdate.b2.uop.fp_val, issue_slots[10].brupdate.b2.uop.fp_val connect slots_10.io.brupdate.b2.uop.fcn_op, issue_slots[10].brupdate.b2.uop.fcn_op connect slots_10.io.brupdate.b2.uop.fcn_dw, issue_slots[10].brupdate.b2.uop.fcn_dw connect slots_10.io.brupdate.b2.uop.frs3_en, issue_slots[10].brupdate.b2.uop.frs3_en connect slots_10.io.brupdate.b2.uop.lrs2_rtype, issue_slots[10].brupdate.b2.uop.lrs2_rtype connect slots_10.io.brupdate.b2.uop.lrs1_rtype, issue_slots[10].brupdate.b2.uop.lrs1_rtype connect slots_10.io.brupdate.b2.uop.dst_rtype, issue_slots[10].brupdate.b2.uop.dst_rtype connect slots_10.io.brupdate.b2.uop.lrs3, issue_slots[10].brupdate.b2.uop.lrs3 connect slots_10.io.brupdate.b2.uop.lrs2, issue_slots[10].brupdate.b2.uop.lrs2 connect slots_10.io.brupdate.b2.uop.lrs1, issue_slots[10].brupdate.b2.uop.lrs1 connect slots_10.io.brupdate.b2.uop.ldst, issue_slots[10].brupdate.b2.uop.ldst connect slots_10.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[10].brupdate.b2.uop.ldst_is_rs1 connect slots_10.io.brupdate.b2.uop.csr_cmd, issue_slots[10].brupdate.b2.uop.csr_cmd connect slots_10.io.brupdate.b2.uop.flush_on_commit, issue_slots[10].brupdate.b2.uop.flush_on_commit connect slots_10.io.brupdate.b2.uop.is_unique, issue_slots[10].brupdate.b2.uop.is_unique connect slots_10.io.brupdate.b2.uop.uses_stq, issue_slots[10].brupdate.b2.uop.uses_stq connect slots_10.io.brupdate.b2.uop.uses_ldq, issue_slots[10].brupdate.b2.uop.uses_ldq connect slots_10.io.brupdate.b2.uop.mem_signed, issue_slots[10].brupdate.b2.uop.mem_signed connect slots_10.io.brupdate.b2.uop.mem_size, issue_slots[10].brupdate.b2.uop.mem_size connect slots_10.io.brupdate.b2.uop.mem_cmd, issue_slots[10].brupdate.b2.uop.mem_cmd connect slots_10.io.brupdate.b2.uop.exc_cause, issue_slots[10].brupdate.b2.uop.exc_cause connect slots_10.io.brupdate.b2.uop.exception, issue_slots[10].brupdate.b2.uop.exception connect slots_10.io.brupdate.b2.uop.stale_pdst, issue_slots[10].brupdate.b2.uop.stale_pdst connect slots_10.io.brupdate.b2.uop.ppred_busy, issue_slots[10].brupdate.b2.uop.ppred_busy connect slots_10.io.brupdate.b2.uop.prs3_busy, issue_slots[10].brupdate.b2.uop.prs3_busy connect slots_10.io.brupdate.b2.uop.prs2_busy, issue_slots[10].brupdate.b2.uop.prs2_busy connect slots_10.io.brupdate.b2.uop.prs1_busy, issue_slots[10].brupdate.b2.uop.prs1_busy connect slots_10.io.brupdate.b2.uop.ppred, issue_slots[10].brupdate.b2.uop.ppred connect slots_10.io.brupdate.b2.uop.prs3, issue_slots[10].brupdate.b2.uop.prs3 connect slots_10.io.brupdate.b2.uop.prs2, issue_slots[10].brupdate.b2.uop.prs2 connect slots_10.io.brupdate.b2.uop.prs1, issue_slots[10].brupdate.b2.uop.prs1 connect slots_10.io.brupdate.b2.uop.pdst, issue_slots[10].brupdate.b2.uop.pdst connect slots_10.io.brupdate.b2.uop.rxq_idx, issue_slots[10].brupdate.b2.uop.rxq_idx connect slots_10.io.brupdate.b2.uop.stq_idx, issue_slots[10].brupdate.b2.uop.stq_idx connect slots_10.io.brupdate.b2.uop.ldq_idx, issue_slots[10].brupdate.b2.uop.ldq_idx connect slots_10.io.brupdate.b2.uop.rob_idx, issue_slots[10].brupdate.b2.uop.rob_idx connect slots_10.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[10].brupdate.b2.uop.fp_ctrl.vec connect slots_10.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[10].brupdate.b2.uop.fp_ctrl.wflags connect slots_10.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[10].brupdate.b2.uop.fp_ctrl.sqrt connect slots_10.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[10].brupdate.b2.uop.fp_ctrl.div connect slots_10.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[10].brupdate.b2.uop.fp_ctrl.fma connect slots_10.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[10].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_10.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[10].brupdate.b2.uop.fp_ctrl.toint connect slots_10.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[10].brupdate.b2.uop.fp_ctrl.fromint connect slots_10.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_10.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_10.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[10].brupdate.b2.uop.fp_ctrl.swap23 connect slots_10.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[10].brupdate.b2.uop.fp_ctrl.swap12 connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren3 connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren2 connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren1 connect slots_10.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[10].brupdate.b2.uop.fp_ctrl.wen connect slots_10.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[10].brupdate.b2.uop.fp_ctrl.ldst connect slots_10.io.brupdate.b2.uop.op2_sel, issue_slots[10].brupdate.b2.uop.op2_sel connect slots_10.io.brupdate.b2.uop.op1_sel, issue_slots[10].brupdate.b2.uop.op1_sel connect slots_10.io.brupdate.b2.uop.imm_packed, issue_slots[10].brupdate.b2.uop.imm_packed connect slots_10.io.brupdate.b2.uop.pimm, issue_slots[10].brupdate.b2.uop.pimm connect slots_10.io.brupdate.b2.uop.imm_sel, issue_slots[10].brupdate.b2.uop.imm_sel connect slots_10.io.brupdate.b2.uop.imm_rename, issue_slots[10].brupdate.b2.uop.imm_rename connect slots_10.io.brupdate.b2.uop.taken, issue_slots[10].brupdate.b2.uop.taken connect slots_10.io.brupdate.b2.uop.pc_lob, issue_slots[10].brupdate.b2.uop.pc_lob connect slots_10.io.brupdate.b2.uop.edge_inst, issue_slots[10].brupdate.b2.uop.edge_inst connect slots_10.io.brupdate.b2.uop.ftq_idx, issue_slots[10].brupdate.b2.uop.ftq_idx connect slots_10.io.brupdate.b2.uop.is_mov, issue_slots[10].brupdate.b2.uop.is_mov connect slots_10.io.brupdate.b2.uop.is_rocc, issue_slots[10].brupdate.b2.uop.is_rocc connect slots_10.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[10].brupdate.b2.uop.is_sys_pc2epc connect slots_10.io.brupdate.b2.uop.is_eret, issue_slots[10].brupdate.b2.uop.is_eret connect slots_10.io.brupdate.b2.uop.is_amo, issue_slots[10].brupdate.b2.uop.is_amo connect slots_10.io.brupdate.b2.uop.is_sfence, issue_slots[10].brupdate.b2.uop.is_sfence connect slots_10.io.brupdate.b2.uop.is_fencei, issue_slots[10].brupdate.b2.uop.is_fencei connect slots_10.io.brupdate.b2.uop.is_fence, issue_slots[10].brupdate.b2.uop.is_fence connect slots_10.io.brupdate.b2.uop.is_sfb, issue_slots[10].brupdate.b2.uop.is_sfb connect slots_10.io.brupdate.b2.uop.br_type, issue_slots[10].brupdate.b2.uop.br_type connect slots_10.io.brupdate.b2.uop.br_tag, issue_slots[10].brupdate.b2.uop.br_tag connect slots_10.io.brupdate.b2.uop.br_mask, issue_slots[10].brupdate.b2.uop.br_mask connect slots_10.io.brupdate.b2.uop.dis_col_sel, issue_slots[10].brupdate.b2.uop.dis_col_sel connect slots_10.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p3_bypass_hint connect slots_10.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p2_bypass_hint connect slots_10.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p1_bypass_hint connect slots_10.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[10].brupdate.b2.uop.iw_p2_speculative_child connect slots_10.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[10].brupdate.b2.uop.iw_p1_speculative_child connect slots_10.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[10].brupdate.b2.uop.iw_issued_partial_dgen connect slots_10.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[10].brupdate.b2.uop.iw_issued_partial_agen connect slots_10.io.brupdate.b2.uop.iw_issued, issue_slots[10].brupdate.b2.uop.iw_issued connect slots_10.io.brupdate.b2.uop.fu_code[0], issue_slots[10].brupdate.b2.uop.fu_code[0] connect slots_10.io.brupdate.b2.uop.fu_code[1], issue_slots[10].brupdate.b2.uop.fu_code[1] connect slots_10.io.brupdate.b2.uop.fu_code[2], issue_slots[10].brupdate.b2.uop.fu_code[2] connect slots_10.io.brupdate.b2.uop.fu_code[3], issue_slots[10].brupdate.b2.uop.fu_code[3] connect slots_10.io.brupdate.b2.uop.fu_code[4], issue_slots[10].brupdate.b2.uop.fu_code[4] connect slots_10.io.brupdate.b2.uop.fu_code[5], issue_slots[10].brupdate.b2.uop.fu_code[5] connect slots_10.io.brupdate.b2.uop.fu_code[6], issue_slots[10].brupdate.b2.uop.fu_code[6] connect slots_10.io.brupdate.b2.uop.fu_code[7], issue_slots[10].brupdate.b2.uop.fu_code[7] connect slots_10.io.brupdate.b2.uop.fu_code[8], issue_slots[10].brupdate.b2.uop.fu_code[8] connect slots_10.io.brupdate.b2.uop.fu_code[9], issue_slots[10].brupdate.b2.uop.fu_code[9] connect slots_10.io.brupdate.b2.uop.iq_type[0], issue_slots[10].brupdate.b2.uop.iq_type[0] connect slots_10.io.brupdate.b2.uop.iq_type[1], issue_slots[10].brupdate.b2.uop.iq_type[1] connect slots_10.io.brupdate.b2.uop.iq_type[2], issue_slots[10].brupdate.b2.uop.iq_type[2] connect slots_10.io.brupdate.b2.uop.iq_type[3], issue_slots[10].brupdate.b2.uop.iq_type[3] connect slots_10.io.brupdate.b2.uop.debug_pc, issue_slots[10].brupdate.b2.uop.debug_pc connect slots_10.io.brupdate.b2.uop.is_rvc, issue_slots[10].brupdate.b2.uop.is_rvc connect slots_10.io.brupdate.b2.uop.debug_inst, issue_slots[10].brupdate.b2.uop.debug_inst connect slots_10.io.brupdate.b2.uop.inst, issue_slots[10].brupdate.b2.uop.inst connect slots_10.io.brupdate.b1.mispredict_mask, issue_slots[10].brupdate.b1.mispredict_mask connect slots_10.io.brupdate.b1.resolve_mask, issue_slots[10].brupdate.b1.resolve_mask connect issue_slots[10].out_uop.debug_tsrc, slots_10.io.out_uop.debug_tsrc connect issue_slots[10].out_uop.debug_fsrc, slots_10.io.out_uop.debug_fsrc connect issue_slots[10].out_uop.bp_xcpt_if, slots_10.io.out_uop.bp_xcpt_if connect issue_slots[10].out_uop.bp_debug_if, slots_10.io.out_uop.bp_debug_if connect issue_slots[10].out_uop.xcpt_ma_if, slots_10.io.out_uop.xcpt_ma_if connect issue_slots[10].out_uop.xcpt_ae_if, slots_10.io.out_uop.xcpt_ae_if connect issue_slots[10].out_uop.xcpt_pf_if, slots_10.io.out_uop.xcpt_pf_if connect issue_slots[10].out_uop.fp_typ, slots_10.io.out_uop.fp_typ connect issue_slots[10].out_uop.fp_rm, slots_10.io.out_uop.fp_rm connect issue_slots[10].out_uop.fp_val, slots_10.io.out_uop.fp_val connect issue_slots[10].out_uop.fcn_op, slots_10.io.out_uop.fcn_op connect issue_slots[10].out_uop.fcn_dw, slots_10.io.out_uop.fcn_dw connect issue_slots[10].out_uop.frs3_en, slots_10.io.out_uop.frs3_en connect issue_slots[10].out_uop.lrs2_rtype, slots_10.io.out_uop.lrs2_rtype connect issue_slots[10].out_uop.lrs1_rtype, slots_10.io.out_uop.lrs1_rtype connect issue_slots[10].out_uop.dst_rtype, slots_10.io.out_uop.dst_rtype connect issue_slots[10].out_uop.lrs3, slots_10.io.out_uop.lrs3 connect issue_slots[10].out_uop.lrs2, slots_10.io.out_uop.lrs2 connect issue_slots[10].out_uop.lrs1, slots_10.io.out_uop.lrs1 connect issue_slots[10].out_uop.ldst, slots_10.io.out_uop.ldst connect issue_slots[10].out_uop.ldst_is_rs1, slots_10.io.out_uop.ldst_is_rs1 connect issue_slots[10].out_uop.csr_cmd, slots_10.io.out_uop.csr_cmd connect issue_slots[10].out_uop.flush_on_commit, slots_10.io.out_uop.flush_on_commit connect issue_slots[10].out_uop.is_unique, slots_10.io.out_uop.is_unique connect issue_slots[10].out_uop.uses_stq, slots_10.io.out_uop.uses_stq connect issue_slots[10].out_uop.uses_ldq, slots_10.io.out_uop.uses_ldq connect issue_slots[10].out_uop.mem_signed, slots_10.io.out_uop.mem_signed connect issue_slots[10].out_uop.mem_size, slots_10.io.out_uop.mem_size connect issue_slots[10].out_uop.mem_cmd, slots_10.io.out_uop.mem_cmd connect issue_slots[10].out_uop.exc_cause, slots_10.io.out_uop.exc_cause connect issue_slots[10].out_uop.exception, slots_10.io.out_uop.exception connect issue_slots[10].out_uop.stale_pdst, slots_10.io.out_uop.stale_pdst connect issue_slots[10].out_uop.ppred_busy, slots_10.io.out_uop.ppred_busy connect issue_slots[10].out_uop.prs3_busy, slots_10.io.out_uop.prs3_busy connect issue_slots[10].out_uop.prs2_busy, slots_10.io.out_uop.prs2_busy connect issue_slots[10].out_uop.prs1_busy, slots_10.io.out_uop.prs1_busy connect issue_slots[10].out_uop.ppred, slots_10.io.out_uop.ppred connect issue_slots[10].out_uop.prs3, slots_10.io.out_uop.prs3 connect issue_slots[10].out_uop.prs2, slots_10.io.out_uop.prs2 connect issue_slots[10].out_uop.prs1, slots_10.io.out_uop.prs1 connect issue_slots[10].out_uop.pdst, slots_10.io.out_uop.pdst connect issue_slots[10].out_uop.rxq_idx, slots_10.io.out_uop.rxq_idx connect issue_slots[10].out_uop.stq_idx, slots_10.io.out_uop.stq_idx connect issue_slots[10].out_uop.ldq_idx, slots_10.io.out_uop.ldq_idx connect issue_slots[10].out_uop.rob_idx, slots_10.io.out_uop.rob_idx connect issue_slots[10].out_uop.fp_ctrl.vec, slots_10.io.out_uop.fp_ctrl.vec connect issue_slots[10].out_uop.fp_ctrl.wflags, slots_10.io.out_uop.fp_ctrl.wflags connect issue_slots[10].out_uop.fp_ctrl.sqrt, slots_10.io.out_uop.fp_ctrl.sqrt connect issue_slots[10].out_uop.fp_ctrl.div, slots_10.io.out_uop.fp_ctrl.div connect issue_slots[10].out_uop.fp_ctrl.fma, slots_10.io.out_uop.fp_ctrl.fma connect issue_slots[10].out_uop.fp_ctrl.fastpipe, slots_10.io.out_uop.fp_ctrl.fastpipe connect issue_slots[10].out_uop.fp_ctrl.toint, slots_10.io.out_uop.fp_ctrl.toint connect issue_slots[10].out_uop.fp_ctrl.fromint, slots_10.io.out_uop.fp_ctrl.fromint connect issue_slots[10].out_uop.fp_ctrl.typeTagOut, slots_10.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[10].out_uop.fp_ctrl.typeTagIn, slots_10.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[10].out_uop.fp_ctrl.swap23, slots_10.io.out_uop.fp_ctrl.swap23 connect issue_slots[10].out_uop.fp_ctrl.swap12, slots_10.io.out_uop.fp_ctrl.swap12 connect issue_slots[10].out_uop.fp_ctrl.ren3, slots_10.io.out_uop.fp_ctrl.ren3 connect issue_slots[10].out_uop.fp_ctrl.ren2, slots_10.io.out_uop.fp_ctrl.ren2 connect issue_slots[10].out_uop.fp_ctrl.ren1, slots_10.io.out_uop.fp_ctrl.ren1 connect issue_slots[10].out_uop.fp_ctrl.wen, slots_10.io.out_uop.fp_ctrl.wen connect issue_slots[10].out_uop.fp_ctrl.ldst, slots_10.io.out_uop.fp_ctrl.ldst connect issue_slots[10].out_uop.op2_sel, slots_10.io.out_uop.op2_sel connect issue_slots[10].out_uop.op1_sel, slots_10.io.out_uop.op1_sel connect issue_slots[10].out_uop.imm_packed, slots_10.io.out_uop.imm_packed connect issue_slots[10].out_uop.pimm, slots_10.io.out_uop.pimm connect issue_slots[10].out_uop.imm_sel, slots_10.io.out_uop.imm_sel connect issue_slots[10].out_uop.imm_rename, slots_10.io.out_uop.imm_rename connect issue_slots[10].out_uop.taken, slots_10.io.out_uop.taken connect issue_slots[10].out_uop.pc_lob, slots_10.io.out_uop.pc_lob connect issue_slots[10].out_uop.edge_inst, slots_10.io.out_uop.edge_inst connect issue_slots[10].out_uop.ftq_idx, slots_10.io.out_uop.ftq_idx connect issue_slots[10].out_uop.is_mov, slots_10.io.out_uop.is_mov connect issue_slots[10].out_uop.is_rocc, slots_10.io.out_uop.is_rocc connect issue_slots[10].out_uop.is_sys_pc2epc, slots_10.io.out_uop.is_sys_pc2epc connect issue_slots[10].out_uop.is_eret, slots_10.io.out_uop.is_eret connect issue_slots[10].out_uop.is_amo, slots_10.io.out_uop.is_amo connect issue_slots[10].out_uop.is_sfence, slots_10.io.out_uop.is_sfence connect issue_slots[10].out_uop.is_fencei, slots_10.io.out_uop.is_fencei connect issue_slots[10].out_uop.is_fence, slots_10.io.out_uop.is_fence connect issue_slots[10].out_uop.is_sfb, slots_10.io.out_uop.is_sfb connect issue_slots[10].out_uop.br_type, slots_10.io.out_uop.br_type connect issue_slots[10].out_uop.br_tag, slots_10.io.out_uop.br_tag connect issue_slots[10].out_uop.br_mask, slots_10.io.out_uop.br_mask connect issue_slots[10].out_uop.dis_col_sel, slots_10.io.out_uop.dis_col_sel connect issue_slots[10].out_uop.iw_p3_bypass_hint, slots_10.io.out_uop.iw_p3_bypass_hint connect issue_slots[10].out_uop.iw_p2_bypass_hint, slots_10.io.out_uop.iw_p2_bypass_hint connect issue_slots[10].out_uop.iw_p1_bypass_hint, slots_10.io.out_uop.iw_p1_bypass_hint connect issue_slots[10].out_uop.iw_p2_speculative_child, slots_10.io.out_uop.iw_p2_speculative_child connect issue_slots[10].out_uop.iw_p1_speculative_child, slots_10.io.out_uop.iw_p1_speculative_child connect issue_slots[10].out_uop.iw_issued_partial_dgen, slots_10.io.out_uop.iw_issued_partial_dgen connect issue_slots[10].out_uop.iw_issued_partial_agen, slots_10.io.out_uop.iw_issued_partial_agen connect issue_slots[10].out_uop.iw_issued, slots_10.io.out_uop.iw_issued connect issue_slots[10].out_uop.fu_code[0], slots_10.io.out_uop.fu_code[0] connect issue_slots[10].out_uop.fu_code[1], slots_10.io.out_uop.fu_code[1] connect issue_slots[10].out_uop.fu_code[2], slots_10.io.out_uop.fu_code[2] connect issue_slots[10].out_uop.fu_code[3], slots_10.io.out_uop.fu_code[3] connect issue_slots[10].out_uop.fu_code[4], slots_10.io.out_uop.fu_code[4] connect issue_slots[10].out_uop.fu_code[5], slots_10.io.out_uop.fu_code[5] connect issue_slots[10].out_uop.fu_code[6], slots_10.io.out_uop.fu_code[6] connect issue_slots[10].out_uop.fu_code[7], slots_10.io.out_uop.fu_code[7] connect issue_slots[10].out_uop.fu_code[8], slots_10.io.out_uop.fu_code[8] connect issue_slots[10].out_uop.fu_code[9], slots_10.io.out_uop.fu_code[9] connect issue_slots[10].out_uop.iq_type[0], slots_10.io.out_uop.iq_type[0] connect issue_slots[10].out_uop.iq_type[1], slots_10.io.out_uop.iq_type[1] connect issue_slots[10].out_uop.iq_type[2], slots_10.io.out_uop.iq_type[2] connect issue_slots[10].out_uop.iq_type[3], slots_10.io.out_uop.iq_type[3] connect issue_slots[10].out_uop.debug_pc, slots_10.io.out_uop.debug_pc connect issue_slots[10].out_uop.is_rvc, slots_10.io.out_uop.is_rvc connect issue_slots[10].out_uop.debug_inst, slots_10.io.out_uop.debug_inst connect issue_slots[10].out_uop.inst, slots_10.io.out_uop.inst connect slots_10.io.in_uop.bits.debug_tsrc, issue_slots[10].in_uop.bits.debug_tsrc connect slots_10.io.in_uop.bits.debug_fsrc, issue_slots[10].in_uop.bits.debug_fsrc connect slots_10.io.in_uop.bits.bp_xcpt_if, issue_slots[10].in_uop.bits.bp_xcpt_if connect slots_10.io.in_uop.bits.bp_debug_if, issue_slots[10].in_uop.bits.bp_debug_if connect slots_10.io.in_uop.bits.xcpt_ma_if, issue_slots[10].in_uop.bits.xcpt_ma_if connect slots_10.io.in_uop.bits.xcpt_ae_if, issue_slots[10].in_uop.bits.xcpt_ae_if connect slots_10.io.in_uop.bits.xcpt_pf_if, issue_slots[10].in_uop.bits.xcpt_pf_if connect slots_10.io.in_uop.bits.fp_typ, issue_slots[10].in_uop.bits.fp_typ connect slots_10.io.in_uop.bits.fp_rm, issue_slots[10].in_uop.bits.fp_rm connect slots_10.io.in_uop.bits.fp_val, issue_slots[10].in_uop.bits.fp_val connect slots_10.io.in_uop.bits.fcn_op, issue_slots[10].in_uop.bits.fcn_op connect slots_10.io.in_uop.bits.fcn_dw, issue_slots[10].in_uop.bits.fcn_dw connect slots_10.io.in_uop.bits.frs3_en, issue_slots[10].in_uop.bits.frs3_en connect slots_10.io.in_uop.bits.lrs2_rtype, issue_slots[10].in_uop.bits.lrs2_rtype connect slots_10.io.in_uop.bits.lrs1_rtype, issue_slots[10].in_uop.bits.lrs1_rtype connect slots_10.io.in_uop.bits.dst_rtype, issue_slots[10].in_uop.bits.dst_rtype connect slots_10.io.in_uop.bits.lrs3, issue_slots[10].in_uop.bits.lrs3 connect slots_10.io.in_uop.bits.lrs2, issue_slots[10].in_uop.bits.lrs2 connect slots_10.io.in_uop.bits.lrs1, issue_slots[10].in_uop.bits.lrs1 connect slots_10.io.in_uop.bits.ldst, issue_slots[10].in_uop.bits.ldst connect slots_10.io.in_uop.bits.ldst_is_rs1, issue_slots[10].in_uop.bits.ldst_is_rs1 connect slots_10.io.in_uop.bits.csr_cmd, issue_slots[10].in_uop.bits.csr_cmd connect slots_10.io.in_uop.bits.flush_on_commit, issue_slots[10].in_uop.bits.flush_on_commit connect slots_10.io.in_uop.bits.is_unique, issue_slots[10].in_uop.bits.is_unique connect slots_10.io.in_uop.bits.uses_stq, issue_slots[10].in_uop.bits.uses_stq connect slots_10.io.in_uop.bits.uses_ldq, issue_slots[10].in_uop.bits.uses_ldq connect slots_10.io.in_uop.bits.mem_signed, issue_slots[10].in_uop.bits.mem_signed connect slots_10.io.in_uop.bits.mem_size, issue_slots[10].in_uop.bits.mem_size connect slots_10.io.in_uop.bits.mem_cmd, issue_slots[10].in_uop.bits.mem_cmd connect slots_10.io.in_uop.bits.exc_cause, issue_slots[10].in_uop.bits.exc_cause connect slots_10.io.in_uop.bits.exception, issue_slots[10].in_uop.bits.exception connect slots_10.io.in_uop.bits.stale_pdst, issue_slots[10].in_uop.bits.stale_pdst connect slots_10.io.in_uop.bits.ppred_busy, issue_slots[10].in_uop.bits.ppred_busy connect slots_10.io.in_uop.bits.prs3_busy, issue_slots[10].in_uop.bits.prs3_busy connect slots_10.io.in_uop.bits.prs2_busy, issue_slots[10].in_uop.bits.prs2_busy connect slots_10.io.in_uop.bits.prs1_busy, issue_slots[10].in_uop.bits.prs1_busy connect slots_10.io.in_uop.bits.ppred, issue_slots[10].in_uop.bits.ppred connect slots_10.io.in_uop.bits.prs3, issue_slots[10].in_uop.bits.prs3 connect slots_10.io.in_uop.bits.prs2, issue_slots[10].in_uop.bits.prs2 connect slots_10.io.in_uop.bits.prs1, issue_slots[10].in_uop.bits.prs1 connect slots_10.io.in_uop.bits.pdst, issue_slots[10].in_uop.bits.pdst connect slots_10.io.in_uop.bits.rxq_idx, issue_slots[10].in_uop.bits.rxq_idx connect slots_10.io.in_uop.bits.stq_idx, issue_slots[10].in_uop.bits.stq_idx connect slots_10.io.in_uop.bits.ldq_idx, issue_slots[10].in_uop.bits.ldq_idx connect slots_10.io.in_uop.bits.rob_idx, issue_slots[10].in_uop.bits.rob_idx connect slots_10.io.in_uop.bits.fp_ctrl.vec, issue_slots[10].in_uop.bits.fp_ctrl.vec connect slots_10.io.in_uop.bits.fp_ctrl.wflags, issue_slots[10].in_uop.bits.fp_ctrl.wflags connect slots_10.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[10].in_uop.bits.fp_ctrl.sqrt connect slots_10.io.in_uop.bits.fp_ctrl.div, issue_slots[10].in_uop.bits.fp_ctrl.div connect slots_10.io.in_uop.bits.fp_ctrl.fma, issue_slots[10].in_uop.bits.fp_ctrl.fma connect slots_10.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].in_uop.bits.fp_ctrl.fastpipe connect slots_10.io.in_uop.bits.fp_ctrl.toint, issue_slots[10].in_uop.bits.fp_ctrl.toint connect slots_10.io.in_uop.bits.fp_ctrl.fromint, issue_slots[10].in_uop.bits.fp_ctrl.fromint connect slots_10.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut connect slots_10.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn connect slots_10.io.in_uop.bits.fp_ctrl.swap23, issue_slots[10].in_uop.bits.fp_ctrl.swap23 connect slots_10.io.in_uop.bits.fp_ctrl.swap12, issue_slots[10].in_uop.bits.fp_ctrl.swap12 connect slots_10.io.in_uop.bits.fp_ctrl.ren3, issue_slots[10].in_uop.bits.fp_ctrl.ren3 connect slots_10.io.in_uop.bits.fp_ctrl.ren2, issue_slots[10].in_uop.bits.fp_ctrl.ren2 connect slots_10.io.in_uop.bits.fp_ctrl.ren1, issue_slots[10].in_uop.bits.fp_ctrl.ren1 connect slots_10.io.in_uop.bits.fp_ctrl.wen, issue_slots[10].in_uop.bits.fp_ctrl.wen connect slots_10.io.in_uop.bits.fp_ctrl.ldst, issue_slots[10].in_uop.bits.fp_ctrl.ldst connect slots_10.io.in_uop.bits.op2_sel, issue_slots[10].in_uop.bits.op2_sel connect slots_10.io.in_uop.bits.op1_sel, issue_slots[10].in_uop.bits.op1_sel connect slots_10.io.in_uop.bits.imm_packed, issue_slots[10].in_uop.bits.imm_packed connect slots_10.io.in_uop.bits.pimm, issue_slots[10].in_uop.bits.pimm connect slots_10.io.in_uop.bits.imm_sel, issue_slots[10].in_uop.bits.imm_sel connect slots_10.io.in_uop.bits.imm_rename, issue_slots[10].in_uop.bits.imm_rename connect slots_10.io.in_uop.bits.taken, issue_slots[10].in_uop.bits.taken connect slots_10.io.in_uop.bits.pc_lob, issue_slots[10].in_uop.bits.pc_lob connect slots_10.io.in_uop.bits.edge_inst, issue_slots[10].in_uop.bits.edge_inst connect slots_10.io.in_uop.bits.ftq_idx, issue_slots[10].in_uop.bits.ftq_idx connect slots_10.io.in_uop.bits.is_mov, issue_slots[10].in_uop.bits.is_mov connect slots_10.io.in_uop.bits.is_rocc, issue_slots[10].in_uop.bits.is_rocc connect slots_10.io.in_uop.bits.is_sys_pc2epc, issue_slots[10].in_uop.bits.is_sys_pc2epc connect slots_10.io.in_uop.bits.is_eret, issue_slots[10].in_uop.bits.is_eret connect slots_10.io.in_uop.bits.is_amo, issue_slots[10].in_uop.bits.is_amo connect slots_10.io.in_uop.bits.is_sfence, issue_slots[10].in_uop.bits.is_sfence connect slots_10.io.in_uop.bits.is_fencei, issue_slots[10].in_uop.bits.is_fencei connect slots_10.io.in_uop.bits.is_fence, issue_slots[10].in_uop.bits.is_fence connect slots_10.io.in_uop.bits.is_sfb, issue_slots[10].in_uop.bits.is_sfb connect slots_10.io.in_uop.bits.br_type, issue_slots[10].in_uop.bits.br_type connect slots_10.io.in_uop.bits.br_tag, issue_slots[10].in_uop.bits.br_tag connect slots_10.io.in_uop.bits.br_mask, issue_slots[10].in_uop.bits.br_mask connect slots_10.io.in_uop.bits.dis_col_sel, issue_slots[10].in_uop.bits.dis_col_sel connect slots_10.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[10].in_uop.bits.iw_p3_bypass_hint connect slots_10.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[10].in_uop.bits.iw_p2_bypass_hint connect slots_10.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[10].in_uop.bits.iw_p1_bypass_hint connect slots_10.io.in_uop.bits.iw_p2_speculative_child, issue_slots[10].in_uop.bits.iw_p2_speculative_child connect slots_10.io.in_uop.bits.iw_p1_speculative_child, issue_slots[10].in_uop.bits.iw_p1_speculative_child connect slots_10.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[10].in_uop.bits.iw_issued_partial_dgen connect slots_10.io.in_uop.bits.iw_issued_partial_agen, issue_slots[10].in_uop.bits.iw_issued_partial_agen connect slots_10.io.in_uop.bits.iw_issued, issue_slots[10].in_uop.bits.iw_issued connect slots_10.io.in_uop.bits.fu_code[0], issue_slots[10].in_uop.bits.fu_code[0] connect slots_10.io.in_uop.bits.fu_code[1], issue_slots[10].in_uop.bits.fu_code[1] connect slots_10.io.in_uop.bits.fu_code[2], issue_slots[10].in_uop.bits.fu_code[2] connect slots_10.io.in_uop.bits.fu_code[3], issue_slots[10].in_uop.bits.fu_code[3] connect slots_10.io.in_uop.bits.fu_code[4], issue_slots[10].in_uop.bits.fu_code[4] connect slots_10.io.in_uop.bits.fu_code[5], issue_slots[10].in_uop.bits.fu_code[5] connect slots_10.io.in_uop.bits.fu_code[6], issue_slots[10].in_uop.bits.fu_code[6] connect slots_10.io.in_uop.bits.fu_code[7], issue_slots[10].in_uop.bits.fu_code[7] connect slots_10.io.in_uop.bits.fu_code[8], issue_slots[10].in_uop.bits.fu_code[8] connect slots_10.io.in_uop.bits.fu_code[9], issue_slots[10].in_uop.bits.fu_code[9] connect slots_10.io.in_uop.bits.iq_type[0], issue_slots[10].in_uop.bits.iq_type[0] connect slots_10.io.in_uop.bits.iq_type[1], issue_slots[10].in_uop.bits.iq_type[1] connect slots_10.io.in_uop.bits.iq_type[2], issue_slots[10].in_uop.bits.iq_type[2] connect slots_10.io.in_uop.bits.iq_type[3], issue_slots[10].in_uop.bits.iq_type[3] connect slots_10.io.in_uop.bits.debug_pc, issue_slots[10].in_uop.bits.debug_pc connect slots_10.io.in_uop.bits.is_rvc, issue_slots[10].in_uop.bits.is_rvc connect slots_10.io.in_uop.bits.debug_inst, issue_slots[10].in_uop.bits.debug_inst connect slots_10.io.in_uop.bits.inst, issue_slots[10].in_uop.bits.inst connect slots_10.io.in_uop.valid, issue_slots[10].in_uop.valid connect issue_slots[10].iss_uop.debug_tsrc, slots_10.io.iss_uop.debug_tsrc connect issue_slots[10].iss_uop.debug_fsrc, slots_10.io.iss_uop.debug_fsrc connect issue_slots[10].iss_uop.bp_xcpt_if, slots_10.io.iss_uop.bp_xcpt_if connect issue_slots[10].iss_uop.bp_debug_if, slots_10.io.iss_uop.bp_debug_if connect issue_slots[10].iss_uop.xcpt_ma_if, slots_10.io.iss_uop.xcpt_ma_if connect issue_slots[10].iss_uop.xcpt_ae_if, slots_10.io.iss_uop.xcpt_ae_if connect issue_slots[10].iss_uop.xcpt_pf_if, slots_10.io.iss_uop.xcpt_pf_if connect issue_slots[10].iss_uop.fp_typ, slots_10.io.iss_uop.fp_typ connect issue_slots[10].iss_uop.fp_rm, slots_10.io.iss_uop.fp_rm connect issue_slots[10].iss_uop.fp_val, slots_10.io.iss_uop.fp_val connect issue_slots[10].iss_uop.fcn_op, slots_10.io.iss_uop.fcn_op connect issue_slots[10].iss_uop.fcn_dw, slots_10.io.iss_uop.fcn_dw connect issue_slots[10].iss_uop.frs3_en, slots_10.io.iss_uop.frs3_en connect issue_slots[10].iss_uop.lrs2_rtype, slots_10.io.iss_uop.lrs2_rtype connect issue_slots[10].iss_uop.lrs1_rtype, slots_10.io.iss_uop.lrs1_rtype connect issue_slots[10].iss_uop.dst_rtype, slots_10.io.iss_uop.dst_rtype connect issue_slots[10].iss_uop.lrs3, slots_10.io.iss_uop.lrs3 connect issue_slots[10].iss_uop.lrs2, slots_10.io.iss_uop.lrs2 connect issue_slots[10].iss_uop.lrs1, slots_10.io.iss_uop.lrs1 connect issue_slots[10].iss_uop.ldst, slots_10.io.iss_uop.ldst connect issue_slots[10].iss_uop.ldst_is_rs1, slots_10.io.iss_uop.ldst_is_rs1 connect issue_slots[10].iss_uop.csr_cmd, slots_10.io.iss_uop.csr_cmd connect issue_slots[10].iss_uop.flush_on_commit, slots_10.io.iss_uop.flush_on_commit connect issue_slots[10].iss_uop.is_unique, slots_10.io.iss_uop.is_unique connect issue_slots[10].iss_uop.uses_stq, slots_10.io.iss_uop.uses_stq connect issue_slots[10].iss_uop.uses_ldq, slots_10.io.iss_uop.uses_ldq connect issue_slots[10].iss_uop.mem_signed, slots_10.io.iss_uop.mem_signed connect issue_slots[10].iss_uop.mem_size, slots_10.io.iss_uop.mem_size connect issue_slots[10].iss_uop.mem_cmd, slots_10.io.iss_uop.mem_cmd connect issue_slots[10].iss_uop.exc_cause, slots_10.io.iss_uop.exc_cause connect issue_slots[10].iss_uop.exception, slots_10.io.iss_uop.exception connect issue_slots[10].iss_uop.stale_pdst, slots_10.io.iss_uop.stale_pdst connect issue_slots[10].iss_uop.ppred_busy, slots_10.io.iss_uop.ppred_busy connect issue_slots[10].iss_uop.prs3_busy, slots_10.io.iss_uop.prs3_busy connect issue_slots[10].iss_uop.prs2_busy, slots_10.io.iss_uop.prs2_busy connect issue_slots[10].iss_uop.prs1_busy, slots_10.io.iss_uop.prs1_busy connect issue_slots[10].iss_uop.ppred, slots_10.io.iss_uop.ppred connect issue_slots[10].iss_uop.prs3, slots_10.io.iss_uop.prs3 connect issue_slots[10].iss_uop.prs2, slots_10.io.iss_uop.prs2 connect issue_slots[10].iss_uop.prs1, slots_10.io.iss_uop.prs1 connect issue_slots[10].iss_uop.pdst, slots_10.io.iss_uop.pdst connect issue_slots[10].iss_uop.rxq_idx, slots_10.io.iss_uop.rxq_idx connect issue_slots[10].iss_uop.stq_idx, slots_10.io.iss_uop.stq_idx connect issue_slots[10].iss_uop.ldq_idx, slots_10.io.iss_uop.ldq_idx connect issue_slots[10].iss_uop.rob_idx, slots_10.io.iss_uop.rob_idx connect issue_slots[10].iss_uop.fp_ctrl.vec, slots_10.io.iss_uop.fp_ctrl.vec connect issue_slots[10].iss_uop.fp_ctrl.wflags, slots_10.io.iss_uop.fp_ctrl.wflags connect issue_slots[10].iss_uop.fp_ctrl.sqrt, slots_10.io.iss_uop.fp_ctrl.sqrt connect issue_slots[10].iss_uop.fp_ctrl.div, slots_10.io.iss_uop.fp_ctrl.div connect issue_slots[10].iss_uop.fp_ctrl.fma, slots_10.io.iss_uop.fp_ctrl.fma connect issue_slots[10].iss_uop.fp_ctrl.fastpipe, slots_10.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[10].iss_uop.fp_ctrl.toint, slots_10.io.iss_uop.fp_ctrl.toint connect issue_slots[10].iss_uop.fp_ctrl.fromint, slots_10.io.iss_uop.fp_ctrl.fromint connect issue_slots[10].iss_uop.fp_ctrl.typeTagOut, slots_10.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[10].iss_uop.fp_ctrl.typeTagIn, slots_10.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[10].iss_uop.fp_ctrl.swap23, slots_10.io.iss_uop.fp_ctrl.swap23 connect issue_slots[10].iss_uop.fp_ctrl.swap12, slots_10.io.iss_uop.fp_ctrl.swap12 connect issue_slots[10].iss_uop.fp_ctrl.ren3, slots_10.io.iss_uop.fp_ctrl.ren3 connect issue_slots[10].iss_uop.fp_ctrl.ren2, slots_10.io.iss_uop.fp_ctrl.ren2 connect issue_slots[10].iss_uop.fp_ctrl.ren1, slots_10.io.iss_uop.fp_ctrl.ren1 connect issue_slots[10].iss_uop.fp_ctrl.wen, slots_10.io.iss_uop.fp_ctrl.wen connect issue_slots[10].iss_uop.fp_ctrl.ldst, slots_10.io.iss_uop.fp_ctrl.ldst connect issue_slots[10].iss_uop.op2_sel, slots_10.io.iss_uop.op2_sel connect issue_slots[10].iss_uop.op1_sel, slots_10.io.iss_uop.op1_sel connect issue_slots[10].iss_uop.imm_packed, slots_10.io.iss_uop.imm_packed connect issue_slots[10].iss_uop.pimm, slots_10.io.iss_uop.pimm connect issue_slots[10].iss_uop.imm_sel, slots_10.io.iss_uop.imm_sel connect issue_slots[10].iss_uop.imm_rename, slots_10.io.iss_uop.imm_rename connect issue_slots[10].iss_uop.taken, slots_10.io.iss_uop.taken connect issue_slots[10].iss_uop.pc_lob, slots_10.io.iss_uop.pc_lob connect issue_slots[10].iss_uop.edge_inst, slots_10.io.iss_uop.edge_inst connect issue_slots[10].iss_uop.ftq_idx, slots_10.io.iss_uop.ftq_idx connect issue_slots[10].iss_uop.is_mov, slots_10.io.iss_uop.is_mov connect issue_slots[10].iss_uop.is_rocc, slots_10.io.iss_uop.is_rocc connect issue_slots[10].iss_uop.is_sys_pc2epc, slots_10.io.iss_uop.is_sys_pc2epc connect issue_slots[10].iss_uop.is_eret, slots_10.io.iss_uop.is_eret connect issue_slots[10].iss_uop.is_amo, slots_10.io.iss_uop.is_amo connect issue_slots[10].iss_uop.is_sfence, slots_10.io.iss_uop.is_sfence connect issue_slots[10].iss_uop.is_fencei, slots_10.io.iss_uop.is_fencei connect issue_slots[10].iss_uop.is_fence, slots_10.io.iss_uop.is_fence connect issue_slots[10].iss_uop.is_sfb, slots_10.io.iss_uop.is_sfb connect issue_slots[10].iss_uop.br_type, slots_10.io.iss_uop.br_type connect issue_slots[10].iss_uop.br_tag, slots_10.io.iss_uop.br_tag connect issue_slots[10].iss_uop.br_mask, slots_10.io.iss_uop.br_mask connect issue_slots[10].iss_uop.dis_col_sel, slots_10.io.iss_uop.dis_col_sel connect issue_slots[10].iss_uop.iw_p3_bypass_hint, slots_10.io.iss_uop.iw_p3_bypass_hint connect issue_slots[10].iss_uop.iw_p2_bypass_hint, slots_10.io.iss_uop.iw_p2_bypass_hint connect issue_slots[10].iss_uop.iw_p1_bypass_hint, slots_10.io.iss_uop.iw_p1_bypass_hint connect issue_slots[10].iss_uop.iw_p2_speculative_child, slots_10.io.iss_uop.iw_p2_speculative_child connect issue_slots[10].iss_uop.iw_p1_speculative_child, slots_10.io.iss_uop.iw_p1_speculative_child connect issue_slots[10].iss_uop.iw_issued_partial_dgen, slots_10.io.iss_uop.iw_issued_partial_dgen connect issue_slots[10].iss_uop.iw_issued_partial_agen, slots_10.io.iss_uop.iw_issued_partial_agen connect issue_slots[10].iss_uop.iw_issued, slots_10.io.iss_uop.iw_issued connect issue_slots[10].iss_uop.fu_code[0], slots_10.io.iss_uop.fu_code[0] connect issue_slots[10].iss_uop.fu_code[1], slots_10.io.iss_uop.fu_code[1] connect issue_slots[10].iss_uop.fu_code[2], slots_10.io.iss_uop.fu_code[2] connect issue_slots[10].iss_uop.fu_code[3], slots_10.io.iss_uop.fu_code[3] connect issue_slots[10].iss_uop.fu_code[4], slots_10.io.iss_uop.fu_code[4] connect issue_slots[10].iss_uop.fu_code[5], slots_10.io.iss_uop.fu_code[5] connect issue_slots[10].iss_uop.fu_code[6], slots_10.io.iss_uop.fu_code[6] connect issue_slots[10].iss_uop.fu_code[7], slots_10.io.iss_uop.fu_code[7] connect issue_slots[10].iss_uop.fu_code[8], slots_10.io.iss_uop.fu_code[8] connect issue_slots[10].iss_uop.fu_code[9], slots_10.io.iss_uop.fu_code[9] connect issue_slots[10].iss_uop.iq_type[0], slots_10.io.iss_uop.iq_type[0] connect issue_slots[10].iss_uop.iq_type[1], slots_10.io.iss_uop.iq_type[1] connect issue_slots[10].iss_uop.iq_type[2], slots_10.io.iss_uop.iq_type[2] connect issue_slots[10].iss_uop.iq_type[3], slots_10.io.iss_uop.iq_type[3] connect issue_slots[10].iss_uop.debug_pc, slots_10.io.iss_uop.debug_pc connect issue_slots[10].iss_uop.is_rvc, slots_10.io.iss_uop.is_rvc connect issue_slots[10].iss_uop.debug_inst, slots_10.io.iss_uop.debug_inst connect issue_slots[10].iss_uop.inst, slots_10.io.iss_uop.inst connect slots_10.io.grant, issue_slots[10].grant connect issue_slots[10].request, slots_10.io.request connect issue_slots[10].will_be_valid, slots_10.io.will_be_valid connect issue_slots[10].valid, slots_10.io.valid connect slots_11.io.child_rebusys, issue_slots[11].child_rebusys connect slots_11.io.pred_wakeup_port.bits, issue_slots[11].pred_wakeup_port.bits connect slots_11.io.pred_wakeup_port.valid, issue_slots[11].pred_wakeup_port.valid connect slots_11.io.wakeup_ports[0].bits.rebusy, issue_slots[11].wakeup_ports[0].bits.rebusy connect slots_11.io.wakeup_ports[0].bits.speculative_mask, issue_slots[11].wakeup_ports[0].bits.speculative_mask connect slots_11.io.wakeup_ports[0].bits.bypassable, issue_slots[11].wakeup_ports[0].bits.bypassable connect slots_11.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[0].bits.uop.debug_tsrc connect slots_11.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[0].bits.uop.debug_fsrc connect slots_11.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_11.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[0].bits.uop.bp_debug_if connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_11.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[11].wakeup_ports[0].bits.uop.fp_typ connect slots_11.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[11].wakeup_ports[0].bits.uop.fp_rm connect slots_11.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[11].wakeup_ports[0].bits.uop.fp_val connect slots_11.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[11].wakeup_ports[0].bits.uop.fcn_op connect slots_11.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[0].bits.uop.fcn_dw connect slots_11.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[11].wakeup_ports[0].bits.uop.frs3_en connect slots_11.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_11.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_11.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[0].bits.uop.dst_rtype connect slots_11.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[11].wakeup_ports[0].bits.uop.lrs3 connect slots_11.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[11].wakeup_ports[0].bits.uop.lrs2 connect slots_11.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[11].wakeup_ports[0].bits.uop.lrs1 connect slots_11.io.wakeup_ports[0].bits.uop.ldst, issue_slots[11].wakeup_ports[0].bits.uop.ldst connect slots_11.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_11.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[0].bits.uop.csr_cmd connect slots_11.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[0].bits.uop.flush_on_commit connect slots_11.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[11].wakeup_ports[0].bits.uop.is_unique connect slots_11.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[11].wakeup_ports[0].bits.uop.uses_stq connect slots_11.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[0].bits.uop.uses_ldq connect slots_11.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[11].wakeup_ports[0].bits.uop.mem_signed connect slots_11.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[11].wakeup_ports[0].bits.uop.mem_size connect slots_11.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[0].bits.uop.mem_cmd connect slots_11.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[11].wakeup_ports[0].bits.uop.exc_cause connect slots_11.io.wakeup_ports[0].bits.uop.exception, issue_slots[11].wakeup_ports[0].bits.uop.exception connect slots_11.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[0].bits.uop.stale_pdst connect slots_11.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[0].bits.uop.ppred_busy connect slots_11.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs3_busy connect slots_11.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs2_busy connect slots_11.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs1_busy connect slots_11.io.wakeup_ports[0].bits.uop.ppred, issue_slots[11].wakeup_ports[0].bits.uop.ppred connect slots_11.io.wakeup_ports[0].bits.uop.prs3, issue_slots[11].wakeup_ports[0].bits.uop.prs3 connect slots_11.io.wakeup_ports[0].bits.uop.prs2, issue_slots[11].wakeup_ports[0].bits.uop.prs2 connect slots_11.io.wakeup_ports[0].bits.uop.prs1, issue_slots[11].wakeup_ports[0].bits.uop.prs1 connect slots_11.io.wakeup_ports[0].bits.uop.pdst, issue_slots[11].wakeup_ports[0].bits.uop.pdst connect slots_11.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[0].bits.uop.rxq_idx connect slots_11.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[11].wakeup_ports[0].bits.uop.stq_idx connect slots_11.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[0].bits.uop.ldq_idx connect slots_11.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[11].wakeup_ports[0].bits.uop.rob_idx connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_11.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[11].wakeup_ports[0].bits.uop.op2_sel connect slots_11.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[11].wakeup_ports[0].bits.uop.op1_sel connect slots_11.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[11].wakeup_ports[0].bits.uop.imm_packed connect slots_11.io.wakeup_ports[0].bits.uop.pimm, issue_slots[11].wakeup_ports[0].bits.uop.pimm connect slots_11.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[11].wakeup_ports[0].bits.uop.imm_sel connect slots_11.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[11].wakeup_ports[0].bits.uop.imm_rename connect slots_11.io.wakeup_ports[0].bits.uop.taken, issue_slots[11].wakeup_ports[0].bits.uop.taken connect slots_11.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[11].wakeup_ports[0].bits.uop.pc_lob connect slots_11.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[11].wakeup_ports[0].bits.uop.edge_inst connect slots_11.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[0].bits.uop.ftq_idx connect slots_11.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[11].wakeup_ports[0].bits.uop.is_mov connect slots_11.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[11].wakeup_ports[0].bits.uop.is_rocc connect slots_11.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_11.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[11].wakeup_ports[0].bits.uop.is_eret connect slots_11.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[11].wakeup_ports[0].bits.uop.is_amo connect slots_11.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[11].wakeup_ports[0].bits.uop.is_sfence connect slots_11.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[11].wakeup_ports[0].bits.uop.is_fencei connect slots_11.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[11].wakeup_ports[0].bits.uop.is_fence connect slots_11.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[11].wakeup_ports[0].bits.uop.is_sfb connect slots_11.io.wakeup_ports[0].bits.uop.br_type, issue_slots[11].wakeup_ports[0].bits.uop.br_type connect slots_11.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[11].wakeup_ports[0].bits.uop.br_tag connect slots_11.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[11].wakeup_ports[0].bits.uop.br_mask connect slots_11.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[0].bits.uop.dis_col_sel connect slots_11.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_11.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_11.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_11.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_11.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[0] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[1] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[2] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[3] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[4] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[5] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[6] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[7] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[8] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[9] connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[0] connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[1] connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[2] connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[3] connect slots_11.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[11].wakeup_ports[0].bits.uop.debug_pc connect slots_11.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[11].wakeup_ports[0].bits.uop.is_rvc connect slots_11.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[11].wakeup_ports[0].bits.uop.debug_inst connect slots_11.io.wakeup_ports[0].bits.uop.inst, issue_slots[11].wakeup_ports[0].bits.uop.inst connect slots_11.io.wakeup_ports[0].valid, issue_slots[11].wakeup_ports[0].valid connect slots_11.io.wakeup_ports[1].bits.rebusy, issue_slots[11].wakeup_ports[1].bits.rebusy connect slots_11.io.wakeup_ports[1].bits.speculative_mask, issue_slots[11].wakeup_ports[1].bits.speculative_mask connect slots_11.io.wakeup_ports[1].bits.bypassable, issue_slots[11].wakeup_ports[1].bits.bypassable connect slots_11.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[1].bits.uop.debug_tsrc connect slots_11.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[1].bits.uop.debug_fsrc connect slots_11.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_11.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[1].bits.uop.bp_debug_if connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_11.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[11].wakeup_ports[1].bits.uop.fp_typ connect slots_11.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[11].wakeup_ports[1].bits.uop.fp_rm connect slots_11.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[11].wakeup_ports[1].bits.uop.fp_val connect slots_11.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[11].wakeup_ports[1].bits.uop.fcn_op connect slots_11.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[1].bits.uop.fcn_dw connect slots_11.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[11].wakeup_ports[1].bits.uop.frs3_en connect slots_11.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_11.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_11.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[1].bits.uop.dst_rtype connect slots_11.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[11].wakeup_ports[1].bits.uop.lrs3 connect slots_11.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[11].wakeup_ports[1].bits.uop.lrs2 connect slots_11.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[11].wakeup_ports[1].bits.uop.lrs1 connect slots_11.io.wakeup_ports[1].bits.uop.ldst, issue_slots[11].wakeup_ports[1].bits.uop.ldst connect slots_11.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_11.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[1].bits.uop.csr_cmd connect slots_11.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[1].bits.uop.flush_on_commit connect slots_11.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[11].wakeup_ports[1].bits.uop.is_unique connect slots_11.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[11].wakeup_ports[1].bits.uop.uses_stq connect slots_11.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[1].bits.uop.uses_ldq connect slots_11.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[11].wakeup_ports[1].bits.uop.mem_signed connect slots_11.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[11].wakeup_ports[1].bits.uop.mem_size connect slots_11.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[1].bits.uop.mem_cmd connect slots_11.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[11].wakeup_ports[1].bits.uop.exc_cause connect slots_11.io.wakeup_ports[1].bits.uop.exception, issue_slots[11].wakeup_ports[1].bits.uop.exception connect slots_11.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[1].bits.uop.stale_pdst connect slots_11.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[1].bits.uop.ppred_busy connect slots_11.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs3_busy connect slots_11.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs2_busy connect slots_11.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs1_busy connect slots_11.io.wakeup_ports[1].bits.uop.ppred, issue_slots[11].wakeup_ports[1].bits.uop.ppred connect slots_11.io.wakeup_ports[1].bits.uop.prs3, issue_slots[11].wakeup_ports[1].bits.uop.prs3 connect slots_11.io.wakeup_ports[1].bits.uop.prs2, issue_slots[11].wakeup_ports[1].bits.uop.prs2 connect slots_11.io.wakeup_ports[1].bits.uop.prs1, issue_slots[11].wakeup_ports[1].bits.uop.prs1 connect slots_11.io.wakeup_ports[1].bits.uop.pdst, issue_slots[11].wakeup_ports[1].bits.uop.pdst connect slots_11.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[1].bits.uop.rxq_idx connect slots_11.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[11].wakeup_ports[1].bits.uop.stq_idx connect slots_11.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[1].bits.uop.ldq_idx connect slots_11.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[11].wakeup_ports[1].bits.uop.rob_idx connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_11.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[11].wakeup_ports[1].bits.uop.op2_sel connect slots_11.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[11].wakeup_ports[1].bits.uop.op1_sel connect slots_11.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[11].wakeup_ports[1].bits.uop.imm_packed connect slots_11.io.wakeup_ports[1].bits.uop.pimm, issue_slots[11].wakeup_ports[1].bits.uop.pimm connect slots_11.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[11].wakeup_ports[1].bits.uop.imm_sel connect slots_11.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[11].wakeup_ports[1].bits.uop.imm_rename connect slots_11.io.wakeup_ports[1].bits.uop.taken, issue_slots[11].wakeup_ports[1].bits.uop.taken connect slots_11.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[11].wakeup_ports[1].bits.uop.pc_lob connect slots_11.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[11].wakeup_ports[1].bits.uop.edge_inst connect slots_11.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[1].bits.uop.ftq_idx connect slots_11.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[11].wakeup_ports[1].bits.uop.is_mov connect slots_11.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[11].wakeup_ports[1].bits.uop.is_rocc connect slots_11.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_11.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[11].wakeup_ports[1].bits.uop.is_eret connect slots_11.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[11].wakeup_ports[1].bits.uop.is_amo connect slots_11.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[11].wakeup_ports[1].bits.uop.is_sfence connect slots_11.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[11].wakeup_ports[1].bits.uop.is_fencei connect slots_11.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[11].wakeup_ports[1].bits.uop.is_fence connect slots_11.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[11].wakeup_ports[1].bits.uop.is_sfb connect slots_11.io.wakeup_ports[1].bits.uop.br_type, issue_slots[11].wakeup_ports[1].bits.uop.br_type connect slots_11.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[11].wakeup_ports[1].bits.uop.br_tag connect slots_11.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[11].wakeup_ports[1].bits.uop.br_mask connect slots_11.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[1].bits.uop.dis_col_sel connect slots_11.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_11.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_11.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_11.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_11.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[0] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[1] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[2] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[3] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[4] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[5] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[6] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[7] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[8] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[9] connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[0] connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[1] connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[2] connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[3] connect slots_11.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[11].wakeup_ports[1].bits.uop.debug_pc connect slots_11.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[11].wakeup_ports[1].bits.uop.is_rvc connect slots_11.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[11].wakeup_ports[1].bits.uop.debug_inst connect slots_11.io.wakeup_ports[1].bits.uop.inst, issue_slots[11].wakeup_ports[1].bits.uop.inst connect slots_11.io.wakeup_ports[1].valid, issue_slots[11].wakeup_ports[1].valid connect slots_11.io.wakeup_ports[2].bits.rebusy, issue_slots[11].wakeup_ports[2].bits.rebusy connect slots_11.io.wakeup_ports[2].bits.speculative_mask, issue_slots[11].wakeup_ports[2].bits.speculative_mask connect slots_11.io.wakeup_ports[2].bits.bypassable, issue_slots[11].wakeup_ports[2].bits.bypassable connect slots_11.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[2].bits.uop.debug_tsrc connect slots_11.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[2].bits.uop.debug_fsrc connect slots_11.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_11.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[2].bits.uop.bp_debug_if connect slots_11.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_11.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_11.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_11.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[11].wakeup_ports[2].bits.uop.fp_typ connect slots_11.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[11].wakeup_ports[2].bits.uop.fp_rm connect slots_11.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[11].wakeup_ports[2].bits.uop.fp_val connect slots_11.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[11].wakeup_ports[2].bits.uop.fcn_op connect slots_11.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[2].bits.uop.fcn_dw connect slots_11.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[11].wakeup_ports[2].bits.uop.frs3_en connect slots_11.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_11.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_11.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[2].bits.uop.dst_rtype connect slots_11.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[11].wakeup_ports[2].bits.uop.lrs3 connect slots_11.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[11].wakeup_ports[2].bits.uop.lrs2 connect slots_11.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[11].wakeup_ports[2].bits.uop.lrs1 connect slots_11.io.wakeup_ports[2].bits.uop.ldst, issue_slots[11].wakeup_ports[2].bits.uop.ldst connect slots_11.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_11.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[2].bits.uop.csr_cmd connect slots_11.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[2].bits.uop.flush_on_commit connect slots_11.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[11].wakeup_ports[2].bits.uop.is_unique connect slots_11.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[11].wakeup_ports[2].bits.uop.uses_stq connect slots_11.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[2].bits.uop.uses_ldq connect slots_11.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[11].wakeup_ports[2].bits.uop.mem_signed connect slots_11.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[11].wakeup_ports[2].bits.uop.mem_size connect slots_11.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[2].bits.uop.mem_cmd connect slots_11.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[11].wakeup_ports[2].bits.uop.exc_cause connect slots_11.io.wakeup_ports[2].bits.uop.exception, issue_slots[11].wakeup_ports[2].bits.uop.exception connect slots_11.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[2].bits.uop.stale_pdst connect slots_11.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[2].bits.uop.ppred_busy connect slots_11.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[2].bits.uop.prs3_busy connect slots_11.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[2].bits.uop.prs2_busy connect slots_11.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[2].bits.uop.prs1_busy connect slots_11.io.wakeup_ports[2].bits.uop.ppred, issue_slots[11].wakeup_ports[2].bits.uop.ppred connect slots_11.io.wakeup_ports[2].bits.uop.prs3, issue_slots[11].wakeup_ports[2].bits.uop.prs3 connect slots_11.io.wakeup_ports[2].bits.uop.prs2, issue_slots[11].wakeup_ports[2].bits.uop.prs2 connect slots_11.io.wakeup_ports[2].bits.uop.prs1, issue_slots[11].wakeup_ports[2].bits.uop.prs1 connect slots_11.io.wakeup_ports[2].bits.uop.pdst, issue_slots[11].wakeup_ports[2].bits.uop.pdst connect slots_11.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[2].bits.uop.rxq_idx connect slots_11.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[11].wakeup_ports[2].bits.uop.stq_idx connect slots_11.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[2].bits.uop.ldq_idx connect slots_11.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[11].wakeup_ports[2].bits.uop.rob_idx connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_11.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[11].wakeup_ports[2].bits.uop.op2_sel connect slots_11.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[11].wakeup_ports[2].bits.uop.op1_sel connect slots_11.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[11].wakeup_ports[2].bits.uop.imm_packed connect slots_11.io.wakeup_ports[2].bits.uop.pimm, issue_slots[11].wakeup_ports[2].bits.uop.pimm connect slots_11.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[11].wakeup_ports[2].bits.uop.imm_sel connect slots_11.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[11].wakeup_ports[2].bits.uop.imm_rename connect slots_11.io.wakeup_ports[2].bits.uop.taken, issue_slots[11].wakeup_ports[2].bits.uop.taken connect slots_11.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[11].wakeup_ports[2].bits.uop.pc_lob connect slots_11.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[11].wakeup_ports[2].bits.uop.edge_inst connect slots_11.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[2].bits.uop.ftq_idx connect slots_11.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[11].wakeup_ports[2].bits.uop.is_mov connect slots_11.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[11].wakeup_ports[2].bits.uop.is_rocc connect slots_11.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_11.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[11].wakeup_ports[2].bits.uop.is_eret connect slots_11.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[11].wakeup_ports[2].bits.uop.is_amo connect slots_11.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[11].wakeup_ports[2].bits.uop.is_sfence connect slots_11.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[11].wakeup_ports[2].bits.uop.is_fencei connect slots_11.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[11].wakeup_ports[2].bits.uop.is_fence connect slots_11.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[11].wakeup_ports[2].bits.uop.is_sfb connect slots_11.io.wakeup_ports[2].bits.uop.br_type, issue_slots[11].wakeup_ports[2].bits.uop.br_type connect slots_11.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[11].wakeup_ports[2].bits.uop.br_tag connect slots_11.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[11].wakeup_ports[2].bits.uop.br_mask connect slots_11.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[2].bits.uop.dis_col_sel connect slots_11.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_11.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_11.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_11.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_11.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_11.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_11.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_11.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[11].wakeup_ports[2].bits.uop.iw_issued connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[0] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[1] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[2] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[3] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[4] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[5] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[6] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[7] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[8] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[9] connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[0] connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[1] connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[2] connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[3] connect slots_11.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[11].wakeup_ports[2].bits.uop.debug_pc connect slots_11.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[11].wakeup_ports[2].bits.uop.is_rvc connect slots_11.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[11].wakeup_ports[2].bits.uop.debug_inst connect slots_11.io.wakeup_ports[2].bits.uop.inst, issue_slots[11].wakeup_ports[2].bits.uop.inst connect slots_11.io.wakeup_ports[2].valid, issue_slots[11].wakeup_ports[2].valid connect slots_11.io.wakeup_ports[3].bits.rebusy, issue_slots[11].wakeup_ports[3].bits.rebusy connect slots_11.io.wakeup_ports[3].bits.speculative_mask, issue_slots[11].wakeup_ports[3].bits.speculative_mask connect slots_11.io.wakeup_ports[3].bits.bypassable, issue_slots[11].wakeup_ports[3].bits.bypassable connect slots_11.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[3].bits.uop.debug_tsrc connect slots_11.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[3].bits.uop.debug_fsrc connect slots_11.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_11.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[3].bits.uop.bp_debug_if connect slots_11.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_11.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_11.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_11.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[11].wakeup_ports[3].bits.uop.fp_typ connect slots_11.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[11].wakeup_ports[3].bits.uop.fp_rm connect slots_11.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[11].wakeup_ports[3].bits.uop.fp_val connect slots_11.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[11].wakeup_ports[3].bits.uop.fcn_op connect slots_11.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[3].bits.uop.fcn_dw connect slots_11.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[11].wakeup_ports[3].bits.uop.frs3_en connect slots_11.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_11.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_11.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[3].bits.uop.dst_rtype connect slots_11.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[11].wakeup_ports[3].bits.uop.lrs3 connect slots_11.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[11].wakeup_ports[3].bits.uop.lrs2 connect slots_11.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[11].wakeup_ports[3].bits.uop.lrs1 connect slots_11.io.wakeup_ports[3].bits.uop.ldst, issue_slots[11].wakeup_ports[3].bits.uop.ldst connect slots_11.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_11.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[3].bits.uop.csr_cmd connect slots_11.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[3].bits.uop.flush_on_commit connect slots_11.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[11].wakeup_ports[3].bits.uop.is_unique connect slots_11.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[11].wakeup_ports[3].bits.uop.uses_stq connect slots_11.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[3].bits.uop.uses_ldq connect slots_11.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[11].wakeup_ports[3].bits.uop.mem_signed connect slots_11.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[11].wakeup_ports[3].bits.uop.mem_size connect slots_11.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[3].bits.uop.mem_cmd connect slots_11.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[11].wakeup_ports[3].bits.uop.exc_cause connect slots_11.io.wakeup_ports[3].bits.uop.exception, issue_slots[11].wakeup_ports[3].bits.uop.exception connect slots_11.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[3].bits.uop.stale_pdst connect slots_11.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[3].bits.uop.ppred_busy connect slots_11.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[3].bits.uop.prs3_busy connect slots_11.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[3].bits.uop.prs2_busy connect slots_11.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[3].bits.uop.prs1_busy connect slots_11.io.wakeup_ports[3].bits.uop.ppred, issue_slots[11].wakeup_ports[3].bits.uop.ppred connect slots_11.io.wakeup_ports[3].bits.uop.prs3, issue_slots[11].wakeup_ports[3].bits.uop.prs3 connect slots_11.io.wakeup_ports[3].bits.uop.prs2, issue_slots[11].wakeup_ports[3].bits.uop.prs2 connect slots_11.io.wakeup_ports[3].bits.uop.prs1, issue_slots[11].wakeup_ports[3].bits.uop.prs1 connect slots_11.io.wakeup_ports[3].bits.uop.pdst, issue_slots[11].wakeup_ports[3].bits.uop.pdst connect slots_11.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[3].bits.uop.rxq_idx connect slots_11.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[11].wakeup_ports[3].bits.uop.stq_idx connect slots_11.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[3].bits.uop.ldq_idx connect slots_11.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[11].wakeup_ports[3].bits.uop.rob_idx connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_11.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[11].wakeup_ports[3].bits.uop.op2_sel connect slots_11.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[11].wakeup_ports[3].bits.uop.op1_sel connect slots_11.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[11].wakeup_ports[3].bits.uop.imm_packed connect slots_11.io.wakeup_ports[3].bits.uop.pimm, issue_slots[11].wakeup_ports[3].bits.uop.pimm connect slots_11.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[11].wakeup_ports[3].bits.uop.imm_sel connect slots_11.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[11].wakeup_ports[3].bits.uop.imm_rename connect slots_11.io.wakeup_ports[3].bits.uop.taken, issue_slots[11].wakeup_ports[3].bits.uop.taken connect slots_11.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[11].wakeup_ports[3].bits.uop.pc_lob connect slots_11.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[11].wakeup_ports[3].bits.uop.edge_inst connect slots_11.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[3].bits.uop.ftq_idx connect slots_11.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[11].wakeup_ports[3].bits.uop.is_mov connect slots_11.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[11].wakeup_ports[3].bits.uop.is_rocc connect slots_11.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_11.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[11].wakeup_ports[3].bits.uop.is_eret connect slots_11.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[11].wakeup_ports[3].bits.uop.is_amo connect slots_11.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[11].wakeup_ports[3].bits.uop.is_sfence connect slots_11.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[11].wakeup_ports[3].bits.uop.is_fencei connect slots_11.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[11].wakeup_ports[3].bits.uop.is_fence connect slots_11.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[11].wakeup_ports[3].bits.uop.is_sfb connect slots_11.io.wakeup_ports[3].bits.uop.br_type, issue_slots[11].wakeup_ports[3].bits.uop.br_type connect slots_11.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[11].wakeup_ports[3].bits.uop.br_tag connect slots_11.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[11].wakeup_ports[3].bits.uop.br_mask connect slots_11.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[3].bits.uop.dis_col_sel connect slots_11.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_11.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_11.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_11.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_11.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_11.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_11.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_11.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[11].wakeup_ports[3].bits.uop.iw_issued connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[0] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[1] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[2] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[3] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[4] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[5] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[6] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[7] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[8] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[9] connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[0] connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[1] connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[2] connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[3] connect slots_11.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[11].wakeup_ports[3].bits.uop.debug_pc connect slots_11.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[11].wakeup_ports[3].bits.uop.is_rvc connect slots_11.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[11].wakeup_ports[3].bits.uop.debug_inst connect slots_11.io.wakeup_ports[3].bits.uop.inst, issue_slots[11].wakeup_ports[3].bits.uop.inst connect slots_11.io.wakeup_ports[3].valid, issue_slots[11].wakeup_ports[3].valid connect slots_11.io.wakeup_ports[4].bits.rebusy, issue_slots[11].wakeup_ports[4].bits.rebusy connect slots_11.io.wakeup_ports[4].bits.speculative_mask, issue_slots[11].wakeup_ports[4].bits.speculative_mask connect slots_11.io.wakeup_ports[4].bits.bypassable, issue_slots[11].wakeup_ports[4].bits.bypassable connect slots_11.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[4].bits.uop.debug_tsrc connect slots_11.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[4].bits.uop.debug_fsrc connect slots_11.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_11.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[4].bits.uop.bp_debug_if connect slots_11.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_11.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_11.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_11.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[11].wakeup_ports[4].bits.uop.fp_typ connect slots_11.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[11].wakeup_ports[4].bits.uop.fp_rm connect slots_11.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[11].wakeup_ports[4].bits.uop.fp_val connect slots_11.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[11].wakeup_ports[4].bits.uop.fcn_op connect slots_11.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[4].bits.uop.fcn_dw connect slots_11.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[11].wakeup_ports[4].bits.uop.frs3_en connect slots_11.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_11.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_11.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[4].bits.uop.dst_rtype connect slots_11.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[11].wakeup_ports[4].bits.uop.lrs3 connect slots_11.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[11].wakeup_ports[4].bits.uop.lrs2 connect slots_11.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[11].wakeup_ports[4].bits.uop.lrs1 connect slots_11.io.wakeup_ports[4].bits.uop.ldst, issue_slots[11].wakeup_ports[4].bits.uop.ldst connect slots_11.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_11.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[4].bits.uop.csr_cmd connect slots_11.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[4].bits.uop.flush_on_commit connect slots_11.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[11].wakeup_ports[4].bits.uop.is_unique connect slots_11.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[11].wakeup_ports[4].bits.uop.uses_stq connect slots_11.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[4].bits.uop.uses_ldq connect slots_11.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[11].wakeup_ports[4].bits.uop.mem_signed connect slots_11.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[11].wakeup_ports[4].bits.uop.mem_size connect slots_11.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[4].bits.uop.mem_cmd connect slots_11.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[11].wakeup_ports[4].bits.uop.exc_cause connect slots_11.io.wakeup_ports[4].bits.uop.exception, issue_slots[11].wakeup_ports[4].bits.uop.exception connect slots_11.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[4].bits.uop.stale_pdst connect slots_11.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[4].bits.uop.ppred_busy connect slots_11.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[4].bits.uop.prs3_busy connect slots_11.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[4].bits.uop.prs2_busy connect slots_11.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[4].bits.uop.prs1_busy connect slots_11.io.wakeup_ports[4].bits.uop.ppred, issue_slots[11].wakeup_ports[4].bits.uop.ppred connect slots_11.io.wakeup_ports[4].bits.uop.prs3, issue_slots[11].wakeup_ports[4].bits.uop.prs3 connect slots_11.io.wakeup_ports[4].bits.uop.prs2, issue_slots[11].wakeup_ports[4].bits.uop.prs2 connect slots_11.io.wakeup_ports[4].bits.uop.prs1, issue_slots[11].wakeup_ports[4].bits.uop.prs1 connect slots_11.io.wakeup_ports[4].bits.uop.pdst, issue_slots[11].wakeup_ports[4].bits.uop.pdst connect slots_11.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[4].bits.uop.rxq_idx connect slots_11.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[11].wakeup_ports[4].bits.uop.stq_idx connect slots_11.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[4].bits.uop.ldq_idx connect slots_11.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[11].wakeup_ports[4].bits.uop.rob_idx connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_11.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[11].wakeup_ports[4].bits.uop.op2_sel connect slots_11.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[11].wakeup_ports[4].bits.uop.op1_sel connect slots_11.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[11].wakeup_ports[4].bits.uop.imm_packed connect slots_11.io.wakeup_ports[4].bits.uop.pimm, issue_slots[11].wakeup_ports[4].bits.uop.pimm connect slots_11.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[11].wakeup_ports[4].bits.uop.imm_sel connect slots_11.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[11].wakeup_ports[4].bits.uop.imm_rename connect slots_11.io.wakeup_ports[4].bits.uop.taken, issue_slots[11].wakeup_ports[4].bits.uop.taken connect slots_11.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[11].wakeup_ports[4].bits.uop.pc_lob connect slots_11.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[11].wakeup_ports[4].bits.uop.edge_inst connect slots_11.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[4].bits.uop.ftq_idx connect slots_11.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[11].wakeup_ports[4].bits.uop.is_mov connect slots_11.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[11].wakeup_ports[4].bits.uop.is_rocc connect slots_11.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_11.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[11].wakeup_ports[4].bits.uop.is_eret connect slots_11.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[11].wakeup_ports[4].bits.uop.is_amo connect slots_11.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[11].wakeup_ports[4].bits.uop.is_sfence connect slots_11.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[11].wakeup_ports[4].bits.uop.is_fencei connect slots_11.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[11].wakeup_ports[4].bits.uop.is_fence connect slots_11.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[11].wakeup_ports[4].bits.uop.is_sfb connect slots_11.io.wakeup_ports[4].bits.uop.br_type, issue_slots[11].wakeup_ports[4].bits.uop.br_type connect slots_11.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[11].wakeup_ports[4].bits.uop.br_tag connect slots_11.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[11].wakeup_ports[4].bits.uop.br_mask connect slots_11.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[4].bits.uop.dis_col_sel connect slots_11.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_11.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_11.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_11.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_11.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_11.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_11.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_11.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[11].wakeup_ports[4].bits.uop.iw_issued connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[0] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[1] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[2] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[3] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[4] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[5] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[6] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[7] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[8] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[9] connect slots_11.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[4].bits.uop.iq_type[0] connect slots_11.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[4].bits.uop.iq_type[1] connect slots_11.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[4].bits.uop.iq_type[2] connect slots_11.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[4].bits.uop.iq_type[3] connect slots_11.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[11].wakeup_ports[4].bits.uop.debug_pc connect slots_11.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[11].wakeup_ports[4].bits.uop.is_rvc connect slots_11.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[11].wakeup_ports[4].bits.uop.debug_inst connect slots_11.io.wakeup_ports[4].bits.uop.inst, issue_slots[11].wakeup_ports[4].bits.uop.inst connect slots_11.io.wakeup_ports[4].valid, issue_slots[11].wakeup_ports[4].valid connect slots_11.io.squash_grant, issue_slots[11].squash_grant connect slots_11.io.clear, issue_slots[11].clear connect slots_11.io.kill, issue_slots[11].kill connect slots_11.io.brupdate.b2.target_offset, issue_slots[11].brupdate.b2.target_offset connect slots_11.io.brupdate.b2.jalr_target, issue_slots[11].brupdate.b2.jalr_target connect slots_11.io.brupdate.b2.pc_sel, issue_slots[11].brupdate.b2.pc_sel connect slots_11.io.brupdate.b2.cfi_type, issue_slots[11].brupdate.b2.cfi_type connect slots_11.io.brupdate.b2.taken, issue_slots[11].brupdate.b2.taken connect slots_11.io.brupdate.b2.mispredict, issue_slots[11].brupdate.b2.mispredict connect slots_11.io.brupdate.b2.uop.debug_tsrc, issue_slots[11].brupdate.b2.uop.debug_tsrc connect slots_11.io.brupdate.b2.uop.debug_fsrc, issue_slots[11].brupdate.b2.uop.debug_fsrc connect slots_11.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[11].brupdate.b2.uop.bp_xcpt_if connect slots_11.io.brupdate.b2.uop.bp_debug_if, issue_slots[11].brupdate.b2.uop.bp_debug_if connect slots_11.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[11].brupdate.b2.uop.xcpt_ma_if connect slots_11.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[11].brupdate.b2.uop.xcpt_ae_if connect slots_11.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[11].brupdate.b2.uop.xcpt_pf_if connect slots_11.io.brupdate.b2.uop.fp_typ, issue_slots[11].brupdate.b2.uop.fp_typ connect slots_11.io.brupdate.b2.uop.fp_rm, issue_slots[11].brupdate.b2.uop.fp_rm connect slots_11.io.brupdate.b2.uop.fp_val, issue_slots[11].brupdate.b2.uop.fp_val connect slots_11.io.brupdate.b2.uop.fcn_op, issue_slots[11].brupdate.b2.uop.fcn_op connect slots_11.io.brupdate.b2.uop.fcn_dw, issue_slots[11].brupdate.b2.uop.fcn_dw connect slots_11.io.brupdate.b2.uop.frs3_en, issue_slots[11].brupdate.b2.uop.frs3_en connect slots_11.io.brupdate.b2.uop.lrs2_rtype, issue_slots[11].brupdate.b2.uop.lrs2_rtype connect slots_11.io.brupdate.b2.uop.lrs1_rtype, issue_slots[11].brupdate.b2.uop.lrs1_rtype connect slots_11.io.brupdate.b2.uop.dst_rtype, issue_slots[11].brupdate.b2.uop.dst_rtype connect slots_11.io.brupdate.b2.uop.lrs3, issue_slots[11].brupdate.b2.uop.lrs3 connect slots_11.io.brupdate.b2.uop.lrs2, issue_slots[11].brupdate.b2.uop.lrs2 connect slots_11.io.brupdate.b2.uop.lrs1, issue_slots[11].brupdate.b2.uop.lrs1 connect slots_11.io.brupdate.b2.uop.ldst, issue_slots[11].brupdate.b2.uop.ldst connect slots_11.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[11].brupdate.b2.uop.ldst_is_rs1 connect slots_11.io.brupdate.b2.uop.csr_cmd, issue_slots[11].brupdate.b2.uop.csr_cmd connect slots_11.io.brupdate.b2.uop.flush_on_commit, issue_slots[11].brupdate.b2.uop.flush_on_commit connect slots_11.io.brupdate.b2.uop.is_unique, issue_slots[11].brupdate.b2.uop.is_unique connect slots_11.io.brupdate.b2.uop.uses_stq, issue_slots[11].brupdate.b2.uop.uses_stq connect slots_11.io.brupdate.b2.uop.uses_ldq, issue_slots[11].brupdate.b2.uop.uses_ldq connect slots_11.io.brupdate.b2.uop.mem_signed, issue_slots[11].brupdate.b2.uop.mem_signed connect slots_11.io.brupdate.b2.uop.mem_size, issue_slots[11].brupdate.b2.uop.mem_size connect slots_11.io.brupdate.b2.uop.mem_cmd, issue_slots[11].brupdate.b2.uop.mem_cmd connect slots_11.io.brupdate.b2.uop.exc_cause, issue_slots[11].brupdate.b2.uop.exc_cause connect slots_11.io.brupdate.b2.uop.exception, issue_slots[11].brupdate.b2.uop.exception connect slots_11.io.brupdate.b2.uop.stale_pdst, issue_slots[11].brupdate.b2.uop.stale_pdst connect slots_11.io.brupdate.b2.uop.ppred_busy, issue_slots[11].brupdate.b2.uop.ppred_busy connect slots_11.io.brupdate.b2.uop.prs3_busy, issue_slots[11].brupdate.b2.uop.prs3_busy connect slots_11.io.brupdate.b2.uop.prs2_busy, issue_slots[11].brupdate.b2.uop.prs2_busy connect slots_11.io.brupdate.b2.uop.prs1_busy, issue_slots[11].brupdate.b2.uop.prs1_busy connect slots_11.io.brupdate.b2.uop.ppred, issue_slots[11].brupdate.b2.uop.ppred connect slots_11.io.brupdate.b2.uop.prs3, issue_slots[11].brupdate.b2.uop.prs3 connect slots_11.io.brupdate.b2.uop.prs2, issue_slots[11].brupdate.b2.uop.prs2 connect slots_11.io.brupdate.b2.uop.prs1, issue_slots[11].brupdate.b2.uop.prs1 connect slots_11.io.brupdate.b2.uop.pdst, issue_slots[11].brupdate.b2.uop.pdst connect slots_11.io.brupdate.b2.uop.rxq_idx, issue_slots[11].brupdate.b2.uop.rxq_idx connect slots_11.io.brupdate.b2.uop.stq_idx, issue_slots[11].brupdate.b2.uop.stq_idx connect slots_11.io.brupdate.b2.uop.ldq_idx, issue_slots[11].brupdate.b2.uop.ldq_idx connect slots_11.io.brupdate.b2.uop.rob_idx, issue_slots[11].brupdate.b2.uop.rob_idx connect slots_11.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[11].brupdate.b2.uop.fp_ctrl.vec connect slots_11.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[11].brupdate.b2.uop.fp_ctrl.wflags connect slots_11.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[11].brupdate.b2.uop.fp_ctrl.sqrt connect slots_11.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[11].brupdate.b2.uop.fp_ctrl.div connect slots_11.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[11].brupdate.b2.uop.fp_ctrl.fma connect slots_11.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[11].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_11.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[11].brupdate.b2.uop.fp_ctrl.toint connect slots_11.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[11].brupdate.b2.uop.fp_ctrl.fromint connect slots_11.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_11.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_11.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[11].brupdate.b2.uop.fp_ctrl.swap23 connect slots_11.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[11].brupdate.b2.uop.fp_ctrl.swap12 connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren3 connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren2 connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren1 connect slots_11.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[11].brupdate.b2.uop.fp_ctrl.wen connect slots_11.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[11].brupdate.b2.uop.fp_ctrl.ldst connect slots_11.io.brupdate.b2.uop.op2_sel, issue_slots[11].brupdate.b2.uop.op2_sel connect slots_11.io.brupdate.b2.uop.op1_sel, issue_slots[11].brupdate.b2.uop.op1_sel connect slots_11.io.brupdate.b2.uop.imm_packed, issue_slots[11].brupdate.b2.uop.imm_packed connect slots_11.io.brupdate.b2.uop.pimm, issue_slots[11].brupdate.b2.uop.pimm connect slots_11.io.brupdate.b2.uop.imm_sel, issue_slots[11].brupdate.b2.uop.imm_sel connect slots_11.io.brupdate.b2.uop.imm_rename, issue_slots[11].brupdate.b2.uop.imm_rename connect slots_11.io.brupdate.b2.uop.taken, issue_slots[11].brupdate.b2.uop.taken connect slots_11.io.brupdate.b2.uop.pc_lob, issue_slots[11].brupdate.b2.uop.pc_lob connect slots_11.io.brupdate.b2.uop.edge_inst, issue_slots[11].brupdate.b2.uop.edge_inst connect slots_11.io.brupdate.b2.uop.ftq_idx, issue_slots[11].brupdate.b2.uop.ftq_idx connect slots_11.io.brupdate.b2.uop.is_mov, issue_slots[11].brupdate.b2.uop.is_mov connect slots_11.io.brupdate.b2.uop.is_rocc, issue_slots[11].brupdate.b2.uop.is_rocc connect slots_11.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[11].brupdate.b2.uop.is_sys_pc2epc connect slots_11.io.brupdate.b2.uop.is_eret, issue_slots[11].brupdate.b2.uop.is_eret connect slots_11.io.brupdate.b2.uop.is_amo, issue_slots[11].brupdate.b2.uop.is_amo connect slots_11.io.brupdate.b2.uop.is_sfence, issue_slots[11].brupdate.b2.uop.is_sfence connect slots_11.io.brupdate.b2.uop.is_fencei, issue_slots[11].brupdate.b2.uop.is_fencei connect slots_11.io.brupdate.b2.uop.is_fence, issue_slots[11].brupdate.b2.uop.is_fence connect slots_11.io.brupdate.b2.uop.is_sfb, issue_slots[11].brupdate.b2.uop.is_sfb connect slots_11.io.brupdate.b2.uop.br_type, issue_slots[11].brupdate.b2.uop.br_type connect slots_11.io.brupdate.b2.uop.br_tag, issue_slots[11].brupdate.b2.uop.br_tag connect slots_11.io.brupdate.b2.uop.br_mask, issue_slots[11].brupdate.b2.uop.br_mask connect slots_11.io.brupdate.b2.uop.dis_col_sel, issue_slots[11].brupdate.b2.uop.dis_col_sel connect slots_11.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p3_bypass_hint connect slots_11.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p2_bypass_hint connect slots_11.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p1_bypass_hint connect slots_11.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[11].brupdate.b2.uop.iw_p2_speculative_child connect slots_11.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[11].brupdate.b2.uop.iw_p1_speculative_child connect slots_11.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[11].brupdate.b2.uop.iw_issued_partial_dgen connect slots_11.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[11].brupdate.b2.uop.iw_issued_partial_agen connect slots_11.io.brupdate.b2.uop.iw_issued, issue_slots[11].brupdate.b2.uop.iw_issued connect slots_11.io.brupdate.b2.uop.fu_code[0], issue_slots[11].brupdate.b2.uop.fu_code[0] connect slots_11.io.brupdate.b2.uop.fu_code[1], issue_slots[11].brupdate.b2.uop.fu_code[1] connect slots_11.io.brupdate.b2.uop.fu_code[2], issue_slots[11].brupdate.b2.uop.fu_code[2] connect slots_11.io.brupdate.b2.uop.fu_code[3], issue_slots[11].brupdate.b2.uop.fu_code[3] connect slots_11.io.brupdate.b2.uop.fu_code[4], issue_slots[11].brupdate.b2.uop.fu_code[4] connect slots_11.io.brupdate.b2.uop.fu_code[5], issue_slots[11].brupdate.b2.uop.fu_code[5] connect slots_11.io.brupdate.b2.uop.fu_code[6], issue_slots[11].brupdate.b2.uop.fu_code[6] connect slots_11.io.brupdate.b2.uop.fu_code[7], issue_slots[11].brupdate.b2.uop.fu_code[7] connect slots_11.io.brupdate.b2.uop.fu_code[8], issue_slots[11].brupdate.b2.uop.fu_code[8] connect slots_11.io.brupdate.b2.uop.fu_code[9], issue_slots[11].brupdate.b2.uop.fu_code[9] connect slots_11.io.brupdate.b2.uop.iq_type[0], issue_slots[11].brupdate.b2.uop.iq_type[0] connect slots_11.io.brupdate.b2.uop.iq_type[1], issue_slots[11].brupdate.b2.uop.iq_type[1] connect slots_11.io.brupdate.b2.uop.iq_type[2], issue_slots[11].brupdate.b2.uop.iq_type[2] connect slots_11.io.brupdate.b2.uop.iq_type[3], issue_slots[11].brupdate.b2.uop.iq_type[3] connect slots_11.io.brupdate.b2.uop.debug_pc, issue_slots[11].brupdate.b2.uop.debug_pc connect slots_11.io.brupdate.b2.uop.is_rvc, issue_slots[11].brupdate.b2.uop.is_rvc connect slots_11.io.brupdate.b2.uop.debug_inst, issue_slots[11].brupdate.b2.uop.debug_inst connect slots_11.io.brupdate.b2.uop.inst, issue_slots[11].brupdate.b2.uop.inst connect slots_11.io.brupdate.b1.mispredict_mask, issue_slots[11].brupdate.b1.mispredict_mask connect slots_11.io.brupdate.b1.resolve_mask, issue_slots[11].brupdate.b1.resolve_mask connect issue_slots[11].out_uop.debug_tsrc, slots_11.io.out_uop.debug_tsrc connect issue_slots[11].out_uop.debug_fsrc, slots_11.io.out_uop.debug_fsrc connect issue_slots[11].out_uop.bp_xcpt_if, slots_11.io.out_uop.bp_xcpt_if connect issue_slots[11].out_uop.bp_debug_if, slots_11.io.out_uop.bp_debug_if connect issue_slots[11].out_uop.xcpt_ma_if, slots_11.io.out_uop.xcpt_ma_if connect issue_slots[11].out_uop.xcpt_ae_if, slots_11.io.out_uop.xcpt_ae_if connect issue_slots[11].out_uop.xcpt_pf_if, slots_11.io.out_uop.xcpt_pf_if connect issue_slots[11].out_uop.fp_typ, slots_11.io.out_uop.fp_typ connect issue_slots[11].out_uop.fp_rm, slots_11.io.out_uop.fp_rm connect issue_slots[11].out_uop.fp_val, slots_11.io.out_uop.fp_val connect issue_slots[11].out_uop.fcn_op, slots_11.io.out_uop.fcn_op connect issue_slots[11].out_uop.fcn_dw, slots_11.io.out_uop.fcn_dw connect issue_slots[11].out_uop.frs3_en, slots_11.io.out_uop.frs3_en connect issue_slots[11].out_uop.lrs2_rtype, slots_11.io.out_uop.lrs2_rtype connect issue_slots[11].out_uop.lrs1_rtype, slots_11.io.out_uop.lrs1_rtype connect issue_slots[11].out_uop.dst_rtype, slots_11.io.out_uop.dst_rtype connect issue_slots[11].out_uop.lrs3, slots_11.io.out_uop.lrs3 connect issue_slots[11].out_uop.lrs2, slots_11.io.out_uop.lrs2 connect issue_slots[11].out_uop.lrs1, slots_11.io.out_uop.lrs1 connect issue_slots[11].out_uop.ldst, slots_11.io.out_uop.ldst connect issue_slots[11].out_uop.ldst_is_rs1, slots_11.io.out_uop.ldst_is_rs1 connect issue_slots[11].out_uop.csr_cmd, slots_11.io.out_uop.csr_cmd connect issue_slots[11].out_uop.flush_on_commit, slots_11.io.out_uop.flush_on_commit connect issue_slots[11].out_uop.is_unique, slots_11.io.out_uop.is_unique connect issue_slots[11].out_uop.uses_stq, slots_11.io.out_uop.uses_stq connect issue_slots[11].out_uop.uses_ldq, slots_11.io.out_uop.uses_ldq connect issue_slots[11].out_uop.mem_signed, slots_11.io.out_uop.mem_signed connect issue_slots[11].out_uop.mem_size, slots_11.io.out_uop.mem_size connect issue_slots[11].out_uop.mem_cmd, slots_11.io.out_uop.mem_cmd connect issue_slots[11].out_uop.exc_cause, slots_11.io.out_uop.exc_cause connect issue_slots[11].out_uop.exception, slots_11.io.out_uop.exception connect issue_slots[11].out_uop.stale_pdst, slots_11.io.out_uop.stale_pdst connect issue_slots[11].out_uop.ppred_busy, slots_11.io.out_uop.ppred_busy connect issue_slots[11].out_uop.prs3_busy, slots_11.io.out_uop.prs3_busy connect issue_slots[11].out_uop.prs2_busy, slots_11.io.out_uop.prs2_busy connect issue_slots[11].out_uop.prs1_busy, slots_11.io.out_uop.prs1_busy connect issue_slots[11].out_uop.ppred, slots_11.io.out_uop.ppred connect issue_slots[11].out_uop.prs3, slots_11.io.out_uop.prs3 connect issue_slots[11].out_uop.prs2, slots_11.io.out_uop.prs2 connect issue_slots[11].out_uop.prs1, slots_11.io.out_uop.prs1 connect issue_slots[11].out_uop.pdst, slots_11.io.out_uop.pdst connect issue_slots[11].out_uop.rxq_idx, slots_11.io.out_uop.rxq_idx connect issue_slots[11].out_uop.stq_idx, slots_11.io.out_uop.stq_idx connect issue_slots[11].out_uop.ldq_idx, slots_11.io.out_uop.ldq_idx connect issue_slots[11].out_uop.rob_idx, slots_11.io.out_uop.rob_idx connect issue_slots[11].out_uop.fp_ctrl.vec, slots_11.io.out_uop.fp_ctrl.vec connect issue_slots[11].out_uop.fp_ctrl.wflags, slots_11.io.out_uop.fp_ctrl.wflags connect issue_slots[11].out_uop.fp_ctrl.sqrt, slots_11.io.out_uop.fp_ctrl.sqrt connect issue_slots[11].out_uop.fp_ctrl.div, slots_11.io.out_uop.fp_ctrl.div connect issue_slots[11].out_uop.fp_ctrl.fma, slots_11.io.out_uop.fp_ctrl.fma connect issue_slots[11].out_uop.fp_ctrl.fastpipe, slots_11.io.out_uop.fp_ctrl.fastpipe connect issue_slots[11].out_uop.fp_ctrl.toint, slots_11.io.out_uop.fp_ctrl.toint connect issue_slots[11].out_uop.fp_ctrl.fromint, slots_11.io.out_uop.fp_ctrl.fromint connect issue_slots[11].out_uop.fp_ctrl.typeTagOut, slots_11.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[11].out_uop.fp_ctrl.typeTagIn, slots_11.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[11].out_uop.fp_ctrl.swap23, slots_11.io.out_uop.fp_ctrl.swap23 connect issue_slots[11].out_uop.fp_ctrl.swap12, slots_11.io.out_uop.fp_ctrl.swap12 connect issue_slots[11].out_uop.fp_ctrl.ren3, slots_11.io.out_uop.fp_ctrl.ren3 connect issue_slots[11].out_uop.fp_ctrl.ren2, slots_11.io.out_uop.fp_ctrl.ren2 connect issue_slots[11].out_uop.fp_ctrl.ren1, slots_11.io.out_uop.fp_ctrl.ren1 connect issue_slots[11].out_uop.fp_ctrl.wen, slots_11.io.out_uop.fp_ctrl.wen connect issue_slots[11].out_uop.fp_ctrl.ldst, slots_11.io.out_uop.fp_ctrl.ldst connect issue_slots[11].out_uop.op2_sel, slots_11.io.out_uop.op2_sel connect issue_slots[11].out_uop.op1_sel, slots_11.io.out_uop.op1_sel connect issue_slots[11].out_uop.imm_packed, slots_11.io.out_uop.imm_packed connect issue_slots[11].out_uop.pimm, slots_11.io.out_uop.pimm connect issue_slots[11].out_uop.imm_sel, slots_11.io.out_uop.imm_sel connect issue_slots[11].out_uop.imm_rename, slots_11.io.out_uop.imm_rename connect issue_slots[11].out_uop.taken, slots_11.io.out_uop.taken connect issue_slots[11].out_uop.pc_lob, slots_11.io.out_uop.pc_lob connect issue_slots[11].out_uop.edge_inst, slots_11.io.out_uop.edge_inst connect issue_slots[11].out_uop.ftq_idx, slots_11.io.out_uop.ftq_idx connect issue_slots[11].out_uop.is_mov, slots_11.io.out_uop.is_mov connect issue_slots[11].out_uop.is_rocc, slots_11.io.out_uop.is_rocc connect issue_slots[11].out_uop.is_sys_pc2epc, slots_11.io.out_uop.is_sys_pc2epc connect issue_slots[11].out_uop.is_eret, slots_11.io.out_uop.is_eret connect issue_slots[11].out_uop.is_amo, slots_11.io.out_uop.is_amo connect issue_slots[11].out_uop.is_sfence, slots_11.io.out_uop.is_sfence connect issue_slots[11].out_uop.is_fencei, slots_11.io.out_uop.is_fencei connect issue_slots[11].out_uop.is_fence, slots_11.io.out_uop.is_fence connect issue_slots[11].out_uop.is_sfb, slots_11.io.out_uop.is_sfb connect issue_slots[11].out_uop.br_type, slots_11.io.out_uop.br_type connect issue_slots[11].out_uop.br_tag, slots_11.io.out_uop.br_tag connect issue_slots[11].out_uop.br_mask, slots_11.io.out_uop.br_mask connect issue_slots[11].out_uop.dis_col_sel, slots_11.io.out_uop.dis_col_sel connect issue_slots[11].out_uop.iw_p3_bypass_hint, slots_11.io.out_uop.iw_p3_bypass_hint connect issue_slots[11].out_uop.iw_p2_bypass_hint, slots_11.io.out_uop.iw_p2_bypass_hint connect issue_slots[11].out_uop.iw_p1_bypass_hint, slots_11.io.out_uop.iw_p1_bypass_hint connect issue_slots[11].out_uop.iw_p2_speculative_child, slots_11.io.out_uop.iw_p2_speculative_child connect issue_slots[11].out_uop.iw_p1_speculative_child, slots_11.io.out_uop.iw_p1_speculative_child connect issue_slots[11].out_uop.iw_issued_partial_dgen, slots_11.io.out_uop.iw_issued_partial_dgen connect issue_slots[11].out_uop.iw_issued_partial_agen, slots_11.io.out_uop.iw_issued_partial_agen connect issue_slots[11].out_uop.iw_issued, slots_11.io.out_uop.iw_issued connect issue_slots[11].out_uop.fu_code[0], slots_11.io.out_uop.fu_code[0] connect issue_slots[11].out_uop.fu_code[1], slots_11.io.out_uop.fu_code[1] connect issue_slots[11].out_uop.fu_code[2], slots_11.io.out_uop.fu_code[2] connect issue_slots[11].out_uop.fu_code[3], slots_11.io.out_uop.fu_code[3] connect issue_slots[11].out_uop.fu_code[4], slots_11.io.out_uop.fu_code[4] connect issue_slots[11].out_uop.fu_code[5], slots_11.io.out_uop.fu_code[5] connect issue_slots[11].out_uop.fu_code[6], slots_11.io.out_uop.fu_code[6] connect issue_slots[11].out_uop.fu_code[7], slots_11.io.out_uop.fu_code[7] connect issue_slots[11].out_uop.fu_code[8], slots_11.io.out_uop.fu_code[8] connect issue_slots[11].out_uop.fu_code[9], slots_11.io.out_uop.fu_code[9] connect issue_slots[11].out_uop.iq_type[0], slots_11.io.out_uop.iq_type[0] connect issue_slots[11].out_uop.iq_type[1], slots_11.io.out_uop.iq_type[1] connect issue_slots[11].out_uop.iq_type[2], slots_11.io.out_uop.iq_type[2] connect issue_slots[11].out_uop.iq_type[3], slots_11.io.out_uop.iq_type[3] connect issue_slots[11].out_uop.debug_pc, slots_11.io.out_uop.debug_pc connect issue_slots[11].out_uop.is_rvc, slots_11.io.out_uop.is_rvc connect issue_slots[11].out_uop.debug_inst, slots_11.io.out_uop.debug_inst connect issue_slots[11].out_uop.inst, slots_11.io.out_uop.inst connect slots_11.io.in_uop.bits.debug_tsrc, issue_slots[11].in_uop.bits.debug_tsrc connect slots_11.io.in_uop.bits.debug_fsrc, issue_slots[11].in_uop.bits.debug_fsrc connect slots_11.io.in_uop.bits.bp_xcpt_if, issue_slots[11].in_uop.bits.bp_xcpt_if connect slots_11.io.in_uop.bits.bp_debug_if, issue_slots[11].in_uop.bits.bp_debug_if connect slots_11.io.in_uop.bits.xcpt_ma_if, issue_slots[11].in_uop.bits.xcpt_ma_if connect slots_11.io.in_uop.bits.xcpt_ae_if, issue_slots[11].in_uop.bits.xcpt_ae_if connect slots_11.io.in_uop.bits.xcpt_pf_if, issue_slots[11].in_uop.bits.xcpt_pf_if connect slots_11.io.in_uop.bits.fp_typ, issue_slots[11].in_uop.bits.fp_typ connect slots_11.io.in_uop.bits.fp_rm, issue_slots[11].in_uop.bits.fp_rm connect slots_11.io.in_uop.bits.fp_val, issue_slots[11].in_uop.bits.fp_val connect slots_11.io.in_uop.bits.fcn_op, issue_slots[11].in_uop.bits.fcn_op connect slots_11.io.in_uop.bits.fcn_dw, issue_slots[11].in_uop.bits.fcn_dw connect slots_11.io.in_uop.bits.frs3_en, issue_slots[11].in_uop.bits.frs3_en connect slots_11.io.in_uop.bits.lrs2_rtype, issue_slots[11].in_uop.bits.lrs2_rtype connect slots_11.io.in_uop.bits.lrs1_rtype, issue_slots[11].in_uop.bits.lrs1_rtype connect slots_11.io.in_uop.bits.dst_rtype, issue_slots[11].in_uop.bits.dst_rtype connect slots_11.io.in_uop.bits.lrs3, issue_slots[11].in_uop.bits.lrs3 connect slots_11.io.in_uop.bits.lrs2, issue_slots[11].in_uop.bits.lrs2 connect slots_11.io.in_uop.bits.lrs1, issue_slots[11].in_uop.bits.lrs1 connect slots_11.io.in_uop.bits.ldst, issue_slots[11].in_uop.bits.ldst connect slots_11.io.in_uop.bits.ldst_is_rs1, issue_slots[11].in_uop.bits.ldst_is_rs1 connect slots_11.io.in_uop.bits.csr_cmd, issue_slots[11].in_uop.bits.csr_cmd connect slots_11.io.in_uop.bits.flush_on_commit, issue_slots[11].in_uop.bits.flush_on_commit connect slots_11.io.in_uop.bits.is_unique, issue_slots[11].in_uop.bits.is_unique connect slots_11.io.in_uop.bits.uses_stq, issue_slots[11].in_uop.bits.uses_stq connect slots_11.io.in_uop.bits.uses_ldq, issue_slots[11].in_uop.bits.uses_ldq connect slots_11.io.in_uop.bits.mem_signed, issue_slots[11].in_uop.bits.mem_signed connect slots_11.io.in_uop.bits.mem_size, issue_slots[11].in_uop.bits.mem_size connect slots_11.io.in_uop.bits.mem_cmd, issue_slots[11].in_uop.bits.mem_cmd connect slots_11.io.in_uop.bits.exc_cause, issue_slots[11].in_uop.bits.exc_cause connect slots_11.io.in_uop.bits.exception, issue_slots[11].in_uop.bits.exception connect slots_11.io.in_uop.bits.stale_pdst, issue_slots[11].in_uop.bits.stale_pdst connect slots_11.io.in_uop.bits.ppred_busy, issue_slots[11].in_uop.bits.ppred_busy connect slots_11.io.in_uop.bits.prs3_busy, issue_slots[11].in_uop.bits.prs3_busy connect slots_11.io.in_uop.bits.prs2_busy, issue_slots[11].in_uop.bits.prs2_busy connect slots_11.io.in_uop.bits.prs1_busy, issue_slots[11].in_uop.bits.prs1_busy connect slots_11.io.in_uop.bits.ppred, issue_slots[11].in_uop.bits.ppred connect slots_11.io.in_uop.bits.prs3, issue_slots[11].in_uop.bits.prs3 connect slots_11.io.in_uop.bits.prs2, issue_slots[11].in_uop.bits.prs2 connect slots_11.io.in_uop.bits.prs1, issue_slots[11].in_uop.bits.prs1 connect slots_11.io.in_uop.bits.pdst, issue_slots[11].in_uop.bits.pdst connect slots_11.io.in_uop.bits.rxq_idx, issue_slots[11].in_uop.bits.rxq_idx connect slots_11.io.in_uop.bits.stq_idx, issue_slots[11].in_uop.bits.stq_idx connect slots_11.io.in_uop.bits.ldq_idx, issue_slots[11].in_uop.bits.ldq_idx connect slots_11.io.in_uop.bits.rob_idx, issue_slots[11].in_uop.bits.rob_idx connect slots_11.io.in_uop.bits.fp_ctrl.vec, issue_slots[11].in_uop.bits.fp_ctrl.vec connect slots_11.io.in_uop.bits.fp_ctrl.wflags, issue_slots[11].in_uop.bits.fp_ctrl.wflags connect slots_11.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[11].in_uop.bits.fp_ctrl.sqrt connect slots_11.io.in_uop.bits.fp_ctrl.div, issue_slots[11].in_uop.bits.fp_ctrl.div connect slots_11.io.in_uop.bits.fp_ctrl.fma, issue_slots[11].in_uop.bits.fp_ctrl.fma connect slots_11.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].in_uop.bits.fp_ctrl.fastpipe connect slots_11.io.in_uop.bits.fp_ctrl.toint, issue_slots[11].in_uop.bits.fp_ctrl.toint connect slots_11.io.in_uop.bits.fp_ctrl.fromint, issue_slots[11].in_uop.bits.fp_ctrl.fromint connect slots_11.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut connect slots_11.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn connect slots_11.io.in_uop.bits.fp_ctrl.swap23, issue_slots[11].in_uop.bits.fp_ctrl.swap23 connect slots_11.io.in_uop.bits.fp_ctrl.swap12, issue_slots[11].in_uop.bits.fp_ctrl.swap12 connect slots_11.io.in_uop.bits.fp_ctrl.ren3, issue_slots[11].in_uop.bits.fp_ctrl.ren3 connect slots_11.io.in_uop.bits.fp_ctrl.ren2, issue_slots[11].in_uop.bits.fp_ctrl.ren2 connect slots_11.io.in_uop.bits.fp_ctrl.ren1, issue_slots[11].in_uop.bits.fp_ctrl.ren1 connect slots_11.io.in_uop.bits.fp_ctrl.wen, issue_slots[11].in_uop.bits.fp_ctrl.wen connect slots_11.io.in_uop.bits.fp_ctrl.ldst, issue_slots[11].in_uop.bits.fp_ctrl.ldst connect slots_11.io.in_uop.bits.op2_sel, issue_slots[11].in_uop.bits.op2_sel connect slots_11.io.in_uop.bits.op1_sel, issue_slots[11].in_uop.bits.op1_sel connect slots_11.io.in_uop.bits.imm_packed, issue_slots[11].in_uop.bits.imm_packed connect slots_11.io.in_uop.bits.pimm, issue_slots[11].in_uop.bits.pimm connect slots_11.io.in_uop.bits.imm_sel, issue_slots[11].in_uop.bits.imm_sel connect slots_11.io.in_uop.bits.imm_rename, issue_slots[11].in_uop.bits.imm_rename connect slots_11.io.in_uop.bits.taken, issue_slots[11].in_uop.bits.taken connect slots_11.io.in_uop.bits.pc_lob, issue_slots[11].in_uop.bits.pc_lob connect slots_11.io.in_uop.bits.edge_inst, issue_slots[11].in_uop.bits.edge_inst connect slots_11.io.in_uop.bits.ftq_idx, issue_slots[11].in_uop.bits.ftq_idx connect slots_11.io.in_uop.bits.is_mov, issue_slots[11].in_uop.bits.is_mov connect slots_11.io.in_uop.bits.is_rocc, issue_slots[11].in_uop.bits.is_rocc connect slots_11.io.in_uop.bits.is_sys_pc2epc, issue_slots[11].in_uop.bits.is_sys_pc2epc connect slots_11.io.in_uop.bits.is_eret, issue_slots[11].in_uop.bits.is_eret connect slots_11.io.in_uop.bits.is_amo, issue_slots[11].in_uop.bits.is_amo connect slots_11.io.in_uop.bits.is_sfence, issue_slots[11].in_uop.bits.is_sfence connect slots_11.io.in_uop.bits.is_fencei, issue_slots[11].in_uop.bits.is_fencei connect slots_11.io.in_uop.bits.is_fence, issue_slots[11].in_uop.bits.is_fence connect slots_11.io.in_uop.bits.is_sfb, issue_slots[11].in_uop.bits.is_sfb connect slots_11.io.in_uop.bits.br_type, issue_slots[11].in_uop.bits.br_type connect slots_11.io.in_uop.bits.br_tag, issue_slots[11].in_uop.bits.br_tag connect slots_11.io.in_uop.bits.br_mask, issue_slots[11].in_uop.bits.br_mask connect slots_11.io.in_uop.bits.dis_col_sel, issue_slots[11].in_uop.bits.dis_col_sel connect slots_11.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[11].in_uop.bits.iw_p3_bypass_hint connect slots_11.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[11].in_uop.bits.iw_p2_bypass_hint connect slots_11.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[11].in_uop.bits.iw_p1_bypass_hint connect slots_11.io.in_uop.bits.iw_p2_speculative_child, issue_slots[11].in_uop.bits.iw_p2_speculative_child connect slots_11.io.in_uop.bits.iw_p1_speculative_child, issue_slots[11].in_uop.bits.iw_p1_speculative_child connect slots_11.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[11].in_uop.bits.iw_issued_partial_dgen connect slots_11.io.in_uop.bits.iw_issued_partial_agen, issue_slots[11].in_uop.bits.iw_issued_partial_agen connect slots_11.io.in_uop.bits.iw_issued, issue_slots[11].in_uop.bits.iw_issued connect slots_11.io.in_uop.bits.fu_code[0], issue_slots[11].in_uop.bits.fu_code[0] connect slots_11.io.in_uop.bits.fu_code[1], issue_slots[11].in_uop.bits.fu_code[1] connect slots_11.io.in_uop.bits.fu_code[2], issue_slots[11].in_uop.bits.fu_code[2] connect slots_11.io.in_uop.bits.fu_code[3], issue_slots[11].in_uop.bits.fu_code[3] connect slots_11.io.in_uop.bits.fu_code[4], issue_slots[11].in_uop.bits.fu_code[4] connect slots_11.io.in_uop.bits.fu_code[5], issue_slots[11].in_uop.bits.fu_code[5] connect slots_11.io.in_uop.bits.fu_code[6], issue_slots[11].in_uop.bits.fu_code[6] connect slots_11.io.in_uop.bits.fu_code[7], issue_slots[11].in_uop.bits.fu_code[7] connect slots_11.io.in_uop.bits.fu_code[8], issue_slots[11].in_uop.bits.fu_code[8] connect slots_11.io.in_uop.bits.fu_code[9], issue_slots[11].in_uop.bits.fu_code[9] connect slots_11.io.in_uop.bits.iq_type[0], issue_slots[11].in_uop.bits.iq_type[0] connect slots_11.io.in_uop.bits.iq_type[1], issue_slots[11].in_uop.bits.iq_type[1] connect slots_11.io.in_uop.bits.iq_type[2], issue_slots[11].in_uop.bits.iq_type[2] connect slots_11.io.in_uop.bits.iq_type[3], issue_slots[11].in_uop.bits.iq_type[3] connect slots_11.io.in_uop.bits.debug_pc, issue_slots[11].in_uop.bits.debug_pc connect slots_11.io.in_uop.bits.is_rvc, issue_slots[11].in_uop.bits.is_rvc connect slots_11.io.in_uop.bits.debug_inst, issue_slots[11].in_uop.bits.debug_inst connect slots_11.io.in_uop.bits.inst, issue_slots[11].in_uop.bits.inst connect slots_11.io.in_uop.valid, issue_slots[11].in_uop.valid connect issue_slots[11].iss_uop.debug_tsrc, slots_11.io.iss_uop.debug_tsrc connect issue_slots[11].iss_uop.debug_fsrc, slots_11.io.iss_uop.debug_fsrc connect issue_slots[11].iss_uop.bp_xcpt_if, slots_11.io.iss_uop.bp_xcpt_if connect issue_slots[11].iss_uop.bp_debug_if, slots_11.io.iss_uop.bp_debug_if connect issue_slots[11].iss_uop.xcpt_ma_if, slots_11.io.iss_uop.xcpt_ma_if connect issue_slots[11].iss_uop.xcpt_ae_if, slots_11.io.iss_uop.xcpt_ae_if connect issue_slots[11].iss_uop.xcpt_pf_if, slots_11.io.iss_uop.xcpt_pf_if connect issue_slots[11].iss_uop.fp_typ, slots_11.io.iss_uop.fp_typ connect issue_slots[11].iss_uop.fp_rm, slots_11.io.iss_uop.fp_rm connect issue_slots[11].iss_uop.fp_val, slots_11.io.iss_uop.fp_val connect issue_slots[11].iss_uop.fcn_op, slots_11.io.iss_uop.fcn_op connect issue_slots[11].iss_uop.fcn_dw, slots_11.io.iss_uop.fcn_dw connect issue_slots[11].iss_uop.frs3_en, slots_11.io.iss_uop.frs3_en connect issue_slots[11].iss_uop.lrs2_rtype, slots_11.io.iss_uop.lrs2_rtype connect issue_slots[11].iss_uop.lrs1_rtype, slots_11.io.iss_uop.lrs1_rtype connect issue_slots[11].iss_uop.dst_rtype, slots_11.io.iss_uop.dst_rtype connect issue_slots[11].iss_uop.lrs3, slots_11.io.iss_uop.lrs3 connect issue_slots[11].iss_uop.lrs2, slots_11.io.iss_uop.lrs2 connect issue_slots[11].iss_uop.lrs1, slots_11.io.iss_uop.lrs1 connect issue_slots[11].iss_uop.ldst, slots_11.io.iss_uop.ldst connect issue_slots[11].iss_uop.ldst_is_rs1, slots_11.io.iss_uop.ldst_is_rs1 connect issue_slots[11].iss_uop.csr_cmd, slots_11.io.iss_uop.csr_cmd connect issue_slots[11].iss_uop.flush_on_commit, slots_11.io.iss_uop.flush_on_commit connect issue_slots[11].iss_uop.is_unique, slots_11.io.iss_uop.is_unique connect issue_slots[11].iss_uop.uses_stq, slots_11.io.iss_uop.uses_stq connect issue_slots[11].iss_uop.uses_ldq, slots_11.io.iss_uop.uses_ldq connect issue_slots[11].iss_uop.mem_signed, slots_11.io.iss_uop.mem_signed connect issue_slots[11].iss_uop.mem_size, slots_11.io.iss_uop.mem_size connect issue_slots[11].iss_uop.mem_cmd, slots_11.io.iss_uop.mem_cmd connect issue_slots[11].iss_uop.exc_cause, slots_11.io.iss_uop.exc_cause connect issue_slots[11].iss_uop.exception, slots_11.io.iss_uop.exception connect issue_slots[11].iss_uop.stale_pdst, slots_11.io.iss_uop.stale_pdst connect issue_slots[11].iss_uop.ppred_busy, slots_11.io.iss_uop.ppred_busy connect issue_slots[11].iss_uop.prs3_busy, slots_11.io.iss_uop.prs3_busy connect issue_slots[11].iss_uop.prs2_busy, slots_11.io.iss_uop.prs2_busy connect issue_slots[11].iss_uop.prs1_busy, slots_11.io.iss_uop.prs1_busy connect issue_slots[11].iss_uop.ppred, slots_11.io.iss_uop.ppred connect issue_slots[11].iss_uop.prs3, slots_11.io.iss_uop.prs3 connect issue_slots[11].iss_uop.prs2, slots_11.io.iss_uop.prs2 connect issue_slots[11].iss_uop.prs1, slots_11.io.iss_uop.prs1 connect issue_slots[11].iss_uop.pdst, slots_11.io.iss_uop.pdst connect issue_slots[11].iss_uop.rxq_idx, slots_11.io.iss_uop.rxq_idx connect issue_slots[11].iss_uop.stq_idx, slots_11.io.iss_uop.stq_idx connect issue_slots[11].iss_uop.ldq_idx, slots_11.io.iss_uop.ldq_idx connect issue_slots[11].iss_uop.rob_idx, slots_11.io.iss_uop.rob_idx connect issue_slots[11].iss_uop.fp_ctrl.vec, slots_11.io.iss_uop.fp_ctrl.vec connect issue_slots[11].iss_uop.fp_ctrl.wflags, slots_11.io.iss_uop.fp_ctrl.wflags connect issue_slots[11].iss_uop.fp_ctrl.sqrt, slots_11.io.iss_uop.fp_ctrl.sqrt connect issue_slots[11].iss_uop.fp_ctrl.div, slots_11.io.iss_uop.fp_ctrl.div connect issue_slots[11].iss_uop.fp_ctrl.fma, slots_11.io.iss_uop.fp_ctrl.fma connect issue_slots[11].iss_uop.fp_ctrl.fastpipe, slots_11.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[11].iss_uop.fp_ctrl.toint, slots_11.io.iss_uop.fp_ctrl.toint connect issue_slots[11].iss_uop.fp_ctrl.fromint, slots_11.io.iss_uop.fp_ctrl.fromint connect issue_slots[11].iss_uop.fp_ctrl.typeTagOut, slots_11.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[11].iss_uop.fp_ctrl.typeTagIn, slots_11.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[11].iss_uop.fp_ctrl.swap23, slots_11.io.iss_uop.fp_ctrl.swap23 connect issue_slots[11].iss_uop.fp_ctrl.swap12, slots_11.io.iss_uop.fp_ctrl.swap12 connect issue_slots[11].iss_uop.fp_ctrl.ren3, slots_11.io.iss_uop.fp_ctrl.ren3 connect issue_slots[11].iss_uop.fp_ctrl.ren2, slots_11.io.iss_uop.fp_ctrl.ren2 connect issue_slots[11].iss_uop.fp_ctrl.ren1, slots_11.io.iss_uop.fp_ctrl.ren1 connect issue_slots[11].iss_uop.fp_ctrl.wen, slots_11.io.iss_uop.fp_ctrl.wen connect issue_slots[11].iss_uop.fp_ctrl.ldst, slots_11.io.iss_uop.fp_ctrl.ldst connect issue_slots[11].iss_uop.op2_sel, slots_11.io.iss_uop.op2_sel connect issue_slots[11].iss_uop.op1_sel, slots_11.io.iss_uop.op1_sel connect issue_slots[11].iss_uop.imm_packed, slots_11.io.iss_uop.imm_packed connect issue_slots[11].iss_uop.pimm, slots_11.io.iss_uop.pimm connect issue_slots[11].iss_uop.imm_sel, slots_11.io.iss_uop.imm_sel connect issue_slots[11].iss_uop.imm_rename, slots_11.io.iss_uop.imm_rename connect issue_slots[11].iss_uop.taken, slots_11.io.iss_uop.taken connect issue_slots[11].iss_uop.pc_lob, slots_11.io.iss_uop.pc_lob connect issue_slots[11].iss_uop.edge_inst, slots_11.io.iss_uop.edge_inst connect issue_slots[11].iss_uop.ftq_idx, slots_11.io.iss_uop.ftq_idx connect issue_slots[11].iss_uop.is_mov, slots_11.io.iss_uop.is_mov connect issue_slots[11].iss_uop.is_rocc, slots_11.io.iss_uop.is_rocc connect issue_slots[11].iss_uop.is_sys_pc2epc, slots_11.io.iss_uop.is_sys_pc2epc connect issue_slots[11].iss_uop.is_eret, slots_11.io.iss_uop.is_eret connect issue_slots[11].iss_uop.is_amo, slots_11.io.iss_uop.is_amo connect issue_slots[11].iss_uop.is_sfence, slots_11.io.iss_uop.is_sfence connect issue_slots[11].iss_uop.is_fencei, slots_11.io.iss_uop.is_fencei connect issue_slots[11].iss_uop.is_fence, slots_11.io.iss_uop.is_fence connect issue_slots[11].iss_uop.is_sfb, slots_11.io.iss_uop.is_sfb connect issue_slots[11].iss_uop.br_type, slots_11.io.iss_uop.br_type connect issue_slots[11].iss_uop.br_tag, slots_11.io.iss_uop.br_tag connect issue_slots[11].iss_uop.br_mask, slots_11.io.iss_uop.br_mask connect issue_slots[11].iss_uop.dis_col_sel, slots_11.io.iss_uop.dis_col_sel connect issue_slots[11].iss_uop.iw_p3_bypass_hint, slots_11.io.iss_uop.iw_p3_bypass_hint connect issue_slots[11].iss_uop.iw_p2_bypass_hint, slots_11.io.iss_uop.iw_p2_bypass_hint connect issue_slots[11].iss_uop.iw_p1_bypass_hint, slots_11.io.iss_uop.iw_p1_bypass_hint connect issue_slots[11].iss_uop.iw_p2_speculative_child, slots_11.io.iss_uop.iw_p2_speculative_child connect issue_slots[11].iss_uop.iw_p1_speculative_child, slots_11.io.iss_uop.iw_p1_speculative_child connect issue_slots[11].iss_uop.iw_issued_partial_dgen, slots_11.io.iss_uop.iw_issued_partial_dgen connect issue_slots[11].iss_uop.iw_issued_partial_agen, slots_11.io.iss_uop.iw_issued_partial_agen connect issue_slots[11].iss_uop.iw_issued, slots_11.io.iss_uop.iw_issued connect issue_slots[11].iss_uop.fu_code[0], slots_11.io.iss_uop.fu_code[0] connect issue_slots[11].iss_uop.fu_code[1], slots_11.io.iss_uop.fu_code[1] connect issue_slots[11].iss_uop.fu_code[2], slots_11.io.iss_uop.fu_code[2] connect issue_slots[11].iss_uop.fu_code[3], slots_11.io.iss_uop.fu_code[3] connect issue_slots[11].iss_uop.fu_code[4], slots_11.io.iss_uop.fu_code[4] connect issue_slots[11].iss_uop.fu_code[5], slots_11.io.iss_uop.fu_code[5] connect issue_slots[11].iss_uop.fu_code[6], slots_11.io.iss_uop.fu_code[6] connect issue_slots[11].iss_uop.fu_code[7], slots_11.io.iss_uop.fu_code[7] connect issue_slots[11].iss_uop.fu_code[8], slots_11.io.iss_uop.fu_code[8] connect issue_slots[11].iss_uop.fu_code[9], slots_11.io.iss_uop.fu_code[9] connect issue_slots[11].iss_uop.iq_type[0], slots_11.io.iss_uop.iq_type[0] connect issue_slots[11].iss_uop.iq_type[1], slots_11.io.iss_uop.iq_type[1] connect issue_slots[11].iss_uop.iq_type[2], slots_11.io.iss_uop.iq_type[2] connect issue_slots[11].iss_uop.iq_type[3], slots_11.io.iss_uop.iq_type[3] connect issue_slots[11].iss_uop.debug_pc, slots_11.io.iss_uop.debug_pc connect issue_slots[11].iss_uop.is_rvc, slots_11.io.iss_uop.is_rvc connect issue_slots[11].iss_uop.debug_inst, slots_11.io.iss_uop.debug_inst connect issue_slots[11].iss_uop.inst, slots_11.io.iss_uop.inst connect slots_11.io.grant, issue_slots[11].grant connect issue_slots[11].request, slots_11.io.request connect issue_slots[11].will_be_valid, slots_11.io.will_be_valid connect issue_slots[11].valid, slots_11.io.valid connect slots_12.io.child_rebusys, issue_slots[12].child_rebusys connect slots_12.io.pred_wakeup_port.bits, issue_slots[12].pred_wakeup_port.bits connect slots_12.io.pred_wakeup_port.valid, issue_slots[12].pred_wakeup_port.valid connect slots_12.io.wakeup_ports[0].bits.rebusy, issue_slots[12].wakeup_ports[0].bits.rebusy connect slots_12.io.wakeup_ports[0].bits.speculative_mask, issue_slots[12].wakeup_ports[0].bits.speculative_mask connect slots_12.io.wakeup_ports[0].bits.bypassable, issue_slots[12].wakeup_ports[0].bits.bypassable connect slots_12.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[0].bits.uop.debug_tsrc connect slots_12.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[0].bits.uop.debug_fsrc connect slots_12.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_12.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[0].bits.uop.bp_debug_if connect slots_12.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_12.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_12.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_12.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[12].wakeup_ports[0].bits.uop.fp_typ connect slots_12.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[12].wakeup_ports[0].bits.uop.fp_rm connect slots_12.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[12].wakeup_ports[0].bits.uop.fp_val connect slots_12.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[12].wakeup_ports[0].bits.uop.fcn_op connect slots_12.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[0].bits.uop.fcn_dw connect slots_12.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[12].wakeup_ports[0].bits.uop.frs3_en connect slots_12.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_12.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_12.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[0].bits.uop.dst_rtype connect slots_12.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[12].wakeup_ports[0].bits.uop.lrs3 connect slots_12.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[12].wakeup_ports[0].bits.uop.lrs2 connect slots_12.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[12].wakeup_ports[0].bits.uop.lrs1 connect slots_12.io.wakeup_ports[0].bits.uop.ldst, issue_slots[12].wakeup_ports[0].bits.uop.ldst connect slots_12.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_12.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[0].bits.uop.csr_cmd connect slots_12.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[0].bits.uop.flush_on_commit connect slots_12.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[12].wakeup_ports[0].bits.uop.is_unique connect slots_12.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[12].wakeup_ports[0].bits.uop.uses_stq connect slots_12.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[0].bits.uop.uses_ldq connect slots_12.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[12].wakeup_ports[0].bits.uop.mem_signed connect slots_12.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[12].wakeup_ports[0].bits.uop.mem_size connect slots_12.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[0].bits.uop.mem_cmd connect slots_12.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[12].wakeup_ports[0].bits.uop.exc_cause connect slots_12.io.wakeup_ports[0].bits.uop.exception, issue_slots[12].wakeup_ports[0].bits.uop.exception connect slots_12.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[0].bits.uop.stale_pdst connect slots_12.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[0].bits.uop.ppred_busy connect slots_12.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[0].bits.uop.prs3_busy connect slots_12.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[0].bits.uop.prs2_busy connect slots_12.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[0].bits.uop.prs1_busy connect slots_12.io.wakeup_ports[0].bits.uop.ppred, issue_slots[12].wakeup_ports[0].bits.uop.ppred connect slots_12.io.wakeup_ports[0].bits.uop.prs3, issue_slots[12].wakeup_ports[0].bits.uop.prs3 connect slots_12.io.wakeup_ports[0].bits.uop.prs2, issue_slots[12].wakeup_ports[0].bits.uop.prs2 connect slots_12.io.wakeup_ports[0].bits.uop.prs1, issue_slots[12].wakeup_ports[0].bits.uop.prs1 connect slots_12.io.wakeup_ports[0].bits.uop.pdst, issue_slots[12].wakeup_ports[0].bits.uop.pdst connect slots_12.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[0].bits.uop.rxq_idx connect slots_12.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[12].wakeup_ports[0].bits.uop.stq_idx connect slots_12.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[0].bits.uop.ldq_idx connect slots_12.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[12].wakeup_ports[0].bits.uop.rob_idx connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_12.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[12].wakeup_ports[0].bits.uop.op2_sel connect slots_12.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[12].wakeup_ports[0].bits.uop.op1_sel connect slots_12.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[12].wakeup_ports[0].bits.uop.imm_packed connect slots_12.io.wakeup_ports[0].bits.uop.pimm, issue_slots[12].wakeup_ports[0].bits.uop.pimm connect slots_12.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[12].wakeup_ports[0].bits.uop.imm_sel connect slots_12.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[12].wakeup_ports[0].bits.uop.imm_rename connect slots_12.io.wakeup_ports[0].bits.uop.taken, issue_slots[12].wakeup_ports[0].bits.uop.taken connect slots_12.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[12].wakeup_ports[0].bits.uop.pc_lob connect slots_12.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[12].wakeup_ports[0].bits.uop.edge_inst connect slots_12.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[0].bits.uop.ftq_idx connect slots_12.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[12].wakeup_ports[0].bits.uop.is_mov connect slots_12.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[12].wakeup_ports[0].bits.uop.is_rocc connect slots_12.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_12.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[12].wakeup_ports[0].bits.uop.is_eret connect slots_12.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[12].wakeup_ports[0].bits.uop.is_amo connect slots_12.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[12].wakeup_ports[0].bits.uop.is_sfence connect slots_12.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[12].wakeup_ports[0].bits.uop.is_fencei connect slots_12.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[12].wakeup_ports[0].bits.uop.is_fence connect slots_12.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[12].wakeup_ports[0].bits.uop.is_sfb connect slots_12.io.wakeup_ports[0].bits.uop.br_type, issue_slots[12].wakeup_ports[0].bits.uop.br_type connect slots_12.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[12].wakeup_ports[0].bits.uop.br_tag connect slots_12.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[12].wakeup_ports[0].bits.uop.br_mask connect slots_12.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[0].bits.uop.dis_col_sel connect slots_12.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_12.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_12.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_12.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_12.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_12.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_12.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_12.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[12].wakeup_ports[0].bits.uop.iw_issued connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[0] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[1] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[2] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[3] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[4] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[5] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[6] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[7] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[8] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[9] connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[0] connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[1] connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[2] connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[3] connect slots_12.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[12].wakeup_ports[0].bits.uop.debug_pc connect slots_12.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[12].wakeup_ports[0].bits.uop.is_rvc connect slots_12.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[12].wakeup_ports[0].bits.uop.debug_inst connect slots_12.io.wakeup_ports[0].bits.uop.inst, issue_slots[12].wakeup_ports[0].bits.uop.inst connect slots_12.io.wakeup_ports[0].valid, issue_slots[12].wakeup_ports[0].valid connect slots_12.io.wakeup_ports[1].bits.rebusy, issue_slots[12].wakeup_ports[1].bits.rebusy connect slots_12.io.wakeup_ports[1].bits.speculative_mask, issue_slots[12].wakeup_ports[1].bits.speculative_mask connect slots_12.io.wakeup_ports[1].bits.bypassable, issue_slots[12].wakeup_ports[1].bits.bypassable connect slots_12.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[1].bits.uop.debug_tsrc connect slots_12.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[1].bits.uop.debug_fsrc connect slots_12.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_12.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[1].bits.uop.bp_debug_if connect slots_12.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_12.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_12.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_12.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[12].wakeup_ports[1].bits.uop.fp_typ connect slots_12.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[12].wakeup_ports[1].bits.uop.fp_rm connect slots_12.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[12].wakeup_ports[1].bits.uop.fp_val connect slots_12.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[12].wakeup_ports[1].bits.uop.fcn_op connect slots_12.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[1].bits.uop.fcn_dw connect slots_12.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[12].wakeup_ports[1].bits.uop.frs3_en connect slots_12.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_12.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_12.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[1].bits.uop.dst_rtype connect slots_12.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[12].wakeup_ports[1].bits.uop.lrs3 connect slots_12.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[12].wakeup_ports[1].bits.uop.lrs2 connect slots_12.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[12].wakeup_ports[1].bits.uop.lrs1 connect slots_12.io.wakeup_ports[1].bits.uop.ldst, issue_slots[12].wakeup_ports[1].bits.uop.ldst connect slots_12.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_12.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[1].bits.uop.csr_cmd connect slots_12.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[1].bits.uop.flush_on_commit connect slots_12.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[12].wakeup_ports[1].bits.uop.is_unique connect slots_12.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[12].wakeup_ports[1].bits.uop.uses_stq connect slots_12.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[1].bits.uop.uses_ldq connect slots_12.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[12].wakeup_ports[1].bits.uop.mem_signed connect slots_12.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[12].wakeup_ports[1].bits.uop.mem_size connect slots_12.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[1].bits.uop.mem_cmd connect slots_12.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[12].wakeup_ports[1].bits.uop.exc_cause connect slots_12.io.wakeup_ports[1].bits.uop.exception, issue_slots[12].wakeup_ports[1].bits.uop.exception connect slots_12.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[1].bits.uop.stale_pdst connect slots_12.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[1].bits.uop.ppred_busy connect slots_12.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[1].bits.uop.prs3_busy connect slots_12.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[1].bits.uop.prs2_busy connect slots_12.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[1].bits.uop.prs1_busy connect slots_12.io.wakeup_ports[1].bits.uop.ppred, issue_slots[12].wakeup_ports[1].bits.uop.ppred connect slots_12.io.wakeup_ports[1].bits.uop.prs3, issue_slots[12].wakeup_ports[1].bits.uop.prs3 connect slots_12.io.wakeup_ports[1].bits.uop.prs2, issue_slots[12].wakeup_ports[1].bits.uop.prs2 connect slots_12.io.wakeup_ports[1].bits.uop.prs1, issue_slots[12].wakeup_ports[1].bits.uop.prs1 connect slots_12.io.wakeup_ports[1].bits.uop.pdst, issue_slots[12].wakeup_ports[1].bits.uop.pdst connect slots_12.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[1].bits.uop.rxq_idx connect slots_12.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[12].wakeup_ports[1].bits.uop.stq_idx connect slots_12.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[1].bits.uop.ldq_idx connect slots_12.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[12].wakeup_ports[1].bits.uop.rob_idx connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_12.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[12].wakeup_ports[1].bits.uop.op2_sel connect slots_12.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[12].wakeup_ports[1].bits.uop.op1_sel connect slots_12.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[12].wakeup_ports[1].bits.uop.imm_packed connect slots_12.io.wakeup_ports[1].bits.uop.pimm, issue_slots[12].wakeup_ports[1].bits.uop.pimm connect slots_12.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[12].wakeup_ports[1].bits.uop.imm_sel connect slots_12.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[12].wakeup_ports[1].bits.uop.imm_rename connect slots_12.io.wakeup_ports[1].bits.uop.taken, issue_slots[12].wakeup_ports[1].bits.uop.taken connect slots_12.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[12].wakeup_ports[1].bits.uop.pc_lob connect slots_12.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[12].wakeup_ports[1].bits.uop.edge_inst connect slots_12.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[1].bits.uop.ftq_idx connect slots_12.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[12].wakeup_ports[1].bits.uop.is_mov connect slots_12.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[12].wakeup_ports[1].bits.uop.is_rocc connect slots_12.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_12.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[12].wakeup_ports[1].bits.uop.is_eret connect slots_12.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[12].wakeup_ports[1].bits.uop.is_amo connect slots_12.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[12].wakeup_ports[1].bits.uop.is_sfence connect slots_12.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[12].wakeup_ports[1].bits.uop.is_fencei connect slots_12.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[12].wakeup_ports[1].bits.uop.is_fence connect slots_12.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[12].wakeup_ports[1].bits.uop.is_sfb connect slots_12.io.wakeup_ports[1].bits.uop.br_type, issue_slots[12].wakeup_ports[1].bits.uop.br_type connect slots_12.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[12].wakeup_ports[1].bits.uop.br_tag connect slots_12.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[12].wakeup_ports[1].bits.uop.br_mask connect slots_12.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[1].bits.uop.dis_col_sel connect slots_12.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_12.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_12.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_12.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_12.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_12.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_12.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_12.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[12].wakeup_ports[1].bits.uop.iw_issued connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[0] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[1] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[2] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[3] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[4] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[5] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[6] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[7] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[8] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[9] connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[0] connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[1] connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[2] connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[3] connect slots_12.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[12].wakeup_ports[1].bits.uop.debug_pc connect slots_12.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[12].wakeup_ports[1].bits.uop.is_rvc connect slots_12.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[12].wakeup_ports[1].bits.uop.debug_inst connect slots_12.io.wakeup_ports[1].bits.uop.inst, issue_slots[12].wakeup_ports[1].bits.uop.inst connect slots_12.io.wakeup_ports[1].valid, issue_slots[12].wakeup_ports[1].valid connect slots_12.io.wakeup_ports[2].bits.rebusy, issue_slots[12].wakeup_ports[2].bits.rebusy connect slots_12.io.wakeup_ports[2].bits.speculative_mask, issue_slots[12].wakeup_ports[2].bits.speculative_mask connect slots_12.io.wakeup_ports[2].bits.bypassable, issue_slots[12].wakeup_ports[2].bits.bypassable connect slots_12.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[2].bits.uop.debug_tsrc connect slots_12.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[2].bits.uop.debug_fsrc connect slots_12.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_12.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[2].bits.uop.bp_debug_if connect slots_12.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_12.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_12.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_12.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[12].wakeup_ports[2].bits.uop.fp_typ connect slots_12.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[12].wakeup_ports[2].bits.uop.fp_rm connect slots_12.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[12].wakeup_ports[2].bits.uop.fp_val connect slots_12.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[12].wakeup_ports[2].bits.uop.fcn_op connect slots_12.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[2].bits.uop.fcn_dw connect slots_12.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[12].wakeup_ports[2].bits.uop.frs3_en connect slots_12.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_12.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_12.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[2].bits.uop.dst_rtype connect slots_12.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[12].wakeup_ports[2].bits.uop.lrs3 connect slots_12.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[12].wakeup_ports[2].bits.uop.lrs2 connect slots_12.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[12].wakeup_ports[2].bits.uop.lrs1 connect slots_12.io.wakeup_ports[2].bits.uop.ldst, issue_slots[12].wakeup_ports[2].bits.uop.ldst connect slots_12.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_12.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[2].bits.uop.csr_cmd connect slots_12.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[2].bits.uop.flush_on_commit connect slots_12.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[12].wakeup_ports[2].bits.uop.is_unique connect slots_12.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[12].wakeup_ports[2].bits.uop.uses_stq connect slots_12.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[2].bits.uop.uses_ldq connect slots_12.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[12].wakeup_ports[2].bits.uop.mem_signed connect slots_12.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[12].wakeup_ports[2].bits.uop.mem_size connect slots_12.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[2].bits.uop.mem_cmd connect slots_12.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[12].wakeup_ports[2].bits.uop.exc_cause connect slots_12.io.wakeup_ports[2].bits.uop.exception, issue_slots[12].wakeup_ports[2].bits.uop.exception connect slots_12.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[2].bits.uop.stale_pdst connect slots_12.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[2].bits.uop.ppred_busy connect slots_12.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[2].bits.uop.prs3_busy connect slots_12.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[2].bits.uop.prs2_busy connect slots_12.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[2].bits.uop.prs1_busy connect slots_12.io.wakeup_ports[2].bits.uop.ppred, issue_slots[12].wakeup_ports[2].bits.uop.ppred connect slots_12.io.wakeup_ports[2].bits.uop.prs3, issue_slots[12].wakeup_ports[2].bits.uop.prs3 connect slots_12.io.wakeup_ports[2].bits.uop.prs2, issue_slots[12].wakeup_ports[2].bits.uop.prs2 connect slots_12.io.wakeup_ports[2].bits.uop.prs1, issue_slots[12].wakeup_ports[2].bits.uop.prs1 connect slots_12.io.wakeup_ports[2].bits.uop.pdst, issue_slots[12].wakeup_ports[2].bits.uop.pdst connect slots_12.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[2].bits.uop.rxq_idx connect slots_12.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[12].wakeup_ports[2].bits.uop.stq_idx connect slots_12.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[2].bits.uop.ldq_idx connect slots_12.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[12].wakeup_ports[2].bits.uop.rob_idx connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_12.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[12].wakeup_ports[2].bits.uop.op2_sel connect slots_12.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[12].wakeup_ports[2].bits.uop.op1_sel connect slots_12.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[12].wakeup_ports[2].bits.uop.imm_packed connect slots_12.io.wakeup_ports[2].bits.uop.pimm, issue_slots[12].wakeup_ports[2].bits.uop.pimm connect slots_12.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[12].wakeup_ports[2].bits.uop.imm_sel connect slots_12.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[12].wakeup_ports[2].bits.uop.imm_rename connect slots_12.io.wakeup_ports[2].bits.uop.taken, issue_slots[12].wakeup_ports[2].bits.uop.taken connect slots_12.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[12].wakeup_ports[2].bits.uop.pc_lob connect slots_12.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[12].wakeup_ports[2].bits.uop.edge_inst connect slots_12.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[2].bits.uop.ftq_idx connect slots_12.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[12].wakeup_ports[2].bits.uop.is_mov connect slots_12.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[12].wakeup_ports[2].bits.uop.is_rocc connect slots_12.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_12.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[12].wakeup_ports[2].bits.uop.is_eret connect slots_12.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[12].wakeup_ports[2].bits.uop.is_amo connect slots_12.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[12].wakeup_ports[2].bits.uop.is_sfence connect slots_12.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[12].wakeup_ports[2].bits.uop.is_fencei connect slots_12.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[12].wakeup_ports[2].bits.uop.is_fence connect slots_12.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[12].wakeup_ports[2].bits.uop.is_sfb connect slots_12.io.wakeup_ports[2].bits.uop.br_type, issue_slots[12].wakeup_ports[2].bits.uop.br_type connect slots_12.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[12].wakeup_ports[2].bits.uop.br_tag connect slots_12.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[12].wakeup_ports[2].bits.uop.br_mask connect slots_12.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[2].bits.uop.dis_col_sel connect slots_12.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_12.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_12.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_12.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_12.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_12.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_12.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_12.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[12].wakeup_ports[2].bits.uop.iw_issued connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[0] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[1] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[2] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[3] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[4] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[5] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[6] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[7] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[8] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[9] connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[0] connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[1] connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[2] connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[3] connect slots_12.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[12].wakeup_ports[2].bits.uop.debug_pc connect slots_12.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[12].wakeup_ports[2].bits.uop.is_rvc connect slots_12.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[12].wakeup_ports[2].bits.uop.debug_inst connect slots_12.io.wakeup_ports[2].bits.uop.inst, issue_slots[12].wakeup_ports[2].bits.uop.inst connect slots_12.io.wakeup_ports[2].valid, issue_slots[12].wakeup_ports[2].valid connect slots_12.io.wakeup_ports[3].bits.rebusy, issue_slots[12].wakeup_ports[3].bits.rebusy connect slots_12.io.wakeup_ports[3].bits.speculative_mask, issue_slots[12].wakeup_ports[3].bits.speculative_mask connect slots_12.io.wakeup_ports[3].bits.bypassable, issue_slots[12].wakeup_ports[3].bits.bypassable connect slots_12.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[3].bits.uop.debug_tsrc connect slots_12.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[3].bits.uop.debug_fsrc connect slots_12.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_12.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[3].bits.uop.bp_debug_if connect slots_12.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_12.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_12.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_12.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[12].wakeup_ports[3].bits.uop.fp_typ connect slots_12.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[12].wakeup_ports[3].bits.uop.fp_rm connect slots_12.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[12].wakeup_ports[3].bits.uop.fp_val connect slots_12.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[12].wakeup_ports[3].bits.uop.fcn_op connect slots_12.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[3].bits.uop.fcn_dw connect slots_12.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[12].wakeup_ports[3].bits.uop.frs3_en connect slots_12.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_12.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_12.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[3].bits.uop.dst_rtype connect slots_12.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[12].wakeup_ports[3].bits.uop.lrs3 connect slots_12.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[12].wakeup_ports[3].bits.uop.lrs2 connect slots_12.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[12].wakeup_ports[3].bits.uop.lrs1 connect slots_12.io.wakeup_ports[3].bits.uop.ldst, issue_slots[12].wakeup_ports[3].bits.uop.ldst connect slots_12.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_12.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[3].bits.uop.csr_cmd connect slots_12.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[3].bits.uop.flush_on_commit connect slots_12.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[12].wakeup_ports[3].bits.uop.is_unique connect slots_12.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[12].wakeup_ports[3].bits.uop.uses_stq connect slots_12.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[3].bits.uop.uses_ldq connect slots_12.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[12].wakeup_ports[3].bits.uop.mem_signed connect slots_12.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[12].wakeup_ports[3].bits.uop.mem_size connect slots_12.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[3].bits.uop.mem_cmd connect slots_12.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[12].wakeup_ports[3].bits.uop.exc_cause connect slots_12.io.wakeup_ports[3].bits.uop.exception, issue_slots[12].wakeup_ports[3].bits.uop.exception connect slots_12.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[3].bits.uop.stale_pdst connect slots_12.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[3].bits.uop.ppred_busy connect slots_12.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[3].bits.uop.prs3_busy connect slots_12.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[3].bits.uop.prs2_busy connect slots_12.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[3].bits.uop.prs1_busy connect slots_12.io.wakeup_ports[3].bits.uop.ppred, issue_slots[12].wakeup_ports[3].bits.uop.ppred connect slots_12.io.wakeup_ports[3].bits.uop.prs3, issue_slots[12].wakeup_ports[3].bits.uop.prs3 connect slots_12.io.wakeup_ports[3].bits.uop.prs2, issue_slots[12].wakeup_ports[3].bits.uop.prs2 connect slots_12.io.wakeup_ports[3].bits.uop.prs1, issue_slots[12].wakeup_ports[3].bits.uop.prs1 connect slots_12.io.wakeup_ports[3].bits.uop.pdst, issue_slots[12].wakeup_ports[3].bits.uop.pdst connect slots_12.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[3].bits.uop.rxq_idx connect slots_12.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[12].wakeup_ports[3].bits.uop.stq_idx connect slots_12.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[3].bits.uop.ldq_idx connect slots_12.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[12].wakeup_ports[3].bits.uop.rob_idx connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_12.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[12].wakeup_ports[3].bits.uop.op2_sel connect slots_12.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[12].wakeup_ports[3].bits.uop.op1_sel connect slots_12.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[12].wakeup_ports[3].bits.uop.imm_packed connect slots_12.io.wakeup_ports[3].bits.uop.pimm, issue_slots[12].wakeup_ports[3].bits.uop.pimm connect slots_12.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[12].wakeup_ports[3].bits.uop.imm_sel connect slots_12.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[12].wakeup_ports[3].bits.uop.imm_rename connect slots_12.io.wakeup_ports[3].bits.uop.taken, issue_slots[12].wakeup_ports[3].bits.uop.taken connect slots_12.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[12].wakeup_ports[3].bits.uop.pc_lob connect slots_12.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[12].wakeup_ports[3].bits.uop.edge_inst connect slots_12.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[3].bits.uop.ftq_idx connect slots_12.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[12].wakeup_ports[3].bits.uop.is_mov connect slots_12.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[12].wakeup_ports[3].bits.uop.is_rocc connect slots_12.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_12.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[12].wakeup_ports[3].bits.uop.is_eret connect slots_12.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[12].wakeup_ports[3].bits.uop.is_amo connect slots_12.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[12].wakeup_ports[3].bits.uop.is_sfence connect slots_12.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[12].wakeup_ports[3].bits.uop.is_fencei connect slots_12.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[12].wakeup_ports[3].bits.uop.is_fence connect slots_12.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[12].wakeup_ports[3].bits.uop.is_sfb connect slots_12.io.wakeup_ports[3].bits.uop.br_type, issue_slots[12].wakeup_ports[3].bits.uop.br_type connect slots_12.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[12].wakeup_ports[3].bits.uop.br_tag connect slots_12.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[12].wakeup_ports[3].bits.uop.br_mask connect slots_12.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[3].bits.uop.dis_col_sel connect slots_12.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_12.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_12.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_12.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_12.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_12.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_12.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_12.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[12].wakeup_ports[3].bits.uop.iw_issued connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[0] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[1] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[2] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[3] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[4] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[5] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[6] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[7] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[8] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[9] connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[0] connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[1] connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[2] connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[3] connect slots_12.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[12].wakeup_ports[3].bits.uop.debug_pc connect slots_12.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[12].wakeup_ports[3].bits.uop.is_rvc connect slots_12.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[12].wakeup_ports[3].bits.uop.debug_inst connect slots_12.io.wakeup_ports[3].bits.uop.inst, issue_slots[12].wakeup_ports[3].bits.uop.inst connect slots_12.io.wakeup_ports[3].valid, issue_slots[12].wakeup_ports[3].valid connect slots_12.io.wakeup_ports[4].bits.rebusy, issue_slots[12].wakeup_ports[4].bits.rebusy connect slots_12.io.wakeup_ports[4].bits.speculative_mask, issue_slots[12].wakeup_ports[4].bits.speculative_mask connect slots_12.io.wakeup_ports[4].bits.bypassable, issue_slots[12].wakeup_ports[4].bits.bypassable connect slots_12.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[4].bits.uop.debug_tsrc connect slots_12.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[4].bits.uop.debug_fsrc connect slots_12.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_12.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[4].bits.uop.bp_debug_if connect slots_12.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_12.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_12.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_12.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[12].wakeup_ports[4].bits.uop.fp_typ connect slots_12.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[12].wakeup_ports[4].bits.uop.fp_rm connect slots_12.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[12].wakeup_ports[4].bits.uop.fp_val connect slots_12.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[12].wakeup_ports[4].bits.uop.fcn_op connect slots_12.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[4].bits.uop.fcn_dw connect slots_12.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[12].wakeup_ports[4].bits.uop.frs3_en connect slots_12.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_12.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_12.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[4].bits.uop.dst_rtype connect slots_12.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[12].wakeup_ports[4].bits.uop.lrs3 connect slots_12.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[12].wakeup_ports[4].bits.uop.lrs2 connect slots_12.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[12].wakeup_ports[4].bits.uop.lrs1 connect slots_12.io.wakeup_ports[4].bits.uop.ldst, issue_slots[12].wakeup_ports[4].bits.uop.ldst connect slots_12.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_12.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[4].bits.uop.csr_cmd connect slots_12.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[4].bits.uop.flush_on_commit connect slots_12.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[12].wakeup_ports[4].bits.uop.is_unique connect slots_12.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[12].wakeup_ports[4].bits.uop.uses_stq connect slots_12.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[4].bits.uop.uses_ldq connect slots_12.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[12].wakeup_ports[4].bits.uop.mem_signed connect slots_12.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[12].wakeup_ports[4].bits.uop.mem_size connect slots_12.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[4].bits.uop.mem_cmd connect slots_12.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[12].wakeup_ports[4].bits.uop.exc_cause connect slots_12.io.wakeup_ports[4].bits.uop.exception, issue_slots[12].wakeup_ports[4].bits.uop.exception connect slots_12.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[4].bits.uop.stale_pdst connect slots_12.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[4].bits.uop.ppred_busy connect slots_12.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[4].bits.uop.prs3_busy connect slots_12.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[4].bits.uop.prs2_busy connect slots_12.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[4].bits.uop.prs1_busy connect slots_12.io.wakeup_ports[4].bits.uop.ppred, issue_slots[12].wakeup_ports[4].bits.uop.ppred connect slots_12.io.wakeup_ports[4].bits.uop.prs3, issue_slots[12].wakeup_ports[4].bits.uop.prs3 connect slots_12.io.wakeup_ports[4].bits.uop.prs2, issue_slots[12].wakeup_ports[4].bits.uop.prs2 connect slots_12.io.wakeup_ports[4].bits.uop.prs1, issue_slots[12].wakeup_ports[4].bits.uop.prs1 connect slots_12.io.wakeup_ports[4].bits.uop.pdst, issue_slots[12].wakeup_ports[4].bits.uop.pdst connect slots_12.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[4].bits.uop.rxq_idx connect slots_12.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[12].wakeup_ports[4].bits.uop.stq_idx connect slots_12.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[4].bits.uop.ldq_idx connect slots_12.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[12].wakeup_ports[4].bits.uop.rob_idx connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_12.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[12].wakeup_ports[4].bits.uop.op2_sel connect slots_12.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[12].wakeup_ports[4].bits.uop.op1_sel connect slots_12.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[12].wakeup_ports[4].bits.uop.imm_packed connect slots_12.io.wakeup_ports[4].bits.uop.pimm, issue_slots[12].wakeup_ports[4].bits.uop.pimm connect slots_12.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[12].wakeup_ports[4].bits.uop.imm_sel connect slots_12.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[12].wakeup_ports[4].bits.uop.imm_rename connect slots_12.io.wakeup_ports[4].bits.uop.taken, issue_slots[12].wakeup_ports[4].bits.uop.taken connect slots_12.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[12].wakeup_ports[4].bits.uop.pc_lob connect slots_12.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[12].wakeup_ports[4].bits.uop.edge_inst connect slots_12.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[4].bits.uop.ftq_idx connect slots_12.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[12].wakeup_ports[4].bits.uop.is_mov connect slots_12.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[12].wakeup_ports[4].bits.uop.is_rocc connect slots_12.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_12.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[12].wakeup_ports[4].bits.uop.is_eret connect slots_12.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[12].wakeup_ports[4].bits.uop.is_amo connect slots_12.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[12].wakeup_ports[4].bits.uop.is_sfence connect slots_12.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[12].wakeup_ports[4].bits.uop.is_fencei connect slots_12.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[12].wakeup_ports[4].bits.uop.is_fence connect slots_12.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[12].wakeup_ports[4].bits.uop.is_sfb connect slots_12.io.wakeup_ports[4].bits.uop.br_type, issue_slots[12].wakeup_ports[4].bits.uop.br_type connect slots_12.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[12].wakeup_ports[4].bits.uop.br_tag connect slots_12.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[12].wakeup_ports[4].bits.uop.br_mask connect slots_12.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[4].bits.uop.dis_col_sel connect slots_12.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_12.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_12.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_12.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_12.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_12.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_12.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_12.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[12].wakeup_ports[4].bits.uop.iw_issued connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[0] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[1] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[2] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[3] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[4] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[5] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[6] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[7] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[8] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[9] connect slots_12.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[4].bits.uop.iq_type[0] connect slots_12.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[4].bits.uop.iq_type[1] connect slots_12.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[4].bits.uop.iq_type[2] connect slots_12.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[4].bits.uop.iq_type[3] connect slots_12.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[12].wakeup_ports[4].bits.uop.debug_pc connect slots_12.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[12].wakeup_ports[4].bits.uop.is_rvc connect slots_12.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[12].wakeup_ports[4].bits.uop.debug_inst connect slots_12.io.wakeup_ports[4].bits.uop.inst, issue_slots[12].wakeup_ports[4].bits.uop.inst connect slots_12.io.wakeup_ports[4].valid, issue_slots[12].wakeup_ports[4].valid connect slots_12.io.squash_grant, issue_slots[12].squash_grant connect slots_12.io.clear, issue_slots[12].clear connect slots_12.io.kill, issue_slots[12].kill connect slots_12.io.brupdate.b2.target_offset, issue_slots[12].brupdate.b2.target_offset connect slots_12.io.brupdate.b2.jalr_target, issue_slots[12].brupdate.b2.jalr_target connect slots_12.io.brupdate.b2.pc_sel, issue_slots[12].brupdate.b2.pc_sel connect slots_12.io.brupdate.b2.cfi_type, issue_slots[12].brupdate.b2.cfi_type connect slots_12.io.brupdate.b2.taken, issue_slots[12].brupdate.b2.taken connect slots_12.io.brupdate.b2.mispredict, issue_slots[12].brupdate.b2.mispredict connect slots_12.io.brupdate.b2.uop.debug_tsrc, issue_slots[12].brupdate.b2.uop.debug_tsrc connect slots_12.io.brupdate.b2.uop.debug_fsrc, issue_slots[12].brupdate.b2.uop.debug_fsrc connect slots_12.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[12].brupdate.b2.uop.bp_xcpt_if connect slots_12.io.brupdate.b2.uop.bp_debug_if, issue_slots[12].brupdate.b2.uop.bp_debug_if connect slots_12.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[12].brupdate.b2.uop.xcpt_ma_if connect slots_12.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[12].brupdate.b2.uop.xcpt_ae_if connect slots_12.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[12].brupdate.b2.uop.xcpt_pf_if connect slots_12.io.brupdate.b2.uop.fp_typ, issue_slots[12].brupdate.b2.uop.fp_typ connect slots_12.io.brupdate.b2.uop.fp_rm, issue_slots[12].brupdate.b2.uop.fp_rm connect slots_12.io.brupdate.b2.uop.fp_val, issue_slots[12].brupdate.b2.uop.fp_val connect slots_12.io.brupdate.b2.uop.fcn_op, issue_slots[12].brupdate.b2.uop.fcn_op connect slots_12.io.brupdate.b2.uop.fcn_dw, issue_slots[12].brupdate.b2.uop.fcn_dw connect slots_12.io.brupdate.b2.uop.frs3_en, issue_slots[12].brupdate.b2.uop.frs3_en connect slots_12.io.brupdate.b2.uop.lrs2_rtype, issue_slots[12].brupdate.b2.uop.lrs2_rtype connect slots_12.io.brupdate.b2.uop.lrs1_rtype, issue_slots[12].brupdate.b2.uop.lrs1_rtype connect slots_12.io.brupdate.b2.uop.dst_rtype, issue_slots[12].brupdate.b2.uop.dst_rtype connect slots_12.io.brupdate.b2.uop.lrs3, issue_slots[12].brupdate.b2.uop.lrs3 connect slots_12.io.brupdate.b2.uop.lrs2, issue_slots[12].brupdate.b2.uop.lrs2 connect slots_12.io.brupdate.b2.uop.lrs1, issue_slots[12].brupdate.b2.uop.lrs1 connect slots_12.io.brupdate.b2.uop.ldst, issue_slots[12].brupdate.b2.uop.ldst connect slots_12.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[12].brupdate.b2.uop.ldst_is_rs1 connect slots_12.io.brupdate.b2.uop.csr_cmd, issue_slots[12].brupdate.b2.uop.csr_cmd connect slots_12.io.brupdate.b2.uop.flush_on_commit, issue_slots[12].brupdate.b2.uop.flush_on_commit connect slots_12.io.brupdate.b2.uop.is_unique, issue_slots[12].brupdate.b2.uop.is_unique connect slots_12.io.brupdate.b2.uop.uses_stq, issue_slots[12].brupdate.b2.uop.uses_stq connect slots_12.io.brupdate.b2.uop.uses_ldq, issue_slots[12].brupdate.b2.uop.uses_ldq connect slots_12.io.brupdate.b2.uop.mem_signed, issue_slots[12].brupdate.b2.uop.mem_signed connect slots_12.io.brupdate.b2.uop.mem_size, issue_slots[12].brupdate.b2.uop.mem_size connect slots_12.io.brupdate.b2.uop.mem_cmd, issue_slots[12].brupdate.b2.uop.mem_cmd connect slots_12.io.brupdate.b2.uop.exc_cause, issue_slots[12].brupdate.b2.uop.exc_cause connect slots_12.io.brupdate.b2.uop.exception, issue_slots[12].brupdate.b2.uop.exception connect slots_12.io.brupdate.b2.uop.stale_pdst, issue_slots[12].brupdate.b2.uop.stale_pdst connect slots_12.io.brupdate.b2.uop.ppred_busy, issue_slots[12].brupdate.b2.uop.ppred_busy connect slots_12.io.brupdate.b2.uop.prs3_busy, issue_slots[12].brupdate.b2.uop.prs3_busy connect slots_12.io.brupdate.b2.uop.prs2_busy, issue_slots[12].brupdate.b2.uop.prs2_busy connect slots_12.io.brupdate.b2.uop.prs1_busy, issue_slots[12].brupdate.b2.uop.prs1_busy connect slots_12.io.brupdate.b2.uop.ppred, issue_slots[12].brupdate.b2.uop.ppred connect slots_12.io.brupdate.b2.uop.prs3, issue_slots[12].brupdate.b2.uop.prs3 connect slots_12.io.brupdate.b2.uop.prs2, issue_slots[12].brupdate.b2.uop.prs2 connect slots_12.io.brupdate.b2.uop.prs1, issue_slots[12].brupdate.b2.uop.prs1 connect slots_12.io.brupdate.b2.uop.pdst, issue_slots[12].brupdate.b2.uop.pdst connect slots_12.io.brupdate.b2.uop.rxq_idx, issue_slots[12].brupdate.b2.uop.rxq_idx connect slots_12.io.brupdate.b2.uop.stq_idx, issue_slots[12].brupdate.b2.uop.stq_idx connect slots_12.io.brupdate.b2.uop.ldq_idx, issue_slots[12].brupdate.b2.uop.ldq_idx connect slots_12.io.brupdate.b2.uop.rob_idx, issue_slots[12].brupdate.b2.uop.rob_idx connect slots_12.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[12].brupdate.b2.uop.fp_ctrl.vec connect slots_12.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[12].brupdate.b2.uop.fp_ctrl.wflags connect slots_12.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[12].brupdate.b2.uop.fp_ctrl.sqrt connect slots_12.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[12].brupdate.b2.uop.fp_ctrl.div connect slots_12.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[12].brupdate.b2.uop.fp_ctrl.fma connect slots_12.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[12].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_12.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[12].brupdate.b2.uop.fp_ctrl.toint connect slots_12.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[12].brupdate.b2.uop.fp_ctrl.fromint connect slots_12.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_12.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_12.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[12].brupdate.b2.uop.fp_ctrl.swap23 connect slots_12.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[12].brupdate.b2.uop.fp_ctrl.swap12 connect slots_12.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[12].brupdate.b2.uop.fp_ctrl.ren3 connect slots_12.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[12].brupdate.b2.uop.fp_ctrl.ren2 connect slots_12.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[12].brupdate.b2.uop.fp_ctrl.ren1 connect slots_12.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[12].brupdate.b2.uop.fp_ctrl.wen connect slots_12.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[12].brupdate.b2.uop.fp_ctrl.ldst connect slots_12.io.brupdate.b2.uop.op2_sel, issue_slots[12].brupdate.b2.uop.op2_sel connect slots_12.io.brupdate.b2.uop.op1_sel, issue_slots[12].brupdate.b2.uop.op1_sel connect slots_12.io.brupdate.b2.uop.imm_packed, issue_slots[12].brupdate.b2.uop.imm_packed connect slots_12.io.brupdate.b2.uop.pimm, issue_slots[12].brupdate.b2.uop.pimm connect slots_12.io.brupdate.b2.uop.imm_sel, issue_slots[12].brupdate.b2.uop.imm_sel connect slots_12.io.brupdate.b2.uop.imm_rename, issue_slots[12].brupdate.b2.uop.imm_rename connect slots_12.io.brupdate.b2.uop.taken, issue_slots[12].brupdate.b2.uop.taken connect slots_12.io.brupdate.b2.uop.pc_lob, issue_slots[12].brupdate.b2.uop.pc_lob connect slots_12.io.brupdate.b2.uop.edge_inst, issue_slots[12].brupdate.b2.uop.edge_inst connect slots_12.io.brupdate.b2.uop.ftq_idx, issue_slots[12].brupdate.b2.uop.ftq_idx connect slots_12.io.brupdate.b2.uop.is_mov, issue_slots[12].brupdate.b2.uop.is_mov connect slots_12.io.brupdate.b2.uop.is_rocc, issue_slots[12].brupdate.b2.uop.is_rocc connect slots_12.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[12].brupdate.b2.uop.is_sys_pc2epc connect slots_12.io.brupdate.b2.uop.is_eret, issue_slots[12].brupdate.b2.uop.is_eret connect slots_12.io.brupdate.b2.uop.is_amo, issue_slots[12].brupdate.b2.uop.is_amo connect slots_12.io.brupdate.b2.uop.is_sfence, issue_slots[12].brupdate.b2.uop.is_sfence connect slots_12.io.brupdate.b2.uop.is_fencei, issue_slots[12].brupdate.b2.uop.is_fencei connect slots_12.io.brupdate.b2.uop.is_fence, issue_slots[12].brupdate.b2.uop.is_fence connect slots_12.io.brupdate.b2.uop.is_sfb, issue_slots[12].brupdate.b2.uop.is_sfb connect slots_12.io.brupdate.b2.uop.br_type, issue_slots[12].brupdate.b2.uop.br_type connect slots_12.io.brupdate.b2.uop.br_tag, issue_slots[12].brupdate.b2.uop.br_tag connect slots_12.io.brupdate.b2.uop.br_mask, issue_slots[12].brupdate.b2.uop.br_mask connect slots_12.io.brupdate.b2.uop.dis_col_sel, issue_slots[12].brupdate.b2.uop.dis_col_sel connect slots_12.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[12].brupdate.b2.uop.iw_p3_bypass_hint connect slots_12.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[12].brupdate.b2.uop.iw_p2_bypass_hint connect slots_12.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[12].brupdate.b2.uop.iw_p1_bypass_hint connect slots_12.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[12].brupdate.b2.uop.iw_p2_speculative_child connect slots_12.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[12].brupdate.b2.uop.iw_p1_speculative_child connect slots_12.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[12].brupdate.b2.uop.iw_issued_partial_dgen connect slots_12.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[12].brupdate.b2.uop.iw_issued_partial_agen connect slots_12.io.brupdate.b2.uop.iw_issued, issue_slots[12].brupdate.b2.uop.iw_issued connect slots_12.io.brupdate.b2.uop.fu_code[0], issue_slots[12].brupdate.b2.uop.fu_code[0] connect slots_12.io.brupdate.b2.uop.fu_code[1], issue_slots[12].brupdate.b2.uop.fu_code[1] connect slots_12.io.brupdate.b2.uop.fu_code[2], issue_slots[12].brupdate.b2.uop.fu_code[2] connect slots_12.io.brupdate.b2.uop.fu_code[3], issue_slots[12].brupdate.b2.uop.fu_code[3] connect slots_12.io.brupdate.b2.uop.fu_code[4], issue_slots[12].brupdate.b2.uop.fu_code[4] connect slots_12.io.brupdate.b2.uop.fu_code[5], issue_slots[12].brupdate.b2.uop.fu_code[5] connect slots_12.io.brupdate.b2.uop.fu_code[6], issue_slots[12].brupdate.b2.uop.fu_code[6] connect slots_12.io.brupdate.b2.uop.fu_code[7], issue_slots[12].brupdate.b2.uop.fu_code[7] connect slots_12.io.brupdate.b2.uop.fu_code[8], issue_slots[12].brupdate.b2.uop.fu_code[8] connect slots_12.io.brupdate.b2.uop.fu_code[9], issue_slots[12].brupdate.b2.uop.fu_code[9] connect slots_12.io.brupdate.b2.uop.iq_type[0], issue_slots[12].brupdate.b2.uop.iq_type[0] connect slots_12.io.brupdate.b2.uop.iq_type[1], issue_slots[12].brupdate.b2.uop.iq_type[1] connect slots_12.io.brupdate.b2.uop.iq_type[2], issue_slots[12].brupdate.b2.uop.iq_type[2] connect slots_12.io.brupdate.b2.uop.iq_type[3], issue_slots[12].brupdate.b2.uop.iq_type[3] connect slots_12.io.brupdate.b2.uop.debug_pc, issue_slots[12].brupdate.b2.uop.debug_pc connect slots_12.io.brupdate.b2.uop.is_rvc, issue_slots[12].brupdate.b2.uop.is_rvc connect slots_12.io.brupdate.b2.uop.debug_inst, issue_slots[12].brupdate.b2.uop.debug_inst connect slots_12.io.brupdate.b2.uop.inst, issue_slots[12].brupdate.b2.uop.inst connect slots_12.io.brupdate.b1.mispredict_mask, issue_slots[12].brupdate.b1.mispredict_mask connect slots_12.io.brupdate.b1.resolve_mask, issue_slots[12].brupdate.b1.resolve_mask connect issue_slots[12].out_uop.debug_tsrc, slots_12.io.out_uop.debug_tsrc connect issue_slots[12].out_uop.debug_fsrc, slots_12.io.out_uop.debug_fsrc connect issue_slots[12].out_uop.bp_xcpt_if, slots_12.io.out_uop.bp_xcpt_if connect issue_slots[12].out_uop.bp_debug_if, slots_12.io.out_uop.bp_debug_if connect issue_slots[12].out_uop.xcpt_ma_if, slots_12.io.out_uop.xcpt_ma_if connect issue_slots[12].out_uop.xcpt_ae_if, slots_12.io.out_uop.xcpt_ae_if connect issue_slots[12].out_uop.xcpt_pf_if, slots_12.io.out_uop.xcpt_pf_if connect issue_slots[12].out_uop.fp_typ, slots_12.io.out_uop.fp_typ connect issue_slots[12].out_uop.fp_rm, slots_12.io.out_uop.fp_rm connect issue_slots[12].out_uop.fp_val, slots_12.io.out_uop.fp_val connect issue_slots[12].out_uop.fcn_op, slots_12.io.out_uop.fcn_op connect issue_slots[12].out_uop.fcn_dw, slots_12.io.out_uop.fcn_dw connect issue_slots[12].out_uop.frs3_en, slots_12.io.out_uop.frs3_en connect issue_slots[12].out_uop.lrs2_rtype, slots_12.io.out_uop.lrs2_rtype connect issue_slots[12].out_uop.lrs1_rtype, slots_12.io.out_uop.lrs1_rtype connect issue_slots[12].out_uop.dst_rtype, slots_12.io.out_uop.dst_rtype connect issue_slots[12].out_uop.lrs3, slots_12.io.out_uop.lrs3 connect issue_slots[12].out_uop.lrs2, slots_12.io.out_uop.lrs2 connect issue_slots[12].out_uop.lrs1, slots_12.io.out_uop.lrs1 connect issue_slots[12].out_uop.ldst, slots_12.io.out_uop.ldst connect issue_slots[12].out_uop.ldst_is_rs1, slots_12.io.out_uop.ldst_is_rs1 connect issue_slots[12].out_uop.csr_cmd, slots_12.io.out_uop.csr_cmd connect issue_slots[12].out_uop.flush_on_commit, slots_12.io.out_uop.flush_on_commit connect issue_slots[12].out_uop.is_unique, slots_12.io.out_uop.is_unique connect issue_slots[12].out_uop.uses_stq, slots_12.io.out_uop.uses_stq connect issue_slots[12].out_uop.uses_ldq, slots_12.io.out_uop.uses_ldq connect issue_slots[12].out_uop.mem_signed, slots_12.io.out_uop.mem_signed connect issue_slots[12].out_uop.mem_size, slots_12.io.out_uop.mem_size connect issue_slots[12].out_uop.mem_cmd, slots_12.io.out_uop.mem_cmd connect issue_slots[12].out_uop.exc_cause, slots_12.io.out_uop.exc_cause connect issue_slots[12].out_uop.exception, slots_12.io.out_uop.exception connect issue_slots[12].out_uop.stale_pdst, slots_12.io.out_uop.stale_pdst connect issue_slots[12].out_uop.ppred_busy, slots_12.io.out_uop.ppred_busy connect issue_slots[12].out_uop.prs3_busy, slots_12.io.out_uop.prs3_busy connect issue_slots[12].out_uop.prs2_busy, slots_12.io.out_uop.prs2_busy connect issue_slots[12].out_uop.prs1_busy, slots_12.io.out_uop.prs1_busy connect issue_slots[12].out_uop.ppred, slots_12.io.out_uop.ppred connect issue_slots[12].out_uop.prs3, slots_12.io.out_uop.prs3 connect issue_slots[12].out_uop.prs2, slots_12.io.out_uop.prs2 connect issue_slots[12].out_uop.prs1, slots_12.io.out_uop.prs1 connect issue_slots[12].out_uop.pdst, slots_12.io.out_uop.pdst connect issue_slots[12].out_uop.rxq_idx, slots_12.io.out_uop.rxq_idx connect issue_slots[12].out_uop.stq_idx, slots_12.io.out_uop.stq_idx connect issue_slots[12].out_uop.ldq_idx, slots_12.io.out_uop.ldq_idx connect issue_slots[12].out_uop.rob_idx, slots_12.io.out_uop.rob_idx connect issue_slots[12].out_uop.fp_ctrl.vec, slots_12.io.out_uop.fp_ctrl.vec connect issue_slots[12].out_uop.fp_ctrl.wflags, slots_12.io.out_uop.fp_ctrl.wflags connect issue_slots[12].out_uop.fp_ctrl.sqrt, slots_12.io.out_uop.fp_ctrl.sqrt connect issue_slots[12].out_uop.fp_ctrl.div, slots_12.io.out_uop.fp_ctrl.div connect issue_slots[12].out_uop.fp_ctrl.fma, slots_12.io.out_uop.fp_ctrl.fma connect issue_slots[12].out_uop.fp_ctrl.fastpipe, slots_12.io.out_uop.fp_ctrl.fastpipe connect issue_slots[12].out_uop.fp_ctrl.toint, slots_12.io.out_uop.fp_ctrl.toint connect issue_slots[12].out_uop.fp_ctrl.fromint, slots_12.io.out_uop.fp_ctrl.fromint connect issue_slots[12].out_uop.fp_ctrl.typeTagOut, slots_12.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[12].out_uop.fp_ctrl.typeTagIn, slots_12.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[12].out_uop.fp_ctrl.swap23, slots_12.io.out_uop.fp_ctrl.swap23 connect issue_slots[12].out_uop.fp_ctrl.swap12, slots_12.io.out_uop.fp_ctrl.swap12 connect issue_slots[12].out_uop.fp_ctrl.ren3, slots_12.io.out_uop.fp_ctrl.ren3 connect issue_slots[12].out_uop.fp_ctrl.ren2, slots_12.io.out_uop.fp_ctrl.ren2 connect issue_slots[12].out_uop.fp_ctrl.ren1, slots_12.io.out_uop.fp_ctrl.ren1 connect issue_slots[12].out_uop.fp_ctrl.wen, slots_12.io.out_uop.fp_ctrl.wen connect issue_slots[12].out_uop.fp_ctrl.ldst, slots_12.io.out_uop.fp_ctrl.ldst connect issue_slots[12].out_uop.op2_sel, slots_12.io.out_uop.op2_sel connect issue_slots[12].out_uop.op1_sel, slots_12.io.out_uop.op1_sel connect issue_slots[12].out_uop.imm_packed, slots_12.io.out_uop.imm_packed connect issue_slots[12].out_uop.pimm, slots_12.io.out_uop.pimm connect issue_slots[12].out_uop.imm_sel, slots_12.io.out_uop.imm_sel connect issue_slots[12].out_uop.imm_rename, slots_12.io.out_uop.imm_rename connect issue_slots[12].out_uop.taken, slots_12.io.out_uop.taken connect issue_slots[12].out_uop.pc_lob, slots_12.io.out_uop.pc_lob connect issue_slots[12].out_uop.edge_inst, slots_12.io.out_uop.edge_inst connect issue_slots[12].out_uop.ftq_idx, slots_12.io.out_uop.ftq_idx connect issue_slots[12].out_uop.is_mov, slots_12.io.out_uop.is_mov connect issue_slots[12].out_uop.is_rocc, slots_12.io.out_uop.is_rocc connect issue_slots[12].out_uop.is_sys_pc2epc, slots_12.io.out_uop.is_sys_pc2epc connect issue_slots[12].out_uop.is_eret, slots_12.io.out_uop.is_eret connect issue_slots[12].out_uop.is_amo, slots_12.io.out_uop.is_amo connect issue_slots[12].out_uop.is_sfence, slots_12.io.out_uop.is_sfence connect issue_slots[12].out_uop.is_fencei, slots_12.io.out_uop.is_fencei connect issue_slots[12].out_uop.is_fence, slots_12.io.out_uop.is_fence connect issue_slots[12].out_uop.is_sfb, slots_12.io.out_uop.is_sfb connect issue_slots[12].out_uop.br_type, slots_12.io.out_uop.br_type connect issue_slots[12].out_uop.br_tag, slots_12.io.out_uop.br_tag connect issue_slots[12].out_uop.br_mask, slots_12.io.out_uop.br_mask connect issue_slots[12].out_uop.dis_col_sel, slots_12.io.out_uop.dis_col_sel connect issue_slots[12].out_uop.iw_p3_bypass_hint, slots_12.io.out_uop.iw_p3_bypass_hint connect issue_slots[12].out_uop.iw_p2_bypass_hint, slots_12.io.out_uop.iw_p2_bypass_hint connect issue_slots[12].out_uop.iw_p1_bypass_hint, slots_12.io.out_uop.iw_p1_bypass_hint connect issue_slots[12].out_uop.iw_p2_speculative_child, slots_12.io.out_uop.iw_p2_speculative_child connect issue_slots[12].out_uop.iw_p1_speculative_child, slots_12.io.out_uop.iw_p1_speculative_child connect issue_slots[12].out_uop.iw_issued_partial_dgen, slots_12.io.out_uop.iw_issued_partial_dgen connect issue_slots[12].out_uop.iw_issued_partial_agen, slots_12.io.out_uop.iw_issued_partial_agen connect issue_slots[12].out_uop.iw_issued, slots_12.io.out_uop.iw_issued connect issue_slots[12].out_uop.fu_code[0], slots_12.io.out_uop.fu_code[0] connect issue_slots[12].out_uop.fu_code[1], slots_12.io.out_uop.fu_code[1] connect issue_slots[12].out_uop.fu_code[2], slots_12.io.out_uop.fu_code[2] connect issue_slots[12].out_uop.fu_code[3], slots_12.io.out_uop.fu_code[3] connect issue_slots[12].out_uop.fu_code[4], slots_12.io.out_uop.fu_code[4] connect issue_slots[12].out_uop.fu_code[5], slots_12.io.out_uop.fu_code[5] connect issue_slots[12].out_uop.fu_code[6], slots_12.io.out_uop.fu_code[6] connect issue_slots[12].out_uop.fu_code[7], slots_12.io.out_uop.fu_code[7] connect issue_slots[12].out_uop.fu_code[8], slots_12.io.out_uop.fu_code[8] connect issue_slots[12].out_uop.fu_code[9], slots_12.io.out_uop.fu_code[9] connect issue_slots[12].out_uop.iq_type[0], slots_12.io.out_uop.iq_type[0] connect issue_slots[12].out_uop.iq_type[1], slots_12.io.out_uop.iq_type[1] connect issue_slots[12].out_uop.iq_type[2], slots_12.io.out_uop.iq_type[2] connect issue_slots[12].out_uop.iq_type[3], slots_12.io.out_uop.iq_type[3] connect issue_slots[12].out_uop.debug_pc, slots_12.io.out_uop.debug_pc connect issue_slots[12].out_uop.is_rvc, slots_12.io.out_uop.is_rvc connect issue_slots[12].out_uop.debug_inst, slots_12.io.out_uop.debug_inst connect issue_slots[12].out_uop.inst, slots_12.io.out_uop.inst connect slots_12.io.in_uop.bits.debug_tsrc, issue_slots[12].in_uop.bits.debug_tsrc connect slots_12.io.in_uop.bits.debug_fsrc, issue_slots[12].in_uop.bits.debug_fsrc connect slots_12.io.in_uop.bits.bp_xcpt_if, issue_slots[12].in_uop.bits.bp_xcpt_if connect slots_12.io.in_uop.bits.bp_debug_if, issue_slots[12].in_uop.bits.bp_debug_if connect slots_12.io.in_uop.bits.xcpt_ma_if, issue_slots[12].in_uop.bits.xcpt_ma_if connect slots_12.io.in_uop.bits.xcpt_ae_if, issue_slots[12].in_uop.bits.xcpt_ae_if connect slots_12.io.in_uop.bits.xcpt_pf_if, issue_slots[12].in_uop.bits.xcpt_pf_if connect slots_12.io.in_uop.bits.fp_typ, issue_slots[12].in_uop.bits.fp_typ connect slots_12.io.in_uop.bits.fp_rm, issue_slots[12].in_uop.bits.fp_rm connect slots_12.io.in_uop.bits.fp_val, issue_slots[12].in_uop.bits.fp_val connect slots_12.io.in_uop.bits.fcn_op, issue_slots[12].in_uop.bits.fcn_op connect slots_12.io.in_uop.bits.fcn_dw, issue_slots[12].in_uop.bits.fcn_dw connect slots_12.io.in_uop.bits.frs3_en, issue_slots[12].in_uop.bits.frs3_en connect slots_12.io.in_uop.bits.lrs2_rtype, issue_slots[12].in_uop.bits.lrs2_rtype connect slots_12.io.in_uop.bits.lrs1_rtype, issue_slots[12].in_uop.bits.lrs1_rtype connect slots_12.io.in_uop.bits.dst_rtype, issue_slots[12].in_uop.bits.dst_rtype connect slots_12.io.in_uop.bits.lrs3, issue_slots[12].in_uop.bits.lrs3 connect slots_12.io.in_uop.bits.lrs2, issue_slots[12].in_uop.bits.lrs2 connect slots_12.io.in_uop.bits.lrs1, issue_slots[12].in_uop.bits.lrs1 connect slots_12.io.in_uop.bits.ldst, issue_slots[12].in_uop.bits.ldst connect slots_12.io.in_uop.bits.ldst_is_rs1, issue_slots[12].in_uop.bits.ldst_is_rs1 connect slots_12.io.in_uop.bits.csr_cmd, issue_slots[12].in_uop.bits.csr_cmd connect slots_12.io.in_uop.bits.flush_on_commit, issue_slots[12].in_uop.bits.flush_on_commit connect slots_12.io.in_uop.bits.is_unique, issue_slots[12].in_uop.bits.is_unique connect slots_12.io.in_uop.bits.uses_stq, issue_slots[12].in_uop.bits.uses_stq connect slots_12.io.in_uop.bits.uses_ldq, issue_slots[12].in_uop.bits.uses_ldq connect slots_12.io.in_uop.bits.mem_signed, issue_slots[12].in_uop.bits.mem_signed connect slots_12.io.in_uop.bits.mem_size, issue_slots[12].in_uop.bits.mem_size connect slots_12.io.in_uop.bits.mem_cmd, issue_slots[12].in_uop.bits.mem_cmd connect slots_12.io.in_uop.bits.exc_cause, issue_slots[12].in_uop.bits.exc_cause connect slots_12.io.in_uop.bits.exception, issue_slots[12].in_uop.bits.exception connect slots_12.io.in_uop.bits.stale_pdst, issue_slots[12].in_uop.bits.stale_pdst connect slots_12.io.in_uop.bits.ppred_busy, issue_slots[12].in_uop.bits.ppred_busy connect slots_12.io.in_uop.bits.prs3_busy, issue_slots[12].in_uop.bits.prs3_busy connect slots_12.io.in_uop.bits.prs2_busy, issue_slots[12].in_uop.bits.prs2_busy connect slots_12.io.in_uop.bits.prs1_busy, issue_slots[12].in_uop.bits.prs1_busy connect slots_12.io.in_uop.bits.ppred, issue_slots[12].in_uop.bits.ppred connect slots_12.io.in_uop.bits.prs3, issue_slots[12].in_uop.bits.prs3 connect slots_12.io.in_uop.bits.prs2, issue_slots[12].in_uop.bits.prs2 connect slots_12.io.in_uop.bits.prs1, issue_slots[12].in_uop.bits.prs1 connect slots_12.io.in_uop.bits.pdst, issue_slots[12].in_uop.bits.pdst connect slots_12.io.in_uop.bits.rxq_idx, issue_slots[12].in_uop.bits.rxq_idx connect slots_12.io.in_uop.bits.stq_idx, issue_slots[12].in_uop.bits.stq_idx connect slots_12.io.in_uop.bits.ldq_idx, issue_slots[12].in_uop.bits.ldq_idx connect slots_12.io.in_uop.bits.rob_idx, issue_slots[12].in_uop.bits.rob_idx connect slots_12.io.in_uop.bits.fp_ctrl.vec, issue_slots[12].in_uop.bits.fp_ctrl.vec connect slots_12.io.in_uop.bits.fp_ctrl.wflags, issue_slots[12].in_uop.bits.fp_ctrl.wflags connect slots_12.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[12].in_uop.bits.fp_ctrl.sqrt connect slots_12.io.in_uop.bits.fp_ctrl.div, issue_slots[12].in_uop.bits.fp_ctrl.div connect slots_12.io.in_uop.bits.fp_ctrl.fma, issue_slots[12].in_uop.bits.fp_ctrl.fma connect slots_12.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].in_uop.bits.fp_ctrl.fastpipe connect slots_12.io.in_uop.bits.fp_ctrl.toint, issue_slots[12].in_uop.bits.fp_ctrl.toint connect slots_12.io.in_uop.bits.fp_ctrl.fromint, issue_slots[12].in_uop.bits.fp_ctrl.fromint connect slots_12.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut connect slots_12.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn connect slots_12.io.in_uop.bits.fp_ctrl.swap23, issue_slots[12].in_uop.bits.fp_ctrl.swap23 connect slots_12.io.in_uop.bits.fp_ctrl.swap12, issue_slots[12].in_uop.bits.fp_ctrl.swap12 connect slots_12.io.in_uop.bits.fp_ctrl.ren3, issue_slots[12].in_uop.bits.fp_ctrl.ren3 connect slots_12.io.in_uop.bits.fp_ctrl.ren2, issue_slots[12].in_uop.bits.fp_ctrl.ren2 connect slots_12.io.in_uop.bits.fp_ctrl.ren1, issue_slots[12].in_uop.bits.fp_ctrl.ren1 connect slots_12.io.in_uop.bits.fp_ctrl.wen, issue_slots[12].in_uop.bits.fp_ctrl.wen connect slots_12.io.in_uop.bits.fp_ctrl.ldst, issue_slots[12].in_uop.bits.fp_ctrl.ldst connect slots_12.io.in_uop.bits.op2_sel, issue_slots[12].in_uop.bits.op2_sel connect slots_12.io.in_uop.bits.op1_sel, issue_slots[12].in_uop.bits.op1_sel connect slots_12.io.in_uop.bits.imm_packed, issue_slots[12].in_uop.bits.imm_packed connect slots_12.io.in_uop.bits.pimm, issue_slots[12].in_uop.bits.pimm connect slots_12.io.in_uop.bits.imm_sel, issue_slots[12].in_uop.bits.imm_sel connect slots_12.io.in_uop.bits.imm_rename, issue_slots[12].in_uop.bits.imm_rename connect slots_12.io.in_uop.bits.taken, issue_slots[12].in_uop.bits.taken connect slots_12.io.in_uop.bits.pc_lob, issue_slots[12].in_uop.bits.pc_lob connect slots_12.io.in_uop.bits.edge_inst, issue_slots[12].in_uop.bits.edge_inst connect slots_12.io.in_uop.bits.ftq_idx, issue_slots[12].in_uop.bits.ftq_idx connect slots_12.io.in_uop.bits.is_mov, issue_slots[12].in_uop.bits.is_mov connect slots_12.io.in_uop.bits.is_rocc, issue_slots[12].in_uop.bits.is_rocc connect slots_12.io.in_uop.bits.is_sys_pc2epc, issue_slots[12].in_uop.bits.is_sys_pc2epc connect slots_12.io.in_uop.bits.is_eret, issue_slots[12].in_uop.bits.is_eret connect slots_12.io.in_uop.bits.is_amo, issue_slots[12].in_uop.bits.is_amo connect slots_12.io.in_uop.bits.is_sfence, issue_slots[12].in_uop.bits.is_sfence connect slots_12.io.in_uop.bits.is_fencei, issue_slots[12].in_uop.bits.is_fencei connect slots_12.io.in_uop.bits.is_fence, issue_slots[12].in_uop.bits.is_fence connect slots_12.io.in_uop.bits.is_sfb, issue_slots[12].in_uop.bits.is_sfb connect slots_12.io.in_uop.bits.br_type, issue_slots[12].in_uop.bits.br_type connect slots_12.io.in_uop.bits.br_tag, issue_slots[12].in_uop.bits.br_tag connect slots_12.io.in_uop.bits.br_mask, issue_slots[12].in_uop.bits.br_mask connect slots_12.io.in_uop.bits.dis_col_sel, issue_slots[12].in_uop.bits.dis_col_sel connect slots_12.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[12].in_uop.bits.iw_p3_bypass_hint connect slots_12.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[12].in_uop.bits.iw_p2_bypass_hint connect slots_12.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[12].in_uop.bits.iw_p1_bypass_hint connect slots_12.io.in_uop.bits.iw_p2_speculative_child, issue_slots[12].in_uop.bits.iw_p2_speculative_child connect slots_12.io.in_uop.bits.iw_p1_speculative_child, issue_slots[12].in_uop.bits.iw_p1_speculative_child connect slots_12.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[12].in_uop.bits.iw_issued_partial_dgen connect slots_12.io.in_uop.bits.iw_issued_partial_agen, issue_slots[12].in_uop.bits.iw_issued_partial_agen connect slots_12.io.in_uop.bits.iw_issued, issue_slots[12].in_uop.bits.iw_issued connect slots_12.io.in_uop.bits.fu_code[0], issue_slots[12].in_uop.bits.fu_code[0] connect slots_12.io.in_uop.bits.fu_code[1], issue_slots[12].in_uop.bits.fu_code[1] connect slots_12.io.in_uop.bits.fu_code[2], issue_slots[12].in_uop.bits.fu_code[2] connect slots_12.io.in_uop.bits.fu_code[3], issue_slots[12].in_uop.bits.fu_code[3] connect slots_12.io.in_uop.bits.fu_code[4], issue_slots[12].in_uop.bits.fu_code[4] connect slots_12.io.in_uop.bits.fu_code[5], issue_slots[12].in_uop.bits.fu_code[5] connect slots_12.io.in_uop.bits.fu_code[6], issue_slots[12].in_uop.bits.fu_code[6] connect slots_12.io.in_uop.bits.fu_code[7], issue_slots[12].in_uop.bits.fu_code[7] connect slots_12.io.in_uop.bits.fu_code[8], issue_slots[12].in_uop.bits.fu_code[8] connect slots_12.io.in_uop.bits.fu_code[9], issue_slots[12].in_uop.bits.fu_code[9] connect slots_12.io.in_uop.bits.iq_type[0], issue_slots[12].in_uop.bits.iq_type[0] connect slots_12.io.in_uop.bits.iq_type[1], issue_slots[12].in_uop.bits.iq_type[1] connect slots_12.io.in_uop.bits.iq_type[2], issue_slots[12].in_uop.bits.iq_type[2] connect slots_12.io.in_uop.bits.iq_type[3], issue_slots[12].in_uop.bits.iq_type[3] connect slots_12.io.in_uop.bits.debug_pc, issue_slots[12].in_uop.bits.debug_pc connect slots_12.io.in_uop.bits.is_rvc, issue_slots[12].in_uop.bits.is_rvc connect slots_12.io.in_uop.bits.debug_inst, issue_slots[12].in_uop.bits.debug_inst connect slots_12.io.in_uop.bits.inst, issue_slots[12].in_uop.bits.inst connect slots_12.io.in_uop.valid, issue_slots[12].in_uop.valid connect issue_slots[12].iss_uop.debug_tsrc, slots_12.io.iss_uop.debug_tsrc connect issue_slots[12].iss_uop.debug_fsrc, slots_12.io.iss_uop.debug_fsrc connect issue_slots[12].iss_uop.bp_xcpt_if, slots_12.io.iss_uop.bp_xcpt_if connect issue_slots[12].iss_uop.bp_debug_if, slots_12.io.iss_uop.bp_debug_if connect issue_slots[12].iss_uop.xcpt_ma_if, slots_12.io.iss_uop.xcpt_ma_if connect issue_slots[12].iss_uop.xcpt_ae_if, slots_12.io.iss_uop.xcpt_ae_if connect issue_slots[12].iss_uop.xcpt_pf_if, slots_12.io.iss_uop.xcpt_pf_if connect issue_slots[12].iss_uop.fp_typ, slots_12.io.iss_uop.fp_typ connect issue_slots[12].iss_uop.fp_rm, slots_12.io.iss_uop.fp_rm connect issue_slots[12].iss_uop.fp_val, slots_12.io.iss_uop.fp_val connect issue_slots[12].iss_uop.fcn_op, slots_12.io.iss_uop.fcn_op connect issue_slots[12].iss_uop.fcn_dw, slots_12.io.iss_uop.fcn_dw connect issue_slots[12].iss_uop.frs3_en, slots_12.io.iss_uop.frs3_en connect issue_slots[12].iss_uop.lrs2_rtype, slots_12.io.iss_uop.lrs2_rtype connect issue_slots[12].iss_uop.lrs1_rtype, slots_12.io.iss_uop.lrs1_rtype connect issue_slots[12].iss_uop.dst_rtype, slots_12.io.iss_uop.dst_rtype connect issue_slots[12].iss_uop.lrs3, slots_12.io.iss_uop.lrs3 connect issue_slots[12].iss_uop.lrs2, slots_12.io.iss_uop.lrs2 connect issue_slots[12].iss_uop.lrs1, slots_12.io.iss_uop.lrs1 connect issue_slots[12].iss_uop.ldst, slots_12.io.iss_uop.ldst connect issue_slots[12].iss_uop.ldst_is_rs1, slots_12.io.iss_uop.ldst_is_rs1 connect issue_slots[12].iss_uop.csr_cmd, slots_12.io.iss_uop.csr_cmd connect issue_slots[12].iss_uop.flush_on_commit, slots_12.io.iss_uop.flush_on_commit connect issue_slots[12].iss_uop.is_unique, slots_12.io.iss_uop.is_unique connect issue_slots[12].iss_uop.uses_stq, slots_12.io.iss_uop.uses_stq connect issue_slots[12].iss_uop.uses_ldq, slots_12.io.iss_uop.uses_ldq connect issue_slots[12].iss_uop.mem_signed, slots_12.io.iss_uop.mem_signed connect issue_slots[12].iss_uop.mem_size, slots_12.io.iss_uop.mem_size connect issue_slots[12].iss_uop.mem_cmd, slots_12.io.iss_uop.mem_cmd connect issue_slots[12].iss_uop.exc_cause, slots_12.io.iss_uop.exc_cause connect issue_slots[12].iss_uop.exception, slots_12.io.iss_uop.exception connect issue_slots[12].iss_uop.stale_pdst, slots_12.io.iss_uop.stale_pdst connect issue_slots[12].iss_uop.ppred_busy, slots_12.io.iss_uop.ppred_busy connect issue_slots[12].iss_uop.prs3_busy, slots_12.io.iss_uop.prs3_busy connect issue_slots[12].iss_uop.prs2_busy, slots_12.io.iss_uop.prs2_busy connect issue_slots[12].iss_uop.prs1_busy, slots_12.io.iss_uop.prs1_busy connect issue_slots[12].iss_uop.ppred, slots_12.io.iss_uop.ppred connect issue_slots[12].iss_uop.prs3, slots_12.io.iss_uop.prs3 connect issue_slots[12].iss_uop.prs2, slots_12.io.iss_uop.prs2 connect issue_slots[12].iss_uop.prs1, slots_12.io.iss_uop.prs1 connect issue_slots[12].iss_uop.pdst, slots_12.io.iss_uop.pdst connect issue_slots[12].iss_uop.rxq_idx, slots_12.io.iss_uop.rxq_idx connect issue_slots[12].iss_uop.stq_idx, slots_12.io.iss_uop.stq_idx connect issue_slots[12].iss_uop.ldq_idx, slots_12.io.iss_uop.ldq_idx connect issue_slots[12].iss_uop.rob_idx, slots_12.io.iss_uop.rob_idx connect issue_slots[12].iss_uop.fp_ctrl.vec, slots_12.io.iss_uop.fp_ctrl.vec connect issue_slots[12].iss_uop.fp_ctrl.wflags, slots_12.io.iss_uop.fp_ctrl.wflags connect issue_slots[12].iss_uop.fp_ctrl.sqrt, slots_12.io.iss_uop.fp_ctrl.sqrt connect issue_slots[12].iss_uop.fp_ctrl.div, slots_12.io.iss_uop.fp_ctrl.div connect issue_slots[12].iss_uop.fp_ctrl.fma, slots_12.io.iss_uop.fp_ctrl.fma connect issue_slots[12].iss_uop.fp_ctrl.fastpipe, slots_12.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[12].iss_uop.fp_ctrl.toint, slots_12.io.iss_uop.fp_ctrl.toint connect issue_slots[12].iss_uop.fp_ctrl.fromint, slots_12.io.iss_uop.fp_ctrl.fromint connect issue_slots[12].iss_uop.fp_ctrl.typeTagOut, slots_12.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[12].iss_uop.fp_ctrl.typeTagIn, slots_12.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[12].iss_uop.fp_ctrl.swap23, slots_12.io.iss_uop.fp_ctrl.swap23 connect issue_slots[12].iss_uop.fp_ctrl.swap12, slots_12.io.iss_uop.fp_ctrl.swap12 connect issue_slots[12].iss_uop.fp_ctrl.ren3, slots_12.io.iss_uop.fp_ctrl.ren3 connect issue_slots[12].iss_uop.fp_ctrl.ren2, slots_12.io.iss_uop.fp_ctrl.ren2 connect issue_slots[12].iss_uop.fp_ctrl.ren1, slots_12.io.iss_uop.fp_ctrl.ren1 connect issue_slots[12].iss_uop.fp_ctrl.wen, slots_12.io.iss_uop.fp_ctrl.wen connect issue_slots[12].iss_uop.fp_ctrl.ldst, slots_12.io.iss_uop.fp_ctrl.ldst connect issue_slots[12].iss_uop.op2_sel, slots_12.io.iss_uop.op2_sel connect issue_slots[12].iss_uop.op1_sel, slots_12.io.iss_uop.op1_sel connect issue_slots[12].iss_uop.imm_packed, slots_12.io.iss_uop.imm_packed connect issue_slots[12].iss_uop.pimm, slots_12.io.iss_uop.pimm connect issue_slots[12].iss_uop.imm_sel, slots_12.io.iss_uop.imm_sel connect issue_slots[12].iss_uop.imm_rename, slots_12.io.iss_uop.imm_rename connect issue_slots[12].iss_uop.taken, slots_12.io.iss_uop.taken connect issue_slots[12].iss_uop.pc_lob, slots_12.io.iss_uop.pc_lob connect issue_slots[12].iss_uop.edge_inst, slots_12.io.iss_uop.edge_inst connect issue_slots[12].iss_uop.ftq_idx, slots_12.io.iss_uop.ftq_idx connect issue_slots[12].iss_uop.is_mov, slots_12.io.iss_uop.is_mov connect issue_slots[12].iss_uop.is_rocc, slots_12.io.iss_uop.is_rocc connect issue_slots[12].iss_uop.is_sys_pc2epc, slots_12.io.iss_uop.is_sys_pc2epc connect issue_slots[12].iss_uop.is_eret, slots_12.io.iss_uop.is_eret connect issue_slots[12].iss_uop.is_amo, slots_12.io.iss_uop.is_amo connect issue_slots[12].iss_uop.is_sfence, slots_12.io.iss_uop.is_sfence connect issue_slots[12].iss_uop.is_fencei, slots_12.io.iss_uop.is_fencei connect issue_slots[12].iss_uop.is_fence, slots_12.io.iss_uop.is_fence connect issue_slots[12].iss_uop.is_sfb, slots_12.io.iss_uop.is_sfb connect issue_slots[12].iss_uop.br_type, slots_12.io.iss_uop.br_type connect issue_slots[12].iss_uop.br_tag, slots_12.io.iss_uop.br_tag connect issue_slots[12].iss_uop.br_mask, slots_12.io.iss_uop.br_mask connect issue_slots[12].iss_uop.dis_col_sel, slots_12.io.iss_uop.dis_col_sel connect issue_slots[12].iss_uop.iw_p3_bypass_hint, slots_12.io.iss_uop.iw_p3_bypass_hint connect issue_slots[12].iss_uop.iw_p2_bypass_hint, slots_12.io.iss_uop.iw_p2_bypass_hint connect issue_slots[12].iss_uop.iw_p1_bypass_hint, slots_12.io.iss_uop.iw_p1_bypass_hint connect issue_slots[12].iss_uop.iw_p2_speculative_child, slots_12.io.iss_uop.iw_p2_speculative_child connect issue_slots[12].iss_uop.iw_p1_speculative_child, slots_12.io.iss_uop.iw_p1_speculative_child connect issue_slots[12].iss_uop.iw_issued_partial_dgen, slots_12.io.iss_uop.iw_issued_partial_dgen connect issue_slots[12].iss_uop.iw_issued_partial_agen, slots_12.io.iss_uop.iw_issued_partial_agen connect issue_slots[12].iss_uop.iw_issued, slots_12.io.iss_uop.iw_issued connect issue_slots[12].iss_uop.fu_code[0], slots_12.io.iss_uop.fu_code[0] connect issue_slots[12].iss_uop.fu_code[1], slots_12.io.iss_uop.fu_code[1] connect issue_slots[12].iss_uop.fu_code[2], slots_12.io.iss_uop.fu_code[2] connect issue_slots[12].iss_uop.fu_code[3], slots_12.io.iss_uop.fu_code[3] connect issue_slots[12].iss_uop.fu_code[4], slots_12.io.iss_uop.fu_code[4] connect issue_slots[12].iss_uop.fu_code[5], slots_12.io.iss_uop.fu_code[5] connect issue_slots[12].iss_uop.fu_code[6], slots_12.io.iss_uop.fu_code[6] connect issue_slots[12].iss_uop.fu_code[7], slots_12.io.iss_uop.fu_code[7] connect issue_slots[12].iss_uop.fu_code[8], slots_12.io.iss_uop.fu_code[8] connect issue_slots[12].iss_uop.fu_code[9], slots_12.io.iss_uop.fu_code[9] connect issue_slots[12].iss_uop.iq_type[0], slots_12.io.iss_uop.iq_type[0] connect issue_slots[12].iss_uop.iq_type[1], slots_12.io.iss_uop.iq_type[1] connect issue_slots[12].iss_uop.iq_type[2], slots_12.io.iss_uop.iq_type[2] connect issue_slots[12].iss_uop.iq_type[3], slots_12.io.iss_uop.iq_type[3] connect issue_slots[12].iss_uop.debug_pc, slots_12.io.iss_uop.debug_pc connect issue_slots[12].iss_uop.is_rvc, slots_12.io.iss_uop.is_rvc connect issue_slots[12].iss_uop.debug_inst, slots_12.io.iss_uop.debug_inst connect issue_slots[12].iss_uop.inst, slots_12.io.iss_uop.inst connect slots_12.io.grant, issue_slots[12].grant connect issue_slots[12].request, slots_12.io.request connect issue_slots[12].will_be_valid, slots_12.io.will_be_valid connect issue_slots[12].valid, slots_12.io.valid connect slots_13.io.child_rebusys, issue_slots[13].child_rebusys connect slots_13.io.pred_wakeup_port.bits, issue_slots[13].pred_wakeup_port.bits connect slots_13.io.pred_wakeup_port.valid, issue_slots[13].pred_wakeup_port.valid connect slots_13.io.wakeup_ports[0].bits.rebusy, issue_slots[13].wakeup_ports[0].bits.rebusy connect slots_13.io.wakeup_ports[0].bits.speculative_mask, issue_slots[13].wakeup_ports[0].bits.speculative_mask connect slots_13.io.wakeup_ports[0].bits.bypassable, issue_slots[13].wakeup_ports[0].bits.bypassable connect slots_13.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[0].bits.uop.debug_tsrc connect slots_13.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[0].bits.uop.debug_fsrc connect slots_13.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_13.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[0].bits.uop.bp_debug_if connect slots_13.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_13.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_13.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_13.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[13].wakeup_ports[0].bits.uop.fp_typ connect slots_13.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[13].wakeup_ports[0].bits.uop.fp_rm connect slots_13.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[13].wakeup_ports[0].bits.uop.fp_val connect slots_13.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[13].wakeup_ports[0].bits.uop.fcn_op connect slots_13.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[0].bits.uop.fcn_dw connect slots_13.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[13].wakeup_ports[0].bits.uop.frs3_en connect slots_13.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_13.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_13.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[0].bits.uop.dst_rtype connect slots_13.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[13].wakeup_ports[0].bits.uop.lrs3 connect slots_13.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[13].wakeup_ports[0].bits.uop.lrs2 connect slots_13.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[13].wakeup_ports[0].bits.uop.lrs1 connect slots_13.io.wakeup_ports[0].bits.uop.ldst, issue_slots[13].wakeup_ports[0].bits.uop.ldst connect slots_13.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_13.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[0].bits.uop.csr_cmd connect slots_13.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[0].bits.uop.flush_on_commit connect slots_13.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[13].wakeup_ports[0].bits.uop.is_unique connect slots_13.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[13].wakeup_ports[0].bits.uop.uses_stq connect slots_13.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[0].bits.uop.uses_ldq connect slots_13.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[13].wakeup_ports[0].bits.uop.mem_signed connect slots_13.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[13].wakeup_ports[0].bits.uop.mem_size connect slots_13.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[0].bits.uop.mem_cmd connect slots_13.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[13].wakeup_ports[0].bits.uop.exc_cause connect slots_13.io.wakeup_ports[0].bits.uop.exception, issue_slots[13].wakeup_ports[0].bits.uop.exception connect slots_13.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[0].bits.uop.stale_pdst connect slots_13.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[0].bits.uop.ppred_busy connect slots_13.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[0].bits.uop.prs3_busy connect slots_13.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[0].bits.uop.prs2_busy connect slots_13.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[0].bits.uop.prs1_busy connect slots_13.io.wakeup_ports[0].bits.uop.ppred, issue_slots[13].wakeup_ports[0].bits.uop.ppred connect slots_13.io.wakeup_ports[0].bits.uop.prs3, issue_slots[13].wakeup_ports[0].bits.uop.prs3 connect slots_13.io.wakeup_ports[0].bits.uop.prs2, issue_slots[13].wakeup_ports[0].bits.uop.prs2 connect slots_13.io.wakeup_ports[0].bits.uop.prs1, issue_slots[13].wakeup_ports[0].bits.uop.prs1 connect slots_13.io.wakeup_ports[0].bits.uop.pdst, issue_slots[13].wakeup_ports[0].bits.uop.pdst connect slots_13.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[0].bits.uop.rxq_idx connect slots_13.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[13].wakeup_ports[0].bits.uop.stq_idx connect slots_13.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[0].bits.uop.ldq_idx connect slots_13.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[13].wakeup_ports[0].bits.uop.rob_idx connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_13.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[13].wakeup_ports[0].bits.uop.op2_sel connect slots_13.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[13].wakeup_ports[0].bits.uop.op1_sel connect slots_13.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[13].wakeup_ports[0].bits.uop.imm_packed connect slots_13.io.wakeup_ports[0].bits.uop.pimm, issue_slots[13].wakeup_ports[0].bits.uop.pimm connect slots_13.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[13].wakeup_ports[0].bits.uop.imm_sel connect slots_13.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[13].wakeup_ports[0].bits.uop.imm_rename connect slots_13.io.wakeup_ports[0].bits.uop.taken, issue_slots[13].wakeup_ports[0].bits.uop.taken connect slots_13.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[13].wakeup_ports[0].bits.uop.pc_lob connect slots_13.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[13].wakeup_ports[0].bits.uop.edge_inst connect slots_13.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[0].bits.uop.ftq_idx connect slots_13.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[13].wakeup_ports[0].bits.uop.is_mov connect slots_13.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[13].wakeup_ports[0].bits.uop.is_rocc connect slots_13.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_13.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[13].wakeup_ports[0].bits.uop.is_eret connect slots_13.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[13].wakeup_ports[0].bits.uop.is_amo connect slots_13.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[13].wakeup_ports[0].bits.uop.is_sfence connect slots_13.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[13].wakeup_ports[0].bits.uop.is_fencei connect slots_13.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[13].wakeup_ports[0].bits.uop.is_fence connect slots_13.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[13].wakeup_ports[0].bits.uop.is_sfb connect slots_13.io.wakeup_ports[0].bits.uop.br_type, issue_slots[13].wakeup_ports[0].bits.uop.br_type connect slots_13.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[13].wakeup_ports[0].bits.uop.br_tag connect slots_13.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[13].wakeup_ports[0].bits.uop.br_mask connect slots_13.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[0].bits.uop.dis_col_sel connect slots_13.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_13.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_13.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_13.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_13.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_13.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_13.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_13.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[13].wakeup_ports[0].bits.uop.iw_issued connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[0] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[1] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[2] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[3] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[4] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[5] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[6] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[7] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[8] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[9] connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[0] connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[1] connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[2] connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[3] connect slots_13.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[13].wakeup_ports[0].bits.uop.debug_pc connect slots_13.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[13].wakeup_ports[0].bits.uop.is_rvc connect slots_13.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[13].wakeup_ports[0].bits.uop.debug_inst connect slots_13.io.wakeup_ports[0].bits.uop.inst, issue_slots[13].wakeup_ports[0].bits.uop.inst connect slots_13.io.wakeup_ports[0].valid, issue_slots[13].wakeup_ports[0].valid connect slots_13.io.wakeup_ports[1].bits.rebusy, issue_slots[13].wakeup_ports[1].bits.rebusy connect slots_13.io.wakeup_ports[1].bits.speculative_mask, issue_slots[13].wakeup_ports[1].bits.speculative_mask connect slots_13.io.wakeup_ports[1].bits.bypassable, issue_slots[13].wakeup_ports[1].bits.bypassable connect slots_13.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[1].bits.uop.debug_tsrc connect slots_13.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[1].bits.uop.debug_fsrc connect slots_13.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_13.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[1].bits.uop.bp_debug_if connect slots_13.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_13.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_13.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_13.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[13].wakeup_ports[1].bits.uop.fp_typ connect slots_13.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[13].wakeup_ports[1].bits.uop.fp_rm connect slots_13.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[13].wakeup_ports[1].bits.uop.fp_val connect slots_13.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[13].wakeup_ports[1].bits.uop.fcn_op connect slots_13.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[1].bits.uop.fcn_dw connect slots_13.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[13].wakeup_ports[1].bits.uop.frs3_en connect slots_13.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_13.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_13.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[1].bits.uop.dst_rtype connect slots_13.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[13].wakeup_ports[1].bits.uop.lrs3 connect slots_13.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[13].wakeup_ports[1].bits.uop.lrs2 connect slots_13.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[13].wakeup_ports[1].bits.uop.lrs1 connect slots_13.io.wakeup_ports[1].bits.uop.ldst, issue_slots[13].wakeup_ports[1].bits.uop.ldst connect slots_13.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_13.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[1].bits.uop.csr_cmd connect slots_13.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[1].bits.uop.flush_on_commit connect slots_13.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[13].wakeup_ports[1].bits.uop.is_unique connect slots_13.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[13].wakeup_ports[1].bits.uop.uses_stq connect slots_13.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[1].bits.uop.uses_ldq connect slots_13.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[13].wakeup_ports[1].bits.uop.mem_signed connect slots_13.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[13].wakeup_ports[1].bits.uop.mem_size connect slots_13.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[1].bits.uop.mem_cmd connect slots_13.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[13].wakeup_ports[1].bits.uop.exc_cause connect slots_13.io.wakeup_ports[1].bits.uop.exception, issue_slots[13].wakeup_ports[1].bits.uop.exception connect slots_13.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[1].bits.uop.stale_pdst connect slots_13.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[1].bits.uop.ppred_busy connect slots_13.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[1].bits.uop.prs3_busy connect slots_13.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[1].bits.uop.prs2_busy connect slots_13.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[1].bits.uop.prs1_busy connect slots_13.io.wakeup_ports[1].bits.uop.ppred, issue_slots[13].wakeup_ports[1].bits.uop.ppred connect slots_13.io.wakeup_ports[1].bits.uop.prs3, issue_slots[13].wakeup_ports[1].bits.uop.prs3 connect slots_13.io.wakeup_ports[1].bits.uop.prs2, issue_slots[13].wakeup_ports[1].bits.uop.prs2 connect slots_13.io.wakeup_ports[1].bits.uop.prs1, issue_slots[13].wakeup_ports[1].bits.uop.prs1 connect slots_13.io.wakeup_ports[1].bits.uop.pdst, issue_slots[13].wakeup_ports[1].bits.uop.pdst connect slots_13.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[1].bits.uop.rxq_idx connect slots_13.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[13].wakeup_ports[1].bits.uop.stq_idx connect slots_13.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[1].bits.uop.ldq_idx connect slots_13.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[13].wakeup_ports[1].bits.uop.rob_idx connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_13.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[13].wakeup_ports[1].bits.uop.op2_sel connect slots_13.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[13].wakeup_ports[1].bits.uop.op1_sel connect slots_13.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[13].wakeup_ports[1].bits.uop.imm_packed connect slots_13.io.wakeup_ports[1].bits.uop.pimm, issue_slots[13].wakeup_ports[1].bits.uop.pimm connect slots_13.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[13].wakeup_ports[1].bits.uop.imm_sel connect slots_13.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[13].wakeup_ports[1].bits.uop.imm_rename connect slots_13.io.wakeup_ports[1].bits.uop.taken, issue_slots[13].wakeup_ports[1].bits.uop.taken connect slots_13.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[13].wakeup_ports[1].bits.uop.pc_lob connect slots_13.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[13].wakeup_ports[1].bits.uop.edge_inst connect slots_13.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[1].bits.uop.ftq_idx connect slots_13.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[13].wakeup_ports[1].bits.uop.is_mov connect slots_13.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[13].wakeup_ports[1].bits.uop.is_rocc connect slots_13.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_13.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[13].wakeup_ports[1].bits.uop.is_eret connect slots_13.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[13].wakeup_ports[1].bits.uop.is_amo connect slots_13.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[13].wakeup_ports[1].bits.uop.is_sfence connect slots_13.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[13].wakeup_ports[1].bits.uop.is_fencei connect slots_13.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[13].wakeup_ports[1].bits.uop.is_fence connect slots_13.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[13].wakeup_ports[1].bits.uop.is_sfb connect slots_13.io.wakeup_ports[1].bits.uop.br_type, issue_slots[13].wakeup_ports[1].bits.uop.br_type connect slots_13.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[13].wakeup_ports[1].bits.uop.br_tag connect slots_13.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[13].wakeup_ports[1].bits.uop.br_mask connect slots_13.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[1].bits.uop.dis_col_sel connect slots_13.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_13.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_13.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_13.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_13.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_13.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_13.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_13.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[13].wakeup_ports[1].bits.uop.iw_issued connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[0] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[1] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[2] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[3] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[4] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[5] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[6] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[7] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[8] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[9] connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[0] connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[1] connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[2] connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[3] connect slots_13.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[13].wakeup_ports[1].bits.uop.debug_pc connect slots_13.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[13].wakeup_ports[1].bits.uop.is_rvc connect slots_13.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[13].wakeup_ports[1].bits.uop.debug_inst connect slots_13.io.wakeup_ports[1].bits.uop.inst, issue_slots[13].wakeup_ports[1].bits.uop.inst connect slots_13.io.wakeup_ports[1].valid, issue_slots[13].wakeup_ports[1].valid connect slots_13.io.wakeup_ports[2].bits.rebusy, issue_slots[13].wakeup_ports[2].bits.rebusy connect slots_13.io.wakeup_ports[2].bits.speculative_mask, issue_slots[13].wakeup_ports[2].bits.speculative_mask connect slots_13.io.wakeup_ports[2].bits.bypassable, issue_slots[13].wakeup_ports[2].bits.bypassable connect slots_13.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[2].bits.uop.debug_tsrc connect slots_13.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[2].bits.uop.debug_fsrc connect slots_13.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_13.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[2].bits.uop.bp_debug_if connect slots_13.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_13.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_13.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_13.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[13].wakeup_ports[2].bits.uop.fp_typ connect slots_13.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[13].wakeup_ports[2].bits.uop.fp_rm connect slots_13.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[13].wakeup_ports[2].bits.uop.fp_val connect slots_13.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[13].wakeup_ports[2].bits.uop.fcn_op connect slots_13.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[2].bits.uop.fcn_dw connect slots_13.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[13].wakeup_ports[2].bits.uop.frs3_en connect slots_13.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_13.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_13.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[2].bits.uop.dst_rtype connect slots_13.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[13].wakeup_ports[2].bits.uop.lrs3 connect slots_13.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[13].wakeup_ports[2].bits.uop.lrs2 connect slots_13.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[13].wakeup_ports[2].bits.uop.lrs1 connect slots_13.io.wakeup_ports[2].bits.uop.ldst, issue_slots[13].wakeup_ports[2].bits.uop.ldst connect slots_13.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_13.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[2].bits.uop.csr_cmd connect slots_13.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[2].bits.uop.flush_on_commit connect slots_13.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[13].wakeup_ports[2].bits.uop.is_unique connect slots_13.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[13].wakeup_ports[2].bits.uop.uses_stq connect slots_13.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[2].bits.uop.uses_ldq connect slots_13.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[13].wakeup_ports[2].bits.uop.mem_signed connect slots_13.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[13].wakeup_ports[2].bits.uop.mem_size connect slots_13.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[2].bits.uop.mem_cmd connect slots_13.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[13].wakeup_ports[2].bits.uop.exc_cause connect slots_13.io.wakeup_ports[2].bits.uop.exception, issue_slots[13].wakeup_ports[2].bits.uop.exception connect slots_13.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[2].bits.uop.stale_pdst connect slots_13.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[2].bits.uop.ppred_busy connect slots_13.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[2].bits.uop.prs3_busy connect slots_13.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[2].bits.uop.prs2_busy connect slots_13.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[2].bits.uop.prs1_busy connect slots_13.io.wakeup_ports[2].bits.uop.ppred, issue_slots[13].wakeup_ports[2].bits.uop.ppred connect slots_13.io.wakeup_ports[2].bits.uop.prs3, issue_slots[13].wakeup_ports[2].bits.uop.prs3 connect slots_13.io.wakeup_ports[2].bits.uop.prs2, issue_slots[13].wakeup_ports[2].bits.uop.prs2 connect slots_13.io.wakeup_ports[2].bits.uop.prs1, issue_slots[13].wakeup_ports[2].bits.uop.prs1 connect slots_13.io.wakeup_ports[2].bits.uop.pdst, issue_slots[13].wakeup_ports[2].bits.uop.pdst connect slots_13.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[2].bits.uop.rxq_idx connect slots_13.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[13].wakeup_ports[2].bits.uop.stq_idx connect slots_13.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[2].bits.uop.ldq_idx connect slots_13.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[13].wakeup_ports[2].bits.uop.rob_idx connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_13.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[13].wakeup_ports[2].bits.uop.op2_sel connect slots_13.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[13].wakeup_ports[2].bits.uop.op1_sel connect slots_13.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[13].wakeup_ports[2].bits.uop.imm_packed connect slots_13.io.wakeup_ports[2].bits.uop.pimm, issue_slots[13].wakeup_ports[2].bits.uop.pimm connect slots_13.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[13].wakeup_ports[2].bits.uop.imm_sel connect slots_13.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[13].wakeup_ports[2].bits.uop.imm_rename connect slots_13.io.wakeup_ports[2].bits.uop.taken, issue_slots[13].wakeup_ports[2].bits.uop.taken connect slots_13.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[13].wakeup_ports[2].bits.uop.pc_lob connect slots_13.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[13].wakeup_ports[2].bits.uop.edge_inst connect slots_13.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[2].bits.uop.ftq_idx connect slots_13.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[13].wakeup_ports[2].bits.uop.is_mov connect slots_13.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[13].wakeup_ports[2].bits.uop.is_rocc connect slots_13.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_13.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[13].wakeup_ports[2].bits.uop.is_eret connect slots_13.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[13].wakeup_ports[2].bits.uop.is_amo connect slots_13.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[13].wakeup_ports[2].bits.uop.is_sfence connect slots_13.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[13].wakeup_ports[2].bits.uop.is_fencei connect slots_13.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[13].wakeup_ports[2].bits.uop.is_fence connect slots_13.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[13].wakeup_ports[2].bits.uop.is_sfb connect slots_13.io.wakeup_ports[2].bits.uop.br_type, issue_slots[13].wakeup_ports[2].bits.uop.br_type connect slots_13.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[13].wakeup_ports[2].bits.uop.br_tag connect slots_13.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[13].wakeup_ports[2].bits.uop.br_mask connect slots_13.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[2].bits.uop.dis_col_sel connect slots_13.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_13.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_13.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_13.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_13.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_13.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_13.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_13.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[13].wakeup_ports[2].bits.uop.iw_issued connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[0] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[1] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[2] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[3] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[4] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[5] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[6] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[7] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[8] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[9] connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[0] connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[1] connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[2] connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[3] connect slots_13.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[13].wakeup_ports[2].bits.uop.debug_pc connect slots_13.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[13].wakeup_ports[2].bits.uop.is_rvc connect slots_13.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[13].wakeup_ports[2].bits.uop.debug_inst connect slots_13.io.wakeup_ports[2].bits.uop.inst, issue_slots[13].wakeup_ports[2].bits.uop.inst connect slots_13.io.wakeup_ports[2].valid, issue_slots[13].wakeup_ports[2].valid connect slots_13.io.wakeup_ports[3].bits.rebusy, issue_slots[13].wakeup_ports[3].bits.rebusy connect slots_13.io.wakeup_ports[3].bits.speculative_mask, issue_slots[13].wakeup_ports[3].bits.speculative_mask connect slots_13.io.wakeup_ports[3].bits.bypassable, issue_slots[13].wakeup_ports[3].bits.bypassable connect slots_13.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[3].bits.uop.debug_tsrc connect slots_13.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[3].bits.uop.debug_fsrc connect slots_13.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_13.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[3].bits.uop.bp_debug_if connect slots_13.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_13.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_13.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_13.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[13].wakeup_ports[3].bits.uop.fp_typ connect slots_13.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[13].wakeup_ports[3].bits.uop.fp_rm connect slots_13.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[13].wakeup_ports[3].bits.uop.fp_val connect slots_13.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[13].wakeup_ports[3].bits.uop.fcn_op connect slots_13.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[3].bits.uop.fcn_dw connect slots_13.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[13].wakeup_ports[3].bits.uop.frs3_en connect slots_13.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_13.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_13.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[3].bits.uop.dst_rtype connect slots_13.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[13].wakeup_ports[3].bits.uop.lrs3 connect slots_13.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[13].wakeup_ports[3].bits.uop.lrs2 connect slots_13.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[13].wakeup_ports[3].bits.uop.lrs1 connect slots_13.io.wakeup_ports[3].bits.uop.ldst, issue_slots[13].wakeup_ports[3].bits.uop.ldst connect slots_13.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_13.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[3].bits.uop.csr_cmd connect slots_13.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[3].bits.uop.flush_on_commit connect slots_13.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[13].wakeup_ports[3].bits.uop.is_unique connect slots_13.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[13].wakeup_ports[3].bits.uop.uses_stq connect slots_13.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[3].bits.uop.uses_ldq connect slots_13.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[13].wakeup_ports[3].bits.uop.mem_signed connect slots_13.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[13].wakeup_ports[3].bits.uop.mem_size connect slots_13.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[3].bits.uop.mem_cmd connect slots_13.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[13].wakeup_ports[3].bits.uop.exc_cause connect slots_13.io.wakeup_ports[3].bits.uop.exception, issue_slots[13].wakeup_ports[3].bits.uop.exception connect slots_13.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[3].bits.uop.stale_pdst connect slots_13.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[3].bits.uop.ppred_busy connect slots_13.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[3].bits.uop.prs3_busy connect slots_13.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[3].bits.uop.prs2_busy connect slots_13.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[3].bits.uop.prs1_busy connect slots_13.io.wakeup_ports[3].bits.uop.ppred, issue_slots[13].wakeup_ports[3].bits.uop.ppred connect slots_13.io.wakeup_ports[3].bits.uop.prs3, issue_slots[13].wakeup_ports[3].bits.uop.prs3 connect slots_13.io.wakeup_ports[3].bits.uop.prs2, issue_slots[13].wakeup_ports[3].bits.uop.prs2 connect slots_13.io.wakeup_ports[3].bits.uop.prs1, issue_slots[13].wakeup_ports[3].bits.uop.prs1 connect slots_13.io.wakeup_ports[3].bits.uop.pdst, issue_slots[13].wakeup_ports[3].bits.uop.pdst connect slots_13.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[3].bits.uop.rxq_idx connect slots_13.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[13].wakeup_ports[3].bits.uop.stq_idx connect slots_13.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[3].bits.uop.ldq_idx connect slots_13.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[13].wakeup_ports[3].bits.uop.rob_idx connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_13.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[13].wakeup_ports[3].bits.uop.op2_sel connect slots_13.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[13].wakeup_ports[3].bits.uop.op1_sel connect slots_13.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[13].wakeup_ports[3].bits.uop.imm_packed connect slots_13.io.wakeup_ports[3].bits.uop.pimm, issue_slots[13].wakeup_ports[3].bits.uop.pimm connect slots_13.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[13].wakeup_ports[3].bits.uop.imm_sel connect slots_13.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[13].wakeup_ports[3].bits.uop.imm_rename connect slots_13.io.wakeup_ports[3].bits.uop.taken, issue_slots[13].wakeup_ports[3].bits.uop.taken connect slots_13.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[13].wakeup_ports[3].bits.uop.pc_lob connect slots_13.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[13].wakeup_ports[3].bits.uop.edge_inst connect slots_13.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[3].bits.uop.ftq_idx connect slots_13.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[13].wakeup_ports[3].bits.uop.is_mov connect slots_13.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[13].wakeup_ports[3].bits.uop.is_rocc connect slots_13.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_13.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[13].wakeup_ports[3].bits.uop.is_eret connect slots_13.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[13].wakeup_ports[3].bits.uop.is_amo connect slots_13.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[13].wakeup_ports[3].bits.uop.is_sfence connect slots_13.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[13].wakeup_ports[3].bits.uop.is_fencei connect slots_13.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[13].wakeup_ports[3].bits.uop.is_fence connect slots_13.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[13].wakeup_ports[3].bits.uop.is_sfb connect slots_13.io.wakeup_ports[3].bits.uop.br_type, issue_slots[13].wakeup_ports[3].bits.uop.br_type connect slots_13.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[13].wakeup_ports[3].bits.uop.br_tag connect slots_13.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[13].wakeup_ports[3].bits.uop.br_mask connect slots_13.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[3].bits.uop.dis_col_sel connect slots_13.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_13.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_13.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_13.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_13.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_13.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_13.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_13.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[13].wakeup_ports[3].bits.uop.iw_issued connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[0] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[1] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[2] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[3] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[4] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[5] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[6] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[7] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[8] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[9] connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[0] connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[1] connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[2] connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[3] connect slots_13.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[13].wakeup_ports[3].bits.uop.debug_pc connect slots_13.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[13].wakeup_ports[3].bits.uop.is_rvc connect slots_13.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[13].wakeup_ports[3].bits.uop.debug_inst connect slots_13.io.wakeup_ports[3].bits.uop.inst, issue_slots[13].wakeup_ports[3].bits.uop.inst connect slots_13.io.wakeup_ports[3].valid, issue_slots[13].wakeup_ports[3].valid connect slots_13.io.wakeup_ports[4].bits.rebusy, issue_slots[13].wakeup_ports[4].bits.rebusy connect slots_13.io.wakeup_ports[4].bits.speculative_mask, issue_slots[13].wakeup_ports[4].bits.speculative_mask connect slots_13.io.wakeup_ports[4].bits.bypassable, issue_slots[13].wakeup_ports[4].bits.bypassable connect slots_13.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[4].bits.uop.debug_tsrc connect slots_13.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[4].bits.uop.debug_fsrc connect slots_13.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_13.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[4].bits.uop.bp_debug_if connect slots_13.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_13.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_13.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_13.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[13].wakeup_ports[4].bits.uop.fp_typ connect slots_13.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[13].wakeup_ports[4].bits.uop.fp_rm connect slots_13.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[13].wakeup_ports[4].bits.uop.fp_val connect slots_13.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[13].wakeup_ports[4].bits.uop.fcn_op connect slots_13.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[4].bits.uop.fcn_dw connect slots_13.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[13].wakeup_ports[4].bits.uop.frs3_en connect slots_13.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_13.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_13.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[4].bits.uop.dst_rtype connect slots_13.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[13].wakeup_ports[4].bits.uop.lrs3 connect slots_13.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[13].wakeup_ports[4].bits.uop.lrs2 connect slots_13.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[13].wakeup_ports[4].bits.uop.lrs1 connect slots_13.io.wakeup_ports[4].bits.uop.ldst, issue_slots[13].wakeup_ports[4].bits.uop.ldst connect slots_13.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_13.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[4].bits.uop.csr_cmd connect slots_13.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[4].bits.uop.flush_on_commit connect slots_13.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[13].wakeup_ports[4].bits.uop.is_unique connect slots_13.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[13].wakeup_ports[4].bits.uop.uses_stq connect slots_13.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[4].bits.uop.uses_ldq connect slots_13.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[13].wakeup_ports[4].bits.uop.mem_signed connect slots_13.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[13].wakeup_ports[4].bits.uop.mem_size connect slots_13.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[4].bits.uop.mem_cmd connect slots_13.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[13].wakeup_ports[4].bits.uop.exc_cause connect slots_13.io.wakeup_ports[4].bits.uop.exception, issue_slots[13].wakeup_ports[4].bits.uop.exception connect slots_13.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[4].bits.uop.stale_pdst connect slots_13.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[4].bits.uop.ppred_busy connect slots_13.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[4].bits.uop.prs3_busy connect slots_13.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[4].bits.uop.prs2_busy connect slots_13.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[4].bits.uop.prs1_busy connect slots_13.io.wakeup_ports[4].bits.uop.ppred, issue_slots[13].wakeup_ports[4].bits.uop.ppred connect slots_13.io.wakeup_ports[4].bits.uop.prs3, issue_slots[13].wakeup_ports[4].bits.uop.prs3 connect slots_13.io.wakeup_ports[4].bits.uop.prs2, issue_slots[13].wakeup_ports[4].bits.uop.prs2 connect slots_13.io.wakeup_ports[4].bits.uop.prs1, issue_slots[13].wakeup_ports[4].bits.uop.prs1 connect slots_13.io.wakeup_ports[4].bits.uop.pdst, issue_slots[13].wakeup_ports[4].bits.uop.pdst connect slots_13.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[4].bits.uop.rxq_idx connect slots_13.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[13].wakeup_ports[4].bits.uop.stq_idx connect slots_13.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[4].bits.uop.ldq_idx connect slots_13.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[13].wakeup_ports[4].bits.uop.rob_idx connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_13.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[13].wakeup_ports[4].bits.uop.op2_sel connect slots_13.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[13].wakeup_ports[4].bits.uop.op1_sel connect slots_13.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[13].wakeup_ports[4].bits.uop.imm_packed connect slots_13.io.wakeup_ports[4].bits.uop.pimm, issue_slots[13].wakeup_ports[4].bits.uop.pimm connect slots_13.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[13].wakeup_ports[4].bits.uop.imm_sel connect slots_13.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[13].wakeup_ports[4].bits.uop.imm_rename connect slots_13.io.wakeup_ports[4].bits.uop.taken, issue_slots[13].wakeup_ports[4].bits.uop.taken connect slots_13.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[13].wakeup_ports[4].bits.uop.pc_lob connect slots_13.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[13].wakeup_ports[4].bits.uop.edge_inst connect slots_13.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[4].bits.uop.ftq_idx connect slots_13.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[13].wakeup_ports[4].bits.uop.is_mov connect slots_13.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[13].wakeup_ports[4].bits.uop.is_rocc connect slots_13.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_13.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[13].wakeup_ports[4].bits.uop.is_eret connect slots_13.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[13].wakeup_ports[4].bits.uop.is_amo connect slots_13.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[13].wakeup_ports[4].bits.uop.is_sfence connect slots_13.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[13].wakeup_ports[4].bits.uop.is_fencei connect slots_13.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[13].wakeup_ports[4].bits.uop.is_fence connect slots_13.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[13].wakeup_ports[4].bits.uop.is_sfb connect slots_13.io.wakeup_ports[4].bits.uop.br_type, issue_slots[13].wakeup_ports[4].bits.uop.br_type connect slots_13.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[13].wakeup_ports[4].bits.uop.br_tag connect slots_13.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[13].wakeup_ports[4].bits.uop.br_mask connect slots_13.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[4].bits.uop.dis_col_sel connect slots_13.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_13.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_13.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_13.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_13.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_13.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_13.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_13.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[13].wakeup_ports[4].bits.uop.iw_issued connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[0] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[1] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[2] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[3] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[4] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[5] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[6] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[7] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[8] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[9] connect slots_13.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[4].bits.uop.iq_type[0] connect slots_13.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[4].bits.uop.iq_type[1] connect slots_13.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[4].bits.uop.iq_type[2] connect slots_13.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[4].bits.uop.iq_type[3] connect slots_13.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[13].wakeup_ports[4].bits.uop.debug_pc connect slots_13.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[13].wakeup_ports[4].bits.uop.is_rvc connect slots_13.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[13].wakeup_ports[4].bits.uop.debug_inst connect slots_13.io.wakeup_ports[4].bits.uop.inst, issue_slots[13].wakeup_ports[4].bits.uop.inst connect slots_13.io.wakeup_ports[4].valid, issue_slots[13].wakeup_ports[4].valid connect slots_13.io.squash_grant, issue_slots[13].squash_grant connect slots_13.io.clear, issue_slots[13].clear connect slots_13.io.kill, issue_slots[13].kill connect slots_13.io.brupdate.b2.target_offset, issue_slots[13].brupdate.b2.target_offset connect slots_13.io.brupdate.b2.jalr_target, issue_slots[13].brupdate.b2.jalr_target connect slots_13.io.brupdate.b2.pc_sel, issue_slots[13].brupdate.b2.pc_sel connect slots_13.io.brupdate.b2.cfi_type, issue_slots[13].brupdate.b2.cfi_type connect slots_13.io.brupdate.b2.taken, issue_slots[13].brupdate.b2.taken connect slots_13.io.brupdate.b2.mispredict, issue_slots[13].brupdate.b2.mispredict connect slots_13.io.brupdate.b2.uop.debug_tsrc, issue_slots[13].brupdate.b2.uop.debug_tsrc connect slots_13.io.brupdate.b2.uop.debug_fsrc, issue_slots[13].brupdate.b2.uop.debug_fsrc connect slots_13.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[13].brupdate.b2.uop.bp_xcpt_if connect slots_13.io.brupdate.b2.uop.bp_debug_if, issue_slots[13].brupdate.b2.uop.bp_debug_if connect slots_13.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[13].brupdate.b2.uop.xcpt_ma_if connect slots_13.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[13].brupdate.b2.uop.xcpt_ae_if connect slots_13.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[13].brupdate.b2.uop.xcpt_pf_if connect slots_13.io.brupdate.b2.uop.fp_typ, issue_slots[13].brupdate.b2.uop.fp_typ connect slots_13.io.brupdate.b2.uop.fp_rm, issue_slots[13].brupdate.b2.uop.fp_rm connect slots_13.io.brupdate.b2.uop.fp_val, issue_slots[13].brupdate.b2.uop.fp_val connect slots_13.io.brupdate.b2.uop.fcn_op, issue_slots[13].brupdate.b2.uop.fcn_op connect slots_13.io.brupdate.b2.uop.fcn_dw, issue_slots[13].brupdate.b2.uop.fcn_dw connect slots_13.io.brupdate.b2.uop.frs3_en, issue_slots[13].brupdate.b2.uop.frs3_en connect slots_13.io.brupdate.b2.uop.lrs2_rtype, issue_slots[13].brupdate.b2.uop.lrs2_rtype connect slots_13.io.brupdate.b2.uop.lrs1_rtype, issue_slots[13].brupdate.b2.uop.lrs1_rtype connect slots_13.io.brupdate.b2.uop.dst_rtype, issue_slots[13].brupdate.b2.uop.dst_rtype connect slots_13.io.brupdate.b2.uop.lrs3, issue_slots[13].brupdate.b2.uop.lrs3 connect slots_13.io.brupdate.b2.uop.lrs2, issue_slots[13].brupdate.b2.uop.lrs2 connect slots_13.io.brupdate.b2.uop.lrs1, issue_slots[13].brupdate.b2.uop.lrs1 connect slots_13.io.brupdate.b2.uop.ldst, issue_slots[13].brupdate.b2.uop.ldst connect slots_13.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[13].brupdate.b2.uop.ldst_is_rs1 connect slots_13.io.brupdate.b2.uop.csr_cmd, issue_slots[13].brupdate.b2.uop.csr_cmd connect slots_13.io.brupdate.b2.uop.flush_on_commit, issue_slots[13].brupdate.b2.uop.flush_on_commit connect slots_13.io.brupdate.b2.uop.is_unique, issue_slots[13].brupdate.b2.uop.is_unique connect slots_13.io.brupdate.b2.uop.uses_stq, issue_slots[13].brupdate.b2.uop.uses_stq connect slots_13.io.brupdate.b2.uop.uses_ldq, issue_slots[13].brupdate.b2.uop.uses_ldq connect slots_13.io.brupdate.b2.uop.mem_signed, issue_slots[13].brupdate.b2.uop.mem_signed connect slots_13.io.brupdate.b2.uop.mem_size, issue_slots[13].brupdate.b2.uop.mem_size connect slots_13.io.brupdate.b2.uop.mem_cmd, issue_slots[13].brupdate.b2.uop.mem_cmd connect slots_13.io.brupdate.b2.uop.exc_cause, issue_slots[13].brupdate.b2.uop.exc_cause connect slots_13.io.brupdate.b2.uop.exception, issue_slots[13].brupdate.b2.uop.exception connect slots_13.io.brupdate.b2.uop.stale_pdst, issue_slots[13].brupdate.b2.uop.stale_pdst connect slots_13.io.brupdate.b2.uop.ppred_busy, issue_slots[13].brupdate.b2.uop.ppred_busy connect slots_13.io.brupdate.b2.uop.prs3_busy, issue_slots[13].brupdate.b2.uop.prs3_busy connect slots_13.io.brupdate.b2.uop.prs2_busy, issue_slots[13].brupdate.b2.uop.prs2_busy connect slots_13.io.brupdate.b2.uop.prs1_busy, issue_slots[13].brupdate.b2.uop.prs1_busy connect slots_13.io.brupdate.b2.uop.ppred, issue_slots[13].brupdate.b2.uop.ppred connect slots_13.io.brupdate.b2.uop.prs3, issue_slots[13].brupdate.b2.uop.prs3 connect slots_13.io.brupdate.b2.uop.prs2, issue_slots[13].brupdate.b2.uop.prs2 connect slots_13.io.brupdate.b2.uop.prs1, issue_slots[13].brupdate.b2.uop.prs1 connect slots_13.io.brupdate.b2.uop.pdst, issue_slots[13].brupdate.b2.uop.pdst connect slots_13.io.brupdate.b2.uop.rxq_idx, issue_slots[13].brupdate.b2.uop.rxq_idx connect slots_13.io.brupdate.b2.uop.stq_idx, issue_slots[13].brupdate.b2.uop.stq_idx connect slots_13.io.brupdate.b2.uop.ldq_idx, issue_slots[13].brupdate.b2.uop.ldq_idx connect slots_13.io.brupdate.b2.uop.rob_idx, issue_slots[13].brupdate.b2.uop.rob_idx connect slots_13.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[13].brupdate.b2.uop.fp_ctrl.vec connect slots_13.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[13].brupdate.b2.uop.fp_ctrl.wflags connect slots_13.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[13].brupdate.b2.uop.fp_ctrl.sqrt connect slots_13.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[13].brupdate.b2.uop.fp_ctrl.div connect slots_13.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[13].brupdate.b2.uop.fp_ctrl.fma connect slots_13.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[13].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_13.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[13].brupdate.b2.uop.fp_ctrl.toint connect slots_13.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[13].brupdate.b2.uop.fp_ctrl.fromint connect slots_13.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_13.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_13.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[13].brupdate.b2.uop.fp_ctrl.swap23 connect slots_13.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[13].brupdate.b2.uop.fp_ctrl.swap12 connect slots_13.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[13].brupdate.b2.uop.fp_ctrl.ren3 connect slots_13.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[13].brupdate.b2.uop.fp_ctrl.ren2 connect slots_13.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[13].brupdate.b2.uop.fp_ctrl.ren1 connect slots_13.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[13].brupdate.b2.uop.fp_ctrl.wen connect slots_13.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[13].brupdate.b2.uop.fp_ctrl.ldst connect slots_13.io.brupdate.b2.uop.op2_sel, issue_slots[13].brupdate.b2.uop.op2_sel connect slots_13.io.brupdate.b2.uop.op1_sel, issue_slots[13].brupdate.b2.uop.op1_sel connect slots_13.io.brupdate.b2.uop.imm_packed, issue_slots[13].brupdate.b2.uop.imm_packed connect slots_13.io.brupdate.b2.uop.pimm, issue_slots[13].brupdate.b2.uop.pimm connect slots_13.io.brupdate.b2.uop.imm_sel, issue_slots[13].brupdate.b2.uop.imm_sel connect slots_13.io.brupdate.b2.uop.imm_rename, issue_slots[13].brupdate.b2.uop.imm_rename connect slots_13.io.brupdate.b2.uop.taken, issue_slots[13].brupdate.b2.uop.taken connect slots_13.io.brupdate.b2.uop.pc_lob, issue_slots[13].brupdate.b2.uop.pc_lob connect slots_13.io.brupdate.b2.uop.edge_inst, issue_slots[13].brupdate.b2.uop.edge_inst connect slots_13.io.brupdate.b2.uop.ftq_idx, issue_slots[13].brupdate.b2.uop.ftq_idx connect slots_13.io.brupdate.b2.uop.is_mov, issue_slots[13].brupdate.b2.uop.is_mov connect slots_13.io.brupdate.b2.uop.is_rocc, issue_slots[13].brupdate.b2.uop.is_rocc connect slots_13.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[13].brupdate.b2.uop.is_sys_pc2epc connect slots_13.io.brupdate.b2.uop.is_eret, issue_slots[13].brupdate.b2.uop.is_eret connect slots_13.io.brupdate.b2.uop.is_amo, issue_slots[13].brupdate.b2.uop.is_amo connect slots_13.io.brupdate.b2.uop.is_sfence, issue_slots[13].brupdate.b2.uop.is_sfence connect slots_13.io.brupdate.b2.uop.is_fencei, issue_slots[13].brupdate.b2.uop.is_fencei connect slots_13.io.brupdate.b2.uop.is_fence, issue_slots[13].brupdate.b2.uop.is_fence connect slots_13.io.brupdate.b2.uop.is_sfb, issue_slots[13].brupdate.b2.uop.is_sfb connect slots_13.io.brupdate.b2.uop.br_type, issue_slots[13].brupdate.b2.uop.br_type connect slots_13.io.brupdate.b2.uop.br_tag, issue_slots[13].brupdate.b2.uop.br_tag connect slots_13.io.brupdate.b2.uop.br_mask, issue_slots[13].brupdate.b2.uop.br_mask connect slots_13.io.brupdate.b2.uop.dis_col_sel, issue_slots[13].brupdate.b2.uop.dis_col_sel connect slots_13.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[13].brupdate.b2.uop.iw_p3_bypass_hint connect slots_13.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[13].brupdate.b2.uop.iw_p2_bypass_hint connect slots_13.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[13].brupdate.b2.uop.iw_p1_bypass_hint connect slots_13.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[13].brupdate.b2.uop.iw_p2_speculative_child connect slots_13.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[13].brupdate.b2.uop.iw_p1_speculative_child connect slots_13.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[13].brupdate.b2.uop.iw_issued_partial_dgen connect slots_13.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[13].brupdate.b2.uop.iw_issued_partial_agen connect slots_13.io.brupdate.b2.uop.iw_issued, issue_slots[13].brupdate.b2.uop.iw_issued connect slots_13.io.brupdate.b2.uop.fu_code[0], issue_slots[13].brupdate.b2.uop.fu_code[0] connect slots_13.io.brupdate.b2.uop.fu_code[1], issue_slots[13].brupdate.b2.uop.fu_code[1] connect slots_13.io.brupdate.b2.uop.fu_code[2], issue_slots[13].brupdate.b2.uop.fu_code[2] connect slots_13.io.brupdate.b2.uop.fu_code[3], issue_slots[13].brupdate.b2.uop.fu_code[3] connect slots_13.io.brupdate.b2.uop.fu_code[4], issue_slots[13].brupdate.b2.uop.fu_code[4] connect slots_13.io.brupdate.b2.uop.fu_code[5], issue_slots[13].brupdate.b2.uop.fu_code[5] connect slots_13.io.brupdate.b2.uop.fu_code[6], issue_slots[13].brupdate.b2.uop.fu_code[6] connect slots_13.io.brupdate.b2.uop.fu_code[7], issue_slots[13].brupdate.b2.uop.fu_code[7] connect slots_13.io.brupdate.b2.uop.fu_code[8], issue_slots[13].brupdate.b2.uop.fu_code[8] connect slots_13.io.brupdate.b2.uop.fu_code[9], issue_slots[13].brupdate.b2.uop.fu_code[9] connect slots_13.io.brupdate.b2.uop.iq_type[0], issue_slots[13].brupdate.b2.uop.iq_type[0] connect slots_13.io.brupdate.b2.uop.iq_type[1], issue_slots[13].brupdate.b2.uop.iq_type[1] connect slots_13.io.brupdate.b2.uop.iq_type[2], issue_slots[13].brupdate.b2.uop.iq_type[2] connect slots_13.io.brupdate.b2.uop.iq_type[3], issue_slots[13].brupdate.b2.uop.iq_type[3] connect slots_13.io.brupdate.b2.uop.debug_pc, issue_slots[13].brupdate.b2.uop.debug_pc connect slots_13.io.brupdate.b2.uop.is_rvc, issue_slots[13].brupdate.b2.uop.is_rvc connect slots_13.io.brupdate.b2.uop.debug_inst, issue_slots[13].brupdate.b2.uop.debug_inst connect slots_13.io.brupdate.b2.uop.inst, issue_slots[13].brupdate.b2.uop.inst connect slots_13.io.brupdate.b1.mispredict_mask, issue_slots[13].brupdate.b1.mispredict_mask connect slots_13.io.brupdate.b1.resolve_mask, issue_slots[13].brupdate.b1.resolve_mask connect issue_slots[13].out_uop.debug_tsrc, slots_13.io.out_uop.debug_tsrc connect issue_slots[13].out_uop.debug_fsrc, slots_13.io.out_uop.debug_fsrc connect issue_slots[13].out_uop.bp_xcpt_if, slots_13.io.out_uop.bp_xcpt_if connect issue_slots[13].out_uop.bp_debug_if, slots_13.io.out_uop.bp_debug_if connect issue_slots[13].out_uop.xcpt_ma_if, slots_13.io.out_uop.xcpt_ma_if connect issue_slots[13].out_uop.xcpt_ae_if, slots_13.io.out_uop.xcpt_ae_if connect issue_slots[13].out_uop.xcpt_pf_if, slots_13.io.out_uop.xcpt_pf_if connect issue_slots[13].out_uop.fp_typ, slots_13.io.out_uop.fp_typ connect issue_slots[13].out_uop.fp_rm, slots_13.io.out_uop.fp_rm connect issue_slots[13].out_uop.fp_val, slots_13.io.out_uop.fp_val connect issue_slots[13].out_uop.fcn_op, slots_13.io.out_uop.fcn_op connect issue_slots[13].out_uop.fcn_dw, slots_13.io.out_uop.fcn_dw connect issue_slots[13].out_uop.frs3_en, slots_13.io.out_uop.frs3_en connect issue_slots[13].out_uop.lrs2_rtype, slots_13.io.out_uop.lrs2_rtype connect issue_slots[13].out_uop.lrs1_rtype, slots_13.io.out_uop.lrs1_rtype connect issue_slots[13].out_uop.dst_rtype, slots_13.io.out_uop.dst_rtype connect issue_slots[13].out_uop.lrs3, slots_13.io.out_uop.lrs3 connect issue_slots[13].out_uop.lrs2, slots_13.io.out_uop.lrs2 connect issue_slots[13].out_uop.lrs1, slots_13.io.out_uop.lrs1 connect issue_slots[13].out_uop.ldst, slots_13.io.out_uop.ldst connect issue_slots[13].out_uop.ldst_is_rs1, slots_13.io.out_uop.ldst_is_rs1 connect issue_slots[13].out_uop.csr_cmd, slots_13.io.out_uop.csr_cmd connect issue_slots[13].out_uop.flush_on_commit, slots_13.io.out_uop.flush_on_commit connect issue_slots[13].out_uop.is_unique, slots_13.io.out_uop.is_unique connect issue_slots[13].out_uop.uses_stq, slots_13.io.out_uop.uses_stq connect issue_slots[13].out_uop.uses_ldq, slots_13.io.out_uop.uses_ldq connect issue_slots[13].out_uop.mem_signed, slots_13.io.out_uop.mem_signed connect issue_slots[13].out_uop.mem_size, slots_13.io.out_uop.mem_size connect issue_slots[13].out_uop.mem_cmd, slots_13.io.out_uop.mem_cmd connect issue_slots[13].out_uop.exc_cause, slots_13.io.out_uop.exc_cause connect issue_slots[13].out_uop.exception, slots_13.io.out_uop.exception connect issue_slots[13].out_uop.stale_pdst, slots_13.io.out_uop.stale_pdst connect issue_slots[13].out_uop.ppred_busy, slots_13.io.out_uop.ppred_busy connect issue_slots[13].out_uop.prs3_busy, slots_13.io.out_uop.prs3_busy connect issue_slots[13].out_uop.prs2_busy, slots_13.io.out_uop.prs2_busy connect issue_slots[13].out_uop.prs1_busy, slots_13.io.out_uop.prs1_busy connect issue_slots[13].out_uop.ppred, slots_13.io.out_uop.ppred connect issue_slots[13].out_uop.prs3, slots_13.io.out_uop.prs3 connect issue_slots[13].out_uop.prs2, slots_13.io.out_uop.prs2 connect issue_slots[13].out_uop.prs1, slots_13.io.out_uop.prs1 connect issue_slots[13].out_uop.pdst, slots_13.io.out_uop.pdst connect issue_slots[13].out_uop.rxq_idx, slots_13.io.out_uop.rxq_idx connect issue_slots[13].out_uop.stq_idx, slots_13.io.out_uop.stq_idx connect issue_slots[13].out_uop.ldq_idx, slots_13.io.out_uop.ldq_idx connect issue_slots[13].out_uop.rob_idx, slots_13.io.out_uop.rob_idx connect issue_slots[13].out_uop.fp_ctrl.vec, slots_13.io.out_uop.fp_ctrl.vec connect issue_slots[13].out_uop.fp_ctrl.wflags, slots_13.io.out_uop.fp_ctrl.wflags connect issue_slots[13].out_uop.fp_ctrl.sqrt, slots_13.io.out_uop.fp_ctrl.sqrt connect issue_slots[13].out_uop.fp_ctrl.div, slots_13.io.out_uop.fp_ctrl.div connect issue_slots[13].out_uop.fp_ctrl.fma, slots_13.io.out_uop.fp_ctrl.fma connect issue_slots[13].out_uop.fp_ctrl.fastpipe, slots_13.io.out_uop.fp_ctrl.fastpipe connect issue_slots[13].out_uop.fp_ctrl.toint, slots_13.io.out_uop.fp_ctrl.toint connect issue_slots[13].out_uop.fp_ctrl.fromint, slots_13.io.out_uop.fp_ctrl.fromint connect issue_slots[13].out_uop.fp_ctrl.typeTagOut, slots_13.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[13].out_uop.fp_ctrl.typeTagIn, slots_13.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[13].out_uop.fp_ctrl.swap23, slots_13.io.out_uop.fp_ctrl.swap23 connect issue_slots[13].out_uop.fp_ctrl.swap12, slots_13.io.out_uop.fp_ctrl.swap12 connect issue_slots[13].out_uop.fp_ctrl.ren3, slots_13.io.out_uop.fp_ctrl.ren3 connect issue_slots[13].out_uop.fp_ctrl.ren2, slots_13.io.out_uop.fp_ctrl.ren2 connect issue_slots[13].out_uop.fp_ctrl.ren1, slots_13.io.out_uop.fp_ctrl.ren1 connect issue_slots[13].out_uop.fp_ctrl.wen, slots_13.io.out_uop.fp_ctrl.wen connect issue_slots[13].out_uop.fp_ctrl.ldst, slots_13.io.out_uop.fp_ctrl.ldst connect issue_slots[13].out_uop.op2_sel, slots_13.io.out_uop.op2_sel connect issue_slots[13].out_uop.op1_sel, slots_13.io.out_uop.op1_sel connect issue_slots[13].out_uop.imm_packed, slots_13.io.out_uop.imm_packed connect issue_slots[13].out_uop.pimm, slots_13.io.out_uop.pimm connect issue_slots[13].out_uop.imm_sel, slots_13.io.out_uop.imm_sel connect issue_slots[13].out_uop.imm_rename, slots_13.io.out_uop.imm_rename connect issue_slots[13].out_uop.taken, slots_13.io.out_uop.taken connect issue_slots[13].out_uop.pc_lob, slots_13.io.out_uop.pc_lob connect issue_slots[13].out_uop.edge_inst, slots_13.io.out_uop.edge_inst connect issue_slots[13].out_uop.ftq_idx, slots_13.io.out_uop.ftq_idx connect issue_slots[13].out_uop.is_mov, slots_13.io.out_uop.is_mov connect issue_slots[13].out_uop.is_rocc, slots_13.io.out_uop.is_rocc connect issue_slots[13].out_uop.is_sys_pc2epc, slots_13.io.out_uop.is_sys_pc2epc connect issue_slots[13].out_uop.is_eret, slots_13.io.out_uop.is_eret connect issue_slots[13].out_uop.is_amo, slots_13.io.out_uop.is_amo connect issue_slots[13].out_uop.is_sfence, slots_13.io.out_uop.is_sfence connect issue_slots[13].out_uop.is_fencei, slots_13.io.out_uop.is_fencei connect issue_slots[13].out_uop.is_fence, slots_13.io.out_uop.is_fence connect issue_slots[13].out_uop.is_sfb, slots_13.io.out_uop.is_sfb connect issue_slots[13].out_uop.br_type, slots_13.io.out_uop.br_type connect issue_slots[13].out_uop.br_tag, slots_13.io.out_uop.br_tag connect issue_slots[13].out_uop.br_mask, slots_13.io.out_uop.br_mask connect issue_slots[13].out_uop.dis_col_sel, slots_13.io.out_uop.dis_col_sel connect issue_slots[13].out_uop.iw_p3_bypass_hint, slots_13.io.out_uop.iw_p3_bypass_hint connect issue_slots[13].out_uop.iw_p2_bypass_hint, slots_13.io.out_uop.iw_p2_bypass_hint connect issue_slots[13].out_uop.iw_p1_bypass_hint, slots_13.io.out_uop.iw_p1_bypass_hint connect issue_slots[13].out_uop.iw_p2_speculative_child, slots_13.io.out_uop.iw_p2_speculative_child connect issue_slots[13].out_uop.iw_p1_speculative_child, slots_13.io.out_uop.iw_p1_speculative_child connect issue_slots[13].out_uop.iw_issued_partial_dgen, slots_13.io.out_uop.iw_issued_partial_dgen connect issue_slots[13].out_uop.iw_issued_partial_agen, slots_13.io.out_uop.iw_issued_partial_agen connect issue_slots[13].out_uop.iw_issued, slots_13.io.out_uop.iw_issued connect issue_slots[13].out_uop.fu_code[0], slots_13.io.out_uop.fu_code[0] connect issue_slots[13].out_uop.fu_code[1], slots_13.io.out_uop.fu_code[1] connect issue_slots[13].out_uop.fu_code[2], slots_13.io.out_uop.fu_code[2] connect issue_slots[13].out_uop.fu_code[3], slots_13.io.out_uop.fu_code[3] connect issue_slots[13].out_uop.fu_code[4], slots_13.io.out_uop.fu_code[4] connect issue_slots[13].out_uop.fu_code[5], slots_13.io.out_uop.fu_code[5] connect issue_slots[13].out_uop.fu_code[6], slots_13.io.out_uop.fu_code[6] connect issue_slots[13].out_uop.fu_code[7], slots_13.io.out_uop.fu_code[7] connect issue_slots[13].out_uop.fu_code[8], slots_13.io.out_uop.fu_code[8] connect issue_slots[13].out_uop.fu_code[9], slots_13.io.out_uop.fu_code[9] connect issue_slots[13].out_uop.iq_type[0], slots_13.io.out_uop.iq_type[0] connect issue_slots[13].out_uop.iq_type[1], slots_13.io.out_uop.iq_type[1] connect issue_slots[13].out_uop.iq_type[2], slots_13.io.out_uop.iq_type[2] connect issue_slots[13].out_uop.iq_type[3], slots_13.io.out_uop.iq_type[3] connect issue_slots[13].out_uop.debug_pc, slots_13.io.out_uop.debug_pc connect issue_slots[13].out_uop.is_rvc, slots_13.io.out_uop.is_rvc connect issue_slots[13].out_uop.debug_inst, slots_13.io.out_uop.debug_inst connect issue_slots[13].out_uop.inst, slots_13.io.out_uop.inst connect slots_13.io.in_uop.bits.debug_tsrc, issue_slots[13].in_uop.bits.debug_tsrc connect slots_13.io.in_uop.bits.debug_fsrc, issue_slots[13].in_uop.bits.debug_fsrc connect slots_13.io.in_uop.bits.bp_xcpt_if, issue_slots[13].in_uop.bits.bp_xcpt_if connect slots_13.io.in_uop.bits.bp_debug_if, issue_slots[13].in_uop.bits.bp_debug_if connect slots_13.io.in_uop.bits.xcpt_ma_if, issue_slots[13].in_uop.bits.xcpt_ma_if connect slots_13.io.in_uop.bits.xcpt_ae_if, issue_slots[13].in_uop.bits.xcpt_ae_if connect slots_13.io.in_uop.bits.xcpt_pf_if, issue_slots[13].in_uop.bits.xcpt_pf_if connect slots_13.io.in_uop.bits.fp_typ, issue_slots[13].in_uop.bits.fp_typ connect slots_13.io.in_uop.bits.fp_rm, issue_slots[13].in_uop.bits.fp_rm connect slots_13.io.in_uop.bits.fp_val, issue_slots[13].in_uop.bits.fp_val connect slots_13.io.in_uop.bits.fcn_op, issue_slots[13].in_uop.bits.fcn_op connect slots_13.io.in_uop.bits.fcn_dw, issue_slots[13].in_uop.bits.fcn_dw connect slots_13.io.in_uop.bits.frs3_en, issue_slots[13].in_uop.bits.frs3_en connect slots_13.io.in_uop.bits.lrs2_rtype, issue_slots[13].in_uop.bits.lrs2_rtype connect slots_13.io.in_uop.bits.lrs1_rtype, issue_slots[13].in_uop.bits.lrs1_rtype connect slots_13.io.in_uop.bits.dst_rtype, issue_slots[13].in_uop.bits.dst_rtype connect slots_13.io.in_uop.bits.lrs3, issue_slots[13].in_uop.bits.lrs3 connect slots_13.io.in_uop.bits.lrs2, issue_slots[13].in_uop.bits.lrs2 connect slots_13.io.in_uop.bits.lrs1, issue_slots[13].in_uop.bits.lrs1 connect slots_13.io.in_uop.bits.ldst, issue_slots[13].in_uop.bits.ldst connect slots_13.io.in_uop.bits.ldst_is_rs1, issue_slots[13].in_uop.bits.ldst_is_rs1 connect slots_13.io.in_uop.bits.csr_cmd, issue_slots[13].in_uop.bits.csr_cmd connect slots_13.io.in_uop.bits.flush_on_commit, issue_slots[13].in_uop.bits.flush_on_commit connect slots_13.io.in_uop.bits.is_unique, issue_slots[13].in_uop.bits.is_unique connect slots_13.io.in_uop.bits.uses_stq, issue_slots[13].in_uop.bits.uses_stq connect slots_13.io.in_uop.bits.uses_ldq, issue_slots[13].in_uop.bits.uses_ldq connect slots_13.io.in_uop.bits.mem_signed, issue_slots[13].in_uop.bits.mem_signed connect slots_13.io.in_uop.bits.mem_size, issue_slots[13].in_uop.bits.mem_size connect slots_13.io.in_uop.bits.mem_cmd, issue_slots[13].in_uop.bits.mem_cmd connect slots_13.io.in_uop.bits.exc_cause, issue_slots[13].in_uop.bits.exc_cause connect slots_13.io.in_uop.bits.exception, issue_slots[13].in_uop.bits.exception connect slots_13.io.in_uop.bits.stale_pdst, issue_slots[13].in_uop.bits.stale_pdst connect slots_13.io.in_uop.bits.ppred_busy, issue_slots[13].in_uop.bits.ppred_busy connect slots_13.io.in_uop.bits.prs3_busy, issue_slots[13].in_uop.bits.prs3_busy connect slots_13.io.in_uop.bits.prs2_busy, issue_slots[13].in_uop.bits.prs2_busy connect slots_13.io.in_uop.bits.prs1_busy, issue_slots[13].in_uop.bits.prs1_busy connect slots_13.io.in_uop.bits.ppred, issue_slots[13].in_uop.bits.ppred connect slots_13.io.in_uop.bits.prs3, issue_slots[13].in_uop.bits.prs3 connect slots_13.io.in_uop.bits.prs2, issue_slots[13].in_uop.bits.prs2 connect slots_13.io.in_uop.bits.prs1, issue_slots[13].in_uop.bits.prs1 connect slots_13.io.in_uop.bits.pdst, issue_slots[13].in_uop.bits.pdst connect slots_13.io.in_uop.bits.rxq_idx, issue_slots[13].in_uop.bits.rxq_idx connect slots_13.io.in_uop.bits.stq_idx, issue_slots[13].in_uop.bits.stq_idx connect slots_13.io.in_uop.bits.ldq_idx, issue_slots[13].in_uop.bits.ldq_idx connect slots_13.io.in_uop.bits.rob_idx, issue_slots[13].in_uop.bits.rob_idx connect slots_13.io.in_uop.bits.fp_ctrl.vec, issue_slots[13].in_uop.bits.fp_ctrl.vec connect slots_13.io.in_uop.bits.fp_ctrl.wflags, issue_slots[13].in_uop.bits.fp_ctrl.wflags connect slots_13.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[13].in_uop.bits.fp_ctrl.sqrt connect slots_13.io.in_uop.bits.fp_ctrl.div, issue_slots[13].in_uop.bits.fp_ctrl.div connect slots_13.io.in_uop.bits.fp_ctrl.fma, issue_slots[13].in_uop.bits.fp_ctrl.fma connect slots_13.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].in_uop.bits.fp_ctrl.fastpipe connect slots_13.io.in_uop.bits.fp_ctrl.toint, issue_slots[13].in_uop.bits.fp_ctrl.toint connect slots_13.io.in_uop.bits.fp_ctrl.fromint, issue_slots[13].in_uop.bits.fp_ctrl.fromint connect slots_13.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut connect slots_13.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn connect slots_13.io.in_uop.bits.fp_ctrl.swap23, issue_slots[13].in_uop.bits.fp_ctrl.swap23 connect slots_13.io.in_uop.bits.fp_ctrl.swap12, issue_slots[13].in_uop.bits.fp_ctrl.swap12 connect slots_13.io.in_uop.bits.fp_ctrl.ren3, issue_slots[13].in_uop.bits.fp_ctrl.ren3 connect slots_13.io.in_uop.bits.fp_ctrl.ren2, issue_slots[13].in_uop.bits.fp_ctrl.ren2 connect slots_13.io.in_uop.bits.fp_ctrl.ren1, issue_slots[13].in_uop.bits.fp_ctrl.ren1 connect slots_13.io.in_uop.bits.fp_ctrl.wen, issue_slots[13].in_uop.bits.fp_ctrl.wen connect slots_13.io.in_uop.bits.fp_ctrl.ldst, issue_slots[13].in_uop.bits.fp_ctrl.ldst connect slots_13.io.in_uop.bits.op2_sel, issue_slots[13].in_uop.bits.op2_sel connect slots_13.io.in_uop.bits.op1_sel, issue_slots[13].in_uop.bits.op1_sel connect slots_13.io.in_uop.bits.imm_packed, issue_slots[13].in_uop.bits.imm_packed connect slots_13.io.in_uop.bits.pimm, issue_slots[13].in_uop.bits.pimm connect slots_13.io.in_uop.bits.imm_sel, issue_slots[13].in_uop.bits.imm_sel connect slots_13.io.in_uop.bits.imm_rename, issue_slots[13].in_uop.bits.imm_rename connect slots_13.io.in_uop.bits.taken, issue_slots[13].in_uop.bits.taken connect slots_13.io.in_uop.bits.pc_lob, issue_slots[13].in_uop.bits.pc_lob connect slots_13.io.in_uop.bits.edge_inst, issue_slots[13].in_uop.bits.edge_inst connect slots_13.io.in_uop.bits.ftq_idx, issue_slots[13].in_uop.bits.ftq_idx connect slots_13.io.in_uop.bits.is_mov, issue_slots[13].in_uop.bits.is_mov connect slots_13.io.in_uop.bits.is_rocc, issue_slots[13].in_uop.bits.is_rocc connect slots_13.io.in_uop.bits.is_sys_pc2epc, issue_slots[13].in_uop.bits.is_sys_pc2epc connect slots_13.io.in_uop.bits.is_eret, issue_slots[13].in_uop.bits.is_eret connect slots_13.io.in_uop.bits.is_amo, issue_slots[13].in_uop.bits.is_amo connect slots_13.io.in_uop.bits.is_sfence, issue_slots[13].in_uop.bits.is_sfence connect slots_13.io.in_uop.bits.is_fencei, issue_slots[13].in_uop.bits.is_fencei connect slots_13.io.in_uop.bits.is_fence, issue_slots[13].in_uop.bits.is_fence connect slots_13.io.in_uop.bits.is_sfb, issue_slots[13].in_uop.bits.is_sfb connect slots_13.io.in_uop.bits.br_type, issue_slots[13].in_uop.bits.br_type connect slots_13.io.in_uop.bits.br_tag, issue_slots[13].in_uop.bits.br_tag connect slots_13.io.in_uop.bits.br_mask, issue_slots[13].in_uop.bits.br_mask connect slots_13.io.in_uop.bits.dis_col_sel, issue_slots[13].in_uop.bits.dis_col_sel connect slots_13.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[13].in_uop.bits.iw_p3_bypass_hint connect slots_13.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[13].in_uop.bits.iw_p2_bypass_hint connect slots_13.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[13].in_uop.bits.iw_p1_bypass_hint connect slots_13.io.in_uop.bits.iw_p2_speculative_child, issue_slots[13].in_uop.bits.iw_p2_speculative_child connect slots_13.io.in_uop.bits.iw_p1_speculative_child, issue_slots[13].in_uop.bits.iw_p1_speculative_child connect slots_13.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[13].in_uop.bits.iw_issued_partial_dgen connect slots_13.io.in_uop.bits.iw_issued_partial_agen, issue_slots[13].in_uop.bits.iw_issued_partial_agen connect slots_13.io.in_uop.bits.iw_issued, issue_slots[13].in_uop.bits.iw_issued connect slots_13.io.in_uop.bits.fu_code[0], issue_slots[13].in_uop.bits.fu_code[0] connect slots_13.io.in_uop.bits.fu_code[1], issue_slots[13].in_uop.bits.fu_code[1] connect slots_13.io.in_uop.bits.fu_code[2], issue_slots[13].in_uop.bits.fu_code[2] connect slots_13.io.in_uop.bits.fu_code[3], issue_slots[13].in_uop.bits.fu_code[3] connect slots_13.io.in_uop.bits.fu_code[4], issue_slots[13].in_uop.bits.fu_code[4] connect slots_13.io.in_uop.bits.fu_code[5], issue_slots[13].in_uop.bits.fu_code[5] connect slots_13.io.in_uop.bits.fu_code[6], issue_slots[13].in_uop.bits.fu_code[6] connect slots_13.io.in_uop.bits.fu_code[7], issue_slots[13].in_uop.bits.fu_code[7] connect slots_13.io.in_uop.bits.fu_code[8], issue_slots[13].in_uop.bits.fu_code[8] connect slots_13.io.in_uop.bits.fu_code[9], issue_slots[13].in_uop.bits.fu_code[9] connect slots_13.io.in_uop.bits.iq_type[0], issue_slots[13].in_uop.bits.iq_type[0] connect slots_13.io.in_uop.bits.iq_type[1], issue_slots[13].in_uop.bits.iq_type[1] connect slots_13.io.in_uop.bits.iq_type[2], issue_slots[13].in_uop.bits.iq_type[2] connect slots_13.io.in_uop.bits.iq_type[3], issue_slots[13].in_uop.bits.iq_type[3] connect slots_13.io.in_uop.bits.debug_pc, issue_slots[13].in_uop.bits.debug_pc connect slots_13.io.in_uop.bits.is_rvc, issue_slots[13].in_uop.bits.is_rvc connect slots_13.io.in_uop.bits.debug_inst, issue_slots[13].in_uop.bits.debug_inst connect slots_13.io.in_uop.bits.inst, issue_slots[13].in_uop.bits.inst connect slots_13.io.in_uop.valid, issue_slots[13].in_uop.valid connect issue_slots[13].iss_uop.debug_tsrc, slots_13.io.iss_uop.debug_tsrc connect issue_slots[13].iss_uop.debug_fsrc, slots_13.io.iss_uop.debug_fsrc connect issue_slots[13].iss_uop.bp_xcpt_if, slots_13.io.iss_uop.bp_xcpt_if connect issue_slots[13].iss_uop.bp_debug_if, slots_13.io.iss_uop.bp_debug_if connect issue_slots[13].iss_uop.xcpt_ma_if, slots_13.io.iss_uop.xcpt_ma_if connect issue_slots[13].iss_uop.xcpt_ae_if, slots_13.io.iss_uop.xcpt_ae_if connect issue_slots[13].iss_uop.xcpt_pf_if, slots_13.io.iss_uop.xcpt_pf_if connect issue_slots[13].iss_uop.fp_typ, slots_13.io.iss_uop.fp_typ connect issue_slots[13].iss_uop.fp_rm, slots_13.io.iss_uop.fp_rm connect issue_slots[13].iss_uop.fp_val, slots_13.io.iss_uop.fp_val connect issue_slots[13].iss_uop.fcn_op, slots_13.io.iss_uop.fcn_op connect issue_slots[13].iss_uop.fcn_dw, slots_13.io.iss_uop.fcn_dw connect issue_slots[13].iss_uop.frs3_en, slots_13.io.iss_uop.frs3_en connect issue_slots[13].iss_uop.lrs2_rtype, slots_13.io.iss_uop.lrs2_rtype connect issue_slots[13].iss_uop.lrs1_rtype, slots_13.io.iss_uop.lrs1_rtype connect issue_slots[13].iss_uop.dst_rtype, slots_13.io.iss_uop.dst_rtype connect issue_slots[13].iss_uop.lrs3, slots_13.io.iss_uop.lrs3 connect issue_slots[13].iss_uop.lrs2, slots_13.io.iss_uop.lrs2 connect issue_slots[13].iss_uop.lrs1, slots_13.io.iss_uop.lrs1 connect issue_slots[13].iss_uop.ldst, slots_13.io.iss_uop.ldst connect issue_slots[13].iss_uop.ldst_is_rs1, slots_13.io.iss_uop.ldst_is_rs1 connect issue_slots[13].iss_uop.csr_cmd, slots_13.io.iss_uop.csr_cmd connect issue_slots[13].iss_uop.flush_on_commit, slots_13.io.iss_uop.flush_on_commit connect issue_slots[13].iss_uop.is_unique, slots_13.io.iss_uop.is_unique connect issue_slots[13].iss_uop.uses_stq, slots_13.io.iss_uop.uses_stq connect issue_slots[13].iss_uop.uses_ldq, slots_13.io.iss_uop.uses_ldq connect issue_slots[13].iss_uop.mem_signed, slots_13.io.iss_uop.mem_signed connect issue_slots[13].iss_uop.mem_size, slots_13.io.iss_uop.mem_size connect issue_slots[13].iss_uop.mem_cmd, slots_13.io.iss_uop.mem_cmd connect issue_slots[13].iss_uop.exc_cause, slots_13.io.iss_uop.exc_cause connect issue_slots[13].iss_uop.exception, slots_13.io.iss_uop.exception connect issue_slots[13].iss_uop.stale_pdst, slots_13.io.iss_uop.stale_pdst connect issue_slots[13].iss_uop.ppred_busy, slots_13.io.iss_uop.ppred_busy connect issue_slots[13].iss_uop.prs3_busy, slots_13.io.iss_uop.prs3_busy connect issue_slots[13].iss_uop.prs2_busy, slots_13.io.iss_uop.prs2_busy connect issue_slots[13].iss_uop.prs1_busy, slots_13.io.iss_uop.prs1_busy connect issue_slots[13].iss_uop.ppred, slots_13.io.iss_uop.ppred connect issue_slots[13].iss_uop.prs3, slots_13.io.iss_uop.prs3 connect issue_slots[13].iss_uop.prs2, slots_13.io.iss_uop.prs2 connect issue_slots[13].iss_uop.prs1, slots_13.io.iss_uop.prs1 connect issue_slots[13].iss_uop.pdst, slots_13.io.iss_uop.pdst connect issue_slots[13].iss_uop.rxq_idx, slots_13.io.iss_uop.rxq_idx connect issue_slots[13].iss_uop.stq_idx, slots_13.io.iss_uop.stq_idx connect issue_slots[13].iss_uop.ldq_idx, slots_13.io.iss_uop.ldq_idx connect issue_slots[13].iss_uop.rob_idx, slots_13.io.iss_uop.rob_idx connect issue_slots[13].iss_uop.fp_ctrl.vec, slots_13.io.iss_uop.fp_ctrl.vec connect issue_slots[13].iss_uop.fp_ctrl.wflags, slots_13.io.iss_uop.fp_ctrl.wflags connect issue_slots[13].iss_uop.fp_ctrl.sqrt, slots_13.io.iss_uop.fp_ctrl.sqrt connect issue_slots[13].iss_uop.fp_ctrl.div, slots_13.io.iss_uop.fp_ctrl.div connect issue_slots[13].iss_uop.fp_ctrl.fma, slots_13.io.iss_uop.fp_ctrl.fma connect issue_slots[13].iss_uop.fp_ctrl.fastpipe, slots_13.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[13].iss_uop.fp_ctrl.toint, slots_13.io.iss_uop.fp_ctrl.toint connect issue_slots[13].iss_uop.fp_ctrl.fromint, slots_13.io.iss_uop.fp_ctrl.fromint connect issue_slots[13].iss_uop.fp_ctrl.typeTagOut, slots_13.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[13].iss_uop.fp_ctrl.typeTagIn, slots_13.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[13].iss_uop.fp_ctrl.swap23, slots_13.io.iss_uop.fp_ctrl.swap23 connect issue_slots[13].iss_uop.fp_ctrl.swap12, slots_13.io.iss_uop.fp_ctrl.swap12 connect issue_slots[13].iss_uop.fp_ctrl.ren3, slots_13.io.iss_uop.fp_ctrl.ren3 connect issue_slots[13].iss_uop.fp_ctrl.ren2, slots_13.io.iss_uop.fp_ctrl.ren2 connect issue_slots[13].iss_uop.fp_ctrl.ren1, slots_13.io.iss_uop.fp_ctrl.ren1 connect issue_slots[13].iss_uop.fp_ctrl.wen, slots_13.io.iss_uop.fp_ctrl.wen connect issue_slots[13].iss_uop.fp_ctrl.ldst, slots_13.io.iss_uop.fp_ctrl.ldst connect issue_slots[13].iss_uop.op2_sel, slots_13.io.iss_uop.op2_sel connect issue_slots[13].iss_uop.op1_sel, slots_13.io.iss_uop.op1_sel connect issue_slots[13].iss_uop.imm_packed, slots_13.io.iss_uop.imm_packed connect issue_slots[13].iss_uop.pimm, slots_13.io.iss_uop.pimm connect issue_slots[13].iss_uop.imm_sel, slots_13.io.iss_uop.imm_sel connect issue_slots[13].iss_uop.imm_rename, slots_13.io.iss_uop.imm_rename connect issue_slots[13].iss_uop.taken, slots_13.io.iss_uop.taken connect issue_slots[13].iss_uop.pc_lob, slots_13.io.iss_uop.pc_lob connect issue_slots[13].iss_uop.edge_inst, slots_13.io.iss_uop.edge_inst connect issue_slots[13].iss_uop.ftq_idx, slots_13.io.iss_uop.ftq_idx connect issue_slots[13].iss_uop.is_mov, slots_13.io.iss_uop.is_mov connect issue_slots[13].iss_uop.is_rocc, slots_13.io.iss_uop.is_rocc connect issue_slots[13].iss_uop.is_sys_pc2epc, slots_13.io.iss_uop.is_sys_pc2epc connect issue_slots[13].iss_uop.is_eret, slots_13.io.iss_uop.is_eret connect issue_slots[13].iss_uop.is_amo, slots_13.io.iss_uop.is_amo connect issue_slots[13].iss_uop.is_sfence, slots_13.io.iss_uop.is_sfence connect issue_slots[13].iss_uop.is_fencei, slots_13.io.iss_uop.is_fencei connect issue_slots[13].iss_uop.is_fence, slots_13.io.iss_uop.is_fence connect issue_slots[13].iss_uop.is_sfb, slots_13.io.iss_uop.is_sfb connect issue_slots[13].iss_uop.br_type, slots_13.io.iss_uop.br_type connect issue_slots[13].iss_uop.br_tag, slots_13.io.iss_uop.br_tag connect issue_slots[13].iss_uop.br_mask, slots_13.io.iss_uop.br_mask connect issue_slots[13].iss_uop.dis_col_sel, slots_13.io.iss_uop.dis_col_sel connect issue_slots[13].iss_uop.iw_p3_bypass_hint, slots_13.io.iss_uop.iw_p3_bypass_hint connect issue_slots[13].iss_uop.iw_p2_bypass_hint, slots_13.io.iss_uop.iw_p2_bypass_hint connect issue_slots[13].iss_uop.iw_p1_bypass_hint, slots_13.io.iss_uop.iw_p1_bypass_hint connect issue_slots[13].iss_uop.iw_p2_speculative_child, slots_13.io.iss_uop.iw_p2_speculative_child connect issue_slots[13].iss_uop.iw_p1_speculative_child, slots_13.io.iss_uop.iw_p1_speculative_child connect issue_slots[13].iss_uop.iw_issued_partial_dgen, slots_13.io.iss_uop.iw_issued_partial_dgen connect issue_slots[13].iss_uop.iw_issued_partial_agen, slots_13.io.iss_uop.iw_issued_partial_agen connect issue_slots[13].iss_uop.iw_issued, slots_13.io.iss_uop.iw_issued connect issue_slots[13].iss_uop.fu_code[0], slots_13.io.iss_uop.fu_code[0] connect issue_slots[13].iss_uop.fu_code[1], slots_13.io.iss_uop.fu_code[1] connect issue_slots[13].iss_uop.fu_code[2], slots_13.io.iss_uop.fu_code[2] connect issue_slots[13].iss_uop.fu_code[3], slots_13.io.iss_uop.fu_code[3] connect issue_slots[13].iss_uop.fu_code[4], slots_13.io.iss_uop.fu_code[4] connect issue_slots[13].iss_uop.fu_code[5], slots_13.io.iss_uop.fu_code[5] connect issue_slots[13].iss_uop.fu_code[6], slots_13.io.iss_uop.fu_code[6] connect issue_slots[13].iss_uop.fu_code[7], slots_13.io.iss_uop.fu_code[7] connect issue_slots[13].iss_uop.fu_code[8], slots_13.io.iss_uop.fu_code[8] connect issue_slots[13].iss_uop.fu_code[9], slots_13.io.iss_uop.fu_code[9] connect issue_slots[13].iss_uop.iq_type[0], slots_13.io.iss_uop.iq_type[0] connect issue_slots[13].iss_uop.iq_type[1], slots_13.io.iss_uop.iq_type[1] connect issue_slots[13].iss_uop.iq_type[2], slots_13.io.iss_uop.iq_type[2] connect issue_slots[13].iss_uop.iq_type[3], slots_13.io.iss_uop.iq_type[3] connect issue_slots[13].iss_uop.debug_pc, slots_13.io.iss_uop.debug_pc connect issue_slots[13].iss_uop.is_rvc, slots_13.io.iss_uop.is_rvc connect issue_slots[13].iss_uop.debug_inst, slots_13.io.iss_uop.debug_inst connect issue_slots[13].iss_uop.inst, slots_13.io.iss_uop.inst connect slots_13.io.grant, issue_slots[13].grant connect issue_slots[13].request, slots_13.io.request connect issue_slots[13].will_be_valid, slots_13.io.will_be_valid connect issue_slots[13].valid, slots_13.io.valid connect slots_14.io.child_rebusys, issue_slots[14].child_rebusys connect slots_14.io.pred_wakeup_port.bits, issue_slots[14].pred_wakeup_port.bits connect slots_14.io.pred_wakeup_port.valid, issue_slots[14].pred_wakeup_port.valid connect slots_14.io.wakeup_ports[0].bits.rebusy, issue_slots[14].wakeup_ports[0].bits.rebusy connect slots_14.io.wakeup_ports[0].bits.speculative_mask, issue_slots[14].wakeup_ports[0].bits.speculative_mask connect slots_14.io.wakeup_ports[0].bits.bypassable, issue_slots[14].wakeup_ports[0].bits.bypassable connect slots_14.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[0].bits.uop.debug_tsrc connect slots_14.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[0].bits.uop.debug_fsrc connect slots_14.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_14.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[0].bits.uop.bp_debug_if connect slots_14.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_14.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_14.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_14.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[14].wakeup_ports[0].bits.uop.fp_typ connect slots_14.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[14].wakeup_ports[0].bits.uop.fp_rm connect slots_14.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[14].wakeup_ports[0].bits.uop.fp_val connect slots_14.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[14].wakeup_ports[0].bits.uop.fcn_op connect slots_14.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[0].bits.uop.fcn_dw connect slots_14.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[14].wakeup_ports[0].bits.uop.frs3_en connect slots_14.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_14.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_14.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[0].bits.uop.dst_rtype connect slots_14.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[14].wakeup_ports[0].bits.uop.lrs3 connect slots_14.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[14].wakeup_ports[0].bits.uop.lrs2 connect slots_14.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[14].wakeup_ports[0].bits.uop.lrs1 connect slots_14.io.wakeup_ports[0].bits.uop.ldst, issue_slots[14].wakeup_ports[0].bits.uop.ldst connect slots_14.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_14.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[0].bits.uop.csr_cmd connect slots_14.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[0].bits.uop.flush_on_commit connect slots_14.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[14].wakeup_ports[0].bits.uop.is_unique connect slots_14.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[14].wakeup_ports[0].bits.uop.uses_stq connect slots_14.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[0].bits.uop.uses_ldq connect slots_14.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[14].wakeup_ports[0].bits.uop.mem_signed connect slots_14.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[14].wakeup_ports[0].bits.uop.mem_size connect slots_14.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[0].bits.uop.mem_cmd connect slots_14.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[14].wakeup_ports[0].bits.uop.exc_cause connect slots_14.io.wakeup_ports[0].bits.uop.exception, issue_slots[14].wakeup_ports[0].bits.uop.exception connect slots_14.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[0].bits.uop.stale_pdst connect slots_14.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[0].bits.uop.ppred_busy connect slots_14.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[0].bits.uop.prs3_busy connect slots_14.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[0].bits.uop.prs2_busy connect slots_14.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[0].bits.uop.prs1_busy connect slots_14.io.wakeup_ports[0].bits.uop.ppred, issue_slots[14].wakeup_ports[0].bits.uop.ppred connect slots_14.io.wakeup_ports[0].bits.uop.prs3, issue_slots[14].wakeup_ports[0].bits.uop.prs3 connect slots_14.io.wakeup_ports[0].bits.uop.prs2, issue_slots[14].wakeup_ports[0].bits.uop.prs2 connect slots_14.io.wakeup_ports[0].bits.uop.prs1, issue_slots[14].wakeup_ports[0].bits.uop.prs1 connect slots_14.io.wakeup_ports[0].bits.uop.pdst, issue_slots[14].wakeup_ports[0].bits.uop.pdst connect slots_14.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[0].bits.uop.rxq_idx connect slots_14.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[14].wakeup_ports[0].bits.uop.stq_idx connect slots_14.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[0].bits.uop.ldq_idx connect slots_14.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[14].wakeup_ports[0].bits.uop.rob_idx connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_14.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[14].wakeup_ports[0].bits.uop.op2_sel connect slots_14.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[14].wakeup_ports[0].bits.uop.op1_sel connect slots_14.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[14].wakeup_ports[0].bits.uop.imm_packed connect slots_14.io.wakeup_ports[0].bits.uop.pimm, issue_slots[14].wakeup_ports[0].bits.uop.pimm connect slots_14.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[14].wakeup_ports[0].bits.uop.imm_sel connect slots_14.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[14].wakeup_ports[0].bits.uop.imm_rename connect slots_14.io.wakeup_ports[0].bits.uop.taken, issue_slots[14].wakeup_ports[0].bits.uop.taken connect slots_14.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[14].wakeup_ports[0].bits.uop.pc_lob connect slots_14.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[14].wakeup_ports[0].bits.uop.edge_inst connect slots_14.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[0].bits.uop.ftq_idx connect slots_14.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[14].wakeup_ports[0].bits.uop.is_mov connect slots_14.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[14].wakeup_ports[0].bits.uop.is_rocc connect slots_14.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_14.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[14].wakeup_ports[0].bits.uop.is_eret connect slots_14.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[14].wakeup_ports[0].bits.uop.is_amo connect slots_14.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[14].wakeup_ports[0].bits.uop.is_sfence connect slots_14.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[14].wakeup_ports[0].bits.uop.is_fencei connect slots_14.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[14].wakeup_ports[0].bits.uop.is_fence connect slots_14.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[14].wakeup_ports[0].bits.uop.is_sfb connect slots_14.io.wakeup_ports[0].bits.uop.br_type, issue_slots[14].wakeup_ports[0].bits.uop.br_type connect slots_14.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[14].wakeup_ports[0].bits.uop.br_tag connect slots_14.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[14].wakeup_ports[0].bits.uop.br_mask connect slots_14.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[0].bits.uop.dis_col_sel connect slots_14.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_14.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_14.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_14.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_14.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_14.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_14.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_14.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[14].wakeup_ports[0].bits.uop.iw_issued connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[0] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[1] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[2] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[3] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[4] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[5] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[6] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[7] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[8] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[9] connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[0] connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[1] connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[2] connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[3] connect slots_14.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[14].wakeup_ports[0].bits.uop.debug_pc connect slots_14.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[14].wakeup_ports[0].bits.uop.is_rvc connect slots_14.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[14].wakeup_ports[0].bits.uop.debug_inst connect slots_14.io.wakeup_ports[0].bits.uop.inst, issue_slots[14].wakeup_ports[0].bits.uop.inst connect slots_14.io.wakeup_ports[0].valid, issue_slots[14].wakeup_ports[0].valid connect slots_14.io.wakeup_ports[1].bits.rebusy, issue_slots[14].wakeup_ports[1].bits.rebusy connect slots_14.io.wakeup_ports[1].bits.speculative_mask, issue_slots[14].wakeup_ports[1].bits.speculative_mask connect slots_14.io.wakeup_ports[1].bits.bypassable, issue_slots[14].wakeup_ports[1].bits.bypassable connect slots_14.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[1].bits.uop.debug_tsrc connect slots_14.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[1].bits.uop.debug_fsrc connect slots_14.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_14.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[1].bits.uop.bp_debug_if connect slots_14.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_14.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_14.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_14.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[14].wakeup_ports[1].bits.uop.fp_typ connect slots_14.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[14].wakeup_ports[1].bits.uop.fp_rm connect slots_14.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[14].wakeup_ports[1].bits.uop.fp_val connect slots_14.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[14].wakeup_ports[1].bits.uop.fcn_op connect slots_14.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[1].bits.uop.fcn_dw connect slots_14.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[14].wakeup_ports[1].bits.uop.frs3_en connect slots_14.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_14.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_14.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[1].bits.uop.dst_rtype connect slots_14.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[14].wakeup_ports[1].bits.uop.lrs3 connect slots_14.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[14].wakeup_ports[1].bits.uop.lrs2 connect slots_14.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[14].wakeup_ports[1].bits.uop.lrs1 connect slots_14.io.wakeup_ports[1].bits.uop.ldst, issue_slots[14].wakeup_ports[1].bits.uop.ldst connect slots_14.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_14.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[1].bits.uop.csr_cmd connect slots_14.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[1].bits.uop.flush_on_commit connect slots_14.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[14].wakeup_ports[1].bits.uop.is_unique connect slots_14.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[14].wakeup_ports[1].bits.uop.uses_stq connect slots_14.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[1].bits.uop.uses_ldq connect slots_14.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[14].wakeup_ports[1].bits.uop.mem_signed connect slots_14.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[14].wakeup_ports[1].bits.uop.mem_size connect slots_14.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[1].bits.uop.mem_cmd connect slots_14.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[14].wakeup_ports[1].bits.uop.exc_cause connect slots_14.io.wakeup_ports[1].bits.uop.exception, issue_slots[14].wakeup_ports[1].bits.uop.exception connect slots_14.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[1].bits.uop.stale_pdst connect slots_14.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[1].bits.uop.ppred_busy connect slots_14.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[1].bits.uop.prs3_busy connect slots_14.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[1].bits.uop.prs2_busy connect slots_14.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[1].bits.uop.prs1_busy connect slots_14.io.wakeup_ports[1].bits.uop.ppred, issue_slots[14].wakeup_ports[1].bits.uop.ppred connect slots_14.io.wakeup_ports[1].bits.uop.prs3, issue_slots[14].wakeup_ports[1].bits.uop.prs3 connect slots_14.io.wakeup_ports[1].bits.uop.prs2, issue_slots[14].wakeup_ports[1].bits.uop.prs2 connect slots_14.io.wakeup_ports[1].bits.uop.prs1, issue_slots[14].wakeup_ports[1].bits.uop.prs1 connect slots_14.io.wakeup_ports[1].bits.uop.pdst, issue_slots[14].wakeup_ports[1].bits.uop.pdst connect slots_14.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[1].bits.uop.rxq_idx connect slots_14.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[14].wakeup_ports[1].bits.uop.stq_idx connect slots_14.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[1].bits.uop.ldq_idx connect slots_14.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[14].wakeup_ports[1].bits.uop.rob_idx connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_14.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[14].wakeup_ports[1].bits.uop.op2_sel connect slots_14.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[14].wakeup_ports[1].bits.uop.op1_sel connect slots_14.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[14].wakeup_ports[1].bits.uop.imm_packed connect slots_14.io.wakeup_ports[1].bits.uop.pimm, issue_slots[14].wakeup_ports[1].bits.uop.pimm connect slots_14.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[14].wakeup_ports[1].bits.uop.imm_sel connect slots_14.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[14].wakeup_ports[1].bits.uop.imm_rename connect slots_14.io.wakeup_ports[1].bits.uop.taken, issue_slots[14].wakeup_ports[1].bits.uop.taken connect slots_14.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[14].wakeup_ports[1].bits.uop.pc_lob connect slots_14.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[14].wakeup_ports[1].bits.uop.edge_inst connect slots_14.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[1].bits.uop.ftq_idx connect slots_14.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[14].wakeup_ports[1].bits.uop.is_mov connect slots_14.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[14].wakeup_ports[1].bits.uop.is_rocc connect slots_14.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_14.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[14].wakeup_ports[1].bits.uop.is_eret connect slots_14.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[14].wakeup_ports[1].bits.uop.is_amo connect slots_14.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[14].wakeup_ports[1].bits.uop.is_sfence connect slots_14.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[14].wakeup_ports[1].bits.uop.is_fencei connect slots_14.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[14].wakeup_ports[1].bits.uop.is_fence connect slots_14.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[14].wakeup_ports[1].bits.uop.is_sfb connect slots_14.io.wakeup_ports[1].bits.uop.br_type, issue_slots[14].wakeup_ports[1].bits.uop.br_type connect slots_14.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[14].wakeup_ports[1].bits.uop.br_tag connect slots_14.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[14].wakeup_ports[1].bits.uop.br_mask connect slots_14.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[1].bits.uop.dis_col_sel connect slots_14.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_14.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_14.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_14.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_14.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_14.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_14.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_14.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[14].wakeup_ports[1].bits.uop.iw_issued connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[0] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[1] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[2] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[3] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[4] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[5] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[6] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[7] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[8] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[9] connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[0] connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[1] connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[2] connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[3] connect slots_14.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[14].wakeup_ports[1].bits.uop.debug_pc connect slots_14.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[14].wakeup_ports[1].bits.uop.is_rvc connect slots_14.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[14].wakeup_ports[1].bits.uop.debug_inst connect slots_14.io.wakeup_ports[1].bits.uop.inst, issue_slots[14].wakeup_ports[1].bits.uop.inst connect slots_14.io.wakeup_ports[1].valid, issue_slots[14].wakeup_ports[1].valid connect slots_14.io.wakeup_ports[2].bits.rebusy, issue_slots[14].wakeup_ports[2].bits.rebusy connect slots_14.io.wakeup_ports[2].bits.speculative_mask, issue_slots[14].wakeup_ports[2].bits.speculative_mask connect slots_14.io.wakeup_ports[2].bits.bypassable, issue_slots[14].wakeup_ports[2].bits.bypassable connect slots_14.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[2].bits.uop.debug_tsrc connect slots_14.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[2].bits.uop.debug_fsrc connect slots_14.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_14.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[2].bits.uop.bp_debug_if connect slots_14.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_14.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_14.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_14.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[14].wakeup_ports[2].bits.uop.fp_typ connect slots_14.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[14].wakeup_ports[2].bits.uop.fp_rm connect slots_14.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[14].wakeup_ports[2].bits.uop.fp_val connect slots_14.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[14].wakeup_ports[2].bits.uop.fcn_op connect slots_14.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[2].bits.uop.fcn_dw connect slots_14.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[14].wakeup_ports[2].bits.uop.frs3_en connect slots_14.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_14.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_14.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[2].bits.uop.dst_rtype connect slots_14.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[14].wakeup_ports[2].bits.uop.lrs3 connect slots_14.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[14].wakeup_ports[2].bits.uop.lrs2 connect slots_14.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[14].wakeup_ports[2].bits.uop.lrs1 connect slots_14.io.wakeup_ports[2].bits.uop.ldst, issue_slots[14].wakeup_ports[2].bits.uop.ldst connect slots_14.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_14.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[2].bits.uop.csr_cmd connect slots_14.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[2].bits.uop.flush_on_commit connect slots_14.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[14].wakeup_ports[2].bits.uop.is_unique connect slots_14.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[14].wakeup_ports[2].bits.uop.uses_stq connect slots_14.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[2].bits.uop.uses_ldq connect slots_14.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[14].wakeup_ports[2].bits.uop.mem_signed connect slots_14.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[14].wakeup_ports[2].bits.uop.mem_size connect slots_14.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[2].bits.uop.mem_cmd connect slots_14.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[14].wakeup_ports[2].bits.uop.exc_cause connect slots_14.io.wakeup_ports[2].bits.uop.exception, issue_slots[14].wakeup_ports[2].bits.uop.exception connect slots_14.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[2].bits.uop.stale_pdst connect slots_14.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[2].bits.uop.ppred_busy connect slots_14.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[2].bits.uop.prs3_busy connect slots_14.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[2].bits.uop.prs2_busy connect slots_14.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[2].bits.uop.prs1_busy connect slots_14.io.wakeup_ports[2].bits.uop.ppred, issue_slots[14].wakeup_ports[2].bits.uop.ppred connect slots_14.io.wakeup_ports[2].bits.uop.prs3, issue_slots[14].wakeup_ports[2].bits.uop.prs3 connect slots_14.io.wakeup_ports[2].bits.uop.prs2, issue_slots[14].wakeup_ports[2].bits.uop.prs2 connect slots_14.io.wakeup_ports[2].bits.uop.prs1, issue_slots[14].wakeup_ports[2].bits.uop.prs1 connect slots_14.io.wakeup_ports[2].bits.uop.pdst, issue_slots[14].wakeup_ports[2].bits.uop.pdst connect slots_14.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[2].bits.uop.rxq_idx connect slots_14.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[14].wakeup_ports[2].bits.uop.stq_idx connect slots_14.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[2].bits.uop.ldq_idx connect slots_14.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[14].wakeup_ports[2].bits.uop.rob_idx connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_14.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[14].wakeup_ports[2].bits.uop.op2_sel connect slots_14.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[14].wakeup_ports[2].bits.uop.op1_sel connect slots_14.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[14].wakeup_ports[2].bits.uop.imm_packed connect slots_14.io.wakeup_ports[2].bits.uop.pimm, issue_slots[14].wakeup_ports[2].bits.uop.pimm connect slots_14.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[14].wakeup_ports[2].bits.uop.imm_sel connect slots_14.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[14].wakeup_ports[2].bits.uop.imm_rename connect slots_14.io.wakeup_ports[2].bits.uop.taken, issue_slots[14].wakeup_ports[2].bits.uop.taken connect slots_14.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[14].wakeup_ports[2].bits.uop.pc_lob connect slots_14.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[14].wakeup_ports[2].bits.uop.edge_inst connect slots_14.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[2].bits.uop.ftq_idx connect slots_14.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[14].wakeup_ports[2].bits.uop.is_mov connect slots_14.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[14].wakeup_ports[2].bits.uop.is_rocc connect slots_14.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_14.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[14].wakeup_ports[2].bits.uop.is_eret connect slots_14.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[14].wakeup_ports[2].bits.uop.is_amo connect slots_14.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[14].wakeup_ports[2].bits.uop.is_sfence connect slots_14.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[14].wakeup_ports[2].bits.uop.is_fencei connect slots_14.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[14].wakeup_ports[2].bits.uop.is_fence connect slots_14.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[14].wakeup_ports[2].bits.uop.is_sfb connect slots_14.io.wakeup_ports[2].bits.uop.br_type, issue_slots[14].wakeup_ports[2].bits.uop.br_type connect slots_14.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[14].wakeup_ports[2].bits.uop.br_tag connect slots_14.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[14].wakeup_ports[2].bits.uop.br_mask connect slots_14.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[2].bits.uop.dis_col_sel connect slots_14.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_14.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_14.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_14.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_14.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_14.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_14.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_14.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[14].wakeup_ports[2].bits.uop.iw_issued connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[0] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[1] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[2] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[3] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[4] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[5] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[6] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[7] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[8] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[9] connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[0] connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[1] connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[2] connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[3] connect slots_14.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[14].wakeup_ports[2].bits.uop.debug_pc connect slots_14.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[14].wakeup_ports[2].bits.uop.is_rvc connect slots_14.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[14].wakeup_ports[2].bits.uop.debug_inst connect slots_14.io.wakeup_ports[2].bits.uop.inst, issue_slots[14].wakeup_ports[2].bits.uop.inst connect slots_14.io.wakeup_ports[2].valid, issue_slots[14].wakeup_ports[2].valid connect slots_14.io.wakeup_ports[3].bits.rebusy, issue_slots[14].wakeup_ports[3].bits.rebusy connect slots_14.io.wakeup_ports[3].bits.speculative_mask, issue_slots[14].wakeup_ports[3].bits.speculative_mask connect slots_14.io.wakeup_ports[3].bits.bypassable, issue_slots[14].wakeup_ports[3].bits.bypassable connect slots_14.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[3].bits.uop.debug_tsrc connect slots_14.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[3].bits.uop.debug_fsrc connect slots_14.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_14.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[3].bits.uop.bp_debug_if connect slots_14.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_14.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_14.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_14.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[14].wakeup_ports[3].bits.uop.fp_typ connect slots_14.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[14].wakeup_ports[3].bits.uop.fp_rm connect slots_14.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[14].wakeup_ports[3].bits.uop.fp_val connect slots_14.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[14].wakeup_ports[3].bits.uop.fcn_op connect slots_14.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[3].bits.uop.fcn_dw connect slots_14.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[14].wakeup_ports[3].bits.uop.frs3_en connect slots_14.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_14.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_14.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[3].bits.uop.dst_rtype connect slots_14.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[14].wakeup_ports[3].bits.uop.lrs3 connect slots_14.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[14].wakeup_ports[3].bits.uop.lrs2 connect slots_14.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[14].wakeup_ports[3].bits.uop.lrs1 connect slots_14.io.wakeup_ports[3].bits.uop.ldst, issue_slots[14].wakeup_ports[3].bits.uop.ldst connect slots_14.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_14.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[3].bits.uop.csr_cmd connect slots_14.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[3].bits.uop.flush_on_commit connect slots_14.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[14].wakeup_ports[3].bits.uop.is_unique connect slots_14.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[14].wakeup_ports[3].bits.uop.uses_stq connect slots_14.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[3].bits.uop.uses_ldq connect slots_14.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[14].wakeup_ports[3].bits.uop.mem_signed connect slots_14.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[14].wakeup_ports[3].bits.uop.mem_size connect slots_14.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[3].bits.uop.mem_cmd connect slots_14.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[14].wakeup_ports[3].bits.uop.exc_cause connect slots_14.io.wakeup_ports[3].bits.uop.exception, issue_slots[14].wakeup_ports[3].bits.uop.exception connect slots_14.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[3].bits.uop.stale_pdst connect slots_14.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[3].bits.uop.ppred_busy connect slots_14.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[3].bits.uop.prs3_busy connect slots_14.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[3].bits.uop.prs2_busy connect slots_14.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[3].bits.uop.prs1_busy connect slots_14.io.wakeup_ports[3].bits.uop.ppred, issue_slots[14].wakeup_ports[3].bits.uop.ppred connect slots_14.io.wakeup_ports[3].bits.uop.prs3, issue_slots[14].wakeup_ports[3].bits.uop.prs3 connect slots_14.io.wakeup_ports[3].bits.uop.prs2, issue_slots[14].wakeup_ports[3].bits.uop.prs2 connect slots_14.io.wakeup_ports[3].bits.uop.prs1, issue_slots[14].wakeup_ports[3].bits.uop.prs1 connect slots_14.io.wakeup_ports[3].bits.uop.pdst, issue_slots[14].wakeup_ports[3].bits.uop.pdst connect slots_14.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[3].bits.uop.rxq_idx connect slots_14.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[14].wakeup_ports[3].bits.uop.stq_idx connect slots_14.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[3].bits.uop.ldq_idx connect slots_14.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[14].wakeup_ports[3].bits.uop.rob_idx connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_14.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[14].wakeup_ports[3].bits.uop.op2_sel connect slots_14.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[14].wakeup_ports[3].bits.uop.op1_sel connect slots_14.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[14].wakeup_ports[3].bits.uop.imm_packed connect slots_14.io.wakeup_ports[3].bits.uop.pimm, issue_slots[14].wakeup_ports[3].bits.uop.pimm connect slots_14.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[14].wakeup_ports[3].bits.uop.imm_sel connect slots_14.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[14].wakeup_ports[3].bits.uop.imm_rename connect slots_14.io.wakeup_ports[3].bits.uop.taken, issue_slots[14].wakeup_ports[3].bits.uop.taken connect slots_14.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[14].wakeup_ports[3].bits.uop.pc_lob connect slots_14.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[14].wakeup_ports[3].bits.uop.edge_inst connect slots_14.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[3].bits.uop.ftq_idx connect slots_14.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[14].wakeup_ports[3].bits.uop.is_mov connect slots_14.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[14].wakeup_ports[3].bits.uop.is_rocc connect slots_14.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_14.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[14].wakeup_ports[3].bits.uop.is_eret connect slots_14.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[14].wakeup_ports[3].bits.uop.is_amo connect slots_14.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[14].wakeup_ports[3].bits.uop.is_sfence connect slots_14.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[14].wakeup_ports[3].bits.uop.is_fencei connect slots_14.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[14].wakeup_ports[3].bits.uop.is_fence connect slots_14.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[14].wakeup_ports[3].bits.uop.is_sfb connect slots_14.io.wakeup_ports[3].bits.uop.br_type, issue_slots[14].wakeup_ports[3].bits.uop.br_type connect slots_14.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[14].wakeup_ports[3].bits.uop.br_tag connect slots_14.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[14].wakeup_ports[3].bits.uop.br_mask connect slots_14.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[3].bits.uop.dis_col_sel connect slots_14.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_14.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_14.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_14.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_14.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_14.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_14.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_14.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[14].wakeup_ports[3].bits.uop.iw_issued connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[0] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[1] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[2] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[3] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[4] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[5] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[6] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[7] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[8] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[9] connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[0] connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[1] connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[2] connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[3] connect slots_14.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[14].wakeup_ports[3].bits.uop.debug_pc connect slots_14.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[14].wakeup_ports[3].bits.uop.is_rvc connect slots_14.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[14].wakeup_ports[3].bits.uop.debug_inst connect slots_14.io.wakeup_ports[3].bits.uop.inst, issue_slots[14].wakeup_ports[3].bits.uop.inst connect slots_14.io.wakeup_ports[3].valid, issue_slots[14].wakeup_ports[3].valid connect slots_14.io.wakeup_ports[4].bits.rebusy, issue_slots[14].wakeup_ports[4].bits.rebusy connect slots_14.io.wakeup_ports[4].bits.speculative_mask, issue_slots[14].wakeup_ports[4].bits.speculative_mask connect slots_14.io.wakeup_ports[4].bits.bypassable, issue_slots[14].wakeup_ports[4].bits.bypassable connect slots_14.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[4].bits.uop.debug_tsrc connect slots_14.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[4].bits.uop.debug_fsrc connect slots_14.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_14.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[4].bits.uop.bp_debug_if connect slots_14.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_14.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_14.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_14.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[14].wakeup_ports[4].bits.uop.fp_typ connect slots_14.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[14].wakeup_ports[4].bits.uop.fp_rm connect slots_14.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[14].wakeup_ports[4].bits.uop.fp_val connect slots_14.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[14].wakeup_ports[4].bits.uop.fcn_op connect slots_14.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[4].bits.uop.fcn_dw connect slots_14.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[14].wakeup_ports[4].bits.uop.frs3_en connect slots_14.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_14.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_14.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[4].bits.uop.dst_rtype connect slots_14.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[14].wakeup_ports[4].bits.uop.lrs3 connect slots_14.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[14].wakeup_ports[4].bits.uop.lrs2 connect slots_14.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[14].wakeup_ports[4].bits.uop.lrs1 connect slots_14.io.wakeup_ports[4].bits.uop.ldst, issue_slots[14].wakeup_ports[4].bits.uop.ldst connect slots_14.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_14.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[4].bits.uop.csr_cmd connect slots_14.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[4].bits.uop.flush_on_commit connect slots_14.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[14].wakeup_ports[4].bits.uop.is_unique connect slots_14.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[14].wakeup_ports[4].bits.uop.uses_stq connect slots_14.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[4].bits.uop.uses_ldq connect slots_14.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[14].wakeup_ports[4].bits.uop.mem_signed connect slots_14.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[14].wakeup_ports[4].bits.uop.mem_size connect slots_14.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[4].bits.uop.mem_cmd connect slots_14.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[14].wakeup_ports[4].bits.uop.exc_cause connect slots_14.io.wakeup_ports[4].bits.uop.exception, issue_slots[14].wakeup_ports[4].bits.uop.exception connect slots_14.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[4].bits.uop.stale_pdst connect slots_14.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[4].bits.uop.ppred_busy connect slots_14.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[4].bits.uop.prs3_busy connect slots_14.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[4].bits.uop.prs2_busy connect slots_14.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[4].bits.uop.prs1_busy connect slots_14.io.wakeup_ports[4].bits.uop.ppred, issue_slots[14].wakeup_ports[4].bits.uop.ppred connect slots_14.io.wakeup_ports[4].bits.uop.prs3, issue_slots[14].wakeup_ports[4].bits.uop.prs3 connect slots_14.io.wakeup_ports[4].bits.uop.prs2, issue_slots[14].wakeup_ports[4].bits.uop.prs2 connect slots_14.io.wakeup_ports[4].bits.uop.prs1, issue_slots[14].wakeup_ports[4].bits.uop.prs1 connect slots_14.io.wakeup_ports[4].bits.uop.pdst, issue_slots[14].wakeup_ports[4].bits.uop.pdst connect slots_14.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[4].bits.uop.rxq_idx connect slots_14.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[14].wakeup_ports[4].bits.uop.stq_idx connect slots_14.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[4].bits.uop.ldq_idx connect slots_14.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[14].wakeup_ports[4].bits.uop.rob_idx connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_14.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[14].wakeup_ports[4].bits.uop.op2_sel connect slots_14.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[14].wakeup_ports[4].bits.uop.op1_sel connect slots_14.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[14].wakeup_ports[4].bits.uop.imm_packed connect slots_14.io.wakeup_ports[4].bits.uop.pimm, issue_slots[14].wakeup_ports[4].bits.uop.pimm connect slots_14.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[14].wakeup_ports[4].bits.uop.imm_sel connect slots_14.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[14].wakeup_ports[4].bits.uop.imm_rename connect slots_14.io.wakeup_ports[4].bits.uop.taken, issue_slots[14].wakeup_ports[4].bits.uop.taken connect slots_14.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[14].wakeup_ports[4].bits.uop.pc_lob connect slots_14.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[14].wakeup_ports[4].bits.uop.edge_inst connect slots_14.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[4].bits.uop.ftq_idx connect slots_14.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[14].wakeup_ports[4].bits.uop.is_mov connect slots_14.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[14].wakeup_ports[4].bits.uop.is_rocc connect slots_14.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_14.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[14].wakeup_ports[4].bits.uop.is_eret connect slots_14.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[14].wakeup_ports[4].bits.uop.is_amo connect slots_14.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[14].wakeup_ports[4].bits.uop.is_sfence connect slots_14.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[14].wakeup_ports[4].bits.uop.is_fencei connect slots_14.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[14].wakeup_ports[4].bits.uop.is_fence connect slots_14.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[14].wakeup_ports[4].bits.uop.is_sfb connect slots_14.io.wakeup_ports[4].bits.uop.br_type, issue_slots[14].wakeup_ports[4].bits.uop.br_type connect slots_14.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[14].wakeup_ports[4].bits.uop.br_tag connect slots_14.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[14].wakeup_ports[4].bits.uop.br_mask connect slots_14.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[4].bits.uop.dis_col_sel connect slots_14.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_14.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_14.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_14.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_14.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_14.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_14.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_14.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[14].wakeup_ports[4].bits.uop.iw_issued connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[0] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[1] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[2] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[3] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[4] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[5] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[6] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[7] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[8] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[9] connect slots_14.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[4].bits.uop.iq_type[0] connect slots_14.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[4].bits.uop.iq_type[1] connect slots_14.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[4].bits.uop.iq_type[2] connect slots_14.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[4].bits.uop.iq_type[3] connect slots_14.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[14].wakeup_ports[4].bits.uop.debug_pc connect slots_14.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[14].wakeup_ports[4].bits.uop.is_rvc connect slots_14.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[14].wakeup_ports[4].bits.uop.debug_inst connect slots_14.io.wakeup_ports[4].bits.uop.inst, issue_slots[14].wakeup_ports[4].bits.uop.inst connect slots_14.io.wakeup_ports[4].valid, issue_slots[14].wakeup_ports[4].valid connect slots_14.io.squash_grant, issue_slots[14].squash_grant connect slots_14.io.clear, issue_slots[14].clear connect slots_14.io.kill, issue_slots[14].kill connect slots_14.io.brupdate.b2.target_offset, issue_slots[14].brupdate.b2.target_offset connect slots_14.io.brupdate.b2.jalr_target, issue_slots[14].brupdate.b2.jalr_target connect slots_14.io.brupdate.b2.pc_sel, issue_slots[14].brupdate.b2.pc_sel connect slots_14.io.brupdate.b2.cfi_type, issue_slots[14].brupdate.b2.cfi_type connect slots_14.io.brupdate.b2.taken, issue_slots[14].brupdate.b2.taken connect slots_14.io.brupdate.b2.mispredict, issue_slots[14].brupdate.b2.mispredict connect slots_14.io.brupdate.b2.uop.debug_tsrc, issue_slots[14].brupdate.b2.uop.debug_tsrc connect slots_14.io.brupdate.b2.uop.debug_fsrc, issue_slots[14].brupdate.b2.uop.debug_fsrc connect slots_14.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[14].brupdate.b2.uop.bp_xcpt_if connect slots_14.io.brupdate.b2.uop.bp_debug_if, issue_slots[14].brupdate.b2.uop.bp_debug_if connect slots_14.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[14].brupdate.b2.uop.xcpt_ma_if connect slots_14.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[14].brupdate.b2.uop.xcpt_ae_if connect slots_14.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[14].brupdate.b2.uop.xcpt_pf_if connect slots_14.io.brupdate.b2.uop.fp_typ, issue_slots[14].brupdate.b2.uop.fp_typ connect slots_14.io.brupdate.b2.uop.fp_rm, issue_slots[14].brupdate.b2.uop.fp_rm connect slots_14.io.brupdate.b2.uop.fp_val, issue_slots[14].brupdate.b2.uop.fp_val connect slots_14.io.brupdate.b2.uop.fcn_op, issue_slots[14].brupdate.b2.uop.fcn_op connect slots_14.io.brupdate.b2.uop.fcn_dw, issue_slots[14].brupdate.b2.uop.fcn_dw connect slots_14.io.brupdate.b2.uop.frs3_en, issue_slots[14].brupdate.b2.uop.frs3_en connect slots_14.io.brupdate.b2.uop.lrs2_rtype, issue_slots[14].brupdate.b2.uop.lrs2_rtype connect slots_14.io.brupdate.b2.uop.lrs1_rtype, issue_slots[14].brupdate.b2.uop.lrs1_rtype connect slots_14.io.brupdate.b2.uop.dst_rtype, issue_slots[14].brupdate.b2.uop.dst_rtype connect slots_14.io.brupdate.b2.uop.lrs3, issue_slots[14].brupdate.b2.uop.lrs3 connect slots_14.io.brupdate.b2.uop.lrs2, issue_slots[14].brupdate.b2.uop.lrs2 connect slots_14.io.brupdate.b2.uop.lrs1, issue_slots[14].brupdate.b2.uop.lrs1 connect slots_14.io.brupdate.b2.uop.ldst, issue_slots[14].brupdate.b2.uop.ldst connect slots_14.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[14].brupdate.b2.uop.ldst_is_rs1 connect slots_14.io.brupdate.b2.uop.csr_cmd, issue_slots[14].brupdate.b2.uop.csr_cmd connect slots_14.io.brupdate.b2.uop.flush_on_commit, issue_slots[14].brupdate.b2.uop.flush_on_commit connect slots_14.io.brupdate.b2.uop.is_unique, issue_slots[14].brupdate.b2.uop.is_unique connect slots_14.io.brupdate.b2.uop.uses_stq, issue_slots[14].brupdate.b2.uop.uses_stq connect slots_14.io.brupdate.b2.uop.uses_ldq, issue_slots[14].brupdate.b2.uop.uses_ldq connect slots_14.io.brupdate.b2.uop.mem_signed, issue_slots[14].brupdate.b2.uop.mem_signed connect slots_14.io.brupdate.b2.uop.mem_size, issue_slots[14].brupdate.b2.uop.mem_size connect slots_14.io.brupdate.b2.uop.mem_cmd, issue_slots[14].brupdate.b2.uop.mem_cmd connect slots_14.io.brupdate.b2.uop.exc_cause, issue_slots[14].brupdate.b2.uop.exc_cause connect slots_14.io.brupdate.b2.uop.exception, issue_slots[14].brupdate.b2.uop.exception connect slots_14.io.brupdate.b2.uop.stale_pdst, issue_slots[14].brupdate.b2.uop.stale_pdst connect slots_14.io.brupdate.b2.uop.ppred_busy, issue_slots[14].brupdate.b2.uop.ppred_busy connect slots_14.io.brupdate.b2.uop.prs3_busy, issue_slots[14].brupdate.b2.uop.prs3_busy connect slots_14.io.brupdate.b2.uop.prs2_busy, issue_slots[14].brupdate.b2.uop.prs2_busy connect slots_14.io.brupdate.b2.uop.prs1_busy, issue_slots[14].brupdate.b2.uop.prs1_busy connect slots_14.io.brupdate.b2.uop.ppred, issue_slots[14].brupdate.b2.uop.ppred connect slots_14.io.brupdate.b2.uop.prs3, issue_slots[14].brupdate.b2.uop.prs3 connect slots_14.io.brupdate.b2.uop.prs2, issue_slots[14].brupdate.b2.uop.prs2 connect slots_14.io.brupdate.b2.uop.prs1, issue_slots[14].brupdate.b2.uop.prs1 connect slots_14.io.brupdate.b2.uop.pdst, issue_slots[14].brupdate.b2.uop.pdst connect slots_14.io.brupdate.b2.uop.rxq_idx, issue_slots[14].brupdate.b2.uop.rxq_idx connect slots_14.io.brupdate.b2.uop.stq_idx, issue_slots[14].brupdate.b2.uop.stq_idx connect slots_14.io.brupdate.b2.uop.ldq_idx, issue_slots[14].brupdate.b2.uop.ldq_idx connect slots_14.io.brupdate.b2.uop.rob_idx, issue_slots[14].brupdate.b2.uop.rob_idx connect slots_14.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[14].brupdate.b2.uop.fp_ctrl.vec connect slots_14.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[14].brupdate.b2.uop.fp_ctrl.wflags connect slots_14.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[14].brupdate.b2.uop.fp_ctrl.sqrt connect slots_14.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[14].brupdate.b2.uop.fp_ctrl.div connect slots_14.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[14].brupdate.b2.uop.fp_ctrl.fma connect slots_14.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[14].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_14.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[14].brupdate.b2.uop.fp_ctrl.toint connect slots_14.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[14].brupdate.b2.uop.fp_ctrl.fromint connect slots_14.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_14.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_14.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[14].brupdate.b2.uop.fp_ctrl.swap23 connect slots_14.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[14].brupdate.b2.uop.fp_ctrl.swap12 connect slots_14.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[14].brupdate.b2.uop.fp_ctrl.ren3 connect slots_14.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[14].brupdate.b2.uop.fp_ctrl.ren2 connect slots_14.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[14].brupdate.b2.uop.fp_ctrl.ren1 connect slots_14.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[14].brupdate.b2.uop.fp_ctrl.wen connect slots_14.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[14].brupdate.b2.uop.fp_ctrl.ldst connect slots_14.io.brupdate.b2.uop.op2_sel, issue_slots[14].brupdate.b2.uop.op2_sel connect slots_14.io.brupdate.b2.uop.op1_sel, issue_slots[14].brupdate.b2.uop.op1_sel connect slots_14.io.brupdate.b2.uop.imm_packed, issue_slots[14].brupdate.b2.uop.imm_packed connect slots_14.io.brupdate.b2.uop.pimm, issue_slots[14].brupdate.b2.uop.pimm connect slots_14.io.brupdate.b2.uop.imm_sel, issue_slots[14].brupdate.b2.uop.imm_sel connect slots_14.io.brupdate.b2.uop.imm_rename, issue_slots[14].brupdate.b2.uop.imm_rename connect slots_14.io.brupdate.b2.uop.taken, issue_slots[14].brupdate.b2.uop.taken connect slots_14.io.brupdate.b2.uop.pc_lob, issue_slots[14].brupdate.b2.uop.pc_lob connect slots_14.io.brupdate.b2.uop.edge_inst, issue_slots[14].brupdate.b2.uop.edge_inst connect slots_14.io.brupdate.b2.uop.ftq_idx, issue_slots[14].brupdate.b2.uop.ftq_idx connect slots_14.io.brupdate.b2.uop.is_mov, issue_slots[14].brupdate.b2.uop.is_mov connect slots_14.io.brupdate.b2.uop.is_rocc, issue_slots[14].brupdate.b2.uop.is_rocc connect slots_14.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[14].brupdate.b2.uop.is_sys_pc2epc connect slots_14.io.brupdate.b2.uop.is_eret, issue_slots[14].brupdate.b2.uop.is_eret connect slots_14.io.brupdate.b2.uop.is_amo, issue_slots[14].brupdate.b2.uop.is_amo connect slots_14.io.brupdate.b2.uop.is_sfence, issue_slots[14].brupdate.b2.uop.is_sfence connect slots_14.io.brupdate.b2.uop.is_fencei, issue_slots[14].brupdate.b2.uop.is_fencei connect slots_14.io.brupdate.b2.uop.is_fence, issue_slots[14].brupdate.b2.uop.is_fence connect slots_14.io.brupdate.b2.uop.is_sfb, issue_slots[14].brupdate.b2.uop.is_sfb connect slots_14.io.brupdate.b2.uop.br_type, issue_slots[14].brupdate.b2.uop.br_type connect slots_14.io.brupdate.b2.uop.br_tag, issue_slots[14].brupdate.b2.uop.br_tag connect slots_14.io.brupdate.b2.uop.br_mask, issue_slots[14].brupdate.b2.uop.br_mask connect slots_14.io.brupdate.b2.uop.dis_col_sel, issue_slots[14].brupdate.b2.uop.dis_col_sel connect slots_14.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[14].brupdate.b2.uop.iw_p3_bypass_hint connect slots_14.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[14].brupdate.b2.uop.iw_p2_bypass_hint connect slots_14.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[14].brupdate.b2.uop.iw_p1_bypass_hint connect slots_14.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[14].brupdate.b2.uop.iw_p2_speculative_child connect slots_14.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[14].brupdate.b2.uop.iw_p1_speculative_child connect slots_14.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[14].brupdate.b2.uop.iw_issued_partial_dgen connect slots_14.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[14].brupdate.b2.uop.iw_issued_partial_agen connect slots_14.io.brupdate.b2.uop.iw_issued, issue_slots[14].brupdate.b2.uop.iw_issued connect slots_14.io.brupdate.b2.uop.fu_code[0], issue_slots[14].brupdate.b2.uop.fu_code[0] connect slots_14.io.brupdate.b2.uop.fu_code[1], issue_slots[14].brupdate.b2.uop.fu_code[1] connect slots_14.io.brupdate.b2.uop.fu_code[2], issue_slots[14].brupdate.b2.uop.fu_code[2] connect slots_14.io.brupdate.b2.uop.fu_code[3], issue_slots[14].brupdate.b2.uop.fu_code[3] connect slots_14.io.brupdate.b2.uop.fu_code[4], issue_slots[14].brupdate.b2.uop.fu_code[4] connect slots_14.io.brupdate.b2.uop.fu_code[5], issue_slots[14].brupdate.b2.uop.fu_code[5] connect slots_14.io.brupdate.b2.uop.fu_code[6], issue_slots[14].brupdate.b2.uop.fu_code[6] connect slots_14.io.brupdate.b2.uop.fu_code[7], issue_slots[14].brupdate.b2.uop.fu_code[7] connect slots_14.io.brupdate.b2.uop.fu_code[8], issue_slots[14].brupdate.b2.uop.fu_code[8] connect slots_14.io.brupdate.b2.uop.fu_code[9], issue_slots[14].brupdate.b2.uop.fu_code[9] connect slots_14.io.brupdate.b2.uop.iq_type[0], issue_slots[14].brupdate.b2.uop.iq_type[0] connect slots_14.io.brupdate.b2.uop.iq_type[1], issue_slots[14].brupdate.b2.uop.iq_type[1] connect slots_14.io.brupdate.b2.uop.iq_type[2], issue_slots[14].brupdate.b2.uop.iq_type[2] connect slots_14.io.brupdate.b2.uop.iq_type[3], issue_slots[14].brupdate.b2.uop.iq_type[3] connect slots_14.io.brupdate.b2.uop.debug_pc, issue_slots[14].brupdate.b2.uop.debug_pc connect slots_14.io.brupdate.b2.uop.is_rvc, issue_slots[14].brupdate.b2.uop.is_rvc connect slots_14.io.brupdate.b2.uop.debug_inst, issue_slots[14].brupdate.b2.uop.debug_inst connect slots_14.io.brupdate.b2.uop.inst, issue_slots[14].brupdate.b2.uop.inst connect slots_14.io.brupdate.b1.mispredict_mask, issue_slots[14].brupdate.b1.mispredict_mask connect slots_14.io.brupdate.b1.resolve_mask, issue_slots[14].brupdate.b1.resolve_mask connect issue_slots[14].out_uop.debug_tsrc, slots_14.io.out_uop.debug_tsrc connect issue_slots[14].out_uop.debug_fsrc, slots_14.io.out_uop.debug_fsrc connect issue_slots[14].out_uop.bp_xcpt_if, slots_14.io.out_uop.bp_xcpt_if connect issue_slots[14].out_uop.bp_debug_if, slots_14.io.out_uop.bp_debug_if connect issue_slots[14].out_uop.xcpt_ma_if, slots_14.io.out_uop.xcpt_ma_if connect issue_slots[14].out_uop.xcpt_ae_if, slots_14.io.out_uop.xcpt_ae_if connect issue_slots[14].out_uop.xcpt_pf_if, slots_14.io.out_uop.xcpt_pf_if connect issue_slots[14].out_uop.fp_typ, slots_14.io.out_uop.fp_typ connect issue_slots[14].out_uop.fp_rm, slots_14.io.out_uop.fp_rm connect issue_slots[14].out_uop.fp_val, slots_14.io.out_uop.fp_val connect issue_slots[14].out_uop.fcn_op, slots_14.io.out_uop.fcn_op connect issue_slots[14].out_uop.fcn_dw, slots_14.io.out_uop.fcn_dw connect issue_slots[14].out_uop.frs3_en, slots_14.io.out_uop.frs3_en connect issue_slots[14].out_uop.lrs2_rtype, slots_14.io.out_uop.lrs2_rtype connect issue_slots[14].out_uop.lrs1_rtype, slots_14.io.out_uop.lrs1_rtype connect issue_slots[14].out_uop.dst_rtype, slots_14.io.out_uop.dst_rtype connect issue_slots[14].out_uop.lrs3, slots_14.io.out_uop.lrs3 connect issue_slots[14].out_uop.lrs2, slots_14.io.out_uop.lrs2 connect issue_slots[14].out_uop.lrs1, slots_14.io.out_uop.lrs1 connect issue_slots[14].out_uop.ldst, slots_14.io.out_uop.ldst connect issue_slots[14].out_uop.ldst_is_rs1, slots_14.io.out_uop.ldst_is_rs1 connect issue_slots[14].out_uop.csr_cmd, slots_14.io.out_uop.csr_cmd connect issue_slots[14].out_uop.flush_on_commit, slots_14.io.out_uop.flush_on_commit connect issue_slots[14].out_uop.is_unique, slots_14.io.out_uop.is_unique connect issue_slots[14].out_uop.uses_stq, slots_14.io.out_uop.uses_stq connect issue_slots[14].out_uop.uses_ldq, slots_14.io.out_uop.uses_ldq connect issue_slots[14].out_uop.mem_signed, slots_14.io.out_uop.mem_signed connect issue_slots[14].out_uop.mem_size, slots_14.io.out_uop.mem_size connect issue_slots[14].out_uop.mem_cmd, slots_14.io.out_uop.mem_cmd connect issue_slots[14].out_uop.exc_cause, slots_14.io.out_uop.exc_cause connect issue_slots[14].out_uop.exception, slots_14.io.out_uop.exception connect issue_slots[14].out_uop.stale_pdst, slots_14.io.out_uop.stale_pdst connect issue_slots[14].out_uop.ppred_busy, slots_14.io.out_uop.ppred_busy connect issue_slots[14].out_uop.prs3_busy, slots_14.io.out_uop.prs3_busy connect issue_slots[14].out_uop.prs2_busy, slots_14.io.out_uop.prs2_busy connect issue_slots[14].out_uop.prs1_busy, slots_14.io.out_uop.prs1_busy connect issue_slots[14].out_uop.ppred, slots_14.io.out_uop.ppred connect issue_slots[14].out_uop.prs3, slots_14.io.out_uop.prs3 connect issue_slots[14].out_uop.prs2, slots_14.io.out_uop.prs2 connect issue_slots[14].out_uop.prs1, slots_14.io.out_uop.prs1 connect issue_slots[14].out_uop.pdst, slots_14.io.out_uop.pdst connect issue_slots[14].out_uop.rxq_idx, slots_14.io.out_uop.rxq_idx connect issue_slots[14].out_uop.stq_idx, slots_14.io.out_uop.stq_idx connect issue_slots[14].out_uop.ldq_idx, slots_14.io.out_uop.ldq_idx connect issue_slots[14].out_uop.rob_idx, slots_14.io.out_uop.rob_idx connect issue_slots[14].out_uop.fp_ctrl.vec, slots_14.io.out_uop.fp_ctrl.vec connect issue_slots[14].out_uop.fp_ctrl.wflags, slots_14.io.out_uop.fp_ctrl.wflags connect issue_slots[14].out_uop.fp_ctrl.sqrt, slots_14.io.out_uop.fp_ctrl.sqrt connect issue_slots[14].out_uop.fp_ctrl.div, slots_14.io.out_uop.fp_ctrl.div connect issue_slots[14].out_uop.fp_ctrl.fma, slots_14.io.out_uop.fp_ctrl.fma connect issue_slots[14].out_uop.fp_ctrl.fastpipe, slots_14.io.out_uop.fp_ctrl.fastpipe connect issue_slots[14].out_uop.fp_ctrl.toint, slots_14.io.out_uop.fp_ctrl.toint connect issue_slots[14].out_uop.fp_ctrl.fromint, slots_14.io.out_uop.fp_ctrl.fromint connect issue_slots[14].out_uop.fp_ctrl.typeTagOut, slots_14.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[14].out_uop.fp_ctrl.typeTagIn, slots_14.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[14].out_uop.fp_ctrl.swap23, slots_14.io.out_uop.fp_ctrl.swap23 connect issue_slots[14].out_uop.fp_ctrl.swap12, slots_14.io.out_uop.fp_ctrl.swap12 connect issue_slots[14].out_uop.fp_ctrl.ren3, slots_14.io.out_uop.fp_ctrl.ren3 connect issue_slots[14].out_uop.fp_ctrl.ren2, slots_14.io.out_uop.fp_ctrl.ren2 connect issue_slots[14].out_uop.fp_ctrl.ren1, slots_14.io.out_uop.fp_ctrl.ren1 connect issue_slots[14].out_uop.fp_ctrl.wen, slots_14.io.out_uop.fp_ctrl.wen connect issue_slots[14].out_uop.fp_ctrl.ldst, slots_14.io.out_uop.fp_ctrl.ldst connect issue_slots[14].out_uop.op2_sel, slots_14.io.out_uop.op2_sel connect issue_slots[14].out_uop.op1_sel, slots_14.io.out_uop.op1_sel connect issue_slots[14].out_uop.imm_packed, slots_14.io.out_uop.imm_packed connect issue_slots[14].out_uop.pimm, slots_14.io.out_uop.pimm connect issue_slots[14].out_uop.imm_sel, slots_14.io.out_uop.imm_sel connect issue_slots[14].out_uop.imm_rename, slots_14.io.out_uop.imm_rename connect issue_slots[14].out_uop.taken, slots_14.io.out_uop.taken connect issue_slots[14].out_uop.pc_lob, slots_14.io.out_uop.pc_lob connect issue_slots[14].out_uop.edge_inst, slots_14.io.out_uop.edge_inst connect issue_slots[14].out_uop.ftq_idx, slots_14.io.out_uop.ftq_idx connect issue_slots[14].out_uop.is_mov, slots_14.io.out_uop.is_mov connect issue_slots[14].out_uop.is_rocc, slots_14.io.out_uop.is_rocc connect issue_slots[14].out_uop.is_sys_pc2epc, slots_14.io.out_uop.is_sys_pc2epc connect issue_slots[14].out_uop.is_eret, slots_14.io.out_uop.is_eret connect issue_slots[14].out_uop.is_amo, slots_14.io.out_uop.is_amo connect issue_slots[14].out_uop.is_sfence, slots_14.io.out_uop.is_sfence connect issue_slots[14].out_uop.is_fencei, slots_14.io.out_uop.is_fencei connect issue_slots[14].out_uop.is_fence, slots_14.io.out_uop.is_fence connect issue_slots[14].out_uop.is_sfb, slots_14.io.out_uop.is_sfb connect issue_slots[14].out_uop.br_type, slots_14.io.out_uop.br_type connect issue_slots[14].out_uop.br_tag, slots_14.io.out_uop.br_tag connect issue_slots[14].out_uop.br_mask, slots_14.io.out_uop.br_mask connect issue_slots[14].out_uop.dis_col_sel, slots_14.io.out_uop.dis_col_sel connect issue_slots[14].out_uop.iw_p3_bypass_hint, slots_14.io.out_uop.iw_p3_bypass_hint connect issue_slots[14].out_uop.iw_p2_bypass_hint, slots_14.io.out_uop.iw_p2_bypass_hint connect issue_slots[14].out_uop.iw_p1_bypass_hint, slots_14.io.out_uop.iw_p1_bypass_hint connect issue_slots[14].out_uop.iw_p2_speculative_child, slots_14.io.out_uop.iw_p2_speculative_child connect issue_slots[14].out_uop.iw_p1_speculative_child, slots_14.io.out_uop.iw_p1_speculative_child connect issue_slots[14].out_uop.iw_issued_partial_dgen, slots_14.io.out_uop.iw_issued_partial_dgen connect issue_slots[14].out_uop.iw_issued_partial_agen, slots_14.io.out_uop.iw_issued_partial_agen connect issue_slots[14].out_uop.iw_issued, slots_14.io.out_uop.iw_issued connect issue_slots[14].out_uop.fu_code[0], slots_14.io.out_uop.fu_code[0] connect issue_slots[14].out_uop.fu_code[1], slots_14.io.out_uop.fu_code[1] connect issue_slots[14].out_uop.fu_code[2], slots_14.io.out_uop.fu_code[2] connect issue_slots[14].out_uop.fu_code[3], slots_14.io.out_uop.fu_code[3] connect issue_slots[14].out_uop.fu_code[4], slots_14.io.out_uop.fu_code[4] connect issue_slots[14].out_uop.fu_code[5], slots_14.io.out_uop.fu_code[5] connect issue_slots[14].out_uop.fu_code[6], slots_14.io.out_uop.fu_code[6] connect issue_slots[14].out_uop.fu_code[7], slots_14.io.out_uop.fu_code[7] connect issue_slots[14].out_uop.fu_code[8], slots_14.io.out_uop.fu_code[8] connect issue_slots[14].out_uop.fu_code[9], slots_14.io.out_uop.fu_code[9] connect issue_slots[14].out_uop.iq_type[0], slots_14.io.out_uop.iq_type[0] connect issue_slots[14].out_uop.iq_type[1], slots_14.io.out_uop.iq_type[1] connect issue_slots[14].out_uop.iq_type[2], slots_14.io.out_uop.iq_type[2] connect issue_slots[14].out_uop.iq_type[3], slots_14.io.out_uop.iq_type[3] connect issue_slots[14].out_uop.debug_pc, slots_14.io.out_uop.debug_pc connect issue_slots[14].out_uop.is_rvc, slots_14.io.out_uop.is_rvc connect issue_slots[14].out_uop.debug_inst, slots_14.io.out_uop.debug_inst connect issue_slots[14].out_uop.inst, slots_14.io.out_uop.inst connect slots_14.io.in_uop.bits.debug_tsrc, issue_slots[14].in_uop.bits.debug_tsrc connect slots_14.io.in_uop.bits.debug_fsrc, issue_slots[14].in_uop.bits.debug_fsrc connect slots_14.io.in_uop.bits.bp_xcpt_if, issue_slots[14].in_uop.bits.bp_xcpt_if connect slots_14.io.in_uop.bits.bp_debug_if, issue_slots[14].in_uop.bits.bp_debug_if connect slots_14.io.in_uop.bits.xcpt_ma_if, issue_slots[14].in_uop.bits.xcpt_ma_if connect slots_14.io.in_uop.bits.xcpt_ae_if, issue_slots[14].in_uop.bits.xcpt_ae_if connect slots_14.io.in_uop.bits.xcpt_pf_if, issue_slots[14].in_uop.bits.xcpt_pf_if connect slots_14.io.in_uop.bits.fp_typ, issue_slots[14].in_uop.bits.fp_typ connect slots_14.io.in_uop.bits.fp_rm, issue_slots[14].in_uop.bits.fp_rm connect slots_14.io.in_uop.bits.fp_val, issue_slots[14].in_uop.bits.fp_val connect slots_14.io.in_uop.bits.fcn_op, issue_slots[14].in_uop.bits.fcn_op connect slots_14.io.in_uop.bits.fcn_dw, issue_slots[14].in_uop.bits.fcn_dw connect slots_14.io.in_uop.bits.frs3_en, issue_slots[14].in_uop.bits.frs3_en connect slots_14.io.in_uop.bits.lrs2_rtype, issue_slots[14].in_uop.bits.lrs2_rtype connect slots_14.io.in_uop.bits.lrs1_rtype, issue_slots[14].in_uop.bits.lrs1_rtype connect slots_14.io.in_uop.bits.dst_rtype, issue_slots[14].in_uop.bits.dst_rtype connect slots_14.io.in_uop.bits.lrs3, issue_slots[14].in_uop.bits.lrs3 connect slots_14.io.in_uop.bits.lrs2, issue_slots[14].in_uop.bits.lrs2 connect slots_14.io.in_uop.bits.lrs1, issue_slots[14].in_uop.bits.lrs1 connect slots_14.io.in_uop.bits.ldst, issue_slots[14].in_uop.bits.ldst connect slots_14.io.in_uop.bits.ldst_is_rs1, issue_slots[14].in_uop.bits.ldst_is_rs1 connect slots_14.io.in_uop.bits.csr_cmd, issue_slots[14].in_uop.bits.csr_cmd connect slots_14.io.in_uop.bits.flush_on_commit, issue_slots[14].in_uop.bits.flush_on_commit connect slots_14.io.in_uop.bits.is_unique, issue_slots[14].in_uop.bits.is_unique connect slots_14.io.in_uop.bits.uses_stq, issue_slots[14].in_uop.bits.uses_stq connect slots_14.io.in_uop.bits.uses_ldq, issue_slots[14].in_uop.bits.uses_ldq connect slots_14.io.in_uop.bits.mem_signed, issue_slots[14].in_uop.bits.mem_signed connect slots_14.io.in_uop.bits.mem_size, issue_slots[14].in_uop.bits.mem_size connect slots_14.io.in_uop.bits.mem_cmd, issue_slots[14].in_uop.bits.mem_cmd connect slots_14.io.in_uop.bits.exc_cause, issue_slots[14].in_uop.bits.exc_cause connect slots_14.io.in_uop.bits.exception, issue_slots[14].in_uop.bits.exception connect slots_14.io.in_uop.bits.stale_pdst, issue_slots[14].in_uop.bits.stale_pdst connect slots_14.io.in_uop.bits.ppred_busy, issue_slots[14].in_uop.bits.ppred_busy connect slots_14.io.in_uop.bits.prs3_busy, issue_slots[14].in_uop.bits.prs3_busy connect slots_14.io.in_uop.bits.prs2_busy, issue_slots[14].in_uop.bits.prs2_busy connect slots_14.io.in_uop.bits.prs1_busy, issue_slots[14].in_uop.bits.prs1_busy connect slots_14.io.in_uop.bits.ppred, issue_slots[14].in_uop.bits.ppred connect slots_14.io.in_uop.bits.prs3, issue_slots[14].in_uop.bits.prs3 connect slots_14.io.in_uop.bits.prs2, issue_slots[14].in_uop.bits.prs2 connect slots_14.io.in_uop.bits.prs1, issue_slots[14].in_uop.bits.prs1 connect slots_14.io.in_uop.bits.pdst, issue_slots[14].in_uop.bits.pdst connect slots_14.io.in_uop.bits.rxq_idx, issue_slots[14].in_uop.bits.rxq_idx connect slots_14.io.in_uop.bits.stq_idx, issue_slots[14].in_uop.bits.stq_idx connect slots_14.io.in_uop.bits.ldq_idx, issue_slots[14].in_uop.bits.ldq_idx connect slots_14.io.in_uop.bits.rob_idx, issue_slots[14].in_uop.bits.rob_idx connect slots_14.io.in_uop.bits.fp_ctrl.vec, issue_slots[14].in_uop.bits.fp_ctrl.vec connect slots_14.io.in_uop.bits.fp_ctrl.wflags, issue_slots[14].in_uop.bits.fp_ctrl.wflags connect slots_14.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[14].in_uop.bits.fp_ctrl.sqrt connect slots_14.io.in_uop.bits.fp_ctrl.div, issue_slots[14].in_uop.bits.fp_ctrl.div connect slots_14.io.in_uop.bits.fp_ctrl.fma, issue_slots[14].in_uop.bits.fp_ctrl.fma connect slots_14.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].in_uop.bits.fp_ctrl.fastpipe connect slots_14.io.in_uop.bits.fp_ctrl.toint, issue_slots[14].in_uop.bits.fp_ctrl.toint connect slots_14.io.in_uop.bits.fp_ctrl.fromint, issue_slots[14].in_uop.bits.fp_ctrl.fromint connect slots_14.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut connect slots_14.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn connect slots_14.io.in_uop.bits.fp_ctrl.swap23, issue_slots[14].in_uop.bits.fp_ctrl.swap23 connect slots_14.io.in_uop.bits.fp_ctrl.swap12, issue_slots[14].in_uop.bits.fp_ctrl.swap12 connect slots_14.io.in_uop.bits.fp_ctrl.ren3, issue_slots[14].in_uop.bits.fp_ctrl.ren3 connect slots_14.io.in_uop.bits.fp_ctrl.ren2, issue_slots[14].in_uop.bits.fp_ctrl.ren2 connect slots_14.io.in_uop.bits.fp_ctrl.ren1, issue_slots[14].in_uop.bits.fp_ctrl.ren1 connect slots_14.io.in_uop.bits.fp_ctrl.wen, issue_slots[14].in_uop.bits.fp_ctrl.wen connect slots_14.io.in_uop.bits.fp_ctrl.ldst, issue_slots[14].in_uop.bits.fp_ctrl.ldst connect slots_14.io.in_uop.bits.op2_sel, issue_slots[14].in_uop.bits.op2_sel connect slots_14.io.in_uop.bits.op1_sel, issue_slots[14].in_uop.bits.op1_sel connect slots_14.io.in_uop.bits.imm_packed, issue_slots[14].in_uop.bits.imm_packed connect slots_14.io.in_uop.bits.pimm, issue_slots[14].in_uop.bits.pimm connect slots_14.io.in_uop.bits.imm_sel, issue_slots[14].in_uop.bits.imm_sel connect slots_14.io.in_uop.bits.imm_rename, issue_slots[14].in_uop.bits.imm_rename connect slots_14.io.in_uop.bits.taken, issue_slots[14].in_uop.bits.taken connect slots_14.io.in_uop.bits.pc_lob, issue_slots[14].in_uop.bits.pc_lob connect slots_14.io.in_uop.bits.edge_inst, issue_slots[14].in_uop.bits.edge_inst connect slots_14.io.in_uop.bits.ftq_idx, issue_slots[14].in_uop.bits.ftq_idx connect slots_14.io.in_uop.bits.is_mov, issue_slots[14].in_uop.bits.is_mov connect slots_14.io.in_uop.bits.is_rocc, issue_slots[14].in_uop.bits.is_rocc connect slots_14.io.in_uop.bits.is_sys_pc2epc, issue_slots[14].in_uop.bits.is_sys_pc2epc connect slots_14.io.in_uop.bits.is_eret, issue_slots[14].in_uop.bits.is_eret connect slots_14.io.in_uop.bits.is_amo, issue_slots[14].in_uop.bits.is_amo connect slots_14.io.in_uop.bits.is_sfence, issue_slots[14].in_uop.bits.is_sfence connect slots_14.io.in_uop.bits.is_fencei, issue_slots[14].in_uop.bits.is_fencei connect slots_14.io.in_uop.bits.is_fence, issue_slots[14].in_uop.bits.is_fence connect slots_14.io.in_uop.bits.is_sfb, issue_slots[14].in_uop.bits.is_sfb connect slots_14.io.in_uop.bits.br_type, issue_slots[14].in_uop.bits.br_type connect slots_14.io.in_uop.bits.br_tag, issue_slots[14].in_uop.bits.br_tag connect slots_14.io.in_uop.bits.br_mask, issue_slots[14].in_uop.bits.br_mask connect slots_14.io.in_uop.bits.dis_col_sel, issue_slots[14].in_uop.bits.dis_col_sel connect slots_14.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[14].in_uop.bits.iw_p3_bypass_hint connect slots_14.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[14].in_uop.bits.iw_p2_bypass_hint connect slots_14.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[14].in_uop.bits.iw_p1_bypass_hint connect slots_14.io.in_uop.bits.iw_p2_speculative_child, issue_slots[14].in_uop.bits.iw_p2_speculative_child connect slots_14.io.in_uop.bits.iw_p1_speculative_child, issue_slots[14].in_uop.bits.iw_p1_speculative_child connect slots_14.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[14].in_uop.bits.iw_issued_partial_dgen connect slots_14.io.in_uop.bits.iw_issued_partial_agen, issue_slots[14].in_uop.bits.iw_issued_partial_agen connect slots_14.io.in_uop.bits.iw_issued, issue_slots[14].in_uop.bits.iw_issued connect slots_14.io.in_uop.bits.fu_code[0], issue_slots[14].in_uop.bits.fu_code[0] connect slots_14.io.in_uop.bits.fu_code[1], issue_slots[14].in_uop.bits.fu_code[1] connect slots_14.io.in_uop.bits.fu_code[2], issue_slots[14].in_uop.bits.fu_code[2] connect slots_14.io.in_uop.bits.fu_code[3], issue_slots[14].in_uop.bits.fu_code[3] connect slots_14.io.in_uop.bits.fu_code[4], issue_slots[14].in_uop.bits.fu_code[4] connect slots_14.io.in_uop.bits.fu_code[5], issue_slots[14].in_uop.bits.fu_code[5] connect slots_14.io.in_uop.bits.fu_code[6], issue_slots[14].in_uop.bits.fu_code[6] connect slots_14.io.in_uop.bits.fu_code[7], issue_slots[14].in_uop.bits.fu_code[7] connect slots_14.io.in_uop.bits.fu_code[8], issue_slots[14].in_uop.bits.fu_code[8] connect slots_14.io.in_uop.bits.fu_code[9], issue_slots[14].in_uop.bits.fu_code[9] connect slots_14.io.in_uop.bits.iq_type[0], issue_slots[14].in_uop.bits.iq_type[0] connect slots_14.io.in_uop.bits.iq_type[1], issue_slots[14].in_uop.bits.iq_type[1] connect slots_14.io.in_uop.bits.iq_type[2], issue_slots[14].in_uop.bits.iq_type[2] connect slots_14.io.in_uop.bits.iq_type[3], issue_slots[14].in_uop.bits.iq_type[3] connect slots_14.io.in_uop.bits.debug_pc, issue_slots[14].in_uop.bits.debug_pc connect slots_14.io.in_uop.bits.is_rvc, issue_slots[14].in_uop.bits.is_rvc connect slots_14.io.in_uop.bits.debug_inst, issue_slots[14].in_uop.bits.debug_inst connect slots_14.io.in_uop.bits.inst, issue_slots[14].in_uop.bits.inst connect slots_14.io.in_uop.valid, issue_slots[14].in_uop.valid connect issue_slots[14].iss_uop.debug_tsrc, slots_14.io.iss_uop.debug_tsrc connect issue_slots[14].iss_uop.debug_fsrc, slots_14.io.iss_uop.debug_fsrc connect issue_slots[14].iss_uop.bp_xcpt_if, slots_14.io.iss_uop.bp_xcpt_if connect issue_slots[14].iss_uop.bp_debug_if, slots_14.io.iss_uop.bp_debug_if connect issue_slots[14].iss_uop.xcpt_ma_if, slots_14.io.iss_uop.xcpt_ma_if connect issue_slots[14].iss_uop.xcpt_ae_if, slots_14.io.iss_uop.xcpt_ae_if connect issue_slots[14].iss_uop.xcpt_pf_if, slots_14.io.iss_uop.xcpt_pf_if connect issue_slots[14].iss_uop.fp_typ, slots_14.io.iss_uop.fp_typ connect issue_slots[14].iss_uop.fp_rm, slots_14.io.iss_uop.fp_rm connect issue_slots[14].iss_uop.fp_val, slots_14.io.iss_uop.fp_val connect issue_slots[14].iss_uop.fcn_op, slots_14.io.iss_uop.fcn_op connect issue_slots[14].iss_uop.fcn_dw, slots_14.io.iss_uop.fcn_dw connect issue_slots[14].iss_uop.frs3_en, slots_14.io.iss_uop.frs3_en connect issue_slots[14].iss_uop.lrs2_rtype, slots_14.io.iss_uop.lrs2_rtype connect issue_slots[14].iss_uop.lrs1_rtype, slots_14.io.iss_uop.lrs1_rtype connect issue_slots[14].iss_uop.dst_rtype, slots_14.io.iss_uop.dst_rtype connect issue_slots[14].iss_uop.lrs3, slots_14.io.iss_uop.lrs3 connect issue_slots[14].iss_uop.lrs2, slots_14.io.iss_uop.lrs2 connect issue_slots[14].iss_uop.lrs1, slots_14.io.iss_uop.lrs1 connect issue_slots[14].iss_uop.ldst, slots_14.io.iss_uop.ldst connect issue_slots[14].iss_uop.ldst_is_rs1, slots_14.io.iss_uop.ldst_is_rs1 connect issue_slots[14].iss_uop.csr_cmd, slots_14.io.iss_uop.csr_cmd connect issue_slots[14].iss_uop.flush_on_commit, slots_14.io.iss_uop.flush_on_commit connect issue_slots[14].iss_uop.is_unique, slots_14.io.iss_uop.is_unique connect issue_slots[14].iss_uop.uses_stq, slots_14.io.iss_uop.uses_stq connect issue_slots[14].iss_uop.uses_ldq, slots_14.io.iss_uop.uses_ldq connect issue_slots[14].iss_uop.mem_signed, slots_14.io.iss_uop.mem_signed connect issue_slots[14].iss_uop.mem_size, slots_14.io.iss_uop.mem_size connect issue_slots[14].iss_uop.mem_cmd, slots_14.io.iss_uop.mem_cmd connect issue_slots[14].iss_uop.exc_cause, slots_14.io.iss_uop.exc_cause connect issue_slots[14].iss_uop.exception, slots_14.io.iss_uop.exception connect issue_slots[14].iss_uop.stale_pdst, slots_14.io.iss_uop.stale_pdst connect issue_slots[14].iss_uop.ppred_busy, slots_14.io.iss_uop.ppred_busy connect issue_slots[14].iss_uop.prs3_busy, slots_14.io.iss_uop.prs3_busy connect issue_slots[14].iss_uop.prs2_busy, slots_14.io.iss_uop.prs2_busy connect issue_slots[14].iss_uop.prs1_busy, slots_14.io.iss_uop.prs1_busy connect issue_slots[14].iss_uop.ppred, slots_14.io.iss_uop.ppred connect issue_slots[14].iss_uop.prs3, slots_14.io.iss_uop.prs3 connect issue_slots[14].iss_uop.prs2, slots_14.io.iss_uop.prs2 connect issue_slots[14].iss_uop.prs1, slots_14.io.iss_uop.prs1 connect issue_slots[14].iss_uop.pdst, slots_14.io.iss_uop.pdst connect issue_slots[14].iss_uop.rxq_idx, slots_14.io.iss_uop.rxq_idx connect issue_slots[14].iss_uop.stq_idx, slots_14.io.iss_uop.stq_idx connect issue_slots[14].iss_uop.ldq_idx, slots_14.io.iss_uop.ldq_idx connect issue_slots[14].iss_uop.rob_idx, slots_14.io.iss_uop.rob_idx connect issue_slots[14].iss_uop.fp_ctrl.vec, slots_14.io.iss_uop.fp_ctrl.vec connect issue_slots[14].iss_uop.fp_ctrl.wflags, slots_14.io.iss_uop.fp_ctrl.wflags connect issue_slots[14].iss_uop.fp_ctrl.sqrt, slots_14.io.iss_uop.fp_ctrl.sqrt connect issue_slots[14].iss_uop.fp_ctrl.div, slots_14.io.iss_uop.fp_ctrl.div connect issue_slots[14].iss_uop.fp_ctrl.fma, slots_14.io.iss_uop.fp_ctrl.fma connect issue_slots[14].iss_uop.fp_ctrl.fastpipe, slots_14.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[14].iss_uop.fp_ctrl.toint, slots_14.io.iss_uop.fp_ctrl.toint connect issue_slots[14].iss_uop.fp_ctrl.fromint, slots_14.io.iss_uop.fp_ctrl.fromint connect issue_slots[14].iss_uop.fp_ctrl.typeTagOut, slots_14.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[14].iss_uop.fp_ctrl.typeTagIn, slots_14.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[14].iss_uop.fp_ctrl.swap23, slots_14.io.iss_uop.fp_ctrl.swap23 connect issue_slots[14].iss_uop.fp_ctrl.swap12, slots_14.io.iss_uop.fp_ctrl.swap12 connect issue_slots[14].iss_uop.fp_ctrl.ren3, slots_14.io.iss_uop.fp_ctrl.ren3 connect issue_slots[14].iss_uop.fp_ctrl.ren2, slots_14.io.iss_uop.fp_ctrl.ren2 connect issue_slots[14].iss_uop.fp_ctrl.ren1, slots_14.io.iss_uop.fp_ctrl.ren1 connect issue_slots[14].iss_uop.fp_ctrl.wen, slots_14.io.iss_uop.fp_ctrl.wen connect issue_slots[14].iss_uop.fp_ctrl.ldst, slots_14.io.iss_uop.fp_ctrl.ldst connect issue_slots[14].iss_uop.op2_sel, slots_14.io.iss_uop.op2_sel connect issue_slots[14].iss_uop.op1_sel, slots_14.io.iss_uop.op1_sel connect issue_slots[14].iss_uop.imm_packed, slots_14.io.iss_uop.imm_packed connect issue_slots[14].iss_uop.pimm, slots_14.io.iss_uop.pimm connect issue_slots[14].iss_uop.imm_sel, slots_14.io.iss_uop.imm_sel connect issue_slots[14].iss_uop.imm_rename, slots_14.io.iss_uop.imm_rename connect issue_slots[14].iss_uop.taken, slots_14.io.iss_uop.taken connect issue_slots[14].iss_uop.pc_lob, slots_14.io.iss_uop.pc_lob connect issue_slots[14].iss_uop.edge_inst, slots_14.io.iss_uop.edge_inst connect issue_slots[14].iss_uop.ftq_idx, slots_14.io.iss_uop.ftq_idx connect issue_slots[14].iss_uop.is_mov, slots_14.io.iss_uop.is_mov connect issue_slots[14].iss_uop.is_rocc, slots_14.io.iss_uop.is_rocc connect issue_slots[14].iss_uop.is_sys_pc2epc, slots_14.io.iss_uop.is_sys_pc2epc connect issue_slots[14].iss_uop.is_eret, slots_14.io.iss_uop.is_eret connect issue_slots[14].iss_uop.is_amo, slots_14.io.iss_uop.is_amo connect issue_slots[14].iss_uop.is_sfence, slots_14.io.iss_uop.is_sfence connect issue_slots[14].iss_uop.is_fencei, slots_14.io.iss_uop.is_fencei connect issue_slots[14].iss_uop.is_fence, slots_14.io.iss_uop.is_fence connect issue_slots[14].iss_uop.is_sfb, slots_14.io.iss_uop.is_sfb connect issue_slots[14].iss_uop.br_type, slots_14.io.iss_uop.br_type connect issue_slots[14].iss_uop.br_tag, slots_14.io.iss_uop.br_tag connect issue_slots[14].iss_uop.br_mask, slots_14.io.iss_uop.br_mask connect issue_slots[14].iss_uop.dis_col_sel, slots_14.io.iss_uop.dis_col_sel connect issue_slots[14].iss_uop.iw_p3_bypass_hint, slots_14.io.iss_uop.iw_p3_bypass_hint connect issue_slots[14].iss_uop.iw_p2_bypass_hint, slots_14.io.iss_uop.iw_p2_bypass_hint connect issue_slots[14].iss_uop.iw_p1_bypass_hint, slots_14.io.iss_uop.iw_p1_bypass_hint connect issue_slots[14].iss_uop.iw_p2_speculative_child, slots_14.io.iss_uop.iw_p2_speculative_child connect issue_slots[14].iss_uop.iw_p1_speculative_child, slots_14.io.iss_uop.iw_p1_speculative_child connect issue_slots[14].iss_uop.iw_issued_partial_dgen, slots_14.io.iss_uop.iw_issued_partial_dgen connect issue_slots[14].iss_uop.iw_issued_partial_agen, slots_14.io.iss_uop.iw_issued_partial_agen connect issue_slots[14].iss_uop.iw_issued, slots_14.io.iss_uop.iw_issued connect issue_slots[14].iss_uop.fu_code[0], slots_14.io.iss_uop.fu_code[0] connect issue_slots[14].iss_uop.fu_code[1], slots_14.io.iss_uop.fu_code[1] connect issue_slots[14].iss_uop.fu_code[2], slots_14.io.iss_uop.fu_code[2] connect issue_slots[14].iss_uop.fu_code[3], slots_14.io.iss_uop.fu_code[3] connect issue_slots[14].iss_uop.fu_code[4], slots_14.io.iss_uop.fu_code[4] connect issue_slots[14].iss_uop.fu_code[5], slots_14.io.iss_uop.fu_code[5] connect issue_slots[14].iss_uop.fu_code[6], slots_14.io.iss_uop.fu_code[6] connect issue_slots[14].iss_uop.fu_code[7], slots_14.io.iss_uop.fu_code[7] connect issue_slots[14].iss_uop.fu_code[8], slots_14.io.iss_uop.fu_code[8] connect issue_slots[14].iss_uop.fu_code[9], slots_14.io.iss_uop.fu_code[9] connect issue_slots[14].iss_uop.iq_type[0], slots_14.io.iss_uop.iq_type[0] connect issue_slots[14].iss_uop.iq_type[1], slots_14.io.iss_uop.iq_type[1] connect issue_slots[14].iss_uop.iq_type[2], slots_14.io.iss_uop.iq_type[2] connect issue_slots[14].iss_uop.iq_type[3], slots_14.io.iss_uop.iq_type[3] connect issue_slots[14].iss_uop.debug_pc, slots_14.io.iss_uop.debug_pc connect issue_slots[14].iss_uop.is_rvc, slots_14.io.iss_uop.is_rvc connect issue_slots[14].iss_uop.debug_inst, slots_14.io.iss_uop.debug_inst connect issue_slots[14].iss_uop.inst, slots_14.io.iss_uop.inst connect slots_14.io.grant, issue_slots[14].grant connect issue_slots[14].request, slots_14.io.request connect issue_slots[14].will_be_valid, slots_14.io.will_be_valid connect issue_slots[14].valid, slots_14.io.valid connect slots_15.io.child_rebusys, issue_slots[15].child_rebusys connect slots_15.io.pred_wakeup_port.bits, issue_slots[15].pred_wakeup_port.bits connect slots_15.io.pred_wakeup_port.valid, issue_slots[15].pred_wakeup_port.valid connect slots_15.io.wakeup_ports[0].bits.rebusy, issue_slots[15].wakeup_ports[0].bits.rebusy connect slots_15.io.wakeup_ports[0].bits.speculative_mask, issue_slots[15].wakeup_ports[0].bits.speculative_mask connect slots_15.io.wakeup_ports[0].bits.bypassable, issue_slots[15].wakeup_ports[0].bits.bypassable connect slots_15.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[0].bits.uop.debug_tsrc connect slots_15.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[0].bits.uop.debug_fsrc connect slots_15.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_15.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[0].bits.uop.bp_debug_if connect slots_15.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_15.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_15.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_15.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[15].wakeup_ports[0].bits.uop.fp_typ connect slots_15.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[15].wakeup_ports[0].bits.uop.fp_rm connect slots_15.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[15].wakeup_ports[0].bits.uop.fp_val connect slots_15.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[15].wakeup_ports[0].bits.uop.fcn_op connect slots_15.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[0].bits.uop.fcn_dw connect slots_15.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[15].wakeup_ports[0].bits.uop.frs3_en connect slots_15.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_15.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_15.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[0].bits.uop.dst_rtype connect slots_15.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[15].wakeup_ports[0].bits.uop.lrs3 connect slots_15.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[15].wakeup_ports[0].bits.uop.lrs2 connect slots_15.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[15].wakeup_ports[0].bits.uop.lrs1 connect slots_15.io.wakeup_ports[0].bits.uop.ldst, issue_slots[15].wakeup_ports[0].bits.uop.ldst connect slots_15.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_15.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[0].bits.uop.csr_cmd connect slots_15.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[0].bits.uop.flush_on_commit connect slots_15.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[15].wakeup_ports[0].bits.uop.is_unique connect slots_15.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[15].wakeup_ports[0].bits.uop.uses_stq connect slots_15.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[0].bits.uop.uses_ldq connect slots_15.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[15].wakeup_ports[0].bits.uop.mem_signed connect slots_15.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[15].wakeup_ports[0].bits.uop.mem_size connect slots_15.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[0].bits.uop.mem_cmd connect slots_15.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[15].wakeup_ports[0].bits.uop.exc_cause connect slots_15.io.wakeup_ports[0].bits.uop.exception, issue_slots[15].wakeup_ports[0].bits.uop.exception connect slots_15.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[0].bits.uop.stale_pdst connect slots_15.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[0].bits.uop.ppred_busy connect slots_15.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[0].bits.uop.prs3_busy connect slots_15.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[0].bits.uop.prs2_busy connect slots_15.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[0].bits.uop.prs1_busy connect slots_15.io.wakeup_ports[0].bits.uop.ppred, issue_slots[15].wakeup_ports[0].bits.uop.ppred connect slots_15.io.wakeup_ports[0].bits.uop.prs3, issue_slots[15].wakeup_ports[0].bits.uop.prs3 connect slots_15.io.wakeup_ports[0].bits.uop.prs2, issue_slots[15].wakeup_ports[0].bits.uop.prs2 connect slots_15.io.wakeup_ports[0].bits.uop.prs1, issue_slots[15].wakeup_ports[0].bits.uop.prs1 connect slots_15.io.wakeup_ports[0].bits.uop.pdst, issue_slots[15].wakeup_ports[0].bits.uop.pdst connect slots_15.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[0].bits.uop.rxq_idx connect slots_15.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[15].wakeup_ports[0].bits.uop.stq_idx connect slots_15.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[0].bits.uop.ldq_idx connect slots_15.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[15].wakeup_ports[0].bits.uop.rob_idx connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_15.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[15].wakeup_ports[0].bits.uop.op2_sel connect slots_15.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[15].wakeup_ports[0].bits.uop.op1_sel connect slots_15.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[15].wakeup_ports[0].bits.uop.imm_packed connect slots_15.io.wakeup_ports[0].bits.uop.pimm, issue_slots[15].wakeup_ports[0].bits.uop.pimm connect slots_15.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[15].wakeup_ports[0].bits.uop.imm_sel connect slots_15.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[15].wakeup_ports[0].bits.uop.imm_rename connect slots_15.io.wakeup_ports[0].bits.uop.taken, issue_slots[15].wakeup_ports[0].bits.uop.taken connect slots_15.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[15].wakeup_ports[0].bits.uop.pc_lob connect slots_15.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[15].wakeup_ports[0].bits.uop.edge_inst connect slots_15.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[0].bits.uop.ftq_idx connect slots_15.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[15].wakeup_ports[0].bits.uop.is_mov connect slots_15.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[15].wakeup_ports[0].bits.uop.is_rocc connect slots_15.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_15.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[15].wakeup_ports[0].bits.uop.is_eret connect slots_15.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[15].wakeup_ports[0].bits.uop.is_amo connect slots_15.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[15].wakeup_ports[0].bits.uop.is_sfence connect slots_15.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[15].wakeup_ports[0].bits.uop.is_fencei connect slots_15.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[15].wakeup_ports[0].bits.uop.is_fence connect slots_15.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[15].wakeup_ports[0].bits.uop.is_sfb connect slots_15.io.wakeup_ports[0].bits.uop.br_type, issue_slots[15].wakeup_ports[0].bits.uop.br_type connect slots_15.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[15].wakeup_ports[0].bits.uop.br_tag connect slots_15.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[15].wakeup_ports[0].bits.uop.br_mask connect slots_15.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[0].bits.uop.dis_col_sel connect slots_15.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_15.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_15.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_15.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_15.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_15.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_15.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_15.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[15].wakeup_ports[0].bits.uop.iw_issued connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[0] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[1] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[2] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[3] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[4] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[5] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[6] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[7] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[8] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[9] connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[0] connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[1] connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[2] connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[3] connect slots_15.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[15].wakeup_ports[0].bits.uop.debug_pc connect slots_15.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[15].wakeup_ports[0].bits.uop.is_rvc connect slots_15.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[15].wakeup_ports[0].bits.uop.debug_inst connect slots_15.io.wakeup_ports[0].bits.uop.inst, issue_slots[15].wakeup_ports[0].bits.uop.inst connect slots_15.io.wakeup_ports[0].valid, issue_slots[15].wakeup_ports[0].valid connect slots_15.io.wakeup_ports[1].bits.rebusy, issue_slots[15].wakeup_ports[1].bits.rebusy connect slots_15.io.wakeup_ports[1].bits.speculative_mask, issue_slots[15].wakeup_ports[1].bits.speculative_mask connect slots_15.io.wakeup_ports[1].bits.bypassable, issue_slots[15].wakeup_ports[1].bits.bypassable connect slots_15.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[1].bits.uop.debug_tsrc connect slots_15.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[1].bits.uop.debug_fsrc connect slots_15.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_15.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[1].bits.uop.bp_debug_if connect slots_15.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_15.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_15.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_15.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[15].wakeup_ports[1].bits.uop.fp_typ connect slots_15.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[15].wakeup_ports[1].bits.uop.fp_rm connect slots_15.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[15].wakeup_ports[1].bits.uop.fp_val connect slots_15.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[15].wakeup_ports[1].bits.uop.fcn_op connect slots_15.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[1].bits.uop.fcn_dw connect slots_15.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[15].wakeup_ports[1].bits.uop.frs3_en connect slots_15.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_15.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_15.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[1].bits.uop.dst_rtype connect slots_15.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[15].wakeup_ports[1].bits.uop.lrs3 connect slots_15.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[15].wakeup_ports[1].bits.uop.lrs2 connect slots_15.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[15].wakeup_ports[1].bits.uop.lrs1 connect slots_15.io.wakeup_ports[1].bits.uop.ldst, issue_slots[15].wakeup_ports[1].bits.uop.ldst connect slots_15.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_15.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[1].bits.uop.csr_cmd connect slots_15.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[1].bits.uop.flush_on_commit connect slots_15.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[15].wakeup_ports[1].bits.uop.is_unique connect slots_15.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[15].wakeup_ports[1].bits.uop.uses_stq connect slots_15.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[1].bits.uop.uses_ldq connect slots_15.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[15].wakeup_ports[1].bits.uop.mem_signed connect slots_15.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[15].wakeup_ports[1].bits.uop.mem_size connect slots_15.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[1].bits.uop.mem_cmd connect slots_15.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[15].wakeup_ports[1].bits.uop.exc_cause connect slots_15.io.wakeup_ports[1].bits.uop.exception, issue_slots[15].wakeup_ports[1].bits.uop.exception connect slots_15.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[1].bits.uop.stale_pdst connect slots_15.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[1].bits.uop.ppred_busy connect slots_15.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[1].bits.uop.prs3_busy connect slots_15.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[1].bits.uop.prs2_busy connect slots_15.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[1].bits.uop.prs1_busy connect slots_15.io.wakeup_ports[1].bits.uop.ppred, issue_slots[15].wakeup_ports[1].bits.uop.ppred connect slots_15.io.wakeup_ports[1].bits.uop.prs3, issue_slots[15].wakeup_ports[1].bits.uop.prs3 connect slots_15.io.wakeup_ports[1].bits.uop.prs2, issue_slots[15].wakeup_ports[1].bits.uop.prs2 connect slots_15.io.wakeup_ports[1].bits.uop.prs1, issue_slots[15].wakeup_ports[1].bits.uop.prs1 connect slots_15.io.wakeup_ports[1].bits.uop.pdst, issue_slots[15].wakeup_ports[1].bits.uop.pdst connect slots_15.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[1].bits.uop.rxq_idx connect slots_15.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[15].wakeup_ports[1].bits.uop.stq_idx connect slots_15.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[1].bits.uop.ldq_idx connect slots_15.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[15].wakeup_ports[1].bits.uop.rob_idx connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_15.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[15].wakeup_ports[1].bits.uop.op2_sel connect slots_15.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[15].wakeup_ports[1].bits.uop.op1_sel connect slots_15.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[15].wakeup_ports[1].bits.uop.imm_packed connect slots_15.io.wakeup_ports[1].bits.uop.pimm, issue_slots[15].wakeup_ports[1].bits.uop.pimm connect slots_15.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[15].wakeup_ports[1].bits.uop.imm_sel connect slots_15.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[15].wakeup_ports[1].bits.uop.imm_rename connect slots_15.io.wakeup_ports[1].bits.uop.taken, issue_slots[15].wakeup_ports[1].bits.uop.taken connect slots_15.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[15].wakeup_ports[1].bits.uop.pc_lob connect slots_15.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[15].wakeup_ports[1].bits.uop.edge_inst connect slots_15.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[1].bits.uop.ftq_idx connect slots_15.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[15].wakeup_ports[1].bits.uop.is_mov connect slots_15.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[15].wakeup_ports[1].bits.uop.is_rocc connect slots_15.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_15.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[15].wakeup_ports[1].bits.uop.is_eret connect slots_15.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[15].wakeup_ports[1].bits.uop.is_amo connect slots_15.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[15].wakeup_ports[1].bits.uop.is_sfence connect slots_15.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[15].wakeup_ports[1].bits.uop.is_fencei connect slots_15.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[15].wakeup_ports[1].bits.uop.is_fence connect slots_15.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[15].wakeup_ports[1].bits.uop.is_sfb connect slots_15.io.wakeup_ports[1].bits.uop.br_type, issue_slots[15].wakeup_ports[1].bits.uop.br_type connect slots_15.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[15].wakeup_ports[1].bits.uop.br_tag connect slots_15.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[15].wakeup_ports[1].bits.uop.br_mask connect slots_15.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[1].bits.uop.dis_col_sel connect slots_15.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_15.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_15.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_15.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_15.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_15.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_15.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_15.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[15].wakeup_ports[1].bits.uop.iw_issued connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[0] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[1] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[2] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[3] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[4] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[5] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[6] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[7] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[8] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[9] connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[0] connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[1] connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[2] connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[3] connect slots_15.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[15].wakeup_ports[1].bits.uop.debug_pc connect slots_15.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[15].wakeup_ports[1].bits.uop.is_rvc connect slots_15.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[15].wakeup_ports[1].bits.uop.debug_inst connect slots_15.io.wakeup_ports[1].bits.uop.inst, issue_slots[15].wakeup_ports[1].bits.uop.inst connect slots_15.io.wakeup_ports[1].valid, issue_slots[15].wakeup_ports[1].valid connect slots_15.io.wakeup_ports[2].bits.rebusy, issue_slots[15].wakeup_ports[2].bits.rebusy connect slots_15.io.wakeup_ports[2].bits.speculative_mask, issue_slots[15].wakeup_ports[2].bits.speculative_mask connect slots_15.io.wakeup_ports[2].bits.bypassable, issue_slots[15].wakeup_ports[2].bits.bypassable connect slots_15.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[2].bits.uop.debug_tsrc connect slots_15.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[2].bits.uop.debug_fsrc connect slots_15.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_15.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[2].bits.uop.bp_debug_if connect slots_15.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_15.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_15.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_15.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[15].wakeup_ports[2].bits.uop.fp_typ connect slots_15.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[15].wakeup_ports[2].bits.uop.fp_rm connect slots_15.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[15].wakeup_ports[2].bits.uop.fp_val connect slots_15.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[15].wakeup_ports[2].bits.uop.fcn_op connect slots_15.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[2].bits.uop.fcn_dw connect slots_15.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[15].wakeup_ports[2].bits.uop.frs3_en connect slots_15.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_15.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_15.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[2].bits.uop.dst_rtype connect slots_15.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[15].wakeup_ports[2].bits.uop.lrs3 connect slots_15.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[15].wakeup_ports[2].bits.uop.lrs2 connect slots_15.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[15].wakeup_ports[2].bits.uop.lrs1 connect slots_15.io.wakeup_ports[2].bits.uop.ldst, issue_slots[15].wakeup_ports[2].bits.uop.ldst connect slots_15.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_15.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[2].bits.uop.csr_cmd connect slots_15.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[2].bits.uop.flush_on_commit connect slots_15.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[15].wakeup_ports[2].bits.uop.is_unique connect slots_15.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[15].wakeup_ports[2].bits.uop.uses_stq connect slots_15.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[2].bits.uop.uses_ldq connect slots_15.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[15].wakeup_ports[2].bits.uop.mem_signed connect slots_15.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[15].wakeup_ports[2].bits.uop.mem_size connect slots_15.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[2].bits.uop.mem_cmd connect slots_15.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[15].wakeup_ports[2].bits.uop.exc_cause connect slots_15.io.wakeup_ports[2].bits.uop.exception, issue_slots[15].wakeup_ports[2].bits.uop.exception connect slots_15.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[2].bits.uop.stale_pdst connect slots_15.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[2].bits.uop.ppred_busy connect slots_15.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[2].bits.uop.prs3_busy connect slots_15.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[2].bits.uop.prs2_busy connect slots_15.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[2].bits.uop.prs1_busy connect slots_15.io.wakeup_ports[2].bits.uop.ppred, issue_slots[15].wakeup_ports[2].bits.uop.ppred connect slots_15.io.wakeup_ports[2].bits.uop.prs3, issue_slots[15].wakeup_ports[2].bits.uop.prs3 connect slots_15.io.wakeup_ports[2].bits.uop.prs2, issue_slots[15].wakeup_ports[2].bits.uop.prs2 connect slots_15.io.wakeup_ports[2].bits.uop.prs1, issue_slots[15].wakeup_ports[2].bits.uop.prs1 connect slots_15.io.wakeup_ports[2].bits.uop.pdst, issue_slots[15].wakeup_ports[2].bits.uop.pdst connect slots_15.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[2].bits.uop.rxq_idx connect slots_15.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[15].wakeup_ports[2].bits.uop.stq_idx connect slots_15.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[2].bits.uop.ldq_idx connect slots_15.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[15].wakeup_ports[2].bits.uop.rob_idx connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_15.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[15].wakeup_ports[2].bits.uop.op2_sel connect slots_15.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[15].wakeup_ports[2].bits.uop.op1_sel connect slots_15.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[15].wakeup_ports[2].bits.uop.imm_packed connect slots_15.io.wakeup_ports[2].bits.uop.pimm, issue_slots[15].wakeup_ports[2].bits.uop.pimm connect slots_15.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[15].wakeup_ports[2].bits.uop.imm_sel connect slots_15.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[15].wakeup_ports[2].bits.uop.imm_rename connect slots_15.io.wakeup_ports[2].bits.uop.taken, issue_slots[15].wakeup_ports[2].bits.uop.taken connect slots_15.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[15].wakeup_ports[2].bits.uop.pc_lob connect slots_15.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[15].wakeup_ports[2].bits.uop.edge_inst connect slots_15.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[2].bits.uop.ftq_idx connect slots_15.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[15].wakeup_ports[2].bits.uop.is_mov connect slots_15.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[15].wakeup_ports[2].bits.uop.is_rocc connect slots_15.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_15.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[15].wakeup_ports[2].bits.uop.is_eret connect slots_15.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[15].wakeup_ports[2].bits.uop.is_amo connect slots_15.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[15].wakeup_ports[2].bits.uop.is_sfence connect slots_15.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[15].wakeup_ports[2].bits.uop.is_fencei connect slots_15.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[15].wakeup_ports[2].bits.uop.is_fence connect slots_15.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[15].wakeup_ports[2].bits.uop.is_sfb connect slots_15.io.wakeup_ports[2].bits.uop.br_type, issue_slots[15].wakeup_ports[2].bits.uop.br_type connect slots_15.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[15].wakeup_ports[2].bits.uop.br_tag connect slots_15.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[15].wakeup_ports[2].bits.uop.br_mask connect slots_15.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[2].bits.uop.dis_col_sel connect slots_15.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_15.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_15.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_15.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_15.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_15.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_15.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_15.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[15].wakeup_ports[2].bits.uop.iw_issued connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[0] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[1] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[2] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[3] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[4] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[5] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[6] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[7] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[8] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[9] connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[0] connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[1] connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[2] connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[3] connect slots_15.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[15].wakeup_ports[2].bits.uop.debug_pc connect slots_15.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[15].wakeup_ports[2].bits.uop.is_rvc connect slots_15.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[15].wakeup_ports[2].bits.uop.debug_inst connect slots_15.io.wakeup_ports[2].bits.uop.inst, issue_slots[15].wakeup_ports[2].bits.uop.inst connect slots_15.io.wakeup_ports[2].valid, issue_slots[15].wakeup_ports[2].valid connect slots_15.io.wakeup_ports[3].bits.rebusy, issue_slots[15].wakeup_ports[3].bits.rebusy connect slots_15.io.wakeup_ports[3].bits.speculative_mask, issue_slots[15].wakeup_ports[3].bits.speculative_mask connect slots_15.io.wakeup_ports[3].bits.bypassable, issue_slots[15].wakeup_ports[3].bits.bypassable connect slots_15.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[3].bits.uop.debug_tsrc connect slots_15.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[3].bits.uop.debug_fsrc connect slots_15.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_15.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[3].bits.uop.bp_debug_if connect slots_15.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_15.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_15.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_15.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[15].wakeup_ports[3].bits.uop.fp_typ connect slots_15.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[15].wakeup_ports[3].bits.uop.fp_rm connect slots_15.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[15].wakeup_ports[3].bits.uop.fp_val connect slots_15.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[15].wakeup_ports[3].bits.uop.fcn_op connect slots_15.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[3].bits.uop.fcn_dw connect slots_15.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[15].wakeup_ports[3].bits.uop.frs3_en connect slots_15.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_15.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_15.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[3].bits.uop.dst_rtype connect slots_15.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[15].wakeup_ports[3].bits.uop.lrs3 connect slots_15.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[15].wakeup_ports[3].bits.uop.lrs2 connect slots_15.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[15].wakeup_ports[3].bits.uop.lrs1 connect slots_15.io.wakeup_ports[3].bits.uop.ldst, issue_slots[15].wakeup_ports[3].bits.uop.ldst connect slots_15.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_15.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[3].bits.uop.csr_cmd connect slots_15.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[3].bits.uop.flush_on_commit connect slots_15.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[15].wakeup_ports[3].bits.uop.is_unique connect slots_15.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[15].wakeup_ports[3].bits.uop.uses_stq connect slots_15.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[3].bits.uop.uses_ldq connect slots_15.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[15].wakeup_ports[3].bits.uop.mem_signed connect slots_15.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[15].wakeup_ports[3].bits.uop.mem_size connect slots_15.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[3].bits.uop.mem_cmd connect slots_15.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[15].wakeup_ports[3].bits.uop.exc_cause connect slots_15.io.wakeup_ports[3].bits.uop.exception, issue_slots[15].wakeup_ports[3].bits.uop.exception connect slots_15.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[3].bits.uop.stale_pdst connect slots_15.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[3].bits.uop.ppred_busy connect slots_15.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[3].bits.uop.prs3_busy connect slots_15.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[3].bits.uop.prs2_busy connect slots_15.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[3].bits.uop.prs1_busy connect slots_15.io.wakeup_ports[3].bits.uop.ppred, issue_slots[15].wakeup_ports[3].bits.uop.ppred connect slots_15.io.wakeup_ports[3].bits.uop.prs3, issue_slots[15].wakeup_ports[3].bits.uop.prs3 connect slots_15.io.wakeup_ports[3].bits.uop.prs2, issue_slots[15].wakeup_ports[3].bits.uop.prs2 connect slots_15.io.wakeup_ports[3].bits.uop.prs1, issue_slots[15].wakeup_ports[3].bits.uop.prs1 connect slots_15.io.wakeup_ports[3].bits.uop.pdst, issue_slots[15].wakeup_ports[3].bits.uop.pdst connect slots_15.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[3].bits.uop.rxq_idx connect slots_15.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[15].wakeup_ports[3].bits.uop.stq_idx connect slots_15.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[3].bits.uop.ldq_idx connect slots_15.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[15].wakeup_ports[3].bits.uop.rob_idx connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_15.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[15].wakeup_ports[3].bits.uop.op2_sel connect slots_15.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[15].wakeup_ports[3].bits.uop.op1_sel connect slots_15.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[15].wakeup_ports[3].bits.uop.imm_packed connect slots_15.io.wakeup_ports[3].bits.uop.pimm, issue_slots[15].wakeup_ports[3].bits.uop.pimm connect slots_15.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[15].wakeup_ports[3].bits.uop.imm_sel connect slots_15.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[15].wakeup_ports[3].bits.uop.imm_rename connect slots_15.io.wakeup_ports[3].bits.uop.taken, issue_slots[15].wakeup_ports[3].bits.uop.taken connect slots_15.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[15].wakeup_ports[3].bits.uop.pc_lob connect slots_15.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[15].wakeup_ports[3].bits.uop.edge_inst connect slots_15.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[3].bits.uop.ftq_idx connect slots_15.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[15].wakeup_ports[3].bits.uop.is_mov connect slots_15.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[15].wakeup_ports[3].bits.uop.is_rocc connect slots_15.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_15.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[15].wakeup_ports[3].bits.uop.is_eret connect slots_15.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[15].wakeup_ports[3].bits.uop.is_amo connect slots_15.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[15].wakeup_ports[3].bits.uop.is_sfence connect slots_15.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[15].wakeup_ports[3].bits.uop.is_fencei connect slots_15.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[15].wakeup_ports[3].bits.uop.is_fence connect slots_15.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[15].wakeup_ports[3].bits.uop.is_sfb connect slots_15.io.wakeup_ports[3].bits.uop.br_type, issue_slots[15].wakeup_ports[3].bits.uop.br_type connect slots_15.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[15].wakeup_ports[3].bits.uop.br_tag connect slots_15.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[15].wakeup_ports[3].bits.uop.br_mask connect slots_15.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[3].bits.uop.dis_col_sel connect slots_15.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_15.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_15.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_15.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_15.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_15.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_15.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_15.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[15].wakeup_ports[3].bits.uop.iw_issued connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[0] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[1] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[2] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[3] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[4] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[5] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[6] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[7] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[8] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[9] connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[0] connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[1] connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[2] connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[3] connect slots_15.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[15].wakeup_ports[3].bits.uop.debug_pc connect slots_15.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[15].wakeup_ports[3].bits.uop.is_rvc connect slots_15.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[15].wakeup_ports[3].bits.uop.debug_inst connect slots_15.io.wakeup_ports[3].bits.uop.inst, issue_slots[15].wakeup_ports[3].bits.uop.inst connect slots_15.io.wakeup_ports[3].valid, issue_slots[15].wakeup_ports[3].valid connect slots_15.io.wakeup_ports[4].bits.rebusy, issue_slots[15].wakeup_ports[4].bits.rebusy connect slots_15.io.wakeup_ports[4].bits.speculative_mask, issue_slots[15].wakeup_ports[4].bits.speculative_mask connect slots_15.io.wakeup_ports[4].bits.bypassable, issue_slots[15].wakeup_ports[4].bits.bypassable connect slots_15.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[4].bits.uop.debug_tsrc connect slots_15.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[4].bits.uop.debug_fsrc connect slots_15.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_15.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[4].bits.uop.bp_debug_if connect slots_15.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_15.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_15.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_15.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[15].wakeup_ports[4].bits.uop.fp_typ connect slots_15.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[15].wakeup_ports[4].bits.uop.fp_rm connect slots_15.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[15].wakeup_ports[4].bits.uop.fp_val connect slots_15.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[15].wakeup_ports[4].bits.uop.fcn_op connect slots_15.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[4].bits.uop.fcn_dw connect slots_15.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[15].wakeup_ports[4].bits.uop.frs3_en connect slots_15.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_15.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_15.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[4].bits.uop.dst_rtype connect slots_15.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[15].wakeup_ports[4].bits.uop.lrs3 connect slots_15.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[15].wakeup_ports[4].bits.uop.lrs2 connect slots_15.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[15].wakeup_ports[4].bits.uop.lrs1 connect slots_15.io.wakeup_ports[4].bits.uop.ldst, issue_slots[15].wakeup_ports[4].bits.uop.ldst connect slots_15.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_15.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[4].bits.uop.csr_cmd connect slots_15.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[4].bits.uop.flush_on_commit connect slots_15.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[15].wakeup_ports[4].bits.uop.is_unique connect slots_15.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[15].wakeup_ports[4].bits.uop.uses_stq connect slots_15.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[4].bits.uop.uses_ldq connect slots_15.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[15].wakeup_ports[4].bits.uop.mem_signed connect slots_15.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[15].wakeup_ports[4].bits.uop.mem_size connect slots_15.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[4].bits.uop.mem_cmd connect slots_15.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[15].wakeup_ports[4].bits.uop.exc_cause connect slots_15.io.wakeup_ports[4].bits.uop.exception, issue_slots[15].wakeup_ports[4].bits.uop.exception connect slots_15.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[4].bits.uop.stale_pdst connect slots_15.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[4].bits.uop.ppred_busy connect slots_15.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[4].bits.uop.prs3_busy connect slots_15.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[4].bits.uop.prs2_busy connect slots_15.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[4].bits.uop.prs1_busy connect slots_15.io.wakeup_ports[4].bits.uop.ppred, issue_slots[15].wakeup_ports[4].bits.uop.ppred connect slots_15.io.wakeup_ports[4].bits.uop.prs3, issue_slots[15].wakeup_ports[4].bits.uop.prs3 connect slots_15.io.wakeup_ports[4].bits.uop.prs2, issue_slots[15].wakeup_ports[4].bits.uop.prs2 connect slots_15.io.wakeup_ports[4].bits.uop.prs1, issue_slots[15].wakeup_ports[4].bits.uop.prs1 connect slots_15.io.wakeup_ports[4].bits.uop.pdst, issue_slots[15].wakeup_ports[4].bits.uop.pdst connect slots_15.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[4].bits.uop.rxq_idx connect slots_15.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[15].wakeup_ports[4].bits.uop.stq_idx connect slots_15.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[4].bits.uop.ldq_idx connect slots_15.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[15].wakeup_ports[4].bits.uop.rob_idx connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_15.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[15].wakeup_ports[4].bits.uop.op2_sel connect slots_15.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[15].wakeup_ports[4].bits.uop.op1_sel connect slots_15.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[15].wakeup_ports[4].bits.uop.imm_packed connect slots_15.io.wakeup_ports[4].bits.uop.pimm, issue_slots[15].wakeup_ports[4].bits.uop.pimm connect slots_15.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[15].wakeup_ports[4].bits.uop.imm_sel connect slots_15.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[15].wakeup_ports[4].bits.uop.imm_rename connect slots_15.io.wakeup_ports[4].bits.uop.taken, issue_slots[15].wakeup_ports[4].bits.uop.taken connect slots_15.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[15].wakeup_ports[4].bits.uop.pc_lob connect slots_15.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[15].wakeup_ports[4].bits.uop.edge_inst connect slots_15.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[4].bits.uop.ftq_idx connect slots_15.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[15].wakeup_ports[4].bits.uop.is_mov connect slots_15.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[15].wakeup_ports[4].bits.uop.is_rocc connect slots_15.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_15.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[15].wakeup_ports[4].bits.uop.is_eret connect slots_15.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[15].wakeup_ports[4].bits.uop.is_amo connect slots_15.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[15].wakeup_ports[4].bits.uop.is_sfence connect slots_15.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[15].wakeup_ports[4].bits.uop.is_fencei connect slots_15.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[15].wakeup_ports[4].bits.uop.is_fence connect slots_15.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[15].wakeup_ports[4].bits.uop.is_sfb connect slots_15.io.wakeup_ports[4].bits.uop.br_type, issue_slots[15].wakeup_ports[4].bits.uop.br_type connect slots_15.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[15].wakeup_ports[4].bits.uop.br_tag connect slots_15.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[15].wakeup_ports[4].bits.uop.br_mask connect slots_15.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[4].bits.uop.dis_col_sel connect slots_15.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_15.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_15.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_15.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_15.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_15.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_15.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_15.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[15].wakeup_ports[4].bits.uop.iw_issued connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[0] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[1] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[2] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[3] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[4] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[5] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[6] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[7] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[8] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[9] connect slots_15.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[4].bits.uop.iq_type[0] connect slots_15.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[4].bits.uop.iq_type[1] connect slots_15.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[4].bits.uop.iq_type[2] connect slots_15.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[4].bits.uop.iq_type[3] connect slots_15.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[15].wakeup_ports[4].bits.uop.debug_pc connect slots_15.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[15].wakeup_ports[4].bits.uop.is_rvc connect slots_15.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[15].wakeup_ports[4].bits.uop.debug_inst connect slots_15.io.wakeup_ports[4].bits.uop.inst, issue_slots[15].wakeup_ports[4].bits.uop.inst connect slots_15.io.wakeup_ports[4].valid, issue_slots[15].wakeup_ports[4].valid connect slots_15.io.squash_grant, issue_slots[15].squash_grant connect slots_15.io.clear, issue_slots[15].clear connect slots_15.io.kill, issue_slots[15].kill connect slots_15.io.brupdate.b2.target_offset, issue_slots[15].brupdate.b2.target_offset connect slots_15.io.brupdate.b2.jalr_target, issue_slots[15].brupdate.b2.jalr_target connect slots_15.io.brupdate.b2.pc_sel, issue_slots[15].brupdate.b2.pc_sel connect slots_15.io.brupdate.b2.cfi_type, issue_slots[15].brupdate.b2.cfi_type connect slots_15.io.brupdate.b2.taken, issue_slots[15].brupdate.b2.taken connect slots_15.io.brupdate.b2.mispredict, issue_slots[15].brupdate.b2.mispredict connect slots_15.io.brupdate.b2.uop.debug_tsrc, issue_slots[15].brupdate.b2.uop.debug_tsrc connect slots_15.io.brupdate.b2.uop.debug_fsrc, issue_slots[15].brupdate.b2.uop.debug_fsrc connect slots_15.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[15].brupdate.b2.uop.bp_xcpt_if connect slots_15.io.brupdate.b2.uop.bp_debug_if, issue_slots[15].brupdate.b2.uop.bp_debug_if connect slots_15.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[15].brupdate.b2.uop.xcpt_ma_if connect slots_15.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[15].brupdate.b2.uop.xcpt_ae_if connect slots_15.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[15].brupdate.b2.uop.xcpt_pf_if connect slots_15.io.brupdate.b2.uop.fp_typ, issue_slots[15].brupdate.b2.uop.fp_typ connect slots_15.io.brupdate.b2.uop.fp_rm, issue_slots[15].brupdate.b2.uop.fp_rm connect slots_15.io.brupdate.b2.uop.fp_val, issue_slots[15].brupdate.b2.uop.fp_val connect slots_15.io.brupdate.b2.uop.fcn_op, issue_slots[15].brupdate.b2.uop.fcn_op connect slots_15.io.brupdate.b2.uop.fcn_dw, issue_slots[15].brupdate.b2.uop.fcn_dw connect slots_15.io.brupdate.b2.uop.frs3_en, issue_slots[15].brupdate.b2.uop.frs3_en connect slots_15.io.brupdate.b2.uop.lrs2_rtype, issue_slots[15].brupdate.b2.uop.lrs2_rtype connect slots_15.io.brupdate.b2.uop.lrs1_rtype, issue_slots[15].brupdate.b2.uop.lrs1_rtype connect slots_15.io.brupdate.b2.uop.dst_rtype, issue_slots[15].brupdate.b2.uop.dst_rtype connect slots_15.io.brupdate.b2.uop.lrs3, issue_slots[15].brupdate.b2.uop.lrs3 connect slots_15.io.brupdate.b2.uop.lrs2, issue_slots[15].brupdate.b2.uop.lrs2 connect slots_15.io.brupdate.b2.uop.lrs1, issue_slots[15].brupdate.b2.uop.lrs1 connect slots_15.io.brupdate.b2.uop.ldst, issue_slots[15].brupdate.b2.uop.ldst connect slots_15.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[15].brupdate.b2.uop.ldst_is_rs1 connect slots_15.io.brupdate.b2.uop.csr_cmd, issue_slots[15].brupdate.b2.uop.csr_cmd connect slots_15.io.brupdate.b2.uop.flush_on_commit, issue_slots[15].brupdate.b2.uop.flush_on_commit connect slots_15.io.brupdate.b2.uop.is_unique, issue_slots[15].brupdate.b2.uop.is_unique connect slots_15.io.brupdate.b2.uop.uses_stq, issue_slots[15].brupdate.b2.uop.uses_stq connect slots_15.io.brupdate.b2.uop.uses_ldq, issue_slots[15].brupdate.b2.uop.uses_ldq connect slots_15.io.brupdate.b2.uop.mem_signed, issue_slots[15].brupdate.b2.uop.mem_signed connect slots_15.io.brupdate.b2.uop.mem_size, issue_slots[15].brupdate.b2.uop.mem_size connect slots_15.io.brupdate.b2.uop.mem_cmd, issue_slots[15].brupdate.b2.uop.mem_cmd connect slots_15.io.brupdate.b2.uop.exc_cause, issue_slots[15].brupdate.b2.uop.exc_cause connect slots_15.io.brupdate.b2.uop.exception, issue_slots[15].brupdate.b2.uop.exception connect slots_15.io.brupdate.b2.uop.stale_pdst, issue_slots[15].brupdate.b2.uop.stale_pdst connect slots_15.io.brupdate.b2.uop.ppred_busy, issue_slots[15].brupdate.b2.uop.ppred_busy connect slots_15.io.brupdate.b2.uop.prs3_busy, issue_slots[15].brupdate.b2.uop.prs3_busy connect slots_15.io.brupdate.b2.uop.prs2_busy, issue_slots[15].brupdate.b2.uop.prs2_busy connect slots_15.io.brupdate.b2.uop.prs1_busy, issue_slots[15].brupdate.b2.uop.prs1_busy connect slots_15.io.brupdate.b2.uop.ppred, issue_slots[15].brupdate.b2.uop.ppred connect slots_15.io.brupdate.b2.uop.prs3, issue_slots[15].brupdate.b2.uop.prs3 connect slots_15.io.brupdate.b2.uop.prs2, issue_slots[15].brupdate.b2.uop.prs2 connect slots_15.io.brupdate.b2.uop.prs1, issue_slots[15].brupdate.b2.uop.prs1 connect slots_15.io.brupdate.b2.uop.pdst, issue_slots[15].brupdate.b2.uop.pdst connect slots_15.io.brupdate.b2.uop.rxq_idx, issue_slots[15].brupdate.b2.uop.rxq_idx connect slots_15.io.brupdate.b2.uop.stq_idx, issue_slots[15].brupdate.b2.uop.stq_idx connect slots_15.io.brupdate.b2.uop.ldq_idx, issue_slots[15].brupdate.b2.uop.ldq_idx connect slots_15.io.brupdate.b2.uop.rob_idx, issue_slots[15].brupdate.b2.uop.rob_idx connect slots_15.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[15].brupdate.b2.uop.fp_ctrl.vec connect slots_15.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[15].brupdate.b2.uop.fp_ctrl.wflags connect slots_15.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[15].brupdate.b2.uop.fp_ctrl.sqrt connect slots_15.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[15].brupdate.b2.uop.fp_ctrl.div connect slots_15.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[15].brupdate.b2.uop.fp_ctrl.fma connect slots_15.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[15].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_15.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[15].brupdate.b2.uop.fp_ctrl.toint connect slots_15.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[15].brupdate.b2.uop.fp_ctrl.fromint connect slots_15.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_15.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_15.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[15].brupdate.b2.uop.fp_ctrl.swap23 connect slots_15.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[15].brupdate.b2.uop.fp_ctrl.swap12 connect slots_15.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[15].brupdate.b2.uop.fp_ctrl.ren3 connect slots_15.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[15].brupdate.b2.uop.fp_ctrl.ren2 connect slots_15.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[15].brupdate.b2.uop.fp_ctrl.ren1 connect slots_15.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[15].brupdate.b2.uop.fp_ctrl.wen connect slots_15.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[15].brupdate.b2.uop.fp_ctrl.ldst connect slots_15.io.brupdate.b2.uop.op2_sel, issue_slots[15].brupdate.b2.uop.op2_sel connect slots_15.io.brupdate.b2.uop.op1_sel, issue_slots[15].brupdate.b2.uop.op1_sel connect slots_15.io.brupdate.b2.uop.imm_packed, issue_slots[15].brupdate.b2.uop.imm_packed connect slots_15.io.brupdate.b2.uop.pimm, issue_slots[15].brupdate.b2.uop.pimm connect slots_15.io.brupdate.b2.uop.imm_sel, issue_slots[15].brupdate.b2.uop.imm_sel connect slots_15.io.brupdate.b2.uop.imm_rename, issue_slots[15].brupdate.b2.uop.imm_rename connect slots_15.io.brupdate.b2.uop.taken, issue_slots[15].brupdate.b2.uop.taken connect slots_15.io.brupdate.b2.uop.pc_lob, issue_slots[15].brupdate.b2.uop.pc_lob connect slots_15.io.brupdate.b2.uop.edge_inst, issue_slots[15].brupdate.b2.uop.edge_inst connect slots_15.io.brupdate.b2.uop.ftq_idx, issue_slots[15].brupdate.b2.uop.ftq_idx connect slots_15.io.brupdate.b2.uop.is_mov, issue_slots[15].brupdate.b2.uop.is_mov connect slots_15.io.brupdate.b2.uop.is_rocc, issue_slots[15].brupdate.b2.uop.is_rocc connect slots_15.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[15].brupdate.b2.uop.is_sys_pc2epc connect slots_15.io.brupdate.b2.uop.is_eret, issue_slots[15].brupdate.b2.uop.is_eret connect slots_15.io.brupdate.b2.uop.is_amo, issue_slots[15].brupdate.b2.uop.is_amo connect slots_15.io.brupdate.b2.uop.is_sfence, issue_slots[15].brupdate.b2.uop.is_sfence connect slots_15.io.brupdate.b2.uop.is_fencei, issue_slots[15].brupdate.b2.uop.is_fencei connect slots_15.io.brupdate.b2.uop.is_fence, issue_slots[15].brupdate.b2.uop.is_fence connect slots_15.io.brupdate.b2.uop.is_sfb, issue_slots[15].brupdate.b2.uop.is_sfb connect slots_15.io.brupdate.b2.uop.br_type, issue_slots[15].brupdate.b2.uop.br_type connect slots_15.io.brupdate.b2.uop.br_tag, issue_slots[15].brupdate.b2.uop.br_tag connect slots_15.io.brupdate.b2.uop.br_mask, issue_slots[15].brupdate.b2.uop.br_mask connect slots_15.io.brupdate.b2.uop.dis_col_sel, issue_slots[15].brupdate.b2.uop.dis_col_sel connect slots_15.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[15].brupdate.b2.uop.iw_p3_bypass_hint connect slots_15.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[15].brupdate.b2.uop.iw_p2_bypass_hint connect slots_15.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[15].brupdate.b2.uop.iw_p1_bypass_hint connect slots_15.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[15].brupdate.b2.uop.iw_p2_speculative_child connect slots_15.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[15].brupdate.b2.uop.iw_p1_speculative_child connect slots_15.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[15].brupdate.b2.uop.iw_issued_partial_dgen connect slots_15.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[15].brupdate.b2.uop.iw_issued_partial_agen connect slots_15.io.brupdate.b2.uop.iw_issued, issue_slots[15].brupdate.b2.uop.iw_issued connect slots_15.io.brupdate.b2.uop.fu_code[0], issue_slots[15].brupdate.b2.uop.fu_code[0] connect slots_15.io.brupdate.b2.uop.fu_code[1], issue_slots[15].brupdate.b2.uop.fu_code[1] connect slots_15.io.brupdate.b2.uop.fu_code[2], issue_slots[15].brupdate.b2.uop.fu_code[2] connect slots_15.io.brupdate.b2.uop.fu_code[3], issue_slots[15].brupdate.b2.uop.fu_code[3] connect slots_15.io.brupdate.b2.uop.fu_code[4], issue_slots[15].brupdate.b2.uop.fu_code[4] connect slots_15.io.brupdate.b2.uop.fu_code[5], issue_slots[15].brupdate.b2.uop.fu_code[5] connect slots_15.io.brupdate.b2.uop.fu_code[6], issue_slots[15].brupdate.b2.uop.fu_code[6] connect slots_15.io.brupdate.b2.uop.fu_code[7], issue_slots[15].brupdate.b2.uop.fu_code[7] connect slots_15.io.brupdate.b2.uop.fu_code[8], issue_slots[15].brupdate.b2.uop.fu_code[8] connect slots_15.io.brupdate.b2.uop.fu_code[9], issue_slots[15].brupdate.b2.uop.fu_code[9] connect slots_15.io.brupdate.b2.uop.iq_type[0], issue_slots[15].brupdate.b2.uop.iq_type[0] connect slots_15.io.brupdate.b2.uop.iq_type[1], issue_slots[15].brupdate.b2.uop.iq_type[1] connect slots_15.io.brupdate.b2.uop.iq_type[2], issue_slots[15].brupdate.b2.uop.iq_type[2] connect slots_15.io.brupdate.b2.uop.iq_type[3], issue_slots[15].brupdate.b2.uop.iq_type[3] connect slots_15.io.brupdate.b2.uop.debug_pc, issue_slots[15].brupdate.b2.uop.debug_pc connect slots_15.io.brupdate.b2.uop.is_rvc, issue_slots[15].brupdate.b2.uop.is_rvc connect slots_15.io.brupdate.b2.uop.debug_inst, issue_slots[15].brupdate.b2.uop.debug_inst connect slots_15.io.brupdate.b2.uop.inst, issue_slots[15].brupdate.b2.uop.inst connect slots_15.io.brupdate.b1.mispredict_mask, issue_slots[15].brupdate.b1.mispredict_mask connect slots_15.io.brupdate.b1.resolve_mask, issue_slots[15].brupdate.b1.resolve_mask connect issue_slots[15].out_uop.debug_tsrc, slots_15.io.out_uop.debug_tsrc connect issue_slots[15].out_uop.debug_fsrc, slots_15.io.out_uop.debug_fsrc connect issue_slots[15].out_uop.bp_xcpt_if, slots_15.io.out_uop.bp_xcpt_if connect issue_slots[15].out_uop.bp_debug_if, slots_15.io.out_uop.bp_debug_if connect issue_slots[15].out_uop.xcpt_ma_if, slots_15.io.out_uop.xcpt_ma_if connect issue_slots[15].out_uop.xcpt_ae_if, slots_15.io.out_uop.xcpt_ae_if connect issue_slots[15].out_uop.xcpt_pf_if, slots_15.io.out_uop.xcpt_pf_if connect issue_slots[15].out_uop.fp_typ, slots_15.io.out_uop.fp_typ connect issue_slots[15].out_uop.fp_rm, slots_15.io.out_uop.fp_rm connect issue_slots[15].out_uop.fp_val, slots_15.io.out_uop.fp_val connect issue_slots[15].out_uop.fcn_op, slots_15.io.out_uop.fcn_op connect issue_slots[15].out_uop.fcn_dw, slots_15.io.out_uop.fcn_dw connect issue_slots[15].out_uop.frs3_en, slots_15.io.out_uop.frs3_en connect issue_slots[15].out_uop.lrs2_rtype, slots_15.io.out_uop.lrs2_rtype connect issue_slots[15].out_uop.lrs1_rtype, slots_15.io.out_uop.lrs1_rtype connect issue_slots[15].out_uop.dst_rtype, slots_15.io.out_uop.dst_rtype connect issue_slots[15].out_uop.lrs3, slots_15.io.out_uop.lrs3 connect issue_slots[15].out_uop.lrs2, slots_15.io.out_uop.lrs2 connect issue_slots[15].out_uop.lrs1, slots_15.io.out_uop.lrs1 connect issue_slots[15].out_uop.ldst, slots_15.io.out_uop.ldst connect issue_slots[15].out_uop.ldst_is_rs1, slots_15.io.out_uop.ldst_is_rs1 connect issue_slots[15].out_uop.csr_cmd, slots_15.io.out_uop.csr_cmd connect issue_slots[15].out_uop.flush_on_commit, slots_15.io.out_uop.flush_on_commit connect issue_slots[15].out_uop.is_unique, slots_15.io.out_uop.is_unique connect issue_slots[15].out_uop.uses_stq, slots_15.io.out_uop.uses_stq connect issue_slots[15].out_uop.uses_ldq, slots_15.io.out_uop.uses_ldq connect issue_slots[15].out_uop.mem_signed, slots_15.io.out_uop.mem_signed connect issue_slots[15].out_uop.mem_size, slots_15.io.out_uop.mem_size connect issue_slots[15].out_uop.mem_cmd, slots_15.io.out_uop.mem_cmd connect issue_slots[15].out_uop.exc_cause, slots_15.io.out_uop.exc_cause connect issue_slots[15].out_uop.exception, slots_15.io.out_uop.exception connect issue_slots[15].out_uop.stale_pdst, slots_15.io.out_uop.stale_pdst connect issue_slots[15].out_uop.ppred_busy, slots_15.io.out_uop.ppred_busy connect issue_slots[15].out_uop.prs3_busy, slots_15.io.out_uop.prs3_busy connect issue_slots[15].out_uop.prs2_busy, slots_15.io.out_uop.prs2_busy connect issue_slots[15].out_uop.prs1_busy, slots_15.io.out_uop.prs1_busy connect issue_slots[15].out_uop.ppred, slots_15.io.out_uop.ppred connect issue_slots[15].out_uop.prs3, slots_15.io.out_uop.prs3 connect issue_slots[15].out_uop.prs2, slots_15.io.out_uop.prs2 connect issue_slots[15].out_uop.prs1, slots_15.io.out_uop.prs1 connect issue_slots[15].out_uop.pdst, slots_15.io.out_uop.pdst connect issue_slots[15].out_uop.rxq_idx, slots_15.io.out_uop.rxq_idx connect issue_slots[15].out_uop.stq_idx, slots_15.io.out_uop.stq_idx connect issue_slots[15].out_uop.ldq_idx, slots_15.io.out_uop.ldq_idx connect issue_slots[15].out_uop.rob_idx, slots_15.io.out_uop.rob_idx connect issue_slots[15].out_uop.fp_ctrl.vec, slots_15.io.out_uop.fp_ctrl.vec connect issue_slots[15].out_uop.fp_ctrl.wflags, slots_15.io.out_uop.fp_ctrl.wflags connect issue_slots[15].out_uop.fp_ctrl.sqrt, slots_15.io.out_uop.fp_ctrl.sqrt connect issue_slots[15].out_uop.fp_ctrl.div, slots_15.io.out_uop.fp_ctrl.div connect issue_slots[15].out_uop.fp_ctrl.fma, slots_15.io.out_uop.fp_ctrl.fma connect issue_slots[15].out_uop.fp_ctrl.fastpipe, slots_15.io.out_uop.fp_ctrl.fastpipe connect issue_slots[15].out_uop.fp_ctrl.toint, slots_15.io.out_uop.fp_ctrl.toint connect issue_slots[15].out_uop.fp_ctrl.fromint, slots_15.io.out_uop.fp_ctrl.fromint connect issue_slots[15].out_uop.fp_ctrl.typeTagOut, slots_15.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[15].out_uop.fp_ctrl.typeTagIn, slots_15.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[15].out_uop.fp_ctrl.swap23, slots_15.io.out_uop.fp_ctrl.swap23 connect issue_slots[15].out_uop.fp_ctrl.swap12, slots_15.io.out_uop.fp_ctrl.swap12 connect issue_slots[15].out_uop.fp_ctrl.ren3, slots_15.io.out_uop.fp_ctrl.ren3 connect issue_slots[15].out_uop.fp_ctrl.ren2, slots_15.io.out_uop.fp_ctrl.ren2 connect issue_slots[15].out_uop.fp_ctrl.ren1, slots_15.io.out_uop.fp_ctrl.ren1 connect issue_slots[15].out_uop.fp_ctrl.wen, slots_15.io.out_uop.fp_ctrl.wen connect issue_slots[15].out_uop.fp_ctrl.ldst, slots_15.io.out_uop.fp_ctrl.ldst connect issue_slots[15].out_uop.op2_sel, slots_15.io.out_uop.op2_sel connect issue_slots[15].out_uop.op1_sel, slots_15.io.out_uop.op1_sel connect issue_slots[15].out_uop.imm_packed, slots_15.io.out_uop.imm_packed connect issue_slots[15].out_uop.pimm, slots_15.io.out_uop.pimm connect issue_slots[15].out_uop.imm_sel, slots_15.io.out_uop.imm_sel connect issue_slots[15].out_uop.imm_rename, slots_15.io.out_uop.imm_rename connect issue_slots[15].out_uop.taken, slots_15.io.out_uop.taken connect issue_slots[15].out_uop.pc_lob, slots_15.io.out_uop.pc_lob connect issue_slots[15].out_uop.edge_inst, slots_15.io.out_uop.edge_inst connect issue_slots[15].out_uop.ftq_idx, slots_15.io.out_uop.ftq_idx connect issue_slots[15].out_uop.is_mov, slots_15.io.out_uop.is_mov connect issue_slots[15].out_uop.is_rocc, slots_15.io.out_uop.is_rocc connect issue_slots[15].out_uop.is_sys_pc2epc, slots_15.io.out_uop.is_sys_pc2epc connect issue_slots[15].out_uop.is_eret, slots_15.io.out_uop.is_eret connect issue_slots[15].out_uop.is_amo, slots_15.io.out_uop.is_amo connect issue_slots[15].out_uop.is_sfence, slots_15.io.out_uop.is_sfence connect issue_slots[15].out_uop.is_fencei, slots_15.io.out_uop.is_fencei connect issue_slots[15].out_uop.is_fence, slots_15.io.out_uop.is_fence connect issue_slots[15].out_uop.is_sfb, slots_15.io.out_uop.is_sfb connect issue_slots[15].out_uop.br_type, slots_15.io.out_uop.br_type connect issue_slots[15].out_uop.br_tag, slots_15.io.out_uop.br_tag connect issue_slots[15].out_uop.br_mask, slots_15.io.out_uop.br_mask connect issue_slots[15].out_uop.dis_col_sel, slots_15.io.out_uop.dis_col_sel connect issue_slots[15].out_uop.iw_p3_bypass_hint, slots_15.io.out_uop.iw_p3_bypass_hint connect issue_slots[15].out_uop.iw_p2_bypass_hint, slots_15.io.out_uop.iw_p2_bypass_hint connect issue_slots[15].out_uop.iw_p1_bypass_hint, slots_15.io.out_uop.iw_p1_bypass_hint connect issue_slots[15].out_uop.iw_p2_speculative_child, slots_15.io.out_uop.iw_p2_speculative_child connect issue_slots[15].out_uop.iw_p1_speculative_child, slots_15.io.out_uop.iw_p1_speculative_child connect issue_slots[15].out_uop.iw_issued_partial_dgen, slots_15.io.out_uop.iw_issued_partial_dgen connect issue_slots[15].out_uop.iw_issued_partial_agen, slots_15.io.out_uop.iw_issued_partial_agen connect issue_slots[15].out_uop.iw_issued, slots_15.io.out_uop.iw_issued connect issue_slots[15].out_uop.fu_code[0], slots_15.io.out_uop.fu_code[0] connect issue_slots[15].out_uop.fu_code[1], slots_15.io.out_uop.fu_code[1] connect issue_slots[15].out_uop.fu_code[2], slots_15.io.out_uop.fu_code[2] connect issue_slots[15].out_uop.fu_code[3], slots_15.io.out_uop.fu_code[3] connect issue_slots[15].out_uop.fu_code[4], slots_15.io.out_uop.fu_code[4] connect issue_slots[15].out_uop.fu_code[5], slots_15.io.out_uop.fu_code[5] connect issue_slots[15].out_uop.fu_code[6], slots_15.io.out_uop.fu_code[6] connect issue_slots[15].out_uop.fu_code[7], slots_15.io.out_uop.fu_code[7] connect issue_slots[15].out_uop.fu_code[8], slots_15.io.out_uop.fu_code[8] connect issue_slots[15].out_uop.fu_code[9], slots_15.io.out_uop.fu_code[9] connect issue_slots[15].out_uop.iq_type[0], slots_15.io.out_uop.iq_type[0] connect issue_slots[15].out_uop.iq_type[1], slots_15.io.out_uop.iq_type[1] connect issue_slots[15].out_uop.iq_type[2], slots_15.io.out_uop.iq_type[2] connect issue_slots[15].out_uop.iq_type[3], slots_15.io.out_uop.iq_type[3] connect issue_slots[15].out_uop.debug_pc, slots_15.io.out_uop.debug_pc connect issue_slots[15].out_uop.is_rvc, slots_15.io.out_uop.is_rvc connect issue_slots[15].out_uop.debug_inst, slots_15.io.out_uop.debug_inst connect issue_slots[15].out_uop.inst, slots_15.io.out_uop.inst connect slots_15.io.in_uop.bits.debug_tsrc, issue_slots[15].in_uop.bits.debug_tsrc connect slots_15.io.in_uop.bits.debug_fsrc, issue_slots[15].in_uop.bits.debug_fsrc connect slots_15.io.in_uop.bits.bp_xcpt_if, issue_slots[15].in_uop.bits.bp_xcpt_if connect slots_15.io.in_uop.bits.bp_debug_if, issue_slots[15].in_uop.bits.bp_debug_if connect slots_15.io.in_uop.bits.xcpt_ma_if, issue_slots[15].in_uop.bits.xcpt_ma_if connect slots_15.io.in_uop.bits.xcpt_ae_if, issue_slots[15].in_uop.bits.xcpt_ae_if connect slots_15.io.in_uop.bits.xcpt_pf_if, issue_slots[15].in_uop.bits.xcpt_pf_if connect slots_15.io.in_uop.bits.fp_typ, issue_slots[15].in_uop.bits.fp_typ connect slots_15.io.in_uop.bits.fp_rm, issue_slots[15].in_uop.bits.fp_rm connect slots_15.io.in_uop.bits.fp_val, issue_slots[15].in_uop.bits.fp_val connect slots_15.io.in_uop.bits.fcn_op, issue_slots[15].in_uop.bits.fcn_op connect slots_15.io.in_uop.bits.fcn_dw, issue_slots[15].in_uop.bits.fcn_dw connect slots_15.io.in_uop.bits.frs3_en, issue_slots[15].in_uop.bits.frs3_en connect slots_15.io.in_uop.bits.lrs2_rtype, issue_slots[15].in_uop.bits.lrs2_rtype connect slots_15.io.in_uop.bits.lrs1_rtype, issue_slots[15].in_uop.bits.lrs1_rtype connect slots_15.io.in_uop.bits.dst_rtype, issue_slots[15].in_uop.bits.dst_rtype connect slots_15.io.in_uop.bits.lrs3, issue_slots[15].in_uop.bits.lrs3 connect slots_15.io.in_uop.bits.lrs2, issue_slots[15].in_uop.bits.lrs2 connect slots_15.io.in_uop.bits.lrs1, issue_slots[15].in_uop.bits.lrs1 connect slots_15.io.in_uop.bits.ldst, issue_slots[15].in_uop.bits.ldst connect slots_15.io.in_uop.bits.ldst_is_rs1, issue_slots[15].in_uop.bits.ldst_is_rs1 connect slots_15.io.in_uop.bits.csr_cmd, issue_slots[15].in_uop.bits.csr_cmd connect slots_15.io.in_uop.bits.flush_on_commit, issue_slots[15].in_uop.bits.flush_on_commit connect slots_15.io.in_uop.bits.is_unique, issue_slots[15].in_uop.bits.is_unique connect slots_15.io.in_uop.bits.uses_stq, issue_slots[15].in_uop.bits.uses_stq connect slots_15.io.in_uop.bits.uses_ldq, issue_slots[15].in_uop.bits.uses_ldq connect slots_15.io.in_uop.bits.mem_signed, issue_slots[15].in_uop.bits.mem_signed connect slots_15.io.in_uop.bits.mem_size, issue_slots[15].in_uop.bits.mem_size connect slots_15.io.in_uop.bits.mem_cmd, issue_slots[15].in_uop.bits.mem_cmd connect slots_15.io.in_uop.bits.exc_cause, issue_slots[15].in_uop.bits.exc_cause connect slots_15.io.in_uop.bits.exception, issue_slots[15].in_uop.bits.exception connect slots_15.io.in_uop.bits.stale_pdst, issue_slots[15].in_uop.bits.stale_pdst connect slots_15.io.in_uop.bits.ppred_busy, issue_slots[15].in_uop.bits.ppred_busy connect slots_15.io.in_uop.bits.prs3_busy, issue_slots[15].in_uop.bits.prs3_busy connect slots_15.io.in_uop.bits.prs2_busy, issue_slots[15].in_uop.bits.prs2_busy connect slots_15.io.in_uop.bits.prs1_busy, issue_slots[15].in_uop.bits.prs1_busy connect slots_15.io.in_uop.bits.ppred, issue_slots[15].in_uop.bits.ppred connect slots_15.io.in_uop.bits.prs3, issue_slots[15].in_uop.bits.prs3 connect slots_15.io.in_uop.bits.prs2, issue_slots[15].in_uop.bits.prs2 connect slots_15.io.in_uop.bits.prs1, issue_slots[15].in_uop.bits.prs1 connect slots_15.io.in_uop.bits.pdst, issue_slots[15].in_uop.bits.pdst connect slots_15.io.in_uop.bits.rxq_idx, issue_slots[15].in_uop.bits.rxq_idx connect slots_15.io.in_uop.bits.stq_idx, issue_slots[15].in_uop.bits.stq_idx connect slots_15.io.in_uop.bits.ldq_idx, issue_slots[15].in_uop.bits.ldq_idx connect slots_15.io.in_uop.bits.rob_idx, issue_slots[15].in_uop.bits.rob_idx connect slots_15.io.in_uop.bits.fp_ctrl.vec, issue_slots[15].in_uop.bits.fp_ctrl.vec connect slots_15.io.in_uop.bits.fp_ctrl.wflags, issue_slots[15].in_uop.bits.fp_ctrl.wflags connect slots_15.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[15].in_uop.bits.fp_ctrl.sqrt connect slots_15.io.in_uop.bits.fp_ctrl.div, issue_slots[15].in_uop.bits.fp_ctrl.div connect slots_15.io.in_uop.bits.fp_ctrl.fma, issue_slots[15].in_uop.bits.fp_ctrl.fma connect slots_15.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].in_uop.bits.fp_ctrl.fastpipe connect slots_15.io.in_uop.bits.fp_ctrl.toint, issue_slots[15].in_uop.bits.fp_ctrl.toint connect slots_15.io.in_uop.bits.fp_ctrl.fromint, issue_slots[15].in_uop.bits.fp_ctrl.fromint connect slots_15.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut connect slots_15.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn connect slots_15.io.in_uop.bits.fp_ctrl.swap23, issue_slots[15].in_uop.bits.fp_ctrl.swap23 connect slots_15.io.in_uop.bits.fp_ctrl.swap12, issue_slots[15].in_uop.bits.fp_ctrl.swap12 connect slots_15.io.in_uop.bits.fp_ctrl.ren3, issue_slots[15].in_uop.bits.fp_ctrl.ren3 connect slots_15.io.in_uop.bits.fp_ctrl.ren2, issue_slots[15].in_uop.bits.fp_ctrl.ren2 connect slots_15.io.in_uop.bits.fp_ctrl.ren1, issue_slots[15].in_uop.bits.fp_ctrl.ren1 connect slots_15.io.in_uop.bits.fp_ctrl.wen, issue_slots[15].in_uop.bits.fp_ctrl.wen connect slots_15.io.in_uop.bits.fp_ctrl.ldst, issue_slots[15].in_uop.bits.fp_ctrl.ldst connect slots_15.io.in_uop.bits.op2_sel, issue_slots[15].in_uop.bits.op2_sel connect slots_15.io.in_uop.bits.op1_sel, issue_slots[15].in_uop.bits.op1_sel connect slots_15.io.in_uop.bits.imm_packed, issue_slots[15].in_uop.bits.imm_packed connect slots_15.io.in_uop.bits.pimm, issue_slots[15].in_uop.bits.pimm connect slots_15.io.in_uop.bits.imm_sel, issue_slots[15].in_uop.bits.imm_sel connect slots_15.io.in_uop.bits.imm_rename, issue_slots[15].in_uop.bits.imm_rename connect slots_15.io.in_uop.bits.taken, issue_slots[15].in_uop.bits.taken connect slots_15.io.in_uop.bits.pc_lob, issue_slots[15].in_uop.bits.pc_lob connect slots_15.io.in_uop.bits.edge_inst, issue_slots[15].in_uop.bits.edge_inst connect slots_15.io.in_uop.bits.ftq_idx, issue_slots[15].in_uop.bits.ftq_idx connect slots_15.io.in_uop.bits.is_mov, issue_slots[15].in_uop.bits.is_mov connect slots_15.io.in_uop.bits.is_rocc, issue_slots[15].in_uop.bits.is_rocc connect slots_15.io.in_uop.bits.is_sys_pc2epc, issue_slots[15].in_uop.bits.is_sys_pc2epc connect slots_15.io.in_uop.bits.is_eret, issue_slots[15].in_uop.bits.is_eret connect slots_15.io.in_uop.bits.is_amo, issue_slots[15].in_uop.bits.is_amo connect slots_15.io.in_uop.bits.is_sfence, issue_slots[15].in_uop.bits.is_sfence connect slots_15.io.in_uop.bits.is_fencei, issue_slots[15].in_uop.bits.is_fencei connect slots_15.io.in_uop.bits.is_fence, issue_slots[15].in_uop.bits.is_fence connect slots_15.io.in_uop.bits.is_sfb, issue_slots[15].in_uop.bits.is_sfb connect slots_15.io.in_uop.bits.br_type, issue_slots[15].in_uop.bits.br_type connect slots_15.io.in_uop.bits.br_tag, issue_slots[15].in_uop.bits.br_tag connect slots_15.io.in_uop.bits.br_mask, issue_slots[15].in_uop.bits.br_mask connect slots_15.io.in_uop.bits.dis_col_sel, issue_slots[15].in_uop.bits.dis_col_sel connect slots_15.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[15].in_uop.bits.iw_p3_bypass_hint connect slots_15.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[15].in_uop.bits.iw_p2_bypass_hint connect slots_15.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[15].in_uop.bits.iw_p1_bypass_hint connect slots_15.io.in_uop.bits.iw_p2_speculative_child, issue_slots[15].in_uop.bits.iw_p2_speculative_child connect slots_15.io.in_uop.bits.iw_p1_speculative_child, issue_slots[15].in_uop.bits.iw_p1_speculative_child connect slots_15.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[15].in_uop.bits.iw_issued_partial_dgen connect slots_15.io.in_uop.bits.iw_issued_partial_agen, issue_slots[15].in_uop.bits.iw_issued_partial_agen connect slots_15.io.in_uop.bits.iw_issued, issue_slots[15].in_uop.bits.iw_issued connect slots_15.io.in_uop.bits.fu_code[0], issue_slots[15].in_uop.bits.fu_code[0] connect slots_15.io.in_uop.bits.fu_code[1], issue_slots[15].in_uop.bits.fu_code[1] connect slots_15.io.in_uop.bits.fu_code[2], issue_slots[15].in_uop.bits.fu_code[2] connect slots_15.io.in_uop.bits.fu_code[3], issue_slots[15].in_uop.bits.fu_code[3] connect slots_15.io.in_uop.bits.fu_code[4], issue_slots[15].in_uop.bits.fu_code[4] connect slots_15.io.in_uop.bits.fu_code[5], issue_slots[15].in_uop.bits.fu_code[5] connect slots_15.io.in_uop.bits.fu_code[6], issue_slots[15].in_uop.bits.fu_code[6] connect slots_15.io.in_uop.bits.fu_code[7], issue_slots[15].in_uop.bits.fu_code[7] connect slots_15.io.in_uop.bits.fu_code[8], issue_slots[15].in_uop.bits.fu_code[8] connect slots_15.io.in_uop.bits.fu_code[9], issue_slots[15].in_uop.bits.fu_code[9] connect slots_15.io.in_uop.bits.iq_type[0], issue_slots[15].in_uop.bits.iq_type[0] connect slots_15.io.in_uop.bits.iq_type[1], issue_slots[15].in_uop.bits.iq_type[1] connect slots_15.io.in_uop.bits.iq_type[2], issue_slots[15].in_uop.bits.iq_type[2] connect slots_15.io.in_uop.bits.iq_type[3], issue_slots[15].in_uop.bits.iq_type[3] connect slots_15.io.in_uop.bits.debug_pc, issue_slots[15].in_uop.bits.debug_pc connect slots_15.io.in_uop.bits.is_rvc, issue_slots[15].in_uop.bits.is_rvc connect slots_15.io.in_uop.bits.debug_inst, issue_slots[15].in_uop.bits.debug_inst connect slots_15.io.in_uop.bits.inst, issue_slots[15].in_uop.bits.inst connect slots_15.io.in_uop.valid, issue_slots[15].in_uop.valid connect issue_slots[15].iss_uop.debug_tsrc, slots_15.io.iss_uop.debug_tsrc connect issue_slots[15].iss_uop.debug_fsrc, slots_15.io.iss_uop.debug_fsrc connect issue_slots[15].iss_uop.bp_xcpt_if, slots_15.io.iss_uop.bp_xcpt_if connect issue_slots[15].iss_uop.bp_debug_if, slots_15.io.iss_uop.bp_debug_if connect issue_slots[15].iss_uop.xcpt_ma_if, slots_15.io.iss_uop.xcpt_ma_if connect issue_slots[15].iss_uop.xcpt_ae_if, slots_15.io.iss_uop.xcpt_ae_if connect issue_slots[15].iss_uop.xcpt_pf_if, slots_15.io.iss_uop.xcpt_pf_if connect issue_slots[15].iss_uop.fp_typ, slots_15.io.iss_uop.fp_typ connect issue_slots[15].iss_uop.fp_rm, slots_15.io.iss_uop.fp_rm connect issue_slots[15].iss_uop.fp_val, slots_15.io.iss_uop.fp_val connect issue_slots[15].iss_uop.fcn_op, slots_15.io.iss_uop.fcn_op connect issue_slots[15].iss_uop.fcn_dw, slots_15.io.iss_uop.fcn_dw connect issue_slots[15].iss_uop.frs3_en, slots_15.io.iss_uop.frs3_en connect issue_slots[15].iss_uop.lrs2_rtype, slots_15.io.iss_uop.lrs2_rtype connect issue_slots[15].iss_uop.lrs1_rtype, slots_15.io.iss_uop.lrs1_rtype connect issue_slots[15].iss_uop.dst_rtype, slots_15.io.iss_uop.dst_rtype connect issue_slots[15].iss_uop.lrs3, slots_15.io.iss_uop.lrs3 connect issue_slots[15].iss_uop.lrs2, slots_15.io.iss_uop.lrs2 connect issue_slots[15].iss_uop.lrs1, slots_15.io.iss_uop.lrs1 connect issue_slots[15].iss_uop.ldst, slots_15.io.iss_uop.ldst connect issue_slots[15].iss_uop.ldst_is_rs1, slots_15.io.iss_uop.ldst_is_rs1 connect issue_slots[15].iss_uop.csr_cmd, slots_15.io.iss_uop.csr_cmd connect issue_slots[15].iss_uop.flush_on_commit, slots_15.io.iss_uop.flush_on_commit connect issue_slots[15].iss_uop.is_unique, slots_15.io.iss_uop.is_unique connect issue_slots[15].iss_uop.uses_stq, slots_15.io.iss_uop.uses_stq connect issue_slots[15].iss_uop.uses_ldq, slots_15.io.iss_uop.uses_ldq connect issue_slots[15].iss_uop.mem_signed, slots_15.io.iss_uop.mem_signed connect issue_slots[15].iss_uop.mem_size, slots_15.io.iss_uop.mem_size connect issue_slots[15].iss_uop.mem_cmd, slots_15.io.iss_uop.mem_cmd connect issue_slots[15].iss_uop.exc_cause, slots_15.io.iss_uop.exc_cause connect issue_slots[15].iss_uop.exception, slots_15.io.iss_uop.exception connect issue_slots[15].iss_uop.stale_pdst, slots_15.io.iss_uop.stale_pdst connect issue_slots[15].iss_uop.ppred_busy, slots_15.io.iss_uop.ppred_busy connect issue_slots[15].iss_uop.prs3_busy, slots_15.io.iss_uop.prs3_busy connect issue_slots[15].iss_uop.prs2_busy, slots_15.io.iss_uop.prs2_busy connect issue_slots[15].iss_uop.prs1_busy, slots_15.io.iss_uop.prs1_busy connect issue_slots[15].iss_uop.ppred, slots_15.io.iss_uop.ppred connect issue_slots[15].iss_uop.prs3, slots_15.io.iss_uop.prs3 connect issue_slots[15].iss_uop.prs2, slots_15.io.iss_uop.prs2 connect issue_slots[15].iss_uop.prs1, slots_15.io.iss_uop.prs1 connect issue_slots[15].iss_uop.pdst, slots_15.io.iss_uop.pdst connect issue_slots[15].iss_uop.rxq_idx, slots_15.io.iss_uop.rxq_idx connect issue_slots[15].iss_uop.stq_idx, slots_15.io.iss_uop.stq_idx connect issue_slots[15].iss_uop.ldq_idx, slots_15.io.iss_uop.ldq_idx connect issue_slots[15].iss_uop.rob_idx, slots_15.io.iss_uop.rob_idx connect issue_slots[15].iss_uop.fp_ctrl.vec, slots_15.io.iss_uop.fp_ctrl.vec connect issue_slots[15].iss_uop.fp_ctrl.wflags, slots_15.io.iss_uop.fp_ctrl.wflags connect issue_slots[15].iss_uop.fp_ctrl.sqrt, slots_15.io.iss_uop.fp_ctrl.sqrt connect issue_slots[15].iss_uop.fp_ctrl.div, slots_15.io.iss_uop.fp_ctrl.div connect issue_slots[15].iss_uop.fp_ctrl.fma, slots_15.io.iss_uop.fp_ctrl.fma connect issue_slots[15].iss_uop.fp_ctrl.fastpipe, slots_15.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[15].iss_uop.fp_ctrl.toint, slots_15.io.iss_uop.fp_ctrl.toint connect issue_slots[15].iss_uop.fp_ctrl.fromint, slots_15.io.iss_uop.fp_ctrl.fromint connect issue_slots[15].iss_uop.fp_ctrl.typeTagOut, slots_15.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[15].iss_uop.fp_ctrl.typeTagIn, slots_15.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[15].iss_uop.fp_ctrl.swap23, slots_15.io.iss_uop.fp_ctrl.swap23 connect issue_slots[15].iss_uop.fp_ctrl.swap12, slots_15.io.iss_uop.fp_ctrl.swap12 connect issue_slots[15].iss_uop.fp_ctrl.ren3, slots_15.io.iss_uop.fp_ctrl.ren3 connect issue_slots[15].iss_uop.fp_ctrl.ren2, slots_15.io.iss_uop.fp_ctrl.ren2 connect issue_slots[15].iss_uop.fp_ctrl.ren1, slots_15.io.iss_uop.fp_ctrl.ren1 connect issue_slots[15].iss_uop.fp_ctrl.wen, slots_15.io.iss_uop.fp_ctrl.wen connect issue_slots[15].iss_uop.fp_ctrl.ldst, slots_15.io.iss_uop.fp_ctrl.ldst connect issue_slots[15].iss_uop.op2_sel, slots_15.io.iss_uop.op2_sel connect issue_slots[15].iss_uop.op1_sel, slots_15.io.iss_uop.op1_sel connect issue_slots[15].iss_uop.imm_packed, slots_15.io.iss_uop.imm_packed connect issue_slots[15].iss_uop.pimm, slots_15.io.iss_uop.pimm connect issue_slots[15].iss_uop.imm_sel, slots_15.io.iss_uop.imm_sel connect issue_slots[15].iss_uop.imm_rename, slots_15.io.iss_uop.imm_rename connect issue_slots[15].iss_uop.taken, slots_15.io.iss_uop.taken connect issue_slots[15].iss_uop.pc_lob, slots_15.io.iss_uop.pc_lob connect issue_slots[15].iss_uop.edge_inst, slots_15.io.iss_uop.edge_inst connect issue_slots[15].iss_uop.ftq_idx, slots_15.io.iss_uop.ftq_idx connect issue_slots[15].iss_uop.is_mov, slots_15.io.iss_uop.is_mov connect issue_slots[15].iss_uop.is_rocc, slots_15.io.iss_uop.is_rocc connect issue_slots[15].iss_uop.is_sys_pc2epc, slots_15.io.iss_uop.is_sys_pc2epc connect issue_slots[15].iss_uop.is_eret, slots_15.io.iss_uop.is_eret connect issue_slots[15].iss_uop.is_amo, slots_15.io.iss_uop.is_amo connect issue_slots[15].iss_uop.is_sfence, slots_15.io.iss_uop.is_sfence connect issue_slots[15].iss_uop.is_fencei, slots_15.io.iss_uop.is_fencei connect issue_slots[15].iss_uop.is_fence, slots_15.io.iss_uop.is_fence connect issue_slots[15].iss_uop.is_sfb, slots_15.io.iss_uop.is_sfb connect issue_slots[15].iss_uop.br_type, slots_15.io.iss_uop.br_type connect issue_slots[15].iss_uop.br_tag, slots_15.io.iss_uop.br_tag connect issue_slots[15].iss_uop.br_mask, slots_15.io.iss_uop.br_mask connect issue_slots[15].iss_uop.dis_col_sel, slots_15.io.iss_uop.dis_col_sel connect issue_slots[15].iss_uop.iw_p3_bypass_hint, slots_15.io.iss_uop.iw_p3_bypass_hint connect issue_slots[15].iss_uop.iw_p2_bypass_hint, slots_15.io.iss_uop.iw_p2_bypass_hint connect issue_slots[15].iss_uop.iw_p1_bypass_hint, slots_15.io.iss_uop.iw_p1_bypass_hint connect issue_slots[15].iss_uop.iw_p2_speculative_child, slots_15.io.iss_uop.iw_p2_speculative_child connect issue_slots[15].iss_uop.iw_p1_speculative_child, slots_15.io.iss_uop.iw_p1_speculative_child connect issue_slots[15].iss_uop.iw_issued_partial_dgen, slots_15.io.iss_uop.iw_issued_partial_dgen connect issue_slots[15].iss_uop.iw_issued_partial_agen, slots_15.io.iss_uop.iw_issued_partial_agen connect issue_slots[15].iss_uop.iw_issued, slots_15.io.iss_uop.iw_issued connect issue_slots[15].iss_uop.fu_code[0], slots_15.io.iss_uop.fu_code[0] connect issue_slots[15].iss_uop.fu_code[1], slots_15.io.iss_uop.fu_code[1] connect issue_slots[15].iss_uop.fu_code[2], slots_15.io.iss_uop.fu_code[2] connect issue_slots[15].iss_uop.fu_code[3], slots_15.io.iss_uop.fu_code[3] connect issue_slots[15].iss_uop.fu_code[4], slots_15.io.iss_uop.fu_code[4] connect issue_slots[15].iss_uop.fu_code[5], slots_15.io.iss_uop.fu_code[5] connect issue_slots[15].iss_uop.fu_code[6], slots_15.io.iss_uop.fu_code[6] connect issue_slots[15].iss_uop.fu_code[7], slots_15.io.iss_uop.fu_code[7] connect issue_slots[15].iss_uop.fu_code[8], slots_15.io.iss_uop.fu_code[8] connect issue_slots[15].iss_uop.fu_code[9], slots_15.io.iss_uop.fu_code[9] connect issue_slots[15].iss_uop.iq_type[0], slots_15.io.iss_uop.iq_type[0] connect issue_slots[15].iss_uop.iq_type[1], slots_15.io.iss_uop.iq_type[1] connect issue_slots[15].iss_uop.iq_type[2], slots_15.io.iss_uop.iq_type[2] connect issue_slots[15].iss_uop.iq_type[3], slots_15.io.iss_uop.iq_type[3] connect issue_slots[15].iss_uop.debug_pc, slots_15.io.iss_uop.debug_pc connect issue_slots[15].iss_uop.is_rvc, slots_15.io.iss_uop.is_rvc connect issue_slots[15].iss_uop.debug_inst, slots_15.io.iss_uop.debug_inst connect issue_slots[15].iss_uop.inst, slots_15.io.iss_uop.inst connect slots_15.io.grant, issue_slots[15].grant connect issue_slots[15].request, slots_15.io.request connect issue_slots[15].will_be_valid, slots_15.io.will_be_valid connect issue_slots[15].valid, slots_15.io.valid connect issue_slots[0].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[0].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[0].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[0].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[0].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[0].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[0].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[0].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[0].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[0].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[0].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[0].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[0].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[0].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[0].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[0].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[0].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[0].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[0].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[0].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[0].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[0].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[0].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[0].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[0].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[0].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[0].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[0].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[0].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[0].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[0].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[0].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[0].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[0].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[0].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[0].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[0].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[0].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[0].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[0].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[0].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[0].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[0].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[0].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[0].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[0].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[0].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[0].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[0].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[0].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[0].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[0].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[0].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[0].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[0].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[0].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[0].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[0].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[0].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[0].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[0].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[0].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[0].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[0].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[0].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[0].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[0].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[0].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[0].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[0].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[0].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[0].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[0].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[0].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[0].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[0].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[0].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[0].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[0].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[0].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[0].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[0].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[0].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[0].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[0].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[0].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[0].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[0].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[0].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[0].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[0].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[0].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[0].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[0].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[0].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[0].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[0].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[0].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[0].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[0].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[0].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[0].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[0].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[0].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[0].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[0].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[0].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[0].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[0].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[0].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[0].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[0].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[0].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[0].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[0].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[0].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[0].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[0].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[0].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[0].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[0].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[0].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[0].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[0].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[0].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[0].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[0].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[0].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[0].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[0].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[0].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[0].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[0].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[0].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[0].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[0].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[0].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[0].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[0].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[0].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[0].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[0].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[0].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[0].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[0].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[0].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[0].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[0].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[0].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[0].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[0].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[0].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[0].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[0].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[0].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[0].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[0].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[0].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[0].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[0].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[0].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[0].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[0].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[0].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[0].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[0].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[0].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[0].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[0].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[0].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[0].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[0].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[0].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[0].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[0].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[0].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[0].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[0].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[0].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[0].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[0].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[0].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[0].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[0].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[0].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[0].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[0].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[0].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[0].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[0].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[0].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[0].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[0].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[0].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[0].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[0].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[0].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[0].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[0].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[0].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[0].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[0].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[0].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[0].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[0].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[0].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[0].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[0].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[0].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[0].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[0].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[0].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[0].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[0].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[0].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[0].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[0].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[0].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[0].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[0].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[0].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[0].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[0].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[0].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[0].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[0].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[0].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[0].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[0].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[0].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[0].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[0].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[0].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[0].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[0].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[0].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[0].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[0].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[0].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[0].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[0].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[0].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[0].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[0].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[0].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[0].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[0].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[0].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[0].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[0].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[0].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[0].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[0].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[0].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[0].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[0].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[0].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[0].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[0].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[0].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[0].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[0].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[0].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[0].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[0].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[0].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[0].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[0].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[0].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[0].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[0].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[0].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[0].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[0].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[0].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[0].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[0].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[0].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[0].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[0].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[0].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[0].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[0].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[0].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[0].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[0].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[0].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[0].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[0].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[0].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[0].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[0].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[0].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[0].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[0].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[0].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[0].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[0].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[0].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[0].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[0].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[0].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[0].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[0].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[0].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[0].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[0].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[0].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[0].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[0].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[0].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[0].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[0].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[0].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[0].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[0].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[0].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[0].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[0].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[0].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[0].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[0].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[0].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[0].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[0].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[0].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[0].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[0].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[0].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[0].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[0].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[0].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[0].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[0].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[0].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[0].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[0].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[0].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[0].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[0].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[0].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[0].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[0].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[0].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[0].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[0].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[0].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[0].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[0].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[0].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[0].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[0].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[0].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[0].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[0].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[0].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[0].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[0].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[0].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[0].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[0].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[0].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[0].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[0].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[0].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[0].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[0].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[0].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[0].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[0].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[0].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[0].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[0].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[0].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[0].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[0].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[0].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[0].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[0].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[0].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[0].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[0].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[0].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[0].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[0].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[0].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[0].child_rebusys, io.child_rebusys connect issue_slots[0].squash_grant, io.squash_grant connect issue_slots[0].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[0].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[0].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[0].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[0].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[0].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[0].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[0].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[0].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[0].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[0].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[0].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[0].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[0].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[0].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[0].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[0].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[0].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[0].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[0].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[0].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[0].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[0].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[0].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[0].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[0].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[0].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[0].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[0].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[0].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[0].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[0].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[0].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[0].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[0].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[0].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[0].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[0].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[0].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[0].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[0].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[0].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[0].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[0].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[0].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[0].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[0].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[0].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[0].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[0].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[0].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[0].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[0].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[0].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[0].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[0].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[0].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[0].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[0].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[0].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[0].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[0].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[0].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[0].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[0].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[0].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[0].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[0].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[0].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[0].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[0].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[0].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[0].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[0].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[0].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[0].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[0].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[0].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[0].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[0].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[0].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[0].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[0].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[0].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[0].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[0].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[0].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[0].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[0].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[0].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[0].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[0].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[0].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[0].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[0].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[0].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[0].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[0].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[0].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[0].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[0].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[0].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[0].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[0].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[0].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[0].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[0].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[0].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[0].kill, io.flush_pipeline connect issue_slots[1].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[1].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[1].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[1].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[1].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[1].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[1].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[1].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[1].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[1].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[1].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[1].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[1].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[1].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[1].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[1].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[1].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[1].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[1].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[1].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[1].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[1].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[1].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[1].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[1].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[1].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[1].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[1].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[1].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[1].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[1].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[1].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[1].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[1].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[1].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[1].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[1].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[1].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[1].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[1].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[1].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[1].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[1].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[1].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[1].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[1].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[1].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[1].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[1].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[1].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[1].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[1].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[1].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[1].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[1].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[1].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[1].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[1].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[1].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[1].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[1].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[1].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[1].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[1].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[1].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[1].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[1].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[1].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[1].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[1].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[1].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[1].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[1].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[1].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[1].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[1].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[1].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[1].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[1].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[1].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[1].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[1].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[1].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[1].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[1].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[1].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[1].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[1].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[1].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[1].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[1].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[1].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[1].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[1].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[1].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[1].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[1].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[1].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[1].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[1].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[1].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[1].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[1].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[1].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[1].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[1].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[1].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[1].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[1].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[1].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[1].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[1].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[1].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[1].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[1].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[1].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[1].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[1].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[1].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[1].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[1].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[1].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[1].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[1].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[1].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[1].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[1].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[1].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[1].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[1].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[1].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[1].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[1].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[1].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[1].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[1].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[1].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[1].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[1].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[1].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[1].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[1].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[1].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[1].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[1].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[1].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[1].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[1].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[1].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[1].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[1].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[1].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[1].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[1].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[1].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[1].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[1].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[1].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[1].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[1].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[1].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[1].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[1].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[1].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[1].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[1].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[1].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[1].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[1].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[1].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[1].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[1].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[1].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[1].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[1].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[1].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[1].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[1].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[1].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[1].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[1].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[1].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[1].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[1].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[1].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[1].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[1].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[1].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[1].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[1].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[1].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[1].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[1].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[1].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[1].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[1].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[1].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[1].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[1].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[1].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[1].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[1].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[1].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[1].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[1].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[1].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[1].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[1].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[1].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[1].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[1].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[1].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[1].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[1].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[1].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[1].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[1].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[1].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[1].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[1].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[1].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[1].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[1].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[1].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[1].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[1].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[1].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[1].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[1].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[1].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[1].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[1].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[1].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[1].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[1].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[1].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[1].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[1].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[1].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[1].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[1].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[1].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[1].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[1].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[1].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[1].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[1].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[1].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[1].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[1].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[1].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[1].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[1].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[1].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[1].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[1].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[1].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[1].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[1].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[1].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[1].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[1].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[1].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[1].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[1].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[1].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[1].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[1].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[1].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[1].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[1].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[1].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[1].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[1].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[1].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[1].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[1].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[1].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[1].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[1].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[1].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[1].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[1].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[1].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[1].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[1].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[1].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[1].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[1].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[1].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[1].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[1].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[1].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[1].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[1].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[1].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[1].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[1].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[1].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[1].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[1].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[1].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[1].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[1].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[1].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[1].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[1].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[1].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[1].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[1].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[1].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[1].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[1].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[1].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[1].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[1].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[1].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[1].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[1].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[1].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[1].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[1].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[1].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[1].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[1].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[1].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[1].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[1].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[1].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[1].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[1].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[1].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[1].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[1].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[1].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[1].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[1].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[1].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[1].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[1].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[1].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[1].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[1].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[1].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[1].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[1].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[1].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[1].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[1].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[1].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[1].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[1].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[1].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[1].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[1].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[1].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[1].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[1].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[1].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[1].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[1].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[1].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[1].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[1].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[1].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[1].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[1].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[1].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[1].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[1].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[1].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[1].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[1].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[1].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[1].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[1].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[1].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[1].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[1].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[1].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[1].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[1].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[1].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[1].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[1].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[1].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[1].child_rebusys, io.child_rebusys connect issue_slots[1].squash_grant, io.squash_grant connect issue_slots[1].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[1].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[1].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[1].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[1].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[1].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[1].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[1].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[1].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[1].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[1].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[1].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[1].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[1].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[1].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[1].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[1].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[1].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[1].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[1].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[1].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[1].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[1].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[1].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[1].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[1].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[1].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[1].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[1].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[1].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[1].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[1].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[1].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[1].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[1].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[1].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[1].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[1].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[1].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[1].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[1].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[1].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[1].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[1].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[1].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[1].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[1].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[1].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[1].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[1].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[1].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[1].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[1].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[1].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[1].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[1].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[1].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[1].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[1].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[1].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[1].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[1].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[1].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[1].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[1].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[1].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[1].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[1].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[1].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[1].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[1].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[1].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[1].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[1].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[1].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[1].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[1].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[1].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[1].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[1].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[1].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[1].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[1].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[1].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[1].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[1].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[1].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[1].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[1].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[1].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[1].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[1].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[1].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[1].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[1].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[1].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[1].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[1].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[1].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[1].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[1].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[1].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[1].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[1].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[1].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[1].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[1].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[1].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[1].kill, io.flush_pipeline connect issue_slots[2].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[2].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[2].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[2].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[2].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[2].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[2].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[2].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[2].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[2].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[2].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[2].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[2].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[2].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[2].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[2].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[2].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[2].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[2].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[2].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[2].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[2].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[2].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[2].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[2].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[2].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[2].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[2].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[2].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[2].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[2].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[2].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[2].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[2].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[2].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[2].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[2].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[2].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[2].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[2].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[2].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[2].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[2].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[2].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[2].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[2].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[2].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[2].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[2].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[2].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[2].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[2].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[2].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[2].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[2].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[2].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[2].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[2].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[2].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[2].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[2].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[2].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[2].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[2].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[2].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[2].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[2].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[2].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[2].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[2].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[2].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[2].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[2].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[2].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[2].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[2].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[2].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[2].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[2].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[2].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[2].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[2].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[2].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[2].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[2].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[2].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[2].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[2].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[2].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[2].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[2].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[2].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[2].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[2].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[2].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[2].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[2].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[2].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[2].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[2].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[2].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[2].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[2].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[2].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[2].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[2].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[2].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[2].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[2].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[2].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[2].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[2].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[2].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[2].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[2].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[2].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[2].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[2].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[2].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[2].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[2].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[2].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[2].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[2].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[2].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[2].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[2].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[2].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[2].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[2].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[2].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[2].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[2].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[2].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[2].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[2].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[2].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[2].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[2].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[2].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[2].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[2].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[2].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[2].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[2].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[2].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[2].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[2].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[2].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[2].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[2].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[2].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[2].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[2].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[2].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[2].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[2].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[2].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[2].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[2].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[2].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[2].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[2].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[2].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[2].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[2].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[2].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[2].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[2].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[2].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[2].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[2].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[2].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[2].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[2].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[2].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[2].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[2].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[2].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[2].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[2].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[2].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[2].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[2].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[2].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[2].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[2].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[2].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[2].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[2].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[2].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[2].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[2].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[2].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[2].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[2].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[2].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[2].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[2].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[2].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[2].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[2].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[2].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[2].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[2].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[2].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[2].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[2].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[2].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[2].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[2].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[2].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[2].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[2].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[2].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[2].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[2].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[2].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[2].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[2].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[2].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[2].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[2].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[2].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[2].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[2].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[2].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[2].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[2].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[2].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[2].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[2].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[2].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[2].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[2].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[2].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[2].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[2].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[2].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[2].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[2].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[2].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[2].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[2].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[2].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[2].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[2].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[2].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[2].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[2].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[2].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[2].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[2].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[2].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[2].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[2].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[2].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[2].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[2].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[2].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[2].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[2].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[2].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[2].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[2].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[2].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[2].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[2].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[2].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[2].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[2].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[2].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[2].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[2].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[2].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[2].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[2].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[2].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[2].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[2].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[2].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[2].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[2].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[2].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[2].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[2].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[2].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[2].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[2].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[2].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[2].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[2].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[2].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[2].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[2].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[2].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[2].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[2].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[2].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[2].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[2].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[2].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[2].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[2].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[2].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[2].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[2].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[2].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[2].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[2].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[2].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[2].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[2].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[2].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[2].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[2].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[2].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[2].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[2].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[2].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[2].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[2].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[2].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[2].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[2].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[2].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[2].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[2].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[2].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[2].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[2].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[2].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[2].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[2].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[2].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[2].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[2].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[2].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[2].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[2].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[2].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[2].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[2].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[2].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[2].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[2].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[2].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[2].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[2].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[2].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[2].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[2].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[2].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[2].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[2].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[2].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[2].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[2].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[2].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[2].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[2].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[2].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[2].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[2].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[2].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[2].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[2].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[2].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[2].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[2].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[2].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[2].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[2].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[2].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[2].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[2].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[2].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[2].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[2].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[2].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[2].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[2].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[2].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[2].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[2].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[2].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[2].child_rebusys, io.child_rebusys connect issue_slots[2].squash_grant, io.squash_grant connect issue_slots[2].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[2].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[2].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[2].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[2].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[2].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[2].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[2].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[2].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[2].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[2].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[2].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[2].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[2].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[2].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[2].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[2].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[2].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[2].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[2].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[2].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[2].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[2].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[2].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[2].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[2].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[2].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[2].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[2].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[2].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[2].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[2].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[2].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[2].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[2].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[2].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[2].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[2].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[2].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[2].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[2].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[2].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[2].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[2].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[2].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[2].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[2].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[2].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[2].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[2].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[2].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[2].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[2].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[2].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[2].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[2].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[2].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[2].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[2].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[2].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[2].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[2].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[2].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[2].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[2].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[2].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[2].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[2].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[2].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[2].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[2].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[2].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[2].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[2].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[2].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[2].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[2].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[2].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[2].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[2].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[2].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[2].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[2].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[2].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[2].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[2].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[2].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[2].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[2].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[2].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[2].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[2].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[2].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[2].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[2].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[2].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[2].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[2].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[2].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[2].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[2].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[2].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[2].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[2].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[2].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[2].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[2].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[2].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[2].kill, io.flush_pipeline connect issue_slots[3].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[3].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[3].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[3].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[3].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[3].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[3].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[3].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[3].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[3].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[3].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[3].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[3].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[3].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[3].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[3].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[3].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[3].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[3].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[3].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[3].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[3].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[3].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[3].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[3].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[3].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[3].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[3].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[3].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[3].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[3].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[3].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[3].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[3].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[3].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[3].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[3].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[3].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[3].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[3].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[3].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[3].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[3].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[3].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[3].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[3].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[3].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[3].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[3].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[3].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[3].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[3].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[3].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[3].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[3].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[3].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[3].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[3].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[3].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[3].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[3].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[3].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[3].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[3].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[3].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[3].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[3].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[3].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[3].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[3].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[3].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[3].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[3].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[3].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[3].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[3].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[3].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[3].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[3].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[3].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[3].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[3].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[3].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[3].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[3].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[3].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[3].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[3].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[3].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[3].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[3].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[3].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[3].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[3].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[3].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[3].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[3].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[3].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[3].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[3].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[3].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[3].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[3].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[3].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[3].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[3].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[3].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[3].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[3].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[3].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[3].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[3].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[3].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[3].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[3].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[3].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[3].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[3].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[3].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[3].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[3].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[3].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[3].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[3].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[3].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[3].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[3].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[3].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[3].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[3].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[3].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[3].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[3].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[3].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[3].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[3].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[3].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[3].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[3].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[3].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[3].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[3].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[3].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[3].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[3].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[3].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[3].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[3].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[3].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[3].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[3].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[3].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[3].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[3].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[3].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[3].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[3].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[3].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[3].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[3].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[3].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[3].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[3].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[3].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[3].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[3].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[3].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[3].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[3].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[3].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[3].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[3].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[3].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[3].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[3].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[3].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[3].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[3].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[3].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[3].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[3].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[3].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[3].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[3].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[3].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[3].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[3].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[3].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[3].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[3].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[3].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[3].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[3].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[3].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[3].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[3].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[3].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[3].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[3].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[3].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[3].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[3].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[3].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[3].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[3].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[3].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[3].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[3].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[3].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[3].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[3].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[3].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[3].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[3].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[3].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[3].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[3].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[3].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[3].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[3].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[3].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[3].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[3].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[3].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[3].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[3].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[3].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[3].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[3].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[3].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[3].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[3].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[3].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[3].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[3].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[3].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[3].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[3].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[3].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[3].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[3].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[3].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[3].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[3].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[3].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[3].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[3].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[3].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[3].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[3].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[3].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[3].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[3].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[3].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[3].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[3].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[3].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[3].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[3].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[3].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[3].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[3].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[3].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[3].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[3].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[3].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[3].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[3].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[3].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[3].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[3].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[3].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[3].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[3].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[3].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[3].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[3].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[3].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[3].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[3].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[3].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[3].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[3].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[3].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[3].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[3].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[3].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[3].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[3].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[3].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[3].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[3].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[3].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[3].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[3].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[3].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[3].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[3].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[3].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[3].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[3].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[3].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[3].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[3].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[3].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[3].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[3].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[3].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[3].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[3].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[3].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[3].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[3].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[3].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[3].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[3].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[3].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[3].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[3].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[3].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[3].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[3].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[3].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[3].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[3].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[3].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[3].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[3].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[3].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[3].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[3].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[3].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[3].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[3].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[3].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[3].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[3].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[3].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[3].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[3].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[3].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[3].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[3].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[3].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[3].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[3].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[3].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[3].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[3].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[3].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[3].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[3].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[3].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[3].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[3].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[3].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[3].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[3].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[3].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[3].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[3].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[3].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[3].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[3].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[3].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[3].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[3].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[3].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[3].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[3].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[3].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[3].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[3].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[3].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[3].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[3].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[3].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[3].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[3].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[3].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[3].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[3].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[3].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[3].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[3].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[3].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[3].child_rebusys, io.child_rebusys connect issue_slots[3].squash_grant, io.squash_grant connect issue_slots[3].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[3].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[3].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[3].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[3].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[3].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[3].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[3].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[3].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[3].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[3].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[3].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[3].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[3].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[3].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[3].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[3].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[3].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[3].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[3].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[3].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[3].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[3].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[3].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[3].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[3].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[3].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[3].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[3].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[3].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[3].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[3].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[3].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[3].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[3].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[3].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[3].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[3].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[3].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[3].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[3].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[3].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[3].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[3].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[3].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[3].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[3].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[3].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[3].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[3].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[3].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[3].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[3].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[3].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[3].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[3].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[3].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[3].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[3].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[3].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[3].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[3].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[3].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[3].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[3].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[3].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[3].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[3].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[3].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[3].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[3].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[3].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[3].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[3].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[3].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[3].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[3].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[3].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[3].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[3].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[3].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[3].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[3].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[3].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[3].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[3].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[3].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[3].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[3].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[3].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[3].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[3].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[3].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[3].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[3].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[3].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[3].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[3].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[3].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[3].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[3].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[3].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[3].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[3].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[3].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[3].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[3].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[3].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[3].kill, io.flush_pipeline connect issue_slots[4].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[4].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[4].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[4].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[4].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[4].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[4].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[4].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[4].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[4].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[4].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[4].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[4].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[4].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[4].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[4].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[4].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[4].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[4].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[4].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[4].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[4].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[4].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[4].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[4].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[4].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[4].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[4].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[4].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[4].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[4].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[4].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[4].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[4].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[4].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[4].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[4].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[4].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[4].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[4].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[4].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[4].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[4].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[4].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[4].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[4].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[4].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[4].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[4].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[4].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[4].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[4].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[4].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[4].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[4].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[4].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[4].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[4].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[4].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[4].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[4].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[4].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[4].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[4].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[4].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[4].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[4].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[4].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[4].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[4].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[4].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[4].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[4].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[4].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[4].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[4].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[4].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[4].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[4].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[4].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[4].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[4].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[4].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[4].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[4].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[4].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[4].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[4].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[4].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[4].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[4].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[4].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[4].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[4].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[4].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[4].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[4].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[4].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[4].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[4].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[4].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[4].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[4].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[4].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[4].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[4].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[4].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[4].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[4].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[4].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[4].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[4].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[4].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[4].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[4].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[4].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[4].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[4].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[4].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[4].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[4].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[4].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[4].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[4].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[4].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[4].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[4].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[4].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[4].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[4].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[4].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[4].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[4].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[4].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[4].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[4].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[4].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[4].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[4].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[4].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[4].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[4].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[4].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[4].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[4].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[4].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[4].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[4].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[4].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[4].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[4].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[4].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[4].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[4].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[4].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[4].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[4].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[4].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[4].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[4].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[4].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[4].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[4].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[4].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[4].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[4].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[4].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[4].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[4].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[4].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[4].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[4].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[4].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[4].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[4].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[4].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[4].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[4].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[4].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[4].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[4].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[4].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[4].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[4].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[4].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[4].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[4].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[4].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[4].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[4].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[4].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[4].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[4].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[4].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[4].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[4].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[4].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[4].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[4].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[4].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[4].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[4].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[4].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[4].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[4].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[4].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[4].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[4].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[4].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[4].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[4].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[4].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[4].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[4].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[4].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[4].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[4].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[4].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[4].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[4].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[4].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[4].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[4].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[4].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[4].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[4].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[4].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[4].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[4].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[4].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[4].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[4].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[4].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[4].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[4].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[4].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[4].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[4].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[4].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[4].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[4].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[4].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[4].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[4].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[4].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[4].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[4].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[4].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[4].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[4].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[4].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[4].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[4].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[4].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[4].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[4].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[4].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[4].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[4].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[4].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[4].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[4].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[4].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[4].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[4].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[4].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[4].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[4].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[4].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[4].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[4].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[4].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[4].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[4].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[4].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[4].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[4].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[4].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[4].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[4].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[4].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[4].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[4].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[4].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[4].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[4].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[4].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[4].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[4].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[4].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[4].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[4].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[4].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[4].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[4].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[4].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[4].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[4].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[4].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[4].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[4].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[4].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[4].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[4].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[4].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[4].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[4].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[4].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[4].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[4].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[4].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[4].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[4].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[4].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[4].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[4].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[4].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[4].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[4].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[4].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[4].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[4].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[4].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[4].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[4].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[4].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[4].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[4].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[4].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[4].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[4].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[4].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[4].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[4].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[4].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[4].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[4].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[4].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[4].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[4].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[4].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[4].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[4].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[4].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[4].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[4].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[4].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[4].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[4].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[4].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[4].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[4].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[4].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[4].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[4].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[4].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[4].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[4].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[4].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[4].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[4].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[4].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[4].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[4].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[4].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[4].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[4].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[4].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[4].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[4].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[4].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[4].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[4].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[4].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[4].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[4].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[4].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[4].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[4].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[4].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[4].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[4].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[4].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[4].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[4].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[4].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[4].child_rebusys, io.child_rebusys connect issue_slots[4].squash_grant, io.squash_grant connect issue_slots[4].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[4].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[4].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[4].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[4].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[4].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[4].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[4].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[4].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[4].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[4].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[4].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[4].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[4].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[4].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[4].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[4].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[4].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[4].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[4].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[4].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[4].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[4].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[4].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[4].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[4].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[4].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[4].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[4].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[4].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[4].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[4].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[4].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[4].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[4].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[4].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[4].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[4].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[4].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[4].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[4].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[4].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[4].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[4].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[4].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[4].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[4].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[4].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[4].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[4].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[4].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[4].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[4].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[4].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[4].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[4].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[4].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[4].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[4].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[4].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[4].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[4].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[4].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[4].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[4].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[4].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[4].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[4].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[4].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[4].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[4].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[4].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[4].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[4].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[4].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[4].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[4].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[4].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[4].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[4].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[4].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[4].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[4].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[4].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[4].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[4].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[4].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[4].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[4].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[4].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[4].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[4].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[4].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[4].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[4].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[4].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[4].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[4].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[4].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[4].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[4].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[4].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[4].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[4].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[4].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[4].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[4].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[4].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[4].kill, io.flush_pipeline connect issue_slots[5].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[5].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[5].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[5].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[5].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[5].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[5].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[5].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[5].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[5].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[5].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[5].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[5].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[5].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[5].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[5].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[5].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[5].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[5].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[5].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[5].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[5].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[5].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[5].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[5].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[5].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[5].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[5].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[5].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[5].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[5].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[5].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[5].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[5].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[5].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[5].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[5].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[5].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[5].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[5].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[5].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[5].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[5].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[5].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[5].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[5].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[5].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[5].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[5].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[5].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[5].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[5].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[5].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[5].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[5].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[5].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[5].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[5].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[5].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[5].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[5].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[5].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[5].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[5].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[5].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[5].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[5].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[5].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[5].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[5].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[5].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[5].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[5].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[5].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[5].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[5].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[5].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[5].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[5].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[5].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[5].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[5].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[5].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[5].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[5].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[5].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[5].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[5].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[5].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[5].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[5].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[5].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[5].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[5].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[5].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[5].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[5].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[5].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[5].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[5].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[5].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[5].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[5].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[5].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[5].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[5].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[5].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[5].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[5].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[5].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[5].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[5].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[5].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[5].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[5].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[5].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[5].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[5].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[5].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[5].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[5].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[5].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[5].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[5].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[5].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[5].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[5].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[5].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[5].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[5].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[5].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[5].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[5].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[5].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[5].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[5].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[5].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[5].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[5].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[5].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[5].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[5].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[5].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[5].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[5].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[5].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[5].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[5].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[5].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[5].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[5].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[5].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[5].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[5].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[5].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[5].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[5].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[5].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[5].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[5].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[5].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[5].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[5].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[5].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[5].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[5].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[5].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[5].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[5].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[5].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[5].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[5].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[5].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[5].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[5].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[5].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[5].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[5].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[5].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[5].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[5].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[5].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[5].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[5].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[5].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[5].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[5].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[5].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[5].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[5].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[5].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[5].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[5].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[5].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[5].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[5].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[5].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[5].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[5].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[5].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[5].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[5].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[5].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[5].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[5].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[5].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[5].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[5].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[5].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[5].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[5].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[5].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[5].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[5].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[5].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[5].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[5].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[5].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[5].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[5].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[5].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[5].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[5].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[5].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[5].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[5].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[5].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[5].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[5].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[5].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[5].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[5].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[5].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[5].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[5].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[5].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[5].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[5].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[5].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[5].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[5].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[5].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[5].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[5].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[5].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[5].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[5].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[5].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[5].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[5].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[5].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[5].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[5].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[5].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[5].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[5].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[5].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[5].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[5].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[5].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[5].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[5].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[5].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[5].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[5].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[5].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[5].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[5].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[5].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[5].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[5].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[5].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[5].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[5].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[5].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[5].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[5].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[5].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[5].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[5].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[5].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[5].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[5].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[5].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[5].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[5].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[5].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[5].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[5].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[5].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[5].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[5].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[5].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[5].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[5].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[5].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[5].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[5].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[5].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[5].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[5].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[5].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[5].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[5].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[5].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[5].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[5].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[5].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[5].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[5].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[5].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[5].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[5].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[5].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[5].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[5].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[5].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[5].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[5].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[5].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[5].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[5].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[5].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[5].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[5].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[5].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[5].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[5].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[5].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[5].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[5].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[5].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[5].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[5].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[5].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[5].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[5].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[5].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[5].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[5].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[5].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[5].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[5].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[5].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[5].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[5].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[5].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[5].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[5].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[5].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[5].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[5].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[5].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[5].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[5].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[5].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[5].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[5].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[5].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[5].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[5].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[5].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[5].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[5].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[5].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[5].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[5].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[5].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[5].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[5].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[5].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[5].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[5].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[5].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[5].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[5].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[5].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[5].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[5].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[5].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[5].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[5].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[5].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[5].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[5].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[5].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[5].child_rebusys, io.child_rebusys connect issue_slots[5].squash_grant, io.squash_grant connect issue_slots[5].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[5].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[5].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[5].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[5].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[5].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[5].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[5].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[5].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[5].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[5].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[5].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[5].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[5].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[5].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[5].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[5].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[5].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[5].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[5].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[5].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[5].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[5].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[5].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[5].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[5].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[5].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[5].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[5].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[5].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[5].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[5].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[5].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[5].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[5].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[5].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[5].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[5].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[5].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[5].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[5].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[5].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[5].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[5].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[5].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[5].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[5].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[5].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[5].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[5].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[5].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[5].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[5].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[5].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[5].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[5].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[5].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[5].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[5].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[5].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[5].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[5].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[5].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[5].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[5].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[5].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[5].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[5].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[5].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[5].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[5].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[5].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[5].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[5].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[5].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[5].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[5].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[5].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[5].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[5].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[5].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[5].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[5].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[5].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[5].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[5].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[5].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[5].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[5].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[5].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[5].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[5].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[5].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[5].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[5].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[5].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[5].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[5].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[5].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[5].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[5].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[5].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[5].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[5].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[5].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[5].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[5].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[5].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[5].kill, io.flush_pipeline connect issue_slots[6].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[6].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[6].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[6].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[6].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[6].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[6].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[6].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[6].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[6].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[6].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[6].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[6].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[6].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[6].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[6].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[6].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[6].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[6].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[6].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[6].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[6].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[6].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[6].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[6].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[6].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[6].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[6].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[6].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[6].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[6].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[6].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[6].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[6].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[6].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[6].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[6].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[6].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[6].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[6].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[6].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[6].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[6].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[6].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[6].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[6].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[6].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[6].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[6].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[6].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[6].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[6].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[6].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[6].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[6].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[6].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[6].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[6].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[6].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[6].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[6].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[6].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[6].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[6].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[6].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[6].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[6].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[6].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[6].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[6].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[6].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[6].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[6].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[6].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[6].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[6].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[6].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[6].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[6].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[6].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[6].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[6].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[6].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[6].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[6].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[6].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[6].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[6].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[6].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[6].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[6].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[6].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[6].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[6].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[6].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[6].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[6].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[6].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[6].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[6].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[6].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[6].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[6].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[6].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[6].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[6].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[6].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[6].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[6].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[6].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[6].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[6].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[6].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[6].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[6].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[6].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[6].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[6].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[6].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[6].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[6].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[6].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[6].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[6].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[6].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[6].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[6].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[6].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[6].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[6].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[6].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[6].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[6].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[6].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[6].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[6].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[6].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[6].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[6].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[6].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[6].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[6].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[6].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[6].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[6].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[6].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[6].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[6].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[6].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[6].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[6].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[6].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[6].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[6].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[6].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[6].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[6].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[6].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[6].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[6].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[6].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[6].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[6].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[6].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[6].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[6].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[6].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[6].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[6].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[6].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[6].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[6].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[6].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[6].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[6].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[6].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[6].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[6].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[6].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[6].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[6].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[6].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[6].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[6].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[6].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[6].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[6].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[6].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[6].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[6].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[6].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[6].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[6].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[6].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[6].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[6].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[6].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[6].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[6].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[6].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[6].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[6].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[6].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[6].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[6].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[6].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[6].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[6].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[6].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[6].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[6].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[6].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[6].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[6].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[6].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[6].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[6].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[6].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[6].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[6].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[6].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[6].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[6].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[6].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[6].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[6].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[6].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[6].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[6].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[6].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[6].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[6].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[6].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[6].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[6].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[6].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[6].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[6].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[6].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[6].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[6].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[6].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[6].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[6].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[6].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[6].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[6].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[6].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[6].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[6].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[6].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[6].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[6].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[6].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[6].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[6].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[6].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[6].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[6].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[6].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[6].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[6].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[6].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[6].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[6].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[6].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[6].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[6].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[6].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[6].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[6].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[6].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[6].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[6].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[6].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[6].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[6].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[6].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[6].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[6].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[6].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[6].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[6].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[6].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[6].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[6].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[6].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[6].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[6].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[6].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[6].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[6].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[6].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[6].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[6].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[6].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[6].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[6].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[6].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[6].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[6].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[6].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[6].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[6].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[6].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[6].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[6].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[6].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[6].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[6].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[6].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[6].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[6].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[6].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[6].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[6].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[6].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[6].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[6].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[6].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[6].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[6].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[6].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[6].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[6].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[6].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[6].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[6].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[6].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[6].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[6].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[6].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[6].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[6].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[6].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[6].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[6].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[6].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[6].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[6].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[6].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[6].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[6].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[6].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[6].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[6].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[6].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[6].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[6].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[6].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[6].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[6].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[6].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[6].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[6].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[6].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[6].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[6].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[6].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[6].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[6].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[6].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[6].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[6].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[6].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[6].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[6].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[6].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[6].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[6].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[6].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[6].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[6].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[6].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[6].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[6].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[6].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[6].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[6].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[6].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[6].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[6].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[6].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[6].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[6].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[6].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[6].child_rebusys, io.child_rebusys connect issue_slots[6].squash_grant, io.squash_grant connect issue_slots[6].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[6].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[6].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[6].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[6].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[6].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[6].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[6].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[6].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[6].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[6].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[6].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[6].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[6].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[6].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[6].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[6].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[6].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[6].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[6].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[6].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[6].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[6].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[6].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[6].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[6].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[6].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[6].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[6].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[6].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[6].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[6].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[6].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[6].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[6].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[6].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[6].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[6].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[6].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[6].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[6].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[6].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[6].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[6].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[6].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[6].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[6].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[6].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[6].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[6].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[6].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[6].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[6].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[6].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[6].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[6].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[6].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[6].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[6].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[6].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[6].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[6].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[6].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[6].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[6].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[6].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[6].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[6].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[6].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[6].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[6].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[6].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[6].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[6].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[6].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[6].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[6].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[6].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[6].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[6].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[6].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[6].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[6].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[6].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[6].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[6].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[6].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[6].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[6].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[6].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[6].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[6].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[6].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[6].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[6].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[6].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[6].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[6].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[6].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[6].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[6].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[6].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[6].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[6].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[6].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[6].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[6].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[6].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[6].kill, io.flush_pipeline connect issue_slots[7].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[7].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[7].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[7].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[7].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[7].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[7].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[7].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[7].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[7].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[7].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[7].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[7].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[7].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[7].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[7].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[7].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[7].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[7].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[7].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[7].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[7].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[7].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[7].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[7].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[7].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[7].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[7].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[7].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[7].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[7].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[7].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[7].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[7].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[7].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[7].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[7].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[7].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[7].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[7].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[7].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[7].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[7].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[7].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[7].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[7].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[7].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[7].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[7].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[7].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[7].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[7].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[7].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[7].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[7].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[7].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[7].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[7].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[7].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[7].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[7].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[7].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[7].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[7].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[7].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[7].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[7].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[7].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[7].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[7].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[7].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[7].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[7].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[7].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[7].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[7].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[7].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[7].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[7].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[7].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[7].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[7].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[7].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[7].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[7].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[7].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[7].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[7].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[7].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[7].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[7].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[7].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[7].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[7].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[7].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[7].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[7].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[7].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[7].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[7].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[7].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[7].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[7].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[7].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[7].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[7].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[7].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[7].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[7].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[7].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[7].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[7].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[7].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[7].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[7].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[7].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[7].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[7].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[7].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[7].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[7].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[7].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[7].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[7].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[7].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[7].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[7].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[7].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[7].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[7].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[7].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[7].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[7].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[7].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[7].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[7].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[7].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[7].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[7].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[7].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[7].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[7].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[7].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[7].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[7].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[7].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[7].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[7].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[7].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[7].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[7].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[7].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[7].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[7].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[7].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[7].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[7].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[7].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[7].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[7].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[7].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[7].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[7].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[7].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[7].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[7].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[7].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[7].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[7].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[7].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[7].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[7].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[7].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[7].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[7].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[7].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[7].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[7].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[7].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[7].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[7].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[7].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[7].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[7].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[7].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[7].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[7].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[7].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[7].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[7].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[7].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[7].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[7].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[7].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[7].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[7].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[7].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[7].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[7].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[7].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[7].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[7].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[7].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[7].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[7].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[7].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[7].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[7].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[7].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[7].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[7].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[7].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[7].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[7].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[7].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[7].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[7].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[7].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[7].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[7].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[7].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[7].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[7].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[7].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[7].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[7].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[7].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[7].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[7].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[7].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[7].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[7].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[7].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[7].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[7].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[7].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[7].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[7].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[7].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[7].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[7].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[7].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[7].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[7].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[7].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[7].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[7].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[7].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[7].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[7].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[7].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[7].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[7].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[7].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[7].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[7].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[7].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[7].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[7].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[7].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[7].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[7].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[7].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[7].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[7].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[7].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[7].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[7].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[7].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[7].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[7].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[7].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[7].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[7].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[7].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[7].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[7].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[7].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[7].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[7].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[7].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[7].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[7].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[7].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[7].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[7].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[7].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[7].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[7].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[7].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[7].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[7].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[7].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[7].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[7].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[7].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[7].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[7].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[7].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[7].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[7].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[7].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[7].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[7].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[7].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[7].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[7].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[7].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[7].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[7].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[7].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[7].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[7].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[7].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[7].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[7].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[7].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[7].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[7].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[7].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[7].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[7].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[7].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[7].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[7].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[7].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[7].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[7].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[7].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[7].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[7].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[7].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[7].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[7].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[7].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[7].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[7].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[7].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[7].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[7].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[7].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[7].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[7].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[7].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[7].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[7].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[7].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[7].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[7].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[7].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[7].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[7].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[7].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[7].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[7].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[7].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[7].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[7].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[7].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[7].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[7].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[7].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[7].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[7].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[7].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[7].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[7].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[7].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[7].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[7].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[7].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[7].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[7].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[7].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[7].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[7].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[7].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[7].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[7].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[7].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[7].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[7].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[7].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[7].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[7].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[7].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[7].child_rebusys, io.child_rebusys connect issue_slots[7].squash_grant, io.squash_grant connect issue_slots[7].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[7].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[7].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[7].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[7].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[7].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[7].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[7].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[7].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[7].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[7].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[7].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[7].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[7].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[7].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[7].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[7].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[7].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[7].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[7].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[7].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[7].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[7].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[7].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[7].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[7].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[7].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[7].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[7].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[7].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[7].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[7].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[7].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[7].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[7].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[7].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[7].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[7].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[7].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[7].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[7].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[7].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[7].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[7].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[7].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[7].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[7].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[7].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[7].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[7].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[7].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[7].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[7].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[7].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[7].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[7].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[7].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[7].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[7].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[7].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[7].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[7].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[7].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[7].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[7].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[7].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[7].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[7].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[7].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[7].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[7].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[7].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[7].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[7].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[7].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[7].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[7].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[7].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[7].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[7].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[7].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[7].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[7].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[7].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[7].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[7].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[7].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[7].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[7].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[7].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[7].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[7].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[7].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[7].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[7].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[7].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[7].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[7].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[7].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[7].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[7].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[7].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[7].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[7].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[7].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[7].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[7].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[7].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[7].kill, io.flush_pipeline connect issue_slots[8].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[8].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[8].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[8].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[8].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[8].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[8].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[8].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[8].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[8].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[8].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[8].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[8].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[8].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[8].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[8].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[8].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[8].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[8].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[8].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[8].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[8].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[8].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[8].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[8].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[8].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[8].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[8].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[8].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[8].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[8].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[8].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[8].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[8].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[8].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[8].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[8].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[8].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[8].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[8].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[8].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[8].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[8].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[8].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[8].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[8].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[8].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[8].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[8].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[8].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[8].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[8].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[8].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[8].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[8].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[8].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[8].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[8].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[8].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[8].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[8].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[8].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[8].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[8].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[8].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[8].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[8].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[8].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[8].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[8].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[8].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[8].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[8].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[8].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[8].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[8].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[8].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[8].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[8].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[8].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[8].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[8].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[8].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[8].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[8].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[8].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[8].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[8].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[8].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[8].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[8].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[8].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[8].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[8].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[8].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[8].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[8].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[8].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[8].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[8].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[8].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[8].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[8].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[8].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[8].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[8].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[8].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[8].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[8].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[8].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[8].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[8].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[8].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[8].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[8].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[8].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[8].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[8].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[8].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[8].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[8].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[8].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[8].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[8].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[8].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[8].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[8].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[8].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[8].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[8].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[8].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[8].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[8].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[8].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[8].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[8].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[8].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[8].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[8].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[8].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[8].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[8].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[8].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[8].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[8].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[8].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[8].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[8].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[8].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[8].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[8].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[8].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[8].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[8].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[8].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[8].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[8].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[8].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[8].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[8].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[8].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[8].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[8].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[8].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[8].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[8].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[8].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[8].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[8].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[8].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[8].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[8].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[8].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[8].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[8].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[8].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[8].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[8].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[8].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[8].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[8].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[8].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[8].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[8].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[8].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[8].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[8].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[8].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[8].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[8].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[8].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[8].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[8].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[8].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[8].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[8].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[8].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[8].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[8].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[8].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[8].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[8].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[8].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[8].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[8].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[8].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[8].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[8].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[8].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[8].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[8].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[8].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[8].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[8].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[8].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[8].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[8].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[8].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[8].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[8].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[8].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[8].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[8].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[8].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[8].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[8].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[8].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[8].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[8].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[8].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[8].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[8].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[8].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[8].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[8].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[8].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[8].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[8].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[8].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[8].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[8].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[8].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[8].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[8].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[8].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[8].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[8].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[8].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[8].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[8].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[8].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[8].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[8].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[8].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[8].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[8].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[8].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[8].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[8].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[8].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[8].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[8].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[8].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[8].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[8].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[8].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[8].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[8].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[8].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[8].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[8].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[8].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[8].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[8].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[8].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[8].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[8].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[8].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[8].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[8].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[8].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[8].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[8].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[8].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[8].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[8].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[8].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[8].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[8].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[8].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[8].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[8].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[8].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[8].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[8].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[8].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[8].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[8].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[8].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[8].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[8].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[8].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[8].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[8].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[8].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[8].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[8].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[8].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[8].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[8].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[8].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[8].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[8].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[8].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[8].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[8].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[8].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[8].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[8].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[8].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[8].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[8].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[8].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[8].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[8].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[8].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[8].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[8].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[8].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[8].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[8].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[8].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[8].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[8].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[8].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[8].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[8].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[8].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[8].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[8].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[8].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[8].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[8].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[8].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[8].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[8].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[8].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[8].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[8].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[8].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[8].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[8].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[8].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[8].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[8].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[8].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[8].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[8].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[8].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[8].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[8].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[8].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[8].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[8].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[8].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[8].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[8].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[8].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[8].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[8].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[8].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[8].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[8].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[8].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[8].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[8].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[8].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[8].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[8].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[8].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[8].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[8].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[8].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[8].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[8].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[8].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[8].child_rebusys, io.child_rebusys connect issue_slots[8].squash_grant, io.squash_grant connect issue_slots[8].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[8].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[8].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[8].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[8].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[8].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[8].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[8].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[8].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[8].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[8].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[8].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[8].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[8].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[8].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[8].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[8].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[8].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[8].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[8].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[8].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[8].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[8].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[8].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[8].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[8].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[8].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[8].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[8].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[8].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[8].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[8].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[8].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[8].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[8].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[8].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[8].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[8].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[8].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[8].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[8].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[8].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[8].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[8].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[8].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[8].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[8].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[8].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[8].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[8].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[8].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[8].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[8].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[8].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[8].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[8].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[8].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[8].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[8].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[8].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[8].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[8].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[8].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[8].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[8].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[8].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[8].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[8].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[8].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[8].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[8].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[8].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[8].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[8].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[8].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[8].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[8].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[8].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[8].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[8].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[8].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[8].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[8].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[8].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[8].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[8].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[8].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[8].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[8].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[8].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[8].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[8].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[8].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[8].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[8].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[8].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[8].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[8].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[8].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[8].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[8].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[8].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[8].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[8].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[8].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[8].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[8].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[8].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[8].kill, io.flush_pipeline connect issue_slots[9].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[9].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[9].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[9].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[9].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[9].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[9].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[9].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[9].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[9].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[9].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[9].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[9].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[9].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[9].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[9].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[9].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[9].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[9].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[9].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[9].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[9].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[9].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[9].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[9].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[9].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[9].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[9].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[9].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[9].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[9].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[9].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[9].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[9].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[9].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[9].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[9].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[9].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[9].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[9].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[9].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[9].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[9].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[9].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[9].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[9].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[9].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[9].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[9].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[9].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[9].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[9].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[9].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[9].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[9].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[9].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[9].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[9].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[9].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[9].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[9].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[9].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[9].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[9].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[9].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[9].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[9].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[9].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[9].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[9].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[9].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[9].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[9].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[9].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[9].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[9].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[9].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[9].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[9].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[9].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[9].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[9].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[9].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[9].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[9].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[9].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[9].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[9].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[9].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[9].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[9].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[9].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[9].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[9].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[9].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[9].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[9].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[9].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[9].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[9].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[9].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[9].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[9].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[9].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[9].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[9].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[9].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[9].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[9].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[9].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[9].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[9].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[9].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[9].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[9].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[9].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[9].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[9].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[9].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[9].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[9].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[9].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[9].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[9].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[9].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[9].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[9].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[9].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[9].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[9].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[9].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[9].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[9].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[9].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[9].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[9].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[9].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[9].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[9].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[9].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[9].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[9].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[9].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[9].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[9].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[9].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[9].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[9].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[9].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[9].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[9].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[9].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[9].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[9].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[9].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[9].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[9].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[9].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[9].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[9].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[9].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[9].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[9].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[9].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[9].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[9].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[9].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[9].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[9].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[9].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[9].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[9].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[9].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[9].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[9].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[9].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[9].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[9].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[9].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[9].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[9].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[9].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[9].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[9].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[9].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[9].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[9].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[9].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[9].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[9].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[9].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[9].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[9].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[9].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[9].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[9].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[9].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[9].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[9].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[9].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[9].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[9].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[9].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[9].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[9].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[9].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[9].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[9].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[9].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[9].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[9].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[9].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[9].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[9].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[9].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[9].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[9].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[9].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[9].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[9].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[9].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[9].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[9].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[9].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[9].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[9].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[9].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[9].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[9].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[9].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[9].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[9].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[9].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[9].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[9].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[9].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[9].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[9].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[9].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[9].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[9].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[9].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[9].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[9].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[9].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[9].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[9].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[9].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[9].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[9].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[9].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[9].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[9].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[9].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[9].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[9].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[9].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[9].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[9].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[9].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[9].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[9].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[9].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[9].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[9].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[9].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[9].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[9].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[9].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[9].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[9].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[9].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[9].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[9].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[9].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[9].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[9].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[9].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[9].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[9].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[9].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[9].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[9].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[9].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[9].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[9].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[9].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[9].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[9].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[9].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[9].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[9].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[9].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[9].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[9].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[9].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[9].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[9].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[9].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[9].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[9].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[9].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[9].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[9].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[9].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[9].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[9].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[9].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[9].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[9].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[9].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[9].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[9].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[9].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[9].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[9].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[9].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[9].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[9].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[9].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[9].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[9].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[9].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[9].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[9].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[9].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[9].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[9].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[9].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[9].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[9].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[9].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[9].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[9].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[9].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[9].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[9].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[9].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[9].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[9].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[9].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[9].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[9].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[9].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[9].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[9].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[9].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[9].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[9].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[9].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[9].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[9].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[9].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[9].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[9].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[9].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[9].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[9].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[9].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[9].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[9].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[9].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[9].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[9].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[9].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[9].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[9].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[9].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[9].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[9].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[9].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[9].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[9].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[9].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[9].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[9].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[9].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[9].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[9].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[9].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[9].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[9].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[9].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[9].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[9].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[9].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[9].child_rebusys, io.child_rebusys connect issue_slots[9].squash_grant, io.squash_grant connect issue_slots[9].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[9].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[9].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[9].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[9].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[9].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[9].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[9].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[9].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[9].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[9].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[9].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[9].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[9].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[9].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[9].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[9].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[9].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[9].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[9].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[9].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[9].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[9].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[9].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[9].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[9].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[9].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[9].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[9].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[9].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[9].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[9].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[9].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[9].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[9].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[9].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[9].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[9].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[9].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[9].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[9].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[9].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[9].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[9].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[9].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[9].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[9].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[9].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[9].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[9].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[9].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[9].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[9].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[9].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[9].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[9].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[9].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[9].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[9].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[9].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[9].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[9].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[9].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[9].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[9].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[9].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[9].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[9].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[9].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[9].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[9].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[9].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[9].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[9].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[9].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[9].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[9].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[9].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[9].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[9].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[9].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[9].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[9].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[9].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[9].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[9].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[9].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[9].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[9].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[9].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[9].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[9].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[9].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[9].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[9].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[9].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[9].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[9].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[9].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[9].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[9].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[9].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[9].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[9].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[9].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[9].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[9].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[9].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[9].kill, io.flush_pipeline connect issue_slots[10].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[10].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[10].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[10].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[10].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[10].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[10].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[10].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[10].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[10].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[10].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[10].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[10].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[10].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[10].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[10].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[10].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[10].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[10].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[10].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[10].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[10].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[10].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[10].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[10].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[10].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[10].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[10].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[10].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[10].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[10].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[10].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[10].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[10].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[10].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[10].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[10].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[10].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[10].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[10].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[10].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[10].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[10].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[10].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[10].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[10].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[10].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[10].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[10].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[10].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[10].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[10].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[10].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[10].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[10].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[10].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[10].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[10].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[10].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[10].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[10].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[10].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[10].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[10].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[10].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[10].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[10].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[10].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[10].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[10].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[10].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[10].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[10].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[10].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[10].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[10].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[10].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[10].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[10].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[10].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[10].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[10].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[10].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[10].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[10].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[10].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[10].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[10].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[10].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[10].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[10].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[10].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[10].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[10].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[10].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[10].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[10].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[10].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[10].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[10].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[10].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[10].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[10].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[10].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[10].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[10].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[10].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[10].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[10].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[10].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[10].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[10].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[10].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[10].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[10].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[10].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[10].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[10].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[10].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[10].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[10].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[10].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[10].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[10].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[10].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[10].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[10].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[10].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[10].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[10].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[10].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[10].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[10].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[10].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[10].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[10].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[10].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[10].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[10].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[10].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[10].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[10].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[10].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[10].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[10].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[10].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[10].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[10].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[10].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[10].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[10].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[10].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[10].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[10].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[10].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[10].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[10].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[10].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[10].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[10].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[10].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[10].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[10].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[10].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[10].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[10].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[10].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[10].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[10].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[10].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[10].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[10].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[10].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[10].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[10].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[10].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[10].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[10].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[10].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[10].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[10].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[10].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[10].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[10].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[10].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[10].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[10].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[10].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[10].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[10].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[10].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[10].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[10].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[10].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[10].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[10].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[10].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[10].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[10].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[10].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[10].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[10].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[10].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[10].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[10].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[10].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[10].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[10].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[10].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[10].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[10].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[10].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[10].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[10].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[10].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[10].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[10].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[10].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[10].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[10].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[10].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[10].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[10].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[10].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[10].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[10].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[10].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[10].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[10].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[10].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[10].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[10].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[10].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[10].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[10].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[10].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[10].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[10].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[10].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[10].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[10].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[10].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[10].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[10].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[10].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[10].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[10].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[10].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[10].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[10].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[10].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[10].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[10].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[10].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[10].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[10].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[10].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[10].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[10].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[10].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[10].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[10].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[10].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[10].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[10].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[10].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[10].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[10].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[10].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[10].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[10].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[10].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[10].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[10].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[10].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[10].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[10].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[10].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[10].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[10].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[10].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[10].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[10].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[10].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[10].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[10].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[10].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[10].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[10].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[10].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[10].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[10].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[10].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[10].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[10].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[10].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[10].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[10].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[10].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[10].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[10].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[10].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[10].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[10].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[10].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[10].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[10].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[10].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[10].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[10].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[10].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[10].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[10].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[10].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[10].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[10].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[10].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[10].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[10].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[10].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[10].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[10].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[10].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[10].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[10].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[10].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[10].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[10].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[10].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[10].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[10].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[10].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[10].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[10].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[10].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[10].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[10].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[10].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[10].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[10].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[10].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[10].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[10].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[10].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[10].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[10].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[10].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[10].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[10].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[10].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[10].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[10].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[10].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[10].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[10].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[10].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[10].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[10].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[10].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[10].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[10].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[10].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[10].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[10].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[10].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[10].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[10].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[10].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[10].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[10].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[10].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[10].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[10].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[10].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[10].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[10].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[10].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[10].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[10].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[10].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[10].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[10].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[10].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[10].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[10].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[10].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[10].child_rebusys, io.child_rebusys connect issue_slots[10].squash_grant, io.squash_grant connect issue_slots[10].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[10].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[10].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[10].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[10].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[10].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[10].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[10].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[10].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[10].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[10].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[10].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[10].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[10].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[10].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[10].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[10].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[10].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[10].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[10].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[10].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[10].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[10].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[10].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[10].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[10].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[10].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[10].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[10].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[10].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[10].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[10].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[10].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[10].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[10].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[10].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[10].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[10].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[10].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[10].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[10].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[10].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[10].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[10].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[10].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[10].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[10].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[10].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[10].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[10].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[10].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[10].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[10].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[10].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[10].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[10].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[10].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[10].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[10].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[10].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[10].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[10].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[10].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[10].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[10].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[10].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[10].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[10].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[10].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[10].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[10].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[10].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[10].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[10].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[10].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[10].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[10].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[10].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[10].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[10].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[10].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[10].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[10].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[10].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[10].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[10].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[10].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[10].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[10].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[10].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[10].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[10].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[10].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[10].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[10].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[10].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[10].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[10].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[10].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[10].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[10].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[10].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[10].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[10].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[10].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[10].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[10].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[10].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[10].kill, io.flush_pipeline connect issue_slots[11].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[11].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[11].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[11].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[11].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[11].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[11].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[11].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[11].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[11].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[11].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[11].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[11].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[11].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[11].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[11].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[11].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[11].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[11].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[11].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[11].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[11].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[11].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[11].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[11].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[11].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[11].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[11].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[11].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[11].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[11].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[11].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[11].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[11].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[11].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[11].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[11].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[11].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[11].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[11].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[11].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[11].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[11].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[11].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[11].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[11].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[11].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[11].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[11].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[11].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[11].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[11].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[11].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[11].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[11].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[11].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[11].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[11].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[11].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[11].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[11].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[11].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[11].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[11].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[11].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[11].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[11].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[11].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[11].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[11].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[11].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[11].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[11].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[11].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[11].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[11].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[11].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[11].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[11].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[11].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[11].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[11].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[11].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[11].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[11].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[11].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[11].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[11].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[11].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[11].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[11].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[11].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[11].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[11].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[11].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[11].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[11].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[11].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[11].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[11].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[11].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[11].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[11].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[11].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[11].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[11].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[11].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[11].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[11].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[11].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[11].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[11].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[11].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[11].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[11].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[11].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[11].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[11].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[11].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[11].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[11].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[11].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[11].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[11].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[11].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[11].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[11].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[11].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[11].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[11].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[11].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[11].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[11].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[11].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[11].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[11].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[11].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[11].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[11].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[11].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[11].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[11].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[11].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[11].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[11].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[11].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[11].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[11].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[11].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[11].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[11].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[11].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[11].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[11].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[11].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[11].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[11].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[11].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[11].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[11].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[11].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[11].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[11].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[11].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[11].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[11].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[11].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[11].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[11].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[11].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[11].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[11].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[11].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[11].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[11].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[11].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[11].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[11].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[11].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[11].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[11].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[11].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[11].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[11].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[11].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[11].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[11].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[11].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[11].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[11].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[11].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[11].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[11].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[11].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[11].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[11].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[11].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[11].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[11].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[11].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[11].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[11].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[11].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[11].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[11].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[11].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[11].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[11].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[11].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[11].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[11].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[11].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[11].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[11].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[11].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[11].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[11].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[11].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[11].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[11].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[11].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[11].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[11].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[11].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[11].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[11].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[11].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[11].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[11].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[11].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[11].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[11].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[11].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[11].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[11].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[11].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[11].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[11].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[11].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[11].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[11].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[11].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[11].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[11].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[11].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[11].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[11].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[11].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[11].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[11].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[11].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[11].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[11].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[11].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[11].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[11].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[11].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[11].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[11].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[11].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[11].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[11].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[11].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[11].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[11].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[11].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[11].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[11].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[11].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[11].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[11].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[11].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[11].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[11].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[11].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[11].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[11].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[11].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[11].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[11].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[11].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[11].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[11].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[11].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[11].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[11].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[11].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[11].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[11].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[11].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[11].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[11].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[11].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[11].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[11].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[11].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[11].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[11].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[11].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[11].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[11].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[11].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[11].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[11].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[11].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[11].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[11].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[11].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[11].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[11].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[11].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[11].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[11].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[11].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[11].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[11].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[11].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[11].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[11].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[11].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[11].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[11].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[11].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[11].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[11].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[11].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[11].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[11].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[11].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[11].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[11].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[11].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[11].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[11].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[11].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[11].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[11].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[11].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[11].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[11].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[11].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[11].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[11].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[11].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[11].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[11].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[11].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[11].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[11].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[11].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[11].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[11].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[11].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[11].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[11].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[11].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[11].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[11].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[11].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[11].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[11].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[11].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[11].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[11].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[11].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[11].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[11].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[11].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[11].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[11].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[11].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[11].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[11].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[11].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[11].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[11].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[11].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[11].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[11].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[11].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[11].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[11].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[11].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[11].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[11].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[11].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[11].child_rebusys, io.child_rebusys connect issue_slots[11].squash_grant, io.squash_grant connect issue_slots[11].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[11].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[11].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[11].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[11].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[11].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[11].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[11].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[11].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[11].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[11].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[11].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[11].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[11].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[11].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[11].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[11].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[11].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[11].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[11].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[11].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[11].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[11].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[11].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[11].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[11].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[11].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[11].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[11].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[11].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[11].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[11].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[11].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[11].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[11].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[11].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[11].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[11].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[11].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[11].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[11].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[11].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[11].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[11].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[11].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[11].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[11].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[11].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[11].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[11].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[11].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[11].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[11].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[11].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[11].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[11].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[11].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[11].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[11].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[11].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[11].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[11].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[11].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[11].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[11].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[11].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[11].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[11].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[11].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[11].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[11].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[11].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[11].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[11].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[11].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[11].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[11].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[11].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[11].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[11].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[11].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[11].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[11].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[11].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[11].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[11].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[11].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[11].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[11].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[11].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[11].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[11].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[11].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[11].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[11].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[11].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[11].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[11].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[11].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[11].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[11].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[11].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[11].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[11].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[11].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[11].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[11].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[11].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[11].kill, io.flush_pipeline connect issue_slots[12].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[12].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[12].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[12].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[12].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[12].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[12].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[12].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[12].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[12].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[12].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[12].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[12].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[12].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[12].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[12].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[12].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[12].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[12].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[12].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[12].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[12].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[12].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[12].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[12].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[12].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[12].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[12].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[12].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[12].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[12].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[12].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[12].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[12].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[12].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[12].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[12].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[12].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[12].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[12].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[12].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[12].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[12].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[12].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[12].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[12].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[12].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[12].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[12].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[12].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[12].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[12].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[12].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[12].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[12].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[12].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[12].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[12].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[12].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[12].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[12].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[12].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[12].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[12].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[12].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[12].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[12].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[12].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[12].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[12].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[12].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[12].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[12].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[12].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[12].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[12].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[12].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[12].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[12].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[12].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[12].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[12].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[12].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[12].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[12].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[12].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[12].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[12].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[12].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[12].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[12].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[12].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[12].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[12].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[12].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[12].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[12].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[12].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[12].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[12].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[12].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[12].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[12].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[12].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[12].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[12].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[12].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[12].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[12].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[12].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[12].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[12].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[12].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[12].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[12].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[12].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[12].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[12].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[12].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[12].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[12].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[12].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[12].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[12].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[12].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[12].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[12].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[12].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[12].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[12].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[12].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[12].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[12].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[12].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[12].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[12].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[12].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[12].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[12].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[12].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[12].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[12].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[12].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[12].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[12].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[12].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[12].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[12].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[12].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[12].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[12].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[12].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[12].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[12].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[12].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[12].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[12].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[12].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[12].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[12].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[12].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[12].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[12].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[12].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[12].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[12].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[12].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[12].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[12].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[12].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[12].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[12].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[12].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[12].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[12].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[12].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[12].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[12].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[12].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[12].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[12].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[12].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[12].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[12].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[12].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[12].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[12].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[12].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[12].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[12].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[12].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[12].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[12].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[12].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[12].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[12].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[12].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[12].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[12].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[12].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[12].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[12].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[12].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[12].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[12].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[12].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[12].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[12].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[12].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[12].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[12].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[12].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[12].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[12].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[12].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[12].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[12].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[12].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[12].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[12].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[12].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[12].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[12].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[12].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[12].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[12].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[12].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[12].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[12].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[12].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[12].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[12].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[12].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[12].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[12].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[12].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[12].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[12].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[12].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[12].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[12].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[12].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[12].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[12].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[12].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[12].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[12].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[12].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[12].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[12].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[12].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[12].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[12].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[12].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[12].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[12].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[12].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[12].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[12].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[12].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[12].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[12].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[12].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[12].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[12].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[12].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[12].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[12].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[12].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[12].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[12].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[12].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[12].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[12].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[12].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[12].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[12].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[12].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[12].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[12].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[12].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[12].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[12].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[12].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[12].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[12].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[12].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[12].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[12].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[12].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[12].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[12].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[12].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[12].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[12].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[12].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[12].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[12].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[12].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[12].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[12].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[12].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[12].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[12].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[12].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[12].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[12].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[12].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[12].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[12].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[12].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[12].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[12].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[12].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[12].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[12].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[12].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[12].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[12].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[12].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[12].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[12].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[12].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[12].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[12].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[12].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[12].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[12].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[12].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[12].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[12].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[12].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[12].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[12].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[12].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[12].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[12].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[12].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[12].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[12].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[12].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[12].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[12].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[12].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[12].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[12].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[12].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[12].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[12].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[12].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[12].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[12].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[12].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[12].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[12].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[12].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[12].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[12].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[12].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[12].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[12].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[12].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[12].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[12].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[12].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[12].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[12].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[12].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[12].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[12].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[12].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[12].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[12].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[12].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[12].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[12].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[12].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[12].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[12].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[12].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[12].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[12].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[12].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[12].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[12].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[12].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[12].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[12].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[12].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[12].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[12].child_rebusys, io.child_rebusys connect issue_slots[12].squash_grant, io.squash_grant connect issue_slots[12].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[12].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[12].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[12].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[12].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[12].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[12].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[12].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[12].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[12].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[12].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[12].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[12].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[12].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[12].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[12].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[12].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[12].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[12].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[12].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[12].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[12].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[12].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[12].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[12].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[12].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[12].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[12].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[12].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[12].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[12].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[12].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[12].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[12].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[12].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[12].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[12].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[12].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[12].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[12].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[12].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[12].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[12].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[12].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[12].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[12].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[12].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[12].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[12].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[12].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[12].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[12].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[12].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[12].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[12].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[12].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[12].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[12].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[12].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[12].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[12].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[12].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[12].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[12].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[12].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[12].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[12].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[12].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[12].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[12].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[12].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[12].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[12].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[12].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[12].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[12].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[12].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[12].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[12].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[12].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[12].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[12].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[12].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[12].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[12].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[12].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[12].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[12].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[12].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[12].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[12].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[12].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[12].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[12].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[12].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[12].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[12].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[12].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[12].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[12].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[12].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[12].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[12].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[12].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[12].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[12].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[12].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[12].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[12].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[12].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[12].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[12].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[12].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[12].kill, io.flush_pipeline connect issue_slots[13].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[13].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[13].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[13].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[13].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[13].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[13].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[13].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[13].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[13].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[13].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[13].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[13].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[13].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[13].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[13].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[13].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[13].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[13].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[13].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[13].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[13].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[13].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[13].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[13].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[13].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[13].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[13].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[13].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[13].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[13].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[13].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[13].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[13].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[13].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[13].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[13].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[13].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[13].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[13].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[13].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[13].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[13].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[13].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[13].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[13].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[13].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[13].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[13].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[13].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[13].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[13].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[13].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[13].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[13].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[13].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[13].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[13].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[13].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[13].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[13].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[13].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[13].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[13].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[13].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[13].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[13].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[13].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[13].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[13].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[13].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[13].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[13].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[13].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[13].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[13].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[13].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[13].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[13].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[13].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[13].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[13].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[13].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[13].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[13].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[13].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[13].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[13].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[13].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[13].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[13].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[13].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[13].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[13].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[13].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[13].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[13].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[13].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[13].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[13].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[13].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[13].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[13].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[13].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[13].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[13].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[13].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[13].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[13].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[13].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[13].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[13].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[13].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[13].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[13].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[13].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[13].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[13].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[13].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[13].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[13].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[13].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[13].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[13].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[13].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[13].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[13].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[13].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[13].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[13].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[13].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[13].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[13].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[13].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[13].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[13].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[13].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[13].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[13].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[13].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[13].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[13].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[13].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[13].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[13].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[13].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[13].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[13].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[13].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[13].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[13].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[13].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[13].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[13].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[13].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[13].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[13].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[13].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[13].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[13].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[13].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[13].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[13].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[13].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[13].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[13].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[13].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[13].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[13].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[13].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[13].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[13].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[13].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[13].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[13].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[13].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[13].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[13].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[13].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[13].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[13].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[13].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[13].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[13].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[13].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[13].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[13].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[13].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[13].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[13].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[13].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[13].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[13].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[13].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[13].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[13].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[13].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[13].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[13].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[13].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[13].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[13].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[13].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[13].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[13].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[13].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[13].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[13].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[13].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[13].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[13].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[13].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[13].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[13].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[13].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[13].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[13].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[13].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[13].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[13].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[13].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[13].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[13].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[13].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[13].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[13].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[13].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[13].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[13].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[13].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[13].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[13].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[13].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[13].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[13].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[13].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[13].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[13].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[13].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[13].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[13].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[13].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[13].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[13].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[13].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[13].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[13].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[13].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[13].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[13].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[13].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[13].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[13].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[13].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[13].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[13].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[13].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[13].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[13].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[13].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[13].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[13].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[13].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[13].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[13].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[13].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[13].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[13].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[13].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[13].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[13].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[13].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[13].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[13].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[13].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[13].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[13].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[13].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[13].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[13].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[13].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[13].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[13].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[13].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[13].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[13].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[13].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[13].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[13].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[13].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[13].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[13].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[13].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[13].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[13].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[13].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[13].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[13].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[13].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[13].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[13].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[13].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[13].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[13].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[13].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[13].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[13].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[13].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[13].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[13].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[13].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[13].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[13].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[13].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[13].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[13].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[13].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[13].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[13].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[13].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[13].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[13].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[13].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[13].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[13].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[13].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[13].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[13].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[13].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[13].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[13].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[13].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[13].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[13].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[13].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[13].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[13].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[13].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[13].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[13].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[13].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[13].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[13].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[13].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[13].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[13].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[13].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[13].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[13].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[13].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[13].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[13].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[13].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[13].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[13].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[13].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[13].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[13].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[13].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[13].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[13].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[13].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[13].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[13].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[13].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[13].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[13].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[13].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[13].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[13].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[13].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[13].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[13].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[13].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[13].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[13].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[13].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[13].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[13].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[13].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[13].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[13].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[13].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[13].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[13].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[13].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[13].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[13].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[13].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[13].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[13].child_rebusys, io.child_rebusys connect issue_slots[13].squash_grant, io.squash_grant connect issue_slots[13].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[13].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[13].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[13].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[13].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[13].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[13].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[13].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[13].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[13].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[13].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[13].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[13].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[13].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[13].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[13].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[13].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[13].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[13].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[13].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[13].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[13].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[13].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[13].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[13].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[13].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[13].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[13].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[13].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[13].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[13].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[13].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[13].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[13].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[13].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[13].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[13].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[13].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[13].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[13].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[13].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[13].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[13].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[13].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[13].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[13].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[13].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[13].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[13].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[13].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[13].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[13].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[13].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[13].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[13].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[13].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[13].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[13].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[13].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[13].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[13].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[13].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[13].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[13].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[13].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[13].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[13].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[13].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[13].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[13].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[13].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[13].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[13].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[13].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[13].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[13].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[13].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[13].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[13].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[13].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[13].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[13].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[13].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[13].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[13].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[13].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[13].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[13].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[13].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[13].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[13].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[13].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[13].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[13].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[13].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[13].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[13].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[13].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[13].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[13].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[13].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[13].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[13].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[13].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[13].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[13].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[13].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[13].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[13].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[13].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[13].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[13].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[13].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[13].kill, io.flush_pipeline connect issue_slots[14].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[14].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[14].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[14].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[14].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[14].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[14].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[14].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[14].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[14].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[14].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[14].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[14].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[14].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[14].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[14].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[14].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[14].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[14].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[14].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[14].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[14].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[14].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[14].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[14].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[14].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[14].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[14].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[14].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[14].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[14].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[14].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[14].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[14].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[14].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[14].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[14].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[14].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[14].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[14].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[14].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[14].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[14].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[14].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[14].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[14].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[14].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[14].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[14].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[14].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[14].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[14].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[14].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[14].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[14].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[14].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[14].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[14].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[14].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[14].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[14].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[14].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[14].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[14].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[14].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[14].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[14].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[14].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[14].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[14].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[14].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[14].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[14].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[14].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[14].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[14].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[14].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[14].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[14].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[14].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[14].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[14].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[14].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[14].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[14].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[14].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[14].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[14].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[14].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[14].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[14].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[14].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[14].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[14].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[14].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[14].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[14].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[14].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[14].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[14].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[14].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[14].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[14].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[14].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[14].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[14].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[14].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[14].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[14].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[14].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[14].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[14].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[14].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[14].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[14].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[14].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[14].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[14].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[14].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[14].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[14].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[14].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[14].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[14].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[14].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[14].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[14].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[14].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[14].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[14].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[14].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[14].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[14].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[14].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[14].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[14].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[14].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[14].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[14].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[14].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[14].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[14].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[14].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[14].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[14].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[14].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[14].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[14].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[14].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[14].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[14].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[14].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[14].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[14].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[14].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[14].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[14].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[14].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[14].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[14].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[14].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[14].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[14].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[14].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[14].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[14].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[14].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[14].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[14].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[14].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[14].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[14].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[14].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[14].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[14].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[14].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[14].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[14].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[14].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[14].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[14].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[14].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[14].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[14].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[14].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[14].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[14].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[14].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[14].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[14].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[14].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[14].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[14].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[14].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[14].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[14].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[14].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[14].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[14].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[14].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[14].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[14].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[14].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[14].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[14].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[14].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[14].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[14].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[14].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[14].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[14].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[14].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[14].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[14].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[14].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[14].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[14].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[14].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[14].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[14].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[14].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[14].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[14].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[14].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[14].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[14].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[14].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[14].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[14].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[14].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[14].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[14].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[14].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[14].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[14].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[14].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[14].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[14].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[14].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[14].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[14].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[14].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[14].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[14].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[14].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[14].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[14].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[14].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[14].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[14].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[14].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[14].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[14].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[14].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[14].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[14].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[14].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[14].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[14].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[14].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[14].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[14].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[14].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[14].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[14].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[14].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[14].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[14].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[14].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[14].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[14].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[14].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[14].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[14].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[14].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[14].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[14].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[14].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[14].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[14].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[14].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[14].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[14].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[14].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[14].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[14].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[14].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[14].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[14].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[14].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[14].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[14].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[14].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[14].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[14].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[14].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[14].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[14].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[14].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[14].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[14].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[14].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[14].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[14].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[14].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[14].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[14].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[14].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[14].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[14].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[14].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[14].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[14].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[14].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[14].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[14].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[14].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[14].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[14].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[14].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[14].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[14].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[14].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[14].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[14].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[14].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[14].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[14].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[14].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[14].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[14].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[14].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[14].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[14].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[14].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[14].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[14].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[14].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[14].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[14].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[14].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[14].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[14].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[14].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[14].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[14].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[14].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[14].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[14].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[14].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[14].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[14].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[14].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[14].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[14].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[14].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[14].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[14].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[14].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[14].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[14].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[14].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[14].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[14].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[14].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[14].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[14].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[14].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[14].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[14].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[14].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[14].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[14].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[14].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[14].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[14].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[14].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[14].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[14].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[14].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[14].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[14].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[14].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[14].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[14].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[14].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[14].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[14].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[14].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[14].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[14].child_rebusys, io.child_rebusys connect issue_slots[14].squash_grant, io.squash_grant connect issue_slots[14].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[14].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[14].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[14].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[14].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[14].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[14].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[14].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[14].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[14].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[14].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[14].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[14].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[14].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[14].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[14].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[14].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[14].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[14].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[14].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[14].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[14].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[14].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[14].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[14].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[14].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[14].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[14].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[14].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[14].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[14].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[14].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[14].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[14].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[14].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[14].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[14].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[14].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[14].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[14].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[14].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[14].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[14].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[14].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[14].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[14].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[14].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[14].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[14].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[14].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[14].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[14].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[14].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[14].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[14].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[14].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[14].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[14].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[14].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[14].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[14].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[14].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[14].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[14].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[14].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[14].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[14].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[14].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[14].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[14].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[14].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[14].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[14].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[14].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[14].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[14].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[14].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[14].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[14].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[14].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[14].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[14].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[14].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[14].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[14].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[14].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[14].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[14].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[14].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[14].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[14].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[14].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[14].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[14].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[14].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[14].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[14].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[14].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[14].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[14].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[14].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[14].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[14].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[14].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[14].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[14].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[14].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[14].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[14].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[14].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[14].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[14].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[14].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[14].kill, io.flush_pipeline connect issue_slots[15].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[15].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[15].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[15].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[15].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[15].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[15].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[15].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[15].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[15].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[15].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[15].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[15].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[15].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[15].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[15].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[15].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[15].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[15].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[15].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[15].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[15].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[15].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[15].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[15].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[15].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[15].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[15].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[15].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[15].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[15].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[15].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[15].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[15].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[15].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[15].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[15].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[15].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[15].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[15].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[15].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[15].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[15].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[15].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[15].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[15].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[15].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[15].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[15].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[15].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[15].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[15].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[15].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[15].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[15].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[15].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[15].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[15].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[15].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[15].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[15].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[15].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[15].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[15].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[15].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[15].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[15].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[15].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[15].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[15].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[15].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[15].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[15].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[15].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[15].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[15].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[15].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[15].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[15].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[15].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[15].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[15].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[15].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[15].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[15].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[15].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[15].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[15].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[15].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[15].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[15].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[15].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[15].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[15].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[15].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[15].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[15].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[15].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[15].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[15].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[15].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[15].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[15].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[15].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[15].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[15].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[15].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[15].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[15].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[15].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[15].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[15].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[15].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[15].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[15].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[15].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[15].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[15].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[15].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[15].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[15].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[15].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[15].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[15].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[15].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[15].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[15].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[15].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[15].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[15].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[15].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[15].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[15].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[15].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[15].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[15].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[15].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[15].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[15].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[15].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[15].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[15].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[15].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[15].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[15].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[15].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[15].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[15].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[15].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[15].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[15].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[15].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[15].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[15].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[15].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[15].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[15].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[15].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[15].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[15].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[15].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[15].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[15].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[15].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[15].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[15].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[15].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[15].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[15].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[15].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[15].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[15].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[15].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[15].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[15].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[15].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[15].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[15].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[15].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[15].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[15].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[15].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[15].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[15].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[15].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[15].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[15].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[15].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[15].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[15].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[15].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[15].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[15].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[15].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[15].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[15].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[15].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[15].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[15].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[15].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[15].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[15].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[15].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[15].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[15].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[15].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[15].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[15].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[15].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[15].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[15].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[15].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[15].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[15].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[15].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[15].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[15].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[15].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[15].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[15].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[15].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[15].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[15].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[15].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[15].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[15].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[15].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[15].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[15].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[15].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[15].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[15].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[15].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[15].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[15].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[15].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[15].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[15].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[15].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[15].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[15].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[15].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[15].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[15].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[15].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[15].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[15].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[15].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[15].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[15].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[15].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[15].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[15].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[15].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[15].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[15].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[15].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[15].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[15].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[15].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[15].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[15].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[15].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[15].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[15].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[15].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[15].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[15].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[15].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[15].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[15].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[15].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[15].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[15].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[15].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[15].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[15].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[15].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[15].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[15].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[15].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[15].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[15].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[15].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[15].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[15].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[15].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[15].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[15].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[15].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[15].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[15].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[15].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[15].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[15].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[15].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[15].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[15].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[15].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[15].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[15].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[15].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[15].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[15].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[15].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[15].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[15].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[15].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[15].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[15].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[15].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[15].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[15].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[15].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[15].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[15].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[15].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[15].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[15].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[15].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[15].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[15].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[15].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[15].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[15].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[15].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[15].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[15].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[15].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[15].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[15].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[15].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[15].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[15].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[15].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[15].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[15].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[15].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[15].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[15].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[15].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[15].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[15].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[15].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[15].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[15].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[15].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[15].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[15].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[15].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[15].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[15].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[15].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[15].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[15].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[15].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[15].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[15].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[15].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[15].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[15].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[15].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[15].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[15].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[15].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[15].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[15].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[15].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[15].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[15].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[15].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[15].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[15].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[15].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[15].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[15].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[15].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[15].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[15].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[15].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[15].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[15].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[15].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[15].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[15].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[15].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[15].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[15].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[15].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[15].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[15].child_rebusys, io.child_rebusys connect issue_slots[15].squash_grant, io.squash_grant connect issue_slots[15].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[15].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[15].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[15].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[15].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[15].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[15].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[15].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[15].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[15].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[15].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[15].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[15].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[15].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[15].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[15].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[15].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[15].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[15].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[15].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[15].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[15].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[15].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[15].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[15].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[15].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[15].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[15].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[15].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[15].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[15].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[15].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[15].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[15].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[15].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[15].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[15].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[15].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[15].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[15].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[15].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[15].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[15].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[15].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[15].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[15].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[15].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[15].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[15].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[15].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[15].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[15].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[15].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[15].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[15].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[15].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[15].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[15].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[15].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[15].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[15].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[15].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[15].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[15].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[15].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[15].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[15].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[15].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[15].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[15].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[15].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[15].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[15].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[15].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[15].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[15].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[15].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[15].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[15].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[15].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[15].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[15].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[15].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[15].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[15].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[15].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[15].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[15].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[15].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[15].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[15].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[15].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[15].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[15].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[15].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[15].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[15].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[15].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[15].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[15].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[15].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[15].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[15].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[15].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[15].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[15].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[15].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[15].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[15].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[15].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[15].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[15].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[15].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[15].kill, io.flush_pipeline connect io.iss_uops[0].valid, UInt<1>(0h0) node _T_225 = add(issue_slots[0].grant, issue_slots[1].grant) node _T_226 = bits(_T_225, 1, 0) node _T_227 = add(issue_slots[2].grant, issue_slots[3].grant) node _T_228 = bits(_T_227, 1, 0) node _T_229 = add(_T_226, _T_228) node _T_230 = bits(_T_229, 2, 0) node _T_231 = add(issue_slots[4].grant, issue_slots[5].grant) node _T_232 = bits(_T_231, 1, 0) node _T_233 = add(issue_slots[6].grant, issue_slots[7].grant) node _T_234 = bits(_T_233, 1, 0) node _T_235 = add(_T_232, _T_234) node _T_236 = bits(_T_235, 2, 0) node _T_237 = add(_T_230, _T_236) node _T_238 = bits(_T_237, 3, 0) node _T_239 = add(issue_slots[8].grant, issue_slots[9].grant) node _T_240 = bits(_T_239, 1, 0) node _T_241 = add(issue_slots[10].grant, issue_slots[11].grant) node _T_242 = bits(_T_241, 1, 0) node _T_243 = add(_T_240, _T_242) node _T_244 = bits(_T_243, 2, 0) node _T_245 = add(issue_slots[12].grant, issue_slots[13].grant) node _T_246 = bits(_T_245, 1, 0) node _T_247 = add(issue_slots[14].grant, issue_slots[15].grant) node _T_248 = bits(_T_247, 1, 0) node _T_249 = add(_T_246, _T_248) node _T_250 = bits(_T_249, 2, 0) node _T_251 = add(_T_244, _T_250) node _T_252 = bits(_T_251, 3, 0) node _T_253 = add(_T_238, _T_252) node _T_254 = bits(_T_253, 4, 0) node _T_255 = leq(_T_254, UInt<1>(0h1)) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: [issue] window giving out too many grants.\n at issue-unit-age-ordered.scala:141 assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, \"[issue] window giving out too many grants.\")\n") : printf assert(clock, _T_255, UInt<1>(0h1), "") : assert node vacants_0 = eq(issue_slots[0].valid, UInt<1>(0h0)) node vacants_1 = eq(issue_slots[1].valid, UInt<1>(0h0)) node vacants_2 = eq(issue_slots[2].valid, UInt<1>(0h0)) node vacants_3 = eq(issue_slots[3].valid, UInt<1>(0h0)) node vacants_4 = eq(issue_slots[4].valid, UInt<1>(0h0)) node vacants_5 = eq(issue_slots[5].valid, UInt<1>(0h0)) node vacants_6 = eq(issue_slots[6].valid, UInt<1>(0h0)) node vacants_7 = eq(issue_slots[7].valid, UInt<1>(0h0)) node vacants_8 = eq(issue_slots[8].valid, UInt<1>(0h0)) node vacants_9 = eq(issue_slots[9].valid, UInt<1>(0h0)) node vacants_10 = eq(issue_slots[10].valid, UInt<1>(0h0)) node vacants_11 = eq(issue_slots[11].valid, UInt<1>(0h0)) node vacants_12 = eq(issue_slots[12].valid, UInt<1>(0h0)) node vacants_13 = eq(issue_slots[13].valid, UInt<1>(0h0)) node vacants_14 = eq(issue_slots[14].valid, UInt<1>(0h0)) node vacants_15 = eq(issue_slots[15].valid, UInt<1>(0h0)) node vacants_16 = eq(io.dis_uops[0].valid, UInt<1>(0h0)) node vacants_17 = eq(io.dis_uops[1].valid, UInt<1>(0h0)) node vacants_18 = eq(io.dis_uops[2].valid, UInt<1>(0h0)) wire shamts_oh : UInt<3>[19] connect shamts_oh[0], UInt<1>(0h0) connect shamts_oh[1], vacants_0 node _shamts_oh_2_T = or(vacants_0, vacants_1) connect shamts_oh[2], _shamts_oh_2_T node _shamts_oh_3_T = or(vacants_0, vacants_1) node _shamts_oh_3_T_1 = or(_shamts_oh_3_T, vacants_2) connect shamts_oh[3], _shamts_oh_3_T_1 wire shamts_oh_4_next : UInt<2> connect shamts_oh_4_next, shamts_oh[3] node _shamts_oh_4_T = eq(shamts_oh[3], UInt<1>(0h0)) node _shamts_oh_4_T_1 = and(_shamts_oh_4_T, vacants_3) when _shamts_oh_4_T_1 : connect shamts_oh_4_next, UInt<1>(0h1) else : node _shamts_oh_4_T_2 = bits(shamts_oh[3], 1, 1) node _shamts_oh_4_T_3 = eq(_shamts_oh_4_T_2, UInt<1>(0h0)) node _shamts_oh_4_T_4 = and(_shamts_oh_4_T_3, vacants_3) when _shamts_oh_4_T_4 : node _shamts_oh_4_next_T = dshl(shamts_oh[3], UInt<1>(0h1)) connect shamts_oh_4_next, _shamts_oh_4_next_T connect shamts_oh[4], shamts_oh_4_next wire shamts_oh_5_next : UInt<2> connect shamts_oh_5_next, shamts_oh[4] node _shamts_oh_5_T = eq(shamts_oh[4], UInt<1>(0h0)) node _shamts_oh_5_T_1 = and(_shamts_oh_5_T, vacants_4) when _shamts_oh_5_T_1 : connect shamts_oh_5_next, UInt<1>(0h1) else : node _shamts_oh_5_T_2 = bits(shamts_oh[4], 1, 1) node _shamts_oh_5_T_3 = eq(_shamts_oh_5_T_2, UInt<1>(0h0)) node _shamts_oh_5_T_4 = and(_shamts_oh_5_T_3, vacants_4) when _shamts_oh_5_T_4 : node _shamts_oh_5_next_T = dshl(shamts_oh[4], UInt<1>(0h1)) connect shamts_oh_5_next, _shamts_oh_5_next_T connect shamts_oh[5], shamts_oh_5_next wire shamts_oh_6_next : UInt<2> connect shamts_oh_6_next, shamts_oh[5] node _shamts_oh_6_T = eq(shamts_oh[5], UInt<1>(0h0)) node _shamts_oh_6_T_1 = and(_shamts_oh_6_T, vacants_5) when _shamts_oh_6_T_1 : connect shamts_oh_6_next, UInt<1>(0h1) else : node _shamts_oh_6_T_2 = bits(shamts_oh[5], 1, 1) node _shamts_oh_6_T_3 = eq(_shamts_oh_6_T_2, UInt<1>(0h0)) node _shamts_oh_6_T_4 = and(_shamts_oh_6_T_3, vacants_5) when _shamts_oh_6_T_4 : node _shamts_oh_6_next_T = dshl(shamts_oh[5], UInt<1>(0h1)) connect shamts_oh_6_next, _shamts_oh_6_next_T connect shamts_oh[6], shamts_oh_6_next wire shamts_oh_7_next : UInt<2> connect shamts_oh_7_next, shamts_oh[6] node _shamts_oh_7_T = eq(shamts_oh[6], UInt<1>(0h0)) node _shamts_oh_7_T_1 = and(_shamts_oh_7_T, vacants_6) when _shamts_oh_7_T_1 : connect shamts_oh_7_next, UInt<1>(0h1) else : node _shamts_oh_7_T_2 = bits(shamts_oh[6], 1, 1) node _shamts_oh_7_T_3 = eq(_shamts_oh_7_T_2, UInt<1>(0h0)) node _shamts_oh_7_T_4 = and(_shamts_oh_7_T_3, vacants_6) when _shamts_oh_7_T_4 : node _shamts_oh_7_next_T = dshl(shamts_oh[6], UInt<1>(0h1)) connect shamts_oh_7_next, _shamts_oh_7_next_T connect shamts_oh[7], shamts_oh_7_next wire shamts_oh_8_next : UInt<3> connect shamts_oh_8_next, shamts_oh[7] node _shamts_oh_8_T = eq(shamts_oh[7], UInt<1>(0h0)) node _shamts_oh_8_T_1 = and(_shamts_oh_8_T, vacants_7) when _shamts_oh_8_T_1 : connect shamts_oh_8_next, UInt<1>(0h1) else : node _shamts_oh_8_T_2 = bits(shamts_oh[7], 2, 2) node _shamts_oh_8_T_3 = eq(_shamts_oh_8_T_2, UInt<1>(0h0)) node _shamts_oh_8_T_4 = and(_shamts_oh_8_T_3, vacants_7) when _shamts_oh_8_T_4 : node _shamts_oh_8_next_T = dshl(shamts_oh[7], UInt<1>(0h1)) connect shamts_oh_8_next, _shamts_oh_8_next_T connect shamts_oh[8], shamts_oh_8_next wire shamts_oh_9_next : UInt<3> connect shamts_oh_9_next, shamts_oh[8] node _shamts_oh_9_T = eq(shamts_oh[8], UInt<1>(0h0)) node _shamts_oh_9_T_1 = and(_shamts_oh_9_T, vacants_8) when _shamts_oh_9_T_1 : connect shamts_oh_9_next, UInt<1>(0h1) else : node _shamts_oh_9_T_2 = bits(shamts_oh[8], 2, 2) node _shamts_oh_9_T_3 = eq(_shamts_oh_9_T_2, UInt<1>(0h0)) node _shamts_oh_9_T_4 = and(_shamts_oh_9_T_3, vacants_8) when _shamts_oh_9_T_4 : node _shamts_oh_9_next_T = dshl(shamts_oh[8], UInt<1>(0h1)) connect shamts_oh_9_next, _shamts_oh_9_next_T connect shamts_oh[9], shamts_oh_9_next wire shamts_oh_10_next : UInt<3> connect shamts_oh_10_next, shamts_oh[9] node _shamts_oh_10_T = eq(shamts_oh[9], UInt<1>(0h0)) node _shamts_oh_10_T_1 = and(_shamts_oh_10_T, vacants_9) when _shamts_oh_10_T_1 : connect shamts_oh_10_next, UInt<1>(0h1) else : node _shamts_oh_10_T_2 = bits(shamts_oh[9], 2, 2) node _shamts_oh_10_T_3 = eq(_shamts_oh_10_T_2, UInt<1>(0h0)) node _shamts_oh_10_T_4 = and(_shamts_oh_10_T_3, vacants_9) when _shamts_oh_10_T_4 : node _shamts_oh_10_next_T = dshl(shamts_oh[9], UInt<1>(0h1)) connect shamts_oh_10_next, _shamts_oh_10_next_T connect shamts_oh[10], shamts_oh_10_next wire shamts_oh_11_next : UInt<3> connect shamts_oh_11_next, shamts_oh[10] node _shamts_oh_11_T = eq(shamts_oh[10], UInt<1>(0h0)) node _shamts_oh_11_T_1 = and(_shamts_oh_11_T, vacants_10) when _shamts_oh_11_T_1 : connect shamts_oh_11_next, UInt<1>(0h1) else : node _shamts_oh_11_T_2 = bits(shamts_oh[10], 2, 2) node _shamts_oh_11_T_3 = eq(_shamts_oh_11_T_2, UInt<1>(0h0)) node _shamts_oh_11_T_4 = and(_shamts_oh_11_T_3, vacants_10) when _shamts_oh_11_T_4 : node _shamts_oh_11_next_T = dshl(shamts_oh[10], UInt<1>(0h1)) connect shamts_oh_11_next, _shamts_oh_11_next_T connect shamts_oh[11], shamts_oh_11_next wire shamts_oh_12_next : UInt<3> connect shamts_oh_12_next, shamts_oh[11] node _shamts_oh_12_T = eq(shamts_oh[11], UInt<1>(0h0)) node _shamts_oh_12_T_1 = and(_shamts_oh_12_T, vacants_11) when _shamts_oh_12_T_1 : connect shamts_oh_12_next, UInt<1>(0h1) else : node _shamts_oh_12_T_2 = bits(shamts_oh[11], 2, 2) node _shamts_oh_12_T_3 = eq(_shamts_oh_12_T_2, UInt<1>(0h0)) node _shamts_oh_12_T_4 = and(_shamts_oh_12_T_3, vacants_11) when _shamts_oh_12_T_4 : node _shamts_oh_12_next_T = dshl(shamts_oh[11], UInt<1>(0h1)) connect shamts_oh_12_next, _shamts_oh_12_next_T connect shamts_oh[12], shamts_oh_12_next wire shamts_oh_13_next : UInt<3> connect shamts_oh_13_next, shamts_oh[12] node _shamts_oh_13_T = eq(shamts_oh[12], UInt<1>(0h0)) node _shamts_oh_13_T_1 = and(_shamts_oh_13_T, vacants_12) when _shamts_oh_13_T_1 : connect shamts_oh_13_next, UInt<1>(0h1) else : node _shamts_oh_13_T_2 = bits(shamts_oh[12], 2, 2) node _shamts_oh_13_T_3 = eq(_shamts_oh_13_T_2, UInt<1>(0h0)) node _shamts_oh_13_T_4 = and(_shamts_oh_13_T_3, vacants_12) when _shamts_oh_13_T_4 : node _shamts_oh_13_next_T = dshl(shamts_oh[12], UInt<1>(0h1)) connect shamts_oh_13_next, _shamts_oh_13_next_T connect shamts_oh[13], shamts_oh_13_next wire shamts_oh_14_next : UInt<3> connect shamts_oh_14_next, shamts_oh[13] node _shamts_oh_14_T = eq(shamts_oh[13], UInt<1>(0h0)) node _shamts_oh_14_T_1 = and(_shamts_oh_14_T, vacants_13) when _shamts_oh_14_T_1 : connect shamts_oh_14_next, UInt<1>(0h1) else : node _shamts_oh_14_T_2 = bits(shamts_oh[13], 2, 2) node _shamts_oh_14_T_3 = eq(_shamts_oh_14_T_2, UInt<1>(0h0)) node _shamts_oh_14_T_4 = and(_shamts_oh_14_T_3, vacants_13) when _shamts_oh_14_T_4 : node _shamts_oh_14_next_T = dshl(shamts_oh[13], UInt<1>(0h1)) connect shamts_oh_14_next, _shamts_oh_14_next_T connect shamts_oh[14], shamts_oh_14_next wire shamts_oh_15_next : UInt<3> connect shamts_oh_15_next, shamts_oh[14] node _shamts_oh_15_T = eq(shamts_oh[14], UInt<1>(0h0)) node _shamts_oh_15_T_1 = and(_shamts_oh_15_T, vacants_14) when _shamts_oh_15_T_1 : connect shamts_oh_15_next, UInt<1>(0h1) else : node _shamts_oh_15_T_2 = bits(shamts_oh[14], 2, 2) node _shamts_oh_15_T_3 = eq(_shamts_oh_15_T_2, UInt<1>(0h0)) node _shamts_oh_15_T_4 = and(_shamts_oh_15_T_3, vacants_14) when _shamts_oh_15_T_4 : node _shamts_oh_15_next_T = dshl(shamts_oh[14], UInt<1>(0h1)) connect shamts_oh_15_next, _shamts_oh_15_next_T connect shamts_oh[15], shamts_oh_15_next wire shamts_oh_16_next : UInt<3> connect shamts_oh_16_next, shamts_oh[15] node _shamts_oh_16_T = eq(shamts_oh[15], UInt<1>(0h0)) node _shamts_oh_16_T_1 = and(_shamts_oh_16_T, vacants_15) when _shamts_oh_16_T_1 : connect shamts_oh_16_next, UInt<1>(0h1) else : node _shamts_oh_16_T_2 = bits(shamts_oh[15], 2, 2) node _shamts_oh_16_T_3 = eq(_shamts_oh_16_T_2, UInt<1>(0h0)) node _shamts_oh_16_T_4 = and(_shamts_oh_16_T_3, vacants_15) when _shamts_oh_16_T_4 : node _shamts_oh_16_next_T = dshl(shamts_oh[15], UInt<1>(0h1)) connect shamts_oh_16_next, _shamts_oh_16_next_T connect shamts_oh[16], shamts_oh_16_next wire shamts_oh_17_next : UInt<3> connect shamts_oh_17_next, shamts_oh[16] node _shamts_oh_17_T = eq(shamts_oh[16], UInt<1>(0h0)) node _shamts_oh_17_T_1 = and(_shamts_oh_17_T, vacants_16) when _shamts_oh_17_T_1 : connect shamts_oh_17_next, UInt<1>(0h1) else : node _shamts_oh_17_T_2 = bits(shamts_oh[16], 2, 2) node _shamts_oh_17_T_3 = eq(_shamts_oh_17_T_2, UInt<1>(0h0)) node _shamts_oh_17_T_4 = and(_shamts_oh_17_T_3, vacants_16) when _shamts_oh_17_T_4 : node _shamts_oh_17_next_T = dshl(shamts_oh[16], UInt<1>(0h1)) connect shamts_oh_17_next, _shamts_oh_17_next_T connect shamts_oh[17], shamts_oh_17_next wire shamts_oh_18_next : UInt<3> connect shamts_oh_18_next, shamts_oh[17] node _shamts_oh_18_T = eq(shamts_oh[17], UInt<1>(0h0)) node _shamts_oh_18_T_1 = and(_shamts_oh_18_T, vacants_17) when _shamts_oh_18_T_1 : connect shamts_oh_18_next, UInt<1>(0h1) else : node _shamts_oh_18_T_2 = bits(shamts_oh[17], 2, 2) node _shamts_oh_18_T_3 = eq(_shamts_oh_18_T_2, UInt<1>(0h0)) node _shamts_oh_18_T_4 = and(_shamts_oh_18_T_3, vacants_17) when _shamts_oh_18_T_4 : node _shamts_oh_18_next_T = dshl(shamts_oh[17], UInt<1>(0h1)) connect shamts_oh_18_next, _shamts_oh_18_next_T connect shamts_oh[18], shamts_oh_18_next node _will_be_valid_T = eq(_WIRE.exception, UInt<1>(0h0)) node _will_be_valid_T_1 = and(io.dis_uops[0].valid, _will_be_valid_T) node _will_be_valid_T_2 = eq(_WIRE.is_fence, UInt<1>(0h0)) node _will_be_valid_T_3 = and(_will_be_valid_T_1, _will_be_valid_T_2) node _will_be_valid_T_4 = eq(_WIRE.is_fencei, UInt<1>(0h0)) node will_be_valid_16 = and(_will_be_valid_T_3, _will_be_valid_T_4) node _will_be_valid_T_5 = eq(_WIRE_1.exception, UInt<1>(0h0)) node _will_be_valid_T_6 = and(io.dis_uops[1].valid, _will_be_valid_T_5) node _will_be_valid_T_7 = eq(_WIRE_1.is_fence, UInt<1>(0h0)) node _will_be_valid_T_8 = and(_will_be_valid_T_6, _will_be_valid_T_7) node _will_be_valid_T_9 = eq(_WIRE_1.is_fencei, UInt<1>(0h0)) node will_be_valid_17 = and(_will_be_valid_T_8, _will_be_valid_T_9) node _will_be_valid_T_10 = eq(_WIRE_2.exception, UInt<1>(0h0)) node _will_be_valid_T_11 = and(io.dis_uops[2].valid, _will_be_valid_T_10) node _will_be_valid_T_12 = eq(_WIRE_2.is_fence, UInt<1>(0h0)) node _will_be_valid_T_13 = and(_will_be_valid_T_11, _will_be_valid_T_12) node _will_be_valid_T_14 = eq(_WIRE_2.is_fencei, UInt<1>(0h0)) node will_be_valid_18 = and(_will_be_valid_T_13, _will_be_valid_T_14) connect issue_slots[0].in_uop.valid, UInt<1>(0h0) connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[1].out_uop.fp_typ connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[1].out_uop.fp_rm connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[1].out_uop.fcn_op connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[1].out_uop.fcn_dw connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[1].out_uop.csr_cmd connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[1].out_uop.fp_ctrl.vec connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[1].out_uop.fp_ctrl.wflags connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[1].out_uop.fp_ctrl.sqrt connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[1].out_uop.fp_ctrl.div connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[1].out_uop.fp_ctrl.fma connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].out_uop.fp_ctrl.fastpipe connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[1].out_uop.fp_ctrl.toint connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[1].out_uop.fp_ctrl.fromint connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].out_uop.fp_ctrl.typeTagOut connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].out_uop.fp_ctrl.typeTagIn connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[1].out_uop.fp_ctrl.swap23 connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[1].out_uop.fp_ctrl.swap12 connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[1].out_uop.fp_ctrl.ren3 connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[1].out_uop.fp_ctrl.ren2 connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[1].out_uop.fp_ctrl.ren1 connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[1].out_uop.fp_ctrl.wen connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[1].out_uop.fp_ctrl.ldst connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[1].out_uop.op2_sel connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[1].out_uop.op1_sel connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed connect issue_slots[0].in_uop.bits.pimm, issue_slots[1].out_uop.pimm connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[1].out_uop.imm_sel connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[1].out_uop.imm_rename connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.is_mov, issue_slots[1].out_uop.is_mov connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[1].out_uop.is_rocc connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.is_eret, issue_slots[1].out_uop.is_eret connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[1].out_uop.is_sfence connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb connect issue_slots[0].in_uop.bits.br_type, issue_slots[1].out_uop.br_type connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[1].out_uop.dis_col_sel connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[1].out_uop.iw_p3_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[1].out_uop.iw_p2_bypass_hint connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[1].out_uop.iw_p1_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[1].out_uop.iw_p2_speculative_child connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[1].out_uop.iw_p1_speculative_child connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[1].out_uop.iw_issued_partial_dgen connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[1].out_uop.iw_issued_partial_agen connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[1].out_uop.iw_issued connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[1].out_uop.fu_code[0] connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[1].out_uop.fu_code[1] connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[1].out_uop.fu_code[2] connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[1].out_uop.fu_code[3] connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[1].out_uop.fu_code[4] connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[1].out_uop.fu_code[5] connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[1].out_uop.fu_code[6] connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[1].out_uop.fu_code[7] connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[1].out_uop.fu_code[8] connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[1].out_uop.fu_code[9] connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[1].out_uop.iq_type[0] connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[1].out_uop.iq_type[1] connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[1].out_uop.iq_type[2] connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[1].out_uop.iq_type[3] connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst node _T_259 = eq(shamts_oh[1], UInt<1>(0h1)) when _T_259 : connect issue_slots[0].in_uop.valid, issue_slots[1].will_be_valid connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[1].out_uop.fp_typ connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[1].out_uop.fp_rm connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[1].out_uop.fcn_op connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[1].out_uop.fcn_dw connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[1].out_uop.csr_cmd connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[1].out_uop.fp_ctrl.vec connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[1].out_uop.fp_ctrl.wflags connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[1].out_uop.fp_ctrl.sqrt connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[1].out_uop.fp_ctrl.div connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[1].out_uop.fp_ctrl.fma connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].out_uop.fp_ctrl.fastpipe connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[1].out_uop.fp_ctrl.toint connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[1].out_uop.fp_ctrl.fromint connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].out_uop.fp_ctrl.typeTagOut connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].out_uop.fp_ctrl.typeTagIn connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[1].out_uop.fp_ctrl.swap23 connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[1].out_uop.fp_ctrl.swap12 connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[1].out_uop.fp_ctrl.ren3 connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[1].out_uop.fp_ctrl.ren2 connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[1].out_uop.fp_ctrl.ren1 connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[1].out_uop.fp_ctrl.wen connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[1].out_uop.fp_ctrl.ldst connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[1].out_uop.op2_sel connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[1].out_uop.op1_sel connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed connect issue_slots[0].in_uop.bits.pimm, issue_slots[1].out_uop.pimm connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[1].out_uop.imm_sel connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[1].out_uop.imm_rename connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.is_mov, issue_slots[1].out_uop.is_mov connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[1].out_uop.is_rocc connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.is_eret, issue_slots[1].out_uop.is_eret connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[1].out_uop.is_sfence connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb connect issue_slots[0].in_uop.bits.br_type, issue_slots[1].out_uop.br_type connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[1].out_uop.dis_col_sel connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[1].out_uop.iw_p3_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[1].out_uop.iw_p2_bypass_hint connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[1].out_uop.iw_p1_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[1].out_uop.iw_p2_speculative_child connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[1].out_uop.iw_p1_speculative_child connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[1].out_uop.iw_issued_partial_dgen connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[1].out_uop.iw_issued_partial_agen connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[1].out_uop.iw_issued connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[1].out_uop.fu_code[0] connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[1].out_uop.fu_code[1] connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[1].out_uop.fu_code[2] connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[1].out_uop.fu_code[3] connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[1].out_uop.fu_code[4] connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[1].out_uop.fu_code[5] connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[1].out_uop.fu_code[6] connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[1].out_uop.fu_code[7] connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[1].out_uop.fu_code[8] connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[1].out_uop.fu_code[9] connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[1].out_uop.iq_type[0] connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[1].out_uop.iq_type[1] connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[1].out_uop.iq_type[2] connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[1].out_uop.iq_type[3] connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst node _T_260 = eq(shamts_oh[2], UInt<2>(0h2)) when _T_260 : connect issue_slots[0].in_uop.valid, issue_slots[2].will_be_valid connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm connect issue_slots[0].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23 connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12 connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3 connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2 connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1 connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[0].in_uop.bits.pimm, issue_slots[2].out_uop.pimm connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename connect issue_slots[0].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret connect issue_slots[0].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[0].in_uop.bits.br_type, issue_slots[2].out_uop.br_type connect issue_slots[0].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0] connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1] connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2] connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3] connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4] connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5] connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6] connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7] connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8] connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9] connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0] connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1] connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2] connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3] connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[2].out_uop.inst node _T_261 = eq(shamts_oh[3], UInt<3>(0h4)) when _T_261 : connect issue_slots[0].in_uop.valid, issue_slots[3].will_be_valid connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm connect issue_slots[0].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[0].in_uop.bits.pimm, issue_slots[3].out_uop.pimm connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename connect issue_slots[0].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret connect issue_slots[0].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[0].in_uop.bits.br_type, issue_slots[3].out_uop.br_type connect issue_slots[0].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[3].out_uop.inst node _issue_slots_0_clear_T = neq(shamts_oh[0], UInt<1>(0h0)) connect issue_slots[0].clear, _issue_slots_0_clear_T connect issue_slots[1].in_uop.valid, UInt<1>(0h0) connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23 connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12 connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3 connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2 connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1 connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[1].in_uop.bits.pimm, issue_slots[2].out_uop.pimm connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[1].in_uop.bits.br_type, issue_slots[2].out_uop.br_type connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0] connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1] connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2] connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3] connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4] connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5] connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6] connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7] connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8] connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9] connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0] connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1] connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2] connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3] connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst node _T_262 = eq(shamts_oh[2], UInt<1>(0h1)) when _T_262 : connect issue_slots[1].in_uop.valid, issue_slots[2].will_be_valid connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23 connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12 connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3 connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2 connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1 connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[1].in_uop.bits.pimm, issue_slots[2].out_uop.pimm connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[1].in_uop.bits.br_type, issue_slots[2].out_uop.br_type connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0] connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1] connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2] connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3] connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4] connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5] connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6] connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7] connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8] connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9] connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0] connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1] connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2] connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3] connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst node _T_263 = eq(shamts_oh[3], UInt<2>(0h2)) when _T_263 : connect issue_slots[1].in_uop.valid, issue_slots[3].will_be_valid connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm connect issue_slots[1].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[1].in_uop.bits.pimm, issue_slots[3].out_uop.pimm connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename connect issue_slots[1].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret connect issue_slots[1].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[1].in_uop.bits.br_type, issue_slots[3].out_uop.br_type connect issue_slots[1].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[3].out_uop.inst node _T_264 = eq(shamts_oh[4], UInt<3>(0h4)) when _T_264 : connect issue_slots[1].in_uop.valid, issue_slots[4].will_be_valid connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm connect issue_slots[1].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[1].in_uop.bits.pimm, issue_slots[4].out_uop.pimm connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename connect issue_slots[1].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret connect issue_slots[1].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[1].in_uop.bits.br_type, issue_slots[4].out_uop.br_type connect issue_slots[1].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[4].out_uop.inst node _issue_slots_1_clear_T = neq(shamts_oh[1], UInt<1>(0h0)) connect issue_slots[1].clear, _issue_slots_1_clear_T connect issue_slots[2].in_uop.valid, UInt<1>(0h0) connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[2].in_uop.bits.pimm, issue_slots[3].out_uop.pimm connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[2].in_uop.bits.br_type, issue_slots[3].out_uop.br_type connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst node _T_265 = eq(shamts_oh[3], UInt<1>(0h1)) when _T_265 : connect issue_slots[2].in_uop.valid, issue_slots[3].will_be_valid connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[2].in_uop.bits.pimm, issue_slots[3].out_uop.pimm connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[2].in_uop.bits.br_type, issue_slots[3].out_uop.br_type connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst node _T_266 = eq(shamts_oh[4], UInt<2>(0h2)) when _T_266 : connect issue_slots[2].in_uop.valid, issue_slots[4].will_be_valid connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm connect issue_slots[2].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[2].in_uop.bits.pimm, issue_slots[4].out_uop.pimm connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename connect issue_slots[2].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret connect issue_slots[2].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[2].in_uop.bits.br_type, issue_slots[4].out_uop.br_type connect issue_slots[2].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[4].out_uop.inst node _T_267 = eq(shamts_oh[5], UInt<3>(0h4)) when _T_267 : connect issue_slots[2].in_uop.valid, issue_slots[5].will_be_valid connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm connect issue_slots[2].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[2].in_uop.bits.pimm, issue_slots[5].out_uop.pimm connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename connect issue_slots[2].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret connect issue_slots[2].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[2].in_uop.bits.br_type, issue_slots[5].out_uop.br_type connect issue_slots[2].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[5].out_uop.inst node _issue_slots_2_clear_T = neq(shamts_oh[2], UInt<1>(0h0)) connect issue_slots[2].clear, _issue_slots_2_clear_T connect issue_slots[3].in_uop.valid, UInt<1>(0h0) connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[3].in_uop.bits.pimm, issue_slots[4].out_uop.pimm connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[3].in_uop.bits.br_type, issue_slots[4].out_uop.br_type connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst node _T_268 = eq(shamts_oh[4], UInt<1>(0h1)) when _T_268 : connect issue_slots[3].in_uop.valid, issue_slots[4].will_be_valid connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[3].in_uop.bits.pimm, issue_slots[4].out_uop.pimm connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[3].in_uop.bits.br_type, issue_slots[4].out_uop.br_type connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst node _T_269 = eq(shamts_oh[5], UInt<2>(0h2)) when _T_269 : connect issue_slots[3].in_uop.valid, issue_slots[5].will_be_valid connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm connect issue_slots[3].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[3].in_uop.bits.pimm, issue_slots[5].out_uop.pimm connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename connect issue_slots[3].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret connect issue_slots[3].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[3].in_uop.bits.br_type, issue_slots[5].out_uop.br_type connect issue_slots[3].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[5].out_uop.inst node _T_270 = eq(shamts_oh[6], UInt<3>(0h4)) when _T_270 : connect issue_slots[3].in_uop.valid, issue_slots[6].will_be_valid connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm connect issue_slots[3].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[3].in_uop.bits.pimm, issue_slots[6].out_uop.pimm connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename connect issue_slots[3].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret connect issue_slots[3].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[3].in_uop.bits.br_type, issue_slots[6].out_uop.br_type connect issue_slots[3].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[6].out_uop.inst node _issue_slots_3_clear_T = neq(shamts_oh[3], UInt<1>(0h0)) connect issue_slots[3].clear, _issue_slots_3_clear_T connect issue_slots[4].in_uop.valid, UInt<1>(0h0) connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[4].in_uop.bits.pimm, issue_slots[5].out_uop.pimm connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[4].in_uop.bits.br_type, issue_slots[5].out_uop.br_type connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst node _T_271 = eq(shamts_oh[5], UInt<1>(0h1)) when _T_271 : connect issue_slots[4].in_uop.valid, issue_slots[5].will_be_valid connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[4].in_uop.bits.pimm, issue_slots[5].out_uop.pimm connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[4].in_uop.bits.br_type, issue_slots[5].out_uop.br_type connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst node _T_272 = eq(shamts_oh[6], UInt<2>(0h2)) when _T_272 : connect issue_slots[4].in_uop.valid, issue_slots[6].will_be_valid connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm connect issue_slots[4].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[4].in_uop.bits.pimm, issue_slots[6].out_uop.pimm connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename connect issue_slots[4].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret connect issue_slots[4].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[4].in_uop.bits.br_type, issue_slots[6].out_uop.br_type connect issue_slots[4].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[6].out_uop.inst node _T_273 = eq(shamts_oh[7], UInt<3>(0h4)) when _T_273 : connect issue_slots[4].in_uop.valid, issue_slots[7].will_be_valid connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm connect issue_slots[4].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[4].in_uop.bits.pimm, issue_slots[7].out_uop.pimm connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename connect issue_slots[4].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret connect issue_slots[4].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[4].in_uop.bits.br_type, issue_slots[7].out_uop.br_type connect issue_slots[4].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[7].out_uop.inst node _issue_slots_4_clear_T = neq(shamts_oh[4], UInt<1>(0h0)) connect issue_slots[4].clear, _issue_slots_4_clear_T connect issue_slots[5].in_uop.valid, UInt<1>(0h0) connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[5].in_uop.bits.pimm, issue_slots[6].out_uop.pimm connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[5].in_uop.bits.br_type, issue_slots[6].out_uop.br_type connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst node _T_274 = eq(shamts_oh[6], UInt<1>(0h1)) when _T_274 : connect issue_slots[5].in_uop.valid, issue_slots[6].will_be_valid connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[5].in_uop.bits.pimm, issue_slots[6].out_uop.pimm connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[5].in_uop.bits.br_type, issue_slots[6].out_uop.br_type connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst node _T_275 = eq(shamts_oh[7], UInt<2>(0h2)) when _T_275 : connect issue_slots[5].in_uop.valid, issue_slots[7].will_be_valid connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm connect issue_slots[5].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[5].in_uop.bits.pimm, issue_slots[7].out_uop.pimm connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename connect issue_slots[5].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret connect issue_slots[5].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[5].in_uop.bits.br_type, issue_slots[7].out_uop.br_type connect issue_slots[5].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[7].out_uop.inst node _T_276 = eq(shamts_oh[8], UInt<3>(0h4)) when _T_276 : connect issue_slots[5].in_uop.valid, issue_slots[8].will_be_valid connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm connect issue_slots[5].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[5].in_uop.bits.pimm, issue_slots[8].out_uop.pimm connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename connect issue_slots[5].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret connect issue_slots[5].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[5].in_uop.bits.br_type, issue_slots[8].out_uop.br_type connect issue_slots[5].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[8].out_uop.inst node _issue_slots_5_clear_T = neq(shamts_oh[5], UInt<1>(0h0)) connect issue_slots[5].clear, _issue_slots_5_clear_T connect issue_slots[6].in_uop.valid, UInt<1>(0h0) connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[6].in_uop.bits.pimm, issue_slots[7].out_uop.pimm connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[6].in_uop.bits.br_type, issue_slots[7].out_uop.br_type connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst node _T_277 = eq(shamts_oh[7], UInt<1>(0h1)) when _T_277 : connect issue_slots[6].in_uop.valid, issue_slots[7].will_be_valid connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[6].in_uop.bits.pimm, issue_slots[7].out_uop.pimm connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[6].in_uop.bits.br_type, issue_slots[7].out_uop.br_type connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst node _T_278 = eq(shamts_oh[8], UInt<2>(0h2)) when _T_278 : connect issue_slots[6].in_uop.valid, issue_slots[8].will_be_valid connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm connect issue_slots[6].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[6].in_uop.bits.pimm, issue_slots[8].out_uop.pimm connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename connect issue_slots[6].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret connect issue_slots[6].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[6].in_uop.bits.br_type, issue_slots[8].out_uop.br_type connect issue_slots[6].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[8].out_uop.inst node _T_279 = eq(shamts_oh[9], UInt<3>(0h4)) when _T_279 : connect issue_slots[6].in_uop.valid, issue_slots[9].will_be_valid connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm connect issue_slots[6].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[6].in_uop.bits.pimm, issue_slots[9].out_uop.pimm connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename connect issue_slots[6].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret connect issue_slots[6].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[6].in_uop.bits.br_type, issue_slots[9].out_uop.br_type connect issue_slots[6].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[9].out_uop.inst node _issue_slots_6_clear_T = neq(shamts_oh[6], UInt<1>(0h0)) connect issue_slots[6].clear, _issue_slots_6_clear_T connect issue_slots[7].in_uop.valid, UInt<1>(0h0) connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[7].in_uop.bits.pimm, issue_slots[8].out_uop.pimm connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[7].in_uop.bits.br_type, issue_slots[8].out_uop.br_type connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst node _T_280 = eq(shamts_oh[8], UInt<1>(0h1)) when _T_280 : connect issue_slots[7].in_uop.valid, issue_slots[8].will_be_valid connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[7].in_uop.bits.pimm, issue_slots[8].out_uop.pimm connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[7].in_uop.bits.br_type, issue_slots[8].out_uop.br_type connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst node _T_281 = eq(shamts_oh[9], UInt<2>(0h2)) when _T_281 : connect issue_slots[7].in_uop.valid, issue_slots[9].will_be_valid connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm connect issue_slots[7].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[7].in_uop.bits.pimm, issue_slots[9].out_uop.pimm connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename connect issue_slots[7].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret connect issue_slots[7].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[7].in_uop.bits.br_type, issue_slots[9].out_uop.br_type connect issue_slots[7].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[9].out_uop.inst node _T_282 = eq(shamts_oh[10], UInt<3>(0h4)) when _T_282 : connect issue_slots[7].in_uop.valid, issue_slots[10].will_be_valid connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm connect issue_slots[7].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[7].in_uop.bits.pimm, issue_slots[10].out_uop.pimm connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename connect issue_slots[7].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret connect issue_slots[7].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[7].in_uop.bits.br_type, issue_slots[10].out_uop.br_type connect issue_slots[7].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[10].out_uop.inst node _issue_slots_7_clear_T = neq(shamts_oh[7], UInt<1>(0h0)) connect issue_slots[7].clear, _issue_slots_7_clear_T connect issue_slots[8].in_uop.valid, UInt<1>(0h0) connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[8].in_uop.bits.pimm, issue_slots[9].out_uop.pimm connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[8].in_uop.bits.br_type, issue_slots[9].out_uop.br_type connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst node _T_283 = eq(shamts_oh[9], UInt<1>(0h1)) when _T_283 : connect issue_slots[8].in_uop.valid, issue_slots[9].will_be_valid connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[8].in_uop.bits.pimm, issue_slots[9].out_uop.pimm connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[8].in_uop.bits.br_type, issue_slots[9].out_uop.br_type connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst node _T_284 = eq(shamts_oh[10], UInt<2>(0h2)) when _T_284 : connect issue_slots[8].in_uop.valid, issue_slots[10].will_be_valid connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm connect issue_slots[8].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[8].in_uop.bits.pimm, issue_slots[10].out_uop.pimm connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename connect issue_slots[8].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret connect issue_slots[8].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[8].in_uop.bits.br_type, issue_slots[10].out_uop.br_type connect issue_slots[8].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[10].out_uop.inst node _T_285 = eq(shamts_oh[11], UInt<3>(0h4)) when _T_285 : connect issue_slots[8].in_uop.valid, issue_slots[11].will_be_valid connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm connect issue_slots[8].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[8].in_uop.bits.pimm, issue_slots[11].out_uop.pimm connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename connect issue_slots[8].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret connect issue_slots[8].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[8].in_uop.bits.br_type, issue_slots[11].out_uop.br_type connect issue_slots[8].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[11].out_uop.inst node _issue_slots_8_clear_T = neq(shamts_oh[8], UInt<1>(0h0)) connect issue_slots[8].clear, _issue_slots_8_clear_T connect issue_slots[9].in_uop.valid, UInt<1>(0h0) connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[9].in_uop.bits.pimm, issue_slots[10].out_uop.pimm connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[9].in_uop.bits.br_type, issue_slots[10].out_uop.br_type connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst node _T_286 = eq(shamts_oh[10], UInt<1>(0h1)) when _T_286 : connect issue_slots[9].in_uop.valid, issue_slots[10].will_be_valid connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[9].in_uop.bits.pimm, issue_slots[10].out_uop.pimm connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[9].in_uop.bits.br_type, issue_slots[10].out_uop.br_type connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst node _T_287 = eq(shamts_oh[11], UInt<2>(0h2)) when _T_287 : connect issue_slots[9].in_uop.valid, issue_slots[11].will_be_valid connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm connect issue_slots[9].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[9].in_uop.bits.pimm, issue_slots[11].out_uop.pimm connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename connect issue_slots[9].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret connect issue_slots[9].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[9].in_uop.bits.br_type, issue_slots[11].out_uop.br_type connect issue_slots[9].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[11].out_uop.inst node _T_288 = eq(shamts_oh[12], UInt<3>(0h4)) when _T_288 : connect issue_slots[9].in_uop.valid, issue_slots[12].will_be_valid connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm connect issue_slots[9].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[12].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[12].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[12].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[12].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23 connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12 connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3 connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2 connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1 connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed connect issue_slots[9].in_uop.bits.pimm, issue_slots[12].out_uop.pimm connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename connect issue_slots[9].in_uop.bits.taken, issue_slots[12].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret connect issue_slots[9].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb connect issue_slots[9].in_uop.bits.br_type, issue_slots[12].out_uop.br_type connect issue_slots[9].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0] connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1] connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2] connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3] connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4] connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5] connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6] connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7] connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8] connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9] connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0] connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1] connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2] connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3] connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[12].out_uop.inst node _issue_slots_9_clear_T = neq(shamts_oh[9], UInt<1>(0h0)) connect issue_slots[9].clear, _issue_slots_9_clear_T connect issue_slots[10].in_uop.valid, UInt<1>(0h0) connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[10].in_uop.bits.pimm, issue_slots[11].out_uop.pimm connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[10].in_uop.bits.br_type, issue_slots[11].out_uop.br_type connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst node _T_289 = eq(shamts_oh[11], UInt<1>(0h1)) when _T_289 : connect issue_slots[10].in_uop.valid, issue_slots[11].will_be_valid connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[10].in_uop.bits.pimm, issue_slots[11].out_uop.pimm connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[10].in_uop.bits.br_type, issue_slots[11].out_uop.br_type connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst node _T_290 = eq(shamts_oh[12], UInt<2>(0h2)) when _T_290 : connect issue_slots[10].in_uop.valid, issue_slots[12].will_be_valid connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm connect issue_slots[10].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[12].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[12].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[12].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[12].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23 connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12 connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3 connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2 connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1 connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed connect issue_slots[10].in_uop.bits.pimm, issue_slots[12].out_uop.pimm connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename connect issue_slots[10].in_uop.bits.taken, issue_slots[12].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret connect issue_slots[10].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb connect issue_slots[10].in_uop.bits.br_type, issue_slots[12].out_uop.br_type connect issue_slots[10].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0] connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1] connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2] connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3] connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4] connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5] connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6] connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7] connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8] connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9] connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0] connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1] connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2] connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3] connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[12].out_uop.inst node _T_291 = eq(shamts_oh[13], UInt<3>(0h4)) when _T_291 : connect issue_slots[10].in_uop.valid, issue_slots[13].will_be_valid connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm connect issue_slots[10].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[13].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[13].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[13].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[13].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23 connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12 connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3 connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2 connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1 connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed connect issue_slots[10].in_uop.bits.pimm, issue_slots[13].out_uop.pimm connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename connect issue_slots[10].in_uop.bits.taken, issue_slots[13].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret connect issue_slots[10].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb connect issue_slots[10].in_uop.bits.br_type, issue_slots[13].out_uop.br_type connect issue_slots[10].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0] connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1] connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2] connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3] connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4] connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5] connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6] connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7] connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8] connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9] connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0] connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1] connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2] connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3] connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[13].out_uop.inst node _issue_slots_10_clear_T = neq(shamts_oh[10], UInt<1>(0h0)) connect issue_slots[10].clear, _issue_slots_10_clear_T connect issue_slots[11].in_uop.valid, UInt<1>(0h0) connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm connect issue_slots[11].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype connect issue_slots[11].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 connect issue_slots[11].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 connect issue_slots[11].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 connect issue_slots[11].in_uop.bits.ldst, issue_slots[12].out_uop.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed connect issue_slots[11].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause connect issue_slots[11].in_uop.bits.exception, issue_slots[12].out_uop.exception connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy connect issue_slots[11].in_uop.bits.ppred, issue_slots[12].out_uop.ppred connect issue_slots[11].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 connect issue_slots[11].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 connect issue_slots[11].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 connect issue_slots[11].in_uop.bits.pdst, issue_slots[12].out_uop.pdst connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23 connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12 connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3 connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2 connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1 connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed connect issue_slots[11].in_uop.bits.pimm, issue_slots[12].out_uop.pimm connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename connect issue_slots[11].in_uop.bits.taken, issue_slots[12].out_uop.taken connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx connect issue_slots[11].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc connect issue_slots[11].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret connect issue_slots[11].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei connect issue_slots[11].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb connect issue_slots[11].in_uop.bits.br_type, issue_slots[12].out_uop.br_type connect issue_slots[11].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag connect issue_slots[11].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0] connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1] connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2] connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3] connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4] connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5] connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6] connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7] connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8] connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9] connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0] connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1] connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2] connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3] connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst connect issue_slots[11].in_uop.bits.inst, issue_slots[12].out_uop.inst node _T_292 = eq(shamts_oh[12], UInt<1>(0h1)) when _T_292 : connect issue_slots[11].in_uop.valid, issue_slots[12].will_be_valid connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm connect issue_slots[11].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype connect issue_slots[11].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 connect issue_slots[11].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 connect issue_slots[11].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 connect issue_slots[11].in_uop.bits.ldst, issue_slots[12].out_uop.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed connect issue_slots[11].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause connect issue_slots[11].in_uop.bits.exception, issue_slots[12].out_uop.exception connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy connect issue_slots[11].in_uop.bits.ppred, issue_slots[12].out_uop.ppred connect issue_slots[11].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 connect issue_slots[11].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 connect issue_slots[11].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 connect issue_slots[11].in_uop.bits.pdst, issue_slots[12].out_uop.pdst connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23 connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12 connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3 connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2 connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1 connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed connect issue_slots[11].in_uop.bits.pimm, issue_slots[12].out_uop.pimm connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename connect issue_slots[11].in_uop.bits.taken, issue_slots[12].out_uop.taken connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx connect issue_slots[11].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc connect issue_slots[11].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret connect issue_slots[11].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei connect issue_slots[11].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb connect issue_slots[11].in_uop.bits.br_type, issue_slots[12].out_uop.br_type connect issue_slots[11].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag connect issue_slots[11].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0] connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1] connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2] connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3] connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4] connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5] connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6] connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7] connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8] connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9] connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0] connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1] connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2] connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3] connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst connect issue_slots[11].in_uop.bits.inst, issue_slots[12].out_uop.inst node _T_293 = eq(shamts_oh[13], UInt<2>(0h2)) when _T_293 : connect issue_slots[11].in_uop.valid, issue_slots[13].will_be_valid connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm connect issue_slots[11].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype connect issue_slots[11].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 connect issue_slots[11].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 connect issue_slots[11].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 connect issue_slots[11].in_uop.bits.ldst, issue_slots[13].out_uop.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed connect issue_slots[11].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause connect issue_slots[11].in_uop.bits.exception, issue_slots[13].out_uop.exception connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy connect issue_slots[11].in_uop.bits.ppred, issue_slots[13].out_uop.ppred connect issue_slots[11].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 connect issue_slots[11].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 connect issue_slots[11].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 connect issue_slots[11].in_uop.bits.pdst, issue_slots[13].out_uop.pdst connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23 connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12 connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3 connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2 connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1 connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed connect issue_slots[11].in_uop.bits.pimm, issue_slots[13].out_uop.pimm connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename connect issue_slots[11].in_uop.bits.taken, issue_slots[13].out_uop.taken connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx connect issue_slots[11].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc connect issue_slots[11].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret connect issue_slots[11].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei connect issue_slots[11].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb connect issue_slots[11].in_uop.bits.br_type, issue_slots[13].out_uop.br_type connect issue_slots[11].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag connect issue_slots[11].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0] connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1] connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2] connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3] connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4] connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5] connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6] connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7] connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8] connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9] connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0] connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1] connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2] connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3] connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst connect issue_slots[11].in_uop.bits.inst, issue_slots[13].out_uop.inst node _T_294 = eq(shamts_oh[14], UInt<3>(0h4)) when _T_294 : connect issue_slots[11].in_uop.valid, issue_slots[14].will_be_valid connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm connect issue_slots[11].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype connect issue_slots[11].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 connect issue_slots[11].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 connect issue_slots[11].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 connect issue_slots[11].in_uop.bits.ldst, issue_slots[14].out_uop.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed connect issue_slots[11].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause connect issue_slots[11].in_uop.bits.exception, issue_slots[14].out_uop.exception connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy connect issue_slots[11].in_uop.bits.ppred, issue_slots[14].out_uop.ppred connect issue_slots[11].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 connect issue_slots[11].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 connect issue_slots[11].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 connect issue_slots[11].in_uop.bits.pdst, issue_slots[14].out_uop.pdst connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23 connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12 connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3 connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2 connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1 connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed connect issue_slots[11].in_uop.bits.pimm, issue_slots[14].out_uop.pimm connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename connect issue_slots[11].in_uop.bits.taken, issue_slots[14].out_uop.taken connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx connect issue_slots[11].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc connect issue_slots[11].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret connect issue_slots[11].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei connect issue_slots[11].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb connect issue_slots[11].in_uop.bits.br_type, issue_slots[14].out_uop.br_type connect issue_slots[11].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag connect issue_slots[11].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0] connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1] connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2] connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3] connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4] connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5] connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6] connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7] connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8] connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9] connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0] connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1] connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2] connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3] connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst connect issue_slots[11].in_uop.bits.inst, issue_slots[14].out_uop.inst node _issue_slots_11_clear_T = neq(shamts_oh[11], UInt<1>(0h0)) connect issue_slots[11].clear, _issue_slots_11_clear_T connect issue_slots[12].in_uop.valid, UInt<1>(0h0) connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm connect issue_slots[12].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype connect issue_slots[12].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 connect issue_slots[12].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 connect issue_slots[12].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 connect issue_slots[12].in_uop.bits.ldst, issue_slots[13].out_uop.ldst connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit connect issue_slots[12].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed connect issue_slots[12].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause connect issue_slots[12].in_uop.bits.exception, issue_slots[13].out_uop.exception connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy connect issue_slots[12].in_uop.bits.ppred, issue_slots[13].out_uop.ppred connect issue_slots[12].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 connect issue_slots[12].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 connect issue_slots[12].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 connect issue_slots[12].in_uop.bits.pdst, issue_slots[13].out_uop.pdst connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23 connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12 connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3 connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2 connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1 connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed connect issue_slots[12].in_uop.bits.pimm, issue_slots[13].out_uop.pimm connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename connect issue_slots[12].in_uop.bits.taken, issue_slots[13].out_uop.taken connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx connect issue_slots[12].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc connect issue_slots[12].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret connect issue_slots[12].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei connect issue_slots[12].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb connect issue_slots[12].in_uop.bits.br_type, issue_slots[13].out_uop.br_type connect issue_slots[12].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag connect issue_slots[12].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0] connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1] connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2] connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3] connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4] connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5] connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6] connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7] connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8] connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9] connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0] connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1] connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2] connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3] connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst connect issue_slots[12].in_uop.bits.inst, issue_slots[13].out_uop.inst node _T_295 = eq(shamts_oh[13], UInt<1>(0h1)) when _T_295 : connect issue_slots[12].in_uop.valid, issue_slots[13].will_be_valid connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm connect issue_slots[12].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype connect issue_slots[12].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 connect issue_slots[12].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 connect issue_slots[12].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 connect issue_slots[12].in_uop.bits.ldst, issue_slots[13].out_uop.ldst connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit connect issue_slots[12].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed connect issue_slots[12].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause connect issue_slots[12].in_uop.bits.exception, issue_slots[13].out_uop.exception connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy connect issue_slots[12].in_uop.bits.ppred, issue_slots[13].out_uop.ppred connect issue_slots[12].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 connect issue_slots[12].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 connect issue_slots[12].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 connect issue_slots[12].in_uop.bits.pdst, issue_slots[13].out_uop.pdst connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23 connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12 connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3 connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2 connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1 connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed connect issue_slots[12].in_uop.bits.pimm, issue_slots[13].out_uop.pimm connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename connect issue_slots[12].in_uop.bits.taken, issue_slots[13].out_uop.taken connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx connect issue_slots[12].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc connect issue_slots[12].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret connect issue_slots[12].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei connect issue_slots[12].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb connect issue_slots[12].in_uop.bits.br_type, issue_slots[13].out_uop.br_type connect issue_slots[12].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag connect issue_slots[12].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0] connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1] connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2] connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3] connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4] connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5] connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6] connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7] connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8] connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9] connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0] connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1] connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2] connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3] connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst connect issue_slots[12].in_uop.bits.inst, issue_slots[13].out_uop.inst node _T_296 = eq(shamts_oh[14], UInt<2>(0h2)) when _T_296 : connect issue_slots[12].in_uop.valid, issue_slots[14].will_be_valid connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm connect issue_slots[12].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype connect issue_slots[12].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 connect issue_slots[12].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 connect issue_slots[12].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 connect issue_slots[12].in_uop.bits.ldst, issue_slots[14].out_uop.ldst connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit connect issue_slots[12].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed connect issue_slots[12].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause connect issue_slots[12].in_uop.bits.exception, issue_slots[14].out_uop.exception connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy connect issue_slots[12].in_uop.bits.ppred, issue_slots[14].out_uop.ppred connect issue_slots[12].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 connect issue_slots[12].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 connect issue_slots[12].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 connect issue_slots[12].in_uop.bits.pdst, issue_slots[14].out_uop.pdst connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23 connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12 connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3 connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2 connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1 connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed connect issue_slots[12].in_uop.bits.pimm, issue_slots[14].out_uop.pimm connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename connect issue_slots[12].in_uop.bits.taken, issue_slots[14].out_uop.taken connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx connect issue_slots[12].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc connect issue_slots[12].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret connect issue_slots[12].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei connect issue_slots[12].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb connect issue_slots[12].in_uop.bits.br_type, issue_slots[14].out_uop.br_type connect issue_slots[12].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag connect issue_slots[12].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0] connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1] connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2] connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3] connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4] connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5] connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6] connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7] connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8] connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9] connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0] connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1] connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2] connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3] connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst connect issue_slots[12].in_uop.bits.inst, issue_slots[14].out_uop.inst node _T_297 = eq(shamts_oh[15], UInt<3>(0h4)) when _T_297 : connect issue_slots[12].in_uop.valid, issue_slots[15].will_be_valid connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm connect issue_slots[12].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype connect issue_slots[12].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 connect issue_slots[12].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 connect issue_slots[12].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 connect issue_slots[12].in_uop.bits.ldst, issue_slots[15].out_uop.ldst connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit connect issue_slots[12].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed connect issue_slots[12].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause connect issue_slots[12].in_uop.bits.exception, issue_slots[15].out_uop.exception connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy connect issue_slots[12].in_uop.bits.ppred, issue_slots[15].out_uop.ppred connect issue_slots[12].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 connect issue_slots[12].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 connect issue_slots[12].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 connect issue_slots[12].in_uop.bits.pdst, issue_slots[15].out_uop.pdst connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23 connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12 connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3 connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2 connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1 connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed connect issue_slots[12].in_uop.bits.pimm, issue_slots[15].out_uop.pimm connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename connect issue_slots[12].in_uop.bits.taken, issue_slots[15].out_uop.taken connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx connect issue_slots[12].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc connect issue_slots[12].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret connect issue_slots[12].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei connect issue_slots[12].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb connect issue_slots[12].in_uop.bits.br_type, issue_slots[15].out_uop.br_type connect issue_slots[12].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag connect issue_slots[12].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0] connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1] connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2] connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3] connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4] connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5] connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6] connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7] connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8] connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9] connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0] connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1] connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2] connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3] connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst connect issue_slots[12].in_uop.bits.inst, issue_slots[15].out_uop.inst node _issue_slots_12_clear_T = neq(shamts_oh[12], UInt<1>(0h0)) connect issue_slots[12].clear, _issue_slots_12_clear_T connect issue_slots[13].in_uop.valid, UInt<1>(0h0) connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if connect issue_slots[13].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ connect issue_slots[13].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm connect issue_slots[13].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val connect issue_slots[13].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op connect issue_slots[13].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype connect issue_slots[13].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 connect issue_slots[13].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 connect issue_slots[13].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 connect issue_slots[13].in_uop.bits.ldst, issue_slots[14].out_uop.ldst connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 connect issue_slots[13].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit connect issue_slots[13].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed connect issue_slots[13].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause connect issue_slots[13].in_uop.bits.exception, issue_slots[14].out_uop.exception connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy connect issue_slots[13].in_uop.bits.ppred, issue_slots[14].out_uop.ppred connect issue_slots[13].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 connect issue_slots[13].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 connect issue_slots[13].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 connect issue_slots[13].in_uop.bits.pdst, issue_slots[14].out_uop.pdst connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx connect issue_slots[13].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt connect issue_slots[13].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div connect issue_slots[13].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe connect issue_slots[13].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23 connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12 connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3 connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2 connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1 connect issue_slots[13].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst connect issue_slots[13].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel connect issue_slots[13].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed connect issue_slots[13].in_uop.bits.pimm, issue_slots[14].out_uop.pimm connect issue_slots[13].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel connect issue_slots[13].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename connect issue_slots[13].in_uop.bits.taken, issue_slots[14].out_uop.taken connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx connect issue_slots[13].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov connect issue_slots[13].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc connect issue_slots[13].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret connect issue_slots[13].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo connect issue_slots[13].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei connect issue_slots[13].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb connect issue_slots[13].in_uop.bits.br_type, issue_slots[14].out_uop.br_type connect issue_slots[13].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag connect issue_slots[13].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask connect issue_slots[13].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen connect issue_slots[13].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued connect issue_slots[13].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0] connect issue_slots[13].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1] connect issue_slots[13].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2] connect issue_slots[13].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3] connect issue_slots[13].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4] connect issue_slots[13].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5] connect issue_slots[13].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6] connect issue_slots[13].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7] connect issue_slots[13].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8] connect issue_slots[13].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9] connect issue_slots[13].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0] connect issue_slots[13].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1] connect issue_slots[13].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2] connect issue_slots[13].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3] connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst connect issue_slots[13].in_uop.bits.inst, issue_slots[14].out_uop.inst node _T_298 = eq(shamts_oh[14], UInt<1>(0h1)) when _T_298 : connect issue_slots[13].in_uop.valid, issue_slots[14].will_be_valid connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if connect issue_slots[13].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ connect issue_slots[13].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm connect issue_slots[13].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val connect issue_slots[13].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op connect issue_slots[13].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype connect issue_slots[13].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 connect issue_slots[13].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 connect issue_slots[13].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 connect issue_slots[13].in_uop.bits.ldst, issue_slots[14].out_uop.ldst connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 connect issue_slots[13].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit connect issue_slots[13].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed connect issue_slots[13].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause connect issue_slots[13].in_uop.bits.exception, issue_slots[14].out_uop.exception connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy connect issue_slots[13].in_uop.bits.ppred, issue_slots[14].out_uop.ppred connect issue_slots[13].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 connect issue_slots[13].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 connect issue_slots[13].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 connect issue_slots[13].in_uop.bits.pdst, issue_slots[14].out_uop.pdst connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx connect issue_slots[13].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt connect issue_slots[13].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div connect issue_slots[13].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe connect issue_slots[13].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23 connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12 connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3 connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2 connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1 connect issue_slots[13].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst connect issue_slots[13].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel connect issue_slots[13].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed connect issue_slots[13].in_uop.bits.pimm, issue_slots[14].out_uop.pimm connect issue_slots[13].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel connect issue_slots[13].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename connect issue_slots[13].in_uop.bits.taken, issue_slots[14].out_uop.taken connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx connect issue_slots[13].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov connect issue_slots[13].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc connect issue_slots[13].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret connect issue_slots[13].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo connect issue_slots[13].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei connect issue_slots[13].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb connect issue_slots[13].in_uop.bits.br_type, issue_slots[14].out_uop.br_type connect issue_slots[13].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag connect issue_slots[13].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask connect issue_slots[13].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen connect issue_slots[13].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued connect issue_slots[13].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0] connect issue_slots[13].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1] connect issue_slots[13].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2] connect issue_slots[13].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3] connect issue_slots[13].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4] connect issue_slots[13].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5] connect issue_slots[13].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6] connect issue_slots[13].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7] connect issue_slots[13].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8] connect issue_slots[13].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9] connect issue_slots[13].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0] connect issue_slots[13].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1] connect issue_slots[13].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2] connect issue_slots[13].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3] connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst connect issue_slots[13].in_uop.bits.inst, issue_slots[14].out_uop.inst node _T_299 = eq(shamts_oh[15], UInt<2>(0h2)) when _T_299 : connect issue_slots[13].in_uop.valid, issue_slots[15].will_be_valid connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if connect issue_slots[13].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ connect issue_slots[13].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm connect issue_slots[13].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val connect issue_slots[13].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op connect issue_slots[13].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype connect issue_slots[13].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 connect issue_slots[13].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 connect issue_slots[13].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 connect issue_slots[13].in_uop.bits.ldst, issue_slots[15].out_uop.ldst connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 connect issue_slots[13].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit connect issue_slots[13].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed connect issue_slots[13].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause connect issue_slots[13].in_uop.bits.exception, issue_slots[15].out_uop.exception connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy connect issue_slots[13].in_uop.bits.ppred, issue_slots[15].out_uop.ppred connect issue_slots[13].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 connect issue_slots[13].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 connect issue_slots[13].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 connect issue_slots[13].in_uop.bits.pdst, issue_slots[15].out_uop.pdst connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx connect issue_slots[13].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt connect issue_slots[13].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div connect issue_slots[13].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe connect issue_slots[13].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23 connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12 connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3 connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2 connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1 connect issue_slots[13].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst connect issue_slots[13].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel connect issue_slots[13].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed connect issue_slots[13].in_uop.bits.pimm, issue_slots[15].out_uop.pimm connect issue_slots[13].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel connect issue_slots[13].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename connect issue_slots[13].in_uop.bits.taken, issue_slots[15].out_uop.taken connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx connect issue_slots[13].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov connect issue_slots[13].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc connect issue_slots[13].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret connect issue_slots[13].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo connect issue_slots[13].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei connect issue_slots[13].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb connect issue_slots[13].in_uop.bits.br_type, issue_slots[15].out_uop.br_type connect issue_slots[13].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag connect issue_slots[13].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask connect issue_slots[13].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen connect issue_slots[13].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued connect issue_slots[13].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0] connect issue_slots[13].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1] connect issue_slots[13].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2] connect issue_slots[13].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3] connect issue_slots[13].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4] connect issue_slots[13].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5] connect issue_slots[13].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6] connect issue_slots[13].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7] connect issue_slots[13].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8] connect issue_slots[13].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9] connect issue_slots[13].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0] connect issue_slots[13].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1] connect issue_slots[13].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2] connect issue_slots[13].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3] connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst connect issue_slots[13].in_uop.bits.inst, issue_slots[15].out_uop.inst node _T_300 = eq(shamts_oh[16], UInt<3>(0h4)) when _T_300 : connect issue_slots[13].in_uop.valid, will_be_valid_16 connect issue_slots[13].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[13].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[13].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[13].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[13].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[13].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[13].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[13].in_uop.bits.fp_typ, _WIRE.fp_typ connect issue_slots[13].in_uop.bits.fp_rm, _WIRE.fp_rm connect issue_slots[13].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[13].in_uop.bits.fcn_op, _WIRE.fcn_op connect issue_slots[13].in_uop.bits.fcn_dw, _WIRE.fcn_dw connect issue_slots[13].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[13].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[13].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[13].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[13].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[13].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[13].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[13].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[13].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[13].in_uop.bits.csr_cmd, _WIRE.csr_cmd connect issue_slots[13].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[13].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[13].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[13].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[13].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[13].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[13].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[13].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[13].in_uop.bits.exception, _WIRE.exception connect issue_slots[13].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[13].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[13].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[13].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[13].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[13].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[13].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[13].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[13].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[13].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[13].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[13].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[13].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[13].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[13].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt connect issue_slots[13].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div connect issue_slots[13].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe connect issue_slots[13].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 connect issue_slots[13].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst connect issue_slots[13].in_uop.bits.op2_sel, _WIRE.op2_sel connect issue_slots[13].in_uop.bits.op1_sel, _WIRE.op1_sel connect issue_slots[13].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[13].in_uop.bits.pimm, _WIRE.pimm connect issue_slots[13].in_uop.bits.imm_sel, _WIRE.imm_sel connect issue_slots[13].in_uop.bits.imm_rename, _WIRE.imm_rename connect issue_slots[13].in_uop.bits.taken, _WIRE.taken connect issue_slots[13].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[13].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[13].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[13].in_uop.bits.is_mov, _WIRE.is_mov connect issue_slots[13].in_uop.bits.is_rocc, _WIRE.is_rocc connect issue_slots[13].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[13].in_uop.bits.is_eret, _WIRE.is_eret connect issue_slots[13].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[13].in_uop.bits.is_sfence, _WIRE.is_sfence connect issue_slots[13].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[13].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[13].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[13].in_uop.bits.br_type, _WIRE.br_type connect issue_slots[13].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[13].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[13].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen connect issue_slots[13].in_uop.bits.iw_issued, _WIRE.iw_issued connect issue_slots[13].in_uop.bits.fu_code[0], _WIRE.fu_code[0] connect issue_slots[13].in_uop.bits.fu_code[1], _WIRE.fu_code[1] connect issue_slots[13].in_uop.bits.fu_code[2], _WIRE.fu_code[2] connect issue_slots[13].in_uop.bits.fu_code[3], _WIRE.fu_code[3] connect issue_slots[13].in_uop.bits.fu_code[4], _WIRE.fu_code[4] connect issue_slots[13].in_uop.bits.fu_code[5], _WIRE.fu_code[5] connect issue_slots[13].in_uop.bits.fu_code[6], _WIRE.fu_code[6] connect issue_slots[13].in_uop.bits.fu_code[7], _WIRE.fu_code[7] connect issue_slots[13].in_uop.bits.fu_code[8], _WIRE.fu_code[8] connect issue_slots[13].in_uop.bits.fu_code[9], _WIRE.fu_code[9] connect issue_slots[13].in_uop.bits.iq_type[0], _WIRE.iq_type[0] connect issue_slots[13].in_uop.bits.iq_type[1], _WIRE.iq_type[1] connect issue_slots[13].in_uop.bits.iq_type[2], _WIRE.iq_type[2] connect issue_slots[13].in_uop.bits.iq_type[3], _WIRE.iq_type[3] connect issue_slots[13].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[13].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[13].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[13].in_uop.bits.inst, _WIRE.inst node _issue_slots_13_clear_T = neq(shamts_oh[13], UInt<1>(0h0)) connect issue_slots[13].clear, _issue_slots_13_clear_T connect issue_slots[14].in_uop.valid, UInt<1>(0h0) connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if connect issue_slots[14].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ connect issue_slots[14].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm connect issue_slots[14].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val connect issue_slots[14].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op connect issue_slots[14].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype connect issue_slots[14].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 connect issue_slots[14].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 connect issue_slots[14].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 connect issue_slots[14].in_uop.bits.ldst, issue_slots[15].out_uop.ldst connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 connect issue_slots[14].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit connect issue_slots[14].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed connect issue_slots[14].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause connect issue_slots[14].in_uop.bits.exception, issue_slots[15].out_uop.exception connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy connect issue_slots[14].in_uop.bits.ppred, issue_slots[15].out_uop.ppred connect issue_slots[14].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 connect issue_slots[14].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 connect issue_slots[14].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 connect issue_slots[14].in_uop.bits.pdst, issue_slots[15].out_uop.pdst connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx connect issue_slots[14].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt connect issue_slots[14].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div connect issue_slots[14].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe connect issue_slots[14].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23 connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12 connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3 connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2 connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1 connect issue_slots[14].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst connect issue_slots[14].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel connect issue_slots[14].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed connect issue_slots[14].in_uop.bits.pimm, issue_slots[15].out_uop.pimm connect issue_slots[14].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel connect issue_slots[14].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename connect issue_slots[14].in_uop.bits.taken, issue_slots[15].out_uop.taken connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx connect issue_slots[14].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov connect issue_slots[14].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc connect issue_slots[14].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret connect issue_slots[14].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo connect issue_slots[14].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei connect issue_slots[14].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb connect issue_slots[14].in_uop.bits.br_type, issue_slots[15].out_uop.br_type connect issue_slots[14].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag connect issue_slots[14].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask connect issue_slots[14].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen connect issue_slots[14].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued connect issue_slots[14].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0] connect issue_slots[14].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1] connect issue_slots[14].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2] connect issue_slots[14].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3] connect issue_slots[14].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4] connect issue_slots[14].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5] connect issue_slots[14].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6] connect issue_slots[14].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7] connect issue_slots[14].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8] connect issue_slots[14].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9] connect issue_slots[14].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0] connect issue_slots[14].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1] connect issue_slots[14].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2] connect issue_slots[14].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3] connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst connect issue_slots[14].in_uop.bits.inst, issue_slots[15].out_uop.inst node _T_301 = eq(shamts_oh[15], UInt<1>(0h1)) when _T_301 : connect issue_slots[14].in_uop.valid, issue_slots[15].will_be_valid connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if connect issue_slots[14].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ connect issue_slots[14].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm connect issue_slots[14].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val connect issue_slots[14].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op connect issue_slots[14].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype connect issue_slots[14].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 connect issue_slots[14].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 connect issue_slots[14].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 connect issue_slots[14].in_uop.bits.ldst, issue_slots[15].out_uop.ldst connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 connect issue_slots[14].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit connect issue_slots[14].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed connect issue_slots[14].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause connect issue_slots[14].in_uop.bits.exception, issue_slots[15].out_uop.exception connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy connect issue_slots[14].in_uop.bits.ppred, issue_slots[15].out_uop.ppred connect issue_slots[14].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 connect issue_slots[14].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 connect issue_slots[14].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 connect issue_slots[14].in_uop.bits.pdst, issue_slots[15].out_uop.pdst connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx connect issue_slots[14].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt connect issue_slots[14].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div connect issue_slots[14].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe connect issue_slots[14].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23 connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12 connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3 connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2 connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1 connect issue_slots[14].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst connect issue_slots[14].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel connect issue_slots[14].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed connect issue_slots[14].in_uop.bits.pimm, issue_slots[15].out_uop.pimm connect issue_slots[14].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel connect issue_slots[14].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename connect issue_slots[14].in_uop.bits.taken, issue_slots[15].out_uop.taken connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx connect issue_slots[14].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov connect issue_slots[14].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc connect issue_slots[14].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret connect issue_slots[14].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo connect issue_slots[14].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei connect issue_slots[14].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb connect issue_slots[14].in_uop.bits.br_type, issue_slots[15].out_uop.br_type connect issue_slots[14].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag connect issue_slots[14].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask connect issue_slots[14].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen connect issue_slots[14].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued connect issue_slots[14].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0] connect issue_slots[14].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1] connect issue_slots[14].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2] connect issue_slots[14].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3] connect issue_slots[14].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4] connect issue_slots[14].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5] connect issue_slots[14].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6] connect issue_slots[14].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7] connect issue_slots[14].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8] connect issue_slots[14].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9] connect issue_slots[14].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0] connect issue_slots[14].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1] connect issue_slots[14].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2] connect issue_slots[14].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3] connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst connect issue_slots[14].in_uop.bits.inst, issue_slots[15].out_uop.inst node _T_302 = eq(shamts_oh[16], UInt<2>(0h2)) when _T_302 : connect issue_slots[14].in_uop.valid, will_be_valid_16 connect issue_slots[14].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[14].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[14].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[14].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[14].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[14].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[14].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[14].in_uop.bits.fp_typ, _WIRE.fp_typ connect issue_slots[14].in_uop.bits.fp_rm, _WIRE.fp_rm connect issue_slots[14].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[14].in_uop.bits.fcn_op, _WIRE.fcn_op connect issue_slots[14].in_uop.bits.fcn_dw, _WIRE.fcn_dw connect issue_slots[14].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[14].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[14].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[14].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[14].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[14].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[14].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[14].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[14].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[14].in_uop.bits.csr_cmd, _WIRE.csr_cmd connect issue_slots[14].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[14].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[14].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[14].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[14].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[14].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[14].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[14].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[14].in_uop.bits.exception, _WIRE.exception connect issue_slots[14].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[14].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[14].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[14].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[14].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[14].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[14].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[14].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[14].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[14].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[14].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[14].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[14].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[14].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[14].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt connect issue_slots[14].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div connect issue_slots[14].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe connect issue_slots[14].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 connect issue_slots[14].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst connect issue_slots[14].in_uop.bits.op2_sel, _WIRE.op2_sel connect issue_slots[14].in_uop.bits.op1_sel, _WIRE.op1_sel connect issue_slots[14].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[14].in_uop.bits.pimm, _WIRE.pimm connect issue_slots[14].in_uop.bits.imm_sel, _WIRE.imm_sel connect issue_slots[14].in_uop.bits.imm_rename, _WIRE.imm_rename connect issue_slots[14].in_uop.bits.taken, _WIRE.taken connect issue_slots[14].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[14].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[14].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[14].in_uop.bits.is_mov, _WIRE.is_mov connect issue_slots[14].in_uop.bits.is_rocc, _WIRE.is_rocc connect issue_slots[14].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[14].in_uop.bits.is_eret, _WIRE.is_eret connect issue_slots[14].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[14].in_uop.bits.is_sfence, _WIRE.is_sfence connect issue_slots[14].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[14].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[14].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[14].in_uop.bits.br_type, _WIRE.br_type connect issue_slots[14].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[14].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[14].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen connect issue_slots[14].in_uop.bits.iw_issued, _WIRE.iw_issued connect issue_slots[14].in_uop.bits.fu_code[0], _WIRE.fu_code[0] connect issue_slots[14].in_uop.bits.fu_code[1], _WIRE.fu_code[1] connect issue_slots[14].in_uop.bits.fu_code[2], _WIRE.fu_code[2] connect issue_slots[14].in_uop.bits.fu_code[3], _WIRE.fu_code[3] connect issue_slots[14].in_uop.bits.fu_code[4], _WIRE.fu_code[4] connect issue_slots[14].in_uop.bits.fu_code[5], _WIRE.fu_code[5] connect issue_slots[14].in_uop.bits.fu_code[6], _WIRE.fu_code[6] connect issue_slots[14].in_uop.bits.fu_code[7], _WIRE.fu_code[7] connect issue_slots[14].in_uop.bits.fu_code[8], _WIRE.fu_code[8] connect issue_slots[14].in_uop.bits.fu_code[9], _WIRE.fu_code[9] connect issue_slots[14].in_uop.bits.iq_type[0], _WIRE.iq_type[0] connect issue_slots[14].in_uop.bits.iq_type[1], _WIRE.iq_type[1] connect issue_slots[14].in_uop.bits.iq_type[2], _WIRE.iq_type[2] connect issue_slots[14].in_uop.bits.iq_type[3], _WIRE.iq_type[3] connect issue_slots[14].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[14].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[14].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[14].in_uop.bits.inst, _WIRE.inst node _T_303 = eq(shamts_oh[17], UInt<3>(0h4)) when _T_303 : connect issue_slots[14].in_uop.valid, will_be_valid_17 connect issue_slots[14].in_uop.bits.debug_tsrc, _WIRE_1.debug_tsrc connect issue_slots[14].in_uop.bits.debug_fsrc, _WIRE_1.debug_fsrc connect issue_slots[14].in_uop.bits.bp_xcpt_if, _WIRE_1.bp_xcpt_if connect issue_slots[14].in_uop.bits.bp_debug_if, _WIRE_1.bp_debug_if connect issue_slots[14].in_uop.bits.xcpt_ma_if, _WIRE_1.xcpt_ma_if connect issue_slots[14].in_uop.bits.xcpt_ae_if, _WIRE_1.xcpt_ae_if connect issue_slots[14].in_uop.bits.xcpt_pf_if, _WIRE_1.xcpt_pf_if connect issue_slots[14].in_uop.bits.fp_typ, _WIRE_1.fp_typ connect issue_slots[14].in_uop.bits.fp_rm, _WIRE_1.fp_rm connect issue_slots[14].in_uop.bits.fp_val, _WIRE_1.fp_val connect issue_slots[14].in_uop.bits.fcn_op, _WIRE_1.fcn_op connect issue_slots[14].in_uop.bits.fcn_dw, _WIRE_1.fcn_dw connect issue_slots[14].in_uop.bits.frs3_en, _WIRE_1.frs3_en connect issue_slots[14].in_uop.bits.lrs2_rtype, _WIRE_1.lrs2_rtype connect issue_slots[14].in_uop.bits.lrs1_rtype, _WIRE_1.lrs1_rtype connect issue_slots[14].in_uop.bits.dst_rtype, _WIRE_1.dst_rtype connect issue_slots[14].in_uop.bits.lrs3, _WIRE_1.lrs3 connect issue_slots[14].in_uop.bits.lrs2, _WIRE_1.lrs2 connect issue_slots[14].in_uop.bits.lrs1, _WIRE_1.lrs1 connect issue_slots[14].in_uop.bits.ldst, _WIRE_1.ldst connect issue_slots[14].in_uop.bits.ldst_is_rs1, _WIRE_1.ldst_is_rs1 connect issue_slots[14].in_uop.bits.csr_cmd, _WIRE_1.csr_cmd connect issue_slots[14].in_uop.bits.flush_on_commit, _WIRE_1.flush_on_commit connect issue_slots[14].in_uop.bits.is_unique, _WIRE_1.is_unique connect issue_slots[14].in_uop.bits.uses_stq, _WIRE_1.uses_stq connect issue_slots[14].in_uop.bits.uses_ldq, _WIRE_1.uses_ldq connect issue_slots[14].in_uop.bits.mem_signed, _WIRE_1.mem_signed connect issue_slots[14].in_uop.bits.mem_size, _WIRE_1.mem_size connect issue_slots[14].in_uop.bits.mem_cmd, _WIRE_1.mem_cmd connect issue_slots[14].in_uop.bits.exc_cause, _WIRE_1.exc_cause connect issue_slots[14].in_uop.bits.exception, _WIRE_1.exception connect issue_slots[14].in_uop.bits.stale_pdst, _WIRE_1.stale_pdst connect issue_slots[14].in_uop.bits.ppred_busy, _WIRE_1.ppred_busy connect issue_slots[14].in_uop.bits.prs3_busy, _WIRE_1.prs3_busy connect issue_slots[14].in_uop.bits.prs2_busy, _WIRE_1.prs2_busy connect issue_slots[14].in_uop.bits.prs1_busy, _WIRE_1.prs1_busy connect issue_slots[14].in_uop.bits.ppred, _WIRE_1.ppred connect issue_slots[14].in_uop.bits.prs3, _WIRE_1.prs3 connect issue_slots[14].in_uop.bits.prs2, _WIRE_1.prs2 connect issue_slots[14].in_uop.bits.prs1, _WIRE_1.prs1 connect issue_slots[14].in_uop.bits.pdst, _WIRE_1.pdst connect issue_slots[14].in_uop.bits.rxq_idx, _WIRE_1.rxq_idx connect issue_slots[14].in_uop.bits.stq_idx, _WIRE_1.stq_idx connect issue_slots[14].in_uop.bits.ldq_idx, _WIRE_1.ldq_idx connect issue_slots[14].in_uop.bits.rob_idx, _WIRE_1.rob_idx connect issue_slots[14].in_uop.bits.fp_ctrl.vec, _WIRE_1.fp_ctrl.vec connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, _WIRE_1.fp_ctrl.wflags connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, _WIRE_1.fp_ctrl.sqrt connect issue_slots[14].in_uop.bits.fp_ctrl.div, _WIRE_1.fp_ctrl.div connect issue_slots[14].in_uop.bits.fp_ctrl.fma, _WIRE_1.fp_ctrl.fma connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, _WIRE_1.fp_ctrl.fastpipe connect issue_slots[14].in_uop.bits.fp_ctrl.toint, _WIRE_1.fp_ctrl.toint connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, _WIRE_1.fp_ctrl.fromint connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, _WIRE_1.fp_ctrl.typeTagOut connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, _WIRE_1.fp_ctrl.typeTagIn connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, _WIRE_1.fp_ctrl.swap23 connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, _WIRE_1.fp_ctrl.swap12 connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, _WIRE_1.fp_ctrl.ren3 connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, _WIRE_1.fp_ctrl.ren2 connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, _WIRE_1.fp_ctrl.ren1 connect issue_slots[14].in_uop.bits.fp_ctrl.wen, _WIRE_1.fp_ctrl.wen connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, _WIRE_1.fp_ctrl.ldst connect issue_slots[14].in_uop.bits.op2_sel, _WIRE_1.op2_sel connect issue_slots[14].in_uop.bits.op1_sel, _WIRE_1.op1_sel connect issue_slots[14].in_uop.bits.imm_packed, _WIRE_1.imm_packed connect issue_slots[14].in_uop.bits.pimm, _WIRE_1.pimm connect issue_slots[14].in_uop.bits.imm_sel, _WIRE_1.imm_sel connect issue_slots[14].in_uop.bits.imm_rename, _WIRE_1.imm_rename connect issue_slots[14].in_uop.bits.taken, _WIRE_1.taken connect issue_slots[14].in_uop.bits.pc_lob, _WIRE_1.pc_lob connect issue_slots[14].in_uop.bits.edge_inst, _WIRE_1.edge_inst connect issue_slots[14].in_uop.bits.ftq_idx, _WIRE_1.ftq_idx connect issue_slots[14].in_uop.bits.is_mov, _WIRE_1.is_mov connect issue_slots[14].in_uop.bits.is_rocc, _WIRE_1.is_rocc connect issue_slots[14].in_uop.bits.is_sys_pc2epc, _WIRE_1.is_sys_pc2epc connect issue_slots[14].in_uop.bits.is_eret, _WIRE_1.is_eret connect issue_slots[14].in_uop.bits.is_amo, _WIRE_1.is_amo connect issue_slots[14].in_uop.bits.is_sfence, _WIRE_1.is_sfence connect issue_slots[14].in_uop.bits.is_fencei, _WIRE_1.is_fencei connect issue_slots[14].in_uop.bits.is_fence, _WIRE_1.is_fence connect issue_slots[14].in_uop.bits.is_sfb, _WIRE_1.is_sfb connect issue_slots[14].in_uop.bits.br_type, _WIRE_1.br_type connect issue_slots[14].in_uop.bits.br_tag, _WIRE_1.br_tag connect issue_slots[14].in_uop.bits.br_mask, _WIRE_1.br_mask connect issue_slots[14].in_uop.bits.dis_col_sel, _WIRE_1.dis_col_sel connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, _WIRE_1.iw_p3_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, _WIRE_1.iw_p2_bypass_hint connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, _WIRE_1.iw_p1_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, _WIRE_1.iw_p2_speculative_child connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, _WIRE_1.iw_p1_speculative_child connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, _WIRE_1.iw_issued_partial_dgen connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, _WIRE_1.iw_issued_partial_agen connect issue_slots[14].in_uop.bits.iw_issued, _WIRE_1.iw_issued connect issue_slots[14].in_uop.bits.fu_code[0], _WIRE_1.fu_code[0] connect issue_slots[14].in_uop.bits.fu_code[1], _WIRE_1.fu_code[1] connect issue_slots[14].in_uop.bits.fu_code[2], _WIRE_1.fu_code[2] connect issue_slots[14].in_uop.bits.fu_code[3], _WIRE_1.fu_code[3] connect issue_slots[14].in_uop.bits.fu_code[4], _WIRE_1.fu_code[4] connect issue_slots[14].in_uop.bits.fu_code[5], _WIRE_1.fu_code[5] connect issue_slots[14].in_uop.bits.fu_code[6], _WIRE_1.fu_code[6] connect issue_slots[14].in_uop.bits.fu_code[7], _WIRE_1.fu_code[7] connect issue_slots[14].in_uop.bits.fu_code[8], _WIRE_1.fu_code[8] connect issue_slots[14].in_uop.bits.fu_code[9], _WIRE_1.fu_code[9] connect issue_slots[14].in_uop.bits.iq_type[0], _WIRE_1.iq_type[0] connect issue_slots[14].in_uop.bits.iq_type[1], _WIRE_1.iq_type[1] connect issue_slots[14].in_uop.bits.iq_type[2], _WIRE_1.iq_type[2] connect issue_slots[14].in_uop.bits.iq_type[3], _WIRE_1.iq_type[3] connect issue_slots[14].in_uop.bits.debug_pc, _WIRE_1.debug_pc connect issue_slots[14].in_uop.bits.is_rvc, _WIRE_1.is_rvc connect issue_slots[14].in_uop.bits.debug_inst, _WIRE_1.debug_inst connect issue_slots[14].in_uop.bits.inst, _WIRE_1.inst node _issue_slots_14_clear_T = neq(shamts_oh[14], UInt<1>(0h0)) connect issue_slots[14].clear, _issue_slots_14_clear_T connect issue_slots[15].in_uop.valid, UInt<1>(0h0) connect issue_slots[15].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[15].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[15].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[15].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[15].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[15].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[15].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[15].in_uop.bits.fp_typ, _WIRE.fp_typ connect issue_slots[15].in_uop.bits.fp_rm, _WIRE.fp_rm connect issue_slots[15].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[15].in_uop.bits.fcn_op, _WIRE.fcn_op connect issue_slots[15].in_uop.bits.fcn_dw, _WIRE.fcn_dw connect issue_slots[15].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[15].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[15].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[15].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[15].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[15].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[15].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[15].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[15].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[15].in_uop.bits.csr_cmd, _WIRE.csr_cmd connect issue_slots[15].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[15].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[15].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[15].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[15].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[15].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[15].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[15].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[15].in_uop.bits.exception, _WIRE.exception connect issue_slots[15].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[15].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[15].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[15].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[15].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[15].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[15].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[15].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[15].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[15].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[15].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[15].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[15].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[15].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[15].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt connect issue_slots[15].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div connect issue_slots[15].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe connect issue_slots[15].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 connect issue_slots[15].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst connect issue_slots[15].in_uop.bits.op2_sel, _WIRE.op2_sel connect issue_slots[15].in_uop.bits.op1_sel, _WIRE.op1_sel connect issue_slots[15].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[15].in_uop.bits.pimm, _WIRE.pimm connect issue_slots[15].in_uop.bits.imm_sel, _WIRE.imm_sel connect issue_slots[15].in_uop.bits.imm_rename, _WIRE.imm_rename connect issue_slots[15].in_uop.bits.taken, _WIRE.taken connect issue_slots[15].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[15].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[15].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[15].in_uop.bits.is_mov, _WIRE.is_mov connect issue_slots[15].in_uop.bits.is_rocc, _WIRE.is_rocc connect issue_slots[15].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[15].in_uop.bits.is_eret, _WIRE.is_eret connect issue_slots[15].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[15].in_uop.bits.is_sfence, _WIRE.is_sfence connect issue_slots[15].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[15].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[15].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[15].in_uop.bits.br_type, _WIRE.br_type connect issue_slots[15].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[15].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[15].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen connect issue_slots[15].in_uop.bits.iw_issued, _WIRE.iw_issued connect issue_slots[15].in_uop.bits.fu_code[0], _WIRE.fu_code[0] connect issue_slots[15].in_uop.bits.fu_code[1], _WIRE.fu_code[1] connect issue_slots[15].in_uop.bits.fu_code[2], _WIRE.fu_code[2] connect issue_slots[15].in_uop.bits.fu_code[3], _WIRE.fu_code[3] connect issue_slots[15].in_uop.bits.fu_code[4], _WIRE.fu_code[4] connect issue_slots[15].in_uop.bits.fu_code[5], _WIRE.fu_code[5] connect issue_slots[15].in_uop.bits.fu_code[6], _WIRE.fu_code[6] connect issue_slots[15].in_uop.bits.fu_code[7], _WIRE.fu_code[7] connect issue_slots[15].in_uop.bits.fu_code[8], _WIRE.fu_code[8] connect issue_slots[15].in_uop.bits.fu_code[9], _WIRE.fu_code[9] connect issue_slots[15].in_uop.bits.iq_type[0], _WIRE.iq_type[0] connect issue_slots[15].in_uop.bits.iq_type[1], _WIRE.iq_type[1] connect issue_slots[15].in_uop.bits.iq_type[2], _WIRE.iq_type[2] connect issue_slots[15].in_uop.bits.iq_type[3], _WIRE.iq_type[3] connect issue_slots[15].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[15].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[15].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[15].in_uop.bits.inst, _WIRE.inst node _T_304 = eq(shamts_oh[16], UInt<1>(0h1)) when _T_304 : connect issue_slots[15].in_uop.valid, will_be_valid_16 connect issue_slots[15].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[15].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[15].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[15].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[15].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[15].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[15].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[15].in_uop.bits.fp_typ, _WIRE.fp_typ connect issue_slots[15].in_uop.bits.fp_rm, _WIRE.fp_rm connect issue_slots[15].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[15].in_uop.bits.fcn_op, _WIRE.fcn_op connect issue_slots[15].in_uop.bits.fcn_dw, _WIRE.fcn_dw connect issue_slots[15].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[15].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[15].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[15].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[15].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[15].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[15].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[15].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[15].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[15].in_uop.bits.csr_cmd, _WIRE.csr_cmd connect issue_slots[15].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[15].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[15].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[15].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[15].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[15].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[15].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[15].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[15].in_uop.bits.exception, _WIRE.exception connect issue_slots[15].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[15].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[15].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[15].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[15].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[15].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[15].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[15].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[15].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[15].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[15].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[15].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[15].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[15].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[15].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt connect issue_slots[15].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div connect issue_slots[15].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe connect issue_slots[15].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 connect issue_slots[15].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst connect issue_slots[15].in_uop.bits.op2_sel, _WIRE.op2_sel connect issue_slots[15].in_uop.bits.op1_sel, _WIRE.op1_sel connect issue_slots[15].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[15].in_uop.bits.pimm, _WIRE.pimm connect issue_slots[15].in_uop.bits.imm_sel, _WIRE.imm_sel connect issue_slots[15].in_uop.bits.imm_rename, _WIRE.imm_rename connect issue_slots[15].in_uop.bits.taken, _WIRE.taken connect issue_slots[15].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[15].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[15].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[15].in_uop.bits.is_mov, _WIRE.is_mov connect issue_slots[15].in_uop.bits.is_rocc, _WIRE.is_rocc connect issue_slots[15].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[15].in_uop.bits.is_eret, _WIRE.is_eret connect issue_slots[15].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[15].in_uop.bits.is_sfence, _WIRE.is_sfence connect issue_slots[15].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[15].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[15].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[15].in_uop.bits.br_type, _WIRE.br_type connect issue_slots[15].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[15].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[15].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen connect issue_slots[15].in_uop.bits.iw_issued, _WIRE.iw_issued connect issue_slots[15].in_uop.bits.fu_code[0], _WIRE.fu_code[0] connect issue_slots[15].in_uop.bits.fu_code[1], _WIRE.fu_code[1] connect issue_slots[15].in_uop.bits.fu_code[2], _WIRE.fu_code[2] connect issue_slots[15].in_uop.bits.fu_code[3], _WIRE.fu_code[3] connect issue_slots[15].in_uop.bits.fu_code[4], _WIRE.fu_code[4] connect issue_slots[15].in_uop.bits.fu_code[5], _WIRE.fu_code[5] connect issue_slots[15].in_uop.bits.fu_code[6], _WIRE.fu_code[6] connect issue_slots[15].in_uop.bits.fu_code[7], _WIRE.fu_code[7] connect issue_slots[15].in_uop.bits.fu_code[8], _WIRE.fu_code[8] connect issue_slots[15].in_uop.bits.fu_code[9], _WIRE.fu_code[9] connect issue_slots[15].in_uop.bits.iq_type[0], _WIRE.iq_type[0] connect issue_slots[15].in_uop.bits.iq_type[1], _WIRE.iq_type[1] connect issue_slots[15].in_uop.bits.iq_type[2], _WIRE.iq_type[2] connect issue_slots[15].in_uop.bits.iq_type[3], _WIRE.iq_type[3] connect issue_slots[15].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[15].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[15].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[15].in_uop.bits.inst, _WIRE.inst node _T_305 = eq(shamts_oh[17], UInt<2>(0h2)) when _T_305 : connect issue_slots[15].in_uop.valid, will_be_valid_17 connect issue_slots[15].in_uop.bits.debug_tsrc, _WIRE_1.debug_tsrc connect issue_slots[15].in_uop.bits.debug_fsrc, _WIRE_1.debug_fsrc connect issue_slots[15].in_uop.bits.bp_xcpt_if, _WIRE_1.bp_xcpt_if connect issue_slots[15].in_uop.bits.bp_debug_if, _WIRE_1.bp_debug_if connect issue_slots[15].in_uop.bits.xcpt_ma_if, _WIRE_1.xcpt_ma_if connect issue_slots[15].in_uop.bits.xcpt_ae_if, _WIRE_1.xcpt_ae_if connect issue_slots[15].in_uop.bits.xcpt_pf_if, _WIRE_1.xcpt_pf_if connect issue_slots[15].in_uop.bits.fp_typ, _WIRE_1.fp_typ connect issue_slots[15].in_uop.bits.fp_rm, _WIRE_1.fp_rm connect issue_slots[15].in_uop.bits.fp_val, _WIRE_1.fp_val connect issue_slots[15].in_uop.bits.fcn_op, _WIRE_1.fcn_op connect issue_slots[15].in_uop.bits.fcn_dw, _WIRE_1.fcn_dw connect issue_slots[15].in_uop.bits.frs3_en, _WIRE_1.frs3_en connect issue_slots[15].in_uop.bits.lrs2_rtype, _WIRE_1.lrs2_rtype connect issue_slots[15].in_uop.bits.lrs1_rtype, _WIRE_1.lrs1_rtype connect issue_slots[15].in_uop.bits.dst_rtype, _WIRE_1.dst_rtype connect issue_slots[15].in_uop.bits.lrs3, _WIRE_1.lrs3 connect issue_slots[15].in_uop.bits.lrs2, _WIRE_1.lrs2 connect issue_slots[15].in_uop.bits.lrs1, _WIRE_1.lrs1 connect issue_slots[15].in_uop.bits.ldst, _WIRE_1.ldst connect issue_slots[15].in_uop.bits.ldst_is_rs1, _WIRE_1.ldst_is_rs1 connect issue_slots[15].in_uop.bits.csr_cmd, _WIRE_1.csr_cmd connect issue_slots[15].in_uop.bits.flush_on_commit, _WIRE_1.flush_on_commit connect issue_slots[15].in_uop.bits.is_unique, _WIRE_1.is_unique connect issue_slots[15].in_uop.bits.uses_stq, _WIRE_1.uses_stq connect issue_slots[15].in_uop.bits.uses_ldq, _WIRE_1.uses_ldq connect issue_slots[15].in_uop.bits.mem_signed, _WIRE_1.mem_signed connect issue_slots[15].in_uop.bits.mem_size, _WIRE_1.mem_size connect issue_slots[15].in_uop.bits.mem_cmd, _WIRE_1.mem_cmd connect issue_slots[15].in_uop.bits.exc_cause, _WIRE_1.exc_cause connect issue_slots[15].in_uop.bits.exception, _WIRE_1.exception connect issue_slots[15].in_uop.bits.stale_pdst, _WIRE_1.stale_pdst connect issue_slots[15].in_uop.bits.ppred_busy, _WIRE_1.ppred_busy connect issue_slots[15].in_uop.bits.prs3_busy, _WIRE_1.prs3_busy connect issue_slots[15].in_uop.bits.prs2_busy, _WIRE_1.prs2_busy connect issue_slots[15].in_uop.bits.prs1_busy, _WIRE_1.prs1_busy connect issue_slots[15].in_uop.bits.ppred, _WIRE_1.ppred connect issue_slots[15].in_uop.bits.prs3, _WIRE_1.prs3 connect issue_slots[15].in_uop.bits.prs2, _WIRE_1.prs2 connect issue_slots[15].in_uop.bits.prs1, _WIRE_1.prs1 connect issue_slots[15].in_uop.bits.pdst, _WIRE_1.pdst connect issue_slots[15].in_uop.bits.rxq_idx, _WIRE_1.rxq_idx connect issue_slots[15].in_uop.bits.stq_idx, _WIRE_1.stq_idx connect issue_slots[15].in_uop.bits.ldq_idx, _WIRE_1.ldq_idx connect issue_slots[15].in_uop.bits.rob_idx, _WIRE_1.rob_idx connect issue_slots[15].in_uop.bits.fp_ctrl.vec, _WIRE_1.fp_ctrl.vec connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, _WIRE_1.fp_ctrl.wflags connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, _WIRE_1.fp_ctrl.sqrt connect issue_slots[15].in_uop.bits.fp_ctrl.div, _WIRE_1.fp_ctrl.div connect issue_slots[15].in_uop.bits.fp_ctrl.fma, _WIRE_1.fp_ctrl.fma connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, _WIRE_1.fp_ctrl.fastpipe connect issue_slots[15].in_uop.bits.fp_ctrl.toint, _WIRE_1.fp_ctrl.toint connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, _WIRE_1.fp_ctrl.fromint connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, _WIRE_1.fp_ctrl.typeTagOut connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, _WIRE_1.fp_ctrl.typeTagIn connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, _WIRE_1.fp_ctrl.swap23 connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, _WIRE_1.fp_ctrl.swap12 connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, _WIRE_1.fp_ctrl.ren3 connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, _WIRE_1.fp_ctrl.ren2 connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, _WIRE_1.fp_ctrl.ren1 connect issue_slots[15].in_uop.bits.fp_ctrl.wen, _WIRE_1.fp_ctrl.wen connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, _WIRE_1.fp_ctrl.ldst connect issue_slots[15].in_uop.bits.op2_sel, _WIRE_1.op2_sel connect issue_slots[15].in_uop.bits.op1_sel, _WIRE_1.op1_sel connect issue_slots[15].in_uop.bits.imm_packed, _WIRE_1.imm_packed connect issue_slots[15].in_uop.bits.pimm, _WIRE_1.pimm connect issue_slots[15].in_uop.bits.imm_sel, _WIRE_1.imm_sel connect issue_slots[15].in_uop.bits.imm_rename, _WIRE_1.imm_rename connect issue_slots[15].in_uop.bits.taken, _WIRE_1.taken connect issue_slots[15].in_uop.bits.pc_lob, _WIRE_1.pc_lob connect issue_slots[15].in_uop.bits.edge_inst, _WIRE_1.edge_inst connect issue_slots[15].in_uop.bits.ftq_idx, _WIRE_1.ftq_idx connect issue_slots[15].in_uop.bits.is_mov, _WIRE_1.is_mov connect issue_slots[15].in_uop.bits.is_rocc, _WIRE_1.is_rocc connect issue_slots[15].in_uop.bits.is_sys_pc2epc, _WIRE_1.is_sys_pc2epc connect issue_slots[15].in_uop.bits.is_eret, _WIRE_1.is_eret connect issue_slots[15].in_uop.bits.is_amo, _WIRE_1.is_amo connect issue_slots[15].in_uop.bits.is_sfence, _WIRE_1.is_sfence connect issue_slots[15].in_uop.bits.is_fencei, _WIRE_1.is_fencei connect issue_slots[15].in_uop.bits.is_fence, _WIRE_1.is_fence connect issue_slots[15].in_uop.bits.is_sfb, _WIRE_1.is_sfb connect issue_slots[15].in_uop.bits.br_type, _WIRE_1.br_type connect issue_slots[15].in_uop.bits.br_tag, _WIRE_1.br_tag connect issue_slots[15].in_uop.bits.br_mask, _WIRE_1.br_mask connect issue_slots[15].in_uop.bits.dis_col_sel, _WIRE_1.dis_col_sel connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, _WIRE_1.iw_p3_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, _WIRE_1.iw_p2_bypass_hint connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, _WIRE_1.iw_p1_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, _WIRE_1.iw_p2_speculative_child connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, _WIRE_1.iw_p1_speculative_child connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, _WIRE_1.iw_issued_partial_dgen connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, _WIRE_1.iw_issued_partial_agen connect issue_slots[15].in_uop.bits.iw_issued, _WIRE_1.iw_issued connect issue_slots[15].in_uop.bits.fu_code[0], _WIRE_1.fu_code[0] connect issue_slots[15].in_uop.bits.fu_code[1], _WIRE_1.fu_code[1] connect issue_slots[15].in_uop.bits.fu_code[2], _WIRE_1.fu_code[2] connect issue_slots[15].in_uop.bits.fu_code[3], _WIRE_1.fu_code[3] connect issue_slots[15].in_uop.bits.fu_code[4], _WIRE_1.fu_code[4] connect issue_slots[15].in_uop.bits.fu_code[5], _WIRE_1.fu_code[5] connect issue_slots[15].in_uop.bits.fu_code[6], _WIRE_1.fu_code[6] connect issue_slots[15].in_uop.bits.fu_code[7], _WIRE_1.fu_code[7] connect issue_slots[15].in_uop.bits.fu_code[8], _WIRE_1.fu_code[8] connect issue_slots[15].in_uop.bits.fu_code[9], _WIRE_1.fu_code[9] connect issue_slots[15].in_uop.bits.iq_type[0], _WIRE_1.iq_type[0] connect issue_slots[15].in_uop.bits.iq_type[1], _WIRE_1.iq_type[1] connect issue_slots[15].in_uop.bits.iq_type[2], _WIRE_1.iq_type[2] connect issue_slots[15].in_uop.bits.iq_type[3], _WIRE_1.iq_type[3] connect issue_slots[15].in_uop.bits.debug_pc, _WIRE_1.debug_pc connect issue_slots[15].in_uop.bits.is_rvc, _WIRE_1.is_rvc connect issue_slots[15].in_uop.bits.debug_inst, _WIRE_1.debug_inst connect issue_slots[15].in_uop.bits.inst, _WIRE_1.inst node _T_306 = eq(shamts_oh[18], UInt<3>(0h4)) when _T_306 : connect issue_slots[15].in_uop.valid, will_be_valid_18 connect issue_slots[15].in_uop.bits.debug_tsrc, _WIRE_2.debug_tsrc connect issue_slots[15].in_uop.bits.debug_fsrc, _WIRE_2.debug_fsrc connect issue_slots[15].in_uop.bits.bp_xcpt_if, _WIRE_2.bp_xcpt_if connect issue_slots[15].in_uop.bits.bp_debug_if, _WIRE_2.bp_debug_if connect issue_slots[15].in_uop.bits.xcpt_ma_if, _WIRE_2.xcpt_ma_if connect issue_slots[15].in_uop.bits.xcpt_ae_if, _WIRE_2.xcpt_ae_if connect issue_slots[15].in_uop.bits.xcpt_pf_if, _WIRE_2.xcpt_pf_if connect issue_slots[15].in_uop.bits.fp_typ, _WIRE_2.fp_typ connect issue_slots[15].in_uop.bits.fp_rm, _WIRE_2.fp_rm connect issue_slots[15].in_uop.bits.fp_val, _WIRE_2.fp_val connect issue_slots[15].in_uop.bits.fcn_op, _WIRE_2.fcn_op connect issue_slots[15].in_uop.bits.fcn_dw, _WIRE_2.fcn_dw connect issue_slots[15].in_uop.bits.frs3_en, _WIRE_2.frs3_en connect issue_slots[15].in_uop.bits.lrs2_rtype, _WIRE_2.lrs2_rtype connect issue_slots[15].in_uop.bits.lrs1_rtype, _WIRE_2.lrs1_rtype connect issue_slots[15].in_uop.bits.dst_rtype, _WIRE_2.dst_rtype connect issue_slots[15].in_uop.bits.lrs3, _WIRE_2.lrs3 connect issue_slots[15].in_uop.bits.lrs2, _WIRE_2.lrs2 connect issue_slots[15].in_uop.bits.lrs1, _WIRE_2.lrs1 connect issue_slots[15].in_uop.bits.ldst, _WIRE_2.ldst connect issue_slots[15].in_uop.bits.ldst_is_rs1, _WIRE_2.ldst_is_rs1 connect issue_slots[15].in_uop.bits.csr_cmd, _WIRE_2.csr_cmd connect issue_slots[15].in_uop.bits.flush_on_commit, _WIRE_2.flush_on_commit connect issue_slots[15].in_uop.bits.is_unique, _WIRE_2.is_unique connect issue_slots[15].in_uop.bits.uses_stq, _WIRE_2.uses_stq connect issue_slots[15].in_uop.bits.uses_ldq, _WIRE_2.uses_ldq connect issue_slots[15].in_uop.bits.mem_signed, _WIRE_2.mem_signed connect issue_slots[15].in_uop.bits.mem_size, _WIRE_2.mem_size connect issue_slots[15].in_uop.bits.mem_cmd, _WIRE_2.mem_cmd connect issue_slots[15].in_uop.bits.exc_cause, _WIRE_2.exc_cause connect issue_slots[15].in_uop.bits.exception, _WIRE_2.exception connect issue_slots[15].in_uop.bits.stale_pdst, _WIRE_2.stale_pdst connect issue_slots[15].in_uop.bits.ppred_busy, _WIRE_2.ppred_busy connect issue_slots[15].in_uop.bits.prs3_busy, _WIRE_2.prs3_busy connect issue_slots[15].in_uop.bits.prs2_busy, _WIRE_2.prs2_busy connect issue_slots[15].in_uop.bits.prs1_busy, _WIRE_2.prs1_busy connect issue_slots[15].in_uop.bits.ppred, _WIRE_2.ppred connect issue_slots[15].in_uop.bits.prs3, _WIRE_2.prs3 connect issue_slots[15].in_uop.bits.prs2, _WIRE_2.prs2 connect issue_slots[15].in_uop.bits.prs1, _WIRE_2.prs1 connect issue_slots[15].in_uop.bits.pdst, _WIRE_2.pdst connect issue_slots[15].in_uop.bits.rxq_idx, _WIRE_2.rxq_idx connect issue_slots[15].in_uop.bits.stq_idx, _WIRE_2.stq_idx connect issue_slots[15].in_uop.bits.ldq_idx, _WIRE_2.ldq_idx connect issue_slots[15].in_uop.bits.rob_idx, _WIRE_2.rob_idx connect issue_slots[15].in_uop.bits.fp_ctrl.vec, _WIRE_2.fp_ctrl.vec connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, _WIRE_2.fp_ctrl.wflags connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, _WIRE_2.fp_ctrl.sqrt connect issue_slots[15].in_uop.bits.fp_ctrl.div, _WIRE_2.fp_ctrl.div connect issue_slots[15].in_uop.bits.fp_ctrl.fma, _WIRE_2.fp_ctrl.fma connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, _WIRE_2.fp_ctrl.fastpipe connect issue_slots[15].in_uop.bits.fp_ctrl.toint, _WIRE_2.fp_ctrl.toint connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, _WIRE_2.fp_ctrl.fromint connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, _WIRE_2.fp_ctrl.typeTagOut connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, _WIRE_2.fp_ctrl.typeTagIn connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, _WIRE_2.fp_ctrl.swap23 connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, _WIRE_2.fp_ctrl.swap12 connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, _WIRE_2.fp_ctrl.ren3 connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, _WIRE_2.fp_ctrl.ren2 connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, _WIRE_2.fp_ctrl.ren1 connect issue_slots[15].in_uop.bits.fp_ctrl.wen, _WIRE_2.fp_ctrl.wen connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, _WIRE_2.fp_ctrl.ldst connect issue_slots[15].in_uop.bits.op2_sel, _WIRE_2.op2_sel connect issue_slots[15].in_uop.bits.op1_sel, _WIRE_2.op1_sel connect issue_slots[15].in_uop.bits.imm_packed, _WIRE_2.imm_packed connect issue_slots[15].in_uop.bits.pimm, _WIRE_2.pimm connect issue_slots[15].in_uop.bits.imm_sel, _WIRE_2.imm_sel connect issue_slots[15].in_uop.bits.imm_rename, _WIRE_2.imm_rename connect issue_slots[15].in_uop.bits.taken, _WIRE_2.taken connect issue_slots[15].in_uop.bits.pc_lob, _WIRE_2.pc_lob connect issue_slots[15].in_uop.bits.edge_inst, _WIRE_2.edge_inst connect issue_slots[15].in_uop.bits.ftq_idx, _WIRE_2.ftq_idx connect issue_slots[15].in_uop.bits.is_mov, _WIRE_2.is_mov connect issue_slots[15].in_uop.bits.is_rocc, _WIRE_2.is_rocc connect issue_slots[15].in_uop.bits.is_sys_pc2epc, _WIRE_2.is_sys_pc2epc connect issue_slots[15].in_uop.bits.is_eret, _WIRE_2.is_eret connect issue_slots[15].in_uop.bits.is_amo, _WIRE_2.is_amo connect issue_slots[15].in_uop.bits.is_sfence, _WIRE_2.is_sfence connect issue_slots[15].in_uop.bits.is_fencei, _WIRE_2.is_fencei connect issue_slots[15].in_uop.bits.is_fence, _WIRE_2.is_fence connect issue_slots[15].in_uop.bits.is_sfb, _WIRE_2.is_sfb connect issue_slots[15].in_uop.bits.br_type, _WIRE_2.br_type connect issue_slots[15].in_uop.bits.br_tag, _WIRE_2.br_tag connect issue_slots[15].in_uop.bits.br_mask, _WIRE_2.br_mask connect issue_slots[15].in_uop.bits.dis_col_sel, _WIRE_2.dis_col_sel connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, _WIRE_2.iw_p3_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, _WIRE_2.iw_p2_bypass_hint connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, _WIRE_2.iw_p1_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, _WIRE_2.iw_p2_speculative_child connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, _WIRE_2.iw_p1_speculative_child connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, _WIRE_2.iw_issued_partial_dgen connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, _WIRE_2.iw_issued_partial_agen connect issue_slots[15].in_uop.bits.iw_issued, _WIRE_2.iw_issued connect issue_slots[15].in_uop.bits.fu_code[0], _WIRE_2.fu_code[0] connect issue_slots[15].in_uop.bits.fu_code[1], _WIRE_2.fu_code[1] connect issue_slots[15].in_uop.bits.fu_code[2], _WIRE_2.fu_code[2] connect issue_slots[15].in_uop.bits.fu_code[3], _WIRE_2.fu_code[3] connect issue_slots[15].in_uop.bits.fu_code[4], _WIRE_2.fu_code[4] connect issue_slots[15].in_uop.bits.fu_code[5], _WIRE_2.fu_code[5] connect issue_slots[15].in_uop.bits.fu_code[6], _WIRE_2.fu_code[6] connect issue_slots[15].in_uop.bits.fu_code[7], _WIRE_2.fu_code[7] connect issue_slots[15].in_uop.bits.fu_code[8], _WIRE_2.fu_code[8] connect issue_slots[15].in_uop.bits.fu_code[9], _WIRE_2.fu_code[9] connect issue_slots[15].in_uop.bits.iq_type[0], _WIRE_2.iq_type[0] connect issue_slots[15].in_uop.bits.iq_type[1], _WIRE_2.iq_type[1] connect issue_slots[15].in_uop.bits.iq_type[2], _WIRE_2.iq_type[2] connect issue_slots[15].in_uop.bits.iq_type[3], _WIRE_2.iq_type[3] connect issue_slots[15].in_uop.bits.debug_pc, _WIRE_2.debug_pc connect issue_slots[15].in_uop.bits.is_rvc, _WIRE_2.is_rvc connect issue_slots[15].in_uop.bits.debug_inst, _WIRE_2.debug_inst connect issue_slots[15].in_uop.bits.inst, _WIRE_2.inst node _issue_slots_15_clear_T = neq(shamts_oh[15], UInt<1>(0h0)) connect issue_slots[15].clear, _issue_slots_15_clear_T reg is_available : UInt<1>[8], clock node _T_307 = eq(issue_slots[8].will_be_valid, UInt<1>(0h0)) node _T_308 = or(_T_307, issue_slots[8].clear) node _T_309 = eq(issue_slots[8].in_uop.valid, UInt<1>(0h0)) node _T_310 = and(_T_308, _T_309) node _T_311 = eq(issue_slots[9].will_be_valid, UInt<1>(0h0)) node _T_312 = or(_T_311, issue_slots[9].clear) node _T_313 = eq(issue_slots[9].in_uop.valid, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(issue_slots[10].will_be_valid, UInt<1>(0h0)) node _T_316 = or(_T_315, issue_slots[10].clear) node _T_317 = eq(issue_slots[10].in_uop.valid, UInt<1>(0h0)) node _T_318 = and(_T_316, _T_317) node _T_319 = eq(issue_slots[11].will_be_valid, UInt<1>(0h0)) node _T_320 = or(_T_319, issue_slots[11].clear) node _T_321 = eq(issue_slots[11].in_uop.valid, UInt<1>(0h0)) node _T_322 = and(_T_320, _T_321) node _T_323 = eq(issue_slots[12].will_be_valid, UInt<1>(0h0)) node _T_324 = or(_T_323, issue_slots[12].clear) node _T_325 = eq(issue_slots[12].in_uop.valid, UInt<1>(0h0)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(issue_slots[13].will_be_valid, UInt<1>(0h0)) node _T_328 = or(_T_327, issue_slots[13].clear) node _T_329 = eq(issue_slots[13].in_uop.valid, UInt<1>(0h0)) node _T_330 = and(_T_328, _T_329) node _T_331 = eq(issue_slots[14].will_be_valid, UInt<1>(0h0)) node _T_332 = or(_T_331, issue_slots[14].clear) node _T_333 = eq(issue_slots[14].in_uop.valid, UInt<1>(0h0)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(issue_slots[15].will_be_valid, UInt<1>(0h0)) node _T_336 = or(_T_335, issue_slots[15].clear) node _T_337 = eq(issue_slots[15].in_uop.valid, UInt<1>(0h0)) node _T_338 = and(_T_336, _T_337) wire _WIRE_18 : UInt<1>[8] connect _WIRE_18[0], _T_310 connect _WIRE_18[1], _T_314 connect _WIRE_18[2], _T_318 connect _WIRE_18[3], _T_322 connect _WIRE_18[4], _T_326 connect _WIRE_18[5], _T_330 connect _WIRE_18[6], _T_334 connect _WIRE_18[7], _T_338 connect is_available, _WIRE_18 node _io_dis_uops_0_ready_T = add(is_available[0], is_available[1]) node _io_dis_uops_0_ready_T_1 = bits(_io_dis_uops_0_ready_T, 1, 0) node _io_dis_uops_0_ready_T_2 = add(is_available[2], is_available[3]) node _io_dis_uops_0_ready_T_3 = bits(_io_dis_uops_0_ready_T_2, 1, 0) node _io_dis_uops_0_ready_T_4 = add(_io_dis_uops_0_ready_T_1, _io_dis_uops_0_ready_T_3) node _io_dis_uops_0_ready_T_5 = bits(_io_dis_uops_0_ready_T_4, 2, 0) node _io_dis_uops_0_ready_T_6 = add(is_available[4], is_available[5]) node _io_dis_uops_0_ready_T_7 = bits(_io_dis_uops_0_ready_T_6, 1, 0) node _io_dis_uops_0_ready_T_8 = add(is_available[6], is_available[7]) node _io_dis_uops_0_ready_T_9 = bits(_io_dis_uops_0_ready_T_8, 1, 0) node _io_dis_uops_0_ready_T_10 = add(_io_dis_uops_0_ready_T_7, _io_dis_uops_0_ready_T_9) node _io_dis_uops_0_ready_T_11 = bits(_io_dis_uops_0_ready_T_10, 2, 0) node _io_dis_uops_0_ready_T_12 = add(_io_dis_uops_0_ready_T_5, _io_dis_uops_0_ready_T_11) node _io_dis_uops_0_ready_T_13 = bits(_io_dis_uops_0_ready_T_12, 3, 0) node _io_dis_uops_0_ready_T_14 = and(io.dis_uops[0].ready, io.dis_uops[0].valid) node _io_dis_uops_0_ready_T_15 = and(io.dis_uops[1].ready, io.dis_uops[1].valid) node _io_dis_uops_0_ready_T_16 = and(io.dis_uops[2].ready, io.dis_uops[2].valid) node _io_dis_uops_0_ready_T_17 = add(_io_dis_uops_0_ready_T_15, _io_dis_uops_0_ready_T_16) node _io_dis_uops_0_ready_T_18 = bits(_io_dis_uops_0_ready_T_17, 1, 0) node _io_dis_uops_0_ready_T_19 = add(_io_dis_uops_0_ready_T_14, _io_dis_uops_0_ready_T_18) node _io_dis_uops_0_ready_T_20 = bits(_io_dis_uops_0_ready_T_19, 1, 0) node _io_dis_uops_0_ready_T_21 = add(UInt<3>(0h0), _io_dis_uops_0_ready_T_20) node _io_dis_uops_0_ready_T_22 = tail(_io_dis_uops_0_ready_T_21, 1) node _io_dis_uops_0_ready_T_23 = gt(_io_dis_uops_0_ready_T_13, _io_dis_uops_0_ready_T_22) reg io_dis_uops_0_ready_REG : UInt<1>, clock connect io_dis_uops_0_ready_REG, _io_dis_uops_0_ready_T_23 connect io.dis_uops[0].ready, io_dis_uops_0_ready_REG node _T_339 = eq(io.dis_uops[0].ready, UInt<1>(0h0)) node _T_340 = shr(shamts_oh[16], 0) node _T_341 = neq(_T_340, UInt<1>(0h0)) node _T_342 = or(_T_339, _T_341) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:214 assert (!io.dis_uops(w).ready || (shamts_oh(w+numIssueSlots) >> w) =/= 0.U)\n") : printf_1 assert(clock, _T_342, UInt<1>(0h1), "") : assert_1 node _io_dis_uops_1_ready_T = add(is_available[0], is_available[1]) node _io_dis_uops_1_ready_T_1 = bits(_io_dis_uops_1_ready_T, 1, 0) node _io_dis_uops_1_ready_T_2 = add(is_available[2], is_available[3]) node _io_dis_uops_1_ready_T_3 = bits(_io_dis_uops_1_ready_T_2, 1, 0) node _io_dis_uops_1_ready_T_4 = add(_io_dis_uops_1_ready_T_1, _io_dis_uops_1_ready_T_3) node _io_dis_uops_1_ready_T_5 = bits(_io_dis_uops_1_ready_T_4, 2, 0) node _io_dis_uops_1_ready_T_6 = add(is_available[4], is_available[5]) node _io_dis_uops_1_ready_T_7 = bits(_io_dis_uops_1_ready_T_6, 1, 0) node _io_dis_uops_1_ready_T_8 = add(is_available[6], is_available[7]) node _io_dis_uops_1_ready_T_9 = bits(_io_dis_uops_1_ready_T_8, 1, 0) node _io_dis_uops_1_ready_T_10 = add(_io_dis_uops_1_ready_T_7, _io_dis_uops_1_ready_T_9) node _io_dis_uops_1_ready_T_11 = bits(_io_dis_uops_1_ready_T_10, 2, 0) node _io_dis_uops_1_ready_T_12 = add(_io_dis_uops_1_ready_T_5, _io_dis_uops_1_ready_T_11) node _io_dis_uops_1_ready_T_13 = bits(_io_dis_uops_1_ready_T_12, 3, 0) node _io_dis_uops_1_ready_T_14 = and(io.dis_uops[0].ready, io.dis_uops[0].valid) node _io_dis_uops_1_ready_T_15 = and(io.dis_uops[1].ready, io.dis_uops[1].valid) node _io_dis_uops_1_ready_T_16 = and(io.dis_uops[2].ready, io.dis_uops[2].valid) node _io_dis_uops_1_ready_T_17 = add(_io_dis_uops_1_ready_T_15, _io_dis_uops_1_ready_T_16) node _io_dis_uops_1_ready_T_18 = bits(_io_dis_uops_1_ready_T_17, 1, 0) node _io_dis_uops_1_ready_T_19 = add(_io_dis_uops_1_ready_T_14, _io_dis_uops_1_ready_T_18) node _io_dis_uops_1_ready_T_20 = bits(_io_dis_uops_1_ready_T_19, 1, 0) node _io_dis_uops_1_ready_T_21 = add(UInt<3>(0h1), _io_dis_uops_1_ready_T_20) node _io_dis_uops_1_ready_T_22 = tail(_io_dis_uops_1_ready_T_21, 1) node _io_dis_uops_1_ready_T_23 = gt(_io_dis_uops_1_ready_T_13, _io_dis_uops_1_ready_T_22) reg io_dis_uops_1_ready_REG : UInt<1>, clock connect io_dis_uops_1_ready_REG, _io_dis_uops_1_ready_T_23 connect io.dis_uops[1].ready, io_dis_uops_1_ready_REG node _T_346 = eq(io.dis_uops[1].ready, UInt<1>(0h0)) node _T_347 = shr(shamts_oh[17], 1) node _T_348 = neq(_T_347, UInt<1>(0h0)) node _T_349 = or(_T_346, _T_348) node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(_T_349, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:214 assert (!io.dis_uops(w).ready || (shamts_oh(w+numIssueSlots) >> w) =/= 0.U)\n") : printf_2 assert(clock, _T_349, UInt<1>(0h1), "") : assert_2 node _io_dis_uops_2_ready_T = add(is_available[0], is_available[1]) node _io_dis_uops_2_ready_T_1 = bits(_io_dis_uops_2_ready_T, 1, 0) node _io_dis_uops_2_ready_T_2 = add(is_available[2], is_available[3]) node _io_dis_uops_2_ready_T_3 = bits(_io_dis_uops_2_ready_T_2, 1, 0) node _io_dis_uops_2_ready_T_4 = add(_io_dis_uops_2_ready_T_1, _io_dis_uops_2_ready_T_3) node _io_dis_uops_2_ready_T_5 = bits(_io_dis_uops_2_ready_T_4, 2, 0) node _io_dis_uops_2_ready_T_6 = add(is_available[4], is_available[5]) node _io_dis_uops_2_ready_T_7 = bits(_io_dis_uops_2_ready_T_6, 1, 0) node _io_dis_uops_2_ready_T_8 = add(is_available[6], is_available[7]) node _io_dis_uops_2_ready_T_9 = bits(_io_dis_uops_2_ready_T_8, 1, 0) node _io_dis_uops_2_ready_T_10 = add(_io_dis_uops_2_ready_T_7, _io_dis_uops_2_ready_T_9) node _io_dis_uops_2_ready_T_11 = bits(_io_dis_uops_2_ready_T_10, 2, 0) node _io_dis_uops_2_ready_T_12 = add(_io_dis_uops_2_ready_T_5, _io_dis_uops_2_ready_T_11) node _io_dis_uops_2_ready_T_13 = bits(_io_dis_uops_2_ready_T_12, 3, 0) node _io_dis_uops_2_ready_T_14 = and(io.dis_uops[0].ready, io.dis_uops[0].valid) node _io_dis_uops_2_ready_T_15 = and(io.dis_uops[1].ready, io.dis_uops[1].valid) node _io_dis_uops_2_ready_T_16 = and(io.dis_uops[2].ready, io.dis_uops[2].valid) node _io_dis_uops_2_ready_T_17 = add(_io_dis_uops_2_ready_T_15, _io_dis_uops_2_ready_T_16) node _io_dis_uops_2_ready_T_18 = bits(_io_dis_uops_2_ready_T_17, 1, 0) node _io_dis_uops_2_ready_T_19 = add(_io_dis_uops_2_ready_T_14, _io_dis_uops_2_ready_T_18) node _io_dis_uops_2_ready_T_20 = bits(_io_dis_uops_2_ready_T_19, 1, 0) node _io_dis_uops_2_ready_T_21 = add(UInt<3>(0h2), _io_dis_uops_2_ready_T_20) node _io_dis_uops_2_ready_T_22 = tail(_io_dis_uops_2_ready_T_21, 1) node _io_dis_uops_2_ready_T_23 = gt(_io_dis_uops_2_ready_T_13, _io_dis_uops_2_ready_T_22) reg io_dis_uops_2_ready_REG : UInt<1>, clock connect io_dis_uops_2_ready_REG, _io_dis_uops_2_ready_T_23 connect io.dis_uops[2].ready, io_dis_uops_2_ready_REG node _T_353 = eq(io.dis_uops[2].ready, UInt<1>(0h0)) node _T_354 = shr(shamts_oh[18], 2) node _T_355 = neq(_T_354, UInt<1>(0h0)) node _T_356 = or(_T_353, _T_355) node _T_357 = asUInt(reset) node _T_358 = eq(_T_357, UInt<1>(0h0)) when _T_358 : node _T_359 = eq(_T_356, UInt<1>(0h0)) when _T_359 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:214 assert (!io.dis_uops(w).ready || (shamts_oh(w+numIssueSlots) >> w) =/= 0.U)\n") : printf_3 assert(clock, _T_356, UInt<1>(0h1), "") : assert_3 wire iss_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[1] connect iss_uops[0].valid, UInt<1>(0h0) invalidate iss_uops[0].bits.debug_tsrc invalidate iss_uops[0].bits.debug_fsrc invalidate iss_uops[0].bits.bp_xcpt_if invalidate iss_uops[0].bits.bp_debug_if invalidate iss_uops[0].bits.xcpt_ma_if invalidate iss_uops[0].bits.xcpt_ae_if invalidate iss_uops[0].bits.xcpt_pf_if invalidate iss_uops[0].bits.fp_typ invalidate iss_uops[0].bits.fp_rm invalidate iss_uops[0].bits.fp_val invalidate iss_uops[0].bits.fcn_op invalidate iss_uops[0].bits.fcn_dw invalidate iss_uops[0].bits.frs3_en invalidate iss_uops[0].bits.lrs2_rtype invalidate iss_uops[0].bits.lrs1_rtype invalidate iss_uops[0].bits.dst_rtype invalidate iss_uops[0].bits.lrs3 invalidate iss_uops[0].bits.lrs2 invalidate iss_uops[0].bits.lrs1 invalidate iss_uops[0].bits.ldst invalidate iss_uops[0].bits.ldst_is_rs1 invalidate iss_uops[0].bits.csr_cmd invalidate iss_uops[0].bits.flush_on_commit invalidate iss_uops[0].bits.is_unique invalidate iss_uops[0].bits.uses_stq invalidate iss_uops[0].bits.uses_ldq invalidate iss_uops[0].bits.mem_signed invalidate iss_uops[0].bits.mem_size invalidate iss_uops[0].bits.mem_cmd invalidate iss_uops[0].bits.exc_cause invalidate iss_uops[0].bits.exception invalidate iss_uops[0].bits.stale_pdst invalidate iss_uops[0].bits.ppred_busy invalidate iss_uops[0].bits.prs3_busy invalidate iss_uops[0].bits.prs2_busy invalidate iss_uops[0].bits.prs1_busy invalidate iss_uops[0].bits.ppred invalidate iss_uops[0].bits.prs3 invalidate iss_uops[0].bits.prs2 invalidate iss_uops[0].bits.prs1 invalidate iss_uops[0].bits.pdst invalidate iss_uops[0].bits.rxq_idx invalidate iss_uops[0].bits.stq_idx invalidate iss_uops[0].bits.ldq_idx invalidate iss_uops[0].bits.rob_idx invalidate iss_uops[0].bits.fp_ctrl.vec invalidate iss_uops[0].bits.fp_ctrl.wflags invalidate iss_uops[0].bits.fp_ctrl.sqrt invalidate iss_uops[0].bits.fp_ctrl.div invalidate iss_uops[0].bits.fp_ctrl.fma invalidate iss_uops[0].bits.fp_ctrl.fastpipe invalidate iss_uops[0].bits.fp_ctrl.toint invalidate iss_uops[0].bits.fp_ctrl.fromint invalidate iss_uops[0].bits.fp_ctrl.typeTagOut invalidate iss_uops[0].bits.fp_ctrl.typeTagIn invalidate iss_uops[0].bits.fp_ctrl.swap23 invalidate iss_uops[0].bits.fp_ctrl.swap12 invalidate iss_uops[0].bits.fp_ctrl.ren3 invalidate iss_uops[0].bits.fp_ctrl.ren2 invalidate iss_uops[0].bits.fp_ctrl.ren1 invalidate iss_uops[0].bits.fp_ctrl.wen invalidate iss_uops[0].bits.fp_ctrl.ldst invalidate iss_uops[0].bits.op2_sel invalidate iss_uops[0].bits.op1_sel invalidate iss_uops[0].bits.imm_packed invalidate iss_uops[0].bits.pimm invalidate iss_uops[0].bits.imm_sel invalidate iss_uops[0].bits.imm_rename invalidate iss_uops[0].bits.taken invalidate iss_uops[0].bits.pc_lob invalidate iss_uops[0].bits.edge_inst invalidate iss_uops[0].bits.ftq_idx invalidate iss_uops[0].bits.is_mov invalidate iss_uops[0].bits.is_rocc invalidate iss_uops[0].bits.is_sys_pc2epc invalidate iss_uops[0].bits.is_eret invalidate iss_uops[0].bits.is_amo invalidate iss_uops[0].bits.is_sfence invalidate iss_uops[0].bits.is_fencei invalidate iss_uops[0].bits.is_fence invalidate iss_uops[0].bits.is_sfb invalidate iss_uops[0].bits.br_type invalidate iss_uops[0].bits.br_tag invalidate iss_uops[0].bits.br_mask invalidate iss_uops[0].bits.dis_col_sel invalidate iss_uops[0].bits.iw_p3_bypass_hint invalidate iss_uops[0].bits.iw_p2_bypass_hint invalidate iss_uops[0].bits.iw_p1_bypass_hint invalidate iss_uops[0].bits.iw_p2_speculative_child invalidate iss_uops[0].bits.iw_p1_speculative_child invalidate iss_uops[0].bits.iw_issued_partial_dgen invalidate iss_uops[0].bits.iw_issued_partial_agen invalidate iss_uops[0].bits.iw_issued invalidate iss_uops[0].bits.fu_code[0] invalidate iss_uops[0].bits.fu_code[1] invalidate iss_uops[0].bits.fu_code[2] invalidate iss_uops[0].bits.fu_code[3] invalidate iss_uops[0].bits.fu_code[4] invalidate iss_uops[0].bits.fu_code[5] invalidate iss_uops[0].bits.fu_code[6] invalidate iss_uops[0].bits.fu_code[7] invalidate iss_uops[0].bits.fu_code[8] invalidate iss_uops[0].bits.fu_code[9] invalidate iss_uops[0].bits.iq_type[0] invalidate iss_uops[0].bits.iq_type[1] invalidate iss_uops[0].bits.iq_type[2] invalidate iss_uops[0].bits.iq_type[3] invalidate iss_uops[0].bits.debug_pc invalidate iss_uops[0].bits.is_rvc invalidate iss_uops[0].bits.debug_inst invalidate iss_uops[0].bits.inst connect issue_slots[0].grant, UInt<1>(0h0) node _fu_code_match_T = and(issue_slots[0].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_1 = and(issue_slots[0].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_2 = and(issue_slots[0].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_3 = and(issue_slots[0].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_4 = and(issue_slots[0].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_5 = and(issue_slots[0].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_6 = and(issue_slots[0].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_7 = and(issue_slots[0].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_8 = and(issue_slots[0].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_9 = and(issue_slots[0].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_10 = or(_fu_code_match_T, _fu_code_match_T_1) node _fu_code_match_T_11 = or(_fu_code_match_T_10, _fu_code_match_T_2) node _fu_code_match_T_12 = or(_fu_code_match_T_11, _fu_code_match_T_3) node _fu_code_match_T_13 = or(_fu_code_match_T_12, _fu_code_match_T_4) node _fu_code_match_T_14 = or(_fu_code_match_T_13, _fu_code_match_T_5) node _fu_code_match_T_15 = or(_fu_code_match_T_14, _fu_code_match_T_6) node _fu_code_match_T_16 = or(_fu_code_match_T_15, _fu_code_match_T_7) node _fu_code_match_T_17 = or(_fu_code_match_T_16, _fu_code_match_T_8) node fu_code_match = or(_fu_code_match_T_17, _fu_code_match_T_9) node can_allocate = and(fu_code_match, UInt<1>(0h1)) node _T_360 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = and(issue_slots[0].request, _T_360) node _T_362 = and(_T_361, can_allocate) node _T_363 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = and(_T_362, _T_363) when _T_364 : connect issue_slots[0].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[0].iss_uop node _T_365 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = and(issue_slots[0].request, _T_365) node _T_367 = and(_T_366, can_allocate) node _T_368 = or(_T_367, UInt<1>(0h0)) node _T_369 = and(issue_slots[0].request, can_allocate) node _T_370 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_371 = and(_T_369, _T_370) node _T_372 = or(_T_371, UInt<1>(0h0)) connect issue_slots[1].grant, UInt<1>(0h0) node _fu_code_match_T_18 = and(issue_slots[1].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_19 = and(issue_slots[1].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_20 = and(issue_slots[1].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_21 = and(issue_slots[1].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_22 = and(issue_slots[1].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_23 = and(issue_slots[1].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_24 = and(issue_slots[1].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_25 = and(issue_slots[1].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_26 = and(issue_slots[1].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_27 = and(issue_slots[1].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_28 = or(_fu_code_match_T_18, _fu_code_match_T_19) node _fu_code_match_T_29 = or(_fu_code_match_T_28, _fu_code_match_T_20) node _fu_code_match_T_30 = or(_fu_code_match_T_29, _fu_code_match_T_21) node _fu_code_match_T_31 = or(_fu_code_match_T_30, _fu_code_match_T_22) node _fu_code_match_T_32 = or(_fu_code_match_T_31, _fu_code_match_T_23) node _fu_code_match_T_33 = or(_fu_code_match_T_32, _fu_code_match_T_24) node _fu_code_match_T_34 = or(_fu_code_match_T_33, _fu_code_match_T_25) node _fu_code_match_T_35 = or(_fu_code_match_T_34, _fu_code_match_T_26) node fu_code_match_1 = or(_fu_code_match_T_35, _fu_code_match_T_27) node can_allocate_1 = and(fu_code_match_1, UInt<1>(0h1)) node _T_373 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_374 = and(issue_slots[1].request, _T_373) node _T_375 = and(_T_374, can_allocate_1) node _T_376 = eq(_T_368, UInt<1>(0h0)) node _T_377 = and(_T_375, _T_376) when _T_377 : connect issue_slots[1].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[1].iss_uop node _T_378 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_379 = and(issue_slots[1].request, _T_378) node _T_380 = and(_T_379, can_allocate_1) node _T_381 = or(_T_380, _T_368) node _T_382 = and(issue_slots[1].request, can_allocate_1) node _T_383 = eq(_T_368, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) node _T_385 = or(_T_384, UInt<1>(0h0)) connect issue_slots[2].grant, UInt<1>(0h0) node _fu_code_match_T_36 = and(issue_slots[2].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_37 = and(issue_slots[2].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_38 = and(issue_slots[2].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_39 = and(issue_slots[2].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_40 = and(issue_slots[2].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_41 = and(issue_slots[2].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_42 = and(issue_slots[2].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_43 = and(issue_slots[2].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_44 = and(issue_slots[2].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_45 = and(issue_slots[2].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_46 = or(_fu_code_match_T_36, _fu_code_match_T_37) node _fu_code_match_T_47 = or(_fu_code_match_T_46, _fu_code_match_T_38) node _fu_code_match_T_48 = or(_fu_code_match_T_47, _fu_code_match_T_39) node _fu_code_match_T_49 = or(_fu_code_match_T_48, _fu_code_match_T_40) node _fu_code_match_T_50 = or(_fu_code_match_T_49, _fu_code_match_T_41) node _fu_code_match_T_51 = or(_fu_code_match_T_50, _fu_code_match_T_42) node _fu_code_match_T_52 = or(_fu_code_match_T_51, _fu_code_match_T_43) node _fu_code_match_T_53 = or(_fu_code_match_T_52, _fu_code_match_T_44) node fu_code_match_2 = or(_fu_code_match_T_53, _fu_code_match_T_45) node can_allocate_2 = and(fu_code_match_2, UInt<1>(0h1)) node _T_386 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_387 = and(issue_slots[2].request, _T_386) node _T_388 = and(_T_387, can_allocate_2) node _T_389 = eq(_T_381, UInt<1>(0h0)) node _T_390 = and(_T_388, _T_389) when _T_390 : connect issue_slots[2].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[2].iss_uop node _T_391 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_392 = and(issue_slots[2].request, _T_391) node _T_393 = and(_T_392, can_allocate_2) node _T_394 = or(_T_393, _T_381) node _T_395 = and(issue_slots[2].request, can_allocate_2) node _T_396 = eq(_T_381, UInt<1>(0h0)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(_T_397, UInt<1>(0h0)) connect issue_slots[3].grant, UInt<1>(0h0) node _fu_code_match_T_54 = and(issue_slots[3].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_55 = and(issue_slots[3].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_56 = and(issue_slots[3].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_57 = and(issue_slots[3].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_58 = and(issue_slots[3].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_59 = and(issue_slots[3].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_60 = and(issue_slots[3].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_61 = and(issue_slots[3].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_62 = and(issue_slots[3].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_63 = and(issue_slots[3].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_64 = or(_fu_code_match_T_54, _fu_code_match_T_55) node _fu_code_match_T_65 = or(_fu_code_match_T_64, _fu_code_match_T_56) node _fu_code_match_T_66 = or(_fu_code_match_T_65, _fu_code_match_T_57) node _fu_code_match_T_67 = or(_fu_code_match_T_66, _fu_code_match_T_58) node _fu_code_match_T_68 = or(_fu_code_match_T_67, _fu_code_match_T_59) node _fu_code_match_T_69 = or(_fu_code_match_T_68, _fu_code_match_T_60) node _fu_code_match_T_70 = or(_fu_code_match_T_69, _fu_code_match_T_61) node _fu_code_match_T_71 = or(_fu_code_match_T_70, _fu_code_match_T_62) node fu_code_match_3 = or(_fu_code_match_T_71, _fu_code_match_T_63) node can_allocate_3 = and(fu_code_match_3, UInt<1>(0h1)) node _T_399 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_400 = and(issue_slots[3].request, _T_399) node _T_401 = and(_T_400, can_allocate_3) node _T_402 = eq(_T_394, UInt<1>(0h0)) node _T_403 = and(_T_401, _T_402) when _T_403 : connect issue_slots[3].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[3].iss_uop node _T_404 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_405 = and(issue_slots[3].request, _T_404) node _T_406 = and(_T_405, can_allocate_3) node _T_407 = or(_T_406, _T_394) node _T_408 = and(issue_slots[3].request, can_allocate_3) node _T_409 = eq(_T_394, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = or(_T_410, UInt<1>(0h0)) connect issue_slots[4].grant, UInt<1>(0h0) node _fu_code_match_T_72 = and(issue_slots[4].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_73 = and(issue_slots[4].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_74 = and(issue_slots[4].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_75 = and(issue_slots[4].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_76 = and(issue_slots[4].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_77 = and(issue_slots[4].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_78 = and(issue_slots[4].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_79 = and(issue_slots[4].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_80 = and(issue_slots[4].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_81 = and(issue_slots[4].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_82 = or(_fu_code_match_T_72, _fu_code_match_T_73) node _fu_code_match_T_83 = or(_fu_code_match_T_82, _fu_code_match_T_74) node _fu_code_match_T_84 = or(_fu_code_match_T_83, _fu_code_match_T_75) node _fu_code_match_T_85 = or(_fu_code_match_T_84, _fu_code_match_T_76) node _fu_code_match_T_86 = or(_fu_code_match_T_85, _fu_code_match_T_77) node _fu_code_match_T_87 = or(_fu_code_match_T_86, _fu_code_match_T_78) node _fu_code_match_T_88 = or(_fu_code_match_T_87, _fu_code_match_T_79) node _fu_code_match_T_89 = or(_fu_code_match_T_88, _fu_code_match_T_80) node fu_code_match_4 = or(_fu_code_match_T_89, _fu_code_match_T_81) node can_allocate_4 = and(fu_code_match_4, UInt<1>(0h1)) node _T_412 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_413 = and(issue_slots[4].request, _T_412) node _T_414 = and(_T_413, can_allocate_4) node _T_415 = eq(_T_407, UInt<1>(0h0)) node _T_416 = and(_T_414, _T_415) when _T_416 : connect issue_slots[4].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[4].iss_uop node _T_417 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_418 = and(issue_slots[4].request, _T_417) node _T_419 = and(_T_418, can_allocate_4) node _T_420 = or(_T_419, _T_407) node _T_421 = and(issue_slots[4].request, can_allocate_4) node _T_422 = eq(_T_407, UInt<1>(0h0)) node _T_423 = and(_T_421, _T_422) node _T_424 = or(_T_423, UInt<1>(0h0)) connect issue_slots[5].grant, UInt<1>(0h0) node _fu_code_match_T_90 = and(issue_slots[5].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_91 = and(issue_slots[5].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_92 = and(issue_slots[5].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_93 = and(issue_slots[5].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_94 = and(issue_slots[5].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_95 = and(issue_slots[5].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_96 = and(issue_slots[5].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_97 = and(issue_slots[5].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_98 = and(issue_slots[5].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_99 = and(issue_slots[5].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_100 = or(_fu_code_match_T_90, _fu_code_match_T_91) node _fu_code_match_T_101 = or(_fu_code_match_T_100, _fu_code_match_T_92) node _fu_code_match_T_102 = or(_fu_code_match_T_101, _fu_code_match_T_93) node _fu_code_match_T_103 = or(_fu_code_match_T_102, _fu_code_match_T_94) node _fu_code_match_T_104 = or(_fu_code_match_T_103, _fu_code_match_T_95) node _fu_code_match_T_105 = or(_fu_code_match_T_104, _fu_code_match_T_96) node _fu_code_match_T_106 = or(_fu_code_match_T_105, _fu_code_match_T_97) node _fu_code_match_T_107 = or(_fu_code_match_T_106, _fu_code_match_T_98) node fu_code_match_5 = or(_fu_code_match_T_107, _fu_code_match_T_99) node can_allocate_5 = and(fu_code_match_5, UInt<1>(0h1)) node _T_425 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_426 = and(issue_slots[5].request, _T_425) node _T_427 = and(_T_426, can_allocate_5) node _T_428 = eq(_T_420, UInt<1>(0h0)) node _T_429 = and(_T_427, _T_428) when _T_429 : connect issue_slots[5].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[5].iss_uop node _T_430 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_431 = and(issue_slots[5].request, _T_430) node _T_432 = and(_T_431, can_allocate_5) node _T_433 = or(_T_432, _T_420) node _T_434 = and(issue_slots[5].request, can_allocate_5) node _T_435 = eq(_T_420, UInt<1>(0h0)) node _T_436 = and(_T_434, _T_435) node _T_437 = or(_T_436, UInt<1>(0h0)) connect issue_slots[6].grant, UInt<1>(0h0) node _fu_code_match_T_108 = and(issue_slots[6].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_109 = and(issue_slots[6].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_110 = and(issue_slots[6].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_111 = and(issue_slots[6].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_112 = and(issue_slots[6].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_113 = and(issue_slots[6].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_114 = and(issue_slots[6].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_115 = and(issue_slots[6].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_116 = and(issue_slots[6].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_117 = and(issue_slots[6].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_118 = or(_fu_code_match_T_108, _fu_code_match_T_109) node _fu_code_match_T_119 = or(_fu_code_match_T_118, _fu_code_match_T_110) node _fu_code_match_T_120 = or(_fu_code_match_T_119, _fu_code_match_T_111) node _fu_code_match_T_121 = or(_fu_code_match_T_120, _fu_code_match_T_112) node _fu_code_match_T_122 = or(_fu_code_match_T_121, _fu_code_match_T_113) node _fu_code_match_T_123 = or(_fu_code_match_T_122, _fu_code_match_T_114) node _fu_code_match_T_124 = or(_fu_code_match_T_123, _fu_code_match_T_115) node _fu_code_match_T_125 = or(_fu_code_match_T_124, _fu_code_match_T_116) node fu_code_match_6 = or(_fu_code_match_T_125, _fu_code_match_T_117) node can_allocate_6 = and(fu_code_match_6, UInt<1>(0h1)) node _T_438 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_439 = and(issue_slots[6].request, _T_438) node _T_440 = and(_T_439, can_allocate_6) node _T_441 = eq(_T_433, UInt<1>(0h0)) node _T_442 = and(_T_440, _T_441) when _T_442 : connect issue_slots[6].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[6].iss_uop node _T_443 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_444 = and(issue_slots[6].request, _T_443) node _T_445 = and(_T_444, can_allocate_6) node _T_446 = or(_T_445, _T_433) node _T_447 = and(issue_slots[6].request, can_allocate_6) node _T_448 = eq(_T_433, UInt<1>(0h0)) node _T_449 = and(_T_447, _T_448) node _T_450 = or(_T_449, UInt<1>(0h0)) connect issue_slots[7].grant, UInt<1>(0h0) node _fu_code_match_T_126 = and(issue_slots[7].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_127 = and(issue_slots[7].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_128 = and(issue_slots[7].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_129 = and(issue_slots[7].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_130 = and(issue_slots[7].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_131 = and(issue_slots[7].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_132 = and(issue_slots[7].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_133 = and(issue_slots[7].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_134 = and(issue_slots[7].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_135 = and(issue_slots[7].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_136 = or(_fu_code_match_T_126, _fu_code_match_T_127) node _fu_code_match_T_137 = or(_fu_code_match_T_136, _fu_code_match_T_128) node _fu_code_match_T_138 = or(_fu_code_match_T_137, _fu_code_match_T_129) node _fu_code_match_T_139 = or(_fu_code_match_T_138, _fu_code_match_T_130) node _fu_code_match_T_140 = or(_fu_code_match_T_139, _fu_code_match_T_131) node _fu_code_match_T_141 = or(_fu_code_match_T_140, _fu_code_match_T_132) node _fu_code_match_T_142 = or(_fu_code_match_T_141, _fu_code_match_T_133) node _fu_code_match_T_143 = or(_fu_code_match_T_142, _fu_code_match_T_134) node fu_code_match_7 = or(_fu_code_match_T_143, _fu_code_match_T_135) node can_allocate_7 = and(fu_code_match_7, UInt<1>(0h1)) node _T_451 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_452 = and(issue_slots[7].request, _T_451) node _T_453 = and(_T_452, can_allocate_7) node _T_454 = eq(_T_446, UInt<1>(0h0)) node _T_455 = and(_T_453, _T_454) when _T_455 : connect issue_slots[7].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[7].iss_uop node _T_456 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_457 = and(issue_slots[7].request, _T_456) node _T_458 = and(_T_457, can_allocate_7) node _T_459 = or(_T_458, _T_446) node _T_460 = and(issue_slots[7].request, can_allocate_7) node _T_461 = eq(_T_446, UInt<1>(0h0)) node _T_462 = and(_T_460, _T_461) node _T_463 = or(_T_462, UInt<1>(0h0)) connect issue_slots[8].grant, UInt<1>(0h0) node _fu_code_match_T_144 = and(issue_slots[8].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_145 = and(issue_slots[8].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_146 = and(issue_slots[8].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_147 = and(issue_slots[8].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_148 = and(issue_slots[8].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_149 = and(issue_slots[8].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_150 = and(issue_slots[8].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_151 = and(issue_slots[8].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_152 = and(issue_slots[8].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_153 = and(issue_slots[8].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_154 = or(_fu_code_match_T_144, _fu_code_match_T_145) node _fu_code_match_T_155 = or(_fu_code_match_T_154, _fu_code_match_T_146) node _fu_code_match_T_156 = or(_fu_code_match_T_155, _fu_code_match_T_147) node _fu_code_match_T_157 = or(_fu_code_match_T_156, _fu_code_match_T_148) node _fu_code_match_T_158 = or(_fu_code_match_T_157, _fu_code_match_T_149) node _fu_code_match_T_159 = or(_fu_code_match_T_158, _fu_code_match_T_150) node _fu_code_match_T_160 = or(_fu_code_match_T_159, _fu_code_match_T_151) node _fu_code_match_T_161 = or(_fu_code_match_T_160, _fu_code_match_T_152) node fu_code_match_8 = or(_fu_code_match_T_161, _fu_code_match_T_153) node can_allocate_8 = and(fu_code_match_8, UInt<1>(0h1)) node _T_464 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = and(issue_slots[8].request, _T_464) node _T_466 = and(_T_465, can_allocate_8) node _T_467 = eq(_T_459, UInt<1>(0h0)) node _T_468 = and(_T_466, _T_467) when _T_468 : connect issue_slots[8].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[8].iss_uop node _T_469 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = and(issue_slots[8].request, _T_469) node _T_471 = and(_T_470, can_allocate_8) node _T_472 = or(_T_471, _T_459) node _T_473 = and(issue_slots[8].request, can_allocate_8) node _T_474 = eq(_T_459, UInt<1>(0h0)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(_T_475, UInt<1>(0h0)) connect issue_slots[9].grant, UInt<1>(0h0) node _fu_code_match_T_162 = and(issue_slots[9].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_163 = and(issue_slots[9].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_164 = and(issue_slots[9].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_165 = and(issue_slots[9].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_166 = and(issue_slots[9].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_167 = and(issue_slots[9].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_168 = and(issue_slots[9].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_169 = and(issue_slots[9].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_170 = and(issue_slots[9].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_171 = and(issue_slots[9].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_172 = or(_fu_code_match_T_162, _fu_code_match_T_163) node _fu_code_match_T_173 = or(_fu_code_match_T_172, _fu_code_match_T_164) node _fu_code_match_T_174 = or(_fu_code_match_T_173, _fu_code_match_T_165) node _fu_code_match_T_175 = or(_fu_code_match_T_174, _fu_code_match_T_166) node _fu_code_match_T_176 = or(_fu_code_match_T_175, _fu_code_match_T_167) node _fu_code_match_T_177 = or(_fu_code_match_T_176, _fu_code_match_T_168) node _fu_code_match_T_178 = or(_fu_code_match_T_177, _fu_code_match_T_169) node _fu_code_match_T_179 = or(_fu_code_match_T_178, _fu_code_match_T_170) node fu_code_match_9 = or(_fu_code_match_T_179, _fu_code_match_T_171) node can_allocate_9 = and(fu_code_match_9, UInt<1>(0h1)) node _T_477 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_478 = and(issue_slots[9].request, _T_477) node _T_479 = and(_T_478, can_allocate_9) node _T_480 = eq(_T_472, UInt<1>(0h0)) node _T_481 = and(_T_479, _T_480) when _T_481 : connect issue_slots[9].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[9].iss_uop node _T_482 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_483 = and(issue_slots[9].request, _T_482) node _T_484 = and(_T_483, can_allocate_9) node _T_485 = or(_T_484, _T_472) node _T_486 = and(issue_slots[9].request, can_allocate_9) node _T_487 = eq(_T_472, UInt<1>(0h0)) node _T_488 = and(_T_486, _T_487) node _T_489 = or(_T_488, UInt<1>(0h0)) connect issue_slots[10].grant, UInt<1>(0h0) node _fu_code_match_T_180 = and(issue_slots[10].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_181 = and(issue_slots[10].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_182 = and(issue_slots[10].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_183 = and(issue_slots[10].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_184 = and(issue_slots[10].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_185 = and(issue_slots[10].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_186 = and(issue_slots[10].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_187 = and(issue_slots[10].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_188 = and(issue_slots[10].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_189 = and(issue_slots[10].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_190 = or(_fu_code_match_T_180, _fu_code_match_T_181) node _fu_code_match_T_191 = or(_fu_code_match_T_190, _fu_code_match_T_182) node _fu_code_match_T_192 = or(_fu_code_match_T_191, _fu_code_match_T_183) node _fu_code_match_T_193 = or(_fu_code_match_T_192, _fu_code_match_T_184) node _fu_code_match_T_194 = or(_fu_code_match_T_193, _fu_code_match_T_185) node _fu_code_match_T_195 = or(_fu_code_match_T_194, _fu_code_match_T_186) node _fu_code_match_T_196 = or(_fu_code_match_T_195, _fu_code_match_T_187) node _fu_code_match_T_197 = or(_fu_code_match_T_196, _fu_code_match_T_188) node fu_code_match_10 = or(_fu_code_match_T_197, _fu_code_match_T_189) node can_allocate_10 = and(fu_code_match_10, UInt<1>(0h1)) node _T_490 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_491 = and(issue_slots[10].request, _T_490) node _T_492 = and(_T_491, can_allocate_10) node _T_493 = eq(_T_485, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) when _T_494 : connect issue_slots[10].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[10].iss_uop node _T_495 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_496 = and(issue_slots[10].request, _T_495) node _T_497 = and(_T_496, can_allocate_10) node _T_498 = or(_T_497, _T_485) node _T_499 = and(issue_slots[10].request, can_allocate_10) node _T_500 = eq(_T_485, UInt<1>(0h0)) node _T_501 = and(_T_499, _T_500) node _T_502 = or(_T_501, UInt<1>(0h0)) connect issue_slots[11].grant, UInt<1>(0h0) node _fu_code_match_T_198 = and(issue_slots[11].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_199 = and(issue_slots[11].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_200 = and(issue_slots[11].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_201 = and(issue_slots[11].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_202 = and(issue_slots[11].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_203 = and(issue_slots[11].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_204 = and(issue_slots[11].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_205 = and(issue_slots[11].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_206 = and(issue_slots[11].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_207 = and(issue_slots[11].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_208 = or(_fu_code_match_T_198, _fu_code_match_T_199) node _fu_code_match_T_209 = or(_fu_code_match_T_208, _fu_code_match_T_200) node _fu_code_match_T_210 = or(_fu_code_match_T_209, _fu_code_match_T_201) node _fu_code_match_T_211 = or(_fu_code_match_T_210, _fu_code_match_T_202) node _fu_code_match_T_212 = or(_fu_code_match_T_211, _fu_code_match_T_203) node _fu_code_match_T_213 = or(_fu_code_match_T_212, _fu_code_match_T_204) node _fu_code_match_T_214 = or(_fu_code_match_T_213, _fu_code_match_T_205) node _fu_code_match_T_215 = or(_fu_code_match_T_214, _fu_code_match_T_206) node fu_code_match_11 = or(_fu_code_match_T_215, _fu_code_match_T_207) node can_allocate_11 = and(fu_code_match_11, UInt<1>(0h1)) node _T_503 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_504 = and(issue_slots[11].request, _T_503) node _T_505 = and(_T_504, can_allocate_11) node _T_506 = eq(_T_498, UInt<1>(0h0)) node _T_507 = and(_T_505, _T_506) when _T_507 : connect issue_slots[11].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[11].iss_uop node _T_508 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_509 = and(issue_slots[11].request, _T_508) node _T_510 = and(_T_509, can_allocate_11) node _T_511 = or(_T_510, _T_498) node _T_512 = and(issue_slots[11].request, can_allocate_11) node _T_513 = eq(_T_498, UInt<1>(0h0)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(_T_514, UInt<1>(0h0)) connect issue_slots[12].grant, UInt<1>(0h0) node _fu_code_match_T_216 = and(issue_slots[12].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_217 = and(issue_slots[12].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_218 = and(issue_slots[12].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_219 = and(issue_slots[12].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_220 = and(issue_slots[12].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_221 = and(issue_slots[12].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_222 = and(issue_slots[12].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_223 = and(issue_slots[12].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_224 = and(issue_slots[12].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_225 = and(issue_slots[12].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_226 = or(_fu_code_match_T_216, _fu_code_match_T_217) node _fu_code_match_T_227 = or(_fu_code_match_T_226, _fu_code_match_T_218) node _fu_code_match_T_228 = or(_fu_code_match_T_227, _fu_code_match_T_219) node _fu_code_match_T_229 = or(_fu_code_match_T_228, _fu_code_match_T_220) node _fu_code_match_T_230 = or(_fu_code_match_T_229, _fu_code_match_T_221) node _fu_code_match_T_231 = or(_fu_code_match_T_230, _fu_code_match_T_222) node _fu_code_match_T_232 = or(_fu_code_match_T_231, _fu_code_match_T_223) node _fu_code_match_T_233 = or(_fu_code_match_T_232, _fu_code_match_T_224) node fu_code_match_12 = or(_fu_code_match_T_233, _fu_code_match_T_225) node can_allocate_12 = and(fu_code_match_12, UInt<1>(0h1)) node _T_516 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_517 = and(issue_slots[12].request, _T_516) node _T_518 = and(_T_517, can_allocate_12) node _T_519 = eq(_T_511, UInt<1>(0h0)) node _T_520 = and(_T_518, _T_519) when _T_520 : connect issue_slots[12].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[12].iss_uop node _T_521 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_522 = and(issue_slots[12].request, _T_521) node _T_523 = and(_T_522, can_allocate_12) node _T_524 = or(_T_523, _T_511) node _T_525 = and(issue_slots[12].request, can_allocate_12) node _T_526 = eq(_T_511, UInt<1>(0h0)) node _T_527 = and(_T_525, _T_526) node _T_528 = or(_T_527, UInt<1>(0h0)) connect issue_slots[13].grant, UInt<1>(0h0) node _fu_code_match_T_234 = and(issue_slots[13].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_235 = and(issue_slots[13].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_236 = and(issue_slots[13].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_237 = and(issue_slots[13].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_238 = and(issue_slots[13].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_239 = and(issue_slots[13].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_240 = and(issue_slots[13].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_241 = and(issue_slots[13].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_242 = and(issue_slots[13].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_243 = and(issue_slots[13].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_244 = or(_fu_code_match_T_234, _fu_code_match_T_235) node _fu_code_match_T_245 = or(_fu_code_match_T_244, _fu_code_match_T_236) node _fu_code_match_T_246 = or(_fu_code_match_T_245, _fu_code_match_T_237) node _fu_code_match_T_247 = or(_fu_code_match_T_246, _fu_code_match_T_238) node _fu_code_match_T_248 = or(_fu_code_match_T_247, _fu_code_match_T_239) node _fu_code_match_T_249 = or(_fu_code_match_T_248, _fu_code_match_T_240) node _fu_code_match_T_250 = or(_fu_code_match_T_249, _fu_code_match_T_241) node _fu_code_match_T_251 = or(_fu_code_match_T_250, _fu_code_match_T_242) node fu_code_match_13 = or(_fu_code_match_T_251, _fu_code_match_T_243) node can_allocate_13 = and(fu_code_match_13, UInt<1>(0h1)) node _T_529 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_530 = and(issue_slots[13].request, _T_529) node _T_531 = and(_T_530, can_allocate_13) node _T_532 = eq(_T_524, UInt<1>(0h0)) node _T_533 = and(_T_531, _T_532) when _T_533 : connect issue_slots[13].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[13].iss_uop node _T_534 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_535 = and(issue_slots[13].request, _T_534) node _T_536 = and(_T_535, can_allocate_13) node _T_537 = or(_T_536, _T_524) node _T_538 = and(issue_slots[13].request, can_allocate_13) node _T_539 = eq(_T_524, UInt<1>(0h0)) node _T_540 = and(_T_538, _T_539) node _T_541 = or(_T_540, UInt<1>(0h0)) connect issue_slots[14].grant, UInt<1>(0h0) node _fu_code_match_T_252 = and(issue_slots[14].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_253 = and(issue_slots[14].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_254 = and(issue_slots[14].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_255 = and(issue_slots[14].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_256 = and(issue_slots[14].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_257 = and(issue_slots[14].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_258 = and(issue_slots[14].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_259 = and(issue_slots[14].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_260 = and(issue_slots[14].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_261 = and(issue_slots[14].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_262 = or(_fu_code_match_T_252, _fu_code_match_T_253) node _fu_code_match_T_263 = or(_fu_code_match_T_262, _fu_code_match_T_254) node _fu_code_match_T_264 = or(_fu_code_match_T_263, _fu_code_match_T_255) node _fu_code_match_T_265 = or(_fu_code_match_T_264, _fu_code_match_T_256) node _fu_code_match_T_266 = or(_fu_code_match_T_265, _fu_code_match_T_257) node _fu_code_match_T_267 = or(_fu_code_match_T_266, _fu_code_match_T_258) node _fu_code_match_T_268 = or(_fu_code_match_T_267, _fu_code_match_T_259) node _fu_code_match_T_269 = or(_fu_code_match_T_268, _fu_code_match_T_260) node fu_code_match_14 = or(_fu_code_match_T_269, _fu_code_match_T_261) node can_allocate_14 = and(fu_code_match_14, UInt<1>(0h1)) node _T_542 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_543 = and(issue_slots[14].request, _T_542) node _T_544 = and(_T_543, can_allocate_14) node _T_545 = eq(_T_537, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) when _T_546 : connect issue_slots[14].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[14].iss_uop node _T_547 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_548 = and(issue_slots[14].request, _T_547) node _T_549 = and(_T_548, can_allocate_14) node _T_550 = or(_T_549, _T_537) node _T_551 = and(issue_slots[14].request, can_allocate_14) node _T_552 = eq(_T_537, UInt<1>(0h0)) node _T_553 = and(_T_551, _T_552) node _T_554 = or(_T_553, UInt<1>(0h0)) connect issue_slots[15].grant, UInt<1>(0h0) node _fu_code_match_T_270 = and(issue_slots[15].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_271 = and(issue_slots[15].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_272 = and(issue_slots[15].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_273 = and(issue_slots[15].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_274 = and(issue_slots[15].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_275 = and(issue_slots[15].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_276 = and(issue_slots[15].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_277 = and(issue_slots[15].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_278 = and(issue_slots[15].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_279 = and(issue_slots[15].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_280 = or(_fu_code_match_T_270, _fu_code_match_T_271) node _fu_code_match_T_281 = or(_fu_code_match_T_280, _fu_code_match_T_272) node _fu_code_match_T_282 = or(_fu_code_match_T_281, _fu_code_match_T_273) node _fu_code_match_T_283 = or(_fu_code_match_T_282, _fu_code_match_T_274) node _fu_code_match_T_284 = or(_fu_code_match_T_283, _fu_code_match_T_275) node _fu_code_match_T_285 = or(_fu_code_match_T_284, _fu_code_match_T_276) node _fu_code_match_T_286 = or(_fu_code_match_T_285, _fu_code_match_T_277) node _fu_code_match_T_287 = or(_fu_code_match_T_286, _fu_code_match_T_278) node fu_code_match_15 = or(_fu_code_match_T_287, _fu_code_match_T_279) node can_allocate_15 = and(fu_code_match_15, UInt<1>(0h1)) node _T_555 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_556 = and(issue_slots[15].request, _T_555) node _T_557 = and(_T_556, can_allocate_15) node _T_558 = eq(_T_550, UInt<1>(0h0)) node _T_559 = and(_T_557, _T_558) when _T_559 : connect issue_slots[15].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[15].iss_uop node _T_560 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_561 = and(issue_slots[15].request, _T_560) node _T_562 = and(_T_561, can_allocate_15) node _T_563 = or(_T_562, _T_550) node _T_564 = and(issue_slots[15].request, can_allocate_15) node _T_565 = eq(_T_550, UInt<1>(0h0)) node _T_566 = and(_T_564, _T_565) node _T_567 = or(_T_566, UInt<1>(0h0)) connect io.iss_uops, iss_uops when io.squash_grant : connect io.iss_uops[0].valid, UInt<1>(0h0)
module IssueUnitCollapsing_4( // @[issue-unit-age-ordered.scala:22:7] input clock, // @[issue-unit-age-ordered.scala:22:7] input reset, // @[issue-unit-age-ordered.scala:22:7] output io_dis_uops_0_ready, // @[issue-unit.scala:44:14] input io_dis_uops_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_dis_uops_1_ready, // @[issue-unit.scala:44:14] input io_dis_uops_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_1_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_1_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_1_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_1_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_dis_uops_2_ready, // @[issue-unit.scala:44:14] input io_dis_uops_2_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_2_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_2_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_2_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_2_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_2_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_2_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_2_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_2_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_iss_uops_0_valid, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_inst, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] output [39:0] io_iss_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] output [15:0] io_iss_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_type, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_taken, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_pimm, // @[issue-unit.scala:44:14] output [19:0] io_iss_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_pdst, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs1, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs2, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs3, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ppred, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_exception, // @[issue-unit.scala:44:14] output [63:0] io_iss_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_ldst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_pred_wakeup_port_valid, // @[issue-unit.scala:44:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-unit.scala:44:14] input [2:0] io_child_rebusys, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_eret, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rocc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_taken, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_brupdate_b2_mispredict, // @[issue-unit.scala:44:14] input io_brupdate_b2_taken, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:44:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:44:14] input io_flush_pipeline, // @[issue-unit.scala:44:14] input io_squash_grant, // @[issue-unit.scala:44:14] input [63:0] io_tsc_reg // @[issue-unit.scala:44:14] ); wire issue_slots_15_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_0_0 = io_dis_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_1_0 = io_dis_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_2_0 = io_dis_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_3_0 = io_dis_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_0_0 = io_dis_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_1_0 = io_dis_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_2_0 = io_dis_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_3_0 = io_dis_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_4_0 = io_dis_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_5_0 = io_dis_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_6_0 = io_dis_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_7_0 = io_dis_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_8_0 = io_dis_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_9_0 = io_dis_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_0 = io_dis_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_agen_0 = io_dis_uops_0_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_dis_uops_0_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_iw_p1_speculative_child_0 = io_dis_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_iw_p2_speculative_child_0 = io_dis_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_dis_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_dis_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_dis_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_dis_col_sel_0 = io_dis_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_type_0 = io_dis_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfence_0 = io_dis_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_eret_0 = io_dis_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rocc_0 = io_dis_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_mov_0 = io_dis_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_imm_rename_0 = io_dis_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_imm_sel_0 = io_dis_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_pimm_0 = io_dis_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_op1_sel_0 = io_dis_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_op2_sel_0 = io_dis_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ldst_0 = io_dis_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wen_0 = io_dis_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren1_0 = io_dis_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren2_0 = io_dis_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren3_0 = io_dis_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap12_0 = io_dis_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap23_0 = io_dis_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fromint_0 = io_dis_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_toint_0 = io_dis_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_dis_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fma_0 = io_dis_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_div_0 = io_dis_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_dis_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wflags_0 = io_dis_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_vec_0 = io_dis_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ppred_0 = io_dis_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ppred_busy_0 = io_dis_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_csr_cmd_0 = io_dis_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fcn_dw_0 = io_dis_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_fcn_op_0 = io_dis_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_fp_rm_0 = io_dis_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_typ_0 = io_dis_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_valid_0 = io_dis_uops_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_inst_0 = io_dis_uops_1_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_debug_inst_0 = io_dis_uops_1_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rvc_0 = io_dis_uops_1_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_1_bits_debug_pc_0 = io_dis_uops_1_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_0_0 = io_dis_uops_1_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_1_0 = io_dis_uops_1_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_2_0 = io_dis_uops_1_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_3_0 = io_dis_uops_1_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_0_0 = io_dis_uops_1_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_1_0 = io_dis_uops_1_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_2_0 = io_dis_uops_1_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_3_0 = io_dis_uops_1_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_4_0 = io_dis_uops_1_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_5_0 = io_dis_uops_1_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_6_0 = io_dis_uops_1_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_7_0 = io_dis_uops_1_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_8_0 = io_dis_uops_1_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_9_0 = io_dis_uops_1_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_0 = io_dis_uops_1_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_agen_0 = io_dis_uops_1_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_dis_uops_1_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_iw_p1_speculative_child_0 = io_dis_uops_1_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_iw_p2_speculative_child_0 = io_dis_uops_1_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_dis_uops_1_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_dis_uops_1_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_dis_uops_1_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_dis_col_sel_0 = io_dis_uops_1_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_1_bits_br_mask_0 = io_dis_uops_1_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_tag_0 = io_dis_uops_1_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_type_0 = io_dis_uops_1_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfb_0 = io_dis_uops_1_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fence_0 = io_dis_uops_1_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fencei_0 = io_dis_uops_1_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfence_0 = io_dis_uops_1_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_amo_0 = io_dis_uops_1_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_eret_0 = io_dis_uops_1_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sys_pc2epc_0 = io_dis_uops_1_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rocc_0 = io_dis_uops_1_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_mov_0 = io_dis_uops_1_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ftq_idx_0 = io_dis_uops_1_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_edge_inst_0 = io_dis_uops_1_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_pc_lob_0 = io_dis_uops_1_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_taken_0 = io_dis_uops_1_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_imm_rename_0 = io_dis_uops_1_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_imm_sel_0 = io_dis_uops_1_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_pimm_0 = io_dis_uops_1_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_1_bits_imm_packed_0 = io_dis_uops_1_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_op1_sel_0 = io_dis_uops_1_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_op2_sel_0 = io_dis_uops_1_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ldst_0 = io_dis_uops_1_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wen_0 = io_dis_uops_1_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren1_0 = io_dis_uops_1_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren2_0 = io_dis_uops_1_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren3_0 = io_dis_uops_1_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap12_0 = io_dis_uops_1_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap23_0 = io_dis_uops_1_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fromint_0 = io_dis_uops_1_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_toint_0 = io_dis_uops_1_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_dis_uops_1_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fma_0 = io_dis_uops_1_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_div_0 = io_dis_uops_1_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_dis_uops_1_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wflags_0 = io_dis_uops_1_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_vec_0 = io_dis_uops_1_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_rob_idx_0 = io_dis_uops_1_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ldq_idx_0 = io_dis_uops_1_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_stq_idx_0 = io_dis_uops_1_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_rxq_idx_0 = io_dis_uops_1_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_pdst_0 = io_dis_uops_1_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs1_0 = io_dis_uops_1_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs2_0 = io_dis_uops_1_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs3_0 = io_dis_uops_1_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ppred_0 = io_dis_uops_1_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs1_busy_0 = io_dis_uops_1_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs2_busy_0 = io_dis_uops_1_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs3_busy_0 = io_dis_uops_1_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ppred_busy_0 = io_dis_uops_1_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_stale_pdst_0 = io_dis_uops_1_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_exception_0 = io_dis_uops_1_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_1_bits_exc_cause_0 = io_dis_uops_1_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_mem_cmd_0 = io_dis_uops_1_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_mem_size_0 = io_dis_uops_1_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_mem_signed_0 = io_dis_uops_1_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_ldq_0 = io_dis_uops_1_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_stq_0 = io_dis_uops_1_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_unique_0 = io_dis_uops_1_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_flush_on_commit_0 = io_dis_uops_1_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_csr_cmd_0 = io_dis_uops_1_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ldst_is_rs1_0 = io_dis_uops_1_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_ldst_0 = io_dis_uops_1_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs1_0 = io_dis_uops_1_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs2_0 = io_dis_uops_1_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs3_0 = io_dis_uops_1_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_dst_rtype_0 = io_dis_uops_1_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs1_rtype_0 = io_dis_uops_1_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs2_rtype_0 = io_dis_uops_1_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_frs3_en_0 = io_dis_uops_1_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fcn_dw_0 = io_dis_uops_1_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_fcn_op_0 = io_dis_uops_1_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_val_0 = io_dis_uops_1_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_fp_rm_0 = io_dis_uops_1_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_typ_0 = io_dis_uops_1_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_pf_if_0 = io_dis_uops_1_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ae_if_0 = io_dis_uops_1_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ma_if_0 = io_dis_uops_1_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_debug_if_0 = io_dis_uops_1_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_xcpt_if_0 = io_dis_uops_1_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_fsrc_0 = io_dis_uops_1_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_tsrc_0 = io_dis_uops_1_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_valid_0 = io_dis_uops_2_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_2_bits_inst_0 = io_dis_uops_2_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_2_bits_debug_inst_0 = io_dis_uops_2_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_rvc_0 = io_dis_uops_2_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_2_bits_debug_pc_0 = io_dis_uops_2_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_0_0 = io_dis_uops_2_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_1_0 = io_dis_uops_2_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_2_0 = io_dis_uops_2_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_3_0 = io_dis_uops_2_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_0_0 = io_dis_uops_2_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_1_0 = io_dis_uops_2_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_2_0 = io_dis_uops_2_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_3_0 = io_dis_uops_2_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_4_0 = io_dis_uops_2_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_5_0 = io_dis_uops_2_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_6_0 = io_dis_uops_2_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_7_0 = io_dis_uops_2_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_8_0 = io_dis_uops_2_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_9_0 = io_dis_uops_2_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_0 = io_dis_uops_2_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_partial_agen_0 = io_dis_uops_2_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_partial_dgen_0 = io_dis_uops_2_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_iw_p1_speculative_child_0 = io_dis_uops_2_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_iw_p2_speculative_child_0 = io_dis_uops_2_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p1_bypass_hint_0 = io_dis_uops_2_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p2_bypass_hint_0 = io_dis_uops_2_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p3_bypass_hint_0 = io_dis_uops_2_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_dis_col_sel_0 = io_dis_uops_2_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_2_bits_br_mask_0 = io_dis_uops_2_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_2_bits_br_tag_0 = io_dis_uops_2_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_2_bits_br_type_0 = io_dis_uops_2_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sfb_0 = io_dis_uops_2_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_fence_0 = io_dis_uops_2_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_fencei_0 = io_dis_uops_2_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sfence_0 = io_dis_uops_2_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_amo_0 = io_dis_uops_2_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_eret_0 = io_dis_uops_2_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sys_pc2epc_0 = io_dis_uops_2_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_rocc_0 = io_dis_uops_2_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_mov_0 = io_dis_uops_2_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ftq_idx_0 = io_dis_uops_2_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_edge_inst_0 = io_dis_uops_2_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_pc_lob_0 = io_dis_uops_2_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_taken_0 = io_dis_uops_2_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_imm_rename_0 = io_dis_uops_2_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_imm_sel_0 = io_dis_uops_2_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_pimm_0 = io_dis_uops_2_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_2_bits_imm_packed_0 = io_dis_uops_2_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_op1_sel_0 = io_dis_uops_2_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_op2_sel_0 = io_dis_uops_2_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ldst_0 = io_dis_uops_2_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_wen_0 = io_dis_uops_2_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren1_0 = io_dis_uops_2_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren2_0 = io_dis_uops_2_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren3_0 = io_dis_uops_2_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_swap12_0 = io_dis_uops_2_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_swap23_0 = io_dis_uops_2_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_2_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_2_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fromint_0 = io_dis_uops_2_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_toint_0 = io_dis_uops_2_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fastpipe_0 = io_dis_uops_2_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fma_0 = io_dis_uops_2_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_div_0 = io_dis_uops_2_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_sqrt_0 = io_dis_uops_2_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_wflags_0 = io_dis_uops_2_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_vec_0 = io_dis_uops_2_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_rob_idx_0 = io_dis_uops_2_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ldq_idx_0 = io_dis_uops_2_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_stq_idx_0 = io_dis_uops_2_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_rxq_idx_0 = io_dis_uops_2_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_pdst_0 = io_dis_uops_2_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs1_0 = io_dis_uops_2_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs2_0 = io_dis_uops_2_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs3_0 = io_dis_uops_2_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ppred_0 = io_dis_uops_2_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs1_busy_0 = io_dis_uops_2_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs2_busy_0 = io_dis_uops_2_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs3_busy_0 = io_dis_uops_2_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_ppred_busy_0 = io_dis_uops_2_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_stale_pdst_0 = io_dis_uops_2_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_exception_0 = io_dis_uops_2_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_2_bits_exc_cause_0 = io_dis_uops_2_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_mem_cmd_0 = io_dis_uops_2_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_mem_size_0 = io_dis_uops_2_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_mem_signed_0 = io_dis_uops_2_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_uses_ldq_0 = io_dis_uops_2_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_uses_stq_0 = io_dis_uops_2_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_unique_0 = io_dis_uops_2_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_flush_on_commit_0 = io_dis_uops_2_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_csr_cmd_0 = io_dis_uops_2_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_ldst_is_rs1_0 = io_dis_uops_2_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_ldst_0 = io_dis_uops_2_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs1_0 = io_dis_uops_2_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs2_0 = io_dis_uops_2_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs3_0 = io_dis_uops_2_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_dst_rtype_0 = io_dis_uops_2_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_lrs1_rtype_0 = io_dis_uops_2_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_lrs2_rtype_0 = io_dis_uops_2_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_frs3_en_0 = io_dis_uops_2_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fcn_dw_0 = io_dis_uops_2_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_fcn_op_0 = io_dis_uops_2_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_val_0 = io_dis_uops_2_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_fp_rm_0 = io_dis_uops_2_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_typ_0 = io_dis_uops_2_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_pf_if_0 = io_dis_uops_2_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_ae_if_0 = io_dis_uops_2_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_ma_if_0 = io_dis_uops_2_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_bp_debug_if_0 = io_dis_uops_2_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_bp_xcpt_if_0 = io_dis_uops_2_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_debug_fsrc_0 = io_dis_uops_2_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_debug_tsrc_0 = io_dis_uops_2_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:22:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:22:7] wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:22:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_2 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_3 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_4 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_5 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_6 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_7 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_8 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_9 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_3 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_4 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_3 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_4 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs1_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_2_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_3_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_4_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_2_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_3_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_4_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs1_rebusys_1_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_2_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_3_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_4_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_1_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_2_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_3_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_4_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire issue_slots_0_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_clear = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:199:49] wire iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:241:22] wire _fu_code_match_T_1 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_2 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_3 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_4 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_5 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_6 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_7 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_8 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_9 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_19 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_20 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_21 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_22 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_23 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_24 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_25 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_26 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_27 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_37 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_38 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_39 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_40 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_41 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_42 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_43 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_44 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_45 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_55 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_56 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_57 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_58 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_59 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_60 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_61 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_62 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_63 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_73 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_74 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_75 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_76 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_77 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_78 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_79 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_80 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_81 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_91 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_92 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_93 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_94 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_95 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_96 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_97 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_98 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_99 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_109 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_110 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_111 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_112 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_113 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_114 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_115 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_116 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_117 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_127 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_128 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_129 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_130 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_131 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_132 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_133 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_134 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_135 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_145 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_146 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_147 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_148 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_149 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_150 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_151 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_152 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_153 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_163 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_164 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_165 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_166 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_167 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_168 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_169 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_170 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_171 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_181 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_182 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_183 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_184 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_185 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_186 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_187 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_188 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_189 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_199 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_200 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_201 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_202 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_203 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_204 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_205 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_206 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_207 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_217 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_218 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_219 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_220 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_221 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_222 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_223 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_224 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_225 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_235 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_236 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_237 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_238 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_239 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_240 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_241 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_242 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_243 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_253 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_254 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_255 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_256 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_257 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_258 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_259 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_260 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_261 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_271 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_272 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_273 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_274 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_275 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_276 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_277 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_278 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_279 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] shamts_oh_0 = 3'h0; // @[issue-unit-age-ordered.scala:158:23] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_0 = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire issue_slots_0_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] iss_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:241:22] wire [31:0] iss_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:241:22] wire [39:0] iss_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:241:22] wire [15:0] iss_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:241:22] wire [19:0] iss_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:241:22] wire [63:0] iss_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:241:22] wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_pred_wakeup_port_valid = io_pred_wakeup_port_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_pred_wakeup_port_bits = io_pred_wakeup_port_bits_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_8_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_9_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_10_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_11_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_12_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_13_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_14_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_15_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_iss_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_iss_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_iss_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_iss_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_4 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_4 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_4 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0 = io_wakeup_ports_0_valid_0 & prs1_matches_0; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_2 = io_wakeup_ports_2_valid_0 & prs1_matches_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_3 = io_wakeup_ports_3_valid_0 & prs1_matches_3; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_4 = io_wakeup_ports_4_valid_0 & prs1_matches_4; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0 = io_wakeup_ports_0_valid_0 & prs2_matches_0; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_2 = io_wakeup_ports_2_valid_0 & prs2_matches_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_3 = io_wakeup_ports_3_valid_0 & prs2_matches_3; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_4 = io_wakeup_ports_4_valid_0 & prs2_matches_4; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0 = io_wakeup_ports_0_valid_0 & prs3_matches_0; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_2 = io_wakeup_ports_2_valid_0 & prs3_matches_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_3 = io_wakeup_ports_3_valid_0 & prs3_matches_3; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_4 = io_wakeup_ports_4_valid_0 & prs3_matches_4; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs1_rebusys_0 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0; // @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95] wire prs2_rebusys_0 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0; // @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95] wire _T_3 = prs1_wakeups_0 | prs1_wakeups_1 | prs1_wakeups_2 | prs1_wakeups_3 | prs1_wakeups_4; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire [2:0] _WIRE_iw_p1_speculative_child = _T_3 ? (prs1_wakeups_0 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs1_wakeups_4, prs1_wakeups_3, prs1_wakeups_2} : io_dis_uops_0_bits_iw_p1_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_iw_p1_bypass_hint = _T_3 & (prs1_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2 | prs1_wakeups_3 | prs1_wakeups_4); // @[Mux.scala:30:73] wire _WIRE_prs1_busy = (|{prs1_rebusys_0, io_child_rebusys_0 & io_dis_uops_0_bits_iw_p1_speculative_child_0}) ? io_dis_uops_0_bits_lrs1_rtype_0 == 2'h0 : ~_T_3 & io_dis_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}] wire _T_33 = prs2_wakeups_0 | prs2_wakeups_1 | prs2_wakeups_2 | prs2_wakeups_3 | prs2_wakeups_4; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire [2:0] _WIRE_iw_p2_speculative_child = _T_33 ? (prs2_wakeups_0 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs2_wakeups_4, prs2_wakeups_3, prs2_wakeups_2} : io_dis_uops_0_bits_iw_p2_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_iw_p2_bypass_hint = _T_33 & (prs2_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2 | prs2_wakeups_3 | prs2_wakeups_4); // @[Mux.scala:30:73] wire _WIRE_prs2_busy = (|{prs2_rebusys_0, io_child_rebusys_0 & io_dis_uops_0_bits_iw_p2_speculative_child_0}) ? io_dis_uops_0_bits_lrs2_rtype_0 == 2'h0 : ~_T_33 & io_dis_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}] wire _T_63 = prs3_wakeups_0 | prs3_wakeups_1 | prs3_wakeups_2 | prs3_wakeups_3 | prs3_wakeups_4; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _WIRE_prs3_busy = ~_T_63 & io_dis_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29] wire _WIRE_iw_p3_bypass_hint = _T_63 & (prs3_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2 | prs3_wakeups_3 | prs3_wakeups_4); // @[Mux.scala:30:73] wire _WIRE_ppred_busy = ~(io_pred_wakeup_port_valid_0 & io_pred_wakeup_port_bits_0 == io_dis_uops_0_bits_ppred_0) & io_dis_uops_0_bits_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :80:{37,65,96}, :81:30] wire prs1_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_4_1 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_4_1 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_4_1 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs1_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs1_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs1_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_4_1 = io_wakeup_ports_4_valid_0 & prs1_matches_4_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs2_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs2_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs2_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_4_1 = io_wakeup_ports_4_valid_0 & prs2_matches_4_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs3_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs3_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs3_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_4_1 = io_wakeup_ports_4_valid_0 & prs3_matches_4_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs1_rebusys_0_1 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95] wire prs2_rebusys_0_1 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95] wire _T_78 = prs1_wakeups_0_1 | prs1_wakeups_1_1 | prs1_wakeups_2_1 | prs1_wakeups_3_1 | prs1_wakeups_4_1; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire [2:0] _WIRE_1_iw_p1_speculative_child = _T_78 ? (prs1_wakeups_0_1 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs1_wakeups_4_1, prs1_wakeups_3_1, prs1_wakeups_2_1} : io_dis_uops_1_bits_iw_p1_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_1_iw_p1_bypass_hint = _T_78 & (prs1_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2_1 | prs1_wakeups_3_1 | prs1_wakeups_4_1); // @[Mux.scala:30:73] wire _WIRE_1_prs1_busy = (|{prs1_rebusys_0_1, io_child_rebusys_0 & io_dis_uops_1_bits_iw_p1_speculative_child_0}) ? io_dis_uops_1_bits_lrs1_rtype_0 == 2'h0 : ~_T_78 & io_dis_uops_1_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}] wire _T_108 = prs2_wakeups_0_1 | prs2_wakeups_1_1 | prs2_wakeups_2_1 | prs2_wakeups_3_1 | prs2_wakeups_4_1; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire [2:0] _WIRE_1_iw_p2_speculative_child = _T_108 ? (prs2_wakeups_0_1 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs2_wakeups_4_1, prs2_wakeups_3_1, prs2_wakeups_2_1} : io_dis_uops_1_bits_iw_p2_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_1_iw_p2_bypass_hint = _T_108 & (prs2_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2_1 | prs2_wakeups_3_1 | prs2_wakeups_4_1); // @[Mux.scala:30:73] wire _WIRE_1_prs2_busy = (|{prs2_rebusys_0_1, io_child_rebusys_0 & io_dis_uops_1_bits_iw_p2_speculative_child_0}) ? io_dis_uops_1_bits_lrs2_rtype_0 == 2'h0 : ~_T_108 & io_dis_uops_1_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}] wire _T_138 = prs3_wakeups_0_1 | prs3_wakeups_1_1 | prs3_wakeups_2_1 | prs3_wakeups_3_1 | prs3_wakeups_4_1; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _WIRE_1_prs3_busy = ~_T_138 & io_dis_uops_1_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29] wire _WIRE_1_iw_p3_bypass_hint = _T_138 & (prs3_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2_1 | prs3_wakeups_3_1 | prs3_wakeups_4_1); // @[Mux.scala:30:73] wire _WIRE_1_ppred_busy = ~(io_pred_wakeup_port_valid_0 & io_pred_wakeup_port_bits_0 == io_dis_uops_1_bits_ppred_0) & io_dis_uops_1_bits_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :80:{37,65,96}, :81:30] wire prs1_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_2_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_3_2 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_4_2 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_2_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_3_2 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_4_2 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_2_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_3_2 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_4_2 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs1_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs1_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_2_2 = io_wakeup_ports_2_valid_0 & prs1_matches_2_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_3_2 = io_wakeup_ports_3_valid_0 & prs1_matches_3_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_4_2 = io_wakeup_ports_4_valid_0 & prs1_matches_4_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs2_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs2_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_2_2 = io_wakeup_ports_2_valid_0 & prs2_matches_2_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_3_2 = io_wakeup_ports_3_valid_0 & prs2_matches_3_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_4_2 = io_wakeup_ports_4_valid_0 & prs2_matches_4_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs3_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs3_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_2_2 = io_wakeup_ports_2_valid_0 & prs3_matches_2_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_3_2 = io_wakeup_ports_3_valid_0 & prs3_matches_3_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_4_2 = io_wakeup_ports_4_valid_0 & prs3_matches_4_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs1_rebusys_0_2 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95] wire prs2_rebusys_0_2 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95] wire _T_153 = prs1_wakeups_0_2 | prs1_wakeups_1_2 | prs1_wakeups_2_2 | prs1_wakeups_3_2 | prs1_wakeups_4_2; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire _T_183 = prs2_wakeups_0_2 | prs2_wakeups_1_2 | prs2_wakeups_2_2 | prs2_wakeups_3_2 | prs2_wakeups_4_2; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire _T_213 = prs3_wakeups_0_2 | prs3_wakeups_1_2 | prs3_wakeups_2_2 | prs3_wakeups_3_2 | prs3_wakeups_4_2; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _fu_code_match_T = issue_slots_0_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_18 = issue_slots_1_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_36 = issue_slots_2_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_54 = issue_slots_3_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_72 = issue_slots_4_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_90 = issue_slots_5_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_108 = issue_slots_6_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_126 = issue_slots_7_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_144 = issue_slots_8_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_162 = issue_slots_9_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_180 = issue_slots_10_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_198 = issue_slots_11_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_216 = issue_slots_12_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_234 = issue_slots_13_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_252 = issue_slots_14_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_270 = issue_slots_15_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire issue_slots_0_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_clear; // @[issue-unit-age-ordered.scala:122:28] wire vacants_0 = ~issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_1 = ~issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_2 = ~issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_3 = ~issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_4 = ~issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_5 = ~issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_6 = ~issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_7 = ~issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_8 = ~issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_9 = ~issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_10 = ~issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_11 = ~issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_12 = ~issue_slots_12_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_13 = ~issue_slots_13_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_14 = ~issue_slots_14_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_15 = ~issue_slots_15_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_16 = ~io_dis_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire vacants_17 = ~io_dis_uops_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire vacants_18 = ~io_dis_uops_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire [2:0] shamts_oh_8_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_9_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_10_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_11_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_12_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_13_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_14_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_15_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_16_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_17_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_18_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_18; // @[issue-unit-age-ordered.scala:158:23] assign shamts_oh_1 = {2'h0, vacants_0}; // @[issue-unit-age-ordered.scala:157:38, :158:23, :174:20] wire _GEN = vacants_0 | vacants_1; // @[issue-unit-age-ordered.scala:157:38, :174:47] wire _shamts_oh_2_T; // @[issue-unit-age-ordered.scala:174:47] assign _shamts_oh_2_T = _GEN; // @[issue-unit-age-ordered.scala:174:47] wire _shamts_oh_3_T; // @[issue-unit-age-ordered.scala:174:47] assign _shamts_oh_3_T = _GEN; // @[issue-unit-age-ordered.scala:174:47] assign shamts_oh_2 = {2'h0, _shamts_oh_2_T}; // @[issue-unit-age-ordered.scala:158:23, :174:{20,47}] wire _shamts_oh_3_T_1 = _shamts_oh_3_T | vacants_2; // @[issue-unit-age-ordered.scala:157:38, :174:47] assign shamts_oh_3 = {2'h0, _shamts_oh_3_T_1}; // @[issue-unit-age-ordered.scala:158:23, :174:{20,47}] wire [1:0] shamts_oh_4_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_4_T = ~(|shamts_oh_3); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_4_T_1 = _shamts_oh_4_T & vacants_3; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_4_T_2 = shamts_oh_3[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_4_T_3 = ~_shamts_oh_4_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_4_T_4 = _shamts_oh_4_T_3 & vacants_3; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_4_next_T = {shamts_oh_3, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_4_next = _shamts_oh_4_T_1 ? 2'h1 : _shamts_oh_4_T_4 ? _shamts_oh_4_next_T[1:0] : shamts_oh_3[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_4 = {1'h0, shamts_oh_4_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_5_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_5_T = ~(|shamts_oh_4); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_5_T_1 = _shamts_oh_5_T & vacants_4; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_5_T_2 = shamts_oh_4[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_5_T_3 = ~_shamts_oh_5_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_5_T_4 = _shamts_oh_5_T_3 & vacants_4; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_5_next_T = {shamts_oh_4, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_5_next = _shamts_oh_5_T_1 ? 2'h1 : _shamts_oh_5_T_4 ? _shamts_oh_5_next_T[1:0] : shamts_oh_4[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_5 = {1'h0, shamts_oh_5_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_6_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_6_T = ~(|shamts_oh_5); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_6_T_1 = _shamts_oh_6_T & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_6_T_2 = shamts_oh_5[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_6_T_3 = ~_shamts_oh_6_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_6_T_4 = _shamts_oh_6_T_3 & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_6_next_T = {shamts_oh_5, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_6_next = _shamts_oh_6_T_1 ? 2'h1 : _shamts_oh_6_T_4 ? _shamts_oh_6_next_T[1:0] : shamts_oh_5[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_6 = {1'h0, shamts_oh_6_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_7_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_7_T = ~(|shamts_oh_6); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_7_T_1 = _shamts_oh_7_T & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_7_T_2 = shamts_oh_6[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_7_T_3 = ~_shamts_oh_7_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_7_T_4 = _shamts_oh_7_T_3 & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_7_next_T = {shamts_oh_6, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_7_next = _shamts_oh_7_T_1 ? 2'h1 : _shamts_oh_7_T_4 ? _shamts_oh_7_next_T[1:0] : shamts_oh_6[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_7 = {1'h0, shamts_oh_7_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] assign shamts_oh_8 = shamts_oh_8_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_8_T = ~(|shamts_oh_7); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_8_T_1 = _shamts_oh_8_T & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_8_T_2 = shamts_oh_7[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_8_T_3 = ~_shamts_oh_8_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_8_T_4 = _shamts_oh_8_T_3 & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_8_next_T = {shamts_oh_7, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_8_next = _shamts_oh_8_T_1 ? 3'h1 : _shamts_oh_8_T_4 ? _shamts_oh_8_next_T[2:0] : shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_9 = shamts_oh_9_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_9_T = ~(|shamts_oh_8); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_9_T_1 = _shamts_oh_9_T & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_9_T_2 = shamts_oh_8[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_9_T_3 = ~_shamts_oh_9_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_9_T_4 = _shamts_oh_9_T_3 & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_9_next_T = {shamts_oh_8, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_9_next = _shamts_oh_9_T_1 ? 3'h1 : _shamts_oh_9_T_4 ? _shamts_oh_9_next_T[2:0] : shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_10 = shamts_oh_10_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_10_T = ~(|shamts_oh_9); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_10_T_1 = _shamts_oh_10_T & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_10_T_2 = shamts_oh_9[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_10_T_3 = ~_shamts_oh_10_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_10_T_4 = _shamts_oh_10_T_3 & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_10_next_T = {shamts_oh_9, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_10_next = _shamts_oh_10_T_1 ? 3'h1 : _shamts_oh_10_T_4 ? _shamts_oh_10_next_T[2:0] : shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_11 = shamts_oh_11_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_11_T = ~(|shamts_oh_10); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_11_T_1 = _shamts_oh_11_T & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_11_T_2 = shamts_oh_10[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_11_T_3 = ~_shamts_oh_11_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_11_T_4 = _shamts_oh_11_T_3 & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_11_next_T = {shamts_oh_10, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_11_next = _shamts_oh_11_T_1 ? 3'h1 : _shamts_oh_11_T_4 ? _shamts_oh_11_next_T[2:0] : shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_12 = shamts_oh_12_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_12_T = ~(|shamts_oh_11); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_12_T_1 = _shamts_oh_12_T & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_12_T_2 = shamts_oh_11[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_12_T_3 = ~_shamts_oh_12_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_12_T_4 = _shamts_oh_12_T_3 & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_12_next_T = {shamts_oh_11, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_12_next = _shamts_oh_12_T_1 ? 3'h1 : _shamts_oh_12_T_4 ? _shamts_oh_12_next_T[2:0] : shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_13 = shamts_oh_13_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_13_T = ~(|shamts_oh_12); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_13_T_1 = _shamts_oh_13_T & vacants_12; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_13_T_2 = shamts_oh_12[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_13_T_3 = ~_shamts_oh_13_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_13_T_4 = _shamts_oh_13_T_3 & vacants_12; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_13_next_T = {shamts_oh_12, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_13_next = _shamts_oh_13_T_1 ? 3'h1 : _shamts_oh_13_T_4 ? _shamts_oh_13_next_T[2:0] : shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_14 = shamts_oh_14_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_14_T = ~(|shamts_oh_13); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_14_T_1 = _shamts_oh_14_T & vacants_13; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_14_T_2 = shamts_oh_13[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_14_T_3 = ~_shamts_oh_14_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_14_T_4 = _shamts_oh_14_T_3 & vacants_13; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_14_next_T = {shamts_oh_13, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_14_next = _shamts_oh_14_T_1 ? 3'h1 : _shamts_oh_14_T_4 ? _shamts_oh_14_next_T[2:0] : shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_15 = shamts_oh_15_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_15_T = ~(|shamts_oh_14); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_15_T_1 = _shamts_oh_15_T & vacants_14; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_15_T_2 = shamts_oh_14[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_15_T_3 = ~_shamts_oh_15_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_15_T_4 = _shamts_oh_15_T_3 & vacants_14; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_15_next_T = {shamts_oh_14, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_15_next = _shamts_oh_15_T_1 ? 3'h1 : _shamts_oh_15_T_4 ? _shamts_oh_15_next_T[2:0] : shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_16 = shamts_oh_16_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_16_T = ~(|shamts_oh_15); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_16_T_1 = _shamts_oh_16_T & vacants_15; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_16_T_2 = shamts_oh_15[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_16_T_3 = ~_shamts_oh_16_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_16_T_4 = _shamts_oh_16_T_3 & vacants_15; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_16_next_T = {shamts_oh_15, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_16_next = _shamts_oh_16_T_1 ? 3'h1 : _shamts_oh_16_T_4 ? _shamts_oh_16_next_T[2:0] : shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_17 = shamts_oh_17_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_17_T = shamts_oh_16 == 3'h0; // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_17_T_1 = _shamts_oh_17_T & vacants_16; // @[issue-unit-age-ordered.scala:157:82, :163:{21,29}] wire _shamts_oh_17_T_2 = shamts_oh_16[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_17_T_3 = ~_shamts_oh_17_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_17_T_4 = _shamts_oh_17_T_3 & vacants_16; // @[issue-unit-age-ordered.scala:157:82, :165:{19,36}] wire [3:0] _shamts_oh_17_next_T = {shamts_oh_16, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_17_next = _shamts_oh_17_T_1 ? 3'h1 : _shamts_oh_17_T_4 ? _shamts_oh_17_next_T[2:0] : shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_18 = shamts_oh_18_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_18_T = shamts_oh_17 == 3'h0; // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_18_T_1 = _shamts_oh_18_T & vacants_17; // @[issue-unit-age-ordered.scala:157:82, :163:{21,29}] wire _shamts_oh_18_T_2 = shamts_oh_17[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_18_T_3 = ~_shamts_oh_18_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_18_T_4 = _shamts_oh_18_T_3 & vacants_17; // @[issue-unit-age-ordered.scala:157:82, :165:{19,36}] wire [3:0] _shamts_oh_18_next_T = {shamts_oh_17, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_18_next = _shamts_oh_18_T_1 ? 3'h1 : _shamts_oh_18_T_4 ? _shamts_oh_18_next_T[2:0] : shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] wire _will_be_valid_T = ~io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_1 = io_dis_uops_0_valid_0 & _will_be_valid_T; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_2 = ~io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_3 = _will_be_valid_T_1 & _will_be_valid_T_2; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_4 = ~io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_16 = _will_be_valid_T_3 & _will_be_valid_T_4; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _will_be_valid_T_5 = ~io_dis_uops_1_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_6 = io_dis_uops_1_valid_0 & _will_be_valid_T_5; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_7 = ~io_dis_uops_1_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_8 = _will_be_valid_T_6 & _will_be_valid_T_7; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_9 = ~io_dis_uops_1_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_17 = _will_be_valid_T_8 & _will_be_valid_T_9; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _will_be_valid_T_10 = ~io_dis_uops_2_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_11 = io_dis_uops_2_valid_0 & _will_be_valid_T_10; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_12 = ~io_dis_uops_2_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_13 = _will_be_valid_T_11 & _will_be_valid_T_12; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_14 = ~io_dis_uops_2_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_18 = _will_be_valid_T_13 & _will_be_valid_T_14; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _T_260 = shamts_oh_2 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_261 = shamts_oh_3 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_0_in_uop_valid = _T_261 ? issue_slots_3_will_be_valid : _T_260 ? issue_slots_2_will_be_valid : shamts_oh_1 == 3'h1 & issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_0_in_uop_bits_debug_tsrc = _T_261 ? issue_slots_3_out_uop_debug_tsrc : _T_260 ? issue_slots_2_out_uop_debug_tsrc : issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_fsrc = _T_261 ? issue_slots_3_out_uop_debug_fsrc : _T_260 ? issue_slots_2_out_uop_debug_fsrc : issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_xcpt_if = _T_261 ? issue_slots_3_out_uop_bp_xcpt_if : _T_260 ? issue_slots_2_out_uop_bp_xcpt_if : issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_debug_if = _T_261 ? issue_slots_3_out_uop_bp_debug_if : _T_260 ? issue_slots_2_out_uop_bp_debug_if : issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ma_if = _T_261 ? issue_slots_3_out_uop_xcpt_ma_if : _T_260 ? issue_slots_2_out_uop_xcpt_ma_if : issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ae_if = _T_261 ? issue_slots_3_out_uop_xcpt_ae_if : _T_260 ? issue_slots_2_out_uop_xcpt_ae_if : issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_pf_if = _T_261 ? issue_slots_3_out_uop_xcpt_pf_if : _T_260 ? issue_slots_2_out_uop_xcpt_pf_if : issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_typ = _T_261 ? issue_slots_3_out_uop_fp_typ : _T_260 ? issue_slots_2_out_uop_fp_typ : issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_rm = _T_261 ? issue_slots_3_out_uop_fp_rm : _T_260 ? issue_slots_2_out_uop_fp_rm : issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_val = _T_261 ? issue_slots_3_out_uop_fp_val : _T_260 ? issue_slots_2_out_uop_fp_val : issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_op = _T_261 ? issue_slots_3_out_uop_fcn_op : _T_260 ? issue_slots_2_out_uop_fcn_op : issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_dw = _T_261 ? issue_slots_3_out_uop_fcn_dw : _T_260 ? issue_slots_2_out_uop_fcn_dw : issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_frs3_en = _T_261 ? issue_slots_3_out_uop_frs3_en : _T_260 ? issue_slots_2_out_uop_frs3_en : issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2_rtype = _T_261 ? issue_slots_3_out_uop_lrs2_rtype : _T_260 ? issue_slots_2_out_uop_lrs2_rtype : issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1_rtype = _T_261 ? issue_slots_3_out_uop_lrs1_rtype : _T_260 ? issue_slots_2_out_uop_lrs1_rtype : issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dst_rtype = _T_261 ? issue_slots_3_out_uop_dst_rtype : _T_260 ? issue_slots_2_out_uop_dst_rtype : issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs3 = _T_261 ? issue_slots_3_out_uop_lrs3 : _T_260 ? issue_slots_2_out_uop_lrs3 : issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2 = _T_261 ? issue_slots_3_out_uop_lrs2 : _T_260 ? issue_slots_2_out_uop_lrs2 : issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1 = _T_261 ? issue_slots_3_out_uop_lrs1 : _T_260 ? issue_slots_2_out_uop_lrs1 : issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst = _T_261 ? issue_slots_3_out_uop_ldst : _T_260 ? issue_slots_2_out_uop_ldst : issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst_is_rs1 = _T_261 ? issue_slots_3_out_uop_ldst_is_rs1 : _T_260 ? issue_slots_2_out_uop_ldst_is_rs1 : issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_csr_cmd = _T_261 ? issue_slots_3_out_uop_csr_cmd : _T_260 ? issue_slots_2_out_uop_csr_cmd : issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_flush_on_commit = _T_261 ? issue_slots_3_out_uop_flush_on_commit : _T_260 ? issue_slots_2_out_uop_flush_on_commit : issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_unique = _T_261 ? issue_slots_3_out_uop_is_unique : _T_260 ? issue_slots_2_out_uop_is_unique : issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_stq = _T_261 ? issue_slots_3_out_uop_uses_stq : _T_260 ? issue_slots_2_out_uop_uses_stq : issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_ldq = _T_261 ? issue_slots_3_out_uop_uses_ldq : _T_260 ? issue_slots_2_out_uop_uses_ldq : issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_signed = _T_261 ? issue_slots_3_out_uop_mem_signed : _T_260 ? issue_slots_2_out_uop_mem_signed : issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_size = _T_261 ? issue_slots_3_out_uop_mem_size : _T_260 ? issue_slots_2_out_uop_mem_size : issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_cmd = _T_261 ? issue_slots_3_out_uop_mem_cmd : _T_260 ? issue_slots_2_out_uop_mem_cmd : issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exc_cause = _T_261 ? issue_slots_3_out_uop_exc_cause : _T_260 ? issue_slots_2_out_uop_exc_cause : issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exception = _T_261 ? issue_slots_3_out_uop_exception : _T_260 ? issue_slots_2_out_uop_exception : issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stale_pdst = _T_261 ? issue_slots_3_out_uop_stale_pdst : _T_260 ? issue_slots_2_out_uop_stale_pdst : issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred_busy = _T_261 ? issue_slots_3_out_uop_ppred_busy : _T_260 ? issue_slots_2_out_uop_ppred_busy : issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3_busy = _T_261 ? issue_slots_3_out_uop_prs3_busy : _T_260 ? issue_slots_2_out_uop_prs3_busy : issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2_busy = _T_261 ? issue_slots_3_out_uop_prs2_busy : _T_260 ? issue_slots_2_out_uop_prs2_busy : issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1_busy = _T_261 ? issue_slots_3_out_uop_prs1_busy : _T_260 ? issue_slots_2_out_uop_prs1_busy : issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred = _T_261 ? issue_slots_3_out_uop_ppred : _T_260 ? issue_slots_2_out_uop_ppred : issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3 = _T_261 ? issue_slots_3_out_uop_prs3 : _T_260 ? issue_slots_2_out_uop_prs3 : issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2 = _T_261 ? issue_slots_3_out_uop_prs2 : _T_260 ? issue_slots_2_out_uop_prs2 : issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1 = _T_261 ? issue_slots_3_out_uop_prs1 : _T_260 ? issue_slots_2_out_uop_prs1 : issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pdst = _T_261 ? issue_slots_3_out_uop_pdst : _T_260 ? issue_slots_2_out_uop_pdst : issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rxq_idx = _T_261 ? issue_slots_3_out_uop_rxq_idx : _T_260 ? issue_slots_2_out_uop_rxq_idx : issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stq_idx = _T_261 ? issue_slots_3_out_uop_stq_idx : _T_260 ? issue_slots_2_out_uop_stq_idx : issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldq_idx = _T_261 ? issue_slots_3_out_uop_ldq_idx : _T_260 ? issue_slots_2_out_uop_ldq_idx : issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rob_idx = _T_261 ? issue_slots_3_out_uop_rob_idx : _T_260 ? issue_slots_2_out_uop_rob_idx : issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_vec = _T_261 ? issue_slots_3_out_uop_fp_ctrl_vec : _T_260 ? issue_slots_2_out_uop_fp_ctrl_vec : issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wflags = _T_261 ? issue_slots_3_out_uop_fp_ctrl_wflags : _T_260 ? issue_slots_2_out_uop_fp_ctrl_wflags : issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_sqrt = _T_261 ? issue_slots_3_out_uop_fp_ctrl_sqrt : _T_260 ? issue_slots_2_out_uop_fp_ctrl_sqrt : issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_div = _T_261 ? issue_slots_3_out_uop_fp_ctrl_div : _T_260 ? issue_slots_2_out_uop_fp_ctrl_div : issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fma = _T_261 ? issue_slots_3_out_uop_fp_ctrl_fma : _T_260 ? issue_slots_2_out_uop_fp_ctrl_fma : issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fastpipe = _T_261 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : _T_260 ? issue_slots_2_out_uop_fp_ctrl_fastpipe : issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_toint = _T_261 ? issue_slots_3_out_uop_fp_ctrl_toint : _T_260 ? issue_slots_2_out_uop_fp_ctrl_toint : issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fromint = _T_261 ? issue_slots_3_out_uop_fp_ctrl_fromint : _T_260 ? issue_slots_2_out_uop_fp_ctrl_fromint : issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut = _T_261 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : _T_260 ? issue_slots_2_out_uop_fp_ctrl_typeTagOut : issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn = _T_261 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : _T_260 ? issue_slots_2_out_uop_fp_ctrl_typeTagIn : issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap23 = _T_261 ? issue_slots_3_out_uop_fp_ctrl_swap23 : _T_260 ? issue_slots_2_out_uop_fp_ctrl_swap23 : issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap12 = _T_261 ? issue_slots_3_out_uop_fp_ctrl_swap12 : _T_260 ? issue_slots_2_out_uop_fp_ctrl_swap12 : issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren3 = _T_261 ? issue_slots_3_out_uop_fp_ctrl_ren3 : _T_260 ? issue_slots_2_out_uop_fp_ctrl_ren3 : issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren2 = _T_261 ? issue_slots_3_out_uop_fp_ctrl_ren2 : _T_260 ? issue_slots_2_out_uop_fp_ctrl_ren2 : issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren1 = _T_261 ? issue_slots_3_out_uop_fp_ctrl_ren1 : _T_260 ? issue_slots_2_out_uop_fp_ctrl_ren1 : issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wen = _T_261 ? issue_slots_3_out_uop_fp_ctrl_wen : _T_260 ? issue_slots_2_out_uop_fp_ctrl_wen : issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ldst = _T_261 ? issue_slots_3_out_uop_fp_ctrl_ldst : _T_260 ? issue_slots_2_out_uop_fp_ctrl_ldst : issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op2_sel = _T_261 ? issue_slots_3_out_uop_op2_sel : _T_260 ? issue_slots_2_out_uop_op2_sel : issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op1_sel = _T_261 ? issue_slots_3_out_uop_op1_sel : _T_260 ? issue_slots_2_out_uop_op1_sel : issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_packed = _T_261 ? issue_slots_3_out_uop_imm_packed : _T_260 ? issue_slots_2_out_uop_imm_packed : issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pimm = _T_261 ? issue_slots_3_out_uop_pimm : _T_260 ? issue_slots_2_out_uop_pimm : issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_sel = _T_261 ? issue_slots_3_out_uop_imm_sel : _T_260 ? issue_slots_2_out_uop_imm_sel : issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_rename = _T_261 ? issue_slots_3_out_uop_imm_rename : _T_260 ? issue_slots_2_out_uop_imm_rename : issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_taken = _T_261 ? issue_slots_3_out_uop_taken : _T_260 ? issue_slots_2_out_uop_taken : issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pc_lob = _T_261 ? issue_slots_3_out_uop_pc_lob : _T_260 ? issue_slots_2_out_uop_pc_lob : issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_edge_inst = _T_261 ? issue_slots_3_out_uop_edge_inst : _T_260 ? issue_slots_2_out_uop_edge_inst : issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ftq_idx = _T_261 ? issue_slots_3_out_uop_ftq_idx : _T_260 ? issue_slots_2_out_uop_ftq_idx : issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_mov = _T_261 ? issue_slots_3_out_uop_is_mov : _T_260 ? issue_slots_2_out_uop_is_mov : issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rocc = _T_261 ? issue_slots_3_out_uop_is_rocc : _T_260 ? issue_slots_2_out_uop_is_rocc : issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sys_pc2epc = _T_261 ? issue_slots_3_out_uop_is_sys_pc2epc : _T_260 ? issue_slots_2_out_uop_is_sys_pc2epc : issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_eret = _T_261 ? issue_slots_3_out_uop_is_eret : _T_260 ? issue_slots_2_out_uop_is_eret : issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_amo = _T_261 ? issue_slots_3_out_uop_is_amo : _T_260 ? issue_slots_2_out_uop_is_amo : issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfence = _T_261 ? issue_slots_3_out_uop_is_sfence : _T_260 ? issue_slots_2_out_uop_is_sfence : issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fencei = _T_261 ? issue_slots_3_out_uop_is_fencei : _T_260 ? issue_slots_2_out_uop_is_fencei : issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fence = _T_261 ? issue_slots_3_out_uop_is_fence : _T_260 ? issue_slots_2_out_uop_is_fence : issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfb = _T_261 ? issue_slots_3_out_uop_is_sfb : _T_260 ? issue_slots_2_out_uop_is_sfb : issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_type = _T_261 ? issue_slots_3_out_uop_br_type : _T_260 ? issue_slots_2_out_uop_br_type : issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_tag = _T_261 ? issue_slots_3_out_uop_br_tag : _T_260 ? issue_slots_2_out_uop_br_tag : issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_mask = _T_261 ? issue_slots_3_out_uop_br_mask : _T_260 ? issue_slots_2_out_uop_br_mask : issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dis_col_sel = _T_261 ? issue_slots_3_out_uop_dis_col_sel : _T_260 ? issue_slots_2_out_uop_dis_col_sel : issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p3_bypass_hint = _T_261 ? issue_slots_3_out_uop_iw_p3_bypass_hint : _T_260 ? issue_slots_2_out_uop_iw_p3_bypass_hint : issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p2_bypass_hint = _T_261 ? issue_slots_3_out_uop_iw_p2_bypass_hint : _T_260 ? issue_slots_2_out_uop_iw_p2_bypass_hint : issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p1_bypass_hint = _T_261 ? issue_slots_3_out_uop_iw_p1_bypass_hint : _T_260 ? issue_slots_2_out_uop_iw_p1_bypass_hint : issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p2_speculative_child = _T_261 ? issue_slots_3_out_uop_iw_p2_speculative_child : _T_260 ? issue_slots_2_out_uop_iw_p2_speculative_child : issue_slots_1_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p1_speculative_child = _T_261 ? issue_slots_3_out_uop_iw_p1_speculative_child : _T_260 ? issue_slots_2_out_uop_iw_p1_speculative_child : issue_slots_1_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_issued = _T_261 ? issue_slots_3_out_uop_iw_issued : _T_260 ? issue_slots_2_out_uop_iw_issued : issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_0 = _T_261 ? issue_slots_3_out_uop_fu_code_0 : _T_260 ? issue_slots_2_out_uop_fu_code_0 : issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_1 = _T_261 ? issue_slots_3_out_uop_fu_code_1 : _T_260 ? issue_slots_2_out_uop_fu_code_1 : issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_2 = _T_261 ? issue_slots_3_out_uop_fu_code_2 : _T_260 ? issue_slots_2_out_uop_fu_code_2 : issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_3 = _T_261 ? issue_slots_3_out_uop_fu_code_3 : _T_260 ? issue_slots_2_out_uop_fu_code_3 : issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_4 = _T_261 ? issue_slots_3_out_uop_fu_code_4 : _T_260 ? issue_slots_2_out_uop_fu_code_4 : issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_5 = _T_261 ? issue_slots_3_out_uop_fu_code_5 : _T_260 ? issue_slots_2_out_uop_fu_code_5 : issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_6 = _T_261 ? issue_slots_3_out_uop_fu_code_6 : _T_260 ? issue_slots_2_out_uop_fu_code_6 : issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_7 = _T_261 ? issue_slots_3_out_uop_fu_code_7 : _T_260 ? issue_slots_2_out_uop_fu_code_7 : issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_8 = _T_261 ? issue_slots_3_out_uop_fu_code_8 : _T_260 ? issue_slots_2_out_uop_fu_code_8 : issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_9 = _T_261 ? issue_slots_3_out_uop_fu_code_9 : _T_260 ? issue_slots_2_out_uop_fu_code_9 : issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_0 = _T_261 ? issue_slots_3_out_uop_iq_type_0 : _T_260 ? issue_slots_2_out_uop_iq_type_0 : issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_1 = _T_261 ? issue_slots_3_out_uop_iq_type_1 : _T_260 ? issue_slots_2_out_uop_iq_type_1 : issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_2 = _T_261 ? issue_slots_3_out_uop_iq_type_2 : _T_260 ? issue_slots_2_out_uop_iq_type_2 : issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_3 = _T_261 ? issue_slots_3_out_uop_iq_type_3 : _T_260 ? issue_slots_2_out_uop_iq_type_3 : issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_pc = _T_261 ? issue_slots_3_out_uop_debug_pc : _T_260 ? issue_slots_2_out_uop_debug_pc : issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rvc = _T_261 ? issue_slots_3_out_uop_is_rvc : _T_260 ? issue_slots_2_out_uop_is_rvc : issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_inst = _T_261 ? issue_slots_3_out_uop_debug_inst : _T_260 ? issue_slots_2_out_uop_debug_inst : issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_inst = _T_261 ? issue_slots_3_out_uop_inst : _T_260 ? issue_slots_2_out_uop_inst : issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] wire _T_263 = shamts_oh_3 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_264 = shamts_oh_4 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_1_in_uop_valid = _T_264 ? issue_slots_4_will_be_valid : _T_263 ? issue_slots_3_will_be_valid : shamts_oh_2 == 3'h1 & issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_1_in_uop_bits_debug_tsrc = _T_264 ? issue_slots_4_out_uop_debug_tsrc : _T_263 ? issue_slots_3_out_uop_debug_tsrc : issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_fsrc = _T_264 ? issue_slots_4_out_uop_debug_fsrc : _T_263 ? issue_slots_3_out_uop_debug_fsrc : issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_xcpt_if = _T_264 ? issue_slots_4_out_uop_bp_xcpt_if : _T_263 ? issue_slots_3_out_uop_bp_xcpt_if : issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_debug_if = _T_264 ? issue_slots_4_out_uop_bp_debug_if : _T_263 ? issue_slots_3_out_uop_bp_debug_if : issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ma_if = _T_264 ? issue_slots_4_out_uop_xcpt_ma_if : _T_263 ? issue_slots_3_out_uop_xcpt_ma_if : issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ae_if = _T_264 ? issue_slots_4_out_uop_xcpt_ae_if : _T_263 ? issue_slots_3_out_uop_xcpt_ae_if : issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_pf_if = _T_264 ? issue_slots_4_out_uop_xcpt_pf_if : _T_263 ? issue_slots_3_out_uop_xcpt_pf_if : issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_typ = _T_264 ? issue_slots_4_out_uop_fp_typ : _T_263 ? issue_slots_3_out_uop_fp_typ : issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_rm = _T_264 ? issue_slots_4_out_uop_fp_rm : _T_263 ? issue_slots_3_out_uop_fp_rm : issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_val = _T_264 ? issue_slots_4_out_uop_fp_val : _T_263 ? issue_slots_3_out_uop_fp_val : issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_op = _T_264 ? issue_slots_4_out_uop_fcn_op : _T_263 ? issue_slots_3_out_uop_fcn_op : issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_dw = _T_264 ? issue_slots_4_out_uop_fcn_dw : _T_263 ? issue_slots_3_out_uop_fcn_dw : issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_frs3_en = _T_264 ? issue_slots_4_out_uop_frs3_en : _T_263 ? issue_slots_3_out_uop_frs3_en : issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2_rtype = _T_264 ? issue_slots_4_out_uop_lrs2_rtype : _T_263 ? issue_slots_3_out_uop_lrs2_rtype : issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1_rtype = _T_264 ? issue_slots_4_out_uop_lrs1_rtype : _T_263 ? issue_slots_3_out_uop_lrs1_rtype : issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dst_rtype = _T_264 ? issue_slots_4_out_uop_dst_rtype : _T_263 ? issue_slots_3_out_uop_dst_rtype : issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs3 = _T_264 ? issue_slots_4_out_uop_lrs3 : _T_263 ? issue_slots_3_out_uop_lrs3 : issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2 = _T_264 ? issue_slots_4_out_uop_lrs2 : _T_263 ? issue_slots_3_out_uop_lrs2 : issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1 = _T_264 ? issue_slots_4_out_uop_lrs1 : _T_263 ? issue_slots_3_out_uop_lrs1 : issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst = _T_264 ? issue_slots_4_out_uop_ldst : _T_263 ? issue_slots_3_out_uop_ldst : issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst_is_rs1 = _T_264 ? issue_slots_4_out_uop_ldst_is_rs1 : _T_263 ? issue_slots_3_out_uop_ldst_is_rs1 : issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_csr_cmd = _T_264 ? issue_slots_4_out_uop_csr_cmd : _T_263 ? issue_slots_3_out_uop_csr_cmd : issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_flush_on_commit = _T_264 ? issue_slots_4_out_uop_flush_on_commit : _T_263 ? issue_slots_3_out_uop_flush_on_commit : issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_unique = _T_264 ? issue_slots_4_out_uop_is_unique : _T_263 ? issue_slots_3_out_uop_is_unique : issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_stq = _T_264 ? issue_slots_4_out_uop_uses_stq : _T_263 ? issue_slots_3_out_uop_uses_stq : issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_ldq = _T_264 ? issue_slots_4_out_uop_uses_ldq : _T_263 ? issue_slots_3_out_uop_uses_ldq : issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_signed = _T_264 ? issue_slots_4_out_uop_mem_signed : _T_263 ? issue_slots_3_out_uop_mem_signed : issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_size = _T_264 ? issue_slots_4_out_uop_mem_size : _T_263 ? issue_slots_3_out_uop_mem_size : issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_cmd = _T_264 ? issue_slots_4_out_uop_mem_cmd : _T_263 ? issue_slots_3_out_uop_mem_cmd : issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exc_cause = _T_264 ? issue_slots_4_out_uop_exc_cause : _T_263 ? issue_slots_3_out_uop_exc_cause : issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exception = _T_264 ? issue_slots_4_out_uop_exception : _T_263 ? issue_slots_3_out_uop_exception : issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stale_pdst = _T_264 ? issue_slots_4_out_uop_stale_pdst : _T_263 ? issue_slots_3_out_uop_stale_pdst : issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred_busy = _T_264 ? issue_slots_4_out_uop_ppred_busy : _T_263 ? issue_slots_3_out_uop_ppred_busy : issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3_busy = _T_264 ? issue_slots_4_out_uop_prs3_busy : _T_263 ? issue_slots_3_out_uop_prs3_busy : issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2_busy = _T_264 ? issue_slots_4_out_uop_prs2_busy : _T_263 ? issue_slots_3_out_uop_prs2_busy : issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1_busy = _T_264 ? issue_slots_4_out_uop_prs1_busy : _T_263 ? issue_slots_3_out_uop_prs1_busy : issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred = _T_264 ? issue_slots_4_out_uop_ppred : _T_263 ? issue_slots_3_out_uop_ppred : issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3 = _T_264 ? issue_slots_4_out_uop_prs3 : _T_263 ? issue_slots_3_out_uop_prs3 : issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2 = _T_264 ? issue_slots_4_out_uop_prs2 : _T_263 ? issue_slots_3_out_uop_prs2 : issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1 = _T_264 ? issue_slots_4_out_uop_prs1 : _T_263 ? issue_slots_3_out_uop_prs1 : issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pdst = _T_264 ? issue_slots_4_out_uop_pdst : _T_263 ? issue_slots_3_out_uop_pdst : issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rxq_idx = _T_264 ? issue_slots_4_out_uop_rxq_idx : _T_263 ? issue_slots_3_out_uop_rxq_idx : issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stq_idx = _T_264 ? issue_slots_4_out_uop_stq_idx : _T_263 ? issue_slots_3_out_uop_stq_idx : issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldq_idx = _T_264 ? issue_slots_4_out_uop_ldq_idx : _T_263 ? issue_slots_3_out_uop_ldq_idx : issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rob_idx = _T_264 ? issue_slots_4_out_uop_rob_idx : _T_263 ? issue_slots_3_out_uop_rob_idx : issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_vec = _T_264 ? issue_slots_4_out_uop_fp_ctrl_vec : _T_263 ? issue_slots_3_out_uop_fp_ctrl_vec : issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wflags = _T_264 ? issue_slots_4_out_uop_fp_ctrl_wflags : _T_263 ? issue_slots_3_out_uop_fp_ctrl_wflags : issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_sqrt = _T_264 ? issue_slots_4_out_uop_fp_ctrl_sqrt : _T_263 ? issue_slots_3_out_uop_fp_ctrl_sqrt : issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_div = _T_264 ? issue_slots_4_out_uop_fp_ctrl_div : _T_263 ? issue_slots_3_out_uop_fp_ctrl_div : issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fma = _T_264 ? issue_slots_4_out_uop_fp_ctrl_fma : _T_263 ? issue_slots_3_out_uop_fp_ctrl_fma : issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fastpipe = _T_264 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : _T_263 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_toint = _T_264 ? issue_slots_4_out_uop_fp_ctrl_toint : _T_263 ? issue_slots_3_out_uop_fp_ctrl_toint : issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fromint = _T_264 ? issue_slots_4_out_uop_fp_ctrl_fromint : _T_263 ? issue_slots_3_out_uop_fp_ctrl_fromint : issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut = _T_264 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : _T_263 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn = _T_264 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : _T_263 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap23 = _T_264 ? issue_slots_4_out_uop_fp_ctrl_swap23 : _T_263 ? issue_slots_3_out_uop_fp_ctrl_swap23 : issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap12 = _T_264 ? issue_slots_4_out_uop_fp_ctrl_swap12 : _T_263 ? issue_slots_3_out_uop_fp_ctrl_swap12 : issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren3 = _T_264 ? issue_slots_4_out_uop_fp_ctrl_ren3 : _T_263 ? issue_slots_3_out_uop_fp_ctrl_ren3 : issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren2 = _T_264 ? issue_slots_4_out_uop_fp_ctrl_ren2 : _T_263 ? issue_slots_3_out_uop_fp_ctrl_ren2 : issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren1 = _T_264 ? issue_slots_4_out_uop_fp_ctrl_ren1 : _T_263 ? issue_slots_3_out_uop_fp_ctrl_ren1 : issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wen = _T_264 ? issue_slots_4_out_uop_fp_ctrl_wen : _T_263 ? issue_slots_3_out_uop_fp_ctrl_wen : issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ldst = _T_264 ? issue_slots_4_out_uop_fp_ctrl_ldst : _T_263 ? issue_slots_3_out_uop_fp_ctrl_ldst : issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op2_sel = _T_264 ? issue_slots_4_out_uop_op2_sel : _T_263 ? issue_slots_3_out_uop_op2_sel : issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op1_sel = _T_264 ? issue_slots_4_out_uop_op1_sel : _T_263 ? issue_slots_3_out_uop_op1_sel : issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_packed = _T_264 ? issue_slots_4_out_uop_imm_packed : _T_263 ? issue_slots_3_out_uop_imm_packed : issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pimm = _T_264 ? issue_slots_4_out_uop_pimm : _T_263 ? issue_slots_3_out_uop_pimm : issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_sel = _T_264 ? issue_slots_4_out_uop_imm_sel : _T_263 ? issue_slots_3_out_uop_imm_sel : issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_rename = _T_264 ? issue_slots_4_out_uop_imm_rename : _T_263 ? issue_slots_3_out_uop_imm_rename : issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_taken = _T_264 ? issue_slots_4_out_uop_taken : _T_263 ? issue_slots_3_out_uop_taken : issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pc_lob = _T_264 ? issue_slots_4_out_uop_pc_lob : _T_263 ? issue_slots_3_out_uop_pc_lob : issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_edge_inst = _T_264 ? issue_slots_4_out_uop_edge_inst : _T_263 ? issue_slots_3_out_uop_edge_inst : issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ftq_idx = _T_264 ? issue_slots_4_out_uop_ftq_idx : _T_263 ? issue_slots_3_out_uop_ftq_idx : issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_mov = _T_264 ? issue_slots_4_out_uop_is_mov : _T_263 ? issue_slots_3_out_uop_is_mov : issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rocc = _T_264 ? issue_slots_4_out_uop_is_rocc : _T_263 ? issue_slots_3_out_uop_is_rocc : issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sys_pc2epc = _T_264 ? issue_slots_4_out_uop_is_sys_pc2epc : _T_263 ? issue_slots_3_out_uop_is_sys_pc2epc : issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_eret = _T_264 ? issue_slots_4_out_uop_is_eret : _T_263 ? issue_slots_3_out_uop_is_eret : issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_amo = _T_264 ? issue_slots_4_out_uop_is_amo : _T_263 ? issue_slots_3_out_uop_is_amo : issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfence = _T_264 ? issue_slots_4_out_uop_is_sfence : _T_263 ? issue_slots_3_out_uop_is_sfence : issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fencei = _T_264 ? issue_slots_4_out_uop_is_fencei : _T_263 ? issue_slots_3_out_uop_is_fencei : issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fence = _T_264 ? issue_slots_4_out_uop_is_fence : _T_263 ? issue_slots_3_out_uop_is_fence : issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfb = _T_264 ? issue_slots_4_out_uop_is_sfb : _T_263 ? issue_slots_3_out_uop_is_sfb : issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_type = _T_264 ? issue_slots_4_out_uop_br_type : _T_263 ? issue_slots_3_out_uop_br_type : issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_tag = _T_264 ? issue_slots_4_out_uop_br_tag : _T_263 ? issue_slots_3_out_uop_br_tag : issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_mask = _T_264 ? issue_slots_4_out_uop_br_mask : _T_263 ? issue_slots_3_out_uop_br_mask : issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dis_col_sel = _T_264 ? issue_slots_4_out_uop_dis_col_sel : _T_263 ? issue_slots_3_out_uop_dis_col_sel : issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p3_bypass_hint = _T_264 ? issue_slots_4_out_uop_iw_p3_bypass_hint : _T_263 ? issue_slots_3_out_uop_iw_p3_bypass_hint : issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p2_bypass_hint = _T_264 ? issue_slots_4_out_uop_iw_p2_bypass_hint : _T_263 ? issue_slots_3_out_uop_iw_p2_bypass_hint : issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p1_bypass_hint = _T_264 ? issue_slots_4_out_uop_iw_p1_bypass_hint : _T_263 ? issue_slots_3_out_uop_iw_p1_bypass_hint : issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p2_speculative_child = _T_264 ? issue_slots_4_out_uop_iw_p2_speculative_child : _T_263 ? issue_slots_3_out_uop_iw_p2_speculative_child : issue_slots_2_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p1_speculative_child = _T_264 ? issue_slots_4_out_uop_iw_p1_speculative_child : _T_263 ? issue_slots_3_out_uop_iw_p1_speculative_child : issue_slots_2_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_issued = _T_264 ? issue_slots_4_out_uop_iw_issued : _T_263 ? issue_slots_3_out_uop_iw_issued : issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_0 = _T_264 ? issue_slots_4_out_uop_fu_code_0 : _T_263 ? issue_slots_3_out_uop_fu_code_0 : issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_1 = _T_264 ? issue_slots_4_out_uop_fu_code_1 : _T_263 ? issue_slots_3_out_uop_fu_code_1 : issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_2 = _T_264 ? issue_slots_4_out_uop_fu_code_2 : _T_263 ? issue_slots_3_out_uop_fu_code_2 : issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_3 = _T_264 ? issue_slots_4_out_uop_fu_code_3 : _T_263 ? issue_slots_3_out_uop_fu_code_3 : issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_4 = _T_264 ? issue_slots_4_out_uop_fu_code_4 : _T_263 ? issue_slots_3_out_uop_fu_code_4 : issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_5 = _T_264 ? issue_slots_4_out_uop_fu_code_5 : _T_263 ? issue_slots_3_out_uop_fu_code_5 : issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_6 = _T_264 ? issue_slots_4_out_uop_fu_code_6 : _T_263 ? issue_slots_3_out_uop_fu_code_6 : issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_7 = _T_264 ? issue_slots_4_out_uop_fu_code_7 : _T_263 ? issue_slots_3_out_uop_fu_code_7 : issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_8 = _T_264 ? issue_slots_4_out_uop_fu_code_8 : _T_263 ? issue_slots_3_out_uop_fu_code_8 : issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_9 = _T_264 ? issue_slots_4_out_uop_fu_code_9 : _T_263 ? issue_slots_3_out_uop_fu_code_9 : issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_0 = _T_264 ? issue_slots_4_out_uop_iq_type_0 : _T_263 ? issue_slots_3_out_uop_iq_type_0 : issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_1 = _T_264 ? issue_slots_4_out_uop_iq_type_1 : _T_263 ? issue_slots_3_out_uop_iq_type_1 : issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_2 = _T_264 ? issue_slots_4_out_uop_iq_type_2 : _T_263 ? issue_slots_3_out_uop_iq_type_2 : issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_3 = _T_264 ? issue_slots_4_out_uop_iq_type_3 : _T_263 ? issue_slots_3_out_uop_iq_type_3 : issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_pc = _T_264 ? issue_slots_4_out_uop_debug_pc : _T_263 ? issue_slots_3_out_uop_debug_pc : issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rvc = _T_264 ? issue_slots_4_out_uop_is_rvc : _T_263 ? issue_slots_3_out_uop_is_rvc : issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_inst = _T_264 ? issue_slots_4_out_uop_debug_inst : _T_263 ? issue_slots_3_out_uop_debug_inst : issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_inst = _T_264 ? issue_slots_4_out_uop_inst : _T_263 ? issue_slots_3_out_uop_inst : issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_1_clear_T = |shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23, :199:49] assign issue_slots_1_clear = _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_266 = shamts_oh_4 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_267 = shamts_oh_5 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_2_in_uop_valid = _T_267 ? issue_slots_5_will_be_valid : _T_266 ? issue_slots_4_will_be_valid : shamts_oh_3 == 3'h1 & issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_2_in_uop_bits_debug_tsrc = _T_267 ? issue_slots_5_out_uop_debug_tsrc : _T_266 ? issue_slots_4_out_uop_debug_tsrc : issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_fsrc = _T_267 ? issue_slots_5_out_uop_debug_fsrc : _T_266 ? issue_slots_4_out_uop_debug_fsrc : issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_xcpt_if = _T_267 ? issue_slots_5_out_uop_bp_xcpt_if : _T_266 ? issue_slots_4_out_uop_bp_xcpt_if : issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_debug_if = _T_267 ? issue_slots_5_out_uop_bp_debug_if : _T_266 ? issue_slots_4_out_uop_bp_debug_if : issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ma_if = _T_267 ? issue_slots_5_out_uop_xcpt_ma_if : _T_266 ? issue_slots_4_out_uop_xcpt_ma_if : issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ae_if = _T_267 ? issue_slots_5_out_uop_xcpt_ae_if : _T_266 ? issue_slots_4_out_uop_xcpt_ae_if : issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_pf_if = _T_267 ? issue_slots_5_out_uop_xcpt_pf_if : _T_266 ? issue_slots_4_out_uop_xcpt_pf_if : issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_typ = _T_267 ? issue_slots_5_out_uop_fp_typ : _T_266 ? issue_slots_4_out_uop_fp_typ : issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_rm = _T_267 ? issue_slots_5_out_uop_fp_rm : _T_266 ? issue_slots_4_out_uop_fp_rm : issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_val = _T_267 ? issue_slots_5_out_uop_fp_val : _T_266 ? issue_slots_4_out_uop_fp_val : issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_op = _T_267 ? issue_slots_5_out_uop_fcn_op : _T_266 ? issue_slots_4_out_uop_fcn_op : issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_dw = _T_267 ? issue_slots_5_out_uop_fcn_dw : _T_266 ? issue_slots_4_out_uop_fcn_dw : issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_frs3_en = _T_267 ? issue_slots_5_out_uop_frs3_en : _T_266 ? issue_slots_4_out_uop_frs3_en : issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2_rtype = _T_267 ? issue_slots_5_out_uop_lrs2_rtype : _T_266 ? issue_slots_4_out_uop_lrs2_rtype : issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1_rtype = _T_267 ? issue_slots_5_out_uop_lrs1_rtype : _T_266 ? issue_slots_4_out_uop_lrs1_rtype : issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dst_rtype = _T_267 ? issue_slots_5_out_uop_dst_rtype : _T_266 ? issue_slots_4_out_uop_dst_rtype : issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs3 = _T_267 ? issue_slots_5_out_uop_lrs3 : _T_266 ? issue_slots_4_out_uop_lrs3 : issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2 = _T_267 ? issue_slots_5_out_uop_lrs2 : _T_266 ? issue_slots_4_out_uop_lrs2 : issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1 = _T_267 ? issue_slots_5_out_uop_lrs1 : _T_266 ? issue_slots_4_out_uop_lrs1 : issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst = _T_267 ? issue_slots_5_out_uop_ldst : _T_266 ? issue_slots_4_out_uop_ldst : issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst_is_rs1 = _T_267 ? issue_slots_5_out_uop_ldst_is_rs1 : _T_266 ? issue_slots_4_out_uop_ldst_is_rs1 : issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_csr_cmd = _T_267 ? issue_slots_5_out_uop_csr_cmd : _T_266 ? issue_slots_4_out_uop_csr_cmd : issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_flush_on_commit = _T_267 ? issue_slots_5_out_uop_flush_on_commit : _T_266 ? issue_slots_4_out_uop_flush_on_commit : issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_unique = _T_267 ? issue_slots_5_out_uop_is_unique : _T_266 ? issue_slots_4_out_uop_is_unique : issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_stq = _T_267 ? issue_slots_5_out_uop_uses_stq : _T_266 ? issue_slots_4_out_uop_uses_stq : issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_ldq = _T_267 ? issue_slots_5_out_uop_uses_ldq : _T_266 ? issue_slots_4_out_uop_uses_ldq : issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_signed = _T_267 ? issue_slots_5_out_uop_mem_signed : _T_266 ? issue_slots_4_out_uop_mem_signed : issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_size = _T_267 ? issue_slots_5_out_uop_mem_size : _T_266 ? issue_slots_4_out_uop_mem_size : issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_cmd = _T_267 ? issue_slots_5_out_uop_mem_cmd : _T_266 ? issue_slots_4_out_uop_mem_cmd : issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exc_cause = _T_267 ? issue_slots_5_out_uop_exc_cause : _T_266 ? issue_slots_4_out_uop_exc_cause : issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exception = _T_267 ? issue_slots_5_out_uop_exception : _T_266 ? issue_slots_4_out_uop_exception : issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stale_pdst = _T_267 ? issue_slots_5_out_uop_stale_pdst : _T_266 ? issue_slots_4_out_uop_stale_pdst : issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred_busy = _T_267 ? issue_slots_5_out_uop_ppred_busy : _T_266 ? issue_slots_4_out_uop_ppred_busy : issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3_busy = _T_267 ? issue_slots_5_out_uop_prs3_busy : _T_266 ? issue_slots_4_out_uop_prs3_busy : issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2_busy = _T_267 ? issue_slots_5_out_uop_prs2_busy : _T_266 ? issue_slots_4_out_uop_prs2_busy : issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1_busy = _T_267 ? issue_slots_5_out_uop_prs1_busy : _T_266 ? issue_slots_4_out_uop_prs1_busy : issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred = _T_267 ? issue_slots_5_out_uop_ppred : _T_266 ? issue_slots_4_out_uop_ppred : issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3 = _T_267 ? issue_slots_5_out_uop_prs3 : _T_266 ? issue_slots_4_out_uop_prs3 : issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2 = _T_267 ? issue_slots_5_out_uop_prs2 : _T_266 ? issue_slots_4_out_uop_prs2 : issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1 = _T_267 ? issue_slots_5_out_uop_prs1 : _T_266 ? issue_slots_4_out_uop_prs1 : issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pdst = _T_267 ? issue_slots_5_out_uop_pdst : _T_266 ? issue_slots_4_out_uop_pdst : issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rxq_idx = _T_267 ? issue_slots_5_out_uop_rxq_idx : _T_266 ? issue_slots_4_out_uop_rxq_idx : issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stq_idx = _T_267 ? issue_slots_5_out_uop_stq_idx : _T_266 ? issue_slots_4_out_uop_stq_idx : issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldq_idx = _T_267 ? issue_slots_5_out_uop_ldq_idx : _T_266 ? issue_slots_4_out_uop_ldq_idx : issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rob_idx = _T_267 ? issue_slots_5_out_uop_rob_idx : _T_266 ? issue_slots_4_out_uop_rob_idx : issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_vec = _T_267 ? issue_slots_5_out_uop_fp_ctrl_vec : _T_266 ? issue_slots_4_out_uop_fp_ctrl_vec : issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wflags = _T_267 ? issue_slots_5_out_uop_fp_ctrl_wflags : _T_266 ? issue_slots_4_out_uop_fp_ctrl_wflags : issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_sqrt = _T_267 ? issue_slots_5_out_uop_fp_ctrl_sqrt : _T_266 ? issue_slots_4_out_uop_fp_ctrl_sqrt : issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_div = _T_267 ? issue_slots_5_out_uop_fp_ctrl_div : _T_266 ? issue_slots_4_out_uop_fp_ctrl_div : issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fma = _T_267 ? issue_slots_5_out_uop_fp_ctrl_fma : _T_266 ? issue_slots_4_out_uop_fp_ctrl_fma : issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fastpipe = _T_267 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : _T_266 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_toint = _T_267 ? issue_slots_5_out_uop_fp_ctrl_toint : _T_266 ? issue_slots_4_out_uop_fp_ctrl_toint : issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fromint = _T_267 ? issue_slots_5_out_uop_fp_ctrl_fromint : _T_266 ? issue_slots_4_out_uop_fp_ctrl_fromint : issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut = _T_267 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : _T_266 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn = _T_267 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : _T_266 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap23 = _T_267 ? issue_slots_5_out_uop_fp_ctrl_swap23 : _T_266 ? issue_slots_4_out_uop_fp_ctrl_swap23 : issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap12 = _T_267 ? issue_slots_5_out_uop_fp_ctrl_swap12 : _T_266 ? issue_slots_4_out_uop_fp_ctrl_swap12 : issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren3 = _T_267 ? issue_slots_5_out_uop_fp_ctrl_ren3 : _T_266 ? issue_slots_4_out_uop_fp_ctrl_ren3 : issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren2 = _T_267 ? issue_slots_5_out_uop_fp_ctrl_ren2 : _T_266 ? issue_slots_4_out_uop_fp_ctrl_ren2 : issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren1 = _T_267 ? issue_slots_5_out_uop_fp_ctrl_ren1 : _T_266 ? issue_slots_4_out_uop_fp_ctrl_ren1 : issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wen = _T_267 ? issue_slots_5_out_uop_fp_ctrl_wen : _T_266 ? issue_slots_4_out_uop_fp_ctrl_wen : issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ldst = _T_267 ? issue_slots_5_out_uop_fp_ctrl_ldst : _T_266 ? issue_slots_4_out_uop_fp_ctrl_ldst : issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op2_sel = _T_267 ? issue_slots_5_out_uop_op2_sel : _T_266 ? issue_slots_4_out_uop_op2_sel : issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op1_sel = _T_267 ? issue_slots_5_out_uop_op1_sel : _T_266 ? issue_slots_4_out_uop_op1_sel : issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_packed = _T_267 ? issue_slots_5_out_uop_imm_packed : _T_266 ? issue_slots_4_out_uop_imm_packed : issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pimm = _T_267 ? issue_slots_5_out_uop_pimm : _T_266 ? issue_slots_4_out_uop_pimm : issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_sel = _T_267 ? issue_slots_5_out_uop_imm_sel : _T_266 ? issue_slots_4_out_uop_imm_sel : issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_rename = _T_267 ? issue_slots_5_out_uop_imm_rename : _T_266 ? issue_slots_4_out_uop_imm_rename : issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_taken = _T_267 ? issue_slots_5_out_uop_taken : _T_266 ? issue_slots_4_out_uop_taken : issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pc_lob = _T_267 ? issue_slots_5_out_uop_pc_lob : _T_266 ? issue_slots_4_out_uop_pc_lob : issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_edge_inst = _T_267 ? issue_slots_5_out_uop_edge_inst : _T_266 ? issue_slots_4_out_uop_edge_inst : issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ftq_idx = _T_267 ? issue_slots_5_out_uop_ftq_idx : _T_266 ? issue_slots_4_out_uop_ftq_idx : issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_mov = _T_267 ? issue_slots_5_out_uop_is_mov : _T_266 ? issue_slots_4_out_uop_is_mov : issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rocc = _T_267 ? issue_slots_5_out_uop_is_rocc : _T_266 ? issue_slots_4_out_uop_is_rocc : issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sys_pc2epc = _T_267 ? issue_slots_5_out_uop_is_sys_pc2epc : _T_266 ? issue_slots_4_out_uop_is_sys_pc2epc : issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_eret = _T_267 ? issue_slots_5_out_uop_is_eret : _T_266 ? issue_slots_4_out_uop_is_eret : issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_amo = _T_267 ? issue_slots_5_out_uop_is_amo : _T_266 ? issue_slots_4_out_uop_is_amo : issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfence = _T_267 ? issue_slots_5_out_uop_is_sfence : _T_266 ? issue_slots_4_out_uop_is_sfence : issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fencei = _T_267 ? issue_slots_5_out_uop_is_fencei : _T_266 ? issue_slots_4_out_uop_is_fencei : issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fence = _T_267 ? issue_slots_5_out_uop_is_fence : _T_266 ? issue_slots_4_out_uop_is_fence : issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfb = _T_267 ? issue_slots_5_out_uop_is_sfb : _T_266 ? issue_slots_4_out_uop_is_sfb : issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_type = _T_267 ? issue_slots_5_out_uop_br_type : _T_266 ? issue_slots_4_out_uop_br_type : issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_tag = _T_267 ? issue_slots_5_out_uop_br_tag : _T_266 ? issue_slots_4_out_uop_br_tag : issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_mask = _T_267 ? issue_slots_5_out_uop_br_mask : _T_266 ? issue_slots_4_out_uop_br_mask : issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dis_col_sel = _T_267 ? issue_slots_5_out_uop_dis_col_sel : _T_266 ? issue_slots_4_out_uop_dis_col_sel : issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p3_bypass_hint = _T_267 ? issue_slots_5_out_uop_iw_p3_bypass_hint : _T_266 ? issue_slots_4_out_uop_iw_p3_bypass_hint : issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p2_bypass_hint = _T_267 ? issue_slots_5_out_uop_iw_p2_bypass_hint : _T_266 ? issue_slots_4_out_uop_iw_p2_bypass_hint : issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p1_bypass_hint = _T_267 ? issue_slots_5_out_uop_iw_p1_bypass_hint : _T_266 ? issue_slots_4_out_uop_iw_p1_bypass_hint : issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p2_speculative_child = _T_267 ? issue_slots_5_out_uop_iw_p2_speculative_child : _T_266 ? issue_slots_4_out_uop_iw_p2_speculative_child : issue_slots_3_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p1_speculative_child = _T_267 ? issue_slots_5_out_uop_iw_p1_speculative_child : _T_266 ? issue_slots_4_out_uop_iw_p1_speculative_child : issue_slots_3_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_issued = _T_267 ? issue_slots_5_out_uop_iw_issued : _T_266 ? issue_slots_4_out_uop_iw_issued : issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_0 = _T_267 ? issue_slots_5_out_uop_fu_code_0 : _T_266 ? issue_slots_4_out_uop_fu_code_0 : issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_1 = _T_267 ? issue_slots_5_out_uop_fu_code_1 : _T_266 ? issue_slots_4_out_uop_fu_code_1 : issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_2 = _T_267 ? issue_slots_5_out_uop_fu_code_2 : _T_266 ? issue_slots_4_out_uop_fu_code_2 : issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_3 = _T_267 ? issue_slots_5_out_uop_fu_code_3 : _T_266 ? issue_slots_4_out_uop_fu_code_3 : issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_4 = _T_267 ? issue_slots_5_out_uop_fu_code_4 : _T_266 ? issue_slots_4_out_uop_fu_code_4 : issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_5 = _T_267 ? issue_slots_5_out_uop_fu_code_5 : _T_266 ? issue_slots_4_out_uop_fu_code_5 : issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_6 = _T_267 ? issue_slots_5_out_uop_fu_code_6 : _T_266 ? issue_slots_4_out_uop_fu_code_6 : issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_7 = _T_267 ? issue_slots_5_out_uop_fu_code_7 : _T_266 ? issue_slots_4_out_uop_fu_code_7 : issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_8 = _T_267 ? issue_slots_5_out_uop_fu_code_8 : _T_266 ? issue_slots_4_out_uop_fu_code_8 : issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_9 = _T_267 ? issue_slots_5_out_uop_fu_code_9 : _T_266 ? issue_slots_4_out_uop_fu_code_9 : issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_0 = _T_267 ? issue_slots_5_out_uop_iq_type_0 : _T_266 ? issue_slots_4_out_uop_iq_type_0 : issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_1 = _T_267 ? issue_slots_5_out_uop_iq_type_1 : _T_266 ? issue_slots_4_out_uop_iq_type_1 : issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_2 = _T_267 ? issue_slots_5_out_uop_iq_type_2 : _T_266 ? issue_slots_4_out_uop_iq_type_2 : issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_3 = _T_267 ? issue_slots_5_out_uop_iq_type_3 : _T_266 ? issue_slots_4_out_uop_iq_type_3 : issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_pc = _T_267 ? issue_slots_5_out_uop_debug_pc : _T_266 ? issue_slots_4_out_uop_debug_pc : issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rvc = _T_267 ? issue_slots_5_out_uop_is_rvc : _T_266 ? issue_slots_4_out_uop_is_rvc : issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_inst = _T_267 ? issue_slots_5_out_uop_debug_inst : _T_266 ? issue_slots_4_out_uop_debug_inst : issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_inst = _T_267 ? issue_slots_5_out_uop_inst : _T_266 ? issue_slots_4_out_uop_inst : issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_2_clear_T = |shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23, :199:49] assign issue_slots_2_clear = _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_269 = shamts_oh_5 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_270 = shamts_oh_6 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_3_in_uop_valid = _T_270 ? issue_slots_6_will_be_valid : _T_269 ? issue_slots_5_will_be_valid : shamts_oh_4 == 3'h1 & issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_3_in_uop_bits_debug_tsrc = _T_270 ? issue_slots_6_out_uop_debug_tsrc : _T_269 ? issue_slots_5_out_uop_debug_tsrc : issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_fsrc = _T_270 ? issue_slots_6_out_uop_debug_fsrc : _T_269 ? issue_slots_5_out_uop_debug_fsrc : issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_xcpt_if = _T_270 ? issue_slots_6_out_uop_bp_xcpt_if : _T_269 ? issue_slots_5_out_uop_bp_xcpt_if : issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_debug_if = _T_270 ? issue_slots_6_out_uop_bp_debug_if : _T_269 ? issue_slots_5_out_uop_bp_debug_if : issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ma_if = _T_270 ? issue_slots_6_out_uop_xcpt_ma_if : _T_269 ? issue_slots_5_out_uop_xcpt_ma_if : issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ae_if = _T_270 ? issue_slots_6_out_uop_xcpt_ae_if : _T_269 ? issue_slots_5_out_uop_xcpt_ae_if : issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_pf_if = _T_270 ? issue_slots_6_out_uop_xcpt_pf_if : _T_269 ? issue_slots_5_out_uop_xcpt_pf_if : issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_typ = _T_270 ? issue_slots_6_out_uop_fp_typ : _T_269 ? issue_slots_5_out_uop_fp_typ : issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_rm = _T_270 ? issue_slots_6_out_uop_fp_rm : _T_269 ? issue_slots_5_out_uop_fp_rm : issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_val = _T_270 ? issue_slots_6_out_uop_fp_val : _T_269 ? issue_slots_5_out_uop_fp_val : issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_op = _T_270 ? issue_slots_6_out_uop_fcn_op : _T_269 ? issue_slots_5_out_uop_fcn_op : issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_dw = _T_270 ? issue_slots_6_out_uop_fcn_dw : _T_269 ? issue_slots_5_out_uop_fcn_dw : issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_frs3_en = _T_270 ? issue_slots_6_out_uop_frs3_en : _T_269 ? issue_slots_5_out_uop_frs3_en : issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2_rtype = _T_270 ? issue_slots_6_out_uop_lrs2_rtype : _T_269 ? issue_slots_5_out_uop_lrs2_rtype : issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1_rtype = _T_270 ? issue_slots_6_out_uop_lrs1_rtype : _T_269 ? issue_slots_5_out_uop_lrs1_rtype : issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dst_rtype = _T_270 ? issue_slots_6_out_uop_dst_rtype : _T_269 ? issue_slots_5_out_uop_dst_rtype : issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs3 = _T_270 ? issue_slots_6_out_uop_lrs3 : _T_269 ? issue_slots_5_out_uop_lrs3 : issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2 = _T_270 ? issue_slots_6_out_uop_lrs2 : _T_269 ? issue_slots_5_out_uop_lrs2 : issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1 = _T_270 ? issue_slots_6_out_uop_lrs1 : _T_269 ? issue_slots_5_out_uop_lrs1 : issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst = _T_270 ? issue_slots_6_out_uop_ldst : _T_269 ? issue_slots_5_out_uop_ldst : issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst_is_rs1 = _T_270 ? issue_slots_6_out_uop_ldst_is_rs1 : _T_269 ? issue_slots_5_out_uop_ldst_is_rs1 : issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_csr_cmd = _T_270 ? issue_slots_6_out_uop_csr_cmd : _T_269 ? issue_slots_5_out_uop_csr_cmd : issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_flush_on_commit = _T_270 ? issue_slots_6_out_uop_flush_on_commit : _T_269 ? issue_slots_5_out_uop_flush_on_commit : issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_unique = _T_270 ? issue_slots_6_out_uop_is_unique : _T_269 ? issue_slots_5_out_uop_is_unique : issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_stq = _T_270 ? issue_slots_6_out_uop_uses_stq : _T_269 ? issue_slots_5_out_uop_uses_stq : issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_ldq = _T_270 ? issue_slots_6_out_uop_uses_ldq : _T_269 ? issue_slots_5_out_uop_uses_ldq : issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_signed = _T_270 ? issue_slots_6_out_uop_mem_signed : _T_269 ? issue_slots_5_out_uop_mem_signed : issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_size = _T_270 ? issue_slots_6_out_uop_mem_size : _T_269 ? issue_slots_5_out_uop_mem_size : issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_cmd = _T_270 ? issue_slots_6_out_uop_mem_cmd : _T_269 ? issue_slots_5_out_uop_mem_cmd : issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exc_cause = _T_270 ? issue_slots_6_out_uop_exc_cause : _T_269 ? issue_slots_5_out_uop_exc_cause : issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exception = _T_270 ? issue_slots_6_out_uop_exception : _T_269 ? issue_slots_5_out_uop_exception : issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stale_pdst = _T_270 ? issue_slots_6_out_uop_stale_pdst : _T_269 ? issue_slots_5_out_uop_stale_pdst : issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred_busy = _T_270 ? issue_slots_6_out_uop_ppred_busy : _T_269 ? issue_slots_5_out_uop_ppred_busy : issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3_busy = _T_270 ? issue_slots_6_out_uop_prs3_busy : _T_269 ? issue_slots_5_out_uop_prs3_busy : issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2_busy = _T_270 ? issue_slots_6_out_uop_prs2_busy : _T_269 ? issue_slots_5_out_uop_prs2_busy : issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1_busy = _T_270 ? issue_slots_6_out_uop_prs1_busy : _T_269 ? issue_slots_5_out_uop_prs1_busy : issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred = _T_270 ? issue_slots_6_out_uop_ppred : _T_269 ? issue_slots_5_out_uop_ppred : issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3 = _T_270 ? issue_slots_6_out_uop_prs3 : _T_269 ? issue_slots_5_out_uop_prs3 : issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2 = _T_270 ? issue_slots_6_out_uop_prs2 : _T_269 ? issue_slots_5_out_uop_prs2 : issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1 = _T_270 ? issue_slots_6_out_uop_prs1 : _T_269 ? issue_slots_5_out_uop_prs1 : issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pdst = _T_270 ? issue_slots_6_out_uop_pdst : _T_269 ? issue_slots_5_out_uop_pdst : issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rxq_idx = _T_270 ? issue_slots_6_out_uop_rxq_idx : _T_269 ? issue_slots_5_out_uop_rxq_idx : issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stq_idx = _T_270 ? issue_slots_6_out_uop_stq_idx : _T_269 ? issue_slots_5_out_uop_stq_idx : issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldq_idx = _T_270 ? issue_slots_6_out_uop_ldq_idx : _T_269 ? issue_slots_5_out_uop_ldq_idx : issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rob_idx = _T_270 ? issue_slots_6_out_uop_rob_idx : _T_269 ? issue_slots_5_out_uop_rob_idx : issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_vec = _T_270 ? issue_slots_6_out_uop_fp_ctrl_vec : _T_269 ? issue_slots_5_out_uop_fp_ctrl_vec : issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wflags = _T_270 ? issue_slots_6_out_uop_fp_ctrl_wflags : _T_269 ? issue_slots_5_out_uop_fp_ctrl_wflags : issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_sqrt = _T_270 ? issue_slots_6_out_uop_fp_ctrl_sqrt : _T_269 ? issue_slots_5_out_uop_fp_ctrl_sqrt : issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_div = _T_270 ? issue_slots_6_out_uop_fp_ctrl_div : _T_269 ? issue_slots_5_out_uop_fp_ctrl_div : issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fma = _T_270 ? issue_slots_6_out_uop_fp_ctrl_fma : _T_269 ? issue_slots_5_out_uop_fp_ctrl_fma : issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fastpipe = _T_270 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : _T_269 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_toint = _T_270 ? issue_slots_6_out_uop_fp_ctrl_toint : _T_269 ? issue_slots_5_out_uop_fp_ctrl_toint : issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fromint = _T_270 ? issue_slots_6_out_uop_fp_ctrl_fromint : _T_269 ? issue_slots_5_out_uop_fp_ctrl_fromint : issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut = _T_270 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : _T_269 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn = _T_270 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : _T_269 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap23 = _T_270 ? issue_slots_6_out_uop_fp_ctrl_swap23 : _T_269 ? issue_slots_5_out_uop_fp_ctrl_swap23 : issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap12 = _T_270 ? issue_slots_6_out_uop_fp_ctrl_swap12 : _T_269 ? issue_slots_5_out_uop_fp_ctrl_swap12 : issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren3 = _T_270 ? issue_slots_6_out_uop_fp_ctrl_ren3 : _T_269 ? issue_slots_5_out_uop_fp_ctrl_ren3 : issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren2 = _T_270 ? issue_slots_6_out_uop_fp_ctrl_ren2 : _T_269 ? issue_slots_5_out_uop_fp_ctrl_ren2 : issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren1 = _T_270 ? issue_slots_6_out_uop_fp_ctrl_ren1 : _T_269 ? issue_slots_5_out_uop_fp_ctrl_ren1 : issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wen = _T_270 ? issue_slots_6_out_uop_fp_ctrl_wen : _T_269 ? issue_slots_5_out_uop_fp_ctrl_wen : issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ldst = _T_270 ? issue_slots_6_out_uop_fp_ctrl_ldst : _T_269 ? issue_slots_5_out_uop_fp_ctrl_ldst : issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op2_sel = _T_270 ? issue_slots_6_out_uop_op2_sel : _T_269 ? issue_slots_5_out_uop_op2_sel : issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op1_sel = _T_270 ? issue_slots_6_out_uop_op1_sel : _T_269 ? issue_slots_5_out_uop_op1_sel : issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_packed = _T_270 ? issue_slots_6_out_uop_imm_packed : _T_269 ? issue_slots_5_out_uop_imm_packed : issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pimm = _T_270 ? issue_slots_6_out_uop_pimm : _T_269 ? issue_slots_5_out_uop_pimm : issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_sel = _T_270 ? issue_slots_6_out_uop_imm_sel : _T_269 ? issue_slots_5_out_uop_imm_sel : issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_rename = _T_270 ? issue_slots_6_out_uop_imm_rename : _T_269 ? issue_slots_5_out_uop_imm_rename : issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_taken = _T_270 ? issue_slots_6_out_uop_taken : _T_269 ? issue_slots_5_out_uop_taken : issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pc_lob = _T_270 ? issue_slots_6_out_uop_pc_lob : _T_269 ? issue_slots_5_out_uop_pc_lob : issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_edge_inst = _T_270 ? issue_slots_6_out_uop_edge_inst : _T_269 ? issue_slots_5_out_uop_edge_inst : issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ftq_idx = _T_270 ? issue_slots_6_out_uop_ftq_idx : _T_269 ? issue_slots_5_out_uop_ftq_idx : issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_mov = _T_270 ? issue_slots_6_out_uop_is_mov : _T_269 ? issue_slots_5_out_uop_is_mov : issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rocc = _T_270 ? issue_slots_6_out_uop_is_rocc : _T_269 ? issue_slots_5_out_uop_is_rocc : issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sys_pc2epc = _T_270 ? issue_slots_6_out_uop_is_sys_pc2epc : _T_269 ? issue_slots_5_out_uop_is_sys_pc2epc : issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_eret = _T_270 ? issue_slots_6_out_uop_is_eret : _T_269 ? issue_slots_5_out_uop_is_eret : issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_amo = _T_270 ? issue_slots_6_out_uop_is_amo : _T_269 ? issue_slots_5_out_uop_is_amo : issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfence = _T_270 ? issue_slots_6_out_uop_is_sfence : _T_269 ? issue_slots_5_out_uop_is_sfence : issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fencei = _T_270 ? issue_slots_6_out_uop_is_fencei : _T_269 ? issue_slots_5_out_uop_is_fencei : issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fence = _T_270 ? issue_slots_6_out_uop_is_fence : _T_269 ? issue_slots_5_out_uop_is_fence : issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfb = _T_270 ? issue_slots_6_out_uop_is_sfb : _T_269 ? issue_slots_5_out_uop_is_sfb : issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_type = _T_270 ? issue_slots_6_out_uop_br_type : _T_269 ? issue_slots_5_out_uop_br_type : issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_tag = _T_270 ? issue_slots_6_out_uop_br_tag : _T_269 ? issue_slots_5_out_uop_br_tag : issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_mask = _T_270 ? issue_slots_6_out_uop_br_mask : _T_269 ? issue_slots_5_out_uop_br_mask : issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dis_col_sel = _T_270 ? issue_slots_6_out_uop_dis_col_sel : _T_269 ? issue_slots_5_out_uop_dis_col_sel : issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p3_bypass_hint = _T_270 ? issue_slots_6_out_uop_iw_p3_bypass_hint : _T_269 ? issue_slots_5_out_uop_iw_p3_bypass_hint : issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p2_bypass_hint = _T_270 ? issue_slots_6_out_uop_iw_p2_bypass_hint : _T_269 ? issue_slots_5_out_uop_iw_p2_bypass_hint : issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p1_bypass_hint = _T_270 ? issue_slots_6_out_uop_iw_p1_bypass_hint : _T_269 ? issue_slots_5_out_uop_iw_p1_bypass_hint : issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p2_speculative_child = _T_270 ? issue_slots_6_out_uop_iw_p2_speculative_child : _T_269 ? issue_slots_5_out_uop_iw_p2_speculative_child : issue_slots_4_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p1_speculative_child = _T_270 ? issue_slots_6_out_uop_iw_p1_speculative_child : _T_269 ? issue_slots_5_out_uop_iw_p1_speculative_child : issue_slots_4_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_issued = _T_270 ? issue_slots_6_out_uop_iw_issued : _T_269 ? issue_slots_5_out_uop_iw_issued : issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_0 = _T_270 ? issue_slots_6_out_uop_fu_code_0 : _T_269 ? issue_slots_5_out_uop_fu_code_0 : issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_1 = _T_270 ? issue_slots_6_out_uop_fu_code_1 : _T_269 ? issue_slots_5_out_uop_fu_code_1 : issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_2 = _T_270 ? issue_slots_6_out_uop_fu_code_2 : _T_269 ? issue_slots_5_out_uop_fu_code_2 : issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_3 = _T_270 ? issue_slots_6_out_uop_fu_code_3 : _T_269 ? issue_slots_5_out_uop_fu_code_3 : issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_4 = _T_270 ? issue_slots_6_out_uop_fu_code_4 : _T_269 ? issue_slots_5_out_uop_fu_code_4 : issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_5 = _T_270 ? issue_slots_6_out_uop_fu_code_5 : _T_269 ? issue_slots_5_out_uop_fu_code_5 : issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_6 = _T_270 ? issue_slots_6_out_uop_fu_code_6 : _T_269 ? issue_slots_5_out_uop_fu_code_6 : issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_7 = _T_270 ? issue_slots_6_out_uop_fu_code_7 : _T_269 ? issue_slots_5_out_uop_fu_code_7 : issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_8 = _T_270 ? issue_slots_6_out_uop_fu_code_8 : _T_269 ? issue_slots_5_out_uop_fu_code_8 : issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_9 = _T_270 ? issue_slots_6_out_uop_fu_code_9 : _T_269 ? issue_slots_5_out_uop_fu_code_9 : issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_0 = _T_270 ? issue_slots_6_out_uop_iq_type_0 : _T_269 ? issue_slots_5_out_uop_iq_type_0 : issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_1 = _T_270 ? issue_slots_6_out_uop_iq_type_1 : _T_269 ? issue_slots_5_out_uop_iq_type_1 : issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_2 = _T_270 ? issue_slots_6_out_uop_iq_type_2 : _T_269 ? issue_slots_5_out_uop_iq_type_2 : issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_3 = _T_270 ? issue_slots_6_out_uop_iq_type_3 : _T_269 ? issue_slots_5_out_uop_iq_type_3 : issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_pc = _T_270 ? issue_slots_6_out_uop_debug_pc : _T_269 ? issue_slots_5_out_uop_debug_pc : issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rvc = _T_270 ? issue_slots_6_out_uop_is_rvc : _T_269 ? issue_slots_5_out_uop_is_rvc : issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_inst = _T_270 ? issue_slots_6_out_uop_debug_inst : _T_269 ? issue_slots_5_out_uop_debug_inst : issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_inst = _T_270 ? issue_slots_6_out_uop_inst : _T_269 ? issue_slots_5_out_uop_inst : issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_3_clear_T = |shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_3_clear = _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_272 = shamts_oh_6 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_273 = shamts_oh_7 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_4_in_uop_valid = _T_273 ? issue_slots_7_will_be_valid : _T_272 ? issue_slots_6_will_be_valid : shamts_oh_5 == 3'h1 & issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_4_in_uop_bits_debug_tsrc = _T_273 ? issue_slots_7_out_uop_debug_tsrc : _T_272 ? issue_slots_6_out_uop_debug_tsrc : issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_fsrc = _T_273 ? issue_slots_7_out_uop_debug_fsrc : _T_272 ? issue_slots_6_out_uop_debug_fsrc : issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_xcpt_if = _T_273 ? issue_slots_7_out_uop_bp_xcpt_if : _T_272 ? issue_slots_6_out_uop_bp_xcpt_if : issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_debug_if = _T_273 ? issue_slots_7_out_uop_bp_debug_if : _T_272 ? issue_slots_6_out_uop_bp_debug_if : issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ma_if = _T_273 ? issue_slots_7_out_uop_xcpt_ma_if : _T_272 ? issue_slots_6_out_uop_xcpt_ma_if : issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ae_if = _T_273 ? issue_slots_7_out_uop_xcpt_ae_if : _T_272 ? issue_slots_6_out_uop_xcpt_ae_if : issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_pf_if = _T_273 ? issue_slots_7_out_uop_xcpt_pf_if : _T_272 ? issue_slots_6_out_uop_xcpt_pf_if : issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_typ = _T_273 ? issue_slots_7_out_uop_fp_typ : _T_272 ? issue_slots_6_out_uop_fp_typ : issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_rm = _T_273 ? issue_slots_7_out_uop_fp_rm : _T_272 ? issue_slots_6_out_uop_fp_rm : issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_val = _T_273 ? issue_slots_7_out_uop_fp_val : _T_272 ? issue_slots_6_out_uop_fp_val : issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_op = _T_273 ? issue_slots_7_out_uop_fcn_op : _T_272 ? issue_slots_6_out_uop_fcn_op : issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_dw = _T_273 ? issue_slots_7_out_uop_fcn_dw : _T_272 ? issue_slots_6_out_uop_fcn_dw : issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_frs3_en = _T_273 ? issue_slots_7_out_uop_frs3_en : _T_272 ? issue_slots_6_out_uop_frs3_en : issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2_rtype = _T_273 ? issue_slots_7_out_uop_lrs2_rtype : _T_272 ? issue_slots_6_out_uop_lrs2_rtype : issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1_rtype = _T_273 ? issue_slots_7_out_uop_lrs1_rtype : _T_272 ? issue_slots_6_out_uop_lrs1_rtype : issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dst_rtype = _T_273 ? issue_slots_7_out_uop_dst_rtype : _T_272 ? issue_slots_6_out_uop_dst_rtype : issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs3 = _T_273 ? issue_slots_7_out_uop_lrs3 : _T_272 ? issue_slots_6_out_uop_lrs3 : issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2 = _T_273 ? issue_slots_7_out_uop_lrs2 : _T_272 ? issue_slots_6_out_uop_lrs2 : issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1 = _T_273 ? issue_slots_7_out_uop_lrs1 : _T_272 ? issue_slots_6_out_uop_lrs1 : issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst = _T_273 ? issue_slots_7_out_uop_ldst : _T_272 ? issue_slots_6_out_uop_ldst : issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst_is_rs1 = _T_273 ? issue_slots_7_out_uop_ldst_is_rs1 : _T_272 ? issue_slots_6_out_uop_ldst_is_rs1 : issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_csr_cmd = _T_273 ? issue_slots_7_out_uop_csr_cmd : _T_272 ? issue_slots_6_out_uop_csr_cmd : issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_flush_on_commit = _T_273 ? issue_slots_7_out_uop_flush_on_commit : _T_272 ? issue_slots_6_out_uop_flush_on_commit : issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_unique = _T_273 ? issue_slots_7_out_uop_is_unique : _T_272 ? issue_slots_6_out_uop_is_unique : issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_stq = _T_273 ? issue_slots_7_out_uop_uses_stq : _T_272 ? issue_slots_6_out_uop_uses_stq : issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_ldq = _T_273 ? issue_slots_7_out_uop_uses_ldq : _T_272 ? issue_slots_6_out_uop_uses_ldq : issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_signed = _T_273 ? issue_slots_7_out_uop_mem_signed : _T_272 ? issue_slots_6_out_uop_mem_signed : issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_size = _T_273 ? issue_slots_7_out_uop_mem_size : _T_272 ? issue_slots_6_out_uop_mem_size : issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_cmd = _T_273 ? issue_slots_7_out_uop_mem_cmd : _T_272 ? issue_slots_6_out_uop_mem_cmd : issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exc_cause = _T_273 ? issue_slots_7_out_uop_exc_cause : _T_272 ? issue_slots_6_out_uop_exc_cause : issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exception = _T_273 ? issue_slots_7_out_uop_exception : _T_272 ? issue_slots_6_out_uop_exception : issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stale_pdst = _T_273 ? issue_slots_7_out_uop_stale_pdst : _T_272 ? issue_slots_6_out_uop_stale_pdst : issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred_busy = _T_273 ? issue_slots_7_out_uop_ppred_busy : _T_272 ? issue_slots_6_out_uop_ppred_busy : issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3_busy = _T_273 ? issue_slots_7_out_uop_prs3_busy : _T_272 ? issue_slots_6_out_uop_prs3_busy : issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2_busy = _T_273 ? issue_slots_7_out_uop_prs2_busy : _T_272 ? issue_slots_6_out_uop_prs2_busy : issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1_busy = _T_273 ? issue_slots_7_out_uop_prs1_busy : _T_272 ? issue_slots_6_out_uop_prs1_busy : issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred = _T_273 ? issue_slots_7_out_uop_ppred : _T_272 ? issue_slots_6_out_uop_ppred : issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3 = _T_273 ? issue_slots_7_out_uop_prs3 : _T_272 ? issue_slots_6_out_uop_prs3 : issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2 = _T_273 ? issue_slots_7_out_uop_prs2 : _T_272 ? issue_slots_6_out_uop_prs2 : issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1 = _T_273 ? issue_slots_7_out_uop_prs1 : _T_272 ? issue_slots_6_out_uop_prs1 : issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pdst = _T_273 ? issue_slots_7_out_uop_pdst : _T_272 ? issue_slots_6_out_uop_pdst : issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rxq_idx = _T_273 ? issue_slots_7_out_uop_rxq_idx : _T_272 ? issue_slots_6_out_uop_rxq_idx : issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stq_idx = _T_273 ? issue_slots_7_out_uop_stq_idx : _T_272 ? issue_slots_6_out_uop_stq_idx : issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldq_idx = _T_273 ? issue_slots_7_out_uop_ldq_idx : _T_272 ? issue_slots_6_out_uop_ldq_idx : issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rob_idx = _T_273 ? issue_slots_7_out_uop_rob_idx : _T_272 ? issue_slots_6_out_uop_rob_idx : issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_vec = _T_273 ? issue_slots_7_out_uop_fp_ctrl_vec : _T_272 ? issue_slots_6_out_uop_fp_ctrl_vec : issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wflags = _T_273 ? issue_slots_7_out_uop_fp_ctrl_wflags : _T_272 ? issue_slots_6_out_uop_fp_ctrl_wflags : issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_sqrt = _T_273 ? issue_slots_7_out_uop_fp_ctrl_sqrt : _T_272 ? issue_slots_6_out_uop_fp_ctrl_sqrt : issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_div = _T_273 ? issue_slots_7_out_uop_fp_ctrl_div : _T_272 ? issue_slots_6_out_uop_fp_ctrl_div : issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fma = _T_273 ? issue_slots_7_out_uop_fp_ctrl_fma : _T_272 ? issue_slots_6_out_uop_fp_ctrl_fma : issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fastpipe = _T_273 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : _T_272 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_toint = _T_273 ? issue_slots_7_out_uop_fp_ctrl_toint : _T_272 ? issue_slots_6_out_uop_fp_ctrl_toint : issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fromint = _T_273 ? issue_slots_7_out_uop_fp_ctrl_fromint : _T_272 ? issue_slots_6_out_uop_fp_ctrl_fromint : issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut = _T_273 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : _T_272 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn = _T_273 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : _T_272 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap23 = _T_273 ? issue_slots_7_out_uop_fp_ctrl_swap23 : _T_272 ? issue_slots_6_out_uop_fp_ctrl_swap23 : issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap12 = _T_273 ? issue_slots_7_out_uop_fp_ctrl_swap12 : _T_272 ? issue_slots_6_out_uop_fp_ctrl_swap12 : issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren3 = _T_273 ? issue_slots_7_out_uop_fp_ctrl_ren3 : _T_272 ? issue_slots_6_out_uop_fp_ctrl_ren3 : issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren2 = _T_273 ? issue_slots_7_out_uop_fp_ctrl_ren2 : _T_272 ? issue_slots_6_out_uop_fp_ctrl_ren2 : issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren1 = _T_273 ? issue_slots_7_out_uop_fp_ctrl_ren1 : _T_272 ? issue_slots_6_out_uop_fp_ctrl_ren1 : issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wen = _T_273 ? issue_slots_7_out_uop_fp_ctrl_wen : _T_272 ? issue_slots_6_out_uop_fp_ctrl_wen : issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ldst = _T_273 ? issue_slots_7_out_uop_fp_ctrl_ldst : _T_272 ? issue_slots_6_out_uop_fp_ctrl_ldst : issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op2_sel = _T_273 ? issue_slots_7_out_uop_op2_sel : _T_272 ? issue_slots_6_out_uop_op2_sel : issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op1_sel = _T_273 ? issue_slots_7_out_uop_op1_sel : _T_272 ? issue_slots_6_out_uop_op1_sel : issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_packed = _T_273 ? issue_slots_7_out_uop_imm_packed : _T_272 ? issue_slots_6_out_uop_imm_packed : issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pimm = _T_273 ? issue_slots_7_out_uop_pimm : _T_272 ? issue_slots_6_out_uop_pimm : issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_sel = _T_273 ? issue_slots_7_out_uop_imm_sel : _T_272 ? issue_slots_6_out_uop_imm_sel : issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_rename = _T_273 ? issue_slots_7_out_uop_imm_rename : _T_272 ? issue_slots_6_out_uop_imm_rename : issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_taken = _T_273 ? issue_slots_7_out_uop_taken : _T_272 ? issue_slots_6_out_uop_taken : issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pc_lob = _T_273 ? issue_slots_7_out_uop_pc_lob : _T_272 ? issue_slots_6_out_uop_pc_lob : issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_edge_inst = _T_273 ? issue_slots_7_out_uop_edge_inst : _T_272 ? issue_slots_6_out_uop_edge_inst : issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ftq_idx = _T_273 ? issue_slots_7_out_uop_ftq_idx : _T_272 ? issue_slots_6_out_uop_ftq_idx : issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_mov = _T_273 ? issue_slots_7_out_uop_is_mov : _T_272 ? issue_slots_6_out_uop_is_mov : issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rocc = _T_273 ? issue_slots_7_out_uop_is_rocc : _T_272 ? issue_slots_6_out_uop_is_rocc : issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sys_pc2epc = _T_273 ? issue_slots_7_out_uop_is_sys_pc2epc : _T_272 ? issue_slots_6_out_uop_is_sys_pc2epc : issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_eret = _T_273 ? issue_slots_7_out_uop_is_eret : _T_272 ? issue_slots_6_out_uop_is_eret : issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_amo = _T_273 ? issue_slots_7_out_uop_is_amo : _T_272 ? issue_slots_6_out_uop_is_amo : issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfence = _T_273 ? issue_slots_7_out_uop_is_sfence : _T_272 ? issue_slots_6_out_uop_is_sfence : issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fencei = _T_273 ? issue_slots_7_out_uop_is_fencei : _T_272 ? issue_slots_6_out_uop_is_fencei : issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fence = _T_273 ? issue_slots_7_out_uop_is_fence : _T_272 ? issue_slots_6_out_uop_is_fence : issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfb = _T_273 ? issue_slots_7_out_uop_is_sfb : _T_272 ? issue_slots_6_out_uop_is_sfb : issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_type = _T_273 ? issue_slots_7_out_uop_br_type : _T_272 ? issue_slots_6_out_uop_br_type : issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_tag = _T_273 ? issue_slots_7_out_uop_br_tag : _T_272 ? issue_slots_6_out_uop_br_tag : issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_mask = _T_273 ? issue_slots_7_out_uop_br_mask : _T_272 ? issue_slots_6_out_uop_br_mask : issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dis_col_sel = _T_273 ? issue_slots_7_out_uop_dis_col_sel : _T_272 ? issue_slots_6_out_uop_dis_col_sel : issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p3_bypass_hint = _T_273 ? issue_slots_7_out_uop_iw_p3_bypass_hint : _T_272 ? issue_slots_6_out_uop_iw_p3_bypass_hint : issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p2_bypass_hint = _T_273 ? issue_slots_7_out_uop_iw_p2_bypass_hint : _T_272 ? issue_slots_6_out_uop_iw_p2_bypass_hint : issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p1_bypass_hint = _T_273 ? issue_slots_7_out_uop_iw_p1_bypass_hint : _T_272 ? issue_slots_6_out_uop_iw_p1_bypass_hint : issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p2_speculative_child = _T_273 ? issue_slots_7_out_uop_iw_p2_speculative_child : _T_272 ? issue_slots_6_out_uop_iw_p2_speculative_child : issue_slots_5_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p1_speculative_child = _T_273 ? issue_slots_7_out_uop_iw_p1_speculative_child : _T_272 ? issue_slots_6_out_uop_iw_p1_speculative_child : issue_slots_5_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_issued = _T_273 ? issue_slots_7_out_uop_iw_issued : _T_272 ? issue_slots_6_out_uop_iw_issued : issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_0 = _T_273 ? issue_slots_7_out_uop_fu_code_0 : _T_272 ? issue_slots_6_out_uop_fu_code_0 : issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_1 = _T_273 ? issue_slots_7_out_uop_fu_code_1 : _T_272 ? issue_slots_6_out_uop_fu_code_1 : issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_2 = _T_273 ? issue_slots_7_out_uop_fu_code_2 : _T_272 ? issue_slots_6_out_uop_fu_code_2 : issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_3 = _T_273 ? issue_slots_7_out_uop_fu_code_3 : _T_272 ? issue_slots_6_out_uop_fu_code_3 : issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_4 = _T_273 ? issue_slots_7_out_uop_fu_code_4 : _T_272 ? issue_slots_6_out_uop_fu_code_4 : issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_5 = _T_273 ? issue_slots_7_out_uop_fu_code_5 : _T_272 ? issue_slots_6_out_uop_fu_code_5 : issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_6 = _T_273 ? issue_slots_7_out_uop_fu_code_6 : _T_272 ? issue_slots_6_out_uop_fu_code_6 : issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_7 = _T_273 ? issue_slots_7_out_uop_fu_code_7 : _T_272 ? issue_slots_6_out_uop_fu_code_7 : issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_8 = _T_273 ? issue_slots_7_out_uop_fu_code_8 : _T_272 ? issue_slots_6_out_uop_fu_code_8 : issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_9 = _T_273 ? issue_slots_7_out_uop_fu_code_9 : _T_272 ? issue_slots_6_out_uop_fu_code_9 : issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_0 = _T_273 ? issue_slots_7_out_uop_iq_type_0 : _T_272 ? issue_slots_6_out_uop_iq_type_0 : issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_1 = _T_273 ? issue_slots_7_out_uop_iq_type_1 : _T_272 ? issue_slots_6_out_uop_iq_type_1 : issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_2 = _T_273 ? issue_slots_7_out_uop_iq_type_2 : _T_272 ? issue_slots_6_out_uop_iq_type_2 : issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_3 = _T_273 ? issue_slots_7_out_uop_iq_type_3 : _T_272 ? issue_slots_6_out_uop_iq_type_3 : issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_pc = _T_273 ? issue_slots_7_out_uop_debug_pc : _T_272 ? issue_slots_6_out_uop_debug_pc : issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rvc = _T_273 ? issue_slots_7_out_uop_is_rvc : _T_272 ? issue_slots_6_out_uop_is_rvc : issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_inst = _T_273 ? issue_slots_7_out_uop_debug_inst : _T_272 ? issue_slots_6_out_uop_debug_inst : issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_inst = _T_273 ? issue_slots_7_out_uop_inst : _T_272 ? issue_slots_6_out_uop_inst : issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_4_clear_T = |shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_4_clear = _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_275 = shamts_oh_7 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_276 = shamts_oh_8 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_5_in_uop_valid = _T_276 ? issue_slots_8_will_be_valid : _T_275 ? issue_slots_7_will_be_valid : shamts_oh_6 == 3'h1 & issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_5_in_uop_bits_debug_tsrc = _T_276 ? issue_slots_8_out_uop_debug_tsrc : _T_275 ? issue_slots_7_out_uop_debug_tsrc : issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_fsrc = _T_276 ? issue_slots_8_out_uop_debug_fsrc : _T_275 ? issue_slots_7_out_uop_debug_fsrc : issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_xcpt_if = _T_276 ? issue_slots_8_out_uop_bp_xcpt_if : _T_275 ? issue_slots_7_out_uop_bp_xcpt_if : issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_debug_if = _T_276 ? issue_slots_8_out_uop_bp_debug_if : _T_275 ? issue_slots_7_out_uop_bp_debug_if : issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ma_if = _T_276 ? issue_slots_8_out_uop_xcpt_ma_if : _T_275 ? issue_slots_7_out_uop_xcpt_ma_if : issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ae_if = _T_276 ? issue_slots_8_out_uop_xcpt_ae_if : _T_275 ? issue_slots_7_out_uop_xcpt_ae_if : issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_pf_if = _T_276 ? issue_slots_8_out_uop_xcpt_pf_if : _T_275 ? issue_slots_7_out_uop_xcpt_pf_if : issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_typ = _T_276 ? issue_slots_8_out_uop_fp_typ : _T_275 ? issue_slots_7_out_uop_fp_typ : issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_rm = _T_276 ? issue_slots_8_out_uop_fp_rm : _T_275 ? issue_slots_7_out_uop_fp_rm : issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_val = _T_276 ? issue_slots_8_out_uop_fp_val : _T_275 ? issue_slots_7_out_uop_fp_val : issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_op = _T_276 ? issue_slots_8_out_uop_fcn_op : _T_275 ? issue_slots_7_out_uop_fcn_op : issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_dw = _T_276 ? issue_slots_8_out_uop_fcn_dw : _T_275 ? issue_slots_7_out_uop_fcn_dw : issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_frs3_en = _T_276 ? issue_slots_8_out_uop_frs3_en : _T_275 ? issue_slots_7_out_uop_frs3_en : issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2_rtype = _T_276 ? issue_slots_8_out_uop_lrs2_rtype : _T_275 ? issue_slots_7_out_uop_lrs2_rtype : issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1_rtype = _T_276 ? issue_slots_8_out_uop_lrs1_rtype : _T_275 ? issue_slots_7_out_uop_lrs1_rtype : issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dst_rtype = _T_276 ? issue_slots_8_out_uop_dst_rtype : _T_275 ? issue_slots_7_out_uop_dst_rtype : issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs3 = _T_276 ? issue_slots_8_out_uop_lrs3 : _T_275 ? issue_slots_7_out_uop_lrs3 : issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2 = _T_276 ? issue_slots_8_out_uop_lrs2 : _T_275 ? issue_slots_7_out_uop_lrs2 : issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1 = _T_276 ? issue_slots_8_out_uop_lrs1 : _T_275 ? issue_slots_7_out_uop_lrs1 : issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst = _T_276 ? issue_slots_8_out_uop_ldst : _T_275 ? issue_slots_7_out_uop_ldst : issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst_is_rs1 = _T_276 ? issue_slots_8_out_uop_ldst_is_rs1 : _T_275 ? issue_slots_7_out_uop_ldst_is_rs1 : issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_csr_cmd = _T_276 ? issue_slots_8_out_uop_csr_cmd : _T_275 ? issue_slots_7_out_uop_csr_cmd : issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_flush_on_commit = _T_276 ? issue_slots_8_out_uop_flush_on_commit : _T_275 ? issue_slots_7_out_uop_flush_on_commit : issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_unique = _T_276 ? issue_slots_8_out_uop_is_unique : _T_275 ? issue_slots_7_out_uop_is_unique : issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_stq = _T_276 ? issue_slots_8_out_uop_uses_stq : _T_275 ? issue_slots_7_out_uop_uses_stq : issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_ldq = _T_276 ? issue_slots_8_out_uop_uses_ldq : _T_275 ? issue_slots_7_out_uop_uses_ldq : issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_signed = _T_276 ? issue_slots_8_out_uop_mem_signed : _T_275 ? issue_slots_7_out_uop_mem_signed : issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_size = _T_276 ? issue_slots_8_out_uop_mem_size : _T_275 ? issue_slots_7_out_uop_mem_size : issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_cmd = _T_276 ? issue_slots_8_out_uop_mem_cmd : _T_275 ? issue_slots_7_out_uop_mem_cmd : issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exc_cause = _T_276 ? issue_slots_8_out_uop_exc_cause : _T_275 ? issue_slots_7_out_uop_exc_cause : issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exception = _T_276 ? issue_slots_8_out_uop_exception : _T_275 ? issue_slots_7_out_uop_exception : issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stale_pdst = _T_276 ? issue_slots_8_out_uop_stale_pdst : _T_275 ? issue_slots_7_out_uop_stale_pdst : issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred_busy = _T_276 ? issue_slots_8_out_uop_ppred_busy : _T_275 ? issue_slots_7_out_uop_ppred_busy : issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3_busy = _T_276 ? issue_slots_8_out_uop_prs3_busy : _T_275 ? issue_slots_7_out_uop_prs3_busy : issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2_busy = _T_276 ? issue_slots_8_out_uop_prs2_busy : _T_275 ? issue_slots_7_out_uop_prs2_busy : issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1_busy = _T_276 ? issue_slots_8_out_uop_prs1_busy : _T_275 ? issue_slots_7_out_uop_prs1_busy : issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred = _T_276 ? issue_slots_8_out_uop_ppred : _T_275 ? issue_slots_7_out_uop_ppred : issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3 = _T_276 ? issue_slots_8_out_uop_prs3 : _T_275 ? issue_slots_7_out_uop_prs3 : issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2 = _T_276 ? issue_slots_8_out_uop_prs2 : _T_275 ? issue_slots_7_out_uop_prs2 : issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1 = _T_276 ? issue_slots_8_out_uop_prs1 : _T_275 ? issue_slots_7_out_uop_prs1 : issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pdst = _T_276 ? issue_slots_8_out_uop_pdst : _T_275 ? issue_slots_7_out_uop_pdst : issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rxq_idx = _T_276 ? issue_slots_8_out_uop_rxq_idx : _T_275 ? issue_slots_7_out_uop_rxq_idx : issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stq_idx = _T_276 ? issue_slots_8_out_uop_stq_idx : _T_275 ? issue_slots_7_out_uop_stq_idx : issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldq_idx = _T_276 ? issue_slots_8_out_uop_ldq_idx : _T_275 ? issue_slots_7_out_uop_ldq_idx : issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rob_idx = _T_276 ? issue_slots_8_out_uop_rob_idx : _T_275 ? issue_slots_7_out_uop_rob_idx : issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_vec = _T_276 ? issue_slots_8_out_uop_fp_ctrl_vec : _T_275 ? issue_slots_7_out_uop_fp_ctrl_vec : issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wflags = _T_276 ? issue_slots_8_out_uop_fp_ctrl_wflags : _T_275 ? issue_slots_7_out_uop_fp_ctrl_wflags : issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_sqrt = _T_276 ? issue_slots_8_out_uop_fp_ctrl_sqrt : _T_275 ? issue_slots_7_out_uop_fp_ctrl_sqrt : issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_div = _T_276 ? issue_slots_8_out_uop_fp_ctrl_div : _T_275 ? issue_slots_7_out_uop_fp_ctrl_div : issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fma = _T_276 ? issue_slots_8_out_uop_fp_ctrl_fma : _T_275 ? issue_slots_7_out_uop_fp_ctrl_fma : issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fastpipe = _T_276 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : _T_275 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_toint = _T_276 ? issue_slots_8_out_uop_fp_ctrl_toint : _T_275 ? issue_slots_7_out_uop_fp_ctrl_toint : issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fromint = _T_276 ? issue_slots_8_out_uop_fp_ctrl_fromint : _T_275 ? issue_slots_7_out_uop_fp_ctrl_fromint : issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut = _T_276 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : _T_275 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn = _T_276 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : _T_275 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap23 = _T_276 ? issue_slots_8_out_uop_fp_ctrl_swap23 : _T_275 ? issue_slots_7_out_uop_fp_ctrl_swap23 : issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap12 = _T_276 ? issue_slots_8_out_uop_fp_ctrl_swap12 : _T_275 ? issue_slots_7_out_uop_fp_ctrl_swap12 : issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren3 = _T_276 ? issue_slots_8_out_uop_fp_ctrl_ren3 : _T_275 ? issue_slots_7_out_uop_fp_ctrl_ren3 : issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren2 = _T_276 ? issue_slots_8_out_uop_fp_ctrl_ren2 : _T_275 ? issue_slots_7_out_uop_fp_ctrl_ren2 : issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren1 = _T_276 ? issue_slots_8_out_uop_fp_ctrl_ren1 : _T_275 ? issue_slots_7_out_uop_fp_ctrl_ren1 : issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wen = _T_276 ? issue_slots_8_out_uop_fp_ctrl_wen : _T_275 ? issue_slots_7_out_uop_fp_ctrl_wen : issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ldst = _T_276 ? issue_slots_8_out_uop_fp_ctrl_ldst : _T_275 ? issue_slots_7_out_uop_fp_ctrl_ldst : issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op2_sel = _T_276 ? issue_slots_8_out_uop_op2_sel : _T_275 ? issue_slots_7_out_uop_op2_sel : issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op1_sel = _T_276 ? issue_slots_8_out_uop_op1_sel : _T_275 ? issue_slots_7_out_uop_op1_sel : issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_packed = _T_276 ? issue_slots_8_out_uop_imm_packed : _T_275 ? issue_slots_7_out_uop_imm_packed : issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pimm = _T_276 ? issue_slots_8_out_uop_pimm : _T_275 ? issue_slots_7_out_uop_pimm : issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_sel = _T_276 ? issue_slots_8_out_uop_imm_sel : _T_275 ? issue_slots_7_out_uop_imm_sel : issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_rename = _T_276 ? issue_slots_8_out_uop_imm_rename : _T_275 ? issue_slots_7_out_uop_imm_rename : issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_taken = _T_276 ? issue_slots_8_out_uop_taken : _T_275 ? issue_slots_7_out_uop_taken : issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pc_lob = _T_276 ? issue_slots_8_out_uop_pc_lob : _T_275 ? issue_slots_7_out_uop_pc_lob : issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_edge_inst = _T_276 ? issue_slots_8_out_uop_edge_inst : _T_275 ? issue_slots_7_out_uop_edge_inst : issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ftq_idx = _T_276 ? issue_slots_8_out_uop_ftq_idx : _T_275 ? issue_slots_7_out_uop_ftq_idx : issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_mov = _T_276 ? issue_slots_8_out_uop_is_mov : _T_275 ? issue_slots_7_out_uop_is_mov : issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rocc = _T_276 ? issue_slots_8_out_uop_is_rocc : _T_275 ? issue_slots_7_out_uop_is_rocc : issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sys_pc2epc = _T_276 ? issue_slots_8_out_uop_is_sys_pc2epc : _T_275 ? issue_slots_7_out_uop_is_sys_pc2epc : issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_eret = _T_276 ? issue_slots_8_out_uop_is_eret : _T_275 ? issue_slots_7_out_uop_is_eret : issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_amo = _T_276 ? issue_slots_8_out_uop_is_amo : _T_275 ? issue_slots_7_out_uop_is_amo : issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfence = _T_276 ? issue_slots_8_out_uop_is_sfence : _T_275 ? issue_slots_7_out_uop_is_sfence : issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fencei = _T_276 ? issue_slots_8_out_uop_is_fencei : _T_275 ? issue_slots_7_out_uop_is_fencei : issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fence = _T_276 ? issue_slots_8_out_uop_is_fence : _T_275 ? issue_slots_7_out_uop_is_fence : issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfb = _T_276 ? issue_slots_8_out_uop_is_sfb : _T_275 ? issue_slots_7_out_uop_is_sfb : issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_type = _T_276 ? issue_slots_8_out_uop_br_type : _T_275 ? issue_slots_7_out_uop_br_type : issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_tag = _T_276 ? issue_slots_8_out_uop_br_tag : _T_275 ? issue_slots_7_out_uop_br_tag : issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_mask = _T_276 ? issue_slots_8_out_uop_br_mask : _T_275 ? issue_slots_7_out_uop_br_mask : issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dis_col_sel = _T_276 ? issue_slots_8_out_uop_dis_col_sel : _T_275 ? issue_slots_7_out_uop_dis_col_sel : issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p3_bypass_hint = _T_276 ? issue_slots_8_out_uop_iw_p3_bypass_hint : _T_275 ? issue_slots_7_out_uop_iw_p3_bypass_hint : issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p2_bypass_hint = _T_276 ? issue_slots_8_out_uop_iw_p2_bypass_hint : _T_275 ? issue_slots_7_out_uop_iw_p2_bypass_hint : issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p1_bypass_hint = _T_276 ? issue_slots_8_out_uop_iw_p1_bypass_hint : _T_275 ? issue_slots_7_out_uop_iw_p1_bypass_hint : issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p2_speculative_child = _T_276 ? issue_slots_8_out_uop_iw_p2_speculative_child : _T_275 ? issue_slots_7_out_uop_iw_p2_speculative_child : issue_slots_6_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p1_speculative_child = _T_276 ? issue_slots_8_out_uop_iw_p1_speculative_child : _T_275 ? issue_slots_7_out_uop_iw_p1_speculative_child : issue_slots_6_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_issued = _T_276 ? issue_slots_8_out_uop_iw_issued : _T_275 ? issue_slots_7_out_uop_iw_issued : issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_0 = _T_276 ? issue_slots_8_out_uop_fu_code_0 : _T_275 ? issue_slots_7_out_uop_fu_code_0 : issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_1 = _T_276 ? issue_slots_8_out_uop_fu_code_1 : _T_275 ? issue_slots_7_out_uop_fu_code_1 : issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_2 = _T_276 ? issue_slots_8_out_uop_fu_code_2 : _T_275 ? issue_slots_7_out_uop_fu_code_2 : issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_3 = _T_276 ? issue_slots_8_out_uop_fu_code_3 : _T_275 ? issue_slots_7_out_uop_fu_code_3 : issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_4 = _T_276 ? issue_slots_8_out_uop_fu_code_4 : _T_275 ? issue_slots_7_out_uop_fu_code_4 : issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_5 = _T_276 ? issue_slots_8_out_uop_fu_code_5 : _T_275 ? issue_slots_7_out_uop_fu_code_5 : issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_6 = _T_276 ? issue_slots_8_out_uop_fu_code_6 : _T_275 ? issue_slots_7_out_uop_fu_code_6 : issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_7 = _T_276 ? issue_slots_8_out_uop_fu_code_7 : _T_275 ? issue_slots_7_out_uop_fu_code_7 : issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_8 = _T_276 ? issue_slots_8_out_uop_fu_code_8 : _T_275 ? issue_slots_7_out_uop_fu_code_8 : issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_9 = _T_276 ? issue_slots_8_out_uop_fu_code_9 : _T_275 ? issue_slots_7_out_uop_fu_code_9 : issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_0 = _T_276 ? issue_slots_8_out_uop_iq_type_0 : _T_275 ? issue_slots_7_out_uop_iq_type_0 : issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_1 = _T_276 ? issue_slots_8_out_uop_iq_type_1 : _T_275 ? issue_slots_7_out_uop_iq_type_1 : issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_2 = _T_276 ? issue_slots_8_out_uop_iq_type_2 : _T_275 ? issue_slots_7_out_uop_iq_type_2 : issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_3 = _T_276 ? issue_slots_8_out_uop_iq_type_3 : _T_275 ? issue_slots_7_out_uop_iq_type_3 : issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_pc = _T_276 ? issue_slots_8_out_uop_debug_pc : _T_275 ? issue_slots_7_out_uop_debug_pc : issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rvc = _T_276 ? issue_slots_8_out_uop_is_rvc : _T_275 ? issue_slots_7_out_uop_is_rvc : issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_inst = _T_276 ? issue_slots_8_out_uop_debug_inst : _T_275 ? issue_slots_7_out_uop_debug_inst : issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_inst = _T_276 ? issue_slots_8_out_uop_inst : _T_275 ? issue_slots_7_out_uop_inst : issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_5_clear_T = |shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_5_clear = _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_278 = shamts_oh_8 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_279 = shamts_oh_9 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_6_in_uop_valid = _T_279 ? issue_slots_9_will_be_valid : _T_278 ? issue_slots_8_will_be_valid : shamts_oh_7 == 3'h1 & issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_6_in_uop_bits_debug_tsrc = _T_279 ? issue_slots_9_out_uop_debug_tsrc : _T_278 ? issue_slots_8_out_uop_debug_tsrc : issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_fsrc = _T_279 ? issue_slots_9_out_uop_debug_fsrc : _T_278 ? issue_slots_8_out_uop_debug_fsrc : issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_xcpt_if = _T_279 ? issue_slots_9_out_uop_bp_xcpt_if : _T_278 ? issue_slots_8_out_uop_bp_xcpt_if : issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_debug_if = _T_279 ? issue_slots_9_out_uop_bp_debug_if : _T_278 ? issue_slots_8_out_uop_bp_debug_if : issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ma_if = _T_279 ? issue_slots_9_out_uop_xcpt_ma_if : _T_278 ? issue_slots_8_out_uop_xcpt_ma_if : issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ae_if = _T_279 ? issue_slots_9_out_uop_xcpt_ae_if : _T_278 ? issue_slots_8_out_uop_xcpt_ae_if : issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_pf_if = _T_279 ? issue_slots_9_out_uop_xcpt_pf_if : _T_278 ? issue_slots_8_out_uop_xcpt_pf_if : issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_typ = _T_279 ? issue_slots_9_out_uop_fp_typ : _T_278 ? issue_slots_8_out_uop_fp_typ : issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_rm = _T_279 ? issue_slots_9_out_uop_fp_rm : _T_278 ? issue_slots_8_out_uop_fp_rm : issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_val = _T_279 ? issue_slots_9_out_uop_fp_val : _T_278 ? issue_slots_8_out_uop_fp_val : issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_op = _T_279 ? issue_slots_9_out_uop_fcn_op : _T_278 ? issue_slots_8_out_uop_fcn_op : issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_dw = _T_279 ? issue_slots_9_out_uop_fcn_dw : _T_278 ? issue_slots_8_out_uop_fcn_dw : issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_frs3_en = _T_279 ? issue_slots_9_out_uop_frs3_en : _T_278 ? issue_slots_8_out_uop_frs3_en : issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2_rtype = _T_279 ? issue_slots_9_out_uop_lrs2_rtype : _T_278 ? issue_slots_8_out_uop_lrs2_rtype : issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1_rtype = _T_279 ? issue_slots_9_out_uop_lrs1_rtype : _T_278 ? issue_slots_8_out_uop_lrs1_rtype : issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dst_rtype = _T_279 ? issue_slots_9_out_uop_dst_rtype : _T_278 ? issue_slots_8_out_uop_dst_rtype : issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs3 = _T_279 ? issue_slots_9_out_uop_lrs3 : _T_278 ? issue_slots_8_out_uop_lrs3 : issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2 = _T_279 ? issue_slots_9_out_uop_lrs2 : _T_278 ? issue_slots_8_out_uop_lrs2 : issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1 = _T_279 ? issue_slots_9_out_uop_lrs1 : _T_278 ? issue_slots_8_out_uop_lrs1 : issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst = _T_279 ? issue_slots_9_out_uop_ldst : _T_278 ? issue_slots_8_out_uop_ldst : issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst_is_rs1 = _T_279 ? issue_slots_9_out_uop_ldst_is_rs1 : _T_278 ? issue_slots_8_out_uop_ldst_is_rs1 : issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_csr_cmd = _T_279 ? issue_slots_9_out_uop_csr_cmd : _T_278 ? issue_slots_8_out_uop_csr_cmd : issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_flush_on_commit = _T_279 ? issue_slots_9_out_uop_flush_on_commit : _T_278 ? issue_slots_8_out_uop_flush_on_commit : issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_unique = _T_279 ? issue_slots_9_out_uop_is_unique : _T_278 ? issue_slots_8_out_uop_is_unique : issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_stq = _T_279 ? issue_slots_9_out_uop_uses_stq : _T_278 ? issue_slots_8_out_uop_uses_stq : issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_ldq = _T_279 ? issue_slots_9_out_uop_uses_ldq : _T_278 ? issue_slots_8_out_uop_uses_ldq : issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_signed = _T_279 ? issue_slots_9_out_uop_mem_signed : _T_278 ? issue_slots_8_out_uop_mem_signed : issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_size = _T_279 ? issue_slots_9_out_uop_mem_size : _T_278 ? issue_slots_8_out_uop_mem_size : issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_cmd = _T_279 ? issue_slots_9_out_uop_mem_cmd : _T_278 ? issue_slots_8_out_uop_mem_cmd : issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exc_cause = _T_279 ? issue_slots_9_out_uop_exc_cause : _T_278 ? issue_slots_8_out_uop_exc_cause : issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exception = _T_279 ? issue_slots_9_out_uop_exception : _T_278 ? issue_slots_8_out_uop_exception : issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stale_pdst = _T_279 ? issue_slots_9_out_uop_stale_pdst : _T_278 ? issue_slots_8_out_uop_stale_pdst : issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred_busy = _T_279 ? issue_slots_9_out_uop_ppred_busy : _T_278 ? issue_slots_8_out_uop_ppred_busy : issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3_busy = _T_279 ? issue_slots_9_out_uop_prs3_busy : _T_278 ? issue_slots_8_out_uop_prs3_busy : issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2_busy = _T_279 ? issue_slots_9_out_uop_prs2_busy : _T_278 ? issue_slots_8_out_uop_prs2_busy : issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1_busy = _T_279 ? issue_slots_9_out_uop_prs1_busy : _T_278 ? issue_slots_8_out_uop_prs1_busy : issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred = _T_279 ? issue_slots_9_out_uop_ppred : _T_278 ? issue_slots_8_out_uop_ppred : issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3 = _T_279 ? issue_slots_9_out_uop_prs3 : _T_278 ? issue_slots_8_out_uop_prs3 : issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2 = _T_279 ? issue_slots_9_out_uop_prs2 : _T_278 ? issue_slots_8_out_uop_prs2 : issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1 = _T_279 ? issue_slots_9_out_uop_prs1 : _T_278 ? issue_slots_8_out_uop_prs1 : issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pdst = _T_279 ? issue_slots_9_out_uop_pdst : _T_278 ? issue_slots_8_out_uop_pdst : issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rxq_idx = _T_279 ? issue_slots_9_out_uop_rxq_idx : _T_278 ? issue_slots_8_out_uop_rxq_idx : issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stq_idx = _T_279 ? issue_slots_9_out_uop_stq_idx : _T_278 ? issue_slots_8_out_uop_stq_idx : issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldq_idx = _T_279 ? issue_slots_9_out_uop_ldq_idx : _T_278 ? issue_slots_8_out_uop_ldq_idx : issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rob_idx = _T_279 ? issue_slots_9_out_uop_rob_idx : _T_278 ? issue_slots_8_out_uop_rob_idx : issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_vec = _T_279 ? issue_slots_9_out_uop_fp_ctrl_vec : _T_278 ? issue_slots_8_out_uop_fp_ctrl_vec : issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wflags = _T_279 ? issue_slots_9_out_uop_fp_ctrl_wflags : _T_278 ? issue_slots_8_out_uop_fp_ctrl_wflags : issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_sqrt = _T_279 ? issue_slots_9_out_uop_fp_ctrl_sqrt : _T_278 ? issue_slots_8_out_uop_fp_ctrl_sqrt : issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_div = _T_279 ? issue_slots_9_out_uop_fp_ctrl_div : _T_278 ? issue_slots_8_out_uop_fp_ctrl_div : issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fma = _T_279 ? issue_slots_9_out_uop_fp_ctrl_fma : _T_278 ? issue_slots_8_out_uop_fp_ctrl_fma : issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fastpipe = _T_279 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : _T_278 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_toint = _T_279 ? issue_slots_9_out_uop_fp_ctrl_toint : _T_278 ? issue_slots_8_out_uop_fp_ctrl_toint : issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fromint = _T_279 ? issue_slots_9_out_uop_fp_ctrl_fromint : _T_278 ? issue_slots_8_out_uop_fp_ctrl_fromint : issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut = _T_279 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : _T_278 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn = _T_279 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : _T_278 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap23 = _T_279 ? issue_slots_9_out_uop_fp_ctrl_swap23 : _T_278 ? issue_slots_8_out_uop_fp_ctrl_swap23 : issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap12 = _T_279 ? issue_slots_9_out_uop_fp_ctrl_swap12 : _T_278 ? issue_slots_8_out_uop_fp_ctrl_swap12 : issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren3 = _T_279 ? issue_slots_9_out_uop_fp_ctrl_ren3 : _T_278 ? issue_slots_8_out_uop_fp_ctrl_ren3 : issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren2 = _T_279 ? issue_slots_9_out_uop_fp_ctrl_ren2 : _T_278 ? issue_slots_8_out_uop_fp_ctrl_ren2 : issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren1 = _T_279 ? issue_slots_9_out_uop_fp_ctrl_ren1 : _T_278 ? issue_slots_8_out_uop_fp_ctrl_ren1 : issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wen = _T_279 ? issue_slots_9_out_uop_fp_ctrl_wen : _T_278 ? issue_slots_8_out_uop_fp_ctrl_wen : issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ldst = _T_279 ? issue_slots_9_out_uop_fp_ctrl_ldst : _T_278 ? issue_slots_8_out_uop_fp_ctrl_ldst : issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op2_sel = _T_279 ? issue_slots_9_out_uop_op2_sel : _T_278 ? issue_slots_8_out_uop_op2_sel : issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op1_sel = _T_279 ? issue_slots_9_out_uop_op1_sel : _T_278 ? issue_slots_8_out_uop_op1_sel : issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_packed = _T_279 ? issue_slots_9_out_uop_imm_packed : _T_278 ? issue_slots_8_out_uop_imm_packed : issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pimm = _T_279 ? issue_slots_9_out_uop_pimm : _T_278 ? issue_slots_8_out_uop_pimm : issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_sel = _T_279 ? issue_slots_9_out_uop_imm_sel : _T_278 ? issue_slots_8_out_uop_imm_sel : issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_rename = _T_279 ? issue_slots_9_out_uop_imm_rename : _T_278 ? issue_slots_8_out_uop_imm_rename : issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_taken = _T_279 ? issue_slots_9_out_uop_taken : _T_278 ? issue_slots_8_out_uop_taken : issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pc_lob = _T_279 ? issue_slots_9_out_uop_pc_lob : _T_278 ? issue_slots_8_out_uop_pc_lob : issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_edge_inst = _T_279 ? issue_slots_9_out_uop_edge_inst : _T_278 ? issue_slots_8_out_uop_edge_inst : issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ftq_idx = _T_279 ? issue_slots_9_out_uop_ftq_idx : _T_278 ? issue_slots_8_out_uop_ftq_idx : issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_mov = _T_279 ? issue_slots_9_out_uop_is_mov : _T_278 ? issue_slots_8_out_uop_is_mov : issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rocc = _T_279 ? issue_slots_9_out_uop_is_rocc : _T_278 ? issue_slots_8_out_uop_is_rocc : issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sys_pc2epc = _T_279 ? issue_slots_9_out_uop_is_sys_pc2epc : _T_278 ? issue_slots_8_out_uop_is_sys_pc2epc : issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_eret = _T_279 ? issue_slots_9_out_uop_is_eret : _T_278 ? issue_slots_8_out_uop_is_eret : issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_amo = _T_279 ? issue_slots_9_out_uop_is_amo : _T_278 ? issue_slots_8_out_uop_is_amo : issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfence = _T_279 ? issue_slots_9_out_uop_is_sfence : _T_278 ? issue_slots_8_out_uop_is_sfence : issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fencei = _T_279 ? issue_slots_9_out_uop_is_fencei : _T_278 ? issue_slots_8_out_uop_is_fencei : issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fence = _T_279 ? issue_slots_9_out_uop_is_fence : _T_278 ? issue_slots_8_out_uop_is_fence : issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfb = _T_279 ? issue_slots_9_out_uop_is_sfb : _T_278 ? issue_slots_8_out_uop_is_sfb : issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_type = _T_279 ? issue_slots_9_out_uop_br_type : _T_278 ? issue_slots_8_out_uop_br_type : issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_tag = _T_279 ? issue_slots_9_out_uop_br_tag : _T_278 ? issue_slots_8_out_uop_br_tag : issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_mask = _T_279 ? issue_slots_9_out_uop_br_mask : _T_278 ? issue_slots_8_out_uop_br_mask : issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dis_col_sel = _T_279 ? issue_slots_9_out_uop_dis_col_sel : _T_278 ? issue_slots_8_out_uop_dis_col_sel : issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p3_bypass_hint = _T_279 ? issue_slots_9_out_uop_iw_p3_bypass_hint : _T_278 ? issue_slots_8_out_uop_iw_p3_bypass_hint : issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p2_bypass_hint = _T_279 ? issue_slots_9_out_uop_iw_p2_bypass_hint : _T_278 ? issue_slots_8_out_uop_iw_p2_bypass_hint : issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p1_bypass_hint = _T_279 ? issue_slots_9_out_uop_iw_p1_bypass_hint : _T_278 ? issue_slots_8_out_uop_iw_p1_bypass_hint : issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p2_speculative_child = _T_279 ? issue_slots_9_out_uop_iw_p2_speculative_child : _T_278 ? issue_slots_8_out_uop_iw_p2_speculative_child : issue_slots_7_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p1_speculative_child = _T_279 ? issue_slots_9_out_uop_iw_p1_speculative_child : _T_278 ? issue_slots_8_out_uop_iw_p1_speculative_child : issue_slots_7_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_issued = _T_279 ? issue_slots_9_out_uop_iw_issued : _T_278 ? issue_slots_8_out_uop_iw_issued : issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_0 = _T_279 ? issue_slots_9_out_uop_fu_code_0 : _T_278 ? issue_slots_8_out_uop_fu_code_0 : issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_1 = _T_279 ? issue_slots_9_out_uop_fu_code_1 : _T_278 ? issue_slots_8_out_uop_fu_code_1 : issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_2 = _T_279 ? issue_slots_9_out_uop_fu_code_2 : _T_278 ? issue_slots_8_out_uop_fu_code_2 : issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_3 = _T_279 ? issue_slots_9_out_uop_fu_code_3 : _T_278 ? issue_slots_8_out_uop_fu_code_3 : issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_4 = _T_279 ? issue_slots_9_out_uop_fu_code_4 : _T_278 ? issue_slots_8_out_uop_fu_code_4 : issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_5 = _T_279 ? issue_slots_9_out_uop_fu_code_5 : _T_278 ? issue_slots_8_out_uop_fu_code_5 : issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_6 = _T_279 ? issue_slots_9_out_uop_fu_code_6 : _T_278 ? issue_slots_8_out_uop_fu_code_6 : issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_7 = _T_279 ? issue_slots_9_out_uop_fu_code_7 : _T_278 ? issue_slots_8_out_uop_fu_code_7 : issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_8 = _T_279 ? issue_slots_9_out_uop_fu_code_8 : _T_278 ? issue_slots_8_out_uop_fu_code_8 : issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_9 = _T_279 ? issue_slots_9_out_uop_fu_code_9 : _T_278 ? issue_slots_8_out_uop_fu_code_9 : issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_0 = _T_279 ? issue_slots_9_out_uop_iq_type_0 : _T_278 ? issue_slots_8_out_uop_iq_type_0 : issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_1 = _T_279 ? issue_slots_9_out_uop_iq_type_1 : _T_278 ? issue_slots_8_out_uop_iq_type_1 : issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_2 = _T_279 ? issue_slots_9_out_uop_iq_type_2 : _T_278 ? issue_slots_8_out_uop_iq_type_2 : issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_3 = _T_279 ? issue_slots_9_out_uop_iq_type_3 : _T_278 ? issue_slots_8_out_uop_iq_type_3 : issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_pc = _T_279 ? issue_slots_9_out_uop_debug_pc : _T_278 ? issue_slots_8_out_uop_debug_pc : issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rvc = _T_279 ? issue_slots_9_out_uop_is_rvc : _T_278 ? issue_slots_8_out_uop_is_rvc : issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_inst = _T_279 ? issue_slots_9_out_uop_debug_inst : _T_278 ? issue_slots_8_out_uop_debug_inst : issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_inst = _T_279 ? issue_slots_9_out_uop_inst : _T_278 ? issue_slots_8_out_uop_inst : issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_6_clear_T = |shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_6_clear = _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_281 = shamts_oh_9 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_282 = shamts_oh_10 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_7_in_uop_valid = _T_282 ? issue_slots_10_will_be_valid : _T_281 ? issue_slots_9_will_be_valid : shamts_oh_8 == 3'h1 & issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_7_in_uop_bits_debug_tsrc = _T_282 ? issue_slots_10_out_uop_debug_tsrc : _T_281 ? issue_slots_9_out_uop_debug_tsrc : issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_fsrc = _T_282 ? issue_slots_10_out_uop_debug_fsrc : _T_281 ? issue_slots_9_out_uop_debug_fsrc : issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_xcpt_if = _T_282 ? issue_slots_10_out_uop_bp_xcpt_if : _T_281 ? issue_slots_9_out_uop_bp_xcpt_if : issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_debug_if = _T_282 ? issue_slots_10_out_uop_bp_debug_if : _T_281 ? issue_slots_9_out_uop_bp_debug_if : issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ma_if = _T_282 ? issue_slots_10_out_uop_xcpt_ma_if : _T_281 ? issue_slots_9_out_uop_xcpt_ma_if : issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ae_if = _T_282 ? issue_slots_10_out_uop_xcpt_ae_if : _T_281 ? issue_slots_9_out_uop_xcpt_ae_if : issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_pf_if = _T_282 ? issue_slots_10_out_uop_xcpt_pf_if : _T_281 ? issue_slots_9_out_uop_xcpt_pf_if : issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_typ = _T_282 ? issue_slots_10_out_uop_fp_typ : _T_281 ? issue_slots_9_out_uop_fp_typ : issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_rm = _T_282 ? issue_slots_10_out_uop_fp_rm : _T_281 ? issue_slots_9_out_uop_fp_rm : issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_val = _T_282 ? issue_slots_10_out_uop_fp_val : _T_281 ? issue_slots_9_out_uop_fp_val : issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_op = _T_282 ? issue_slots_10_out_uop_fcn_op : _T_281 ? issue_slots_9_out_uop_fcn_op : issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_dw = _T_282 ? issue_slots_10_out_uop_fcn_dw : _T_281 ? issue_slots_9_out_uop_fcn_dw : issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_frs3_en = _T_282 ? issue_slots_10_out_uop_frs3_en : _T_281 ? issue_slots_9_out_uop_frs3_en : issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2_rtype = _T_282 ? issue_slots_10_out_uop_lrs2_rtype : _T_281 ? issue_slots_9_out_uop_lrs2_rtype : issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1_rtype = _T_282 ? issue_slots_10_out_uop_lrs1_rtype : _T_281 ? issue_slots_9_out_uop_lrs1_rtype : issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dst_rtype = _T_282 ? issue_slots_10_out_uop_dst_rtype : _T_281 ? issue_slots_9_out_uop_dst_rtype : issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs3 = _T_282 ? issue_slots_10_out_uop_lrs3 : _T_281 ? issue_slots_9_out_uop_lrs3 : issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2 = _T_282 ? issue_slots_10_out_uop_lrs2 : _T_281 ? issue_slots_9_out_uop_lrs2 : issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1 = _T_282 ? issue_slots_10_out_uop_lrs1 : _T_281 ? issue_slots_9_out_uop_lrs1 : issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst = _T_282 ? issue_slots_10_out_uop_ldst : _T_281 ? issue_slots_9_out_uop_ldst : issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst_is_rs1 = _T_282 ? issue_slots_10_out_uop_ldst_is_rs1 : _T_281 ? issue_slots_9_out_uop_ldst_is_rs1 : issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_csr_cmd = _T_282 ? issue_slots_10_out_uop_csr_cmd : _T_281 ? issue_slots_9_out_uop_csr_cmd : issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_flush_on_commit = _T_282 ? issue_slots_10_out_uop_flush_on_commit : _T_281 ? issue_slots_9_out_uop_flush_on_commit : issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_unique = _T_282 ? issue_slots_10_out_uop_is_unique : _T_281 ? issue_slots_9_out_uop_is_unique : issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_stq = _T_282 ? issue_slots_10_out_uop_uses_stq : _T_281 ? issue_slots_9_out_uop_uses_stq : issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_ldq = _T_282 ? issue_slots_10_out_uop_uses_ldq : _T_281 ? issue_slots_9_out_uop_uses_ldq : issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_signed = _T_282 ? issue_slots_10_out_uop_mem_signed : _T_281 ? issue_slots_9_out_uop_mem_signed : issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_size = _T_282 ? issue_slots_10_out_uop_mem_size : _T_281 ? issue_slots_9_out_uop_mem_size : issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_cmd = _T_282 ? issue_slots_10_out_uop_mem_cmd : _T_281 ? issue_slots_9_out_uop_mem_cmd : issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exc_cause = _T_282 ? issue_slots_10_out_uop_exc_cause : _T_281 ? issue_slots_9_out_uop_exc_cause : issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exception = _T_282 ? issue_slots_10_out_uop_exception : _T_281 ? issue_slots_9_out_uop_exception : issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stale_pdst = _T_282 ? issue_slots_10_out_uop_stale_pdst : _T_281 ? issue_slots_9_out_uop_stale_pdst : issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred_busy = _T_282 ? issue_slots_10_out_uop_ppred_busy : _T_281 ? issue_slots_9_out_uop_ppred_busy : issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3_busy = _T_282 ? issue_slots_10_out_uop_prs3_busy : _T_281 ? issue_slots_9_out_uop_prs3_busy : issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2_busy = _T_282 ? issue_slots_10_out_uop_prs2_busy : _T_281 ? issue_slots_9_out_uop_prs2_busy : issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1_busy = _T_282 ? issue_slots_10_out_uop_prs1_busy : _T_281 ? issue_slots_9_out_uop_prs1_busy : issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred = _T_282 ? issue_slots_10_out_uop_ppred : _T_281 ? issue_slots_9_out_uop_ppred : issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3 = _T_282 ? issue_slots_10_out_uop_prs3 : _T_281 ? issue_slots_9_out_uop_prs3 : issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2 = _T_282 ? issue_slots_10_out_uop_prs2 : _T_281 ? issue_slots_9_out_uop_prs2 : issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1 = _T_282 ? issue_slots_10_out_uop_prs1 : _T_281 ? issue_slots_9_out_uop_prs1 : issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pdst = _T_282 ? issue_slots_10_out_uop_pdst : _T_281 ? issue_slots_9_out_uop_pdst : issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rxq_idx = _T_282 ? issue_slots_10_out_uop_rxq_idx : _T_281 ? issue_slots_9_out_uop_rxq_idx : issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stq_idx = _T_282 ? issue_slots_10_out_uop_stq_idx : _T_281 ? issue_slots_9_out_uop_stq_idx : issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldq_idx = _T_282 ? issue_slots_10_out_uop_ldq_idx : _T_281 ? issue_slots_9_out_uop_ldq_idx : issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rob_idx = _T_282 ? issue_slots_10_out_uop_rob_idx : _T_281 ? issue_slots_9_out_uop_rob_idx : issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_vec = _T_282 ? issue_slots_10_out_uop_fp_ctrl_vec : _T_281 ? issue_slots_9_out_uop_fp_ctrl_vec : issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wflags = _T_282 ? issue_slots_10_out_uop_fp_ctrl_wflags : _T_281 ? issue_slots_9_out_uop_fp_ctrl_wflags : issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_sqrt = _T_282 ? issue_slots_10_out_uop_fp_ctrl_sqrt : _T_281 ? issue_slots_9_out_uop_fp_ctrl_sqrt : issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_div = _T_282 ? issue_slots_10_out_uop_fp_ctrl_div : _T_281 ? issue_slots_9_out_uop_fp_ctrl_div : issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fma = _T_282 ? issue_slots_10_out_uop_fp_ctrl_fma : _T_281 ? issue_slots_9_out_uop_fp_ctrl_fma : issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fastpipe = _T_282 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : _T_281 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_toint = _T_282 ? issue_slots_10_out_uop_fp_ctrl_toint : _T_281 ? issue_slots_9_out_uop_fp_ctrl_toint : issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fromint = _T_282 ? issue_slots_10_out_uop_fp_ctrl_fromint : _T_281 ? issue_slots_9_out_uop_fp_ctrl_fromint : issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut = _T_282 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : _T_281 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn = _T_282 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : _T_281 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap23 = _T_282 ? issue_slots_10_out_uop_fp_ctrl_swap23 : _T_281 ? issue_slots_9_out_uop_fp_ctrl_swap23 : issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap12 = _T_282 ? issue_slots_10_out_uop_fp_ctrl_swap12 : _T_281 ? issue_slots_9_out_uop_fp_ctrl_swap12 : issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren3 = _T_282 ? issue_slots_10_out_uop_fp_ctrl_ren3 : _T_281 ? issue_slots_9_out_uop_fp_ctrl_ren3 : issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren2 = _T_282 ? issue_slots_10_out_uop_fp_ctrl_ren2 : _T_281 ? issue_slots_9_out_uop_fp_ctrl_ren2 : issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren1 = _T_282 ? issue_slots_10_out_uop_fp_ctrl_ren1 : _T_281 ? issue_slots_9_out_uop_fp_ctrl_ren1 : issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wen = _T_282 ? issue_slots_10_out_uop_fp_ctrl_wen : _T_281 ? issue_slots_9_out_uop_fp_ctrl_wen : issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ldst = _T_282 ? issue_slots_10_out_uop_fp_ctrl_ldst : _T_281 ? issue_slots_9_out_uop_fp_ctrl_ldst : issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op2_sel = _T_282 ? issue_slots_10_out_uop_op2_sel : _T_281 ? issue_slots_9_out_uop_op2_sel : issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op1_sel = _T_282 ? issue_slots_10_out_uop_op1_sel : _T_281 ? issue_slots_9_out_uop_op1_sel : issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_packed = _T_282 ? issue_slots_10_out_uop_imm_packed : _T_281 ? issue_slots_9_out_uop_imm_packed : issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pimm = _T_282 ? issue_slots_10_out_uop_pimm : _T_281 ? issue_slots_9_out_uop_pimm : issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_sel = _T_282 ? issue_slots_10_out_uop_imm_sel : _T_281 ? issue_slots_9_out_uop_imm_sel : issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_rename = _T_282 ? issue_slots_10_out_uop_imm_rename : _T_281 ? issue_slots_9_out_uop_imm_rename : issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_taken = _T_282 ? issue_slots_10_out_uop_taken : _T_281 ? issue_slots_9_out_uop_taken : issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pc_lob = _T_282 ? issue_slots_10_out_uop_pc_lob : _T_281 ? issue_slots_9_out_uop_pc_lob : issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_edge_inst = _T_282 ? issue_slots_10_out_uop_edge_inst : _T_281 ? issue_slots_9_out_uop_edge_inst : issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ftq_idx = _T_282 ? issue_slots_10_out_uop_ftq_idx : _T_281 ? issue_slots_9_out_uop_ftq_idx : issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_mov = _T_282 ? issue_slots_10_out_uop_is_mov : _T_281 ? issue_slots_9_out_uop_is_mov : issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rocc = _T_282 ? issue_slots_10_out_uop_is_rocc : _T_281 ? issue_slots_9_out_uop_is_rocc : issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sys_pc2epc = _T_282 ? issue_slots_10_out_uop_is_sys_pc2epc : _T_281 ? issue_slots_9_out_uop_is_sys_pc2epc : issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_eret = _T_282 ? issue_slots_10_out_uop_is_eret : _T_281 ? issue_slots_9_out_uop_is_eret : issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_amo = _T_282 ? issue_slots_10_out_uop_is_amo : _T_281 ? issue_slots_9_out_uop_is_amo : issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfence = _T_282 ? issue_slots_10_out_uop_is_sfence : _T_281 ? issue_slots_9_out_uop_is_sfence : issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fencei = _T_282 ? issue_slots_10_out_uop_is_fencei : _T_281 ? issue_slots_9_out_uop_is_fencei : issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fence = _T_282 ? issue_slots_10_out_uop_is_fence : _T_281 ? issue_slots_9_out_uop_is_fence : issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfb = _T_282 ? issue_slots_10_out_uop_is_sfb : _T_281 ? issue_slots_9_out_uop_is_sfb : issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_type = _T_282 ? issue_slots_10_out_uop_br_type : _T_281 ? issue_slots_9_out_uop_br_type : issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_tag = _T_282 ? issue_slots_10_out_uop_br_tag : _T_281 ? issue_slots_9_out_uop_br_tag : issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_mask = _T_282 ? issue_slots_10_out_uop_br_mask : _T_281 ? issue_slots_9_out_uop_br_mask : issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dis_col_sel = _T_282 ? issue_slots_10_out_uop_dis_col_sel : _T_281 ? issue_slots_9_out_uop_dis_col_sel : issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p3_bypass_hint = _T_282 ? issue_slots_10_out_uop_iw_p3_bypass_hint : _T_281 ? issue_slots_9_out_uop_iw_p3_bypass_hint : issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p2_bypass_hint = _T_282 ? issue_slots_10_out_uop_iw_p2_bypass_hint : _T_281 ? issue_slots_9_out_uop_iw_p2_bypass_hint : issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p1_bypass_hint = _T_282 ? issue_slots_10_out_uop_iw_p1_bypass_hint : _T_281 ? issue_slots_9_out_uop_iw_p1_bypass_hint : issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p2_speculative_child = _T_282 ? issue_slots_10_out_uop_iw_p2_speculative_child : _T_281 ? issue_slots_9_out_uop_iw_p2_speculative_child : issue_slots_8_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p1_speculative_child = _T_282 ? issue_slots_10_out_uop_iw_p1_speculative_child : _T_281 ? issue_slots_9_out_uop_iw_p1_speculative_child : issue_slots_8_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_issued = _T_282 ? issue_slots_10_out_uop_iw_issued : _T_281 ? issue_slots_9_out_uop_iw_issued : issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_0 = _T_282 ? issue_slots_10_out_uop_fu_code_0 : _T_281 ? issue_slots_9_out_uop_fu_code_0 : issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_1 = _T_282 ? issue_slots_10_out_uop_fu_code_1 : _T_281 ? issue_slots_9_out_uop_fu_code_1 : issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_2 = _T_282 ? issue_slots_10_out_uop_fu_code_2 : _T_281 ? issue_slots_9_out_uop_fu_code_2 : issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_3 = _T_282 ? issue_slots_10_out_uop_fu_code_3 : _T_281 ? issue_slots_9_out_uop_fu_code_3 : issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_4 = _T_282 ? issue_slots_10_out_uop_fu_code_4 : _T_281 ? issue_slots_9_out_uop_fu_code_4 : issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_5 = _T_282 ? issue_slots_10_out_uop_fu_code_5 : _T_281 ? issue_slots_9_out_uop_fu_code_5 : issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_6 = _T_282 ? issue_slots_10_out_uop_fu_code_6 : _T_281 ? issue_slots_9_out_uop_fu_code_6 : issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_7 = _T_282 ? issue_slots_10_out_uop_fu_code_7 : _T_281 ? issue_slots_9_out_uop_fu_code_7 : issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_8 = _T_282 ? issue_slots_10_out_uop_fu_code_8 : _T_281 ? issue_slots_9_out_uop_fu_code_8 : issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_9 = _T_282 ? issue_slots_10_out_uop_fu_code_9 : _T_281 ? issue_slots_9_out_uop_fu_code_9 : issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_0 = _T_282 ? issue_slots_10_out_uop_iq_type_0 : _T_281 ? issue_slots_9_out_uop_iq_type_0 : issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_1 = _T_282 ? issue_slots_10_out_uop_iq_type_1 : _T_281 ? issue_slots_9_out_uop_iq_type_1 : issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_2 = _T_282 ? issue_slots_10_out_uop_iq_type_2 : _T_281 ? issue_slots_9_out_uop_iq_type_2 : issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_3 = _T_282 ? issue_slots_10_out_uop_iq_type_3 : _T_281 ? issue_slots_9_out_uop_iq_type_3 : issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_pc = _T_282 ? issue_slots_10_out_uop_debug_pc : _T_281 ? issue_slots_9_out_uop_debug_pc : issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rvc = _T_282 ? issue_slots_10_out_uop_is_rvc : _T_281 ? issue_slots_9_out_uop_is_rvc : issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_inst = _T_282 ? issue_slots_10_out_uop_debug_inst : _T_281 ? issue_slots_9_out_uop_debug_inst : issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_inst = _T_282 ? issue_slots_10_out_uop_inst : _T_281 ? issue_slots_9_out_uop_inst : issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_7_clear_T = |shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_7_clear = _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_284 = shamts_oh_10 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_285 = shamts_oh_11 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_8_in_uop_valid = _T_285 ? issue_slots_11_will_be_valid : _T_284 ? issue_slots_10_will_be_valid : shamts_oh_9 == 3'h1 & issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_8_in_uop_bits_debug_tsrc = _T_285 ? issue_slots_11_out_uop_debug_tsrc : _T_284 ? issue_slots_10_out_uop_debug_tsrc : issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_fsrc = _T_285 ? issue_slots_11_out_uop_debug_fsrc : _T_284 ? issue_slots_10_out_uop_debug_fsrc : issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_xcpt_if = _T_285 ? issue_slots_11_out_uop_bp_xcpt_if : _T_284 ? issue_slots_10_out_uop_bp_xcpt_if : issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_debug_if = _T_285 ? issue_slots_11_out_uop_bp_debug_if : _T_284 ? issue_slots_10_out_uop_bp_debug_if : issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ma_if = _T_285 ? issue_slots_11_out_uop_xcpt_ma_if : _T_284 ? issue_slots_10_out_uop_xcpt_ma_if : issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ae_if = _T_285 ? issue_slots_11_out_uop_xcpt_ae_if : _T_284 ? issue_slots_10_out_uop_xcpt_ae_if : issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_pf_if = _T_285 ? issue_slots_11_out_uop_xcpt_pf_if : _T_284 ? issue_slots_10_out_uop_xcpt_pf_if : issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_typ = _T_285 ? issue_slots_11_out_uop_fp_typ : _T_284 ? issue_slots_10_out_uop_fp_typ : issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_rm = _T_285 ? issue_slots_11_out_uop_fp_rm : _T_284 ? issue_slots_10_out_uop_fp_rm : issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_val = _T_285 ? issue_slots_11_out_uop_fp_val : _T_284 ? issue_slots_10_out_uop_fp_val : issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_op = _T_285 ? issue_slots_11_out_uop_fcn_op : _T_284 ? issue_slots_10_out_uop_fcn_op : issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_dw = _T_285 ? issue_slots_11_out_uop_fcn_dw : _T_284 ? issue_slots_10_out_uop_fcn_dw : issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_frs3_en = _T_285 ? issue_slots_11_out_uop_frs3_en : _T_284 ? issue_slots_10_out_uop_frs3_en : issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2_rtype = _T_285 ? issue_slots_11_out_uop_lrs2_rtype : _T_284 ? issue_slots_10_out_uop_lrs2_rtype : issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1_rtype = _T_285 ? issue_slots_11_out_uop_lrs1_rtype : _T_284 ? issue_slots_10_out_uop_lrs1_rtype : issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dst_rtype = _T_285 ? issue_slots_11_out_uop_dst_rtype : _T_284 ? issue_slots_10_out_uop_dst_rtype : issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs3 = _T_285 ? issue_slots_11_out_uop_lrs3 : _T_284 ? issue_slots_10_out_uop_lrs3 : issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2 = _T_285 ? issue_slots_11_out_uop_lrs2 : _T_284 ? issue_slots_10_out_uop_lrs2 : issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1 = _T_285 ? issue_slots_11_out_uop_lrs1 : _T_284 ? issue_slots_10_out_uop_lrs1 : issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst = _T_285 ? issue_slots_11_out_uop_ldst : _T_284 ? issue_slots_10_out_uop_ldst : issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst_is_rs1 = _T_285 ? issue_slots_11_out_uop_ldst_is_rs1 : _T_284 ? issue_slots_10_out_uop_ldst_is_rs1 : issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_csr_cmd = _T_285 ? issue_slots_11_out_uop_csr_cmd : _T_284 ? issue_slots_10_out_uop_csr_cmd : issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_flush_on_commit = _T_285 ? issue_slots_11_out_uop_flush_on_commit : _T_284 ? issue_slots_10_out_uop_flush_on_commit : issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_unique = _T_285 ? issue_slots_11_out_uop_is_unique : _T_284 ? issue_slots_10_out_uop_is_unique : issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_stq = _T_285 ? issue_slots_11_out_uop_uses_stq : _T_284 ? issue_slots_10_out_uop_uses_stq : issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_ldq = _T_285 ? issue_slots_11_out_uop_uses_ldq : _T_284 ? issue_slots_10_out_uop_uses_ldq : issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_signed = _T_285 ? issue_slots_11_out_uop_mem_signed : _T_284 ? issue_slots_10_out_uop_mem_signed : issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_size = _T_285 ? issue_slots_11_out_uop_mem_size : _T_284 ? issue_slots_10_out_uop_mem_size : issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_cmd = _T_285 ? issue_slots_11_out_uop_mem_cmd : _T_284 ? issue_slots_10_out_uop_mem_cmd : issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exc_cause = _T_285 ? issue_slots_11_out_uop_exc_cause : _T_284 ? issue_slots_10_out_uop_exc_cause : issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exception = _T_285 ? issue_slots_11_out_uop_exception : _T_284 ? issue_slots_10_out_uop_exception : issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stale_pdst = _T_285 ? issue_slots_11_out_uop_stale_pdst : _T_284 ? issue_slots_10_out_uop_stale_pdst : issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred_busy = _T_285 ? issue_slots_11_out_uop_ppred_busy : _T_284 ? issue_slots_10_out_uop_ppred_busy : issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3_busy = _T_285 ? issue_slots_11_out_uop_prs3_busy : _T_284 ? issue_slots_10_out_uop_prs3_busy : issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2_busy = _T_285 ? issue_slots_11_out_uop_prs2_busy : _T_284 ? issue_slots_10_out_uop_prs2_busy : issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1_busy = _T_285 ? issue_slots_11_out_uop_prs1_busy : _T_284 ? issue_slots_10_out_uop_prs1_busy : issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred = _T_285 ? issue_slots_11_out_uop_ppred : _T_284 ? issue_slots_10_out_uop_ppred : issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3 = _T_285 ? issue_slots_11_out_uop_prs3 : _T_284 ? issue_slots_10_out_uop_prs3 : issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2 = _T_285 ? issue_slots_11_out_uop_prs2 : _T_284 ? issue_slots_10_out_uop_prs2 : issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1 = _T_285 ? issue_slots_11_out_uop_prs1 : _T_284 ? issue_slots_10_out_uop_prs1 : issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pdst = _T_285 ? issue_slots_11_out_uop_pdst : _T_284 ? issue_slots_10_out_uop_pdst : issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rxq_idx = _T_285 ? issue_slots_11_out_uop_rxq_idx : _T_284 ? issue_slots_10_out_uop_rxq_idx : issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stq_idx = _T_285 ? issue_slots_11_out_uop_stq_idx : _T_284 ? issue_slots_10_out_uop_stq_idx : issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldq_idx = _T_285 ? issue_slots_11_out_uop_ldq_idx : _T_284 ? issue_slots_10_out_uop_ldq_idx : issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rob_idx = _T_285 ? issue_slots_11_out_uop_rob_idx : _T_284 ? issue_slots_10_out_uop_rob_idx : issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_vec = _T_285 ? issue_slots_11_out_uop_fp_ctrl_vec : _T_284 ? issue_slots_10_out_uop_fp_ctrl_vec : issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wflags = _T_285 ? issue_slots_11_out_uop_fp_ctrl_wflags : _T_284 ? issue_slots_10_out_uop_fp_ctrl_wflags : issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_sqrt = _T_285 ? issue_slots_11_out_uop_fp_ctrl_sqrt : _T_284 ? issue_slots_10_out_uop_fp_ctrl_sqrt : issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_div = _T_285 ? issue_slots_11_out_uop_fp_ctrl_div : _T_284 ? issue_slots_10_out_uop_fp_ctrl_div : issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fma = _T_285 ? issue_slots_11_out_uop_fp_ctrl_fma : _T_284 ? issue_slots_10_out_uop_fp_ctrl_fma : issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fastpipe = _T_285 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : _T_284 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_toint = _T_285 ? issue_slots_11_out_uop_fp_ctrl_toint : _T_284 ? issue_slots_10_out_uop_fp_ctrl_toint : issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fromint = _T_285 ? issue_slots_11_out_uop_fp_ctrl_fromint : _T_284 ? issue_slots_10_out_uop_fp_ctrl_fromint : issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut = _T_285 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : _T_284 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn = _T_285 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : _T_284 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap23 = _T_285 ? issue_slots_11_out_uop_fp_ctrl_swap23 : _T_284 ? issue_slots_10_out_uop_fp_ctrl_swap23 : issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap12 = _T_285 ? issue_slots_11_out_uop_fp_ctrl_swap12 : _T_284 ? issue_slots_10_out_uop_fp_ctrl_swap12 : issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren3 = _T_285 ? issue_slots_11_out_uop_fp_ctrl_ren3 : _T_284 ? issue_slots_10_out_uop_fp_ctrl_ren3 : issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren2 = _T_285 ? issue_slots_11_out_uop_fp_ctrl_ren2 : _T_284 ? issue_slots_10_out_uop_fp_ctrl_ren2 : issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren1 = _T_285 ? issue_slots_11_out_uop_fp_ctrl_ren1 : _T_284 ? issue_slots_10_out_uop_fp_ctrl_ren1 : issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wen = _T_285 ? issue_slots_11_out_uop_fp_ctrl_wen : _T_284 ? issue_slots_10_out_uop_fp_ctrl_wen : issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ldst = _T_285 ? issue_slots_11_out_uop_fp_ctrl_ldst : _T_284 ? issue_slots_10_out_uop_fp_ctrl_ldst : issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op2_sel = _T_285 ? issue_slots_11_out_uop_op2_sel : _T_284 ? issue_slots_10_out_uop_op2_sel : issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op1_sel = _T_285 ? issue_slots_11_out_uop_op1_sel : _T_284 ? issue_slots_10_out_uop_op1_sel : issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_packed = _T_285 ? issue_slots_11_out_uop_imm_packed : _T_284 ? issue_slots_10_out_uop_imm_packed : issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pimm = _T_285 ? issue_slots_11_out_uop_pimm : _T_284 ? issue_slots_10_out_uop_pimm : issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_sel = _T_285 ? issue_slots_11_out_uop_imm_sel : _T_284 ? issue_slots_10_out_uop_imm_sel : issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_rename = _T_285 ? issue_slots_11_out_uop_imm_rename : _T_284 ? issue_slots_10_out_uop_imm_rename : issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_taken = _T_285 ? issue_slots_11_out_uop_taken : _T_284 ? issue_slots_10_out_uop_taken : issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pc_lob = _T_285 ? issue_slots_11_out_uop_pc_lob : _T_284 ? issue_slots_10_out_uop_pc_lob : issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_edge_inst = _T_285 ? issue_slots_11_out_uop_edge_inst : _T_284 ? issue_slots_10_out_uop_edge_inst : issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ftq_idx = _T_285 ? issue_slots_11_out_uop_ftq_idx : _T_284 ? issue_slots_10_out_uop_ftq_idx : issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_mov = _T_285 ? issue_slots_11_out_uop_is_mov : _T_284 ? issue_slots_10_out_uop_is_mov : issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rocc = _T_285 ? issue_slots_11_out_uop_is_rocc : _T_284 ? issue_slots_10_out_uop_is_rocc : issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sys_pc2epc = _T_285 ? issue_slots_11_out_uop_is_sys_pc2epc : _T_284 ? issue_slots_10_out_uop_is_sys_pc2epc : issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_eret = _T_285 ? issue_slots_11_out_uop_is_eret : _T_284 ? issue_slots_10_out_uop_is_eret : issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_amo = _T_285 ? issue_slots_11_out_uop_is_amo : _T_284 ? issue_slots_10_out_uop_is_amo : issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfence = _T_285 ? issue_slots_11_out_uop_is_sfence : _T_284 ? issue_slots_10_out_uop_is_sfence : issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fencei = _T_285 ? issue_slots_11_out_uop_is_fencei : _T_284 ? issue_slots_10_out_uop_is_fencei : issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fence = _T_285 ? issue_slots_11_out_uop_is_fence : _T_284 ? issue_slots_10_out_uop_is_fence : issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfb = _T_285 ? issue_slots_11_out_uop_is_sfb : _T_284 ? issue_slots_10_out_uop_is_sfb : issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_type = _T_285 ? issue_slots_11_out_uop_br_type : _T_284 ? issue_slots_10_out_uop_br_type : issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_tag = _T_285 ? issue_slots_11_out_uop_br_tag : _T_284 ? issue_slots_10_out_uop_br_tag : issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_mask = _T_285 ? issue_slots_11_out_uop_br_mask : _T_284 ? issue_slots_10_out_uop_br_mask : issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dis_col_sel = _T_285 ? issue_slots_11_out_uop_dis_col_sel : _T_284 ? issue_slots_10_out_uop_dis_col_sel : issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p3_bypass_hint = _T_285 ? issue_slots_11_out_uop_iw_p3_bypass_hint : _T_284 ? issue_slots_10_out_uop_iw_p3_bypass_hint : issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p2_bypass_hint = _T_285 ? issue_slots_11_out_uop_iw_p2_bypass_hint : _T_284 ? issue_slots_10_out_uop_iw_p2_bypass_hint : issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p1_bypass_hint = _T_285 ? issue_slots_11_out_uop_iw_p1_bypass_hint : _T_284 ? issue_slots_10_out_uop_iw_p1_bypass_hint : issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p2_speculative_child = _T_285 ? issue_slots_11_out_uop_iw_p2_speculative_child : _T_284 ? issue_slots_10_out_uop_iw_p2_speculative_child : issue_slots_9_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p1_speculative_child = _T_285 ? issue_slots_11_out_uop_iw_p1_speculative_child : _T_284 ? issue_slots_10_out_uop_iw_p1_speculative_child : issue_slots_9_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_issued = _T_285 ? issue_slots_11_out_uop_iw_issued : _T_284 ? issue_slots_10_out_uop_iw_issued : issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_0 = _T_285 ? issue_slots_11_out_uop_fu_code_0 : _T_284 ? issue_slots_10_out_uop_fu_code_0 : issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_1 = _T_285 ? issue_slots_11_out_uop_fu_code_1 : _T_284 ? issue_slots_10_out_uop_fu_code_1 : issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_2 = _T_285 ? issue_slots_11_out_uop_fu_code_2 : _T_284 ? issue_slots_10_out_uop_fu_code_2 : issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_3 = _T_285 ? issue_slots_11_out_uop_fu_code_3 : _T_284 ? issue_slots_10_out_uop_fu_code_3 : issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_4 = _T_285 ? issue_slots_11_out_uop_fu_code_4 : _T_284 ? issue_slots_10_out_uop_fu_code_4 : issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_5 = _T_285 ? issue_slots_11_out_uop_fu_code_5 : _T_284 ? issue_slots_10_out_uop_fu_code_5 : issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_6 = _T_285 ? issue_slots_11_out_uop_fu_code_6 : _T_284 ? issue_slots_10_out_uop_fu_code_6 : issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_7 = _T_285 ? issue_slots_11_out_uop_fu_code_7 : _T_284 ? issue_slots_10_out_uop_fu_code_7 : issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_8 = _T_285 ? issue_slots_11_out_uop_fu_code_8 : _T_284 ? issue_slots_10_out_uop_fu_code_8 : issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_9 = _T_285 ? issue_slots_11_out_uop_fu_code_9 : _T_284 ? issue_slots_10_out_uop_fu_code_9 : issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_0 = _T_285 ? issue_slots_11_out_uop_iq_type_0 : _T_284 ? issue_slots_10_out_uop_iq_type_0 : issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_1 = _T_285 ? issue_slots_11_out_uop_iq_type_1 : _T_284 ? issue_slots_10_out_uop_iq_type_1 : issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_2 = _T_285 ? issue_slots_11_out_uop_iq_type_2 : _T_284 ? issue_slots_10_out_uop_iq_type_2 : issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_3 = _T_285 ? issue_slots_11_out_uop_iq_type_3 : _T_284 ? issue_slots_10_out_uop_iq_type_3 : issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_pc = _T_285 ? issue_slots_11_out_uop_debug_pc : _T_284 ? issue_slots_10_out_uop_debug_pc : issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rvc = _T_285 ? issue_slots_11_out_uop_is_rvc : _T_284 ? issue_slots_10_out_uop_is_rvc : issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_inst = _T_285 ? issue_slots_11_out_uop_debug_inst : _T_284 ? issue_slots_10_out_uop_debug_inst : issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_inst = _T_285 ? issue_slots_11_out_uop_inst : _T_284 ? issue_slots_10_out_uop_inst : issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_8_clear_T = |shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_8_clear = _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_287 = shamts_oh_11 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_288 = shamts_oh_12 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_9_in_uop_valid = _T_288 ? issue_slots_12_will_be_valid : _T_287 ? issue_slots_11_will_be_valid : shamts_oh_10 == 3'h1 & issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_9_in_uop_bits_debug_tsrc = _T_288 ? issue_slots_12_out_uop_debug_tsrc : _T_287 ? issue_slots_11_out_uop_debug_tsrc : issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_fsrc = _T_288 ? issue_slots_12_out_uop_debug_fsrc : _T_287 ? issue_slots_11_out_uop_debug_fsrc : issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_xcpt_if = _T_288 ? issue_slots_12_out_uop_bp_xcpt_if : _T_287 ? issue_slots_11_out_uop_bp_xcpt_if : issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_debug_if = _T_288 ? issue_slots_12_out_uop_bp_debug_if : _T_287 ? issue_slots_11_out_uop_bp_debug_if : issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ma_if = _T_288 ? issue_slots_12_out_uop_xcpt_ma_if : _T_287 ? issue_slots_11_out_uop_xcpt_ma_if : issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ae_if = _T_288 ? issue_slots_12_out_uop_xcpt_ae_if : _T_287 ? issue_slots_11_out_uop_xcpt_ae_if : issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_pf_if = _T_288 ? issue_slots_12_out_uop_xcpt_pf_if : _T_287 ? issue_slots_11_out_uop_xcpt_pf_if : issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_typ = _T_288 ? issue_slots_12_out_uop_fp_typ : _T_287 ? issue_slots_11_out_uop_fp_typ : issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_rm = _T_288 ? issue_slots_12_out_uop_fp_rm : _T_287 ? issue_slots_11_out_uop_fp_rm : issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_val = _T_288 ? issue_slots_12_out_uop_fp_val : _T_287 ? issue_slots_11_out_uop_fp_val : issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_op = _T_288 ? issue_slots_12_out_uop_fcn_op : _T_287 ? issue_slots_11_out_uop_fcn_op : issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_dw = _T_288 ? issue_slots_12_out_uop_fcn_dw : _T_287 ? issue_slots_11_out_uop_fcn_dw : issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_frs3_en = _T_288 ? issue_slots_12_out_uop_frs3_en : _T_287 ? issue_slots_11_out_uop_frs3_en : issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2_rtype = _T_288 ? issue_slots_12_out_uop_lrs2_rtype : _T_287 ? issue_slots_11_out_uop_lrs2_rtype : issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1_rtype = _T_288 ? issue_slots_12_out_uop_lrs1_rtype : _T_287 ? issue_slots_11_out_uop_lrs1_rtype : issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dst_rtype = _T_288 ? issue_slots_12_out_uop_dst_rtype : _T_287 ? issue_slots_11_out_uop_dst_rtype : issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs3 = _T_288 ? issue_slots_12_out_uop_lrs3 : _T_287 ? issue_slots_11_out_uop_lrs3 : issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2 = _T_288 ? issue_slots_12_out_uop_lrs2 : _T_287 ? issue_slots_11_out_uop_lrs2 : issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1 = _T_288 ? issue_slots_12_out_uop_lrs1 : _T_287 ? issue_slots_11_out_uop_lrs1 : issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst = _T_288 ? issue_slots_12_out_uop_ldst : _T_287 ? issue_slots_11_out_uop_ldst : issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst_is_rs1 = _T_288 ? issue_slots_12_out_uop_ldst_is_rs1 : _T_287 ? issue_slots_11_out_uop_ldst_is_rs1 : issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_csr_cmd = _T_288 ? issue_slots_12_out_uop_csr_cmd : _T_287 ? issue_slots_11_out_uop_csr_cmd : issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_flush_on_commit = _T_288 ? issue_slots_12_out_uop_flush_on_commit : _T_287 ? issue_slots_11_out_uop_flush_on_commit : issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_unique = _T_288 ? issue_slots_12_out_uop_is_unique : _T_287 ? issue_slots_11_out_uop_is_unique : issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_stq = _T_288 ? issue_slots_12_out_uop_uses_stq : _T_287 ? issue_slots_11_out_uop_uses_stq : issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_ldq = _T_288 ? issue_slots_12_out_uop_uses_ldq : _T_287 ? issue_slots_11_out_uop_uses_ldq : issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_signed = _T_288 ? issue_slots_12_out_uop_mem_signed : _T_287 ? issue_slots_11_out_uop_mem_signed : issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_size = _T_288 ? issue_slots_12_out_uop_mem_size : _T_287 ? issue_slots_11_out_uop_mem_size : issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_cmd = _T_288 ? issue_slots_12_out_uop_mem_cmd : _T_287 ? issue_slots_11_out_uop_mem_cmd : issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exc_cause = _T_288 ? issue_slots_12_out_uop_exc_cause : _T_287 ? issue_slots_11_out_uop_exc_cause : issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exception = _T_288 ? issue_slots_12_out_uop_exception : _T_287 ? issue_slots_11_out_uop_exception : issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stale_pdst = _T_288 ? issue_slots_12_out_uop_stale_pdst : _T_287 ? issue_slots_11_out_uop_stale_pdst : issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred_busy = _T_288 ? issue_slots_12_out_uop_ppred_busy : _T_287 ? issue_slots_11_out_uop_ppred_busy : issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3_busy = _T_288 ? issue_slots_12_out_uop_prs3_busy : _T_287 ? issue_slots_11_out_uop_prs3_busy : issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2_busy = _T_288 ? issue_slots_12_out_uop_prs2_busy : _T_287 ? issue_slots_11_out_uop_prs2_busy : issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1_busy = _T_288 ? issue_slots_12_out_uop_prs1_busy : _T_287 ? issue_slots_11_out_uop_prs1_busy : issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred = _T_288 ? issue_slots_12_out_uop_ppred : _T_287 ? issue_slots_11_out_uop_ppred : issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3 = _T_288 ? issue_slots_12_out_uop_prs3 : _T_287 ? issue_slots_11_out_uop_prs3 : issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2 = _T_288 ? issue_slots_12_out_uop_prs2 : _T_287 ? issue_slots_11_out_uop_prs2 : issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1 = _T_288 ? issue_slots_12_out_uop_prs1 : _T_287 ? issue_slots_11_out_uop_prs1 : issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pdst = _T_288 ? issue_slots_12_out_uop_pdst : _T_287 ? issue_slots_11_out_uop_pdst : issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rxq_idx = _T_288 ? issue_slots_12_out_uop_rxq_idx : _T_287 ? issue_slots_11_out_uop_rxq_idx : issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stq_idx = _T_288 ? issue_slots_12_out_uop_stq_idx : _T_287 ? issue_slots_11_out_uop_stq_idx : issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldq_idx = _T_288 ? issue_slots_12_out_uop_ldq_idx : _T_287 ? issue_slots_11_out_uop_ldq_idx : issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rob_idx = _T_288 ? issue_slots_12_out_uop_rob_idx : _T_287 ? issue_slots_11_out_uop_rob_idx : issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_vec = _T_288 ? issue_slots_12_out_uop_fp_ctrl_vec : _T_287 ? issue_slots_11_out_uop_fp_ctrl_vec : issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wflags = _T_288 ? issue_slots_12_out_uop_fp_ctrl_wflags : _T_287 ? issue_slots_11_out_uop_fp_ctrl_wflags : issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_sqrt = _T_288 ? issue_slots_12_out_uop_fp_ctrl_sqrt : _T_287 ? issue_slots_11_out_uop_fp_ctrl_sqrt : issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_div = _T_288 ? issue_slots_12_out_uop_fp_ctrl_div : _T_287 ? issue_slots_11_out_uop_fp_ctrl_div : issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fma = _T_288 ? issue_slots_12_out_uop_fp_ctrl_fma : _T_287 ? issue_slots_11_out_uop_fp_ctrl_fma : issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fastpipe = _T_288 ? issue_slots_12_out_uop_fp_ctrl_fastpipe : _T_287 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_toint = _T_288 ? issue_slots_12_out_uop_fp_ctrl_toint : _T_287 ? issue_slots_11_out_uop_fp_ctrl_toint : issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fromint = _T_288 ? issue_slots_12_out_uop_fp_ctrl_fromint : _T_287 ? issue_slots_11_out_uop_fp_ctrl_fromint : issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut = _T_288 ? issue_slots_12_out_uop_fp_ctrl_typeTagOut : _T_287 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn = _T_288 ? issue_slots_12_out_uop_fp_ctrl_typeTagIn : _T_287 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap23 = _T_288 ? issue_slots_12_out_uop_fp_ctrl_swap23 : _T_287 ? issue_slots_11_out_uop_fp_ctrl_swap23 : issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap12 = _T_288 ? issue_slots_12_out_uop_fp_ctrl_swap12 : _T_287 ? issue_slots_11_out_uop_fp_ctrl_swap12 : issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren3 = _T_288 ? issue_slots_12_out_uop_fp_ctrl_ren3 : _T_287 ? issue_slots_11_out_uop_fp_ctrl_ren3 : issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren2 = _T_288 ? issue_slots_12_out_uop_fp_ctrl_ren2 : _T_287 ? issue_slots_11_out_uop_fp_ctrl_ren2 : issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren1 = _T_288 ? issue_slots_12_out_uop_fp_ctrl_ren1 : _T_287 ? issue_slots_11_out_uop_fp_ctrl_ren1 : issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wen = _T_288 ? issue_slots_12_out_uop_fp_ctrl_wen : _T_287 ? issue_slots_11_out_uop_fp_ctrl_wen : issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ldst = _T_288 ? issue_slots_12_out_uop_fp_ctrl_ldst : _T_287 ? issue_slots_11_out_uop_fp_ctrl_ldst : issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op2_sel = _T_288 ? issue_slots_12_out_uop_op2_sel : _T_287 ? issue_slots_11_out_uop_op2_sel : issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op1_sel = _T_288 ? issue_slots_12_out_uop_op1_sel : _T_287 ? issue_slots_11_out_uop_op1_sel : issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_packed = _T_288 ? issue_slots_12_out_uop_imm_packed : _T_287 ? issue_slots_11_out_uop_imm_packed : issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pimm = _T_288 ? issue_slots_12_out_uop_pimm : _T_287 ? issue_slots_11_out_uop_pimm : issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_sel = _T_288 ? issue_slots_12_out_uop_imm_sel : _T_287 ? issue_slots_11_out_uop_imm_sel : issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_rename = _T_288 ? issue_slots_12_out_uop_imm_rename : _T_287 ? issue_slots_11_out_uop_imm_rename : issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_taken = _T_288 ? issue_slots_12_out_uop_taken : _T_287 ? issue_slots_11_out_uop_taken : issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pc_lob = _T_288 ? issue_slots_12_out_uop_pc_lob : _T_287 ? issue_slots_11_out_uop_pc_lob : issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_edge_inst = _T_288 ? issue_slots_12_out_uop_edge_inst : _T_287 ? issue_slots_11_out_uop_edge_inst : issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ftq_idx = _T_288 ? issue_slots_12_out_uop_ftq_idx : _T_287 ? issue_slots_11_out_uop_ftq_idx : issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_mov = _T_288 ? issue_slots_12_out_uop_is_mov : _T_287 ? issue_slots_11_out_uop_is_mov : issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rocc = _T_288 ? issue_slots_12_out_uop_is_rocc : _T_287 ? issue_slots_11_out_uop_is_rocc : issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sys_pc2epc = _T_288 ? issue_slots_12_out_uop_is_sys_pc2epc : _T_287 ? issue_slots_11_out_uop_is_sys_pc2epc : issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_eret = _T_288 ? issue_slots_12_out_uop_is_eret : _T_287 ? issue_slots_11_out_uop_is_eret : issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_amo = _T_288 ? issue_slots_12_out_uop_is_amo : _T_287 ? issue_slots_11_out_uop_is_amo : issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfence = _T_288 ? issue_slots_12_out_uop_is_sfence : _T_287 ? issue_slots_11_out_uop_is_sfence : issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fencei = _T_288 ? issue_slots_12_out_uop_is_fencei : _T_287 ? issue_slots_11_out_uop_is_fencei : issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fence = _T_288 ? issue_slots_12_out_uop_is_fence : _T_287 ? issue_slots_11_out_uop_is_fence : issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfb = _T_288 ? issue_slots_12_out_uop_is_sfb : _T_287 ? issue_slots_11_out_uop_is_sfb : issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_type = _T_288 ? issue_slots_12_out_uop_br_type : _T_287 ? issue_slots_11_out_uop_br_type : issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_tag = _T_288 ? issue_slots_12_out_uop_br_tag : _T_287 ? issue_slots_11_out_uop_br_tag : issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_mask = _T_288 ? issue_slots_12_out_uop_br_mask : _T_287 ? issue_slots_11_out_uop_br_mask : issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dis_col_sel = _T_288 ? issue_slots_12_out_uop_dis_col_sel : _T_287 ? issue_slots_11_out_uop_dis_col_sel : issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p3_bypass_hint = _T_288 ? issue_slots_12_out_uop_iw_p3_bypass_hint : _T_287 ? issue_slots_11_out_uop_iw_p3_bypass_hint : issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p2_bypass_hint = _T_288 ? issue_slots_12_out_uop_iw_p2_bypass_hint : _T_287 ? issue_slots_11_out_uop_iw_p2_bypass_hint : issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p1_bypass_hint = _T_288 ? issue_slots_12_out_uop_iw_p1_bypass_hint : _T_287 ? issue_slots_11_out_uop_iw_p1_bypass_hint : issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p2_speculative_child = _T_288 ? issue_slots_12_out_uop_iw_p2_speculative_child : _T_287 ? issue_slots_11_out_uop_iw_p2_speculative_child : issue_slots_10_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p1_speculative_child = _T_288 ? issue_slots_12_out_uop_iw_p1_speculative_child : _T_287 ? issue_slots_11_out_uop_iw_p1_speculative_child : issue_slots_10_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_issued = _T_288 ? issue_slots_12_out_uop_iw_issued : _T_287 ? issue_slots_11_out_uop_iw_issued : issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_0 = _T_288 ? issue_slots_12_out_uop_fu_code_0 : _T_287 ? issue_slots_11_out_uop_fu_code_0 : issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_1 = _T_288 ? issue_slots_12_out_uop_fu_code_1 : _T_287 ? issue_slots_11_out_uop_fu_code_1 : issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_2 = _T_288 ? issue_slots_12_out_uop_fu_code_2 : _T_287 ? issue_slots_11_out_uop_fu_code_2 : issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_3 = _T_288 ? issue_slots_12_out_uop_fu_code_3 : _T_287 ? issue_slots_11_out_uop_fu_code_3 : issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_4 = _T_288 ? issue_slots_12_out_uop_fu_code_4 : _T_287 ? issue_slots_11_out_uop_fu_code_4 : issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_5 = _T_288 ? issue_slots_12_out_uop_fu_code_5 : _T_287 ? issue_slots_11_out_uop_fu_code_5 : issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_6 = _T_288 ? issue_slots_12_out_uop_fu_code_6 : _T_287 ? issue_slots_11_out_uop_fu_code_6 : issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_7 = _T_288 ? issue_slots_12_out_uop_fu_code_7 : _T_287 ? issue_slots_11_out_uop_fu_code_7 : issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_8 = _T_288 ? issue_slots_12_out_uop_fu_code_8 : _T_287 ? issue_slots_11_out_uop_fu_code_8 : issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_9 = _T_288 ? issue_slots_12_out_uop_fu_code_9 : _T_287 ? issue_slots_11_out_uop_fu_code_9 : issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_0 = _T_288 ? issue_slots_12_out_uop_iq_type_0 : _T_287 ? issue_slots_11_out_uop_iq_type_0 : issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_1 = _T_288 ? issue_slots_12_out_uop_iq_type_1 : _T_287 ? issue_slots_11_out_uop_iq_type_1 : issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_2 = _T_288 ? issue_slots_12_out_uop_iq_type_2 : _T_287 ? issue_slots_11_out_uop_iq_type_2 : issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_3 = _T_288 ? issue_slots_12_out_uop_iq_type_3 : _T_287 ? issue_slots_11_out_uop_iq_type_3 : issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_pc = _T_288 ? issue_slots_12_out_uop_debug_pc : _T_287 ? issue_slots_11_out_uop_debug_pc : issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rvc = _T_288 ? issue_slots_12_out_uop_is_rvc : _T_287 ? issue_slots_11_out_uop_is_rvc : issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_inst = _T_288 ? issue_slots_12_out_uop_debug_inst : _T_287 ? issue_slots_11_out_uop_debug_inst : issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_inst = _T_288 ? issue_slots_12_out_uop_inst : _T_287 ? issue_slots_11_out_uop_inst : issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_9_clear_T = |shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_9_clear = _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_290 = shamts_oh_12 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_291 = shamts_oh_13 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_10_in_uop_valid = _T_291 ? issue_slots_13_will_be_valid : _T_290 ? issue_slots_12_will_be_valid : shamts_oh_11 == 3'h1 & issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_10_in_uop_bits_debug_tsrc = _T_291 ? issue_slots_13_out_uop_debug_tsrc : _T_290 ? issue_slots_12_out_uop_debug_tsrc : issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_fsrc = _T_291 ? issue_slots_13_out_uop_debug_fsrc : _T_290 ? issue_slots_12_out_uop_debug_fsrc : issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_xcpt_if = _T_291 ? issue_slots_13_out_uop_bp_xcpt_if : _T_290 ? issue_slots_12_out_uop_bp_xcpt_if : issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_debug_if = _T_291 ? issue_slots_13_out_uop_bp_debug_if : _T_290 ? issue_slots_12_out_uop_bp_debug_if : issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ma_if = _T_291 ? issue_slots_13_out_uop_xcpt_ma_if : _T_290 ? issue_slots_12_out_uop_xcpt_ma_if : issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ae_if = _T_291 ? issue_slots_13_out_uop_xcpt_ae_if : _T_290 ? issue_slots_12_out_uop_xcpt_ae_if : issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_pf_if = _T_291 ? issue_slots_13_out_uop_xcpt_pf_if : _T_290 ? issue_slots_12_out_uop_xcpt_pf_if : issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_typ = _T_291 ? issue_slots_13_out_uop_fp_typ : _T_290 ? issue_slots_12_out_uop_fp_typ : issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_rm = _T_291 ? issue_slots_13_out_uop_fp_rm : _T_290 ? issue_slots_12_out_uop_fp_rm : issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_val = _T_291 ? issue_slots_13_out_uop_fp_val : _T_290 ? issue_slots_12_out_uop_fp_val : issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_op = _T_291 ? issue_slots_13_out_uop_fcn_op : _T_290 ? issue_slots_12_out_uop_fcn_op : issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_dw = _T_291 ? issue_slots_13_out_uop_fcn_dw : _T_290 ? issue_slots_12_out_uop_fcn_dw : issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_frs3_en = _T_291 ? issue_slots_13_out_uop_frs3_en : _T_290 ? issue_slots_12_out_uop_frs3_en : issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2_rtype = _T_291 ? issue_slots_13_out_uop_lrs2_rtype : _T_290 ? issue_slots_12_out_uop_lrs2_rtype : issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1_rtype = _T_291 ? issue_slots_13_out_uop_lrs1_rtype : _T_290 ? issue_slots_12_out_uop_lrs1_rtype : issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dst_rtype = _T_291 ? issue_slots_13_out_uop_dst_rtype : _T_290 ? issue_slots_12_out_uop_dst_rtype : issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs3 = _T_291 ? issue_slots_13_out_uop_lrs3 : _T_290 ? issue_slots_12_out_uop_lrs3 : issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2 = _T_291 ? issue_slots_13_out_uop_lrs2 : _T_290 ? issue_slots_12_out_uop_lrs2 : issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1 = _T_291 ? issue_slots_13_out_uop_lrs1 : _T_290 ? issue_slots_12_out_uop_lrs1 : issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst = _T_291 ? issue_slots_13_out_uop_ldst : _T_290 ? issue_slots_12_out_uop_ldst : issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst_is_rs1 = _T_291 ? issue_slots_13_out_uop_ldst_is_rs1 : _T_290 ? issue_slots_12_out_uop_ldst_is_rs1 : issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_csr_cmd = _T_291 ? issue_slots_13_out_uop_csr_cmd : _T_290 ? issue_slots_12_out_uop_csr_cmd : issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_flush_on_commit = _T_291 ? issue_slots_13_out_uop_flush_on_commit : _T_290 ? issue_slots_12_out_uop_flush_on_commit : issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_unique = _T_291 ? issue_slots_13_out_uop_is_unique : _T_290 ? issue_slots_12_out_uop_is_unique : issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_stq = _T_291 ? issue_slots_13_out_uop_uses_stq : _T_290 ? issue_slots_12_out_uop_uses_stq : issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_ldq = _T_291 ? issue_slots_13_out_uop_uses_ldq : _T_290 ? issue_slots_12_out_uop_uses_ldq : issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_signed = _T_291 ? issue_slots_13_out_uop_mem_signed : _T_290 ? issue_slots_12_out_uop_mem_signed : issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_size = _T_291 ? issue_slots_13_out_uop_mem_size : _T_290 ? issue_slots_12_out_uop_mem_size : issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_cmd = _T_291 ? issue_slots_13_out_uop_mem_cmd : _T_290 ? issue_slots_12_out_uop_mem_cmd : issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exc_cause = _T_291 ? issue_slots_13_out_uop_exc_cause : _T_290 ? issue_slots_12_out_uop_exc_cause : issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exception = _T_291 ? issue_slots_13_out_uop_exception : _T_290 ? issue_slots_12_out_uop_exception : issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stale_pdst = _T_291 ? issue_slots_13_out_uop_stale_pdst : _T_290 ? issue_slots_12_out_uop_stale_pdst : issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred_busy = _T_291 ? issue_slots_13_out_uop_ppred_busy : _T_290 ? issue_slots_12_out_uop_ppred_busy : issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3_busy = _T_291 ? issue_slots_13_out_uop_prs3_busy : _T_290 ? issue_slots_12_out_uop_prs3_busy : issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2_busy = _T_291 ? issue_slots_13_out_uop_prs2_busy : _T_290 ? issue_slots_12_out_uop_prs2_busy : issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1_busy = _T_291 ? issue_slots_13_out_uop_prs1_busy : _T_290 ? issue_slots_12_out_uop_prs1_busy : issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred = _T_291 ? issue_slots_13_out_uop_ppred : _T_290 ? issue_slots_12_out_uop_ppred : issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3 = _T_291 ? issue_slots_13_out_uop_prs3 : _T_290 ? issue_slots_12_out_uop_prs3 : issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2 = _T_291 ? issue_slots_13_out_uop_prs2 : _T_290 ? issue_slots_12_out_uop_prs2 : issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1 = _T_291 ? issue_slots_13_out_uop_prs1 : _T_290 ? issue_slots_12_out_uop_prs1 : issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pdst = _T_291 ? issue_slots_13_out_uop_pdst : _T_290 ? issue_slots_12_out_uop_pdst : issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rxq_idx = _T_291 ? issue_slots_13_out_uop_rxq_idx : _T_290 ? issue_slots_12_out_uop_rxq_idx : issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stq_idx = _T_291 ? issue_slots_13_out_uop_stq_idx : _T_290 ? issue_slots_12_out_uop_stq_idx : issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldq_idx = _T_291 ? issue_slots_13_out_uop_ldq_idx : _T_290 ? issue_slots_12_out_uop_ldq_idx : issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rob_idx = _T_291 ? issue_slots_13_out_uop_rob_idx : _T_290 ? issue_slots_12_out_uop_rob_idx : issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_vec = _T_291 ? issue_slots_13_out_uop_fp_ctrl_vec : _T_290 ? issue_slots_12_out_uop_fp_ctrl_vec : issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wflags = _T_291 ? issue_slots_13_out_uop_fp_ctrl_wflags : _T_290 ? issue_slots_12_out_uop_fp_ctrl_wflags : issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_sqrt = _T_291 ? issue_slots_13_out_uop_fp_ctrl_sqrt : _T_290 ? issue_slots_12_out_uop_fp_ctrl_sqrt : issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_div = _T_291 ? issue_slots_13_out_uop_fp_ctrl_div : _T_290 ? issue_slots_12_out_uop_fp_ctrl_div : issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fma = _T_291 ? issue_slots_13_out_uop_fp_ctrl_fma : _T_290 ? issue_slots_12_out_uop_fp_ctrl_fma : issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fastpipe = _T_291 ? issue_slots_13_out_uop_fp_ctrl_fastpipe : _T_290 ? issue_slots_12_out_uop_fp_ctrl_fastpipe : issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_toint = _T_291 ? issue_slots_13_out_uop_fp_ctrl_toint : _T_290 ? issue_slots_12_out_uop_fp_ctrl_toint : issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fromint = _T_291 ? issue_slots_13_out_uop_fp_ctrl_fromint : _T_290 ? issue_slots_12_out_uop_fp_ctrl_fromint : issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut = _T_291 ? issue_slots_13_out_uop_fp_ctrl_typeTagOut : _T_290 ? issue_slots_12_out_uop_fp_ctrl_typeTagOut : issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn = _T_291 ? issue_slots_13_out_uop_fp_ctrl_typeTagIn : _T_290 ? issue_slots_12_out_uop_fp_ctrl_typeTagIn : issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap23 = _T_291 ? issue_slots_13_out_uop_fp_ctrl_swap23 : _T_290 ? issue_slots_12_out_uop_fp_ctrl_swap23 : issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap12 = _T_291 ? issue_slots_13_out_uop_fp_ctrl_swap12 : _T_290 ? issue_slots_12_out_uop_fp_ctrl_swap12 : issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren3 = _T_291 ? issue_slots_13_out_uop_fp_ctrl_ren3 : _T_290 ? issue_slots_12_out_uop_fp_ctrl_ren3 : issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren2 = _T_291 ? issue_slots_13_out_uop_fp_ctrl_ren2 : _T_290 ? issue_slots_12_out_uop_fp_ctrl_ren2 : issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren1 = _T_291 ? issue_slots_13_out_uop_fp_ctrl_ren1 : _T_290 ? issue_slots_12_out_uop_fp_ctrl_ren1 : issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wen = _T_291 ? issue_slots_13_out_uop_fp_ctrl_wen : _T_290 ? issue_slots_12_out_uop_fp_ctrl_wen : issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ldst = _T_291 ? issue_slots_13_out_uop_fp_ctrl_ldst : _T_290 ? issue_slots_12_out_uop_fp_ctrl_ldst : issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op2_sel = _T_291 ? issue_slots_13_out_uop_op2_sel : _T_290 ? issue_slots_12_out_uop_op2_sel : issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op1_sel = _T_291 ? issue_slots_13_out_uop_op1_sel : _T_290 ? issue_slots_12_out_uop_op1_sel : issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_packed = _T_291 ? issue_slots_13_out_uop_imm_packed : _T_290 ? issue_slots_12_out_uop_imm_packed : issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pimm = _T_291 ? issue_slots_13_out_uop_pimm : _T_290 ? issue_slots_12_out_uop_pimm : issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_sel = _T_291 ? issue_slots_13_out_uop_imm_sel : _T_290 ? issue_slots_12_out_uop_imm_sel : issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_rename = _T_291 ? issue_slots_13_out_uop_imm_rename : _T_290 ? issue_slots_12_out_uop_imm_rename : issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_taken = _T_291 ? issue_slots_13_out_uop_taken : _T_290 ? issue_slots_12_out_uop_taken : issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pc_lob = _T_291 ? issue_slots_13_out_uop_pc_lob : _T_290 ? issue_slots_12_out_uop_pc_lob : issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_edge_inst = _T_291 ? issue_slots_13_out_uop_edge_inst : _T_290 ? issue_slots_12_out_uop_edge_inst : issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ftq_idx = _T_291 ? issue_slots_13_out_uop_ftq_idx : _T_290 ? issue_slots_12_out_uop_ftq_idx : issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_mov = _T_291 ? issue_slots_13_out_uop_is_mov : _T_290 ? issue_slots_12_out_uop_is_mov : issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rocc = _T_291 ? issue_slots_13_out_uop_is_rocc : _T_290 ? issue_slots_12_out_uop_is_rocc : issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sys_pc2epc = _T_291 ? issue_slots_13_out_uop_is_sys_pc2epc : _T_290 ? issue_slots_12_out_uop_is_sys_pc2epc : issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_eret = _T_291 ? issue_slots_13_out_uop_is_eret : _T_290 ? issue_slots_12_out_uop_is_eret : issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_amo = _T_291 ? issue_slots_13_out_uop_is_amo : _T_290 ? issue_slots_12_out_uop_is_amo : issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfence = _T_291 ? issue_slots_13_out_uop_is_sfence : _T_290 ? issue_slots_12_out_uop_is_sfence : issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fencei = _T_291 ? issue_slots_13_out_uop_is_fencei : _T_290 ? issue_slots_12_out_uop_is_fencei : issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fence = _T_291 ? issue_slots_13_out_uop_is_fence : _T_290 ? issue_slots_12_out_uop_is_fence : issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfb = _T_291 ? issue_slots_13_out_uop_is_sfb : _T_290 ? issue_slots_12_out_uop_is_sfb : issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_type = _T_291 ? issue_slots_13_out_uop_br_type : _T_290 ? issue_slots_12_out_uop_br_type : issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_tag = _T_291 ? issue_slots_13_out_uop_br_tag : _T_290 ? issue_slots_12_out_uop_br_tag : issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_mask = _T_291 ? issue_slots_13_out_uop_br_mask : _T_290 ? issue_slots_12_out_uop_br_mask : issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dis_col_sel = _T_291 ? issue_slots_13_out_uop_dis_col_sel : _T_290 ? issue_slots_12_out_uop_dis_col_sel : issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p3_bypass_hint = _T_291 ? issue_slots_13_out_uop_iw_p3_bypass_hint : _T_290 ? issue_slots_12_out_uop_iw_p3_bypass_hint : issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p2_bypass_hint = _T_291 ? issue_slots_13_out_uop_iw_p2_bypass_hint : _T_290 ? issue_slots_12_out_uop_iw_p2_bypass_hint : issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p1_bypass_hint = _T_291 ? issue_slots_13_out_uop_iw_p1_bypass_hint : _T_290 ? issue_slots_12_out_uop_iw_p1_bypass_hint : issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p2_speculative_child = _T_291 ? issue_slots_13_out_uop_iw_p2_speculative_child : _T_290 ? issue_slots_12_out_uop_iw_p2_speculative_child : issue_slots_11_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p1_speculative_child = _T_291 ? issue_slots_13_out_uop_iw_p1_speculative_child : _T_290 ? issue_slots_12_out_uop_iw_p1_speculative_child : issue_slots_11_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_issued = _T_291 ? issue_slots_13_out_uop_iw_issued : _T_290 ? issue_slots_12_out_uop_iw_issued : issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_0 = _T_291 ? issue_slots_13_out_uop_fu_code_0 : _T_290 ? issue_slots_12_out_uop_fu_code_0 : issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_1 = _T_291 ? issue_slots_13_out_uop_fu_code_1 : _T_290 ? issue_slots_12_out_uop_fu_code_1 : issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_2 = _T_291 ? issue_slots_13_out_uop_fu_code_2 : _T_290 ? issue_slots_12_out_uop_fu_code_2 : issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_3 = _T_291 ? issue_slots_13_out_uop_fu_code_3 : _T_290 ? issue_slots_12_out_uop_fu_code_3 : issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_4 = _T_291 ? issue_slots_13_out_uop_fu_code_4 : _T_290 ? issue_slots_12_out_uop_fu_code_4 : issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_5 = _T_291 ? issue_slots_13_out_uop_fu_code_5 : _T_290 ? issue_slots_12_out_uop_fu_code_5 : issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_6 = _T_291 ? issue_slots_13_out_uop_fu_code_6 : _T_290 ? issue_slots_12_out_uop_fu_code_6 : issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_7 = _T_291 ? issue_slots_13_out_uop_fu_code_7 : _T_290 ? issue_slots_12_out_uop_fu_code_7 : issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_8 = _T_291 ? issue_slots_13_out_uop_fu_code_8 : _T_290 ? issue_slots_12_out_uop_fu_code_8 : issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_9 = _T_291 ? issue_slots_13_out_uop_fu_code_9 : _T_290 ? issue_slots_12_out_uop_fu_code_9 : issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_0 = _T_291 ? issue_slots_13_out_uop_iq_type_0 : _T_290 ? issue_slots_12_out_uop_iq_type_0 : issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_1 = _T_291 ? issue_slots_13_out_uop_iq_type_1 : _T_290 ? issue_slots_12_out_uop_iq_type_1 : issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_2 = _T_291 ? issue_slots_13_out_uop_iq_type_2 : _T_290 ? issue_slots_12_out_uop_iq_type_2 : issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_3 = _T_291 ? issue_slots_13_out_uop_iq_type_3 : _T_290 ? issue_slots_12_out_uop_iq_type_3 : issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_pc = _T_291 ? issue_slots_13_out_uop_debug_pc : _T_290 ? issue_slots_12_out_uop_debug_pc : issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rvc = _T_291 ? issue_slots_13_out_uop_is_rvc : _T_290 ? issue_slots_12_out_uop_is_rvc : issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_inst = _T_291 ? issue_slots_13_out_uop_debug_inst : _T_290 ? issue_slots_12_out_uop_debug_inst : issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_inst = _T_291 ? issue_slots_13_out_uop_inst : _T_290 ? issue_slots_12_out_uop_inst : issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_10_clear_T = |shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_10_clear = _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_293 = shamts_oh_13 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_294 = shamts_oh_14 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_11_in_uop_valid = _T_294 ? issue_slots_14_will_be_valid : _T_293 ? issue_slots_13_will_be_valid : shamts_oh_12 == 3'h1 & issue_slots_12_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_11_in_uop_bits_debug_tsrc = _T_294 ? issue_slots_14_out_uop_debug_tsrc : _T_293 ? issue_slots_13_out_uop_debug_tsrc : issue_slots_12_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_fsrc = _T_294 ? issue_slots_14_out_uop_debug_fsrc : _T_293 ? issue_slots_13_out_uop_debug_fsrc : issue_slots_12_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_xcpt_if = _T_294 ? issue_slots_14_out_uop_bp_xcpt_if : _T_293 ? issue_slots_13_out_uop_bp_xcpt_if : issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_debug_if = _T_294 ? issue_slots_14_out_uop_bp_debug_if : _T_293 ? issue_slots_13_out_uop_bp_debug_if : issue_slots_12_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ma_if = _T_294 ? issue_slots_14_out_uop_xcpt_ma_if : _T_293 ? issue_slots_13_out_uop_xcpt_ma_if : issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ae_if = _T_294 ? issue_slots_14_out_uop_xcpt_ae_if : _T_293 ? issue_slots_13_out_uop_xcpt_ae_if : issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_pf_if = _T_294 ? issue_slots_14_out_uop_xcpt_pf_if : _T_293 ? issue_slots_13_out_uop_xcpt_pf_if : issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_typ = _T_294 ? issue_slots_14_out_uop_fp_typ : _T_293 ? issue_slots_13_out_uop_fp_typ : issue_slots_12_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_rm = _T_294 ? issue_slots_14_out_uop_fp_rm : _T_293 ? issue_slots_13_out_uop_fp_rm : issue_slots_12_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_val = _T_294 ? issue_slots_14_out_uop_fp_val : _T_293 ? issue_slots_13_out_uop_fp_val : issue_slots_12_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_op = _T_294 ? issue_slots_14_out_uop_fcn_op : _T_293 ? issue_slots_13_out_uop_fcn_op : issue_slots_12_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_dw = _T_294 ? issue_slots_14_out_uop_fcn_dw : _T_293 ? issue_slots_13_out_uop_fcn_dw : issue_slots_12_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_frs3_en = _T_294 ? issue_slots_14_out_uop_frs3_en : _T_293 ? issue_slots_13_out_uop_frs3_en : issue_slots_12_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2_rtype = _T_294 ? issue_slots_14_out_uop_lrs2_rtype : _T_293 ? issue_slots_13_out_uop_lrs2_rtype : issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1_rtype = _T_294 ? issue_slots_14_out_uop_lrs1_rtype : _T_293 ? issue_slots_13_out_uop_lrs1_rtype : issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dst_rtype = _T_294 ? issue_slots_14_out_uop_dst_rtype : _T_293 ? issue_slots_13_out_uop_dst_rtype : issue_slots_12_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs3 = _T_294 ? issue_slots_14_out_uop_lrs3 : _T_293 ? issue_slots_13_out_uop_lrs3 : issue_slots_12_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2 = _T_294 ? issue_slots_14_out_uop_lrs2 : _T_293 ? issue_slots_13_out_uop_lrs2 : issue_slots_12_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1 = _T_294 ? issue_slots_14_out_uop_lrs1 : _T_293 ? issue_slots_13_out_uop_lrs1 : issue_slots_12_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst = _T_294 ? issue_slots_14_out_uop_ldst : _T_293 ? issue_slots_13_out_uop_ldst : issue_slots_12_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst_is_rs1 = _T_294 ? issue_slots_14_out_uop_ldst_is_rs1 : _T_293 ? issue_slots_13_out_uop_ldst_is_rs1 : issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_csr_cmd = _T_294 ? issue_slots_14_out_uop_csr_cmd : _T_293 ? issue_slots_13_out_uop_csr_cmd : issue_slots_12_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_flush_on_commit = _T_294 ? issue_slots_14_out_uop_flush_on_commit : _T_293 ? issue_slots_13_out_uop_flush_on_commit : issue_slots_12_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_unique = _T_294 ? issue_slots_14_out_uop_is_unique : _T_293 ? issue_slots_13_out_uop_is_unique : issue_slots_12_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_stq = _T_294 ? issue_slots_14_out_uop_uses_stq : _T_293 ? issue_slots_13_out_uop_uses_stq : issue_slots_12_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_ldq = _T_294 ? issue_slots_14_out_uop_uses_ldq : _T_293 ? issue_slots_13_out_uop_uses_ldq : issue_slots_12_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_signed = _T_294 ? issue_slots_14_out_uop_mem_signed : _T_293 ? issue_slots_13_out_uop_mem_signed : issue_slots_12_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_size = _T_294 ? issue_slots_14_out_uop_mem_size : _T_293 ? issue_slots_13_out_uop_mem_size : issue_slots_12_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_cmd = _T_294 ? issue_slots_14_out_uop_mem_cmd : _T_293 ? issue_slots_13_out_uop_mem_cmd : issue_slots_12_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exc_cause = _T_294 ? issue_slots_14_out_uop_exc_cause : _T_293 ? issue_slots_13_out_uop_exc_cause : issue_slots_12_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exception = _T_294 ? issue_slots_14_out_uop_exception : _T_293 ? issue_slots_13_out_uop_exception : issue_slots_12_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stale_pdst = _T_294 ? issue_slots_14_out_uop_stale_pdst : _T_293 ? issue_slots_13_out_uop_stale_pdst : issue_slots_12_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ppred_busy = _T_294 ? issue_slots_14_out_uop_ppred_busy : _T_293 ? issue_slots_13_out_uop_ppred_busy : issue_slots_12_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3_busy = _T_294 ? issue_slots_14_out_uop_prs3_busy : _T_293 ? issue_slots_13_out_uop_prs3_busy : issue_slots_12_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2_busy = _T_294 ? issue_slots_14_out_uop_prs2_busy : _T_293 ? issue_slots_13_out_uop_prs2_busy : issue_slots_12_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1_busy = _T_294 ? issue_slots_14_out_uop_prs1_busy : _T_293 ? issue_slots_13_out_uop_prs1_busy : issue_slots_12_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ppred = _T_294 ? issue_slots_14_out_uop_ppred : _T_293 ? issue_slots_13_out_uop_ppred : issue_slots_12_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3 = _T_294 ? issue_slots_14_out_uop_prs3 : _T_293 ? issue_slots_13_out_uop_prs3 : issue_slots_12_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2 = _T_294 ? issue_slots_14_out_uop_prs2 : _T_293 ? issue_slots_13_out_uop_prs2 : issue_slots_12_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1 = _T_294 ? issue_slots_14_out_uop_prs1 : _T_293 ? issue_slots_13_out_uop_prs1 : issue_slots_12_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pdst = _T_294 ? issue_slots_14_out_uop_pdst : _T_293 ? issue_slots_13_out_uop_pdst : issue_slots_12_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rxq_idx = _T_294 ? issue_slots_14_out_uop_rxq_idx : _T_293 ? issue_slots_13_out_uop_rxq_idx : issue_slots_12_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stq_idx = _T_294 ? issue_slots_14_out_uop_stq_idx : _T_293 ? issue_slots_13_out_uop_stq_idx : issue_slots_12_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldq_idx = _T_294 ? issue_slots_14_out_uop_ldq_idx : _T_293 ? issue_slots_13_out_uop_ldq_idx : issue_slots_12_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rob_idx = _T_294 ? issue_slots_14_out_uop_rob_idx : _T_293 ? issue_slots_13_out_uop_rob_idx : issue_slots_12_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_vec = _T_294 ? issue_slots_14_out_uop_fp_ctrl_vec : _T_293 ? issue_slots_13_out_uop_fp_ctrl_vec : issue_slots_12_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wflags = _T_294 ? issue_slots_14_out_uop_fp_ctrl_wflags : _T_293 ? issue_slots_13_out_uop_fp_ctrl_wflags : issue_slots_12_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_sqrt = _T_294 ? issue_slots_14_out_uop_fp_ctrl_sqrt : _T_293 ? issue_slots_13_out_uop_fp_ctrl_sqrt : issue_slots_12_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_div = _T_294 ? issue_slots_14_out_uop_fp_ctrl_div : _T_293 ? issue_slots_13_out_uop_fp_ctrl_div : issue_slots_12_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fma = _T_294 ? issue_slots_14_out_uop_fp_ctrl_fma : _T_293 ? issue_slots_13_out_uop_fp_ctrl_fma : issue_slots_12_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fastpipe = _T_294 ? issue_slots_14_out_uop_fp_ctrl_fastpipe : _T_293 ? issue_slots_13_out_uop_fp_ctrl_fastpipe : issue_slots_12_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_toint = _T_294 ? issue_slots_14_out_uop_fp_ctrl_toint : _T_293 ? issue_slots_13_out_uop_fp_ctrl_toint : issue_slots_12_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fromint = _T_294 ? issue_slots_14_out_uop_fp_ctrl_fromint : _T_293 ? issue_slots_13_out_uop_fp_ctrl_fromint : issue_slots_12_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut = _T_294 ? issue_slots_14_out_uop_fp_ctrl_typeTagOut : _T_293 ? issue_slots_13_out_uop_fp_ctrl_typeTagOut : issue_slots_12_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn = _T_294 ? issue_slots_14_out_uop_fp_ctrl_typeTagIn : _T_293 ? issue_slots_13_out_uop_fp_ctrl_typeTagIn : issue_slots_12_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap23 = _T_294 ? issue_slots_14_out_uop_fp_ctrl_swap23 : _T_293 ? issue_slots_13_out_uop_fp_ctrl_swap23 : issue_slots_12_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap12 = _T_294 ? issue_slots_14_out_uop_fp_ctrl_swap12 : _T_293 ? issue_slots_13_out_uop_fp_ctrl_swap12 : issue_slots_12_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren3 = _T_294 ? issue_slots_14_out_uop_fp_ctrl_ren3 : _T_293 ? issue_slots_13_out_uop_fp_ctrl_ren3 : issue_slots_12_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren2 = _T_294 ? issue_slots_14_out_uop_fp_ctrl_ren2 : _T_293 ? issue_slots_13_out_uop_fp_ctrl_ren2 : issue_slots_12_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren1 = _T_294 ? issue_slots_14_out_uop_fp_ctrl_ren1 : _T_293 ? issue_slots_13_out_uop_fp_ctrl_ren1 : issue_slots_12_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wen = _T_294 ? issue_slots_14_out_uop_fp_ctrl_wen : _T_293 ? issue_slots_13_out_uop_fp_ctrl_wen : issue_slots_12_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ldst = _T_294 ? issue_slots_14_out_uop_fp_ctrl_ldst : _T_293 ? issue_slots_13_out_uop_fp_ctrl_ldst : issue_slots_12_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op2_sel = _T_294 ? issue_slots_14_out_uop_op2_sel : _T_293 ? issue_slots_13_out_uop_op2_sel : issue_slots_12_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op1_sel = _T_294 ? issue_slots_14_out_uop_op1_sel : _T_293 ? issue_slots_13_out_uop_op1_sel : issue_slots_12_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_packed = _T_294 ? issue_slots_14_out_uop_imm_packed : _T_293 ? issue_slots_13_out_uop_imm_packed : issue_slots_12_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pimm = _T_294 ? issue_slots_14_out_uop_pimm : _T_293 ? issue_slots_13_out_uop_pimm : issue_slots_12_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_sel = _T_294 ? issue_slots_14_out_uop_imm_sel : _T_293 ? issue_slots_13_out_uop_imm_sel : issue_slots_12_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_rename = _T_294 ? issue_slots_14_out_uop_imm_rename : _T_293 ? issue_slots_13_out_uop_imm_rename : issue_slots_12_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_taken = _T_294 ? issue_slots_14_out_uop_taken : _T_293 ? issue_slots_13_out_uop_taken : issue_slots_12_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pc_lob = _T_294 ? issue_slots_14_out_uop_pc_lob : _T_293 ? issue_slots_13_out_uop_pc_lob : issue_slots_12_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_edge_inst = _T_294 ? issue_slots_14_out_uop_edge_inst : _T_293 ? issue_slots_13_out_uop_edge_inst : issue_slots_12_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ftq_idx = _T_294 ? issue_slots_14_out_uop_ftq_idx : _T_293 ? issue_slots_13_out_uop_ftq_idx : issue_slots_12_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_mov = _T_294 ? issue_slots_14_out_uop_is_mov : _T_293 ? issue_slots_13_out_uop_is_mov : issue_slots_12_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rocc = _T_294 ? issue_slots_14_out_uop_is_rocc : _T_293 ? issue_slots_13_out_uop_is_rocc : issue_slots_12_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sys_pc2epc = _T_294 ? issue_slots_14_out_uop_is_sys_pc2epc : _T_293 ? issue_slots_13_out_uop_is_sys_pc2epc : issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_eret = _T_294 ? issue_slots_14_out_uop_is_eret : _T_293 ? issue_slots_13_out_uop_is_eret : issue_slots_12_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_amo = _T_294 ? issue_slots_14_out_uop_is_amo : _T_293 ? issue_slots_13_out_uop_is_amo : issue_slots_12_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfence = _T_294 ? issue_slots_14_out_uop_is_sfence : _T_293 ? issue_slots_13_out_uop_is_sfence : issue_slots_12_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fencei = _T_294 ? issue_slots_14_out_uop_is_fencei : _T_293 ? issue_slots_13_out_uop_is_fencei : issue_slots_12_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fence = _T_294 ? issue_slots_14_out_uop_is_fence : _T_293 ? issue_slots_13_out_uop_is_fence : issue_slots_12_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfb = _T_294 ? issue_slots_14_out_uop_is_sfb : _T_293 ? issue_slots_13_out_uop_is_sfb : issue_slots_12_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_type = _T_294 ? issue_slots_14_out_uop_br_type : _T_293 ? issue_slots_13_out_uop_br_type : issue_slots_12_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_tag = _T_294 ? issue_slots_14_out_uop_br_tag : _T_293 ? issue_slots_13_out_uop_br_tag : issue_slots_12_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_mask = _T_294 ? issue_slots_14_out_uop_br_mask : _T_293 ? issue_slots_13_out_uop_br_mask : issue_slots_12_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dis_col_sel = _T_294 ? issue_slots_14_out_uop_dis_col_sel : _T_293 ? issue_slots_13_out_uop_dis_col_sel : issue_slots_12_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p3_bypass_hint = _T_294 ? issue_slots_14_out_uop_iw_p3_bypass_hint : _T_293 ? issue_slots_13_out_uop_iw_p3_bypass_hint : issue_slots_12_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p2_bypass_hint = _T_294 ? issue_slots_14_out_uop_iw_p2_bypass_hint : _T_293 ? issue_slots_13_out_uop_iw_p2_bypass_hint : issue_slots_12_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p1_bypass_hint = _T_294 ? issue_slots_14_out_uop_iw_p1_bypass_hint : _T_293 ? issue_slots_13_out_uop_iw_p1_bypass_hint : issue_slots_12_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p2_speculative_child = _T_294 ? issue_slots_14_out_uop_iw_p2_speculative_child : _T_293 ? issue_slots_13_out_uop_iw_p2_speculative_child : issue_slots_12_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p1_speculative_child = _T_294 ? issue_slots_14_out_uop_iw_p1_speculative_child : _T_293 ? issue_slots_13_out_uop_iw_p1_speculative_child : issue_slots_12_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_issued = _T_294 ? issue_slots_14_out_uop_iw_issued : _T_293 ? issue_slots_13_out_uop_iw_issued : issue_slots_12_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_0 = _T_294 ? issue_slots_14_out_uop_fu_code_0 : _T_293 ? issue_slots_13_out_uop_fu_code_0 : issue_slots_12_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_1 = _T_294 ? issue_slots_14_out_uop_fu_code_1 : _T_293 ? issue_slots_13_out_uop_fu_code_1 : issue_slots_12_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_2 = _T_294 ? issue_slots_14_out_uop_fu_code_2 : _T_293 ? issue_slots_13_out_uop_fu_code_2 : issue_slots_12_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_3 = _T_294 ? issue_slots_14_out_uop_fu_code_3 : _T_293 ? issue_slots_13_out_uop_fu_code_3 : issue_slots_12_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_4 = _T_294 ? issue_slots_14_out_uop_fu_code_4 : _T_293 ? issue_slots_13_out_uop_fu_code_4 : issue_slots_12_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_5 = _T_294 ? issue_slots_14_out_uop_fu_code_5 : _T_293 ? issue_slots_13_out_uop_fu_code_5 : issue_slots_12_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_6 = _T_294 ? issue_slots_14_out_uop_fu_code_6 : _T_293 ? issue_slots_13_out_uop_fu_code_6 : issue_slots_12_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_7 = _T_294 ? issue_slots_14_out_uop_fu_code_7 : _T_293 ? issue_slots_13_out_uop_fu_code_7 : issue_slots_12_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_8 = _T_294 ? issue_slots_14_out_uop_fu_code_8 : _T_293 ? issue_slots_13_out_uop_fu_code_8 : issue_slots_12_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_9 = _T_294 ? issue_slots_14_out_uop_fu_code_9 : _T_293 ? issue_slots_13_out_uop_fu_code_9 : issue_slots_12_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_0 = _T_294 ? issue_slots_14_out_uop_iq_type_0 : _T_293 ? issue_slots_13_out_uop_iq_type_0 : issue_slots_12_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_1 = _T_294 ? issue_slots_14_out_uop_iq_type_1 : _T_293 ? issue_slots_13_out_uop_iq_type_1 : issue_slots_12_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_2 = _T_294 ? issue_slots_14_out_uop_iq_type_2 : _T_293 ? issue_slots_13_out_uop_iq_type_2 : issue_slots_12_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_3 = _T_294 ? issue_slots_14_out_uop_iq_type_3 : _T_293 ? issue_slots_13_out_uop_iq_type_3 : issue_slots_12_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_pc = _T_294 ? issue_slots_14_out_uop_debug_pc : _T_293 ? issue_slots_13_out_uop_debug_pc : issue_slots_12_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rvc = _T_294 ? issue_slots_14_out_uop_is_rvc : _T_293 ? issue_slots_13_out_uop_is_rvc : issue_slots_12_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_inst = _T_294 ? issue_slots_14_out_uop_debug_inst : _T_293 ? issue_slots_13_out_uop_debug_inst : issue_slots_12_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_inst = _T_294 ? issue_slots_14_out_uop_inst : _T_293 ? issue_slots_13_out_uop_inst : issue_slots_12_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_11_clear_T = |shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_11_clear = _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_296 = shamts_oh_14 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_297 = shamts_oh_15 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_12_in_uop_valid = _T_297 ? issue_slots_15_will_be_valid : _T_296 ? issue_slots_14_will_be_valid : shamts_oh_13 == 3'h1 & issue_slots_13_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_12_in_uop_bits_debug_tsrc = _T_297 ? issue_slots_15_out_uop_debug_tsrc : _T_296 ? issue_slots_14_out_uop_debug_tsrc : issue_slots_13_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_fsrc = _T_297 ? issue_slots_15_out_uop_debug_fsrc : _T_296 ? issue_slots_14_out_uop_debug_fsrc : issue_slots_13_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_bp_xcpt_if = _T_297 ? issue_slots_15_out_uop_bp_xcpt_if : _T_296 ? issue_slots_14_out_uop_bp_xcpt_if : issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_bp_debug_if = _T_297 ? issue_slots_15_out_uop_bp_debug_if : _T_296 ? issue_slots_14_out_uop_bp_debug_if : issue_slots_13_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_ma_if = _T_297 ? issue_slots_15_out_uop_xcpt_ma_if : _T_296 ? issue_slots_14_out_uop_xcpt_ma_if : issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_ae_if = _T_297 ? issue_slots_15_out_uop_xcpt_ae_if : _T_296 ? issue_slots_14_out_uop_xcpt_ae_if : issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_pf_if = _T_297 ? issue_slots_15_out_uop_xcpt_pf_if : _T_296 ? issue_slots_14_out_uop_xcpt_pf_if : issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_typ = _T_297 ? issue_slots_15_out_uop_fp_typ : _T_296 ? issue_slots_14_out_uop_fp_typ : issue_slots_13_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_rm = _T_297 ? issue_slots_15_out_uop_fp_rm : _T_296 ? issue_slots_14_out_uop_fp_rm : issue_slots_13_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_val = _T_297 ? issue_slots_15_out_uop_fp_val : _T_296 ? issue_slots_14_out_uop_fp_val : issue_slots_13_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fcn_op = _T_297 ? issue_slots_15_out_uop_fcn_op : _T_296 ? issue_slots_14_out_uop_fcn_op : issue_slots_13_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fcn_dw = _T_297 ? issue_slots_15_out_uop_fcn_dw : _T_296 ? issue_slots_14_out_uop_fcn_dw : issue_slots_13_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_frs3_en = _T_297 ? issue_slots_15_out_uop_frs3_en : _T_296 ? issue_slots_14_out_uop_frs3_en : issue_slots_13_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs2_rtype = _T_297 ? issue_slots_15_out_uop_lrs2_rtype : _T_296 ? issue_slots_14_out_uop_lrs2_rtype : issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs1_rtype = _T_297 ? issue_slots_15_out_uop_lrs1_rtype : _T_296 ? issue_slots_14_out_uop_lrs1_rtype : issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_dst_rtype = _T_297 ? issue_slots_15_out_uop_dst_rtype : _T_296 ? issue_slots_14_out_uop_dst_rtype : issue_slots_13_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs3 = _T_297 ? issue_slots_15_out_uop_lrs3 : _T_296 ? issue_slots_14_out_uop_lrs3 : issue_slots_13_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs2 = _T_297 ? issue_slots_15_out_uop_lrs2 : _T_296 ? issue_slots_14_out_uop_lrs2 : issue_slots_13_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs1 = _T_297 ? issue_slots_15_out_uop_lrs1 : _T_296 ? issue_slots_14_out_uop_lrs1 : issue_slots_13_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldst = _T_297 ? issue_slots_15_out_uop_ldst : _T_296 ? issue_slots_14_out_uop_ldst : issue_slots_13_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldst_is_rs1 = _T_297 ? issue_slots_15_out_uop_ldst_is_rs1 : _T_296 ? issue_slots_14_out_uop_ldst_is_rs1 : issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_csr_cmd = _T_297 ? issue_slots_15_out_uop_csr_cmd : _T_296 ? issue_slots_14_out_uop_csr_cmd : issue_slots_13_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_flush_on_commit = _T_297 ? issue_slots_15_out_uop_flush_on_commit : _T_296 ? issue_slots_14_out_uop_flush_on_commit : issue_slots_13_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_unique = _T_297 ? issue_slots_15_out_uop_is_unique : _T_296 ? issue_slots_14_out_uop_is_unique : issue_slots_13_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_uses_stq = _T_297 ? issue_slots_15_out_uop_uses_stq : _T_296 ? issue_slots_14_out_uop_uses_stq : issue_slots_13_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_uses_ldq = _T_297 ? issue_slots_15_out_uop_uses_ldq : _T_296 ? issue_slots_14_out_uop_uses_ldq : issue_slots_13_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_signed = _T_297 ? issue_slots_15_out_uop_mem_signed : _T_296 ? issue_slots_14_out_uop_mem_signed : issue_slots_13_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_size = _T_297 ? issue_slots_15_out_uop_mem_size : _T_296 ? issue_slots_14_out_uop_mem_size : issue_slots_13_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_cmd = _T_297 ? issue_slots_15_out_uop_mem_cmd : _T_296 ? issue_slots_14_out_uop_mem_cmd : issue_slots_13_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_exc_cause = _T_297 ? issue_slots_15_out_uop_exc_cause : _T_296 ? issue_slots_14_out_uop_exc_cause : issue_slots_13_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_exception = _T_297 ? issue_slots_15_out_uop_exception : _T_296 ? issue_slots_14_out_uop_exception : issue_slots_13_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_stale_pdst = _T_297 ? issue_slots_15_out_uop_stale_pdst : _T_296 ? issue_slots_14_out_uop_stale_pdst : issue_slots_13_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ppred_busy = _T_297 ? issue_slots_15_out_uop_ppred_busy : _T_296 ? issue_slots_14_out_uop_ppred_busy : issue_slots_13_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs3_busy = _T_297 ? issue_slots_15_out_uop_prs3_busy : _T_296 ? issue_slots_14_out_uop_prs3_busy : issue_slots_13_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs2_busy = _T_297 ? issue_slots_15_out_uop_prs2_busy : _T_296 ? issue_slots_14_out_uop_prs2_busy : issue_slots_13_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs1_busy = _T_297 ? issue_slots_15_out_uop_prs1_busy : _T_296 ? issue_slots_14_out_uop_prs1_busy : issue_slots_13_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ppred = _T_297 ? issue_slots_15_out_uop_ppred : _T_296 ? issue_slots_14_out_uop_ppred : issue_slots_13_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs3 = _T_297 ? issue_slots_15_out_uop_prs3 : _T_296 ? issue_slots_14_out_uop_prs3 : issue_slots_13_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs2 = _T_297 ? issue_slots_15_out_uop_prs2 : _T_296 ? issue_slots_14_out_uop_prs2 : issue_slots_13_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs1 = _T_297 ? issue_slots_15_out_uop_prs1 : _T_296 ? issue_slots_14_out_uop_prs1 : issue_slots_13_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pdst = _T_297 ? issue_slots_15_out_uop_pdst : _T_296 ? issue_slots_14_out_uop_pdst : issue_slots_13_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_rxq_idx = _T_297 ? issue_slots_15_out_uop_rxq_idx : _T_296 ? issue_slots_14_out_uop_rxq_idx : issue_slots_13_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_stq_idx = _T_297 ? issue_slots_15_out_uop_stq_idx : _T_296 ? issue_slots_14_out_uop_stq_idx : issue_slots_13_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldq_idx = _T_297 ? issue_slots_15_out_uop_ldq_idx : _T_296 ? issue_slots_14_out_uop_ldq_idx : issue_slots_13_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_rob_idx = _T_297 ? issue_slots_15_out_uop_rob_idx : _T_296 ? issue_slots_14_out_uop_rob_idx : issue_slots_13_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_vec = _T_297 ? issue_slots_15_out_uop_fp_ctrl_vec : _T_296 ? issue_slots_14_out_uop_fp_ctrl_vec : issue_slots_13_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_wflags = _T_297 ? issue_slots_15_out_uop_fp_ctrl_wflags : _T_296 ? issue_slots_14_out_uop_fp_ctrl_wflags : issue_slots_13_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_sqrt = _T_297 ? issue_slots_15_out_uop_fp_ctrl_sqrt : _T_296 ? issue_slots_14_out_uop_fp_ctrl_sqrt : issue_slots_13_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_div = _T_297 ? issue_slots_15_out_uop_fp_ctrl_div : _T_296 ? issue_slots_14_out_uop_fp_ctrl_div : issue_slots_13_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fma = _T_297 ? issue_slots_15_out_uop_fp_ctrl_fma : _T_296 ? issue_slots_14_out_uop_fp_ctrl_fma : issue_slots_13_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fastpipe = _T_297 ? issue_slots_15_out_uop_fp_ctrl_fastpipe : _T_296 ? issue_slots_14_out_uop_fp_ctrl_fastpipe : issue_slots_13_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_toint = _T_297 ? issue_slots_15_out_uop_fp_ctrl_toint : _T_296 ? issue_slots_14_out_uop_fp_ctrl_toint : issue_slots_13_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fromint = _T_297 ? issue_slots_15_out_uop_fp_ctrl_fromint : _T_296 ? issue_slots_14_out_uop_fp_ctrl_fromint : issue_slots_13_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut = _T_297 ? issue_slots_15_out_uop_fp_ctrl_typeTagOut : _T_296 ? issue_slots_14_out_uop_fp_ctrl_typeTagOut : issue_slots_13_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn = _T_297 ? issue_slots_15_out_uop_fp_ctrl_typeTagIn : _T_296 ? issue_slots_14_out_uop_fp_ctrl_typeTagIn : issue_slots_13_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_swap23 = _T_297 ? issue_slots_15_out_uop_fp_ctrl_swap23 : _T_296 ? issue_slots_14_out_uop_fp_ctrl_swap23 : issue_slots_13_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_swap12 = _T_297 ? issue_slots_15_out_uop_fp_ctrl_swap12 : _T_296 ? issue_slots_14_out_uop_fp_ctrl_swap12 : issue_slots_13_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren3 = _T_297 ? issue_slots_15_out_uop_fp_ctrl_ren3 : _T_296 ? issue_slots_14_out_uop_fp_ctrl_ren3 : issue_slots_13_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren2 = _T_297 ? issue_slots_15_out_uop_fp_ctrl_ren2 : _T_296 ? issue_slots_14_out_uop_fp_ctrl_ren2 : issue_slots_13_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren1 = _T_297 ? issue_slots_15_out_uop_fp_ctrl_ren1 : _T_296 ? issue_slots_14_out_uop_fp_ctrl_ren1 : issue_slots_13_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_wen = _T_297 ? issue_slots_15_out_uop_fp_ctrl_wen : _T_296 ? issue_slots_14_out_uop_fp_ctrl_wen : issue_slots_13_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ldst = _T_297 ? issue_slots_15_out_uop_fp_ctrl_ldst : _T_296 ? issue_slots_14_out_uop_fp_ctrl_ldst : issue_slots_13_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_op2_sel = _T_297 ? issue_slots_15_out_uop_op2_sel : _T_296 ? issue_slots_14_out_uop_op2_sel : issue_slots_13_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_op1_sel = _T_297 ? issue_slots_15_out_uop_op1_sel : _T_296 ? issue_slots_14_out_uop_op1_sel : issue_slots_13_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_packed = _T_297 ? issue_slots_15_out_uop_imm_packed : _T_296 ? issue_slots_14_out_uop_imm_packed : issue_slots_13_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pimm = _T_297 ? issue_slots_15_out_uop_pimm : _T_296 ? issue_slots_14_out_uop_pimm : issue_slots_13_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_sel = _T_297 ? issue_slots_15_out_uop_imm_sel : _T_296 ? issue_slots_14_out_uop_imm_sel : issue_slots_13_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_rename = _T_297 ? issue_slots_15_out_uop_imm_rename : _T_296 ? issue_slots_14_out_uop_imm_rename : issue_slots_13_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_taken = _T_297 ? issue_slots_15_out_uop_taken : _T_296 ? issue_slots_14_out_uop_taken : issue_slots_13_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pc_lob = _T_297 ? issue_slots_15_out_uop_pc_lob : _T_296 ? issue_slots_14_out_uop_pc_lob : issue_slots_13_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_edge_inst = _T_297 ? issue_slots_15_out_uop_edge_inst : _T_296 ? issue_slots_14_out_uop_edge_inst : issue_slots_13_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ftq_idx = _T_297 ? issue_slots_15_out_uop_ftq_idx : _T_296 ? issue_slots_14_out_uop_ftq_idx : issue_slots_13_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_mov = _T_297 ? issue_slots_15_out_uop_is_mov : _T_296 ? issue_slots_14_out_uop_is_mov : issue_slots_13_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_rocc = _T_297 ? issue_slots_15_out_uop_is_rocc : _T_296 ? issue_slots_14_out_uop_is_rocc : issue_slots_13_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sys_pc2epc = _T_297 ? issue_slots_15_out_uop_is_sys_pc2epc : _T_296 ? issue_slots_14_out_uop_is_sys_pc2epc : issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_eret = _T_297 ? issue_slots_15_out_uop_is_eret : _T_296 ? issue_slots_14_out_uop_is_eret : issue_slots_13_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_amo = _T_297 ? issue_slots_15_out_uop_is_amo : _T_296 ? issue_slots_14_out_uop_is_amo : issue_slots_13_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sfence = _T_297 ? issue_slots_15_out_uop_is_sfence : _T_296 ? issue_slots_14_out_uop_is_sfence : issue_slots_13_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_fencei = _T_297 ? issue_slots_15_out_uop_is_fencei : _T_296 ? issue_slots_14_out_uop_is_fencei : issue_slots_13_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_fence = _T_297 ? issue_slots_15_out_uop_is_fence : _T_296 ? issue_slots_14_out_uop_is_fence : issue_slots_13_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sfb = _T_297 ? issue_slots_15_out_uop_is_sfb : _T_296 ? issue_slots_14_out_uop_is_sfb : issue_slots_13_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_type = _T_297 ? issue_slots_15_out_uop_br_type : _T_296 ? issue_slots_14_out_uop_br_type : issue_slots_13_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_tag = _T_297 ? issue_slots_15_out_uop_br_tag : _T_296 ? issue_slots_14_out_uop_br_tag : issue_slots_13_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_mask = _T_297 ? issue_slots_15_out_uop_br_mask : _T_296 ? issue_slots_14_out_uop_br_mask : issue_slots_13_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_dis_col_sel = _T_297 ? issue_slots_15_out_uop_dis_col_sel : _T_296 ? issue_slots_14_out_uop_dis_col_sel : issue_slots_13_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p3_bypass_hint = _T_297 ? issue_slots_15_out_uop_iw_p3_bypass_hint : _T_296 ? issue_slots_14_out_uop_iw_p3_bypass_hint : issue_slots_13_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p2_bypass_hint = _T_297 ? issue_slots_15_out_uop_iw_p2_bypass_hint : _T_296 ? issue_slots_14_out_uop_iw_p2_bypass_hint : issue_slots_13_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p1_bypass_hint = _T_297 ? issue_slots_15_out_uop_iw_p1_bypass_hint : _T_296 ? issue_slots_14_out_uop_iw_p1_bypass_hint : issue_slots_13_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p2_speculative_child = _T_297 ? issue_slots_15_out_uop_iw_p2_speculative_child : _T_296 ? issue_slots_14_out_uop_iw_p2_speculative_child : issue_slots_13_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p1_speculative_child = _T_297 ? issue_slots_15_out_uop_iw_p1_speculative_child : _T_296 ? issue_slots_14_out_uop_iw_p1_speculative_child : issue_slots_13_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_issued = _T_297 ? issue_slots_15_out_uop_iw_issued : _T_296 ? issue_slots_14_out_uop_iw_issued : issue_slots_13_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_0 = _T_297 ? issue_slots_15_out_uop_fu_code_0 : _T_296 ? issue_slots_14_out_uop_fu_code_0 : issue_slots_13_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_1 = _T_297 ? issue_slots_15_out_uop_fu_code_1 : _T_296 ? issue_slots_14_out_uop_fu_code_1 : issue_slots_13_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_2 = _T_297 ? issue_slots_15_out_uop_fu_code_2 : _T_296 ? issue_slots_14_out_uop_fu_code_2 : issue_slots_13_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_3 = _T_297 ? issue_slots_15_out_uop_fu_code_3 : _T_296 ? issue_slots_14_out_uop_fu_code_3 : issue_slots_13_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_4 = _T_297 ? issue_slots_15_out_uop_fu_code_4 : _T_296 ? issue_slots_14_out_uop_fu_code_4 : issue_slots_13_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_5 = _T_297 ? issue_slots_15_out_uop_fu_code_5 : _T_296 ? issue_slots_14_out_uop_fu_code_5 : issue_slots_13_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_6 = _T_297 ? issue_slots_15_out_uop_fu_code_6 : _T_296 ? issue_slots_14_out_uop_fu_code_6 : issue_slots_13_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_7 = _T_297 ? issue_slots_15_out_uop_fu_code_7 : _T_296 ? issue_slots_14_out_uop_fu_code_7 : issue_slots_13_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_8 = _T_297 ? issue_slots_15_out_uop_fu_code_8 : _T_296 ? issue_slots_14_out_uop_fu_code_8 : issue_slots_13_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_9 = _T_297 ? issue_slots_15_out_uop_fu_code_9 : _T_296 ? issue_slots_14_out_uop_fu_code_9 : issue_slots_13_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_0 = _T_297 ? issue_slots_15_out_uop_iq_type_0 : _T_296 ? issue_slots_14_out_uop_iq_type_0 : issue_slots_13_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_1 = _T_297 ? issue_slots_15_out_uop_iq_type_1 : _T_296 ? issue_slots_14_out_uop_iq_type_1 : issue_slots_13_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_2 = _T_297 ? issue_slots_15_out_uop_iq_type_2 : _T_296 ? issue_slots_14_out_uop_iq_type_2 : issue_slots_13_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_3 = _T_297 ? issue_slots_15_out_uop_iq_type_3 : _T_296 ? issue_slots_14_out_uop_iq_type_3 : issue_slots_13_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_pc = _T_297 ? issue_slots_15_out_uop_debug_pc : _T_296 ? issue_slots_14_out_uop_debug_pc : issue_slots_13_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_rvc = _T_297 ? issue_slots_15_out_uop_is_rvc : _T_296 ? issue_slots_14_out_uop_is_rvc : issue_slots_13_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_inst = _T_297 ? issue_slots_15_out_uop_debug_inst : _T_296 ? issue_slots_14_out_uop_debug_inst : issue_slots_13_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_inst = _T_297 ? issue_slots_15_out_uop_inst : _T_296 ? issue_slots_14_out_uop_inst : issue_slots_13_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_12_clear_T = |shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_12_clear = _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_299 = shamts_oh_15 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_300 = shamts_oh_16 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_13_in_uop_valid = _T_300 ? will_be_valid_16 : _T_299 ? issue_slots_15_will_be_valid : shamts_oh_14 == 3'h1 & issue_slots_14_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_13_in_uop_bits_debug_tsrc = _T_300 ? io_dis_uops_0_bits_debug_tsrc_0 : _T_299 ? issue_slots_15_out_uop_debug_tsrc : issue_slots_14_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_fsrc = _T_300 ? io_dis_uops_0_bits_debug_fsrc_0 : _T_299 ? issue_slots_15_out_uop_debug_fsrc : issue_slots_14_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_bp_xcpt_if = _T_300 ? io_dis_uops_0_bits_bp_xcpt_if_0 : _T_299 ? issue_slots_15_out_uop_bp_xcpt_if : issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_bp_debug_if = _T_300 ? io_dis_uops_0_bits_bp_debug_if_0 : _T_299 ? issue_slots_15_out_uop_bp_debug_if : issue_slots_14_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_ma_if = _T_300 ? io_dis_uops_0_bits_xcpt_ma_if_0 : _T_299 ? issue_slots_15_out_uop_xcpt_ma_if : issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_ae_if = _T_300 ? io_dis_uops_0_bits_xcpt_ae_if_0 : _T_299 ? issue_slots_15_out_uop_xcpt_ae_if : issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_pf_if = _T_300 ? io_dis_uops_0_bits_xcpt_pf_if_0 : _T_299 ? issue_slots_15_out_uop_xcpt_pf_if : issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_typ = _T_300 ? io_dis_uops_0_bits_fp_typ_0 : _T_299 ? issue_slots_15_out_uop_fp_typ : issue_slots_14_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_rm = _T_300 ? io_dis_uops_0_bits_fp_rm_0 : _T_299 ? issue_slots_15_out_uop_fp_rm : issue_slots_14_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_val = _T_300 ? io_dis_uops_0_bits_fp_val_0 : _T_299 ? issue_slots_15_out_uop_fp_val : issue_slots_14_out_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fcn_op = _T_300 ? io_dis_uops_0_bits_fcn_op_0 : _T_299 ? issue_slots_15_out_uop_fcn_op : issue_slots_14_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fcn_dw = _T_300 ? io_dis_uops_0_bits_fcn_dw_0 : _T_299 ? issue_slots_15_out_uop_fcn_dw : issue_slots_14_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_frs3_en = _T_300 ? io_dis_uops_0_bits_frs3_en_0 : _T_299 ? issue_slots_15_out_uop_frs3_en : issue_slots_14_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs2_rtype = _T_300 ? io_dis_uops_0_bits_lrs2_rtype_0 : _T_299 ? issue_slots_15_out_uop_lrs2_rtype : issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs1_rtype = _T_300 ? io_dis_uops_0_bits_lrs1_rtype_0 : _T_299 ? issue_slots_15_out_uop_lrs1_rtype : issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_dst_rtype = _T_300 ? io_dis_uops_0_bits_dst_rtype_0 : _T_299 ? issue_slots_15_out_uop_dst_rtype : issue_slots_14_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs3 = _T_300 ? io_dis_uops_0_bits_lrs3_0 : _T_299 ? issue_slots_15_out_uop_lrs3 : issue_slots_14_out_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs2 = _T_300 ? io_dis_uops_0_bits_lrs2_0 : _T_299 ? issue_slots_15_out_uop_lrs2 : issue_slots_14_out_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs1 = _T_300 ? io_dis_uops_0_bits_lrs1_0 : _T_299 ? issue_slots_15_out_uop_lrs1 : issue_slots_14_out_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldst = _T_300 ? io_dis_uops_0_bits_ldst_0 : _T_299 ? issue_slots_15_out_uop_ldst : issue_slots_14_out_uop_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldst_is_rs1 = _T_300 ? io_dis_uops_0_bits_ldst_is_rs1_0 : _T_299 ? issue_slots_15_out_uop_ldst_is_rs1 : issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_csr_cmd = _T_300 ? io_dis_uops_0_bits_csr_cmd_0 : _T_299 ? issue_slots_15_out_uop_csr_cmd : issue_slots_14_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_flush_on_commit = _T_300 ? io_dis_uops_0_bits_flush_on_commit_0 : _T_299 ? issue_slots_15_out_uop_flush_on_commit : issue_slots_14_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_unique = _T_300 ? io_dis_uops_0_bits_is_unique_0 : _T_299 ? issue_slots_15_out_uop_is_unique : issue_slots_14_out_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_uses_stq = _T_300 ? io_dis_uops_0_bits_uses_stq_0 : _T_299 ? issue_slots_15_out_uop_uses_stq : issue_slots_14_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_uses_ldq = _T_300 ? io_dis_uops_0_bits_uses_ldq_0 : _T_299 ? issue_slots_15_out_uop_uses_ldq : issue_slots_14_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_signed = _T_300 ? io_dis_uops_0_bits_mem_signed_0 : _T_299 ? issue_slots_15_out_uop_mem_signed : issue_slots_14_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_size = _T_300 ? io_dis_uops_0_bits_mem_size_0 : _T_299 ? issue_slots_15_out_uop_mem_size : issue_slots_14_out_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_cmd = _T_300 ? io_dis_uops_0_bits_mem_cmd_0 : _T_299 ? issue_slots_15_out_uop_mem_cmd : issue_slots_14_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_exc_cause = _T_300 ? io_dis_uops_0_bits_exc_cause_0 : _T_299 ? issue_slots_15_out_uop_exc_cause : issue_slots_14_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_exception = _T_300 ? io_dis_uops_0_bits_exception_0 : _T_299 ? issue_slots_15_out_uop_exception : issue_slots_14_out_uop_exception; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_stale_pdst = _T_300 ? io_dis_uops_0_bits_stale_pdst_0 : _T_299 ? issue_slots_15_out_uop_stale_pdst : issue_slots_14_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ppred_busy = _T_300 ? _WIRE_ppred_busy : _T_299 ? issue_slots_15_out_uop_ppred_busy : issue_slots_14_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:35:17, :80:96, :81:30, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs3_busy = _T_300 ? _WIRE_prs3_busy : _T_299 ? issue_slots_15_out_uop_prs3_busy : issue_slots_14_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:35:17, :76:38, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs2_busy = _T_300 ? _WIRE_prs2_busy : _T_299 ? issue_slots_15_out_uop_prs2_busy : issue_slots_14_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:65:38, :71:116, :72:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs1_busy = _T_300 ? _WIRE_prs1_busy : _T_299 ? issue_slots_15_out_uop_prs1_busy : issue_slots_14_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:57:38, :62:116, :63:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ppred = _T_300 ? io_dis_uops_0_bits_ppred_0 : _T_299 ? issue_slots_15_out_uop_ppred : issue_slots_14_out_uop_ppred; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs3 = _T_300 ? io_dis_uops_0_bits_prs3_0 : _T_299 ? issue_slots_15_out_uop_prs3 : issue_slots_14_out_uop_prs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs2 = _T_300 ? io_dis_uops_0_bits_prs2_0 : _T_299 ? issue_slots_15_out_uop_prs2 : issue_slots_14_out_uop_prs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs1 = _T_300 ? io_dis_uops_0_bits_prs1_0 : _T_299 ? issue_slots_15_out_uop_prs1 : issue_slots_14_out_uop_prs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pdst = _T_300 ? io_dis_uops_0_bits_pdst_0 : _T_299 ? issue_slots_15_out_uop_pdst : issue_slots_14_out_uop_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_rxq_idx = _T_300 ? io_dis_uops_0_bits_rxq_idx_0 : _T_299 ? issue_slots_15_out_uop_rxq_idx : issue_slots_14_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_stq_idx = _T_300 ? io_dis_uops_0_bits_stq_idx_0 : _T_299 ? issue_slots_15_out_uop_stq_idx : issue_slots_14_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldq_idx = _T_300 ? io_dis_uops_0_bits_ldq_idx_0 : _T_299 ? issue_slots_15_out_uop_ldq_idx : issue_slots_14_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_rob_idx = _T_300 ? io_dis_uops_0_bits_rob_idx_0 : _T_299 ? issue_slots_15_out_uop_rob_idx : issue_slots_14_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_vec = _T_300 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_vec : issue_slots_14_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_wflags = _T_300 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_wflags : issue_slots_14_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_sqrt = _T_300 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_sqrt : issue_slots_14_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_div = _T_300 ? io_dis_uops_0_bits_fp_ctrl_div_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_div : issue_slots_14_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fma = _T_300 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_fma : issue_slots_14_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fastpipe = _T_300 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_fastpipe : issue_slots_14_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_toint = _T_300 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_toint : issue_slots_14_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fromint = _T_300 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_fromint : issue_slots_14_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut = _T_300 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_typeTagOut : issue_slots_14_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn = _T_300 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_typeTagIn : issue_slots_14_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_swap23 = _T_300 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_swap23 : issue_slots_14_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_swap12 = _T_300 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_swap12 : issue_slots_14_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren3 = _T_300 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_ren3 : issue_slots_14_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren2 = _T_300 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_ren2 : issue_slots_14_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren1 = _T_300 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_ren1 : issue_slots_14_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_wen = _T_300 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_wen : issue_slots_14_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ldst = _T_300 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : _T_299 ? issue_slots_15_out_uop_fp_ctrl_ldst : issue_slots_14_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_op2_sel = _T_300 ? io_dis_uops_0_bits_op2_sel_0 : _T_299 ? issue_slots_15_out_uop_op2_sel : issue_slots_14_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_op1_sel = _T_300 ? io_dis_uops_0_bits_op1_sel_0 : _T_299 ? issue_slots_15_out_uop_op1_sel : issue_slots_14_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_packed = _T_300 ? io_dis_uops_0_bits_imm_packed_0 : _T_299 ? issue_slots_15_out_uop_imm_packed : issue_slots_14_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pimm = _T_300 ? io_dis_uops_0_bits_pimm_0 : _T_299 ? issue_slots_15_out_uop_pimm : issue_slots_14_out_uop_pimm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_sel = _T_300 ? io_dis_uops_0_bits_imm_sel_0 : _T_299 ? issue_slots_15_out_uop_imm_sel : issue_slots_14_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_rename = _T_300 ? io_dis_uops_0_bits_imm_rename_0 : _T_299 ? issue_slots_15_out_uop_imm_rename : issue_slots_14_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_taken = _T_300 ? io_dis_uops_0_bits_taken_0 : _T_299 ? issue_slots_15_out_uop_taken : issue_slots_14_out_uop_taken; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pc_lob = _T_300 ? io_dis_uops_0_bits_pc_lob_0 : _T_299 ? issue_slots_15_out_uop_pc_lob : issue_slots_14_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_edge_inst = _T_300 ? io_dis_uops_0_bits_edge_inst_0 : _T_299 ? issue_slots_15_out_uop_edge_inst : issue_slots_14_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ftq_idx = _T_300 ? io_dis_uops_0_bits_ftq_idx_0 : _T_299 ? issue_slots_15_out_uop_ftq_idx : issue_slots_14_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_mov = _T_300 ? io_dis_uops_0_bits_is_mov_0 : _T_299 ? issue_slots_15_out_uop_is_mov : issue_slots_14_out_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_rocc = _T_300 ? io_dis_uops_0_bits_is_rocc_0 : _T_299 ? issue_slots_15_out_uop_is_rocc : issue_slots_14_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sys_pc2epc = _T_300 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : _T_299 ? issue_slots_15_out_uop_is_sys_pc2epc : issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_eret = _T_300 ? io_dis_uops_0_bits_is_eret_0 : _T_299 ? issue_slots_15_out_uop_is_eret : issue_slots_14_out_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_amo = _T_300 ? io_dis_uops_0_bits_is_amo_0 : _T_299 ? issue_slots_15_out_uop_is_amo : issue_slots_14_out_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sfence = _T_300 ? io_dis_uops_0_bits_is_sfence_0 : _T_299 ? issue_slots_15_out_uop_is_sfence : issue_slots_14_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_fencei = _T_300 ? io_dis_uops_0_bits_is_fencei_0 : _T_299 ? issue_slots_15_out_uop_is_fencei : issue_slots_14_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_fence = _T_300 ? io_dis_uops_0_bits_is_fence_0 : _T_299 ? issue_slots_15_out_uop_is_fence : issue_slots_14_out_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sfb = _T_300 ? io_dis_uops_0_bits_is_sfb_0 : _T_299 ? issue_slots_15_out_uop_is_sfb : issue_slots_14_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_type = _T_300 ? io_dis_uops_0_bits_br_type_0 : _T_299 ? issue_slots_15_out_uop_br_type : issue_slots_14_out_uop_br_type; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_tag = _T_300 ? io_dis_uops_0_bits_br_tag_0 : _T_299 ? issue_slots_15_out_uop_br_tag : issue_slots_14_out_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_mask = _T_300 ? io_dis_uops_0_bits_br_mask_0 : _T_299 ? issue_slots_15_out_uop_br_mask : issue_slots_14_out_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_dis_col_sel = _T_300 ? io_dis_uops_0_bits_dis_col_sel_0 : _T_299 ? issue_slots_15_out_uop_dis_col_sel : issue_slots_14_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p3_bypass_hint = _T_300 ? _WIRE_iw_p3_bypass_hint : _T_299 ? issue_slots_15_out_uop_iw_p3_bypass_hint : issue_slots_14_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p2_bypass_hint = _T_300 ? _WIRE_iw_p2_bypass_hint : _T_299 ? issue_slots_15_out_uop_iw_p2_bypass_hint : issue_slots_14_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p1_bypass_hint = _T_300 ? _WIRE_iw_p1_bypass_hint : _T_299 ? issue_slots_15_out_uop_iw_p1_bypass_hint : issue_slots_14_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p2_speculative_child = _T_300 ? _WIRE_iw_p2_speculative_child : _T_299 ? issue_slots_15_out_uop_iw_p2_speculative_child : issue_slots_14_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :65:38, :67:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p1_speculative_child = _T_300 ? _WIRE_iw_p1_speculative_child : _T_299 ? issue_slots_15_out_uop_iw_p1_speculative_child : issue_slots_14_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :57:38, :59:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_issued = ~_T_300 & (_T_299 ? issue_slots_15_out_uop_iw_issued : issue_slots_14_out_uop_iw_issued); // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_0 = _T_300 ? io_dis_uops_0_bits_fu_code_0_0 : _T_299 ? issue_slots_15_out_uop_fu_code_0 : issue_slots_14_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_1 = _T_300 ? io_dis_uops_0_bits_fu_code_1_0 : _T_299 ? issue_slots_15_out_uop_fu_code_1 : issue_slots_14_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_2 = _T_300 ? io_dis_uops_0_bits_fu_code_2_0 : _T_299 ? issue_slots_15_out_uop_fu_code_2 : issue_slots_14_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_3 = _T_300 ? io_dis_uops_0_bits_fu_code_3_0 : _T_299 ? issue_slots_15_out_uop_fu_code_3 : issue_slots_14_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_4 = _T_300 ? io_dis_uops_0_bits_fu_code_4_0 : _T_299 ? issue_slots_15_out_uop_fu_code_4 : issue_slots_14_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_5 = _T_300 ? io_dis_uops_0_bits_fu_code_5_0 : _T_299 ? issue_slots_15_out_uop_fu_code_5 : issue_slots_14_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_6 = _T_300 ? io_dis_uops_0_bits_fu_code_6_0 : _T_299 ? issue_slots_15_out_uop_fu_code_6 : issue_slots_14_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_7 = _T_300 ? io_dis_uops_0_bits_fu_code_7_0 : _T_299 ? issue_slots_15_out_uop_fu_code_7 : issue_slots_14_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_8 = _T_300 ? io_dis_uops_0_bits_fu_code_8_0 : _T_299 ? issue_slots_15_out_uop_fu_code_8 : issue_slots_14_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_9 = _T_300 ? io_dis_uops_0_bits_fu_code_9_0 : _T_299 ? issue_slots_15_out_uop_fu_code_9 : issue_slots_14_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_0 = _T_300 ? io_dis_uops_0_bits_iq_type_0_0 : _T_299 ? issue_slots_15_out_uop_iq_type_0 : issue_slots_14_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_1 = _T_300 ? io_dis_uops_0_bits_iq_type_1_0 : _T_299 ? issue_slots_15_out_uop_iq_type_1 : issue_slots_14_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_2 = _T_300 ? io_dis_uops_0_bits_iq_type_2_0 : _T_299 ? issue_slots_15_out_uop_iq_type_2 : issue_slots_14_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_3 = _T_300 ? io_dis_uops_0_bits_iq_type_3_0 : _T_299 ? issue_slots_15_out_uop_iq_type_3 : issue_slots_14_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_pc = _T_300 ? io_dis_uops_0_bits_debug_pc_0 : _T_299 ? issue_slots_15_out_uop_debug_pc : issue_slots_14_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_rvc = _T_300 ? io_dis_uops_0_bits_is_rvc_0 : _T_299 ? issue_slots_15_out_uop_is_rvc : issue_slots_14_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_inst = _T_300 ? io_dis_uops_0_bits_debug_inst_0 : _T_299 ? issue_slots_15_out_uop_debug_inst : issue_slots_14_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_inst = _T_300 ? io_dis_uops_0_bits_inst_0 : _T_299 ? issue_slots_15_out_uop_inst : issue_slots_14_out_uop_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_13_clear_T = |shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_13_clear = _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_302 = shamts_oh_16 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_303 = shamts_oh_17 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_14_in_uop_valid = _T_303 ? will_be_valid_17 : _T_302 ? will_be_valid_16 : shamts_oh_15 == 3'h1 & issue_slots_15_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_14_in_uop_bits_debug_tsrc = _T_303 ? io_dis_uops_1_bits_debug_tsrc_0 : _T_302 ? io_dis_uops_0_bits_debug_tsrc_0 : issue_slots_15_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_fsrc = _T_303 ? io_dis_uops_1_bits_debug_fsrc_0 : _T_302 ? io_dis_uops_0_bits_debug_fsrc_0 : issue_slots_15_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_bp_xcpt_if = _T_303 ? io_dis_uops_1_bits_bp_xcpt_if_0 : _T_302 ? io_dis_uops_0_bits_bp_xcpt_if_0 : issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_bp_debug_if = _T_303 ? io_dis_uops_1_bits_bp_debug_if_0 : _T_302 ? io_dis_uops_0_bits_bp_debug_if_0 : issue_slots_15_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_ma_if = _T_303 ? io_dis_uops_1_bits_xcpt_ma_if_0 : _T_302 ? io_dis_uops_0_bits_xcpt_ma_if_0 : issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_ae_if = _T_303 ? io_dis_uops_1_bits_xcpt_ae_if_0 : _T_302 ? io_dis_uops_0_bits_xcpt_ae_if_0 : issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_pf_if = _T_303 ? io_dis_uops_1_bits_xcpt_pf_if_0 : _T_302 ? io_dis_uops_0_bits_xcpt_pf_if_0 : issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_typ = _T_303 ? io_dis_uops_1_bits_fp_typ_0 : _T_302 ? io_dis_uops_0_bits_fp_typ_0 : issue_slots_15_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_rm = _T_303 ? io_dis_uops_1_bits_fp_rm_0 : _T_302 ? io_dis_uops_0_bits_fp_rm_0 : issue_slots_15_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_val = _T_303 ? io_dis_uops_1_bits_fp_val_0 : _T_302 ? io_dis_uops_0_bits_fp_val_0 : issue_slots_15_out_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fcn_op = _T_303 ? io_dis_uops_1_bits_fcn_op_0 : _T_302 ? io_dis_uops_0_bits_fcn_op_0 : issue_slots_15_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fcn_dw = _T_303 ? io_dis_uops_1_bits_fcn_dw_0 : _T_302 ? io_dis_uops_0_bits_fcn_dw_0 : issue_slots_15_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_frs3_en = _T_303 ? io_dis_uops_1_bits_frs3_en_0 : _T_302 ? io_dis_uops_0_bits_frs3_en_0 : issue_slots_15_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs2_rtype = _T_303 ? io_dis_uops_1_bits_lrs2_rtype_0 : _T_302 ? io_dis_uops_0_bits_lrs2_rtype_0 : issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs1_rtype = _T_303 ? io_dis_uops_1_bits_lrs1_rtype_0 : _T_302 ? io_dis_uops_0_bits_lrs1_rtype_0 : issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_dst_rtype = _T_303 ? io_dis_uops_1_bits_dst_rtype_0 : _T_302 ? io_dis_uops_0_bits_dst_rtype_0 : issue_slots_15_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs3 = _T_303 ? io_dis_uops_1_bits_lrs3_0 : _T_302 ? io_dis_uops_0_bits_lrs3_0 : issue_slots_15_out_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs2 = _T_303 ? io_dis_uops_1_bits_lrs2_0 : _T_302 ? io_dis_uops_0_bits_lrs2_0 : issue_slots_15_out_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs1 = _T_303 ? io_dis_uops_1_bits_lrs1_0 : _T_302 ? io_dis_uops_0_bits_lrs1_0 : issue_slots_15_out_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldst = _T_303 ? io_dis_uops_1_bits_ldst_0 : _T_302 ? io_dis_uops_0_bits_ldst_0 : issue_slots_15_out_uop_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldst_is_rs1 = _T_303 ? io_dis_uops_1_bits_ldst_is_rs1_0 : _T_302 ? io_dis_uops_0_bits_ldst_is_rs1_0 : issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_csr_cmd = _T_303 ? io_dis_uops_1_bits_csr_cmd_0 : _T_302 ? io_dis_uops_0_bits_csr_cmd_0 : issue_slots_15_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_flush_on_commit = _T_303 ? io_dis_uops_1_bits_flush_on_commit_0 : _T_302 ? io_dis_uops_0_bits_flush_on_commit_0 : issue_slots_15_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_unique = _T_303 ? io_dis_uops_1_bits_is_unique_0 : _T_302 ? io_dis_uops_0_bits_is_unique_0 : issue_slots_15_out_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_uses_stq = _T_303 ? io_dis_uops_1_bits_uses_stq_0 : _T_302 ? io_dis_uops_0_bits_uses_stq_0 : issue_slots_15_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_uses_ldq = _T_303 ? io_dis_uops_1_bits_uses_ldq_0 : _T_302 ? io_dis_uops_0_bits_uses_ldq_0 : issue_slots_15_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_signed = _T_303 ? io_dis_uops_1_bits_mem_signed_0 : _T_302 ? io_dis_uops_0_bits_mem_signed_0 : issue_slots_15_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_size = _T_303 ? io_dis_uops_1_bits_mem_size_0 : _T_302 ? io_dis_uops_0_bits_mem_size_0 : issue_slots_15_out_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_cmd = _T_303 ? io_dis_uops_1_bits_mem_cmd_0 : _T_302 ? io_dis_uops_0_bits_mem_cmd_0 : issue_slots_15_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_exc_cause = _T_303 ? io_dis_uops_1_bits_exc_cause_0 : _T_302 ? io_dis_uops_0_bits_exc_cause_0 : issue_slots_15_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_exception = _T_303 ? io_dis_uops_1_bits_exception_0 : _T_302 ? io_dis_uops_0_bits_exception_0 : issue_slots_15_out_uop_exception; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_stale_pdst = _T_303 ? io_dis_uops_1_bits_stale_pdst_0 : _T_302 ? io_dis_uops_0_bits_stale_pdst_0 : issue_slots_15_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ppred_busy = _T_303 ? _WIRE_1_ppred_busy : _T_302 ? _WIRE_ppred_busy : issue_slots_15_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:35:17, :80:96, :81:30, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs3_busy = _T_303 ? _WIRE_1_prs3_busy : _T_302 ? _WIRE_prs3_busy : issue_slots_15_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:35:17, :76:38, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs2_busy = _T_303 ? _WIRE_1_prs2_busy : _T_302 ? _WIRE_prs2_busy : issue_slots_15_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:65:38, :71:116, :72:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs1_busy = _T_303 ? _WIRE_1_prs1_busy : _T_302 ? _WIRE_prs1_busy : issue_slots_15_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:57:38, :62:116, :63:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ppred = _T_303 ? io_dis_uops_1_bits_ppred_0 : _T_302 ? io_dis_uops_0_bits_ppred_0 : issue_slots_15_out_uop_ppred; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs3 = _T_303 ? io_dis_uops_1_bits_prs3_0 : _T_302 ? io_dis_uops_0_bits_prs3_0 : issue_slots_15_out_uop_prs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs2 = _T_303 ? io_dis_uops_1_bits_prs2_0 : _T_302 ? io_dis_uops_0_bits_prs2_0 : issue_slots_15_out_uop_prs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs1 = _T_303 ? io_dis_uops_1_bits_prs1_0 : _T_302 ? io_dis_uops_0_bits_prs1_0 : issue_slots_15_out_uop_prs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pdst = _T_303 ? io_dis_uops_1_bits_pdst_0 : _T_302 ? io_dis_uops_0_bits_pdst_0 : issue_slots_15_out_uop_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_rxq_idx = _T_303 ? io_dis_uops_1_bits_rxq_idx_0 : _T_302 ? io_dis_uops_0_bits_rxq_idx_0 : issue_slots_15_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_stq_idx = _T_303 ? io_dis_uops_1_bits_stq_idx_0 : _T_302 ? io_dis_uops_0_bits_stq_idx_0 : issue_slots_15_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldq_idx = _T_303 ? io_dis_uops_1_bits_ldq_idx_0 : _T_302 ? io_dis_uops_0_bits_ldq_idx_0 : issue_slots_15_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_rob_idx = _T_303 ? io_dis_uops_1_bits_rob_idx_0 : _T_302 ? io_dis_uops_0_bits_rob_idx_0 : issue_slots_15_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_vec = _T_303 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : issue_slots_15_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_wflags = _T_303 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : issue_slots_15_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_sqrt = _T_303 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : issue_slots_15_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_div = _T_303 ? io_dis_uops_1_bits_fp_ctrl_div_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_div_0 : issue_slots_15_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fma = _T_303 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : issue_slots_15_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fastpipe = _T_303 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : issue_slots_15_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_toint = _T_303 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : issue_slots_15_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fromint = _T_303 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : issue_slots_15_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut = _T_303 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : issue_slots_15_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn = _T_303 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : issue_slots_15_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_swap23 = _T_303 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : issue_slots_15_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_swap12 = _T_303 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : issue_slots_15_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren3 = _T_303 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : issue_slots_15_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren2 = _T_303 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : issue_slots_15_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren1 = _T_303 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : issue_slots_15_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_wen = _T_303 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : issue_slots_15_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ldst = _T_303 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : _T_302 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : issue_slots_15_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_op2_sel = _T_303 ? io_dis_uops_1_bits_op2_sel_0 : _T_302 ? io_dis_uops_0_bits_op2_sel_0 : issue_slots_15_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_op1_sel = _T_303 ? io_dis_uops_1_bits_op1_sel_0 : _T_302 ? io_dis_uops_0_bits_op1_sel_0 : issue_slots_15_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_packed = _T_303 ? io_dis_uops_1_bits_imm_packed_0 : _T_302 ? io_dis_uops_0_bits_imm_packed_0 : issue_slots_15_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pimm = _T_303 ? io_dis_uops_1_bits_pimm_0 : _T_302 ? io_dis_uops_0_bits_pimm_0 : issue_slots_15_out_uop_pimm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_sel = _T_303 ? io_dis_uops_1_bits_imm_sel_0 : _T_302 ? io_dis_uops_0_bits_imm_sel_0 : issue_slots_15_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_rename = _T_303 ? io_dis_uops_1_bits_imm_rename_0 : _T_302 ? io_dis_uops_0_bits_imm_rename_0 : issue_slots_15_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_taken = _T_303 ? io_dis_uops_1_bits_taken_0 : _T_302 ? io_dis_uops_0_bits_taken_0 : issue_slots_15_out_uop_taken; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pc_lob = _T_303 ? io_dis_uops_1_bits_pc_lob_0 : _T_302 ? io_dis_uops_0_bits_pc_lob_0 : issue_slots_15_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_edge_inst = _T_303 ? io_dis_uops_1_bits_edge_inst_0 : _T_302 ? io_dis_uops_0_bits_edge_inst_0 : issue_slots_15_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ftq_idx = _T_303 ? io_dis_uops_1_bits_ftq_idx_0 : _T_302 ? io_dis_uops_0_bits_ftq_idx_0 : issue_slots_15_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_mov = _T_303 ? io_dis_uops_1_bits_is_mov_0 : _T_302 ? io_dis_uops_0_bits_is_mov_0 : issue_slots_15_out_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_rocc = _T_303 ? io_dis_uops_1_bits_is_rocc_0 : _T_302 ? io_dis_uops_0_bits_is_rocc_0 : issue_slots_15_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sys_pc2epc = _T_303 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : _T_302 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_eret = _T_303 ? io_dis_uops_1_bits_is_eret_0 : _T_302 ? io_dis_uops_0_bits_is_eret_0 : issue_slots_15_out_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_amo = _T_303 ? io_dis_uops_1_bits_is_amo_0 : _T_302 ? io_dis_uops_0_bits_is_amo_0 : issue_slots_15_out_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sfence = _T_303 ? io_dis_uops_1_bits_is_sfence_0 : _T_302 ? io_dis_uops_0_bits_is_sfence_0 : issue_slots_15_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_fencei = _T_303 ? io_dis_uops_1_bits_is_fencei_0 : _T_302 ? io_dis_uops_0_bits_is_fencei_0 : issue_slots_15_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_fence = _T_303 ? io_dis_uops_1_bits_is_fence_0 : _T_302 ? io_dis_uops_0_bits_is_fence_0 : issue_slots_15_out_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sfb = _T_303 ? io_dis_uops_1_bits_is_sfb_0 : _T_302 ? io_dis_uops_0_bits_is_sfb_0 : issue_slots_15_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_type = _T_303 ? io_dis_uops_1_bits_br_type_0 : _T_302 ? io_dis_uops_0_bits_br_type_0 : issue_slots_15_out_uop_br_type; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_tag = _T_303 ? io_dis_uops_1_bits_br_tag_0 : _T_302 ? io_dis_uops_0_bits_br_tag_0 : issue_slots_15_out_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_mask = _T_303 ? io_dis_uops_1_bits_br_mask_0 : _T_302 ? io_dis_uops_0_bits_br_mask_0 : issue_slots_15_out_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_dis_col_sel = _T_303 ? io_dis_uops_1_bits_dis_col_sel_0 : _T_302 ? io_dis_uops_0_bits_dis_col_sel_0 : issue_slots_15_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p3_bypass_hint = _T_303 ? _WIRE_1_iw_p3_bypass_hint : _T_302 ? _WIRE_iw_p3_bypass_hint : issue_slots_15_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p2_bypass_hint = _T_303 ? _WIRE_1_iw_p2_bypass_hint : _T_302 ? _WIRE_iw_p2_bypass_hint : issue_slots_15_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p1_bypass_hint = _T_303 ? _WIRE_1_iw_p1_bypass_hint : _T_302 ? _WIRE_iw_p1_bypass_hint : issue_slots_15_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p2_speculative_child = _T_303 ? _WIRE_1_iw_p2_speculative_child : _T_302 ? _WIRE_iw_p2_speculative_child : issue_slots_15_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :65:38, :67:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p1_speculative_child = _T_303 ? _WIRE_1_iw_p1_speculative_child : _T_302 ? _WIRE_iw_p1_speculative_child : issue_slots_15_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :57:38, :59:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_issued = ~(_T_303 | _T_302) & issue_slots_15_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_0 = _T_303 ? io_dis_uops_1_bits_fu_code_0_0 : _T_302 ? io_dis_uops_0_bits_fu_code_0_0 : issue_slots_15_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_1 = _T_303 ? io_dis_uops_1_bits_fu_code_1_0 : _T_302 ? io_dis_uops_0_bits_fu_code_1_0 : issue_slots_15_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_2 = _T_303 ? io_dis_uops_1_bits_fu_code_2_0 : _T_302 ? io_dis_uops_0_bits_fu_code_2_0 : issue_slots_15_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_3 = _T_303 ? io_dis_uops_1_bits_fu_code_3_0 : _T_302 ? io_dis_uops_0_bits_fu_code_3_0 : issue_slots_15_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_4 = _T_303 ? io_dis_uops_1_bits_fu_code_4_0 : _T_302 ? io_dis_uops_0_bits_fu_code_4_0 : issue_slots_15_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_5 = _T_303 ? io_dis_uops_1_bits_fu_code_5_0 : _T_302 ? io_dis_uops_0_bits_fu_code_5_0 : issue_slots_15_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_6 = _T_303 ? io_dis_uops_1_bits_fu_code_6_0 : _T_302 ? io_dis_uops_0_bits_fu_code_6_0 : issue_slots_15_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_7 = _T_303 ? io_dis_uops_1_bits_fu_code_7_0 : _T_302 ? io_dis_uops_0_bits_fu_code_7_0 : issue_slots_15_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_8 = _T_303 ? io_dis_uops_1_bits_fu_code_8_0 : _T_302 ? io_dis_uops_0_bits_fu_code_8_0 : issue_slots_15_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_9 = _T_303 ? io_dis_uops_1_bits_fu_code_9_0 : _T_302 ? io_dis_uops_0_bits_fu_code_9_0 : issue_slots_15_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_0 = _T_303 ? io_dis_uops_1_bits_iq_type_0_0 : _T_302 ? io_dis_uops_0_bits_iq_type_0_0 : issue_slots_15_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_1 = _T_303 ? io_dis_uops_1_bits_iq_type_1_0 : _T_302 ? io_dis_uops_0_bits_iq_type_1_0 : issue_slots_15_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_2 = _T_303 ? io_dis_uops_1_bits_iq_type_2_0 : _T_302 ? io_dis_uops_0_bits_iq_type_2_0 : issue_slots_15_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_3 = _T_303 ? io_dis_uops_1_bits_iq_type_3_0 : _T_302 ? io_dis_uops_0_bits_iq_type_3_0 : issue_slots_15_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_pc = _T_303 ? io_dis_uops_1_bits_debug_pc_0 : _T_302 ? io_dis_uops_0_bits_debug_pc_0 : issue_slots_15_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_rvc = _T_303 ? io_dis_uops_1_bits_is_rvc_0 : _T_302 ? io_dis_uops_0_bits_is_rvc_0 : issue_slots_15_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_inst = _T_303 ? io_dis_uops_1_bits_debug_inst_0 : _T_302 ? io_dis_uops_0_bits_debug_inst_0 : issue_slots_15_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_inst = _T_303 ? io_dis_uops_1_bits_inst_0 : _T_302 ? io_dis_uops_0_bits_inst_0 : issue_slots_15_out_uop_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_14_clear_T = |shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_14_clear = _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_305 = shamts_oh_17 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_306 = shamts_oh_18 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_15_in_uop_valid = _T_306 ? will_be_valid_18 : _T_305 ? will_be_valid_17 : shamts_oh_16 == 3'h1 & will_be_valid_16; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_15_in_uop_bits_debug_tsrc = _T_306 ? io_dis_uops_2_bits_debug_tsrc_0 : _T_305 ? io_dis_uops_1_bits_debug_tsrc_0 : io_dis_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_fsrc = _T_306 ? io_dis_uops_2_bits_debug_fsrc_0 : _T_305 ? io_dis_uops_1_bits_debug_fsrc_0 : io_dis_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_bp_xcpt_if = _T_306 ? io_dis_uops_2_bits_bp_xcpt_if_0 : _T_305 ? io_dis_uops_1_bits_bp_xcpt_if_0 : io_dis_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_bp_debug_if = _T_306 ? io_dis_uops_2_bits_bp_debug_if_0 : _T_305 ? io_dis_uops_1_bits_bp_debug_if_0 : io_dis_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_ma_if = _T_306 ? io_dis_uops_2_bits_xcpt_ma_if_0 : _T_305 ? io_dis_uops_1_bits_xcpt_ma_if_0 : io_dis_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_ae_if = _T_306 ? io_dis_uops_2_bits_xcpt_ae_if_0 : _T_305 ? io_dis_uops_1_bits_xcpt_ae_if_0 : io_dis_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_pf_if = _T_306 ? io_dis_uops_2_bits_xcpt_pf_if_0 : _T_305 ? io_dis_uops_1_bits_xcpt_pf_if_0 : io_dis_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_typ = _T_306 ? io_dis_uops_2_bits_fp_typ_0 : _T_305 ? io_dis_uops_1_bits_fp_typ_0 : io_dis_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_rm = _T_306 ? io_dis_uops_2_bits_fp_rm_0 : _T_305 ? io_dis_uops_1_bits_fp_rm_0 : io_dis_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_val = _T_306 ? io_dis_uops_2_bits_fp_val_0 : _T_305 ? io_dis_uops_1_bits_fp_val_0 : io_dis_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fcn_op = _T_306 ? io_dis_uops_2_bits_fcn_op_0 : _T_305 ? io_dis_uops_1_bits_fcn_op_0 : io_dis_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fcn_dw = _T_306 ? io_dis_uops_2_bits_fcn_dw_0 : _T_305 ? io_dis_uops_1_bits_fcn_dw_0 : io_dis_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_frs3_en = _T_306 ? io_dis_uops_2_bits_frs3_en_0 : _T_305 ? io_dis_uops_1_bits_frs3_en_0 : io_dis_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs2_rtype = _T_306 ? io_dis_uops_2_bits_lrs2_rtype_0 : _T_305 ? io_dis_uops_1_bits_lrs2_rtype_0 : io_dis_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs1_rtype = _T_306 ? io_dis_uops_2_bits_lrs1_rtype_0 : _T_305 ? io_dis_uops_1_bits_lrs1_rtype_0 : io_dis_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_dst_rtype = _T_306 ? io_dis_uops_2_bits_dst_rtype_0 : _T_305 ? io_dis_uops_1_bits_dst_rtype_0 : io_dis_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs3 = _T_306 ? io_dis_uops_2_bits_lrs3_0 : _T_305 ? io_dis_uops_1_bits_lrs3_0 : io_dis_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs2 = _T_306 ? io_dis_uops_2_bits_lrs2_0 : _T_305 ? io_dis_uops_1_bits_lrs2_0 : io_dis_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs1 = _T_306 ? io_dis_uops_2_bits_lrs1_0 : _T_305 ? io_dis_uops_1_bits_lrs1_0 : io_dis_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldst = _T_306 ? io_dis_uops_2_bits_ldst_0 : _T_305 ? io_dis_uops_1_bits_ldst_0 : io_dis_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldst_is_rs1 = _T_306 ? io_dis_uops_2_bits_ldst_is_rs1_0 : _T_305 ? io_dis_uops_1_bits_ldst_is_rs1_0 : io_dis_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_csr_cmd = _T_306 ? io_dis_uops_2_bits_csr_cmd_0 : _T_305 ? io_dis_uops_1_bits_csr_cmd_0 : io_dis_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_flush_on_commit = _T_306 ? io_dis_uops_2_bits_flush_on_commit_0 : _T_305 ? io_dis_uops_1_bits_flush_on_commit_0 : io_dis_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_unique = _T_306 ? io_dis_uops_2_bits_is_unique_0 : _T_305 ? io_dis_uops_1_bits_is_unique_0 : io_dis_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_uses_stq = _T_306 ? io_dis_uops_2_bits_uses_stq_0 : _T_305 ? io_dis_uops_1_bits_uses_stq_0 : io_dis_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_uses_ldq = _T_306 ? io_dis_uops_2_bits_uses_ldq_0 : _T_305 ? io_dis_uops_1_bits_uses_ldq_0 : io_dis_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_signed = _T_306 ? io_dis_uops_2_bits_mem_signed_0 : _T_305 ? io_dis_uops_1_bits_mem_signed_0 : io_dis_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_size = _T_306 ? io_dis_uops_2_bits_mem_size_0 : _T_305 ? io_dis_uops_1_bits_mem_size_0 : io_dis_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_cmd = _T_306 ? io_dis_uops_2_bits_mem_cmd_0 : _T_305 ? io_dis_uops_1_bits_mem_cmd_0 : io_dis_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_exc_cause = _T_306 ? io_dis_uops_2_bits_exc_cause_0 : _T_305 ? io_dis_uops_1_bits_exc_cause_0 : io_dis_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_exception = _T_306 ? io_dis_uops_2_bits_exception_0 : _T_305 ? io_dis_uops_1_bits_exception_0 : io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_stale_pdst = _T_306 ? io_dis_uops_2_bits_stale_pdst_0 : _T_305 ? io_dis_uops_1_bits_stale_pdst_0 : io_dis_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ppred_busy = _T_306 ? ~(io_pred_wakeup_port_valid_0 & io_pred_wakeup_port_bits_0 == io_dis_uops_2_bits_ppred_0) & io_dis_uops_2_bits_ppred_busy_0 : _T_305 ? _WIRE_1_ppred_busy : _WIRE_ppred_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :80:{37,65,96}, :81:30, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs3_busy = _T_306 ? ~_T_213 & io_dis_uops_2_bits_prs3_busy_0 : _T_305 ? _WIRE_1_prs3_busy : _WIRE_prs3_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs2_busy = _T_306 ? ((|{prs2_rebusys_0_2, io_child_rebusys_0 & io_dis_uops_2_bits_iw_p2_speculative_child_0}) ? io_dis_uops_2_bits_lrs2_rtype_0 == 2'h0 : ~_T_183 & io_dis_uops_2_bits_prs2_busy_0) : _T_305 ? _WIRE_1_prs2_busy : _WIRE_prs2_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs1_busy = _T_306 ? ((|{prs1_rebusys_0_2, io_child_rebusys_0 & io_dis_uops_2_bits_iw_p1_speculative_child_0}) ? io_dis_uops_2_bits_lrs1_rtype_0 == 2'h0 : ~_T_153 & io_dis_uops_2_bits_prs1_busy_0) : _T_305 ? _WIRE_1_prs1_busy : _WIRE_prs1_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ppred = _T_306 ? io_dis_uops_2_bits_ppred_0 : _T_305 ? io_dis_uops_1_bits_ppred_0 : io_dis_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs3 = _T_306 ? io_dis_uops_2_bits_prs3_0 : _T_305 ? io_dis_uops_1_bits_prs3_0 : io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs2 = _T_306 ? io_dis_uops_2_bits_prs2_0 : _T_305 ? io_dis_uops_1_bits_prs2_0 : io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs1 = _T_306 ? io_dis_uops_2_bits_prs1_0 : _T_305 ? io_dis_uops_1_bits_prs1_0 : io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pdst = _T_306 ? io_dis_uops_2_bits_pdst_0 : _T_305 ? io_dis_uops_1_bits_pdst_0 : io_dis_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_rxq_idx = _T_306 ? io_dis_uops_2_bits_rxq_idx_0 : _T_305 ? io_dis_uops_1_bits_rxq_idx_0 : io_dis_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_stq_idx = _T_306 ? io_dis_uops_2_bits_stq_idx_0 : _T_305 ? io_dis_uops_1_bits_stq_idx_0 : io_dis_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldq_idx = _T_306 ? io_dis_uops_2_bits_ldq_idx_0 : _T_305 ? io_dis_uops_1_bits_ldq_idx_0 : io_dis_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_rob_idx = _T_306 ? io_dis_uops_2_bits_rob_idx_0 : _T_305 ? io_dis_uops_1_bits_rob_idx_0 : io_dis_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_vec = _T_306 ? io_dis_uops_2_bits_fp_ctrl_vec_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : io_dis_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_wflags = _T_306 ? io_dis_uops_2_bits_fp_ctrl_wflags_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : io_dis_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_sqrt = _T_306 ? io_dis_uops_2_bits_fp_ctrl_sqrt_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : io_dis_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_div = _T_306 ? io_dis_uops_2_bits_fp_ctrl_div_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_div_0 : io_dis_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fma = _T_306 ? io_dis_uops_2_bits_fp_ctrl_fma_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : io_dis_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fastpipe = _T_306 ? io_dis_uops_2_bits_fp_ctrl_fastpipe_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : io_dis_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_toint = _T_306 ? io_dis_uops_2_bits_fp_ctrl_toint_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : io_dis_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fromint = _T_306 ? io_dis_uops_2_bits_fp_ctrl_fromint_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : io_dis_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut = _T_306 ? io_dis_uops_2_bits_fp_ctrl_typeTagOut_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : io_dis_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn = _T_306 ? io_dis_uops_2_bits_fp_ctrl_typeTagIn_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : io_dis_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_swap23 = _T_306 ? io_dis_uops_2_bits_fp_ctrl_swap23_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : io_dis_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_swap12 = _T_306 ? io_dis_uops_2_bits_fp_ctrl_swap12_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : io_dis_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren3 = _T_306 ? io_dis_uops_2_bits_fp_ctrl_ren3_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : io_dis_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren2 = _T_306 ? io_dis_uops_2_bits_fp_ctrl_ren2_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : io_dis_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren1 = _T_306 ? io_dis_uops_2_bits_fp_ctrl_ren1_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : io_dis_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_wen = _T_306 ? io_dis_uops_2_bits_fp_ctrl_wen_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : io_dis_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ldst = _T_306 ? io_dis_uops_2_bits_fp_ctrl_ldst_0 : _T_305 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : io_dis_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_op2_sel = _T_306 ? io_dis_uops_2_bits_op2_sel_0 : _T_305 ? io_dis_uops_1_bits_op2_sel_0 : io_dis_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_op1_sel = _T_306 ? io_dis_uops_2_bits_op1_sel_0 : _T_305 ? io_dis_uops_1_bits_op1_sel_0 : io_dis_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_packed = _T_306 ? io_dis_uops_2_bits_imm_packed_0 : _T_305 ? io_dis_uops_1_bits_imm_packed_0 : io_dis_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pimm = _T_306 ? io_dis_uops_2_bits_pimm_0 : _T_305 ? io_dis_uops_1_bits_pimm_0 : io_dis_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_sel = _T_306 ? io_dis_uops_2_bits_imm_sel_0 : _T_305 ? io_dis_uops_1_bits_imm_sel_0 : io_dis_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_rename = _T_306 ? io_dis_uops_2_bits_imm_rename_0 : _T_305 ? io_dis_uops_1_bits_imm_rename_0 : io_dis_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_taken = _T_306 ? io_dis_uops_2_bits_taken_0 : _T_305 ? io_dis_uops_1_bits_taken_0 : io_dis_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pc_lob = _T_306 ? io_dis_uops_2_bits_pc_lob_0 : _T_305 ? io_dis_uops_1_bits_pc_lob_0 : io_dis_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_edge_inst = _T_306 ? io_dis_uops_2_bits_edge_inst_0 : _T_305 ? io_dis_uops_1_bits_edge_inst_0 : io_dis_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ftq_idx = _T_306 ? io_dis_uops_2_bits_ftq_idx_0 : _T_305 ? io_dis_uops_1_bits_ftq_idx_0 : io_dis_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_mov = _T_306 ? io_dis_uops_2_bits_is_mov_0 : _T_305 ? io_dis_uops_1_bits_is_mov_0 : io_dis_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_rocc = _T_306 ? io_dis_uops_2_bits_is_rocc_0 : _T_305 ? io_dis_uops_1_bits_is_rocc_0 : io_dis_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sys_pc2epc = _T_306 ? io_dis_uops_2_bits_is_sys_pc2epc_0 : _T_305 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : io_dis_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_eret = _T_306 ? io_dis_uops_2_bits_is_eret_0 : _T_305 ? io_dis_uops_1_bits_is_eret_0 : io_dis_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_amo = _T_306 ? io_dis_uops_2_bits_is_amo_0 : _T_305 ? io_dis_uops_1_bits_is_amo_0 : io_dis_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sfence = _T_306 ? io_dis_uops_2_bits_is_sfence_0 : _T_305 ? io_dis_uops_1_bits_is_sfence_0 : io_dis_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_fencei = _T_306 ? io_dis_uops_2_bits_is_fencei_0 : _T_305 ? io_dis_uops_1_bits_is_fencei_0 : io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_fence = _T_306 ? io_dis_uops_2_bits_is_fence_0 : _T_305 ? io_dis_uops_1_bits_is_fence_0 : io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sfb = _T_306 ? io_dis_uops_2_bits_is_sfb_0 : _T_305 ? io_dis_uops_1_bits_is_sfb_0 : io_dis_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_type = _T_306 ? io_dis_uops_2_bits_br_type_0 : _T_305 ? io_dis_uops_1_bits_br_type_0 : io_dis_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_tag = _T_306 ? io_dis_uops_2_bits_br_tag_0 : _T_305 ? io_dis_uops_1_bits_br_tag_0 : io_dis_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_mask = _T_306 ? io_dis_uops_2_bits_br_mask_0 : _T_305 ? io_dis_uops_1_bits_br_mask_0 : io_dis_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_dis_col_sel = _T_306 ? io_dis_uops_2_bits_dis_col_sel_0 : _T_305 ? io_dis_uops_1_bits_dis_col_sel_0 : io_dis_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iw_p3_bypass_hint = _T_306 ? _T_213 & (prs3_wakeups_0_2 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2_2 | prs3_wakeups_3_2 | prs3_wakeups_4_2) : _T_305 ? _WIRE_1_iw_p3_bypass_hint : _WIRE_iw_p3_bypass_hint; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_iw_p2_bypass_hint = _T_306 ? _T_183 & (prs2_wakeups_0_2 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2_2 | prs2_wakeups_3_2 | prs2_wakeups_4_2) : _T_305 ? _WIRE_1_iw_p2_bypass_hint : _WIRE_iw_p2_bypass_hint; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_iw_p1_bypass_hint = _T_306 ? _T_153 & (prs1_wakeups_0_2 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2_2 | prs1_wakeups_3_2 | prs1_wakeups_4_2) : _T_305 ? _WIRE_1_iw_p1_bypass_hint : _WIRE_iw_p1_bypass_hint; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_iw_p2_speculative_child = _T_306 ? (_T_183 ? (prs2_wakeups_0_2 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs2_wakeups_4_2, prs2_wakeups_3_2, prs2_wakeups_2_2} : io_dis_uops_2_bits_iw_p2_speculative_child_0) : _T_305 ? _WIRE_1_iw_p2_speculative_child : _WIRE_iw_p2_speculative_child; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_iw_p1_speculative_child = _T_306 ? (_T_153 ? (prs1_wakeups_0_2 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs1_wakeups_4_2, prs1_wakeups_3_2, prs1_wakeups_2_2} : io_dis_uops_2_bits_iw_p1_speculative_child_0) : _T_305 ? _WIRE_1_iw_p1_speculative_child : _WIRE_iw_p1_speculative_child; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_fu_code_0 = _T_306 ? io_dis_uops_2_bits_fu_code_0_0 : _T_305 ? io_dis_uops_1_bits_fu_code_0_0 : io_dis_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_1 = _T_306 ? io_dis_uops_2_bits_fu_code_1_0 : _T_305 ? io_dis_uops_1_bits_fu_code_1_0 : io_dis_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_2 = _T_306 ? io_dis_uops_2_bits_fu_code_2_0 : _T_305 ? io_dis_uops_1_bits_fu_code_2_0 : io_dis_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_3 = _T_306 ? io_dis_uops_2_bits_fu_code_3_0 : _T_305 ? io_dis_uops_1_bits_fu_code_3_0 : io_dis_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_4 = _T_306 ? io_dis_uops_2_bits_fu_code_4_0 : _T_305 ? io_dis_uops_1_bits_fu_code_4_0 : io_dis_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_5 = _T_306 ? io_dis_uops_2_bits_fu_code_5_0 : _T_305 ? io_dis_uops_1_bits_fu_code_5_0 : io_dis_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_6 = _T_306 ? io_dis_uops_2_bits_fu_code_6_0 : _T_305 ? io_dis_uops_1_bits_fu_code_6_0 : io_dis_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_7 = _T_306 ? io_dis_uops_2_bits_fu_code_7_0 : _T_305 ? io_dis_uops_1_bits_fu_code_7_0 : io_dis_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_8 = _T_306 ? io_dis_uops_2_bits_fu_code_8_0 : _T_305 ? io_dis_uops_1_bits_fu_code_8_0 : io_dis_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_9 = _T_306 ? io_dis_uops_2_bits_fu_code_9_0 : _T_305 ? io_dis_uops_1_bits_fu_code_9_0 : io_dis_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_0 = _T_306 ? io_dis_uops_2_bits_iq_type_0_0 : _T_305 ? io_dis_uops_1_bits_iq_type_0_0 : io_dis_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_1 = _T_306 ? io_dis_uops_2_bits_iq_type_1_0 : _T_305 ? io_dis_uops_1_bits_iq_type_1_0 : io_dis_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_2 = _T_306 ? io_dis_uops_2_bits_iq_type_2_0 : _T_305 ? io_dis_uops_1_bits_iq_type_2_0 : io_dis_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_3 = _T_306 ? io_dis_uops_2_bits_iq_type_3_0 : _T_305 ? io_dis_uops_1_bits_iq_type_3_0 : io_dis_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_pc = _T_306 ? io_dis_uops_2_bits_debug_pc_0 : _T_305 ? io_dis_uops_1_bits_debug_pc_0 : io_dis_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_rvc = _T_306 ? io_dis_uops_2_bits_is_rvc_0 : _T_305 ? io_dis_uops_1_bits_is_rvc_0 : io_dis_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_inst = _T_306 ? io_dis_uops_2_bits_debug_inst_0 : _T_305 ? io_dis_uops_1_bits_debug_inst_0 : io_dis_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_inst = _T_306 ? io_dis_uops_2_bits_inst_0 : _T_305 ? io_dis_uops_1_bits_inst_0 : io_dis_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_15_clear_T = |shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_15_clear = _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] reg is_available_0; // @[issue-unit-age-ordered.scala:208:25] reg is_available_1; // @[issue-unit-age-ordered.scala:208:25] reg is_available_2; // @[issue-unit-age-ordered.scala:208:25] reg is_available_3; // @[issue-unit-age-ordered.scala:208:25] reg is_available_4; // @[issue-unit-age-ordered.scala:208:25] reg is_available_5; // @[issue-unit-age-ordered.scala:208:25] reg is_available_6; // @[issue-unit-age-ordered.scala:208:25] reg is_available_7; // @[issue-unit-age-ordered.scala:208:25] wire [1:0] _GEN_0 = {1'h0, is_available_0} + {1'h0, is_available_1}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T = _GEN_0; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T = _GEN_0; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T = _GEN_0; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_1 = _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_1 = {1'h0, is_available_2} + {1'h0, is_available_3}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_2 = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_2 = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_2 = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_3 = _io_dis_uops_0_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_4 = {1'h0, _io_dis_uops_0_ready_T_1} + {1'h0, _io_dis_uops_0_ready_T_3}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_5 = _io_dis_uops_0_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_2 = {1'h0, is_available_4} + {1'h0, is_available_5}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_6 = _GEN_2; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_6 = _GEN_2; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_6 = _GEN_2; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_7 = _io_dis_uops_0_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_3 = {1'h0, is_available_6} + {1'h0, is_available_7}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_8 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_8 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_8 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_9 = _io_dis_uops_0_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_10 = {1'h0, _io_dis_uops_0_ready_T_7} + {1'h0, _io_dis_uops_0_ready_T_9}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_11 = _io_dis_uops_0_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_12 = {1'h0, _io_dis_uops_0_ready_T_5} + {1'h0, _io_dis_uops_0_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_13 = _io_dis_uops_0_ready_T_12; // @[issue-unit-age-ordered.scala:212:45] wire _GEN_4 = io_dis_uops_0_ready_0 & io_dis_uops_0_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_14; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_14 = _GEN_4; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_14; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_14 = _GEN_4; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_14; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_14 = _GEN_4; // @[Decoupled.scala:51:35] wire _GEN_5 = io_dis_uops_1_ready_0 & io_dis_uops_1_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_15; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_15 = _GEN_5; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_15; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_15 = _GEN_5; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_15; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_15 = _GEN_5; // @[Decoupled.scala:51:35] wire _GEN_6 = io_dis_uops_2_ready_0 & io_dis_uops_2_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_16; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_16 = _GEN_6; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_16; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_16 = _GEN_6; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_16; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_16 = _GEN_6; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_17 = {1'h0, _io_dis_uops_0_ready_T_15} + {1'h0, _io_dis_uops_0_ready_T_16}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_18 = _io_dis_uops_0_ready_T_17; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_0_ready_T_19 = {2'h0, _io_dis_uops_0_ready_T_14} + {1'h0, _io_dis_uops_0_ready_T_18}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_20 = _io_dis_uops_0_ready_T_19[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [3:0] _io_dis_uops_0_ready_T_21 = {2'h0, _io_dis_uops_0_ready_T_20}; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [2:0] _io_dis_uops_0_ready_T_22 = _io_dis_uops_0_ready_T_21[2:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_0_ready_T_23 = _io_dis_uops_0_ready_T_13 > {1'h0, _io_dis_uops_0_ready_T_22}; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_0_ready_0 = io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36] wire [1:0] _io_dis_uops_1_ready_T_1 = _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_3 = _io_dis_uops_1_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_4 = {1'h0, _io_dis_uops_1_ready_T_1} + {1'h0, _io_dis_uops_1_ready_T_3}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_5 = _io_dis_uops_1_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_7 = _io_dis_uops_1_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_9 = _io_dis_uops_1_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_10 = {1'h0, _io_dis_uops_1_ready_T_7} + {1'h0, _io_dis_uops_1_ready_T_9}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_11 = _io_dis_uops_1_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_12 = {1'h0, _io_dis_uops_1_ready_T_5} + {1'h0, _io_dis_uops_1_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_13 = _io_dis_uops_1_ready_T_12; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_17 = {1'h0, _io_dis_uops_1_ready_T_15} + {1'h0, _io_dis_uops_1_ready_T_16}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_1_ready_T_18 = _io_dis_uops_1_ready_T_17; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_1_ready_T_19 = {2'h0, _io_dis_uops_1_ready_T_14} + {1'h0, _io_dis_uops_1_ready_T_18}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_1_ready_T_20 = _io_dis_uops_1_ready_T_19[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [3:0] _io_dis_uops_1_ready_T_21 = {2'h0, _io_dis_uops_1_ready_T_20} + 4'h1; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [2:0] _io_dis_uops_1_ready_T_22 = _io_dis_uops_1_ready_T_21[2:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_1_ready_T_23 = _io_dis_uops_1_ready_T_13 > {1'h0, _io_dis_uops_1_ready_T_22}; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_1_ready_0 = io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36] wire [1:0] _io_dis_uops_2_ready_T_1 = _io_dis_uops_2_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_3 = _io_dis_uops_2_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_4 = {1'h0, _io_dis_uops_2_ready_T_1} + {1'h0, _io_dis_uops_2_ready_T_3}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_5 = _io_dis_uops_2_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_7 = _io_dis_uops_2_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_9 = _io_dis_uops_2_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_10 = {1'h0, _io_dis_uops_2_ready_T_7} + {1'h0, _io_dis_uops_2_ready_T_9}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_11 = _io_dis_uops_2_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_2_ready_T_12 = {1'h0, _io_dis_uops_2_ready_T_5} + {1'h0, _io_dis_uops_2_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_2_ready_T_13 = _io_dis_uops_2_ready_T_12; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_17 = {1'h0, _io_dis_uops_2_ready_T_15} + {1'h0, _io_dis_uops_2_ready_T_16}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_2_ready_T_18 = _io_dis_uops_2_ready_T_17; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_2_ready_T_19 = {2'h0, _io_dis_uops_2_ready_T_14} + {1'h0, _io_dis_uops_2_ready_T_18}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_2_ready_T_20 = _io_dis_uops_2_ready_T_19[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [3:0] _io_dis_uops_2_ready_T_21 = {2'h0, _io_dis_uops_2_ready_T_20} + 4'h2; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [2:0] _io_dis_uops_2_ready_T_22 = _io_dis_uops_2_ready_T_21[2:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_2_ready_T_23 = _io_dis_uops_2_ready_T_13 > {1'h0, _io_dis_uops_2_ready_T_22}; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_2_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_2_ready_0 = io_dis_uops_2_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36]
Generate the Verilog code corresponding to this FIRRTL code module Tile_155 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_411 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_155( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_411 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_162 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_290 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_162( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_290 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_504 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_504( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_261 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_485 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_261( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_485 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_6 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_83 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_84 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_85 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_86 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_6( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_83 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_84 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_85 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_86 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module FDivSqrtUnit : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<65>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0], flip fcsr_rm : UInt<3>} connect io.resp.valid, UInt<1>(0h0) invalidate io.resp.bits.sfence.bits.hg invalidate io.resp.bits.sfence.bits.hv invalidate io.resp.bits.sfence.bits.asid invalidate io.resp.bits.sfence.bits.addr invalidate io.resp.bits.sfence.bits.rs2 invalidate io.resp.bits.sfence.bits.rs1 invalidate io.resp.bits.sfence.valid invalidate io.resp.bits.mxcpt.bits invalidate io.resp.bits.mxcpt.valid invalidate io.resp.bits.addr invalidate io.resp.bits.fflags.bits.flags invalidate io.resp.bits.fflags.bits.uop.debug_tsrc invalidate io.resp.bits.fflags.bits.uop.debug_fsrc invalidate io.resp.bits.fflags.bits.uop.bp_xcpt_if invalidate io.resp.bits.fflags.bits.uop.bp_debug_if invalidate io.resp.bits.fflags.bits.uop.xcpt_ma_if invalidate io.resp.bits.fflags.bits.uop.xcpt_ae_if invalidate io.resp.bits.fflags.bits.uop.xcpt_pf_if invalidate io.resp.bits.fflags.bits.uop.fp_single invalidate io.resp.bits.fflags.bits.uop.fp_val invalidate io.resp.bits.fflags.bits.uop.frs3_en invalidate io.resp.bits.fflags.bits.uop.lrs2_rtype invalidate io.resp.bits.fflags.bits.uop.lrs1_rtype invalidate io.resp.bits.fflags.bits.uop.dst_rtype invalidate io.resp.bits.fflags.bits.uop.ldst_val invalidate io.resp.bits.fflags.bits.uop.lrs3 invalidate io.resp.bits.fflags.bits.uop.lrs2 invalidate io.resp.bits.fflags.bits.uop.lrs1 invalidate io.resp.bits.fflags.bits.uop.ldst invalidate io.resp.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.resp.bits.fflags.bits.uop.flush_on_commit invalidate io.resp.bits.fflags.bits.uop.is_unique invalidate io.resp.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.resp.bits.fflags.bits.uop.uses_stq invalidate io.resp.bits.fflags.bits.uop.uses_ldq invalidate io.resp.bits.fflags.bits.uop.is_amo invalidate io.resp.bits.fflags.bits.uop.is_fencei invalidate io.resp.bits.fflags.bits.uop.is_fence invalidate io.resp.bits.fflags.bits.uop.mem_signed invalidate io.resp.bits.fflags.bits.uop.mem_size invalidate io.resp.bits.fflags.bits.uop.mem_cmd invalidate io.resp.bits.fflags.bits.uop.bypassable invalidate io.resp.bits.fflags.bits.uop.exc_cause invalidate io.resp.bits.fflags.bits.uop.exception invalidate io.resp.bits.fflags.bits.uop.stale_pdst invalidate io.resp.bits.fflags.bits.uop.ppred_busy invalidate io.resp.bits.fflags.bits.uop.prs3_busy invalidate io.resp.bits.fflags.bits.uop.prs2_busy invalidate io.resp.bits.fflags.bits.uop.prs1_busy invalidate io.resp.bits.fflags.bits.uop.ppred invalidate io.resp.bits.fflags.bits.uop.prs3 invalidate io.resp.bits.fflags.bits.uop.prs2 invalidate io.resp.bits.fflags.bits.uop.prs1 invalidate io.resp.bits.fflags.bits.uop.pdst invalidate io.resp.bits.fflags.bits.uop.rxq_idx invalidate io.resp.bits.fflags.bits.uop.stq_idx invalidate io.resp.bits.fflags.bits.uop.ldq_idx invalidate io.resp.bits.fflags.bits.uop.rob_idx invalidate io.resp.bits.fflags.bits.uop.csr_addr invalidate io.resp.bits.fflags.bits.uop.imm_packed invalidate io.resp.bits.fflags.bits.uop.taken invalidate io.resp.bits.fflags.bits.uop.pc_lob invalidate io.resp.bits.fflags.bits.uop.edge_inst invalidate io.resp.bits.fflags.bits.uop.ftq_idx invalidate io.resp.bits.fflags.bits.uop.br_tag invalidate io.resp.bits.fflags.bits.uop.br_mask invalidate io.resp.bits.fflags.bits.uop.is_sfb invalidate io.resp.bits.fflags.bits.uop.is_jal invalidate io.resp.bits.fflags.bits.uop.is_jalr invalidate io.resp.bits.fflags.bits.uop.is_br invalidate io.resp.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.resp.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.resp.bits.fflags.bits.uop.iw_state invalidate io.resp.bits.fflags.bits.uop.ctrl.is_std invalidate io.resp.bits.fflags.bits.uop.ctrl.is_sta invalidate io.resp.bits.fflags.bits.uop.ctrl.is_load invalidate io.resp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.resp.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.br_type invalidate io.resp.bits.fflags.bits.uop.fu_code invalidate io.resp.bits.fflags.bits.uop.iq_type invalidate io.resp.bits.fflags.bits.uop.debug_pc invalidate io.resp.bits.fflags.bits.uop.is_rvc invalidate io.resp.bits.fflags.bits.uop.debug_inst invalidate io.resp.bits.fflags.bits.uop.inst invalidate io.resp.bits.fflags.bits.uop.uopc invalidate io.resp.bits.fflags.valid invalidate io.resp.bits.data invalidate io.resp.bits.predicated invalidate io.resp.bits.uop.debug_tsrc invalidate io.resp.bits.uop.debug_fsrc invalidate io.resp.bits.uop.bp_xcpt_if invalidate io.resp.bits.uop.bp_debug_if invalidate io.resp.bits.uop.xcpt_ma_if invalidate io.resp.bits.uop.xcpt_ae_if invalidate io.resp.bits.uop.xcpt_pf_if invalidate io.resp.bits.uop.fp_single invalidate io.resp.bits.uop.fp_val invalidate io.resp.bits.uop.frs3_en invalidate io.resp.bits.uop.lrs2_rtype invalidate io.resp.bits.uop.lrs1_rtype invalidate io.resp.bits.uop.dst_rtype invalidate io.resp.bits.uop.ldst_val invalidate io.resp.bits.uop.lrs3 invalidate io.resp.bits.uop.lrs2 invalidate io.resp.bits.uop.lrs1 invalidate io.resp.bits.uop.ldst invalidate io.resp.bits.uop.ldst_is_rs1 invalidate io.resp.bits.uop.flush_on_commit invalidate io.resp.bits.uop.is_unique invalidate io.resp.bits.uop.is_sys_pc2epc invalidate io.resp.bits.uop.uses_stq invalidate io.resp.bits.uop.uses_ldq invalidate io.resp.bits.uop.is_amo invalidate io.resp.bits.uop.is_fencei invalidate io.resp.bits.uop.is_fence invalidate io.resp.bits.uop.mem_signed invalidate io.resp.bits.uop.mem_size invalidate io.resp.bits.uop.mem_cmd invalidate io.resp.bits.uop.bypassable invalidate io.resp.bits.uop.exc_cause invalidate io.resp.bits.uop.exception invalidate io.resp.bits.uop.stale_pdst invalidate io.resp.bits.uop.ppred_busy invalidate io.resp.bits.uop.prs3_busy invalidate io.resp.bits.uop.prs2_busy invalidate io.resp.bits.uop.prs1_busy invalidate io.resp.bits.uop.ppred invalidate io.resp.bits.uop.prs3 invalidate io.resp.bits.uop.prs2 invalidate io.resp.bits.uop.prs1 invalidate io.resp.bits.uop.pdst invalidate io.resp.bits.uop.rxq_idx invalidate io.resp.bits.uop.stq_idx invalidate io.resp.bits.uop.ldq_idx invalidate io.resp.bits.uop.rob_idx invalidate io.resp.bits.uop.csr_addr invalidate io.resp.bits.uop.imm_packed invalidate io.resp.bits.uop.taken invalidate io.resp.bits.uop.pc_lob invalidate io.resp.bits.uop.edge_inst invalidate io.resp.bits.uop.ftq_idx invalidate io.resp.bits.uop.br_tag invalidate io.resp.bits.uop.br_mask invalidate io.resp.bits.uop.is_sfb invalidate io.resp.bits.uop.is_jal invalidate io.resp.bits.uop.is_jalr invalidate io.resp.bits.uop.is_br invalidate io.resp.bits.uop.iw_p2_poisoned invalidate io.resp.bits.uop.iw_p1_poisoned invalidate io.resp.bits.uop.iw_state invalidate io.resp.bits.uop.ctrl.is_std invalidate io.resp.bits.uop.ctrl.is_sta invalidate io.resp.bits.uop.ctrl.is_load invalidate io.resp.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.uop.ctrl.op_fcn invalidate io.resp.bits.uop.ctrl.imm_sel invalidate io.resp.bits.uop.ctrl.op2_sel invalidate io.resp.bits.uop.ctrl.op1_sel invalidate io.resp.bits.uop.ctrl.br_type invalidate io.resp.bits.uop.fu_code invalidate io.resp.bits.uop.iq_type invalidate io.resp.bits.uop.debug_pc invalidate io.resp.bits.uop.is_rvc invalidate io.resp.bits.uop.debug_inst invalidate io.resp.bits.uop.inst invalidate io.resp.bits.uop.uopc regreset r_buffer_val : UInt<1>, clock, reset, UInt<1>(0h0) reg r_buffer_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}, clock reg r_buffer_fin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock inst fdiv_decoder of UOPCodeFDivDecoder connect fdiv_decoder.clock, clock connect fdiv_decoder.reset, reset connect fdiv_decoder.io.uopc, io.req.bits.uop.uopc node _r_buffer_val_T = and(io.brupdate.b1.mispredict_mask, r_buffer_req.uop.br_mask) node _r_buffer_val_T_1 = neq(_r_buffer_val_T, UInt<1>(0h0)) node _r_buffer_val_T_2 = eq(_r_buffer_val_T_1, UInt<1>(0h0)) node _r_buffer_val_T_3 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_buffer_val_T_4 = and(_r_buffer_val_T_2, _r_buffer_val_T_3) node _r_buffer_val_T_5 = and(_r_buffer_val_T_4, r_buffer_val) connect r_buffer_val, _r_buffer_val_T_5 node _r_buffer_req_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_buffer_req_uop_br_mask_T_1 = and(r_buffer_req.uop.br_mask, _r_buffer_req_uop_br_mask_T) connect r_buffer_req.uop.br_mask, _r_buffer_req_uop_br_mask_T_1 node _io_req_ready_T = eq(r_buffer_val, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _in1_upconvert_prev_unswizzled_T = bits(io.req.bits.rs1_data, 31, 31) node _in1_upconvert_prev_unswizzled_T_1 = bits(io.req.bits.rs1_data, 52, 52) node _in1_upconvert_prev_unswizzled_T_2 = bits(io.req.bits.rs1_data, 30, 0) node in1_upconvert_prev_unswizzled_hi = cat(_in1_upconvert_prev_unswizzled_T, _in1_upconvert_prev_unswizzled_T_1) node in1_upconvert_floats_0 = cat(in1_upconvert_prev_unswizzled_hi, _in1_upconvert_prev_unswizzled_T_2) node _in1_upconvert_prev_isbox_T = bits(io.req.bits.rs1_data, 64, 60) node in1_upconvert_prev_isbox = andr(_in1_upconvert_prev_isbox_T) node in1_upconvert_oks_0 = and(in1_upconvert_prev_isbox, UInt<1>(0h1)) node in1_upconvert_sign = bits(io.req.bits.rs1_data, 64, 64) node in1_upconvert_fractIn = bits(io.req.bits.rs1_data, 51, 0) node in1_upconvert_expIn = bits(io.req.bits.rs1_data, 63, 52) node _in1_upconvert_fractOut_T = shl(in1_upconvert_fractIn, 24) node in1_upconvert_fractOut = shr(_in1_upconvert_fractOut_T, 53) node in1_upconvert_expOut_expCode = bits(in1_upconvert_expIn, 11, 9) node _in1_upconvert_expOut_commonCase_T = add(in1_upconvert_expIn, UInt<9>(0h100)) node _in1_upconvert_expOut_commonCase_T_1 = tail(_in1_upconvert_expOut_commonCase_T, 1) node _in1_upconvert_expOut_commonCase_T_2 = sub(_in1_upconvert_expOut_commonCase_T_1, UInt<12>(0h800)) node in1_upconvert_expOut_commonCase = tail(_in1_upconvert_expOut_commonCase_T_2, 1) node _in1_upconvert_expOut_T = eq(in1_upconvert_expOut_expCode, UInt<1>(0h0)) node _in1_upconvert_expOut_T_1 = geq(in1_upconvert_expOut_expCode, UInt<3>(0h6)) node _in1_upconvert_expOut_T_2 = or(_in1_upconvert_expOut_T, _in1_upconvert_expOut_T_1) node _in1_upconvert_expOut_T_3 = bits(in1_upconvert_expOut_commonCase, 5, 0) node _in1_upconvert_expOut_T_4 = cat(in1_upconvert_expOut_expCode, _in1_upconvert_expOut_T_3) node _in1_upconvert_expOut_T_5 = bits(in1_upconvert_expOut_commonCase, 8, 0) node in1_upconvert_expOut = mux(_in1_upconvert_expOut_T_2, _in1_upconvert_expOut_T_4, _in1_upconvert_expOut_T_5) node in1_upconvert_hi = cat(in1_upconvert_sign, in1_upconvert_expOut) node in1_upconvert_floats_1 = cat(in1_upconvert_hi, in1_upconvert_fractOut) node _in1_upconvert_T = mux(in1_upconvert_oks_0, UInt<1>(0h0), UInt<33>(0he0400000)) node _in1_upconvert_T_1 = or(in1_upconvert_floats_0, _in1_upconvert_T) inst in1_upconvert_s2d of RecFNToRecFN_1 connect in1_upconvert_s2d.io.in, _in1_upconvert_T_1 connect in1_upconvert_s2d.io.roundingMode, UInt<1>(0h0) invalidate in1_upconvert_s2d.io.detectTininess node _in2_upconvert_prev_unswizzled_T = bits(io.req.bits.rs2_data, 31, 31) node _in2_upconvert_prev_unswizzled_T_1 = bits(io.req.bits.rs2_data, 52, 52) node _in2_upconvert_prev_unswizzled_T_2 = bits(io.req.bits.rs2_data, 30, 0) node in2_upconvert_prev_unswizzled_hi = cat(_in2_upconvert_prev_unswizzled_T, _in2_upconvert_prev_unswizzled_T_1) node in2_upconvert_floats_0 = cat(in2_upconvert_prev_unswizzled_hi, _in2_upconvert_prev_unswizzled_T_2) node _in2_upconvert_prev_isbox_T = bits(io.req.bits.rs2_data, 64, 60) node in2_upconvert_prev_isbox = andr(_in2_upconvert_prev_isbox_T) node in2_upconvert_oks_0 = and(in2_upconvert_prev_isbox, UInt<1>(0h1)) node in2_upconvert_sign = bits(io.req.bits.rs2_data, 64, 64) node in2_upconvert_fractIn = bits(io.req.bits.rs2_data, 51, 0) node in2_upconvert_expIn = bits(io.req.bits.rs2_data, 63, 52) node _in2_upconvert_fractOut_T = shl(in2_upconvert_fractIn, 24) node in2_upconvert_fractOut = shr(_in2_upconvert_fractOut_T, 53) node in2_upconvert_expOut_expCode = bits(in2_upconvert_expIn, 11, 9) node _in2_upconvert_expOut_commonCase_T = add(in2_upconvert_expIn, UInt<9>(0h100)) node _in2_upconvert_expOut_commonCase_T_1 = tail(_in2_upconvert_expOut_commonCase_T, 1) node _in2_upconvert_expOut_commonCase_T_2 = sub(_in2_upconvert_expOut_commonCase_T_1, UInt<12>(0h800)) node in2_upconvert_expOut_commonCase = tail(_in2_upconvert_expOut_commonCase_T_2, 1) node _in2_upconvert_expOut_T = eq(in2_upconvert_expOut_expCode, UInt<1>(0h0)) node _in2_upconvert_expOut_T_1 = geq(in2_upconvert_expOut_expCode, UInt<3>(0h6)) node _in2_upconvert_expOut_T_2 = or(_in2_upconvert_expOut_T, _in2_upconvert_expOut_T_1) node _in2_upconvert_expOut_T_3 = bits(in2_upconvert_expOut_commonCase, 5, 0) node _in2_upconvert_expOut_T_4 = cat(in2_upconvert_expOut_expCode, _in2_upconvert_expOut_T_3) node _in2_upconvert_expOut_T_5 = bits(in2_upconvert_expOut_commonCase, 8, 0) node in2_upconvert_expOut = mux(_in2_upconvert_expOut_T_2, _in2_upconvert_expOut_T_4, _in2_upconvert_expOut_T_5) node in2_upconvert_hi = cat(in2_upconvert_sign, in2_upconvert_expOut) node in2_upconvert_floats_1 = cat(in2_upconvert_hi, in2_upconvert_fractOut) node _in2_upconvert_T = mux(in2_upconvert_oks_0, UInt<1>(0h0), UInt<33>(0he0400000)) node _in2_upconvert_T_1 = or(in2_upconvert_floats_0, _in2_upconvert_T) inst in2_upconvert_s2d of RecFNToRecFN_2 connect in2_upconvert_s2d.io.in, _in2_upconvert_T_1 connect in2_upconvert_s2d.io.roundingMode, UInt<1>(0h0) invalidate in2_upconvert_s2d.io.detectTininess node _T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask) node _T_1 = neq(_T, UInt<1>(0h0)) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = and(io.req.valid, _T_2) node _T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _T_5 = and(_T_3, _T_4) when _T_5 : connect r_buffer_val, UInt<1>(0h1) connect r_buffer_req, io.req.bits node _r_buffer_req_uop_br_mask_T_2 = not(io.brupdate.b1.resolve_mask) node _r_buffer_req_uop_br_mask_T_3 = and(io.req.bits.uop.br_mask, _r_buffer_req_uop_br_mask_T_2) connect r_buffer_req.uop.br_mask, _r_buffer_req_uop_br_mask_T_3 connect r_buffer_fin.vec, fdiv_decoder.io.sigs.vec connect r_buffer_fin.wflags, fdiv_decoder.io.sigs.wflags connect r_buffer_fin.sqrt, fdiv_decoder.io.sigs.sqrt connect r_buffer_fin.div, fdiv_decoder.io.sigs.div connect r_buffer_fin.fma, fdiv_decoder.io.sigs.fma connect r_buffer_fin.fastpipe, fdiv_decoder.io.sigs.fastpipe connect r_buffer_fin.toint, fdiv_decoder.io.sigs.toint connect r_buffer_fin.fromint, fdiv_decoder.io.sigs.fromint connect r_buffer_fin.typeTagOut, fdiv_decoder.io.sigs.typeTagOut connect r_buffer_fin.typeTagIn, fdiv_decoder.io.sigs.typeTagIn connect r_buffer_fin.swap23, fdiv_decoder.io.sigs.swap23 connect r_buffer_fin.swap12, fdiv_decoder.io.sigs.swap12 connect r_buffer_fin.ren3, fdiv_decoder.io.sigs.ren3 connect r_buffer_fin.ren2, fdiv_decoder.io.sigs.ren2 connect r_buffer_fin.ren1, fdiv_decoder.io.sigs.ren1 connect r_buffer_fin.wen, fdiv_decoder.io.sigs.wen connect r_buffer_fin.ldst, fdiv_decoder.io.sigs.ldst node _r_buffer_fin_rm_T = bits(io.req.bits.uop.imm_packed, 2, 0) node _r_buffer_fin_rm_T_1 = eq(_r_buffer_fin_rm_T, UInt<3>(0h7)) node _r_buffer_fin_rm_T_2 = bits(io.req.bits.uop.imm_packed, 2, 0) node _r_buffer_fin_rm_T_3 = mux(_r_buffer_fin_rm_T_1, io.fcsr_rm, _r_buffer_fin_rm_T_2) connect r_buffer_fin.rm, _r_buffer_fin_rm_T_3 connect r_buffer_fin.typ, UInt<1>(0h0) node _r_buffer_fin_in1_prev_unswizzled_T = bits(io.req.bits.rs1_data, 31, 31) node _r_buffer_fin_in1_prev_unswizzled_T_1 = bits(io.req.bits.rs1_data, 52, 52) node _r_buffer_fin_in1_prev_unswizzled_T_2 = bits(io.req.bits.rs1_data, 30, 0) node r_buffer_fin_in1_prev_unswizzled_hi = cat(_r_buffer_fin_in1_prev_unswizzled_T, _r_buffer_fin_in1_prev_unswizzled_T_1) node r_buffer_fin_in1_prev_unswizzled = cat(r_buffer_fin_in1_prev_unswizzled_hi, _r_buffer_fin_in1_prev_unswizzled_T_2) node r_buffer_fin_in1_prev_prev_sign = bits(r_buffer_fin_in1_prev_unswizzled, 32, 32) node r_buffer_fin_in1_prev_prev_fractIn = bits(r_buffer_fin_in1_prev_unswizzled, 22, 0) node r_buffer_fin_in1_prev_prev_expIn = bits(r_buffer_fin_in1_prev_unswizzled, 31, 23) node _r_buffer_fin_in1_prev_prev_fractOut_T = shl(r_buffer_fin_in1_prev_prev_fractIn, 53) node r_buffer_fin_in1_prev_prev_fractOut = shr(_r_buffer_fin_in1_prev_prev_fractOut_T, 24) node r_buffer_fin_in1_prev_prev_expOut_expCode = bits(r_buffer_fin_in1_prev_prev_expIn, 8, 6) node _r_buffer_fin_in1_prev_prev_expOut_commonCase_T = add(r_buffer_fin_in1_prev_prev_expIn, UInt<12>(0h800)) node _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_1 = tail(_r_buffer_fin_in1_prev_prev_expOut_commonCase_T, 1) node _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_2 = sub(_r_buffer_fin_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node r_buffer_fin_in1_prev_prev_expOut_commonCase = tail(_r_buffer_fin_in1_prev_prev_expOut_commonCase_T_2, 1) node _r_buffer_fin_in1_prev_prev_expOut_T = eq(r_buffer_fin_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _r_buffer_fin_in1_prev_prev_expOut_T_1 = geq(r_buffer_fin_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _r_buffer_fin_in1_prev_prev_expOut_T_2 = or(_r_buffer_fin_in1_prev_prev_expOut_T, _r_buffer_fin_in1_prev_prev_expOut_T_1) node _r_buffer_fin_in1_prev_prev_expOut_T_3 = bits(r_buffer_fin_in1_prev_prev_expOut_commonCase, 8, 0) node _r_buffer_fin_in1_prev_prev_expOut_T_4 = cat(r_buffer_fin_in1_prev_prev_expOut_expCode, _r_buffer_fin_in1_prev_prev_expOut_T_3) node _r_buffer_fin_in1_prev_prev_expOut_T_5 = bits(r_buffer_fin_in1_prev_prev_expOut_commonCase, 11, 0) node r_buffer_fin_in1_prev_prev_expOut = mux(_r_buffer_fin_in1_prev_prev_expOut_T_2, _r_buffer_fin_in1_prev_prev_expOut_T_4, _r_buffer_fin_in1_prev_prev_expOut_T_5) node r_buffer_fin_in1_prev_prev_hi = cat(r_buffer_fin_in1_prev_prev_sign, r_buffer_fin_in1_prev_prev_expOut) node r_buffer_fin_in1_floats_0 = cat(r_buffer_fin_in1_prev_prev_hi, r_buffer_fin_in1_prev_prev_fractOut) node _r_buffer_fin_in1_prev_isbox_T = bits(io.req.bits.rs1_data, 64, 60) node r_buffer_fin_in1_prev_isbox = andr(_r_buffer_fin_in1_prev_isbox_T) node r_buffer_fin_in1_oks_0 = and(r_buffer_fin_in1_prev_isbox, UInt<1>(0h1)) node _r_buffer_fin_in1_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _r_buffer_fin_in1_T_1 = or(io.req.bits.rs1_data, _r_buffer_fin_in1_T) connect r_buffer_fin.in1, _r_buffer_fin_in1_T_1 node _r_buffer_fin_in2_prev_unswizzled_T = bits(io.req.bits.rs2_data, 31, 31) node _r_buffer_fin_in2_prev_unswizzled_T_1 = bits(io.req.bits.rs2_data, 52, 52) node _r_buffer_fin_in2_prev_unswizzled_T_2 = bits(io.req.bits.rs2_data, 30, 0) node r_buffer_fin_in2_prev_unswizzled_hi = cat(_r_buffer_fin_in2_prev_unswizzled_T, _r_buffer_fin_in2_prev_unswizzled_T_1) node r_buffer_fin_in2_prev_unswizzled = cat(r_buffer_fin_in2_prev_unswizzled_hi, _r_buffer_fin_in2_prev_unswizzled_T_2) node r_buffer_fin_in2_prev_prev_sign = bits(r_buffer_fin_in2_prev_unswizzled, 32, 32) node r_buffer_fin_in2_prev_prev_fractIn = bits(r_buffer_fin_in2_prev_unswizzled, 22, 0) node r_buffer_fin_in2_prev_prev_expIn = bits(r_buffer_fin_in2_prev_unswizzled, 31, 23) node _r_buffer_fin_in2_prev_prev_fractOut_T = shl(r_buffer_fin_in2_prev_prev_fractIn, 53) node r_buffer_fin_in2_prev_prev_fractOut = shr(_r_buffer_fin_in2_prev_prev_fractOut_T, 24) node r_buffer_fin_in2_prev_prev_expOut_expCode = bits(r_buffer_fin_in2_prev_prev_expIn, 8, 6) node _r_buffer_fin_in2_prev_prev_expOut_commonCase_T = add(r_buffer_fin_in2_prev_prev_expIn, UInt<12>(0h800)) node _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_1 = tail(_r_buffer_fin_in2_prev_prev_expOut_commonCase_T, 1) node _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_2 = sub(_r_buffer_fin_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node r_buffer_fin_in2_prev_prev_expOut_commonCase = tail(_r_buffer_fin_in2_prev_prev_expOut_commonCase_T_2, 1) node _r_buffer_fin_in2_prev_prev_expOut_T = eq(r_buffer_fin_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _r_buffer_fin_in2_prev_prev_expOut_T_1 = geq(r_buffer_fin_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _r_buffer_fin_in2_prev_prev_expOut_T_2 = or(_r_buffer_fin_in2_prev_prev_expOut_T, _r_buffer_fin_in2_prev_prev_expOut_T_1) node _r_buffer_fin_in2_prev_prev_expOut_T_3 = bits(r_buffer_fin_in2_prev_prev_expOut_commonCase, 8, 0) node _r_buffer_fin_in2_prev_prev_expOut_T_4 = cat(r_buffer_fin_in2_prev_prev_expOut_expCode, _r_buffer_fin_in2_prev_prev_expOut_T_3) node _r_buffer_fin_in2_prev_prev_expOut_T_5 = bits(r_buffer_fin_in2_prev_prev_expOut_commonCase, 11, 0) node r_buffer_fin_in2_prev_prev_expOut = mux(_r_buffer_fin_in2_prev_prev_expOut_T_2, _r_buffer_fin_in2_prev_prev_expOut_T_4, _r_buffer_fin_in2_prev_prev_expOut_T_5) node r_buffer_fin_in2_prev_prev_hi = cat(r_buffer_fin_in2_prev_prev_sign, r_buffer_fin_in2_prev_prev_expOut) node r_buffer_fin_in2_floats_0 = cat(r_buffer_fin_in2_prev_prev_hi, r_buffer_fin_in2_prev_prev_fractOut) node _r_buffer_fin_in2_prev_isbox_T = bits(io.req.bits.rs2_data, 64, 60) node r_buffer_fin_in2_prev_isbox = andr(_r_buffer_fin_in2_prev_isbox_T) node r_buffer_fin_in2_oks_0 = and(r_buffer_fin_in2_prev_isbox, UInt<1>(0h1)) node _r_buffer_fin_in2_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _r_buffer_fin_in2_T_1 = or(io.req.bits.rs2_data, _r_buffer_fin_in2_T) connect r_buffer_fin.in2, _r_buffer_fin_in2_T_1 node _T_6 = eq(fdiv_decoder.io.sigs.typeTagIn, UInt<1>(0h0)) when _T_6 : connect r_buffer_fin.in1, in1_upconvert_s2d.io.out connect r_buffer_fin.in2, in2_upconvert_s2d.io.out node _T_7 = and(r_buffer_val, io.req.valid) node _T_8 = eq(_T_7, UInt<1>(0h0)) node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : node _T_11 = eq(_T_8, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "Assertion failed: [fdiv] a request is incoming while the buffer is already full.\n at fdiv.scala:138 assert (!(r_buffer_val && io.req.valid), \"[fdiv] a request is incoming while the buffer is already full.\")\n") : printf assert(clock, _T_8, UInt<1>(0h1), "") : assert inst divsqrt of DivSqrtRecF64 connect divsqrt.clock, clock connect divsqrt.reset, reset regreset r_divsqrt_val : UInt<1>, clock, reset, UInt<1>(0h0) reg r_divsqrt_killed : UInt<1>, clock reg r_divsqrt_fin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock reg r_divsqrt_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock wire output_buffer_available : UInt<1> node _may_fire_input_T = or(r_buffer_fin.div, r_buffer_fin.sqrt) node _may_fire_input_T_1 = and(r_buffer_val, _may_fire_input_T) node _may_fire_input_T_2 = eq(r_divsqrt_val, UInt<1>(0h0)) node _may_fire_input_T_3 = and(_may_fire_input_T_1, _may_fire_input_T_2) node may_fire_input = and(_may_fire_input_T_3, output_buffer_available) node divsqrt_ready = mux(divsqrt.io.sqrtOp, divsqrt.io.inReady_sqrt, divsqrt.io.inReady_div) connect divsqrt.io.inValid, may_fire_input connect divsqrt.io.sqrtOp, r_buffer_fin.sqrt connect divsqrt.io.a, r_buffer_fin.in1 node _divsqrt_io_b_T = mux(divsqrt.io.sqrtOp, r_buffer_fin.in1, r_buffer_fin.in2) connect divsqrt.io.b, _divsqrt_io_b_T connect divsqrt.io.roundingMode, r_buffer_fin.rm invalidate divsqrt.io.detectTininess node _r_divsqrt_killed_T = and(io.brupdate.b1.mispredict_mask, r_divsqrt_uop.br_mask) node _r_divsqrt_killed_T_1 = neq(_r_divsqrt_killed_T, UInt<1>(0h0)) node _r_divsqrt_killed_T_2 = or(r_divsqrt_killed, _r_divsqrt_killed_T_1) node _r_divsqrt_killed_T_3 = or(_r_divsqrt_killed_T_2, io.req.bits.kill) connect r_divsqrt_killed, _r_divsqrt_killed_T_3 node _r_divsqrt_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_divsqrt_uop_br_mask_T_1 = and(r_divsqrt_uop.br_mask, _r_divsqrt_uop_br_mask_T) connect r_divsqrt_uop.br_mask, _r_divsqrt_uop_br_mask_T_1 node _T_12 = and(may_fire_input, divsqrt_ready) when _T_12 : connect r_buffer_val, UInt<1>(0h0) connect r_divsqrt_val, UInt<1>(0h1) connect r_divsqrt_fin, r_buffer_fin connect r_divsqrt_uop, r_buffer_req.uop node _r_divsqrt_killed_T_4 = and(io.brupdate.b1.mispredict_mask, r_buffer_req.uop.br_mask) node _r_divsqrt_killed_T_5 = neq(_r_divsqrt_killed_T_4, UInt<1>(0h0)) node _r_divsqrt_killed_T_6 = or(_r_divsqrt_killed_T_5, io.req.bits.kill) connect r_divsqrt_killed, _r_divsqrt_killed_T_6 node _r_divsqrt_uop_br_mask_T_2 = not(io.brupdate.b1.resolve_mask) node _r_divsqrt_uop_br_mask_T_3 = and(r_buffer_req.uop.br_mask, _r_divsqrt_uop_br_mask_T_2) connect r_divsqrt_uop.br_mask, _r_divsqrt_uop_br_mask_T_3 regreset r_out_val : UInt<1>, clock, reset, UInt<1>(0h0) reg r_out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock reg r_out_flags_double : UInt, clock reg r_out_wdata_double : UInt, clock node _output_buffer_available_T = eq(r_out_val, UInt<1>(0h0)) connect output_buffer_available, _output_buffer_available_T node _r_out_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_out_uop_br_mask_T_1 = and(r_out_uop.br_mask, _r_out_uop_br_mask_T) connect r_out_uop.br_mask, _r_out_uop_br_mask_T_1 node _T_13 = and(io.brupdate.b1.mispredict_mask, r_out_uop.br_mask) node _T_14 = neq(_T_13, UInt<1>(0h0)) node _T_15 = or(io.resp.ready, _T_14) node _T_16 = or(_T_15, io.req.bits.kill) when _T_16 : connect r_out_val, UInt<1>(0h0) node _T_17 = or(divsqrt.io.outValid_div, divsqrt.io.outValid_sqrt) when _T_17 : connect r_divsqrt_val, UInt<1>(0h0) node _r_out_val_T = eq(r_divsqrt_killed, UInt<1>(0h0)) node _r_out_val_T_1 = and(io.brupdate.b1.mispredict_mask, r_divsqrt_uop.br_mask) node _r_out_val_T_2 = neq(_r_out_val_T_1, UInt<1>(0h0)) node _r_out_val_T_3 = eq(_r_out_val_T_2, UInt<1>(0h0)) node _r_out_val_T_4 = and(_r_out_val_T, _r_out_val_T_3) node _r_out_val_T_5 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_out_val_T_6 = and(_r_out_val_T_4, _r_out_val_T_5) connect r_out_val, _r_out_val_T_6 connect r_out_uop, r_divsqrt_uop node _r_out_uop_br_mask_T_2 = not(io.brupdate.b1.resolve_mask) node _r_out_uop_br_mask_T_3 = and(r_divsqrt_uop.br_mask, _r_out_uop_br_mask_T_2) connect r_out_uop.br_mask, _r_out_uop_br_mask_T_3 node _r_out_wdata_double_maskedNaN_T = not(UInt<65>(0h1010000000000000)) node r_out_wdata_double_maskedNaN = and(divsqrt.io.out, _r_out_wdata_double_maskedNaN_T) node _r_out_wdata_double_T = bits(divsqrt.io.out, 63, 61) node _r_out_wdata_double_T_1 = andr(_r_out_wdata_double_T) node _r_out_wdata_double_T_2 = mux(_r_out_wdata_double_T_1, r_out_wdata_double_maskedNaN, divsqrt.io.out) connect r_out_wdata_double, _r_out_wdata_double_T_2 connect r_out_flags_double, divsqrt.io.exceptionFlags node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(r_divsqrt_val, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed: [fdiv] a response is being generated for no request.\n at fdiv.scala:205 assert (r_divsqrt_val, \"[fdiv] a response is being generated for no request.\")\n") : printf_1 assert(clock, r_divsqrt_val, UInt<1>(0h1), "") : assert_1 node _T_21 = or(divsqrt.io.outValid_div, divsqrt.io.outValid_sqrt) node _T_22 = and(r_out_val, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: [fdiv] Buffered output being overwritten by another output from the fdiv/fsqrt unit.\n at fdiv.scala:208 assert (!(r_out_val && (divsqrt.io.outValid_div || divsqrt.io.outValid_sqrt)),\n") : printf_2 assert(clock, _T_23, UInt<1>(0h1), "") : assert_2 inst downvert_d2s of RecFNToRecFN_3 connect downvert_d2s.io.in, r_out_wdata_double connect downvert_d2s.io.roundingMode, r_divsqrt_fin.rm invalidate downvert_d2s.io.detectTininess node _out_flags_T = eq(r_divsqrt_fin.typeTagIn, UInt<1>(0h0)) node _out_flags_T_1 = mux(_out_flags_T, downvert_d2s.io.exceptionFlags, UInt<1>(0h0)) node out_flags = or(r_out_flags_double, _out_flags_T_1) node _io_resp_valid_T = and(io.brupdate.b1.mispredict_mask, r_out_uop.br_mask) node _io_resp_valid_T_1 = neq(_io_resp_valid_T, UInt<1>(0h0)) node _io_resp_valid_T_2 = eq(_io_resp_valid_T_1, UInt<1>(0h0)) node _io_resp_valid_T_3 = and(r_out_val, _io_resp_valid_T_2) connect io.resp.valid, _io_resp_valid_T_3 connect io.resp.bits.uop, r_out_uop node _io_resp_bits_data_T = eq(r_divsqrt_fin.typeTagIn, UInt<1>(0h0)) node _io_resp_bits_data_opts_bigger_swizzledNaN_T = andr(UInt<20>(0hfffff)) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_1 = bits(downvert_d2s.io.out, 31, 31) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_2 = bits(downvert_d2s.io.out, 32, 32) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_3 = bits(downvert_d2s.io.out, 30, 0) node io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi = cat(UInt<20>(0hfffff), _io_resp_bits_data_opts_bigger_swizzledNaN_T_2) node io_resp_bits_data_opts_bigger_swizzledNaN_lo = cat(io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi, _io_resp_bits_data_opts_bigger_swizzledNaN_T_3) node io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo = cat(UInt<7>(0h7f), _io_resp_bits_data_opts_bigger_swizzledNaN_T_1) node io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = cat(UInt<4>(0hf), _io_resp_bits_data_opts_bigger_swizzledNaN_T) node io_resp_bits_data_opts_bigger_swizzledNaN_hi = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi, io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo) node io_resp_bits_data_opts_bigger_swizzledNaN = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi, io_resp_bits_data_opts_bigger_swizzledNaN_lo) node _io_resp_bits_data_opts_bigger_T = andr(UInt<3>(0h7)) node io_resp_bits_data_opts_bigger = mux(_io_resp_bits_data_opts_bigger_T, io_resp_bits_data_opts_bigger_swizzledNaN, UInt<65>(0h1ffffffffffffffff)) node io_resp_bits_data_opts_0 = or(io_resp_bits_data_opts_bigger, UInt<1>(0h0)) node _io_resp_bits_data_T_1 = eq(UInt<1>(0h0), UInt<1>(0h1)) node _io_resp_bits_data_T_2 = mux(_io_resp_bits_data_T_1, downvert_d2s.io.out, io_resp_bits_data_opts_0) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_4 = andr(UInt<20>(0hfffff)) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_5 = bits(r_out_wdata_double, 31, 31) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_6 = bits(r_out_wdata_double, 32, 32) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_7 = bits(r_out_wdata_double, 30, 0) node io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi_1 = cat(UInt<20>(0hfffff), _io_resp_bits_data_opts_bigger_swizzledNaN_T_6) node io_resp_bits_data_opts_bigger_swizzledNaN_lo_1 = cat(io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi_1, _io_resp_bits_data_opts_bigger_swizzledNaN_T_7) node io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo_1 = cat(UInt<7>(0h7f), _io_resp_bits_data_opts_bigger_swizzledNaN_T_5) node io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi_1 = cat(UInt<4>(0hf), _io_resp_bits_data_opts_bigger_swizzledNaN_T_4) node io_resp_bits_data_opts_bigger_swizzledNaN_hi_1 = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi_1, io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo_1) node io_resp_bits_data_opts_bigger_swizzledNaN_1 = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi_1, io_resp_bits_data_opts_bigger_swizzledNaN_lo_1) node _io_resp_bits_data_opts_bigger_T_1 = andr(UInt<3>(0h7)) node io_resp_bits_data_opts_bigger_1 = mux(_io_resp_bits_data_opts_bigger_T_1, io_resp_bits_data_opts_bigger_swizzledNaN_1, UInt<65>(0h1ffffffffffffffff)) node io_resp_bits_data_opts_0_1 = or(io_resp_bits_data_opts_bigger_1, UInt<1>(0h0)) node _io_resp_bits_data_T_3 = eq(UInt<1>(0h1), UInt<1>(0h1)) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, r_out_wdata_double, io_resp_bits_data_opts_0_1) node _io_resp_bits_data_T_5 = mux(_io_resp_bits_data_T, _io_resp_bits_data_T_2, _io_resp_bits_data_T_4) connect io.resp.bits.data, _io_resp_bits_data_T_5 connect io.resp.bits.fflags.valid, io.resp.valid connect io.resp.bits.fflags.bits.uop, r_out_uop node _io_resp_bits_fflags_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_resp_bits_fflags_bits_uop_br_mask_T_1 = and(r_out_uop.br_mask, _io_resp_bits_fflags_bits_uop_br_mask_T) connect io.resp.bits.fflags.bits.uop.br_mask, _io_resp_bits_fflags_bits_uop_br_mask_T_1 connect io.resp.bits.fflags.bits.flags, out_flags
module FDivSqrtUnit( // @[fdiv.scala:84:7] input clock, // @[fdiv.scala:84:7] input reset, // @[fdiv.scala:84:7] output io_req_ready, // @[functional-unit.scala:168:14] input io_req_valid, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14] input [7:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14] input io_req_bits_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_req_bits_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14] input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14] input io_req_bits_kill, // @[functional-unit.scala:168:14] input io_resp_ready, // @[functional-unit.scala:168:14] output io_resp_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [7:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_fflags_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_fflags_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [7:0] io_resp_bits_fflags_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_fflags_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_fflags_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pdst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_prs3, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_fflags_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_flags, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14] input io_brupdate_b2_valid, // @[functional-unit.scala:168:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14] input io_brupdate_b2_taken, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14] input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14] input [2:0] io_fcsr_rm // @[functional-unit.scala:168:14] ); wire io_resp_valid_0; // @[fdiv.scala:84:7] wire [32:0] _downvert_d2s_io_out; // @[fdiv.scala:211:28] wire [4:0] _downvert_d2s_io_exceptionFlags; // @[fdiv.scala:211:28] wire _divsqrt_io_inReady_div; // @[fdiv.scala:143:23] wire _divsqrt_io_inReady_sqrt; // @[fdiv.scala:143:23] wire _divsqrt_io_outValid_div; // @[fdiv.scala:143:23] wire _divsqrt_io_outValid_sqrt; // @[fdiv.scala:143:23] wire [64:0] _divsqrt_io_out; // @[fdiv.scala:143:23] wire [4:0] _divsqrt_io_exceptionFlags; // @[fdiv.scala:143:23] wire [64:0] _in2_upconvert_s2d_io_out; // @[fdiv.scala:112:21] wire [64:0] _in1_upconvert_s2d_io_out; // @[fdiv.scala:112:21] wire _fdiv_decoder_io_sigs_ldst; // @[fdiv.scala:101:28] wire _fdiv_decoder_io_sigs_wen; // @[fdiv.scala:101:28] wire _fdiv_decoder_io_sigs_ren1; // @[fdiv.scala:101:28] wire _fdiv_decoder_io_sigs_ren2; // @[fdiv.scala:101:28] wire _fdiv_decoder_io_sigs_ren3; // @[fdiv.scala:101:28] wire _fdiv_decoder_io_sigs_swap12; // @[fdiv.scala:101:28] wire _fdiv_decoder_io_sigs_swap23; // @[fdiv.scala:101:28] wire [1:0] _fdiv_decoder_io_sigs_typeTagIn; // @[fdiv.scala:101:28] wire [1:0] _fdiv_decoder_io_sigs_typeTagOut; // @[fdiv.scala:101:28] wire _fdiv_decoder_io_sigs_fromint; // @[fdiv.scala:101:28] wire _fdiv_decoder_io_sigs_toint; // @[fdiv.scala:101:28] wire _fdiv_decoder_io_sigs_fastpipe; // @[fdiv.scala:101:28] wire _fdiv_decoder_io_sigs_fma; // @[fdiv.scala:101:28] wire _fdiv_decoder_io_sigs_div; // @[fdiv.scala:101:28] wire _fdiv_decoder_io_sigs_sqrt; // @[fdiv.scala:101:28] wire _fdiv_decoder_io_sigs_wflags; // @[fdiv.scala:101:28] wire io_req_valid_0 = io_req_valid; // @[fdiv.scala:84:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[fdiv.scala:84:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[fdiv.scala:84:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[fdiv.scala:84:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[fdiv.scala:84:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[fdiv.scala:84:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[fdiv.scala:84:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[fdiv.scala:84:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[fdiv.scala:84:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[fdiv.scala:84:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[fdiv.scala:84:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[fdiv.scala:84:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[fdiv.scala:84:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[fdiv.scala:84:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[fdiv.scala:84:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[fdiv.scala:84:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[fdiv.scala:84:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[fdiv.scala:84:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[fdiv.scala:84:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[fdiv.scala:84:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[fdiv.scala:84:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[fdiv.scala:84:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[fdiv.scala:84:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[fdiv.scala:84:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[fdiv.scala:84:7] wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[fdiv.scala:84:7] wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[fdiv.scala:84:7] wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[fdiv.scala:84:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[fdiv.scala:84:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[fdiv.scala:84:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[fdiv.scala:84:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[fdiv.scala:84:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[fdiv.scala:84:7] wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[fdiv.scala:84:7] wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[fdiv.scala:84:7] wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[fdiv.scala:84:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[fdiv.scala:84:7] wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[fdiv.scala:84:7] wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[fdiv.scala:84:7] wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[fdiv.scala:84:7] wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[fdiv.scala:84:7] wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[fdiv.scala:84:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[fdiv.scala:84:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[fdiv.scala:84:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[fdiv.scala:84:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[fdiv.scala:84:7] wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[fdiv.scala:84:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[fdiv.scala:84:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[fdiv.scala:84:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[fdiv.scala:84:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[fdiv.scala:84:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[fdiv.scala:84:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[fdiv.scala:84:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[fdiv.scala:84:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[fdiv.scala:84:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[fdiv.scala:84:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[fdiv.scala:84:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[fdiv.scala:84:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[fdiv.scala:84:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[fdiv.scala:84:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[fdiv.scala:84:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[fdiv.scala:84:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[fdiv.scala:84:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[fdiv.scala:84:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[fdiv.scala:84:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[fdiv.scala:84:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[fdiv.scala:84:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[fdiv.scala:84:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[fdiv.scala:84:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[fdiv.scala:84:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[fdiv.scala:84:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[fdiv.scala:84:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[fdiv.scala:84:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[fdiv.scala:84:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[fdiv.scala:84:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[fdiv.scala:84:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[fdiv.scala:84:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[fdiv.scala:84:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[fdiv.scala:84:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[fdiv.scala:84:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[fdiv.scala:84:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[fdiv.scala:84:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[fdiv.scala:84:7] wire io_resp_ready_0 = io_resp_ready; // @[fdiv.scala:84:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[fdiv.scala:84:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[fdiv.scala:84:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[fdiv.scala:84:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[fdiv.scala:84:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[fdiv.scala:84:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[fdiv.scala:84:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[fdiv.scala:84:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[fdiv.scala:84:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[fdiv.scala:84:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[fdiv.scala:84:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[fdiv.scala:84:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[fdiv.scala:84:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[fdiv.scala:84:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[fdiv.scala:84:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[fdiv.scala:84:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[fdiv.scala:84:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[fdiv.scala:84:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[fdiv.scala:84:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[fdiv.scala:84:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[fdiv.scala:84:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[fdiv.scala:84:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[fdiv.scala:84:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[fdiv.scala:84:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[fdiv.scala:84:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[fdiv.scala:84:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[fdiv.scala:84:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[fdiv.scala:84:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[fdiv.scala:84:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[fdiv.scala:84:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[fdiv.scala:84:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[fdiv.scala:84:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[fdiv.scala:84:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[fdiv.scala:84:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[fdiv.scala:84:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[fdiv.scala:84:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[fdiv.scala:84:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[fdiv.scala:84:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[fdiv.scala:84:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[fdiv.scala:84:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[fdiv.scala:84:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[fdiv.scala:84:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[fdiv.scala:84:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[fdiv.scala:84:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[fdiv.scala:84:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[fdiv.scala:84:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[fdiv.scala:84:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[fdiv.scala:84:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[fdiv.scala:84:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[fdiv.scala:84:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[fdiv.scala:84:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[fdiv.scala:84:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[fdiv.scala:84:7] wire io_req_bits_pred_data = 1'h0; // @[fdiv.scala:84:7] wire io_resp_bits_predicated = 1'h0; // @[fdiv.scala:84:7] wire io_resp_bits_mxcpt_valid = 1'h0; // @[fdiv.scala:84:7] wire io_resp_bits_sfence_valid = 1'h0; // @[fdiv.scala:84:7] wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[fdiv.scala:84:7] wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[fdiv.scala:84:7] wire io_resp_bits_sfence_bits_asid = 1'h0; // @[fdiv.scala:84:7] wire io_resp_bits_sfence_bits_hv = 1'h0; // @[fdiv.scala:84:7] wire io_resp_bits_sfence_bits_hg = 1'h0; // @[fdiv.scala:84:7] wire _io_resp_bits_data_T_1 = 1'h0; // @[package.scala:39:86] wire [64:0] io_req_bits_rs3_data = 65'h0; // @[fdiv.scala:84:7] wire [64:0] _r_buffer_fin_in1_T = 65'h0; // @[FPU.scala:372:31] wire [64:0] _r_buffer_fin_in2_T = 65'h0; // @[FPU.scala:372:31] wire [39:0] io_resp_bits_addr = 40'h0; // @[fdiv.scala:84:7] wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[fdiv.scala:84:7] wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[fdiv.scala:84:7] wire _io_resp_bits_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42] wire _io_resp_bits_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56] wire _io_resp_bits_data_opts_bigger_swizzledNaN_T_4 = 1'h1; // @[FPU.scala:338:42] wire _io_resp_bits_data_opts_bigger_T_1 = 1'h1; // @[FPU.scala:249:56] wire _io_resp_bits_data_T_3 = 1'h1; // @[package.scala:39:86] wire [4:0] io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [4:0] io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi_1 = 5'h1F; // @[FPU.scala:336:26] wire [64:0] _r_out_wdata_double_maskedNaN_T = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27] wire _io_req_ready_T; // @[fdiv.scala:109:19] wire [64:0] _r_buffer_fin_in1_T_1 = io_req_bits_rs1_data_0; // @[FPU.scala:372:26] wire [64:0] _r_buffer_fin_in2_T_1 = io_req_bits_rs2_data_0; // @[FPU.scala:372:26] wire _io_resp_valid_T_3; // @[fdiv.scala:218:30] wire io_resp_bits_fflags_valid_0 = io_resp_valid_0; // @[fdiv.scala:84:7] wire [64:0] _io_resp_bits_data_T_5; // @[fdiv.scala:221:8] wire [7:0] _io_resp_bits_fflags_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [4:0] out_flags; // @[fdiv.scala:216:38] wire io_req_ready_0; // @[fdiv.scala:84:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[fdiv.scala:84:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[fdiv.scala:84:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[fdiv.scala:84:7] wire [31:0] io_resp_bits_uop_inst_0; // @[fdiv.scala:84:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_is_rvc_0; // @[fdiv.scala:84:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[fdiv.scala:84:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_is_br_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_is_jalr_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_is_jal_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_is_sfb_0; // @[fdiv.scala:84:7] wire [7:0] io_resp_bits_uop_br_mask_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_uop_br_tag_0; // @[fdiv.scala:84:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_edge_inst_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_taken_0; // @[fdiv.scala:84:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[fdiv.scala:84:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[fdiv.scala:84:7] wire [4:0] io_resp_bits_uop_rob_idx_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_uop_ldq_idx_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_uop_stq_idx_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_uop_pdst_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_uop_prs1_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_uop_prs2_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_uop_prs3_0; // @[fdiv.scala:84:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_prs1_busy_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_prs2_busy_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_prs3_busy_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_ppred_busy_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_exception_0; // @[fdiv.scala:84:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_bypassable_0; // @[fdiv.scala:84:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_mem_signed_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_is_fence_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_is_fencei_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_is_amo_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_uses_ldq_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_uses_stq_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_is_unique_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_flush_on_commit_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_ldst_val_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_frs3_en_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_fp_val_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_fp_single_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_bp_debug_if_0; // @[fdiv.scala:84:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[fdiv.scala:84:7] wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[fdiv.scala:84:7] wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_load_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_sta_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_std_0; // @[fdiv.scala:84:7] wire [6:0] io_resp_bits_fflags_bits_uop_uopc_0; // @[fdiv.scala:84:7] wire [31:0] io_resp_bits_fflags_bits_uop_inst_0; // @[fdiv.scala:84:7] wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_is_rvc_0; // @[fdiv.scala:84:7] wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_fflags_bits_uop_iq_type_0; // @[fdiv.scala:84:7] wire [9:0] io_resp_bits_fflags_bits_uop_fu_code_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_fflags_bits_uop_iw_state_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_is_br_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_is_jalr_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_is_jal_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_is_sfb_0; // @[fdiv.scala:84:7] wire [7:0] io_resp_bits_fflags_bits_uop_br_mask_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_fflags_bits_uop_br_tag_0; // @[fdiv.scala:84:7] wire [3:0] io_resp_bits_fflags_bits_uop_ftq_idx_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_edge_inst_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_taken_0; // @[fdiv.scala:84:7] wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed_0; // @[fdiv.scala:84:7] wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr_0; // @[fdiv.scala:84:7] wire [4:0] io_resp_bits_fflags_bits_uop_rob_idx_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_fflags_bits_uop_ldq_idx_0; // @[fdiv.scala:84:7] wire [2:0] io_resp_bits_fflags_bits_uop_stq_idx_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_fflags_bits_uop_pdst_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs1_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs2_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_fflags_bits_uop_prs3_0; // @[fdiv.scala:84:7] wire [3:0] io_resp_bits_fflags_bits_uop_ppred_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_prs1_busy_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_prs2_busy_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_prs3_busy_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_ppred_busy_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_fflags_bits_uop_stale_pdst_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_exception_0; // @[fdiv.scala:84:7] wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_bypassable_0; // @[fdiv.scala:84:7] wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_fflags_bits_uop_mem_size_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_mem_signed_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_is_fence_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_is_fencei_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_is_amo_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_uses_ldq_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_uses_stq_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_is_unique_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_flush_on_commit_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_ldst_is_rs1_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_fflags_bits_uop_ldst_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs1_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs2_0; // @[fdiv.scala:84:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs3_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_ldst_val_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_frs3_en_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_fp_val_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_fp_single_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_xcpt_pf_if_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_xcpt_ae_if_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_xcpt_ma_if_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_bp_debug_if_0; // @[fdiv.scala:84:7] wire io_resp_bits_fflags_bits_uop_bp_xcpt_if_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc_0; // @[fdiv.scala:84:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc_0; // @[fdiv.scala:84:7] wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[fdiv.scala:84:7] wire [64:0] io_resp_bits_data_0; // @[fdiv.scala:84:7] reg r_buffer_val; // @[fdiv.scala:97:29] reg [6:0] r_buffer_req_uop_uopc; // @[fdiv.scala:98:25] reg [31:0] r_buffer_req_uop_inst; // @[fdiv.scala:98:25] reg [31:0] r_buffer_req_uop_debug_inst; // @[fdiv.scala:98:25] reg r_buffer_req_uop_is_rvc; // @[fdiv.scala:98:25] reg [39:0] r_buffer_req_uop_debug_pc; // @[fdiv.scala:98:25] reg [2:0] r_buffer_req_uop_iq_type; // @[fdiv.scala:98:25] reg [9:0] r_buffer_req_uop_fu_code; // @[fdiv.scala:98:25] reg [3:0] r_buffer_req_uop_ctrl_br_type; // @[fdiv.scala:98:25] reg [1:0] r_buffer_req_uop_ctrl_op1_sel; // @[fdiv.scala:98:25] reg [2:0] r_buffer_req_uop_ctrl_op2_sel; // @[fdiv.scala:98:25] reg [2:0] r_buffer_req_uop_ctrl_imm_sel; // @[fdiv.scala:98:25] reg [4:0] r_buffer_req_uop_ctrl_op_fcn; // @[fdiv.scala:98:25] reg r_buffer_req_uop_ctrl_fcn_dw; // @[fdiv.scala:98:25] reg [2:0] r_buffer_req_uop_ctrl_csr_cmd; // @[fdiv.scala:98:25] reg r_buffer_req_uop_ctrl_is_load; // @[fdiv.scala:98:25] reg r_buffer_req_uop_ctrl_is_sta; // @[fdiv.scala:98:25] reg r_buffer_req_uop_ctrl_is_std; // @[fdiv.scala:98:25] reg [1:0] r_buffer_req_uop_iw_state; // @[fdiv.scala:98:25] reg r_buffer_req_uop_iw_p1_poisoned; // @[fdiv.scala:98:25] reg r_buffer_req_uop_iw_p2_poisoned; // @[fdiv.scala:98:25] reg r_buffer_req_uop_is_br; // @[fdiv.scala:98:25] reg r_buffer_req_uop_is_jalr; // @[fdiv.scala:98:25] reg r_buffer_req_uop_is_jal; // @[fdiv.scala:98:25] reg r_buffer_req_uop_is_sfb; // @[fdiv.scala:98:25] reg [7:0] r_buffer_req_uop_br_mask; // @[fdiv.scala:98:25] reg [2:0] r_buffer_req_uop_br_tag; // @[fdiv.scala:98:25] reg [3:0] r_buffer_req_uop_ftq_idx; // @[fdiv.scala:98:25] reg r_buffer_req_uop_edge_inst; // @[fdiv.scala:98:25] reg [5:0] r_buffer_req_uop_pc_lob; // @[fdiv.scala:98:25] reg r_buffer_req_uop_taken; // @[fdiv.scala:98:25] reg [19:0] r_buffer_req_uop_imm_packed; // @[fdiv.scala:98:25] reg [11:0] r_buffer_req_uop_csr_addr; // @[fdiv.scala:98:25] reg [4:0] r_buffer_req_uop_rob_idx; // @[fdiv.scala:98:25] reg [2:0] r_buffer_req_uop_ldq_idx; // @[fdiv.scala:98:25] reg [2:0] r_buffer_req_uop_stq_idx; // @[fdiv.scala:98:25] reg [1:0] r_buffer_req_uop_rxq_idx; // @[fdiv.scala:98:25] reg [5:0] r_buffer_req_uop_pdst; // @[fdiv.scala:98:25] reg [5:0] r_buffer_req_uop_prs1; // @[fdiv.scala:98:25] reg [5:0] r_buffer_req_uop_prs2; // @[fdiv.scala:98:25] reg [5:0] r_buffer_req_uop_prs3; // @[fdiv.scala:98:25] reg [3:0] r_buffer_req_uop_ppred; // @[fdiv.scala:98:25] reg r_buffer_req_uop_prs1_busy; // @[fdiv.scala:98:25] reg r_buffer_req_uop_prs2_busy; // @[fdiv.scala:98:25] reg r_buffer_req_uop_prs3_busy; // @[fdiv.scala:98:25] reg r_buffer_req_uop_ppred_busy; // @[fdiv.scala:98:25] reg [5:0] r_buffer_req_uop_stale_pdst; // @[fdiv.scala:98:25] reg r_buffer_req_uop_exception; // @[fdiv.scala:98:25] reg [63:0] r_buffer_req_uop_exc_cause; // @[fdiv.scala:98:25] reg r_buffer_req_uop_bypassable; // @[fdiv.scala:98:25] reg [4:0] r_buffer_req_uop_mem_cmd; // @[fdiv.scala:98:25] reg [1:0] r_buffer_req_uop_mem_size; // @[fdiv.scala:98:25] reg r_buffer_req_uop_mem_signed; // @[fdiv.scala:98:25] reg r_buffer_req_uop_is_fence; // @[fdiv.scala:98:25] reg r_buffer_req_uop_is_fencei; // @[fdiv.scala:98:25] reg r_buffer_req_uop_is_amo; // @[fdiv.scala:98:25] reg r_buffer_req_uop_uses_ldq; // @[fdiv.scala:98:25] reg r_buffer_req_uop_uses_stq; // @[fdiv.scala:98:25] reg r_buffer_req_uop_is_sys_pc2epc; // @[fdiv.scala:98:25] reg r_buffer_req_uop_is_unique; // @[fdiv.scala:98:25] reg r_buffer_req_uop_flush_on_commit; // @[fdiv.scala:98:25] reg r_buffer_req_uop_ldst_is_rs1; // @[fdiv.scala:98:25] reg [5:0] r_buffer_req_uop_ldst; // @[fdiv.scala:98:25] reg [5:0] r_buffer_req_uop_lrs1; // @[fdiv.scala:98:25] reg [5:0] r_buffer_req_uop_lrs2; // @[fdiv.scala:98:25] reg [5:0] r_buffer_req_uop_lrs3; // @[fdiv.scala:98:25] reg r_buffer_req_uop_ldst_val; // @[fdiv.scala:98:25] reg [1:0] r_buffer_req_uop_dst_rtype; // @[fdiv.scala:98:25] reg [1:0] r_buffer_req_uop_lrs1_rtype; // @[fdiv.scala:98:25] reg [1:0] r_buffer_req_uop_lrs2_rtype; // @[fdiv.scala:98:25] reg r_buffer_req_uop_frs3_en; // @[fdiv.scala:98:25] reg r_buffer_req_uop_fp_val; // @[fdiv.scala:98:25] reg r_buffer_req_uop_fp_single; // @[fdiv.scala:98:25] reg r_buffer_req_uop_xcpt_pf_if; // @[fdiv.scala:98:25] reg r_buffer_req_uop_xcpt_ae_if; // @[fdiv.scala:98:25] reg r_buffer_req_uop_xcpt_ma_if; // @[fdiv.scala:98:25] reg r_buffer_req_uop_bp_debug_if; // @[fdiv.scala:98:25] reg r_buffer_req_uop_bp_xcpt_if; // @[fdiv.scala:98:25] reg [1:0] r_buffer_req_uop_debug_fsrc; // @[fdiv.scala:98:25] reg [1:0] r_buffer_req_uop_debug_tsrc; // @[fdiv.scala:98:25] reg [64:0] r_buffer_req_rs1_data; // @[fdiv.scala:98:25] reg [64:0] r_buffer_req_rs2_data; // @[fdiv.scala:98:25] reg r_buffer_req_kill; // @[fdiv.scala:98:25] reg r_buffer_fin_ldst; // @[fdiv.scala:99:25] reg r_buffer_fin_wen; // @[fdiv.scala:99:25] reg r_buffer_fin_ren1; // @[fdiv.scala:99:25] reg r_buffer_fin_ren2; // @[fdiv.scala:99:25] reg r_buffer_fin_ren3; // @[fdiv.scala:99:25] reg r_buffer_fin_swap12; // @[fdiv.scala:99:25] reg r_buffer_fin_swap23; // @[fdiv.scala:99:25] reg [1:0] r_buffer_fin_typeTagIn; // @[fdiv.scala:99:25] reg [1:0] r_buffer_fin_typeTagOut; // @[fdiv.scala:99:25] reg r_buffer_fin_fromint; // @[fdiv.scala:99:25] reg r_buffer_fin_toint; // @[fdiv.scala:99:25] reg r_buffer_fin_fastpipe; // @[fdiv.scala:99:25] reg r_buffer_fin_fma; // @[fdiv.scala:99:25] reg r_buffer_fin_div; // @[fdiv.scala:99:25] reg r_buffer_fin_sqrt; // @[fdiv.scala:99:25] reg r_buffer_fin_wflags; // @[fdiv.scala:99:25] reg [2:0] r_buffer_fin_rm; // @[fdiv.scala:99:25] reg [64:0] r_buffer_fin_in1; // @[fdiv.scala:99:25] reg [64:0] r_buffer_fin_in2; // @[fdiv.scala:99:25] wire [7:0] _GEN = io_brupdate_b1_mispredict_mask_0 & r_buffer_req_uop_br_mask; // @[util.scala:118:51] wire [7:0] _r_buffer_val_T; // @[util.scala:118:51] assign _r_buffer_val_T = _GEN; // @[util.scala:118:51] wire [7:0] _r_divsqrt_killed_T_4; // @[util.scala:118:51] assign _r_divsqrt_killed_T_4 = _GEN; // @[util.scala:118:51] wire _r_buffer_val_T_1 = |_r_buffer_val_T; // @[util.scala:118:{51,59}] wire _r_buffer_val_T_2 = ~_r_buffer_val_T_1; // @[util.scala:118:59] wire _r_buffer_val_T_3 = ~io_req_bits_kill_0; // @[fdiv.scala:84:7, :105:71] wire _r_buffer_val_T_4 = _r_buffer_val_T_2 & _r_buffer_val_T_3; // @[fdiv.scala:105:{19,68,71}] wire _r_buffer_val_T_5 = _r_buffer_val_T_4 & r_buffer_val; // @[fdiv.scala:97:29, :105:{68,89}] wire [7:0] _r_buffer_req_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_buffer_req_uop_br_mask_T_1 = r_buffer_req_uop_br_mask & _r_buffer_req_uop_br_mask_T; // @[util.scala:85:{25,27}] assign _io_req_ready_T = ~r_buffer_val; // @[fdiv.scala:97:29, :109:19] assign io_req_ready_0 = _io_req_ready_T; // @[fdiv.scala:84:7, :109:19] wire _in1_upconvert_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _r_buffer_fin_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _in1_upconvert_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire _r_buffer_fin_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _in1_upconvert_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _r_buffer_fin_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] in1_upconvert_prev_unswizzled_hi = {_in1_upconvert_prev_unswizzled_T, _in1_upconvert_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] in1_upconvert_floats_0 = {in1_upconvert_prev_unswizzled_hi, _in1_upconvert_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire [4:0] _in1_upconvert_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _r_buffer_fin_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire in1_upconvert_prev_isbox = &_in1_upconvert_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire in1_upconvert_oks_0 = in1_upconvert_prev_isbox; // @[FPU.scala:332:84, :362:32] wire in1_upconvert_sign = io_req_bits_rs1_data_0[64]; // @[FPU.scala:274:17] wire [51:0] in1_upconvert_fractIn = io_req_bits_rs1_data_0[51:0]; // @[FPU.scala:275:20] wire [11:0] in1_upconvert_expIn = io_req_bits_rs1_data_0[63:52]; // @[FPU.scala:276:18] wire [75:0] _in1_upconvert_fractOut_T = {in1_upconvert_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] in1_upconvert_fractOut = _in1_upconvert_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] in1_upconvert_expOut_expCode = in1_upconvert_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _in1_upconvert_expOut_commonCase_T = {1'h0, in1_upconvert_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _in1_upconvert_expOut_commonCase_T_1 = _in1_upconvert_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _in1_upconvert_expOut_commonCase_T_2 = {1'h0, _in1_upconvert_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] in1_upconvert_expOut_commonCase = _in1_upconvert_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _in1_upconvert_expOut_T = in1_upconvert_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _in1_upconvert_expOut_T_1 = in1_upconvert_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _in1_upconvert_expOut_T_2 = _in1_upconvert_expOut_T | _in1_upconvert_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _in1_upconvert_expOut_T_3 = in1_upconvert_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _in1_upconvert_expOut_T_4 = {in1_upconvert_expOut_expCode, _in1_upconvert_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _in1_upconvert_expOut_T_5 = in1_upconvert_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] in1_upconvert_expOut = _in1_upconvert_expOut_T_2 ? _in1_upconvert_expOut_T_4 : _in1_upconvert_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] in1_upconvert_hi = {in1_upconvert_sign, in1_upconvert_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] in1_upconvert_floats_1 = {in1_upconvert_hi, in1_upconvert_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _in1_upconvert_T = in1_upconvert_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _in1_upconvert_T_1 = in1_upconvert_floats_0 | _in1_upconvert_T; // @[FPU.scala:356:31, :372:{26,31}] wire _in2_upconvert_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _r_buffer_fin_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _in2_upconvert_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire _r_buffer_fin_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _in2_upconvert_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _r_buffer_fin_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] in2_upconvert_prev_unswizzled_hi = {_in2_upconvert_prev_unswizzled_T, _in2_upconvert_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] in2_upconvert_floats_0 = {in2_upconvert_prev_unswizzled_hi, _in2_upconvert_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire [4:0] _in2_upconvert_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _r_buffer_fin_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire in2_upconvert_prev_isbox = &_in2_upconvert_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire in2_upconvert_oks_0 = in2_upconvert_prev_isbox; // @[FPU.scala:332:84, :362:32] wire in2_upconvert_sign = io_req_bits_rs2_data_0[64]; // @[FPU.scala:274:17] wire [51:0] in2_upconvert_fractIn = io_req_bits_rs2_data_0[51:0]; // @[FPU.scala:275:20] wire [11:0] in2_upconvert_expIn = io_req_bits_rs2_data_0[63:52]; // @[FPU.scala:276:18] wire [75:0] _in2_upconvert_fractOut_T = {in2_upconvert_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] in2_upconvert_fractOut = _in2_upconvert_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] in2_upconvert_expOut_expCode = in2_upconvert_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _in2_upconvert_expOut_commonCase_T = {1'h0, in2_upconvert_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _in2_upconvert_expOut_commonCase_T_1 = _in2_upconvert_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _in2_upconvert_expOut_commonCase_T_2 = {1'h0, _in2_upconvert_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] in2_upconvert_expOut_commonCase = _in2_upconvert_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _in2_upconvert_expOut_T = in2_upconvert_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _in2_upconvert_expOut_T_1 = in2_upconvert_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _in2_upconvert_expOut_T_2 = _in2_upconvert_expOut_T | _in2_upconvert_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _in2_upconvert_expOut_T_3 = in2_upconvert_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _in2_upconvert_expOut_T_4 = {in2_upconvert_expOut_expCode, _in2_upconvert_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _in2_upconvert_expOut_T_5 = in2_upconvert_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] in2_upconvert_expOut = _in2_upconvert_expOut_T_2 ? _in2_upconvert_expOut_T_4 : _in2_upconvert_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] in2_upconvert_hi = {in2_upconvert_sign, in2_upconvert_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] in2_upconvert_floats_1 = {in2_upconvert_hi, in2_upconvert_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _in2_upconvert_T = in2_upconvert_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _in2_upconvert_T_1 = in2_upconvert_floats_0 | _in2_upconvert_T; // @[FPU.scala:356:31, :372:{26,31}] wire [7:0] _r_buffer_req_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_buffer_req_uop_br_mask_T_3 = io_req_bits_uop_br_mask_0 & _r_buffer_req_uop_br_mask_T_2; // @[util.scala:85:{25,27}] wire [2:0] _r_buffer_fin_rm_T = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire [2:0] _r_buffer_fin_rm_T_2 = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire _r_buffer_fin_rm_T_1 = &_r_buffer_fin_rm_T; // @[util.scala:289:58] wire [2:0] _r_buffer_fin_rm_T_3 = _r_buffer_fin_rm_T_1 ? io_fcsr_rm_0 : _r_buffer_fin_rm_T_2; // @[util.scala:289:58] wire [1:0] r_buffer_fin_in1_prev_unswizzled_hi = {_r_buffer_fin_in1_prev_unswizzled_T, _r_buffer_fin_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] r_buffer_fin_in1_prev_unswizzled = {r_buffer_fin_in1_prev_unswizzled_hi, _r_buffer_fin_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire r_buffer_fin_in1_prev_prev_sign = r_buffer_fin_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] r_buffer_fin_in1_prev_prev_fractIn = r_buffer_fin_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] r_buffer_fin_in1_prev_prev_expIn = r_buffer_fin_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _r_buffer_fin_in1_prev_prev_fractOut_T = {r_buffer_fin_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] r_buffer_fin_in1_prev_prev_fractOut = _r_buffer_fin_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] r_buffer_fin_in1_prev_prev_expOut_expCode = r_buffer_fin_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _r_buffer_fin_in1_prev_prev_expOut_commonCase_T = {4'h0, r_buffer_fin_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_1 = _r_buffer_fin_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] r_buffer_fin_in1_prev_prev_expOut_commonCase = _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _r_buffer_fin_in1_prev_prev_expOut_T_5 = r_buffer_fin_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _r_buffer_fin_in1_prev_prev_expOut_T = r_buffer_fin_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _r_buffer_fin_in1_prev_prev_expOut_T_1 = r_buffer_fin_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _r_buffer_fin_in1_prev_prev_expOut_T_2 = _r_buffer_fin_in1_prev_prev_expOut_T | _r_buffer_fin_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _r_buffer_fin_in1_prev_prev_expOut_T_3 = r_buffer_fin_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _r_buffer_fin_in1_prev_prev_expOut_T_4 = {r_buffer_fin_in1_prev_prev_expOut_expCode, _r_buffer_fin_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] r_buffer_fin_in1_prev_prev_expOut = _r_buffer_fin_in1_prev_prev_expOut_T_2 ? _r_buffer_fin_in1_prev_prev_expOut_T_4 : _r_buffer_fin_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] r_buffer_fin_in1_prev_prev_hi = {r_buffer_fin_in1_prev_prev_sign, r_buffer_fin_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] r_buffer_fin_in1_floats_0 = {r_buffer_fin_in1_prev_prev_hi, r_buffer_fin_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire r_buffer_fin_in1_prev_isbox = &_r_buffer_fin_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire r_buffer_fin_in1_oks_0 = r_buffer_fin_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] r_buffer_fin_in2_prev_unswizzled_hi = {_r_buffer_fin_in2_prev_unswizzled_T, _r_buffer_fin_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] r_buffer_fin_in2_prev_unswizzled = {r_buffer_fin_in2_prev_unswizzled_hi, _r_buffer_fin_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire r_buffer_fin_in2_prev_prev_sign = r_buffer_fin_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] r_buffer_fin_in2_prev_prev_fractIn = r_buffer_fin_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] r_buffer_fin_in2_prev_prev_expIn = r_buffer_fin_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _r_buffer_fin_in2_prev_prev_fractOut_T = {r_buffer_fin_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] r_buffer_fin_in2_prev_prev_fractOut = _r_buffer_fin_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] r_buffer_fin_in2_prev_prev_expOut_expCode = r_buffer_fin_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _r_buffer_fin_in2_prev_prev_expOut_commonCase_T = {4'h0, r_buffer_fin_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_1 = _r_buffer_fin_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] r_buffer_fin_in2_prev_prev_expOut_commonCase = _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _r_buffer_fin_in2_prev_prev_expOut_T_5 = r_buffer_fin_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _r_buffer_fin_in2_prev_prev_expOut_T = r_buffer_fin_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _r_buffer_fin_in2_prev_prev_expOut_T_1 = r_buffer_fin_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _r_buffer_fin_in2_prev_prev_expOut_T_2 = _r_buffer_fin_in2_prev_prev_expOut_T | _r_buffer_fin_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _r_buffer_fin_in2_prev_prev_expOut_T_3 = r_buffer_fin_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _r_buffer_fin_in2_prev_prev_expOut_T_4 = {r_buffer_fin_in2_prev_prev_expOut_expCode, _r_buffer_fin_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] r_buffer_fin_in2_prev_prev_expOut = _r_buffer_fin_in2_prev_prev_expOut_T_2 ? _r_buffer_fin_in2_prev_prev_expOut_T_4 : _r_buffer_fin_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] r_buffer_fin_in2_prev_prev_hi = {r_buffer_fin_in2_prev_prev_sign, r_buffer_fin_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] r_buffer_fin_in2_floats_0 = {r_buffer_fin_in2_prev_prev_hi, r_buffer_fin_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire r_buffer_fin_in2_prev_isbox = &_r_buffer_fin_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire r_buffer_fin_in2_oks_0 = r_buffer_fin_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] reg r_divsqrt_val; // @[fdiv.scala:145:30] reg r_divsqrt_killed; // @[fdiv.scala:146:29] reg r_divsqrt_fin_ldst; // @[fdiv.scala:147:26] reg r_divsqrt_fin_wen; // @[fdiv.scala:147:26] reg r_divsqrt_fin_ren1; // @[fdiv.scala:147:26] reg r_divsqrt_fin_ren2; // @[fdiv.scala:147:26] reg r_divsqrt_fin_ren3; // @[fdiv.scala:147:26] reg r_divsqrt_fin_swap12; // @[fdiv.scala:147:26] reg r_divsqrt_fin_swap23; // @[fdiv.scala:147:26] reg [1:0] r_divsqrt_fin_typeTagIn; // @[fdiv.scala:147:26] reg [1:0] r_divsqrt_fin_typeTagOut; // @[fdiv.scala:147:26] reg r_divsqrt_fin_fromint; // @[fdiv.scala:147:26] reg r_divsqrt_fin_toint; // @[fdiv.scala:147:26] reg r_divsqrt_fin_fastpipe; // @[fdiv.scala:147:26] reg r_divsqrt_fin_fma; // @[fdiv.scala:147:26] reg r_divsqrt_fin_div; // @[fdiv.scala:147:26] reg r_divsqrt_fin_sqrt; // @[fdiv.scala:147:26] reg r_divsqrt_fin_wflags; // @[fdiv.scala:147:26] reg r_divsqrt_fin_vec; // @[fdiv.scala:147:26] reg [2:0] r_divsqrt_fin_rm; // @[fdiv.scala:147:26] reg [1:0] r_divsqrt_fin_fmaCmd; // @[fdiv.scala:147:26] reg [1:0] r_divsqrt_fin_typ; // @[fdiv.scala:147:26] reg [1:0] r_divsqrt_fin_fmt; // @[fdiv.scala:147:26] reg [64:0] r_divsqrt_fin_in1; // @[fdiv.scala:147:26] reg [64:0] r_divsqrt_fin_in2; // @[fdiv.scala:147:26] reg [64:0] r_divsqrt_fin_in3; // @[fdiv.scala:147:26] reg [6:0] r_divsqrt_uop_uopc; // @[fdiv.scala:148:26] reg [31:0] r_divsqrt_uop_inst; // @[fdiv.scala:148:26] reg [31:0] r_divsqrt_uop_debug_inst; // @[fdiv.scala:148:26] reg r_divsqrt_uop_is_rvc; // @[fdiv.scala:148:26] reg [39:0] r_divsqrt_uop_debug_pc; // @[fdiv.scala:148:26] reg [2:0] r_divsqrt_uop_iq_type; // @[fdiv.scala:148:26] reg [9:0] r_divsqrt_uop_fu_code; // @[fdiv.scala:148:26] reg [3:0] r_divsqrt_uop_ctrl_br_type; // @[fdiv.scala:148:26] reg [1:0] r_divsqrt_uop_ctrl_op1_sel; // @[fdiv.scala:148:26] reg [2:0] r_divsqrt_uop_ctrl_op2_sel; // @[fdiv.scala:148:26] reg [2:0] r_divsqrt_uop_ctrl_imm_sel; // @[fdiv.scala:148:26] reg [4:0] r_divsqrt_uop_ctrl_op_fcn; // @[fdiv.scala:148:26] reg r_divsqrt_uop_ctrl_fcn_dw; // @[fdiv.scala:148:26] reg [2:0] r_divsqrt_uop_ctrl_csr_cmd; // @[fdiv.scala:148:26] reg r_divsqrt_uop_ctrl_is_load; // @[fdiv.scala:148:26] reg r_divsqrt_uop_ctrl_is_sta; // @[fdiv.scala:148:26] reg r_divsqrt_uop_ctrl_is_std; // @[fdiv.scala:148:26] reg [1:0] r_divsqrt_uop_iw_state; // @[fdiv.scala:148:26] reg r_divsqrt_uop_iw_p1_poisoned; // @[fdiv.scala:148:26] reg r_divsqrt_uop_iw_p2_poisoned; // @[fdiv.scala:148:26] reg r_divsqrt_uop_is_br; // @[fdiv.scala:148:26] reg r_divsqrt_uop_is_jalr; // @[fdiv.scala:148:26] reg r_divsqrt_uop_is_jal; // @[fdiv.scala:148:26] reg r_divsqrt_uop_is_sfb; // @[fdiv.scala:148:26] reg [7:0] r_divsqrt_uop_br_mask; // @[fdiv.scala:148:26] reg [2:0] r_divsqrt_uop_br_tag; // @[fdiv.scala:148:26] reg [3:0] r_divsqrt_uop_ftq_idx; // @[fdiv.scala:148:26] reg r_divsqrt_uop_edge_inst; // @[fdiv.scala:148:26] reg [5:0] r_divsqrt_uop_pc_lob; // @[fdiv.scala:148:26] reg r_divsqrt_uop_taken; // @[fdiv.scala:148:26] reg [19:0] r_divsqrt_uop_imm_packed; // @[fdiv.scala:148:26] reg [11:0] r_divsqrt_uop_csr_addr; // @[fdiv.scala:148:26] reg [4:0] r_divsqrt_uop_rob_idx; // @[fdiv.scala:148:26] reg [2:0] r_divsqrt_uop_ldq_idx; // @[fdiv.scala:148:26] reg [2:0] r_divsqrt_uop_stq_idx; // @[fdiv.scala:148:26] reg [1:0] r_divsqrt_uop_rxq_idx; // @[fdiv.scala:148:26] reg [5:0] r_divsqrt_uop_pdst; // @[fdiv.scala:148:26] reg [5:0] r_divsqrt_uop_prs1; // @[fdiv.scala:148:26] reg [5:0] r_divsqrt_uop_prs2; // @[fdiv.scala:148:26] reg [5:0] r_divsqrt_uop_prs3; // @[fdiv.scala:148:26] reg [3:0] r_divsqrt_uop_ppred; // @[fdiv.scala:148:26] reg r_divsqrt_uop_prs1_busy; // @[fdiv.scala:148:26] reg r_divsqrt_uop_prs2_busy; // @[fdiv.scala:148:26] reg r_divsqrt_uop_prs3_busy; // @[fdiv.scala:148:26] reg r_divsqrt_uop_ppred_busy; // @[fdiv.scala:148:26] reg [5:0] r_divsqrt_uop_stale_pdst; // @[fdiv.scala:148:26] reg r_divsqrt_uop_exception; // @[fdiv.scala:148:26] reg [63:0] r_divsqrt_uop_exc_cause; // @[fdiv.scala:148:26] reg r_divsqrt_uop_bypassable; // @[fdiv.scala:148:26] reg [4:0] r_divsqrt_uop_mem_cmd; // @[fdiv.scala:148:26] reg [1:0] r_divsqrt_uop_mem_size; // @[fdiv.scala:148:26] reg r_divsqrt_uop_mem_signed; // @[fdiv.scala:148:26] reg r_divsqrt_uop_is_fence; // @[fdiv.scala:148:26] reg r_divsqrt_uop_is_fencei; // @[fdiv.scala:148:26] reg r_divsqrt_uop_is_amo; // @[fdiv.scala:148:26] reg r_divsqrt_uop_uses_ldq; // @[fdiv.scala:148:26] reg r_divsqrt_uop_uses_stq; // @[fdiv.scala:148:26] reg r_divsqrt_uop_is_sys_pc2epc; // @[fdiv.scala:148:26] reg r_divsqrt_uop_is_unique; // @[fdiv.scala:148:26] reg r_divsqrt_uop_flush_on_commit; // @[fdiv.scala:148:26] reg r_divsqrt_uop_ldst_is_rs1; // @[fdiv.scala:148:26] reg [5:0] r_divsqrt_uop_ldst; // @[fdiv.scala:148:26] reg [5:0] r_divsqrt_uop_lrs1; // @[fdiv.scala:148:26] reg [5:0] r_divsqrt_uop_lrs2; // @[fdiv.scala:148:26] reg [5:0] r_divsqrt_uop_lrs3; // @[fdiv.scala:148:26] reg r_divsqrt_uop_ldst_val; // @[fdiv.scala:148:26] reg [1:0] r_divsqrt_uop_dst_rtype; // @[fdiv.scala:148:26] reg [1:0] r_divsqrt_uop_lrs1_rtype; // @[fdiv.scala:148:26] reg [1:0] r_divsqrt_uop_lrs2_rtype; // @[fdiv.scala:148:26] reg r_divsqrt_uop_frs3_en; // @[fdiv.scala:148:26] reg r_divsqrt_uop_fp_val; // @[fdiv.scala:148:26] reg r_divsqrt_uop_fp_single; // @[fdiv.scala:148:26] reg r_divsqrt_uop_xcpt_pf_if; // @[fdiv.scala:148:26] reg r_divsqrt_uop_xcpt_ae_if; // @[fdiv.scala:148:26] reg r_divsqrt_uop_xcpt_ma_if; // @[fdiv.scala:148:26] reg r_divsqrt_uop_bp_debug_if; // @[fdiv.scala:148:26] reg r_divsqrt_uop_bp_xcpt_if; // @[fdiv.scala:148:26] reg [1:0] r_divsqrt_uop_debug_fsrc; // @[fdiv.scala:148:26] reg [1:0] r_divsqrt_uop_debug_tsrc; // @[fdiv.scala:148:26] wire _output_buffer_available_T; // @[fdiv.scala:189:30] wire output_buffer_available; // @[fdiv.scala:151:37] wire _may_fire_input_T = r_buffer_fin_div | r_buffer_fin_sqrt; // @[fdiv.scala:99:25, :155:23] wire _may_fire_input_T_1 = r_buffer_val & _may_fire_input_T; // @[fdiv.scala:97:29, :154:18, :155:23] wire _may_fire_input_T_2 = ~r_divsqrt_val; // @[fdiv.scala:145:30, :156:5] wire _may_fire_input_T_3 = _may_fire_input_T_1 & _may_fire_input_T_2; // @[fdiv.scala:154:18, :155:45, :156:5] wire may_fire_input = _may_fire_input_T_3 & output_buffer_available; // @[fdiv.scala:151:37, :155:45, :156:20] wire divsqrt_ready = r_buffer_fin_sqrt ? _divsqrt_io_inReady_sqrt : _divsqrt_io_inReady_div; // @[fdiv.scala:99:25, :143:23, :159:26] wire [64:0] _divsqrt_io_b_T = r_buffer_fin_sqrt ? r_buffer_fin_in1 : r_buffer_fin_in2; // @[fdiv.scala:99:25, :163:22] wire [7:0] _GEN_0 = io_brupdate_b1_mispredict_mask_0 & r_divsqrt_uop_br_mask; // @[util.scala:118:51] wire [7:0] _r_divsqrt_killed_T; // @[util.scala:118:51] assign _r_divsqrt_killed_T = _GEN_0; // @[util.scala:118:51] wire [7:0] _r_out_val_T_1; // @[util.scala:118:51] assign _r_out_val_T_1 = _GEN_0; // @[util.scala:118:51] wire _r_divsqrt_killed_T_1 = |_r_divsqrt_killed_T; // @[util.scala:118:{51,59}] wire _r_divsqrt_killed_T_2 = r_divsqrt_killed | _r_divsqrt_killed_T_1; // @[util.scala:118:59] wire _r_divsqrt_killed_T_3 = _r_divsqrt_killed_T_2 | io_req_bits_kill_0; // @[fdiv.scala:84:7, :167:{40,88}] wire [7:0] _r_divsqrt_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_divsqrt_uop_br_mask_T_1 = r_divsqrt_uop_br_mask & _r_divsqrt_uop_br_mask_T; // @[util.scala:85:{25,27}] wire _r_divsqrt_killed_T_5 = |_r_divsqrt_killed_T_4; // @[util.scala:118:{51,59}] wire _r_divsqrt_killed_T_6 = _r_divsqrt_killed_T_5 | io_req_bits_kill_0; // @[util.scala:118:59] wire [7:0] _r_divsqrt_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_divsqrt_uop_br_mask_T_3 = r_buffer_req_uop_br_mask & _r_divsqrt_uop_br_mask_T_2; // @[util.scala:85:{25,27}] reg r_out_val; // @[fdiv.scala:184:26] reg [6:0] r_out_uop_uopc; // @[fdiv.scala:185:22] assign io_resp_bits_uop_uopc_0 = r_out_uop_uopc; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_uopc_0 = r_out_uop_uopc; // @[fdiv.scala:84:7, :185:22] reg [31:0] r_out_uop_inst; // @[fdiv.scala:185:22] assign io_resp_bits_uop_inst_0 = r_out_uop_inst; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_inst_0 = r_out_uop_inst; // @[fdiv.scala:84:7, :185:22] reg [31:0] r_out_uop_debug_inst; // @[fdiv.scala:185:22] assign io_resp_bits_uop_debug_inst_0 = r_out_uop_debug_inst; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_debug_inst_0 = r_out_uop_debug_inst; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_is_rvc; // @[fdiv.scala:185:22] assign io_resp_bits_uop_is_rvc_0 = r_out_uop_is_rvc; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_is_rvc_0 = r_out_uop_is_rvc; // @[fdiv.scala:84:7, :185:22] reg [39:0] r_out_uop_debug_pc; // @[fdiv.scala:185:22] assign io_resp_bits_uop_debug_pc_0 = r_out_uop_debug_pc; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_debug_pc_0 = r_out_uop_debug_pc; // @[fdiv.scala:84:7, :185:22] reg [2:0] r_out_uop_iq_type; // @[fdiv.scala:185:22] assign io_resp_bits_uop_iq_type_0 = r_out_uop_iq_type; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_iq_type_0 = r_out_uop_iq_type; // @[fdiv.scala:84:7, :185:22] reg [9:0] r_out_uop_fu_code; // @[fdiv.scala:185:22] assign io_resp_bits_uop_fu_code_0 = r_out_uop_fu_code; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_fu_code_0 = r_out_uop_fu_code; // @[fdiv.scala:84:7, :185:22] reg [3:0] r_out_uop_ctrl_br_type; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ctrl_br_type_0 = r_out_uop_ctrl_br_type; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ctrl_br_type_0 = r_out_uop_ctrl_br_type; // @[fdiv.scala:84:7, :185:22] reg [1:0] r_out_uop_ctrl_op1_sel; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ctrl_op1_sel_0 = r_out_uop_ctrl_op1_sel; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0 = r_out_uop_ctrl_op1_sel; // @[fdiv.scala:84:7, :185:22] reg [2:0] r_out_uop_ctrl_op2_sel; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ctrl_op2_sel_0 = r_out_uop_ctrl_op2_sel; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0 = r_out_uop_ctrl_op2_sel; // @[fdiv.scala:84:7, :185:22] reg [2:0] r_out_uop_ctrl_imm_sel; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ctrl_imm_sel_0 = r_out_uop_ctrl_imm_sel; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0 = r_out_uop_ctrl_imm_sel; // @[fdiv.scala:84:7, :185:22] reg [4:0] r_out_uop_ctrl_op_fcn; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ctrl_op_fcn_0 = r_out_uop_ctrl_op_fcn; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0 = r_out_uop_ctrl_op_fcn; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_ctrl_fcn_dw; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_out_uop_ctrl_fcn_dw; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = r_out_uop_ctrl_fcn_dw; // @[fdiv.scala:84:7, :185:22] reg [2:0] r_out_uop_ctrl_csr_cmd; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_out_uop_ctrl_csr_cmd; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = r_out_uop_ctrl_csr_cmd; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_ctrl_is_load; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ctrl_is_load_0 = r_out_uop_ctrl_is_load; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ctrl_is_load_0 = r_out_uop_ctrl_is_load; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_ctrl_is_sta; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ctrl_is_sta_0 = r_out_uop_ctrl_is_sta; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ctrl_is_sta_0 = r_out_uop_ctrl_is_sta; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_ctrl_is_std; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ctrl_is_std_0 = r_out_uop_ctrl_is_std; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ctrl_is_std_0 = r_out_uop_ctrl_is_std; // @[fdiv.scala:84:7, :185:22] reg [1:0] r_out_uop_iw_state; // @[fdiv.scala:185:22] assign io_resp_bits_uop_iw_state_0 = r_out_uop_iw_state; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_iw_state_0 = r_out_uop_iw_state; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_iw_p1_poisoned; // @[fdiv.scala:185:22] assign io_resp_bits_uop_iw_p1_poisoned_0 = r_out_uop_iw_p1_poisoned; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0 = r_out_uop_iw_p1_poisoned; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_iw_p2_poisoned; // @[fdiv.scala:185:22] assign io_resp_bits_uop_iw_p2_poisoned_0 = r_out_uop_iw_p2_poisoned; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0 = r_out_uop_iw_p2_poisoned; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_is_br; // @[fdiv.scala:185:22] assign io_resp_bits_uop_is_br_0 = r_out_uop_is_br; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_is_br_0 = r_out_uop_is_br; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_is_jalr; // @[fdiv.scala:185:22] assign io_resp_bits_uop_is_jalr_0 = r_out_uop_is_jalr; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_is_jalr_0 = r_out_uop_is_jalr; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_is_jal; // @[fdiv.scala:185:22] assign io_resp_bits_uop_is_jal_0 = r_out_uop_is_jal; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_is_jal_0 = r_out_uop_is_jal; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_is_sfb; // @[fdiv.scala:185:22] assign io_resp_bits_uop_is_sfb_0 = r_out_uop_is_sfb; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_is_sfb_0 = r_out_uop_is_sfb; // @[fdiv.scala:84:7, :185:22] reg [7:0] r_out_uop_br_mask; // @[fdiv.scala:185:22] assign io_resp_bits_uop_br_mask_0 = r_out_uop_br_mask; // @[fdiv.scala:84:7, :185:22] reg [2:0] r_out_uop_br_tag; // @[fdiv.scala:185:22] assign io_resp_bits_uop_br_tag_0 = r_out_uop_br_tag; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_br_tag_0 = r_out_uop_br_tag; // @[fdiv.scala:84:7, :185:22] reg [3:0] r_out_uop_ftq_idx; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ftq_idx_0 = r_out_uop_ftq_idx; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ftq_idx_0 = r_out_uop_ftq_idx; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_edge_inst; // @[fdiv.scala:185:22] assign io_resp_bits_uop_edge_inst_0 = r_out_uop_edge_inst; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_edge_inst_0 = r_out_uop_edge_inst; // @[fdiv.scala:84:7, :185:22] reg [5:0] r_out_uop_pc_lob; // @[fdiv.scala:185:22] assign io_resp_bits_uop_pc_lob_0 = r_out_uop_pc_lob; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_pc_lob_0 = r_out_uop_pc_lob; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_taken; // @[fdiv.scala:185:22] assign io_resp_bits_uop_taken_0 = r_out_uop_taken; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_taken_0 = r_out_uop_taken; // @[fdiv.scala:84:7, :185:22] reg [19:0] r_out_uop_imm_packed; // @[fdiv.scala:185:22] assign io_resp_bits_uop_imm_packed_0 = r_out_uop_imm_packed; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_imm_packed_0 = r_out_uop_imm_packed; // @[fdiv.scala:84:7, :185:22] reg [11:0] r_out_uop_csr_addr; // @[fdiv.scala:185:22] assign io_resp_bits_uop_csr_addr_0 = r_out_uop_csr_addr; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_csr_addr_0 = r_out_uop_csr_addr; // @[fdiv.scala:84:7, :185:22] reg [4:0] r_out_uop_rob_idx; // @[fdiv.scala:185:22] assign io_resp_bits_uop_rob_idx_0 = r_out_uop_rob_idx; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_rob_idx_0 = r_out_uop_rob_idx; // @[fdiv.scala:84:7, :185:22] reg [2:0] r_out_uop_ldq_idx; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ldq_idx_0 = r_out_uop_ldq_idx; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ldq_idx_0 = r_out_uop_ldq_idx; // @[fdiv.scala:84:7, :185:22] reg [2:0] r_out_uop_stq_idx; // @[fdiv.scala:185:22] assign io_resp_bits_uop_stq_idx_0 = r_out_uop_stq_idx; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_stq_idx_0 = r_out_uop_stq_idx; // @[fdiv.scala:84:7, :185:22] reg [1:0] r_out_uop_rxq_idx; // @[fdiv.scala:185:22] assign io_resp_bits_uop_rxq_idx_0 = r_out_uop_rxq_idx; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_rxq_idx_0 = r_out_uop_rxq_idx; // @[fdiv.scala:84:7, :185:22] reg [5:0] r_out_uop_pdst; // @[fdiv.scala:185:22] assign io_resp_bits_uop_pdst_0 = r_out_uop_pdst; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_pdst_0 = r_out_uop_pdst; // @[fdiv.scala:84:7, :185:22] reg [5:0] r_out_uop_prs1; // @[fdiv.scala:185:22] assign io_resp_bits_uop_prs1_0 = r_out_uop_prs1; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_prs1_0 = r_out_uop_prs1; // @[fdiv.scala:84:7, :185:22] reg [5:0] r_out_uop_prs2; // @[fdiv.scala:185:22] assign io_resp_bits_uop_prs2_0 = r_out_uop_prs2; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_prs2_0 = r_out_uop_prs2; // @[fdiv.scala:84:7, :185:22] reg [5:0] r_out_uop_prs3; // @[fdiv.scala:185:22] assign io_resp_bits_uop_prs3_0 = r_out_uop_prs3; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_prs3_0 = r_out_uop_prs3; // @[fdiv.scala:84:7, :185:22] reg [3:0] r_out_uop_ppred; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ppred_0 = r_out_uop_ppred; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ppred_0 = r_out_uop_ppred; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_prs1_busy; // @[fdiv.scala:185:22] assign io_resp_bits_uop_prs1_busy_0 = r_out_uop_prs1_busy; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_prs1_busy_0 = r_out_uop_prs1_busy; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_prs2_busy; // @[fdiv.scala:185:22] assign io_resp_bits_uop_prs2_busy_0 = r_out_uop_prs2_busy; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_prs2_busy_0 = r_out_uop_prs2_busy; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_prs3_busy; // @[fdiv.scala:185:22] assign io_resp_bits_uop_prs3_busy_0 = r_out_uop_prs3_busy; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_prs3_busy_0 = r_out_uop_prs3_busy; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_ppred_busy; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ppred_busy_0 = r_out_uop_ppred_busy; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ppred_busy_0 = r_out_uop_ppred_busy; // @[fdiv.scala:84:7, :185:22] reg [5:0] r_out_uop_stale_pdst; // @[fdiv.scala:185:22] assign io_resp_bits_uop_stale_pdst_0 = r_out_uop_stale_pdst; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_stale_pdst_0 = r_out_uop_stale_pdst; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_exception; // @[fdiv.scala:185:22] assign io_resp_bits_uop_exception_0 = r_out_uop_exception; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_exception_0 = r_out_uop_exception; // @[fdiv.scala:84:7, :185:22] reg [63:0] r_out_uop_exc_cause; // @[fdiv.scala:185:22] assign io_resp_bits_uop_exc_cause_0 = r_out_uop_exc_cause; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_exc_cause_0 = r_out_uop_exc_cause; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_bypassable; // @[fdiv.scala:185:22] assign io_resp_bits_uop_bypassable_0 = r_out_uop_bypassable; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_bypassable_0 = r_out_uop_bypassable; // @[fdiv.scala:84:7, :185:22] reg [4:0] r_out_uop_mem_cmd; // @[fdiv.scala:185:22] assign io_resp_bits_uop_mem_cmd_0 = r_out_uop_mem_cmd; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_mem_cmd_0 = r_out_uop_mem_cmd; // @[fdiv.scala:84:7, :185:22] reg [1:0] r_out_uop_mem_size; // @[fdiv.scala:185:22] assign io_resp_bits_uop_mem_size_0 = r_out_uop_mem_size; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_mem_size_0 = r_out_uop_mem_size; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_mem_signed; // @[fdiv.scala:185:22] assign io_resp_bits_uop_mem_signed_0 = r_out_uop_mem_signed; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_mem_signed_0 = r_out_uop_mem_signed; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_is_fence; // @[fdiv.scala:185:22] assign io_resp_bits_uop_is_fence_0 = r_out_uop_is_fence; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_is_fence_0 = r_out_uop_is_fence; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_is_fencei; // @[fdiv.scala:185:22] assign io_resp_bits_uop_is_fencei_0 = r_out_uop_is_fencei; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_is_fencei_0 = r_out_uop_is_fencei; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_is_amo; // @[fdiv.scala:185:22] assign io_resp_bits_uop_is_amo_0 = r_out_uop_is_amo; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_is_amo_0 = r_out_uop_is_amo; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_uses_ldq; // @[fdiv.scala:185:22] assign io_resp_bits_uop_uses_ldq_0 = r_out_uop_uses_ldq; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_uses_ldq_0 = r_out_uop_uses_ldq; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_uses_stq; // @[fdiv.scala:185:22] assign io_resp_bits_uop_uses_stq_0 = r_out_uop_uses_stq; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_uses_stq_0 = r_out_uop_uses_stq; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_is_sys_pc2epc; // @[fdiv.scala:185:22] assign io_resp_bits_uop_is_sys_pc2epc_0 = r_out_uop_is_sys_pc2epc; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0 = r_out_uop_is_sys_pc2epc; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_is_unique; // @[fdiv.scala:185:22] assign io_resp_bits_uop_is_unique_0 = r_out_uop_is_unique; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_is_unique_0 = r_out_uop_is_unique; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_flush_on_commit; // @[fdiv.scala:185:22] assign io_resp_bits_uop_flush_on_commit_0 = r_out_uop_flush_on_commit; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_flush_on_commit_0 = r_out_uop_flush_on_commit; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_ldst_is_rs1; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ldst_is_rs1_0 = r_out_uop_ldst_is_rs1; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ldst_is_rs1_0 = r_out_uop_ldst_is_rs1; // @[fdiv.scala:84:7, :185:22] reg [5:0] r_out_uop_ldst; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ldst_0 = r_out_uop_ldst; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ldst_0 = r_out_uop_ldst; // @[fdiv.scala:84:7, :185:22] reg [5:0] r_out_uop_lrs1; // @[fdiv.scala:185:22] assign io_resp_bits_uop_lrs1_0 = r_out_uop_lrs1; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_lrs1_0 = r_out_uop_lrs1; // @[fdiv.scala:84:7, :185:22] reg [5:0] r_out_uop_lrs2; // @[fdiv.scala:185:22] assign io_resp_bits_uop_lrs2_0 = r_out_uop_lrs2; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_lrs2_0 = r_out_uop_lrs2; // @[fdiv.scala:84:7, :185:22] reg [5:0] r_out_uop_lrs3; // @[fdiv.scala:185:22] assign io_resp_bits_uop_lrs3_0 = r_out_uop_lrs3; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_lrs3_0 = r_out_uop_lrs3; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_ldst_val; // @[fdiv.scala:185:22] assign io_resp_bits_uop_ldst_val_0 = r_out_uop_ldst_val; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_ldst_val_0 = r_out_uop_ldst_val; // @[fdiv.scala:84:7, :185:22] reg [1:0] r_out_uop_dst_rtype; // @[fdiv.scala:185:22] assign io_resp_bits_uop_dst_rtype_0 = r_out_uop_dst_rtype; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_dst_rtype_0 = r_out_uop_dst_rtype; // @[fdiv.scala:84:7, :185:22] reg [1:0] r_out_uop_lrs1_rtype; // @[fdiv.scala:185:22] assign io_resp_bits_uop_lrs1_rtype_0 = r_out_uop_lrs1_rtype; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_lrs1_rtype_0 = r_out_uop_lrs1_rtype; // @[fdiv.scala:84:7, :185:22] reg [1:0] r_out_uop_lrs2_rtype; // @[fdiv.scala:185:22] assign io_resp_bits_uop_lrs2_rtype_0 = r_out_uop_lrs2_rtype; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_lrs2_rtype_0 = r_out_uop_lrs2_rtype; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_frs3_en; // @[fdiv.scala:185:22] assign io_resp_bits_uop_frs3_en_0 = r_out_uop_frs3_en; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_frs3_en_0 = r_out_uop_frs3_en; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_fp_val; // @[fdiv.scala:185:22] assign io_resp_bits_uop_fp_val_0 = r_out_uop_fp_val; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_fp_val_0 = r_out_uop_fp_val; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_fp_single; // @[fdiv.scala:185:22] assign io_resp_bits_uop_fp_single_0 = r_out_uop_fp_single; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_fp_single_0 = r_out_uop_fp_single; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_xcpt_pf_if; // @[fdiv.scala:185:22] assign io_resp_bits_uop_xcpt_pf_if_0 = r_out_uop_xcpt_pf_if; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_xcpt_pf_if_0 = r_out_uop_xcpt_pf_if; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_xcpt_ae_if; // @[fdiv.scala:185:22] assign io_resp_bits_uop_xcpt_ae_if_0 = r_out_uop_xcpt_ae_if; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_xcpt_ae_if_0 = r_out_uop_xcpt_ae_if; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_xcpt_ma_if; // @[fdiv.scala:185:22] assign io_resp_bits_uop_xcpt_ma_if_0 = r_out_uop_xcpt_ma_if; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_xcpt_ma_if_0 = r_out_uop_xcpt_ma_if; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_bp_debug_if; // @[fdiv.scala:185:22] assign io_resp_bits_uop_bp_debug_if_0 = r_out_uop_bp_debug_if; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_bp_debug_if_0 = r_out_uop_bp_debug_if; // @[fdiv.scala:84:7, :185:22] reg r_out_uop_bp_xcpt_if; // @[fdiv.scala:185:22] assign io_resp_bits_uop_bp_xcpt_if_0 = r_out_uop_bp_xcpt_if; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_bp_xcpt_if_0 = r_out_uop_bp_xcpt_if; // @[fdiv.scala:84:7, :185:22] reg [1:0] r_out_uop_debug_fsrc; // @[fdiv.scala:185:22] assign io_resp_bits_uop_debug_fsrc_0 = r_out_uop_debug_fsrc; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_debug_fsrc_0 = r_out_uop_debug_fsrc; // @[fdiv.scala:84:7, :185:22] reg [1:0] r_out_uop_debug_tsrc; // @[fdiv.scala:185:22] assign io_resp_bits_uop_debug_tsrc_0 = r_out_uop_debug_tsrc; // @[fdiv.scala:84:7, :185:22] assign io_resp_bits_fflags_bits_uop_debug_tsrc_0 = r_out_uop_debug_tsrc; // @[fdiv.scala:84:7, :185:22] reg [4:0] r_out_flags_double; // @[fdiv.scala:186:31] reg [64:0] r_out_wdata_double; // @[fdiv.scala:187:31] wire [64:0] _io_resp_bits_data_T_4 = r_out_wdata_double; // @[package.scala:39:76] assign _output_buffer_available_T = ~r_out_val; // @[fdiv.scala:184:26, :189:30] assign output_buffer_available = _output_buffer_available_T; // @[fdiv.scala:151:37, :189:30] wire [7:0] _r_out_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_out_uop_br_mask_T_1 = r_out_uop_br_mask & _r_out_uop_br_mask_T; // @[util.scala:85:{25,27}] wire [7:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_out_uop_br_mask; // @[util.scala:118:51] wire _T_21 = _divsqrt_io_outValid_div | _divsqrt_io_outValid_sqrt; // @[fdiv.scala:143:23, :196:33] wire _r_out_val_T = ~r_divsqrt_killed; // @[fdiv.scala:146:29, :199:18] wire _r_out_val_T_2 = |_r_out_val_T_1; // @[util.scala:118:{51,59}] wire _r_out_val_T_3 = ~_r_out_val_T_2; // @[util.scala:118:59] wire _r_out_val_T_4 = _r_out_val_T & _r_out_val_T_3; // @[fdiv.scala:199:{18,36,39}] wire _r_out_val_T_5 = ~io_req_bits_kill_0; // @[fdiv.scala:84:7, :105:71, :199:88] wire _r_out_val_T_6 = _r_out_val_T_4 & _r_out_val_T_5; // @[fdiv.scala:199:{36,85,88}] wire [7:0] _r_out_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [7:0] _r_out_uop_br_mask_T_3 = r_divsqrt_uop_br_mask & _r_out_uop_br_mask_T_2; // @[util.scala:85:{25,27}] wire [64:0] r_out_wdata_double_maskedNaN = _divsqrt_io_out & 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:25] wire [2:0] _r_out_wdata_double_T = _divsqrt_io_out[63:61]; // @[FPU.scala:249:25] wire _r_out_wdata_double_T_1 = &_r_out_wdata_double_T; // @[FPU.scala:249:{25,56}] wire [64:0] _r_out_wdata_double_T_2 = _r_out_wdata_double_T_1 ? r_out_wdata_double_maskedNaN : _divsqrt_io_out; // @[FPU.scala:249:56, :413:25, :414:10]
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_router_9ClockSinkDomain : output auto : { routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_9 connect routers.clock, childClock connect routers.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0 connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1 connect auto.routers_egress_nodes_out_0.flit.bits, routers.auto.egress_nodes_out_0.flit.bits connect auto.routers_egress_nodes_out_0.flit.valid, routers.auto.egress_nodes_out_0.flit.valid connect routers.auto.egress_nodes_out_0.flit.ready, auto.routers_egress_nodes_out_0.flit.ready connect auto.routers_egress_nodes_out_1.flit.bits, routers.auto.egress_nodes_out_1.flit.bits connect auto.routers_egress_nodes_out_1.flit.valid, routers.auto.egress_nodes_out_1.flit.valid connect routers.auto.egress_nodes_out_1.flit.ready, auto.routers_egress_nodes_out_1.flit.ready connect auto.routers_egress_nodes_out_2.flit.bits, routers.auto.egress_nodes_out_2.flit.bits connect auto.routers_egress_nodes_out_2.flit.valid, routers.auto.egress_nodes_out_2.flit.valid connect routers.auto.egress_nodes_out_2.flit.ready, auto.routers_egress_nodes_out_2.flit.ready connect auto.routers_debug_out, routers.auto.debug_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset
module TLNoC_router_9ClockSinkDomain( // @[ClockDomain.scala:14:9] output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_9 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_egress_nodes_out_2_flit_valid (auto_routers_egress_nodes_out_2_flit_valid), .auto_egress_nodes_out_2_flit_bits_head (auto_routers_egress_nodes_out_2_flit_bits_head), .auto_egress_nodes_out_2_flit_bits_tail (auto_routers_egress_nodes_out_2_flit_bits_tail), .auto_egress_nodes_out_2_flit_bits_payload (auto_routers_egress_nodes_out_2_flit_bits_payload), .auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready), .auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload), .auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready), .auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail), .auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_113 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_113( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_154 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_169 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_154( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_169 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ClockSinkDomain_4 : output auto : { flip rerocc_tile_ctrl_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, rerocc_tile_buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip rerocc_tile_re_ro_cc_in : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, flip rerocc_tile_rerocc_manager_id_sink_in : UInt<7>, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst rerocc_tile of ReRoCCManagerTile_2 connect rerocc_tile.clock, childClock connect rerocc_tile.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect rerocc_tile.auto.rerocc_manager_id_sink_in, auto.rerocc_tile_rerocc_manager_id_sink_in connect rerocc_tile.auto.re_ro_cc_in, auto.rerocc_tile_re_ro_cc_in connect auto.rerocc_tile_buffer_out.e.bits, rerocc_tile.auto.buffer_out.e.bits connect auto.rerocc_tile_buffer_out.e.valid, rerocc_tile.auto.buffer_out.e.valid connect rerocc_tile.auto.buffer_out.e.ready, auto.rerocc_tile_buffer_out.e.ready connect rerocc_tile.auto.buffer_out.d, auto.rerocc_tile_buffer_out.d connect auto.rerocc_tile_buffer_out.c.bits, rerocc_tile.auto.buffer_out.c.bits connect auto.rerocc_tile_buffer_out.c.valid, rerocc_tile.auto.buffer_out.c.valid connect rerocc_tile.auto.buffer_out.c.ready, auto.rerocc_tile_buffer_out.c.ready connect rerocc_tile.auto.buffer_out.b, auto.rerocc_tile_buffer_out.b connect auto.rerocc_tile_buffer_out.a.bits, rerocc_tile.auto.buffer_out.a.bits connect auto.rerocc_tile_buffer_out.a.valid, rerocc_tile.auto.buffer_out.a.valid connect rerocc_tile.auto.buffer_out.a.ready, auto.rerocc_tile_buffer_out.a.ready connect rerocc_tile.auto.ctrl_ctrl_in, auto.rerocc_tile_ctrl_ctrl_in connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset
module ClockSinkDomain_4( // @[ClockDomain.scala:14:9] output auto_rerocc_tile_ctrl_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_ctrl_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_ctrl_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_rerocc_tile_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_rerocc_tile_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_rerocc_tile_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_rerocc_tile_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_rerocc_tile_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_rerocc_tile_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_rerocc_tile_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_req_ready, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_req_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_rerocc_tile_re_ro_cc_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_rerocc_tile_re_ro_cc_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_rerocc_tile_re_ro_cc_in_req_bits_data, // @[LazyModuleImp.scala:107:25] input auto_rerocc_tile_re_ro_cc_in_resp_ready, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_resp_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_data, // @[LazyModuleImp.scala:107:25] input [6:0] auto_rerocc_tile_rerocc_manager_id_sink_in, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire auto_rerocc_tile_ctrl_ctrl_in_a_valid_0 = auto_rerocc_tile_ctrl_ctrl_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_param_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_size_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_source_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [11:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_address_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_data_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_ready_0 = auto_rerocc_tile_ctrl_ctrl_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_ready_0 = auto_rerocc_tile_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_valid_0 = auto_rerocc_tile_buffer_out_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_b_bits_opcode_0 = auto_rerocc_tile_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_buffer_out_b_bits_param_0 = auto_rerocc_tile_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_b_bits_size_0 = auto_rerocc_tile_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_bits_source_0 = auto_rerocc_tile_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_b_bits_address_0 = auto_rerocc_tile_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_buffer_out_b_bits_mask_0 = auto_rerocc_tile_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_b_bits_data_0 = auto_rerocc_tile_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_bits_corrupt_0 = auto_rerocc_tile_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_ready_0 = auto_rerocc_tile_buffer_out_c_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_valid_0 = auto_rerocc_tile_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_d_bits_opcode_0 = auto_rerocc_tile_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_buffer_out_d_bits_param_0 = auto_rerocc_tile_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_d_bits_size_0 = auto_rerocc_tile_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_source_0 = auto_rerocc_tile_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_d_bits_sink_0 = auto_rerocc_tile_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_denied_0 = auto_rerocc_tile_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_d_bits_data_0 = auto_rerocc_tile_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_bits_corrupt_0 = auto_rerocc_tile_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_e_ready_0 = auto_rerocc_tile_buffer_out_e_ready; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_valid_0 = auto_rerocc_tile_re_ro_cc_in_req_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_re_ro_cc_in_req_bits_opcode_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_opcode; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_re_ro_cc_in_req_bits_client_id_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_client_id; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_re_ro_cc_in_req_bits_data_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_data; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_ready_0 = auto_rerocc_tile_re_ro_cc_in_resp_ready; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_rerocc_manager_id_sink_in_0 = auto_rerocc_tile_rerocc_manager_id_sink_in; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire [1:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_ctrl_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_rerocc_tile_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_buffer_out_c_bits_size_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_rerocc_tile_buffer_out_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_buffer_out_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_buffer_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_buffer_out_e_valid_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_req_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_rerocc_tile_re_ro_cc_in_resp_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] ReRoCCManagerTile_2 rerocc_tile ( // @[Integration.scala:45:54] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_ctrl_ctrl_in_a_ready (auto_rerocc_tile_ctrl_ctrl_in_a_ready_0), .auto_ctrl_ctrl_in_a_valid (auto_rerocc_tile_ctrl_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_opcode (auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_param (auto_rerocc_tile_ctrl_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_size (auto_rerocc_tile_ctrl_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_source (auto_rerocc_tile_ctrl_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_address (auto_rerocc_tile_ctrl_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_mask (auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_data (auto_rerocc_tile_ctrl_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_a_bits_corrupt (auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_d_ready (auto_rerocc_tile_ctrl_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_ctrl_ctrl_in_d_valid (auto_rerocc_tile_ctrl_ctrl_in_d_valid_0), .auto_ctrl_ctrl_in_d_bits_opcode (auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0), .auto_ctrl_ctrl_in_d_bits_size (auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0), .auto_ctrl_ctrl_in_d_bits_source (auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0), .auto_ctrl_ctrl_in_d_bits_data (auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0), .auto_buffer_out_a_ready (auto_rerocc_tile_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (auto_rerocc_tile_buffer_out_a_valid_0), .auto_buffer_out_a_bits_opcode (auto_rerocc_tile_buffer_out_a_bits_opcode_0), .auto_buffer_out_a_bits_param (auto_rerocc_tile_buffer_out_a_bits_param_0), .auto_buffer_out_a_bits_size (auto_rerocc_tile_buffer_out_a_bits_size_0), .auto_buffer_out_a_bits_source (auto_rerocc_tile_buffer_out_a_bits_source_0), .auto_buffer_out_a_bits_address (auto_rerocc_tile_buffer_out_a_bits_address_0), .auto_buffer_out_a_bits_mask (auto_rerocc_tile_buffer_out_a_bits_mask_0), .auto_buffer_out_a_bits_data (auto_rerocc_tile_buffer_out_a_bits_data_0), .auto_buffer_out_a_bits_corrupt (auto_rerocc_tile_buffer_out_a_bits_corrupt_0), .auto_buffer_out_b_ready (auto_rerocc_tile_buffer_out_b_ready_0), .auto_buffer_out_b_valid (auto_rerocc_tile_buffer_out_b_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_opcode (auto_rerocc_tile_buffer_out_b_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_param (auto_rerocc_tile_buffer_out_b_bits_param_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_size (auto_rerocc_tile_buffer_out_b_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_source (auto_rerocc_tile_buffer_out_b_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_address (auto_rerocc_tile_buffer_out_b_bits_address_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_mask (auto_rerocc_tile_buffer_out_b_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_data (auto_rerocc_tile_buffer_out_b_bits_data_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_corrupt (auto_rerocc_tile_buffer_out_b_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_ready (auto_rerocc_tile_buffer_out_c_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_valid (auto_rerocc_tile_buffer_out_c_valid_0), .auto_buffer_out_c_bits_opcode (auto_rerocc_tile_buffer_out_c_bits_opcode_0), .auto_buffer_out_c_bits_param (auto_rerocc_tile_buffer_out_c_bits_param_0), .auto_buffer_out_c_bits_size (auto_rerocc_tile_buffer_out_c_bits_size_0), .auto_buffer_out_c_bits_source (auto_rerocc_tile_buffer_out_c_bits_source_0), .auto_buffer_out_c_bits_address (auto_rerocc_tile_buffer_out_c_bits_address_0), .auto_buffer_out_c_bits_data (auto_rerocc_tile_buffer_out_c_bits_data_0), .auto_buffer_out_c_bits_corrupt (auto_rerocc_tile_buffer_out_c_bits_corrupt_0), .auto_buffer_out_d_ready (auto_rerocc_tile_buffer_out_d_ready_0), .auto_buffer_out_d_valid (auto_rerocc_tile_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (auto_rerocc_tile_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_param (auto_rerocc_tile_buffer_out_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (auto_rerocc_tile_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (auto_rerocc_tile_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_sink (auto_rerocc_tile_buffer_out_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_denied (auto_rerocc_tile_buffer_out_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (auto_rerocc_tile_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_corrupt (auto_rerocc_tile_buffer_out_d_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_ready (auto_rerocc_tile_buffer_out_e_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_valid (auto_rerocc_tile_buffer_out_e_valid_0), .auto_buffer_out_e_bits_sink (auto_rerocc_tile_buffer_out_e_bits_sink_0), .auto_re_ro_cc_in_req_ready (auto_rerocc_tile_re_ro_cc_in_req_ready_0), .auto_re_ro_cc_in_req_valid (auto_rerocc_tile_re_ro_cc_in_req_valid_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_opcode (auto_rerocc_tile_re_ro_cc_in_req_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_client_id (auto_rerocc_tile_re_ro_cc_in_req_bits_client_id_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_manager_id (auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_req_bits_data (auto_rerocc_tile_re_ro_cc_in_req_bits_data_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_resp_ready (auto_rerocc_tile_re_ro_cc_in_resp_ready_0), // @[ClockDomain.scala:14:9] .auto_re_ro_cc_in_resp_valid (auto_rerocc_tile_re_ro_cc_in_resp_valid_0), .auto_re_ro_cc_in_resp_bits_opcode (auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0), .auto_re_ro_cc_in_resp_bits_client_id (auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0), .auto_re_ro_cc_in_resp_bits_manager_id (auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0), .auto_re_ro_cc_in_resp_bits_data (auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0), .auto_rerocc_manager_id_sink_in (auto_rerocc_tile_rerocc_manager_id_sink_in_0) // @[ClockDomain.scala:14:9] ); // @[Integration.scala:45:54] assign auto_rerocc_tile_ctrl_ctrl_in_a_ready = auto_rerocc_tile_ctrl_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_valid = auto_rerocc_tile_ctrl_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode = auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_size = auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_source = auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_data = auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_valid = auto_rerocc_tile_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_opcode = auto_rerocc_tile_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_param = auto_rerocc_tile_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_size = auto_rerocc_tile_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_source = auto_rerocc_tile_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_address = auto_rerocc_tile_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_mask = auto_rerocc_tile_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_data = auto_rerocc_tile_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_a_bits_corrupt = auto_rerocc_tile_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_b_ready = auto_rerocc_tile_buffer_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_valid = auto_rerocc_tile_buffer_out_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_opcode = auto_rerocc_tile_buffer_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_param = auto_rerocc_tile_buffer_out_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_size = auto_rerocc_tile_buffer_out_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_source = auto_rerocc_tile_buffer_out_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_address = auto_rerocc_tile_buffer_out_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_data = auto_rerocc_tile_buffer_out_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_c_bits_corrupt = auto_rerocc_tile_buffer_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_d_ready = auto_rerocc_tile_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_e_valid = auto_rerocc_tile_buffer_out_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_buffer_out_e_bits_sink = auto_rerocc_tile_buffer_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_req_ready = auto_rerocc_tile_re_ro_cc_in_req_ready_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_valid = auto_rerocc_tile_re_ro_cc_in_resp_valid_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode = auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id = auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id = auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0; // @[ClockDomain.scala:14:9] assign auto_rerocc_tile_re_ro_cc_in_resp_bits_data = auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_251 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_251( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_265 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_493 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_265( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_493 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_32 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] connect auto.out, nodeOut connect nodeIn, auto.in inst reg of AsyncResetRegVec_w1_i0_32 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] connect reg.io.en, UInt<1>(0h1) node _T = bits(reg.io.q, 0, 0) connect nodeOut.sync[0], _T
module IntSyncCrossingSource_n1x1_32( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] AsyncResetRegVec_w1_i0_32 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (nodeIn_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_sync_0) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module CoherenceManagerWrapper : output auto : { coupler_to_bus_named_mbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coherent_jbar_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, flip l2_ctrls_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coh_clock_groups_in : { member : { coh_0 : { clock : Clock, reset : Reset}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst coh_clock_groups of ClockGroupAggregator_coh inst clockGroup of ClockGroup_5 inst fixedClockNode of FixedClockBroadcast_1 inst broadcast of BundleBridgeNexus_NoOutput_5 inst l2 of InclusiveCache connect l2.clock, childClock connect l2.reset, childReset inst filter of TLFilter connect filter.clock, childClock connect filter.reset, childReset inst InclusiveCache_inner_TLBuffer of TLBuffer_a32d128s7k4z3c connect InclusiveCache_inner_TLBuffer.clock, childClock connect InclusiveCache_inner_TLBuffer.reset, childReset inst InclusiveCache_outer_TLBuffer of TLBuffer_a32d64s4k3z3c connect InclusiveCache_outer_TLBuffer.clock, childClock connect InclusiveCache_outer_TLBuffer.reset, childReset inst cork of TLCacheCork connect cork.clock, childClock connect cork.reset, childReset inst coherent_jbar of TLJbar connect coherent_jbar.clock, childClock connect coherent_jbar.reset, childReset inst binder of BankBinder connect binder.clock, childClock connect binder.reset, childReset inst coupler_to_bus_named_mbus of TLInterconnectCoupler_coh_to_bus_named_mbus connect coupler_to_bus_named_mbus.clock, childClock connect coupler_to_bus_named_mbus.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock connect clockGroup.auto.in, coh_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out connect InclusiveCache_outer_TLBuffer.auto.in, l2.auto.out connect InclusiveCache_inner_TLBuffer.auto.in, filter.auto.anon_out connect l2.auto.in, InclusiveCache_inner_TLBuffer.auto.out connect cork.auto.in, InclusiveCache_outer_TLBuffer.auto.out connect binder.auto.in, cork.auto.out connect filter.auto.anon_in, coherent_jbar.auto.anon_out connect coupler_to_bus_named_mbus.auto.widget_anon_in, binder.auto.out connect coh_clock_groups.auto.in, auto.coh_clock_groups_in connect l2.auto.ctrls_ctrl_in, auto.l2_ctrls_ctrl_in connect coherent_jbar.auto.anon_in, auto.coherent_jbar_anon_in connect coupler_to_bus_named_mbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_mbus_bus_xing_out.d connect auto.coupler_to_bus_named_mbus_bus_xing_out.a.bits, coupler_to_bus_named_mbus.auto.bus_xing_out.a.bits connect auto.coupler_to_bus_named_mbus_bus_xing_out.a.valid, coupler_to_bus_named_mbus.auto.bus_xing_out.a.valid connect coupler_to_bus_named_mbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_mbus_bus_xing_out.a.ready connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset extmodule plusarg_reader_86 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_87 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module CoherenceManagerWrapper( // @[ClockDomain.scala:14:9] input auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coherent_jbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_coherent_jbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coherent_jbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coherent_jbar_anon_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coherent_jbar_anon_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coherent_jbar_anon_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coherent_jbar_anon_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coherent_jbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coherent_jbar_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coherent_jbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coherent_jbar_anon_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_l2_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_l2_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_l2_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_l2_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_l2_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_l2_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_l2_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_l2_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_l2_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_l2_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coh_clock_groups_in_member_coh_0_clock, // @[LazyModuleImp.scala:107:25] input auto_coh_clock_groups_in_member_coh_0_reset // @[LazyModuleImp.scala:107:25] ); wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [4:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [3:0] coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:216:19] wire [3:0] coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [6:0] coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_in_0_b_bits_source; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire filter_auto_anon_out_d_valid; // @[Filter.scala:60:9] wire filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9] wire filter_auto_anon_out_c_ready; // @[Filter.scala:60:9] wire filter_auto_anon_out_b_valid; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_b_bits_source; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9] wire filter_auto_anon_out_a_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_e_valid; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_in_d_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_bits_denied; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_in_d_bits_sink; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_in_d_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_d_bits_size; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_in_d_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_d_bits_opcode; // @[Filter.scala:60:9] wire filter_auto_anon_in_c_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_c_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9] wire filter_auto_anon_in_b_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_b_ready; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_in_b_bits_address; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_in_b_bits_source; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_in_b_bits_param; // @[Filter.scala:60:9] wire filter_auto_anon_in_a_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_a_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9] wire [15:0] filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9] wire fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] wire fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:53:9] wire _binder_auto_in_a_ready; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_valid; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_d_bits_opcode; // @[BankBinder.scala:71:28] wire [1:0] _binder_auto_in_d_bits_param; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_d_bits_size; // @[BankBinder.scala:71:28] wire [4:0] _binder_auto_in_d_bits_source; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_bits_sink; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_bits_denied; // @[BankBinder.scala:71:28] wire [63:0] _binder_auto_in_d_bits_data; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_bits_corrupt; // @[BankBinder.scala:71:28] wire _cork_auto_out_a_valid; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_a_bits_opcode; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_a_bits_param; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_a_bits_size; // @[Configs.scala:120:26] wire [4:0] _cork_auto_out_a_bits_source; // @[Configs.scala:120:26] wire [31:0] _cork_auto_out_a_bits_address; // @[Configs.scala:120:26] wire [7:0] _cork_auto_out_a_bits_mask; // @[Configs.scala:120:26] wire [63:0] _cork_auto_out_a_bits_data; // @[Configs.scala:120:26] wire _cork_auto_out_a_bits_corrupt; // @[Configs.scala:120:26] wire _cork_auto_out_d_ready; // @[Configs.scala:120:26] wire _InclusiveCache_inner_TLBuffer_auto_out_a_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_size; // @[Parameters.scala:56:69] wire [6:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_address; // @[Parameters.scala:56:69] wire [15:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask; // @[Parameters.scala:56:69] wire [127:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_b_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_c_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_size; // @[Parameters.scala:56:69] wire [6:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_address; // @[Parameters.scala:56:69] wire [127:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_d_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_e_valid; // @[Parameters.scala:56:69] wire [3:0] _InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink; // @[Parameters.scala:56:69] wire _l2_auto_in_a_ready; // @[Configs.scala:93:24] wire _l2_auto_in_b_valid; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_b_bits_param; // @[Configs.scala:93:24] wire [6:0] _l2_auto_in_b_bits_source; // @[Configs.scala:93:24] wire [31:0] _l2_auto_in_b_bits_address; // @[Configs.scala:93:24] wire _l2_auto_in_c_ready; // @[Configs.scala:93:24] wire _l2_auto_in_d_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_d_bits_opcode; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_d_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_d_bits_size; // @[Configs.scala:93:24] wire [6:0] _l2_auto_in_d_bits_source; // @[Configs.scala:93:24] wire [3:0] _l2_auto_in_d_bits_sink; // @[Configs.scala:93:24] wire _l2_auto_in_d_bits_denied; // @[Configs.scala:93:24] wire [127:0] _l2_auto_in_d_bits_data; // @[Configs.scala:93:24] wire _l2_auto_in_d_bits_corrupt; // @[Configs.scala:93:24] wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_a_valid_0 = auto_coherent_jbar_anon_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_a_bits_opcode_0 = auto_coherent_jbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_a_bits_param_0 = auto_coherent_jbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_a_bits_size_0 = auto_coherent_jbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_coherent_jbar_anon_in_a_bits_source_0 = auto_coherent_jbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coherent_jbar_anon_in_a_bits_address_0 = auto_coherent_jbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] auto_coherent_jbar_anon_in_a_bits_mask_0 = auto_coherent_jbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] auto_coherent_jbar_anon_in_a_bits_data_0 = auto_coherent_jbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_a_bits_corrupt_0 = auto_coherent_jbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_b_ready_0 = auto_coherent_jbar_anon_in_b_ready; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_c_valid_0 = auto_coherent_jbar_anon_in_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_c_bits_opcode_0 = auto_coherent_jbar_anon_in_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_c_bits_param_0 = auto_coherent_jbar_anon_in_c_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_c_bits_size_0 = auto_coherent_jbar_anon_in_c_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_coherent_jbar_anon_in_c_bits_source_0 = auto_coherent_jbar_anon_in_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coherent_jbar_anon_in_c_bits_address_0 = auto_coherent_jbar_anon_in_c_bits_address; // @[ClockDomain.scala:14:9] wire [127:0] auto_coherent_jbar_anon_in_c_bits_data_0 = auto_coherent_jbar_anon_in_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_c_bits_corrupt_0 = auto_coherent_jbar_anon_in_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_ready_0 = auto_coherent_jbar_anon_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_e_valid_0 = auto_coherent_jbar_anon_in_e_valid; // @[ClockDomain.scala:14:9] wire [3:0] auto_coherent_jbar_anon_in_e_bits_sink_0 = auto_coherent_jbar_anon_in_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_a_valid_0 = auto_l2_ctrls_ctrl_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode_0 = auto_l2_ctrls_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_param_0 = auto_l2_ctrls_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [1:0] auto_l2_ctrls_ctrl_in_a_bits_size_0 = auto_l2_ctrls_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [11:0] auto_l2_ctrls_ctrl_in_a_bits_source_0 = auto_l2_ctrls_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [25:0] auto_l2_ctrls_ctrl_in_a_bits_address_0 = auto_l2_ctrls_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask_0 = auto_l2_ctrls_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_l2_ctrls_ctrl_in_a_bits_data_0 = auto_l2_ctrls_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_a_bits_corrupt_0 = auto_l2_ctrls_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_ready_0 = auto_l2_ctrls_ctrl_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_coh_clock_groups_in_member_coh_0_clock_0 = auto_coh_clock_groups_in_member_coh_0_clock; // @[ClockDomain.scala:14:9] wire auto_coh_clock_groups_in_member_coh_0_reset_0 = auto_coh_clock_groups_in_member_coh_0_reset; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] filter_auto_anon_in_b_bits_opcode = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_b_bits_size = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_b_bits_opcode = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_b_bits_size = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] filter_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] filter_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_auto_anon_in_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_b_bits_size = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_out_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_out_b_bits_size = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coherent_jbar_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coherent_jbar_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_in_0_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_b_bits_size = 3'h6; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_out_0_b_bits_opcode = 3'h6; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_out_0_b_bits_size = 3'h6; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_size = 3'h6; // @[Xbar.scala:352:24] wire [15:0] auto_coherent_jbar_anon_in_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9] wire [15:0] filter_auto_anon_in_b_bits_mask = 16'hFFFF; // @[Filter.scala:60:9] wire [15:0] filter_auto_anon_out_b_bits_mask = 16'hFFFF; // @[Filter.scala:60:9] wire [15:0] filter_anonOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] filter_anonIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coherent_jbar_auto_anon_in_b_bits_mask = 16'hFFFF; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_auto_anon_out_b_bits_mask = 16'hFFFF; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_anonOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] coherent_jbar_anonIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coherent_jbar_in_0_b_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] coherent_jbar_out_0_b_bits_mask = 16'hFFFF; // @[Xbar.scala:216:19] wire [15:0] coherent_jbar_portsBIO_filtered_0_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [127:0] auto_coherent_jbar_anon_in_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9] wire [127:0] filter_auto_anon_in_b_bits_data = 128'h0; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_b_bits_data = 128'h0; // @[Filter.scala:60:9] wire [127:0] filter_anonOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] filter_anonIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coherent_jbar_auto_anon_in_b_bits_data = 128'h0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_out_b_bits_data = 128'h0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coherent_jbar_anonIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coherent_jbar_in_0_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_out_0_b_bits_data = 128'h0; // @[Xbar.scala:216:19] wire [127:0] coherent_jbar_portsBIO_filtered_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire auto_coherent_jbar_anon_in_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire coh_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire coh_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire coh_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixedClockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire fixedClockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire fixedClockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire filter_auto_anon_in_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9] wire filter_auto_anon_out_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9] wire filter_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire filter_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_auto_in_b_valid = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_b_valid = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_b_valid = 1'h0; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeIn_b_valid = 1'h0; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_in_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coherent_jbar_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coherent_jbar_in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire coherent_jbar_out_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire coherent_jbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire coherent_jbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire coherent_jbar__requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire coherent_jbar_beatsBO_opdata = 1'h0; // @[Edges.scala:97:28] wire coherent_jbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire auto_coherent_jbar_anon_in_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire filter_auto_anon_in_e_ready = 1'h1; // @[Filter.scala:60:9] wire filter_auto_anon_out_e_ready = 1'h1; // @[Filter.scala:60:9] wire filter_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire filter_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_auto_in_b_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_e_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_b_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_e_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_b_ready = 1'h1; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeIn_b_ready = 1'h1; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_in_e_ready = 1'h1; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_e_ready = 1'h1; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coherent_jbar_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coherent_jbar_in_0_e_ready = 1'h1; // @[Xbar.scala:159:18] wire coherent_jbar_out_0_e_ready = 1'h1; // @[Xbar.scala:216:19] wire coherent_jbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire coherent_jbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire coherent_jbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire coherent_jbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire coherent_jbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire coherent_jbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire coherent_jbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire coherent_jbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire coherent_jbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire coherent_jbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire coherent_jbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire coherent_jbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire coherent_jbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire coherent_jbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire coherent_jbar__requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire coherent_jbar__requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire coherent_jbar__requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire coherent_jbar__requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire coherent_jbar_requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48] wire coherent_jbar__beatsBO_opdata_T = 1'h1; // @[Edges.scala:97:37] wire coherent_jbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar_portsEOI_filtered_0_ready = 1'h1; // @[Xbar.scala:352:24] wire coherent_jbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] coherent_jbar_beatsBO_0 = 2'h0; // @[Edges.scala:221:14] wire [1:0] coherent_jbar_beatsBO_decode = 2'h3; // @[Edges.scala:220:59] wire [5:0] coherent_jbar__beatsBO_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] coherent_jbar__beatsBO_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] coherent_jbar__beatsBO_decode_T = 13'hFC0; // @[package.scala:243:71] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_size = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_size = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_size = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_size = 3'h0; // @[MixedNode.scala:551:17] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_source = 4'h0; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_source = 4'h0; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_source = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_source = 4'h0; // @[MixedNode.scala:551:17] wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_address = 32'h0; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_address = 32'h0; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_address = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_address = 32'h0; // @[MixedNode.scala:551:17] wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_mask = 8'h0; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_mask = 8'h0; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_mask = 8'h0; // @[MixedNode.scala:542:17] wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_data = 64'h0; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_data = 64'h0; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [32:0] coherent_jbar__requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] coherent_jbar__requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] coherent_jbar__requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] coherent_jbar__requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coherent_jbar_auto_anon_in_a_valid = auto_coherent_jbar_anon_in_a_valid_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_a_bits_opcode = auto_coherent_jbar_anon_in_a_bits_opcode_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_a_bits_param = auto_coherent_jbar_anon_in_a_bits_param_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_a_bits_size = auto_coherent_jbar_anon_in_a_bits_size_0; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_in_a_bits_source = auto_coherent_jbar_anon_in_a_bits_source_0; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_auto_anon_in_a_bits_address = auto_coherent_jbar_anon_in_a_bits_address_0; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_auto_anon_in_a_bits_mask = auto_coherent_jbar_anon_in_a_bits_mask_0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_in_a_bits_data = auto_coherent_jbar_anon_in_a_bits_data_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_a_bits_corrupt = auto_coherent_jbar_anon_in_a_bits_corrupt_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_b_ready = auto_coherent_jbar_anon_in_b_ready_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_in_b_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_c_valid = auto_coherent_jbar_anon_in_c_valid_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_c_bits_opcode = auto_coherent_jbar_anon_in_c_bits_opcode_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_c_bits_param = auto_coherent_jbar_anon_in_c_bits_param_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_c_bits_size = auto_coherent_jbar_anon_in_c_bits_size_0; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_in_c_bits_source = auto_coherent_jbar_anon_in_c_bits_source_0; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_auto_anon_in_c_bits_address = auto_coherent_jbar_anon_in_c_bits_address_0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_in_c_bits_data = auto_coherent_jbar_anon_in_c_bits_data_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_c_bits_corrupt = auto_coherent_jbar_anon_in_c_bits_corrupt_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_ready = auto_coherent_jbar_anon_in_d_ready_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_e_valid = auto_coherent_jbar_anon_in_e_valid_0; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_auto_anon_in_e_bits_sink = auto_coherent_jbar_anon_in_e_bits_sink_0; // @[Jbar.scala:44:9] wire coh_clock_groups_auto_in_member_coh_0_clock = auto_coh_clock_groups_in_member_coh_0_clock_0; // @[ClockGroup.scala:53:9] wire coh_clock_groups_auto_in_member_coh_0_reset = auto_coh_clock_groups_in_member_coh_0_reset_0; // @[ClockGroup.scala:53:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_coherent_jbar_anon_in_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire coh_clock_groups_nodeIn_member_coh_0_clock = coh_clock_groups_auto_in_member_coh_0_clock; // @[ClockGroup.scala:53:9] wire coh_clock_groups_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17] wire coh_clock_groups_nodeIn_member_coh_0_reset = coh_clock_groups_auto_in_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire coh_clock_groups_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_coh_0_clock = coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_coh_0_reset = coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign coh_clock_groups_auto_out_member_coh_0_clock = coh_clock_groups_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9] assign coh_clock_groups_auto_out_member_coh_0_reset = coh_clock_groups_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9] assign coh_clock_groups_nodeOut_member_coh_0_clock = coh_clock_groups_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17] assign coh_clock_groups_nodeOut_member_coh_0_reset = coh_clock_groups_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_coh_0_clock = clockGroup_auto_in_member_coh_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_coh_0_reset = clockGroup_auto_in_member_coh_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire fixedClockNode_auto_anon_in_clock = clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9, :104:9] wire fixedClockNode_auto_anon_in_reset = clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9, :104:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixedClockNode_anonIn_clock = fixedClockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire fixedClockNode_anonOut_clock; // @[MixedNode.scala:542:17] wire fixedClockNode_anonIn_reset = fixedClockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] wire fixedClockNode_anonOut_reset; // @[MixedNode.scala:542:17] assign clockSinkNodeIn_clock = fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] assign clockSinkNodeIn_reset = fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] assign fixedClockNode_auto_anon_out_clock = fixedClockNode_anonOut_clock; // @[ClockGroup.scala:104:9] assign fixedClockNode_auto_anon_out_reset = fixedClockNode_anonOut_reset; // @[ClockGroup.scala:104:9] assign fixedClockNode_anonOut_clock = fixedClockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17] assign fixedClockNode_anonOut_reset = fixedClockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17] wire filter_anonIn_a_ready; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_a_ready = filter_auto_anon_in_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9] wire filter_anonIn_a_valid = filter_auto_anon_in_a_valid; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_a_bits_opcode = filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_a_bits_param = filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_a_bits_size = filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9] wire [6:0] coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9] wire [6:0] filter_anonIn_a_bits_source = filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9] wire [31:0] coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9] wire [31:0] filter_anonIn_a_bits_address = filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9] wire [15:0] coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9] wire [15:0] filter_anonIn_a_bits_mask = filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9] wire [127:0] coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9] wire [127:0] filter_anonIn_a_bits_data = filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9] wire filter_anonIn_a_bits_corrupt = filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9] wire filter_anonIn_b_ready = filter_auto_anon_in_b_ready; // @[Filter.scala:60:9] wire filter_anonIn_b_valid; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_b_valid = filter_auto_anon_in_b_valid; // @[Jbar.scala:44:9] wire [1:0] filter_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coherent_jbar_auto_anon_out_b_bits_param = filter_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9] wire [6:0] filter_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] filter_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [6:0] coherent_jbar_auto_anon_out_b_bits_source = filter_auto_anon_in_b_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_auto_anon_out_b_bits_address = filter_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9] wire filter_anonIn_c_ready; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_c_ready = filter_auto_anon_in_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9] wire filter_anonIn_c_valid = filter_auto_anon_in_c_valid; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_c_bits_opcode = filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_c_bits_param = filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_c_bits_size = filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9] wire [6:0] coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9] wire [6:0] filter_anonIn_c_bits_source = filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9] wire [31:0] coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9] wire [31:0] filter_anonIn_c_bits_address = filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9] wire [127:0] coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9] wire [127:0] filter_anonIn_c_bits_data = filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9] wire filter_anonIn_c_bits_corrupt = filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9] wire filter_anonIn_d_ready = filter_auto_anon_in_d_ready; // @[Filter.scala:60:9] wire filter_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] filter_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_d_valid = filter_auto_anon_in_d_valid; // @[Jbar.scala:44:9] wire [1:0] filter_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_auto_anon_out_d_bits_opcode = filter_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coherent_jbar_auto_anon_out_d_bits_param = filter_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9] wire [6:0] filter_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_auto_anon_out_d_bits_size = filter_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9] wire [3:0] filter_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [6:0] coherent_jbar_auto_anon_out_d_bits_source = filter_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9] wire filter_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [3:0] coherent_jbar_auto_anon_out_d_bits_sink = filter_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9] wire [127:0] filter_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_d_bits_denied = filter_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9] wire filter_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [127:0] coherent_jbar_auto_anon_out_d_bits_data = filter_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_d_bits_corrupt = filter_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9] wire filter_anonIn_e_valid = filter_auto_anon_in_e_valid; // @[Filter.scala:60:9] wire [3:0] coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9] wire [3:0] filter_anonIn_e_bits_sink = filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9] wire filter_anonOut_a_ready = filter_auto_anon_out_a_ready; // @[Filter.scala:60:9] wire filter_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] filter_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] filter_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] filter_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] filter_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire filter_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire filter_anonOut_b_ready; // @[MixedNode.scala:542:17] wire filter_anonOut_b_valid = filter_auto_anon_out_b_valid; // @[Filter.scala:60:9] wire [1:0] filter_anonOut_b_bits_param = filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9] wire [6:0] filter_anonOut_b_bits_source = filter_auto_anon_out_b_bits_source; // @[Filter.scala:60:9] wire [31:0] filter_anonOut_b_bits_address = filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9] wire filter_anonOut_c_ready = filter_auto_anon_out_c_ready; // @[Filter.scala:60:9] wire filter_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [6:0] filter_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] filter_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] filter_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire filter_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire filter_anonOut_d_ready; // @[MixedNode.scala:542:17] wire filter_anonOut_d_valid = filter_auto_anon_out_d_valid; // @[Filter.scala:60:9] wire [2:0] filter_anonOut_d_bits_opcode = filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9] wire [1:0] filter_anonOut_d_bits_param = filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_anonOut_d_bits_size = filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9] wire [6:0] filter_anonOut_d_bits_source = filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9] wire [3:0] filter_anonOut_d_bits_sink = filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9] wire filter_anonOut_d_bits_denied = filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9] wire [127:0] filter_anonOut_d_bits_data = filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9] wire filter_anonOut_d_bits_corrupt = filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9] wire filter_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] filter_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] filter_auto_anon_out_a_bits_opcode; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_a_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_a_bits_size; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_a_bits_source; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_out_a_bits_address; // @[Filter.scala:60:9] wire [15:0] filter_auto_anon_out_a_bits_mask; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_a_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_out_a_bits_corrupt; // @[Filter.scala:60:9] wire filter_auto_anon_out_a_valid; // @[Filter.scala:60:9] wire filter_auto_anon_out_b_ready; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_c_bits_opcode; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_c_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_c_bits_size; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_c_bits_source; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_out_c_bits_address; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_c_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_out_c_bits_corrupt; // @[Filter.scala:60:9] wire filter_auto_anon_out_c_valid; // @[Filter.scala:60:9] wire filter_auto_anon_out_d_ready; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_out_e_bits_sink; // @[Filter.scala:60:9] wire filter_auto_anon_out_e_valid; // @[Filter.scala:60:9] assign filter_anonIn_a_ready = filter_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_out_a_valid = filter_anonOut_a_valid; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_opcode = filter_anonOut_a_bits_opcode; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_param = filter_anonOut_a_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_size = filter_anonOut_a_bits_size; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_source = filter_anonOut_a_bits_source; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_address = filter_anonOut_a_bits_address; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_mask = filter_anonOut_a_bits_mask; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_data = filter_anonOut_a_bits_data; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_corrupt = filter_anonOut_a_bits_corrupt; // @[Filter.scala:60:9] assign filter_auto_anon_out_b_ready = filter_anonOut_b_ready; // @[Filter.scala:60:9] assign filter_anonIn_b_valid = filter_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_b_bits_param = filter_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_b_bits_source = filter_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_b_bits_address = filter_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_c_ready = filter_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_out_c_valid = filter_anonOut_c_valid; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_opcode = filter_anonOut_c_bits_opcode; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_param = filter_anonOut_c_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_size = filter_anonOut_c_bits_size; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_source = filter_anonOut_c_bits_source; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_address = filter_anonOut_c_bits_address; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_data = filter_anonOut_c_bits_data; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_corrupt = filter_anonOut_c_bits_corrupt; // @[Filter.scala:60:9] assign filter_auto_anon_out_d_ready = filter_anonOut_d_ready; // @[Filter.scala:60:9] assign filter_anonIn_d_valid = filter_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_opcode = filter_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_param = filter_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_size = filter_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_source = filter_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_sink = filter_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_denied = filter_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_data = filter_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_corrupt = filter_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_out_e_valid = filter_anonOut_e_valid; // @[Filter.scala:60:9] assign filter_auto_anon_out_e_bits_sink = filter_anonOut_e_bits_sink; // @[Filter.scala:60:9] assign filter_auto_anon_in_a_ready = filter_anonIn_a_ready; // @[Filter.scala:60:9] assign filter_anonOut_a_valid = filter_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_opcode = filter_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_param = filter_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_size = filter_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_source = filter_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_address = filter_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_mask = filter_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_data = filter_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_corrupt = filter_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_b_ready = filter_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_in_b_valid = filter_anonIn_b_valid; // @[Filter.scala:60:9] assign filter_auto_anon_in_b_bits_param = filter_anonIn_b_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_in_b_bits_source = filter_anonIn_b_bits_source; // @[Filter.scala:60:9] assign filter_auto_anon_in_b_bits_address = filter_anonIn_b_bits_address; // @[Filter.scala:60:9] assign filter_auto_anon_in_c_ready = filter_anonIn_c_ready; // @[Filter.scala:60:9] assign filter_anonOut_c_valid = filter_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_opcode = filter_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_param = filter_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_size = filter_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_source = filter_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_address = filter_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_data = filter_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_corrupt = filter_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_d_ready = filter_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_in_d_valid = filter_anonIn_d_valid; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_opcode = filter_anonIn_d_bits_opcode; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_param = filter_anonIn_d_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_size = filter_anonIn_d_bits_size; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_source = filter_anonIn_d_bits_source; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_sink = filter_anonIn_d_bits_sink; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_denied = filter_anonIn_d_bits_denied; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_data = filter_anonIn_d_bits_data; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_corrupt = filter_anonIn_d_bits_corrupt; // @[Filter.scala:60:9] assign filter_anonOut_e_valid = filter_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_e_bits_sink = filter_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_a_valid = InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param = InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size = InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source = InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address = InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask = InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data = InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_c_valid = InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param = InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size = InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source = InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address = InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data = InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_d_ready = InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_e_valid = InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink = InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_a_ready = InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_c_ready = InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_d_valid = InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode = InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param = InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size = InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source = InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink = InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied = InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data = InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_e_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeIn_a_ready = InclusiveCache_outer_TLBuffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_out_a_valid = InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeIn_c_ready = InclusiveCache_outer_TLBuffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_out_c_valid = InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_d_ready = InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeIn_d_valid = InclusiveCache_outer_TLBuffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_out_e_valid = InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_a_ready = InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeOut_a_valid = InclusiveCache_outer_TLBuffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_in_c_ready = InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeOut_c_valid = InclusiveCache_outer_TLBuffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_d_ready = InclusiveCache_outer_TLBuffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_in_d_valid = InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeOut_e_valid = InclusiveCache_outer_TLBuffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coherent_jbar_anonIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_a_ready_0 = coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_a_valid = coherent_jbar_auto_anon_in_a_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_a_bits_opcode = coherent_jbar_auto_anon_in_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_a_bits_param = coherent_jbar_auto_anon_in_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_a_bits_size = coherent_jbar_auto_anon_in_a_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonIn_a_bits_source = coherent_jbar_auto_anon_in_a_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonIn_a_bits_address = coherent_jbar_auto_anon_in_a_bits_address; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_anonIn_a_bits_mask = coherent_jbar_auto_anon_in_a_bits_mask; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonIn_a_bits_data = coherent_jbar_auto_anon_in_a_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_a_bits_corrupt = coherent_jbar_auto_anon_in_a_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_b_ready = coherent_jbar_auto_anon_in_b_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_b_valid_0 = coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_b_bits_param_0 = coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonIn_b_bits_source; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_b_bits_source_0 = coherent_jbar_auto_anon_in_b_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_b_bits_address_0 = coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_c_ready_0 = coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_c_valid = coherent_jbar_auto_anon_in_c_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_c_bits_opcode = coherent_jbar_auto_anon_in_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_c_bits_param = coherent_jbar_auto_anon_in_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_c_bits_size = coherent_jbar_auto_anon_in_c_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonIn_c_bits_source = coherent_jbar_auto_anon_in_c_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonIn_c_bits_address = coherent_jbar_auto_anon_in_c_bits_address; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonIn_c_bits_data = coherent_jbar_auto_anon_in_c_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_c_bits_corrupt = coherent_jbar_auto_anon_in_c_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_ready = coherent_jbar_auto_anon_in_d_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_valid_0 = coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_opcode_0 = coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_param_0 = coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_size_0 = coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_source_0 = coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_sink_0 = coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_denied_0 = coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_data_0 = coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_corrupt_0 = coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_e_valid = coherent_jbar_auto_anon_in_e_valid; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonIn_e_bits_sink = coherent_jbar_auto_anon_in_e_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_a_ready = coherent_jbar_auto_anon_out_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_a_valid; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_valid = coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_opcode = coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_param = coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_size = coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_source = coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_address = coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_mask = coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_data = coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_corrupt = coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_b_ready; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_b_ready = coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_b_valid = coherent_jbar_auto_anon_out_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonOut_b_bits_param = coherent_jbar_auto_anon_out_b_bits_param; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_b_bits_source = coherent_jbar_auto_anon_out_b_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonOut_b_bits_address = coherent_jbar_auto_anon_out_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_c_ready = coherent_jbar_auto_anon_out_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_c_valid; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_valid = coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_opcode = coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_c_bits_param; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_param = coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_c_bits_size; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_size = coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_c_bits_source; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_source = coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonOut_c_bits_address; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_address = coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_c_bits_data; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_data = coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_corrupt = coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_ready; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_d_ready = coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_valid = coherent_jbar_auto_anon_out_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_d_bits_opcode = coherent_jbar_auto_anon_out_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonOut_d_bits_param = coherent_jbar_auto_anon_out_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_d_bits_size = coherent_jbar_auto_anon_out_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_d_bits_source = coherent_jbar_auto_anon_out_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonOut_d_bits_sink = coherent_jbar_auto_anon_out_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_bits_denied = coherent_jbar_auto_anon_out_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_d_bits_data = coherent_jbar_auto_anon_out_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_bits_corrupt = coherent_jbar_auto_anon_out_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_e_valid; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_e_valid = coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_e_bits_sink = coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_a_ready = coherent_jbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_valid = coherent_jbar_anonOut_a_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_opcode = coherent_jbar_anonOut_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_param = coherent_jbar_anonOut_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_size = coherent_jbar_anonOut_a_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_source = coherent_jbar_anonOut_a_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_address = coherent_jbar_anonOut_a_bits_address; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_mask = coherent_jbar_anonOut_a_bits_mask; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_data = coherent_jbar_anonOut_a_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_corrupt = coherent_jbar_anonOut_a_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_b_ready = coherent_jbar_anonOut_b_ready; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_b_valid = coherent_jbar_anonOut_b_valid; // @[Xbar.scala:216:19] wire [1:0] coherent_jbar_out_0_b_bits_param = coherent_jbar_anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [6:0] coherent_jbar_out_0_b_bits_source = coherent_jbar_anonOut_b_bits_source; // @[Xbar.scala:216:19] wire [31:0] coherent_jbar_out_0_b_bits_address = coherent_jbar_anonOut_b_bits_address; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_c_ready = coherent_jbar_anonOut_c_ready; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_valid = coherent_jbar_anonOut_c_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_opcode = coherent_jbar_anonOut_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_param = coherent_jbar_anonOut_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_size = coherent_jbar_anonOut_c_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_source = coherent_jbar_anonOut_c_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_address = coherent_jbar_anonOut_c_bits_address; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_data = coherent_jbar_anonOut_c_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_corrupt = coherent_jbar_anonOut_c_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_d_ready = coherent_jbar_anonOut_d_ready; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_d_valid = coherent_jbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_out_0_d_bits_opcode = coherent_jbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] coherent_jbar_out_0_d_bits_param = coherent_jbar_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_out_0_d_bits_size = coherent_jbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [6:0] coherent_jbar_out_0_d_bits_source = coherent_jbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [3:0] coherent_jbar__out_0_d_bits_sink_T = coherent_jbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire coherent_jbar_out_0_d_bits_denied = coherent_jbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [127:0] coherent_jbar_out_0_d_bits_data = coherent_jbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_d_bits_corrupt = coherent_jbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_e_valid = coherent_jbar_anonOut_e_valid; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign coherent_jbar_auto_anon_out_e_bits_sink = coherent_jbar_anonOut_e_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_a_ready = coherent_jbar_anonIn_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_a_valid = coherent_jbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_a_bits_opcode = coherent_jbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_a_bits_param = coherent_jbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_a_bits_size = coherent_jbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar__in_0_a_bits_source_T = coherent_jbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] coherent_jbar_in_0_a_bits_address = coherent_jbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] coherent_jbar_in_0_a_bits_mask = coherent_jbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_in_0_a_bits_data = coherent_jbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_a_bits_corrupt = coherent_jbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_b_ready = coherent_jbar_anonIn_b_ready; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_b_valid = coherent_jbar_anonIn_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_b_bits_param = coherent_jbar_anonIn_b_bits_param; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar__anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign coherent_jbar_auto_anon_in_b_bits_source = coherent_jbar_anonIn_b_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_b_bits_address = coherent_jbar_anonIn_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_c_ready = coherent_jbar_anonIn_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_c_valid = coherent_jbar_anonIn_c_valid; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_c_bits_opcode = coherent_jbar_anonIn_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_c_bits_param = coherent_jbar_anonIn_c_bits_param; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_c_bits_size = coherent_jbar_anonIn_c_bits_size; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar__in_0_c_bits_source_T = coherent_jbar_anonIn_c_bits_source; // @[Xbar.scala:187:55] wire [31:0] coherent_jbar_in_0_c_bits_address = coherent_jbar_anonIn_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_in_0_c_bits_data = coherent_jbar_anonIn_c_bits_data; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_c_bits_corrupt = coherent_jbar_anonIn_c_bits_corrupt; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_d_ready = coherent_jbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_valid = coherent_jbar_anonIn_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_opcode = coherent_jbar_anonIn_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_param = coherent_jbar_anonIn_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_size = coherent_jbar_anonIn_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign coherent_jbar_auto_anon_in_d_bits_source = coherent_jbar_anonIn_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_sink = coherent_jbar_anonIn_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_denied = coherent_jbar_anonIn_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_data = coherent_jbar_anonIn_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_corrupt = coherent_jbar_anonIn_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_e_valid = coherent_jbar_anonIn_e_valid; // @[Xbar.scala:159:18] wire [3:0] coherent_jbar_in_0_e_bits_sink = coherent_jbar_anonIn_e_bits_sink; // @[Xbar.scala:159:18] wire coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_a_ready = coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18] wire coherent_jbar__portsAOI_filtered_0_valid_T_1 = coherent_jbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_opcode = coherent_jbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_param = coherent_jbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_size = coherent_jbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] coherent_jbar_portsAOI_filtered_0_bits_source = coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] coherent_jbar__requestAIO_T = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] coherent_jbar_portsAOI_filtered_0_bits_address = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] coherent_jbar_portsAOI_filtered_0_bits_mask = coherent_jbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] coherent_jbar_portsAOI_filtered_0_bits_data = coherent_jbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsAOI_filtered_0_bits_corrupt = coherent_jbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsBIO_filtered_0_ready = coherent_jbar_in_0_b_ready; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_b_valid = coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18] wire [1:0] coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_b_bits_param = coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_portsBIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign coherent_jbar__anonIn_b_bits_source_T = coherent_jbar_in_0_b_bits_source; // @[Xbar.scala:156:69, :159:18] wire [31:0] coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_b_bits_address = coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18] wire coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_c_ready = coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18] wire coherent_jbar__portsCOI_filtered_0_valid_T_1 = coherent_jbar_in_0_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_opcode = coherent_jbar_in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_param = coherent_jbar_in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_size = coherent_jbar_in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] coherent_jbar_portsCOI_filtered_0_bits_source = coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] coherent_jbar__requestCIO_T = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] coherent_jbar_portsCOI_filtered_0_bits_address = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] coherent_jbar_portsCOI_filtered_0_bits_data = coherent_jbar_in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsCOI_filtered_0_bits_corrupt = coherent_jbar_in_0_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsDIO_filtered_0_ready = coherent_jbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_valid = coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_opcode = coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_param = coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_size = coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign coherent_jbar__anonIn_d_bits_source_T = coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire [3:0] coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_sink = coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] wire coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_denied = coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_data = coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_corrupt = coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire coherent_jbar__portsEOI_filtered_0_valid_T_1 = coherent_jbar_in_0_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] coherent_jbar__requestEIO_uncommonBits_T = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18] wire [3:0] coherent_jbar_portsEOI_filtered_0_bits_sink = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_a_bits_source = coherent_jbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign coherent_jbar_anonIn_b_bits_source = coherent_jbar__anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign coherent_jbar_in_0_c_bits_source = coherent_jbar__in_0_c_bits_source_T; // @[Xbar.scala:159:18, :187:55] assign coherent_jbar_anonIn_d_bits_source = coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign coherent_jbar_portsAOI_filtered_0_ready = coherent_jbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonOut_a_valid = coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_opcode = coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_param = coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_size = coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_source = coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_address = coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_mask = coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_data = coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_corrupt = coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_b_ready = coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19] wire coherent_jbar__portsBIO_filtered_0_valid_T_1 = coherent_jbar_out_0_b_valid; // @[Xbar.scala:216:19, :355:40] assign coherent_jbar_portsBIO_filtered_0_bits_param = coherent_jbar_out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] wire [6:0] coherent_jbar__requestBOI_uncommonBits_T = coherent_jbar_out_0_b_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_portsBIO_filtered_0_bits_source = coherent_jbar_out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsBIO_filtered_0_bits_address = coherent_jbar_out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsCOI_filtered_0_ready = coherent_jbar_out_0_c_ready; // @[Xbar.scala:216:19, :352:24] wire coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonOut_c_valid = coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_opcode = coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_param = coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_size = coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_source = coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_address = coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_data = coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_corrupt = coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_d_ready = coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19] wire coherent_jbar__portsDIO_filtered_0_valid_T_1 = coherent_jbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign coherent_jbar_portsDIO_filtered_0_bits_opcode = coherent_jbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_param = coherent_jbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_size = coherent_jbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] coherent_jbar__requestDOI_uncommonBits_T = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_portsDIO_filtered_0_bits_source = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_sink = coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_denied = coherent_jbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_data = coherent_jbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_corrupt = coherent_jbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonOut_e_valid = coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19] assign coherent_jbar__anonOut_e_bits_sink_T = coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19] assign coherent_jbar_out_0_d_bits_sink = coherent_jbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign coherent_jbar_anonOut_e_bits_sink = coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] coherent_jbar__requestAIO_T_1 = {1'h0, coherent_jbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] coherent_jbar__requestCIO_T_1 = {1'h0, coherent_jbar__requestCIO_T}; // @[Parameters.scala:137:{31,41}] wire [6:0] coherent_jbar_requestBOI_uncommonBits = coherent_jbar__requestBOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [6:0] coherent_jbar_requestDOI_uncommonBits = coherent_jbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] coherent_jbar_requestEIO_uncommonBits = coherent_jbar__requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] coherent_jbar__beatsAI_decode_T = 13'h3F << coherent_jbar_in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] coherent_jbar__beatsAI_decode_T_1 = coherent_jbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] coherent_jbar__beatsAI_decode_T_2 = ~coherent_jbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] coherent_jbar_beatsAI_decode = coherent_jbar__beatsAI_decode_T_2[5:4]; // @[package.scala:243:46] wire coherent_jbar__beatsAI_opdata_T = coherent_jbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire coherent_jbar_beatsAI_opdata = ~coherent_jbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [1:0] coherent_jbar_beatsAI_0 = coherent_jbar_beatsAI_opdata ? coherent_jbar_beatsAI_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] coherent_jbar__beatsCI_decode_T = 13'h3F << coherent_jbar_in_0_c_bits_size; // @[package.scala:243:71] wire [5:0] coherent_jbar__beatsCI_decode_T_1 = coherent_jbar__beatsCI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] coherent_jbar__beatsCI_decode_T_2 = ~coherent_jbar__beatsCI_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] coherent_jbar_beatsCI_decode = coherent_jbar__beatsCI_decode_T_2[5:4]; // @[package.scala:243:46] wire coherent_jbar_beatsCI_opdata = coherent_jbar_in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [1:0] coherent_jbar_beatsCI_0 = coherent_jbar_beatsCI_opdata ? coherent_jbar_beatsCI_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [12:0] coherent_jbar__beatsDO_decode_T = 13'h3F << coherent_jbar_out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] coherent_jbar__beatsDO_decode_T_1 = coherent_jbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] coherent_jbar__beatsDO_decode_T_2 = ~coherent_jbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] coherent_jbar_beatsDO_decode = coherent_jbar__beatsDO_decode_T_2[5:4]; // @[package.scala:243:46] wire coherent_jbar_beatsDO_opdata = coherent_jbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [1:0] coherent_jbar_beatsDO_0 = coherent_jbar_beatsDO_opdata ? coherent_jbar_beatsDO_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign coherent_jbar_in_0_a_ready = coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_out_0_a_valid = coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_opcode = coherent_jbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_param = coherent_jbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_size = coherent_jbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_source = coherent_jbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_address = coherent_jbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_mask = coherent_jbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_data = coherent_jbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_corrupt = coherent_jbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsAOI_filtered_0_valid = coherent_jbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_out_0_b_ready = coherent_jbar_portsBIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_in_0_b_valid = coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_b_bits_param = coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_b_bits_source = coherent_jbar_portsBIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_b_bits_address = coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_portsBIO_filtered_0_valid = coherent_jbar__portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_in_0_c_ready = coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_out_0_c_valid = coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_opcode = coherent_jbar_portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_param = coherent_jbar_portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_size = coherent_jbar_portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_source = coherent_jbar_portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_address = coherent_jbar_portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_data = coherent_jbar_portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_corrupt = coherent_jbar_portsCOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsCOI_filtered_0_valid = coherent_jbar__portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_out_0_d_ready = coherent_jbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_in_0_d_valid = coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_opcode = coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_param = coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_size = coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_source = coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_sink = coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_denied = coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_data = coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_corrupt = coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_portsDIO_filtered_0_valid = coherent_jbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_out_0_e_valid = coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_e_bits_sink = coherent_jbar_portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsEOI_filtered_0_valid = coherent_jbar__portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingOut_a_ready = coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_bus_xingOut_d_valid = coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_param = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_size = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17] wire [4:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_source = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_data = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [4:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [4:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_anonIn_a_ready = coupler_to_bus_named_mbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_anonIn_d_valid = coupler_to_bus_named_mbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_param = coupler_to_bus_named_mbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_size = coupler_to_bus_named_mbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_source = coupler_to_bus_named_mbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_data = coupler_to_bus_named_mbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_anonOut_a_valid = coupler_to_bus_named_mbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_param = coupler_to_bus_named_mbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_size = coupler_to_bus_named_mbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_source = coupler_to_bus_named_mbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_address = coupler_to_bus_named_mbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_data = coupler_to_bus_named_mbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_d_ready = coupler_to_bus_named_mbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_bus_xingIn_a_ready = coupler_to_bus_named_mbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_valid = coupler_to_bus_named_mbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_param = coupler_to_bus_named_mbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_size = coupler_to_bus_named_mbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_source = coupler_to_bus_named_mbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_data = coupler_to_bus_named_mbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_bus_xingOut_a_valid = coupler_to_bus_named_mbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_param = coupler_to_bus_named_mbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_size = coupler_to_bus_named_mbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_source = coupler_to_bus_named_mbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_address = coupler_to_bus_named_mbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_data = coupler_to_bus_named_mbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_d_ready = coupler_to_bus_named_mbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] InclusiveCache l2 ( // @[Configs.scala:93:24] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_ctrls_ctrl_in_a_ready (auto_l2_ctrls_ctrl_in_a_ready_0), .auto_ctrls_ctrl_in_a_valid (auto_l2_ctrls_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_opcode (auto_l2_ctrls_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_param (auto_l2_ctrls_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_size (auto_l2_ctrls_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_source (auto_l2_ctrls_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_address (auto_l2_ctrls_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_mask (auto_l2_ctrls_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_data (auto_l2_ctrls_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_corrupt (auto_l2_ctrls_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_d_ready (auto_l2_ctrls_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_d_valid (auto_l2_ctrls_ctrl_in_d_valid_0), .auto_ctrls_ctrl_in_d_bits_opcode (auto_l2_ctrls_ctrl_in_d_bits_opcode_0), .auto_ctrls_ctrl_in_d_bits_size (auto_l2_ctrls_ctrl_in_d_bits_size_0), .auto_ctrls_ctrl_in_d_bits_source (auto_l2_ctrls_ctrl_in_d_bits_source_0), .auto_ctrls_ctrl_in_d_bits_data (auto_l2_ctrls_ctrl_in_d_bits_data_0), .auto_in_a_ready (_l2_auto_in_a_ready), .auto_in_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid), // @[Parameters.scala:56:69] .auto_in_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode), // @[Parameters.scala:56:69] .auto_in_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param), // @[Parameters.scala:56:69] .auto_in_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size), // @[Parameters.scala:56:69] .auto_in_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source), // @[Parameters.scala:56:69] .auto_in_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address), // @[Parameters.scala:56:69] .auto_in_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask), // @[Parameters.scala:56:69] .auto_in_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data), // @[Parameters.scala:56:69] .auto_in_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready), // @[Parameters.scala:56:69] .auto_in_b_valid (_l2_auto_in_b_valid), .auto_in_b_bits_param (_l2_auto_in_b_bits_param), .auto_in_b_bits_source (_l2_auto_in_b_bits_source), .auto_in_b_bits_address (_l2_auto_in_b_bits_address), .auto_in_c_ready (_l2_auto_in_c_ready), .auto_in_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid), // @[Parameters.scala:56:69] .auto_in_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode), // @[Parameters.scala:56:69] .auto_in_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param), // @[Parameters.scala:56:69] .auto_in_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size), // @[Parameters.scala:56:69] .auto_in_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source), // @[Parameters.scala:56:69] .auto_in_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address), // @[Parameters.scala:56:69] .auto_in_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data), // @[Parameters.scala:56:69] .auto_in_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready), // @[Parameters.scala:56:69] .auto_in_d_valid (_l2_auto_in_d_valid), .auto_in_d_bits_opcode (_l2_auto_in_d_bits_opcode), .auto_in_d_bits_param (_l2_auto_in_d_bits_param), .auto_in_d_bits_size (_l2_auto_in_d_bits_size), .auto_in_d_bits_source (_l2_auto_in_d_bits_source), .auto_in_d_bits_sink (_l2_auto_in_d_bits_sink), .auto_in_d_bits_denied (_l2_auto_in_d_bits_denied), .auto_in_d_bits_data (_l2_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_l2_auto_in_d_bits_corrupt), .auto_in_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid), // @[Parameters.scala:56:69] .auto_in_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink), // @[Parameters.scala:56:69] .auto_out_a_ready (InclusiveCache_outer_TLBuffer_auto_in_a_ready), // @[Buffer.scala:40:9] .auto_out_a_valid (InclusiveCache_outer_TLBuffer_auto_in_a_valid), .auto_out_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode), .auto_out_a_bits_param (InclusiveCache_outer_TLBuffer_auto_in_a_bits_param), .auto_out_a_bits_size (InclusiveCache_outer_TLBuffer_auto_in_a_bits_size), .auto_out_a_bits_source (InclusiveCache_outer_TLBuffer_auto_in_a_bits_source), .auto_out_a_bits_address (InclusiveCache_outer_TLBuffer_auto_in_a_bits_address), .auto_out_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask), .auto_out_a_bits_data (InclusiveCache_outer_TLBuffer_auto_in_a_bits_data), .auto_out_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt), .auto_out_c_ready (InclusiveCache_outer_TLBuffer_auto_in_c_ready), // @[Buffer.scala:40:9] .auto_out_c_valid (InclusiveCache_outer_TLBuffer_auto_in_c_valid), .auto_out_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode), .auto_out_c_bits_param (InclusiveCache_outer_TLBuffer_auto_in_c_bits_param), .auto_out_c_bits_size (InclusiveCache_outer_TLBuffer_auto_in_c_bits_size), .auto_out_c_bits_source (InclusiveCache_outer_TLBuffer_auto_in_c_bits_source), .auto_out_c_bits_address (InclusiveCache_outer_TLBuffer_auto_in_c_bits_address), .auto_out_c_bits_data (InclusiveCache_outer_TLBuffer_auto_in_c_bits_data), .auto_out_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt), .auto_out_d_ready (InclusiveCache_outer_TLBuffer_auto_in_d_ready), .auto_out_d_valid (InclusiveCache_outer_TLBuffer_auto_in_d_valid), // @[Buffer.scala:40:9] .auto_out_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode), // @[Buffer.scala:40:9] .auto_out_d_bits_param (InclusiveCache_outer_TLBuffer_auto_in_d_bits_param), // @[Buffer.scala:40:9] .auto_out_d_bits_size (InclusiveCache_outer_TLBuffer_auto_in_d_bits_size), // @[Buffer.scala:40:9] .auto_out_d_bits_source (InclusiveCache_outer_TLBuffer_auto_in_d_bits_source), // @[Buffer.scala:40:9] .auto_out_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink), // @[Buffer.scala:40:9] .auto_out_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied), // @[Buffer.scala:40:9] .auto_out_d_bits_data (InclusiveCache_outer_TLBuffer_auto_in_d_bits_data), // @[Buffer.scala:40:9] .auto_out_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt), // @[Buffer.scala:40:9] .auto_out_e_valid (InclusiveCache_outer_TLBuffer_auto_in_e_valid), .auto_out_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink) ); // @[Configs.scala:93:24] TLBuffer_a32d128s7k4z3c InclusiveCache_inner_TLBuffer ( // @[Parameters.scala:56:69] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (filter_auto_anon_out_a_ready), .auto_in_a_valid (filter_auto_anon_out_a_valid), // @[Filter.scala:60:9] .auto_in_a_bits_opcode (filter_auto_anon_out_a_bits_opcode), // @[Filter.scala:60:9] .auto_in_a_bits_param (filter_auto_anon_out_a_bits_param), // @[Filter.scala:60:9] .auto_in_a_bits_size (filter_auto_anon_out_a_bits_size), // @[Filter.scala:60:9] .auto_in_a_bits_source (filter_auto_anon_out_a_bits_source), // @[Filter.scala:60:9] .auto_in_a_bits_address (filter_auto_anon_out_a_bits_address), // @[Filter.scala:60:9] .auto_in_a_bits_mask (filter_auto_anon_out_a_bits_mask), // @[Filter.scala:60:9] .auto_in_a_bits_data (filter_auto_anon_out_a_bits_data), // @[Filter.scala:60:9] .auto_in_a_bits_corrupt (filter_auto_anon_out_a_bits_corrupt), // @[Filter.scala:60:9] .auto_in_b_ready (filter_auto_anon_out_b_ready), // @[Filter.scala:60:9] .auto_in_b_valid (filter_auto_anon_out_b_valid), .auto_in_b_bits_param (filter_auto_anon_out_b_bits_param), .auto_in_b_bits_source (filter_auto_anon_out_b_bits_source), .auto_in_b_bits_address (filter_auto_anon_out_b_bits_address), .auto_in_c_ready (filter_auto_anon_out_c_ready), .auto_in_c_valid (filter_auto_anon_out_c_valid), // @[Filter.scala:60:9] .auto_in_c_bits_opcode (filter_auto_anon_out_c_bits_opcode), // @[Filter.scala:60:9] .auto_in_c_bits_param (filter_auto_anon_out_c_bits_param), // @[Filter.scala:60:9] .auto_in_c_bits_size (filter_auto_anon_out_c_bits_size), // @[Filter.scala:60:9] .auto_in_c_bits_source (filter_auto_anon_out_c_bits_source), // @[Filter.scala:60:9] .auto_in_c_bits_address (filter_auto_anon_out_c_bits_address), // @[Filter.scala:60:9] .auto_in_c_bits_data (filter_auto_anon_out_c_bits_data), // @[Filter.scala:60:9] .auto_in_c_bits_corrupt (filter_auto_anon_out_c_bits_corrupt), // @[Filter.scala:60:9] .auto_in_d_ready (filter_auto_anon_out_d_ready), // @[Filter.scala:60:9] .auto_in_d_valid (filter_auto_anon_out_d_valid), .auto_in_d_bits_opcode (filter_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (filter_auto_anon_out_d_bits_param), .auto_in_d_bits_size (filter_auto_anon_out_d_bits_size), .auto_in_d_bits_source (filter_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (filter_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (filter_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (filter_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (filter_auto_anon_out_d_bits_corrupt), .auto_in_e_valid (filter_auto_anon_out_e_valid), // @[Filter.scala:60:9] .auto_in_e_bits_sink (filter_auto_anon_out_e_bits_sink), // @[Filter.scala:60:9] .auto_out_a_ready (_l2_auto_in_a_ready), // @[Configs.scala:93:24] .auto_out_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid), .auto_out_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode), .auto_out_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param), .auto_out_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size), .auto_out_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source), .auto_out_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address), .auto_out_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask), .auto_out_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt), .auto_out_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready), .auto_out_b_valid (_l2_auto_in_b_valid), // @[Configs.scala:93:24] .auto_out_b_bits_param (_l2_auto_in_b_bits_param), // @[Configs.scala:93:24] .auto_out_b_bits_source (_l2_auto_in_b_bits_source), // @[Configs.scala:93:24] .auto_out_b_bits_address (_l2_auto_in_b_bits_address), // @[Configs.scala:93:24] .auto_out_c_ready (_l2_auto_in_c_ready), // @[Configs.scala:93:24] .auto_out_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid), .auto_out_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode), .auto_out_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param), .auto_out_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size), .auto_out_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source), .auto_out_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address), .auto_out_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data), .auto_out_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt), .auto_out_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready), .auto_out_d_valid (_l2_auto_in_d_valid), // @[Configs.scala:93:24] .auto_out_d_bits_opcode (_l2_auto_in_d_bits_opcode), // @[Configs.scala:93:24] .auto_out_d_bits_param (_l2_auto_in_d_bits_param), // @[Configs.scala:93:24] .auto_out_d_bits_size (_l2_auto_in_d_bits_size), // @[Configs.scala:93:24] .auto_out_d_bits_source (_l2_auto_in_d_bits_source), // @[Configs.scala:93:24] .auto_out_d_bits_sink (_l2_auto_in_d_bits_sink), // @[Configs.scala:93:24] .auto_out_d_bits_denied (_l2_auto_in_d_bits_denied), // @[Configs.scala:93:24] .auto_out_d_bits_data (_l2_auto_in_d_bits_data), // @[Configs.scala:93:24] .auto_out_d_bits_corrupt (_l2_auto_in_d_bits_corrupt), // @[Configs.scala:93:24] .auto_out_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid), .auto_out_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink) ); // @[Parameters.scala:56:69] TLCacheCork cork ( // @[Configs.scala:120:26] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (InclusiveCache_outer_TLBuffer_auto_out_a_ready), .auto_in_a_valid (InclusiveCache_outer_TLBuffer_auto_out_a_valid), // @[Buffer.scala:40:9] .auto_in_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode), // @[Buffer.scala:40:9] .auto_in_a_bits_param (InclusiveCache_outer_TLBuffer_auto_out_a_bits_param), // @[Buffer.scala:40:9] .auto_in_a_bits_size (InclusiveCache_outer_TLBuffer_auto_out_a_bits_size), // @[Buffer.scala:40:9] .auto_in_a_bits_source (InclusiveCache_outer_TLBuffer_auto_out_a_bits_source), // @[Buffer.scala:40:9] .auto_in_a_bits_address (InclusiveCache_outer_TLBuffer_auto_out_a_bits_address), // @[Buffer.scala:40:9] .auto_in_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask), // @[Buffer.scala:40:9] .auto_in_a_bits_data (InclusiveCache_outer_TLBuffer_auto_out_a_bits_data), // @[Buffer.scala:40:9] .auto_in_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9] .auto_in_c_ready (InclusiveCache_outer_TLBuffer_auto_out_c_ready), .auto_in_c_valid (InclusiveCache_outer_TLBuffer_auto_out_c_valid), // @[Buffer.scala:40:9] .auto_in_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode), // @[Buffer.scala:40:9] .auto_in_c_bits_param (InclusiveCache_outer_TLBuffer_auto_out_c_bits_param), // @[Buffer.scala:40:9] .auto_in_c_bits_size (InclusiveCache_outer_TLBuffer_auto_out_c_bits_size), // @[Buffer.scala:40:9] .auto_in_c_bits_source (InclusiveCache_outer_TLBuffer_auto_out_c_bits_source), // @[Buffer.scala:40:9] .auto_in_c_bits_address (InclusiveCache_outer_TLBuffer_auto_out_c_bits_address), // @[Buffer.scala:40:9] .auto_in_c_bits_data (InclusiveCache_outer_TLBuffer_auto_out_c_bits_data), // @[Buffer.scala:40:9] .auto_in_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt), // @[Buffer.scala:40:9] .auto_in_d_ready (InclusiveCache_outer_TLBuffer_auto_out_d_ready), // @[Buffer.scala:40:9] .auto_in_d_valid (InclusiveCache_outer_TLBuffer_auto_out_d_valid), .auto_in_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode), .auto_in_d_bits_param (InclusiveCache_outer_TLBuffer_auto_out_d_bits_param), .auto_in_d_bits_size (InclusiveCache_outer_TLBuffer_auto_out_d_bits_size), .auto_in_d_bits_source (InclusiveCache_outer_TLBuffer_auto_out_d_bits_source), .auto_in_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink), .auto_in_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied), .auto_in_d_bits_data (InclusiveCache_outer_TLBuffer_auto_out_d_bits_data), .auto_in_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt), .auto_in_e_valid (InclusiveCache_outer_TLBuffer_auto_out_e_valid), // @[Buffer.scala:40:9] .auto_in_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink), // @[Buffer.scala:40:9] .auto_out_a_ready (_binder_auto_in_a_ready), // @[BankBinder.scala:71:28] .auto_out_a_valid (_cork_auto_out_a_valid), .auto_out_a_bits_opcode (_cork_auto_out_a_bits_opcode), .auto_out_a_bits_param (_cork_auto_out_a_bits_param), .auto_out_a_bits_size (_cork_auto_out_a_bits_size), .auto_out_a_bits_source (_cork_auto_out_a_bits_source), .auto_out_a_bits_address (_cork_auto_out_a_bits_address), .auto_out_a_bits_mask (_cork_auto_out_a_bits_mask), .auto_out_a_bits_data (_cork_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_cork_auto_out_a_bits_corrupt), .auto_out_d_ready (_cork_auto_out_d_ready), .auto_out_d_valid (_binder_auto_in_d_valid), // @[BankBinder.scala:71:28] .auto_out_d_bits_opcode (_binder_auto_in_d_bits_opcode), // @[BankBinder.scala:71:28] .auto_out_d_bits_param (_binder_auto_in_d_bits_param), // @[BankBinder.scala:71:28] .auto_out_d_bits_size (_binder_auto_in_d_bits_size), // @[BankBinder.scala:71:28] .auto_out_d_bits_source (_binder_auto_in_d_bits_source), // @[BankBinder.scala:71:28] .auto_out_d_bits_sink (_binder_auto_in_d_bits_sink), // @[BankBinder.scala:71:28] .auto_out_d_bits_denied (_binder_auto_in_d_bits_denied), // @[BankBinder.scala:71:28] .auto_out_d_bits_data (_binder_auto_in_d_bits_data), // @[BankBinder.scala:71:28] .auto_out_d_bits_corrupt (_binder_auto_in_d_bits_corrupt) // @[BankBinder.scala:71:28] ); // @[Configs.scala:120:26] BankBinder binder ( // @[BankBinder.scala:71:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_binder_auto_in_a_ready), .auto_in_a_valid (_cork_auto_out_a_valid), // @[Configs.scala:120:26] .auto_in_a_bits_opcode (_cork_auto_out_a_bits_opcode), // @[Configs.scala:120:26] .auto_in_a_bits_param (_cork_auto_out_a_bits_param), // @[Configs.scala:120:26] .auto_in_a_bits_size (_cork_auto_out_a_bits_size), // @[Configs.scala:120:26] .auto_in_a_bits_source (_cork_auto_out_a_bits_source), // @[Configs.scala:120:26] .auto_in_a_bits_address (_cork_auto_out_a_bits_address), // @[Configs.scala:120:26] .auto_in_a_bits_mask (_cork_auto_out_a_bits_mask), // @[Configs.scala:120:26] .auto_in_a_bits_data (_cork_auto_out_a_bits_data), // @[Configs.scala:120:26] .auto_in_a_bits_corrupt (_cork_auto_out_a_bits_corrupt), // @[Configs.scala:120:26] .auto_in_d_ready (_cork_auto_out_d_ready), // @[Configs.scala:120:26] .auto_in_d_valid (_binder_auto_in_d_valid), .auto_in_d_bits_opcode (_binder_auto_in_d_bits_opcode), .auto_in_d_bits_param (_binder_auto_in_d_bits_param), .auto_in_d_bits_size (_binder_auto_in_d_bits_size), .auto_in_d_bits_source (_binder_auto_in_d_bits_source), .auto_in_d_bits_sink (_binder_auto_in_d_bits_sink), .auto_in_d_bits_denied (_binder_auto_in_d_bits_denied), .auto_in_d_bits_data (_binder_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_binder_auto_in_d_bits_corrupt), .auto_out_a_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7] .auto_out_a_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid), .auto_out_a_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode), .auto_out_a_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param), .auto_out_a_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size), .auto_out_a_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source), .auto_out_a_bits_address (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address), .auto_out_a_bits_mask (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask), .auto_out_a_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data), .auto_out_a_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt), .auto_out_d_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready), .auto_out_d_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_sink (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_denied (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyModuleImp.scala:138:7] ); // @[BankBinder.scala:71:28] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_a_ready = auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_b_valid = auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_b_bits_param = auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_b_bits_source = auto_coherent_jbar_anon_in_b_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_b_bits_address = auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_c_ready = auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_valid = auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_opcode = auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_param = auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_size = auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_source = auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_sink = auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_denied = auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_data = auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_corrupt = auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_a_ready = auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_valid = auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_opcode = auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_size = auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_source = auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_data = auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_253 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_253( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SinkC_6 : input clock : Clock input reset : Reset output io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}}, resp : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, set : UInt<11>, flip way : UInt<4>, bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, bs_dat : { data : UInt<128>}, flip rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, rel_beat : { data : UInt<128>, corrupt : UInt<1>}} inst c_q of Queue2_TLBundleC_a32d128s6k4z3c_6 connect c_q.clock, clock connect c_q.reset, reset connect c_q.io.enq.valid, io.c.valid connect c_q.io.enq.bits.corrupt, io.c.bits.corrupt connect c_q.io.enq.bits.data, io.c.bits.data connect c_q.io.enq.bits.address, io.c.bits.address connect c_q.io.enq.bits.source, io.c.bits.source connect c_q.io.enq.bits.size, io.c.bits.size connect c_q.io.enq.bits.param, io.c.bits.param connect c_q.io.enq.bits.opcode, io.c.bits.opcode connect io.c.ready, c_q.io.enq.ready node _offset_T = bits(c_q.io.deq.bits.address, 0, 0) node _offset_T_1 = bits(c_q.io.deq.bits.address, 1, 1) node _offset_T_2 = bits(c_q.io.deq.bits.address, 2, 2) node _offset_T_3 = bits(c_q.io.deq.bits.address, 3, 3) node _offset_T_4 = bits(c_q.io.deq.bits.address, 4, 4) node _offset_T_5 = bits(c_q.io.deq.bits.address, 5, 5) node _offset_T_6 = bits(c_q.io.deq.bits.address, 9, 9) node _offset_T_7 = bits(c_q.io.deq.bits.address, 10, 10) node _offset_T_8 = bits(c_q.io.deq.bits.address, 11, 11) node _offset_T_9 = bits(c_q.io.deq.bits.address, 12, 12) node _offset_T_10 = bits(c_q.io.deq.bits.address, 13, 13) node _offset_T_11 = bits(c_q.io.deq.bits.address, 14, 14) node _offset_T_12 = bits(c_q.io.deq.bits.address, 15, 15) node _offset_T_13 = bits(c_q.io.deq.bits.address, 16, 16) node _offset_T_14 = bits(c_q.io.deq.bits.address, 17, 17) node _offset_T_15 = bits(c_q.io.deq.bits.address, 18, 18) node _offset_T_16 = bits(c_q.io.deq.bits.address, 19, 19) node _offset_T_17 = bits(c_q.io.deq.bits.address, 20, 20) node _offset_T_18 = bits(c_q.io.deq.bits.address, 21, 21) node _offset_T_19 = bits(c_q.io.deq.bits.address, 22, 22) node _offset_T_20 = bits(c_q.io.deq.bits.address, 23, 23) node _offset_T_21 = bits(c_q.io.deq.bits.address, 24, 24) node _offset_T_22 = bits(c_q.io.deq.bits.address, 25, 25) node _offset_T_23 = bits(c_q.io.deq.bits.address, 26, 26) node _offset_T_24 = bits(c_q.io.deq.bits.address, 27, 27) node _offset_T_25 = bits(c_q.io.deq.bits.address, 31, 31) node offset_lo_lo_lo_hi = cat(_offset_T_2, _offset_T_1) node offset_lo_lo_lo = cat(offset_lo_lo_lo_hi, _offset_T) node offset_lo_lo_hi_hi = cat(_offset_T_5, _offset_T_4) node offset_lo_lo_hi = cat(offset_lo_lo_hi_hi, _offset_T_3) node offset_lo_lo = cat(offset_lo_lo_hi, offset_lo_lo_lo) node offset_lo_hi_lo_hi = cat(_offset_T_8, _offset_T_7) node offset_lo_hi_lo = cat(offset_lo_hi_lo_hi, _offset_T_6) node offset_lo_hi_hi_lo = cat(_offset_T_10, _offset_T_9) node offset_lo_hi_hi_hi = cat(_offset_T_12, _offset_T_11) node offset_lo_hi_hi = cat(offset_lo_hi_hi_hi, offset_lo_hi_hi_lo) node offset_lo_hi = cat(offset_lo_hi_hi, offset_lo_hi_lo) node offset_lo = cat(offset_lo_hi, offset_lo_lo) node offset_hi_lo_lo_hi = cat(_offset_T_15, _offset_T_14) node offset_hi_lo_lo = cat(offset_hi_lo_lo_hi, _offset_T_13) node offset_hi_lo_hi_hi = cat(_offset_T_18, _offset_T_17) node offset_hi_lo_hi = cat(offset_hi_lo_hi_hi, _offset_T_16) node offset_hi_lo = cat(offset_hi_lo_hi, offset_hi_lo_lo) node offset_hi_hi_lo_hi = cat(_offset_T_21, _offset_T_20) node offset_hi_hi_lo = cat(offset_hi_hi_lo_hi, _offset_T_19) node offset_hi_hi_hi_lo = cat(_offset_T_23, _offset_T_22) node offset_hi_hi_hi_hi = cat(_offset_T_25, _offset_T_24) node offset_hi_hi_hi = cat(offset_hi_hi_hi_hi, offset_hi_hi_hi_lo) node offset_hi_hi = cat(offset_hi_hi_hi, offset_hi_hi_lo) node offset_hi = cat(offset_hi_hi, offset_hi_lo) node offset = cat(offset_hi, offset_lo) node set = shr(offset, 6) node tag = shr(set, 11) node tag_1 = bits(tag, 8, 0) node set_1 = bits(set, 10, 0) node offset_1 = bits(offset, 5, 0) node _T = and(c_q.io.deq.ready, c_q.io.deq.valid) node _r_beats1_decode_T = dshl(UInt<6>(0h3f), c_q.io.deq.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 5, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 4) node r_beats1_opdata = bits(c_q.io.deq.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node last = or(_r_last_T, _r_last_T_1) node r_3 = and(last, _T) node _r_count_T = not(r_counter1) node beat = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(first, r_beats1, r_counter1) connect r_counter, _r_counter_T node hasData = bits(c_q.io.deq.bits.opcode, 0, 0) node _raw_resp_T = eq(c_q.io.deq.bits.opcode, UInt<3>(0h4)) node _raw_resp_T_1 = eq(c_q.io.deq.bits.opcode, UInt<3>(0h5)) node raw_resp = or(_raw_resp_T, _raw_resp_T_1) reg resp_r : UInt<1>, clock when c_q.io.deq.valid : connect resp_r, raw_resp node resp = mux(c_q.io.deq.valid, raw_resp, resp_r) node _T_1 = and(c_q.io.deq.valid, c_q.io.deq.bits.corrupt) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unavailable\n at SinkC.scala:90 assert (!(c.valid && c.bits.corrupt), \"Data poisoning unavailable\")\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert reg io_set_r : UInt<11>, clock when c_q.io.deq.valid : connect io_set_r, set_1 node _io_set_T = mux(c_q.io.deq.valid, set_1, io_set_r) connect io.set, _io_set_T wire bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}} inst io_bs_adr_q of Queue1_BankedStoreInnerAddress_6 connect io_bs_adr_q.clock, clock connect io_bs_adr_q.reset, reset connect io_bs_adr_q.io.enq.valid, bs_adr.valid connect io_bs_adr_q.io.enq.bits.mask, bs_adr.bits.mask connect io_bs_adr_q.io.enq.bits.beat, bs_adr.bits.beat connect io_bs_adr_q.io.enq.bits.set, bs_adr.bits.set connect io_bs_adr_q.io.enq.bits.way, bs_adr.bits.way connect io_bs_adr_q.io.enq.bits.noop, bs_adr.bits.noop connect bs_adr.ready, io_bs_adr_q.io.enq.ready connect io.bs_adr.bits, io_bs_adr_q.io.deq.bits connect io.bs_adr.valid, io_bs_adr_q.io.deq.valid connect io_bs_adr_q.io.deq.ready, io.bs_adr.ready node _io_bs_dat_data_T = and(bs_adr.ready, bs_adr.valid) reg io_bs_dat_data_r : UInt<128>, clock when _io_bs_dat_data_T : connect io_bs_dat_data_r, c_q.io.deq.bits.data connect io.bs_dat.data, io_bs_dat_data_r node _bs_adr_valid_T = eq(first, UInt<1>(0h0)) node _bs_adr_valid_T_1 = and(c_q.io.deq.valid, hasData) node _bs_adr_valid_T_2 = or(_bs_adr_valid_T, _bs_adr_valid_T_1) node _bs_adr_valid_T_3 = and(resp, _bs_adr_valid_T_2) connect bs_adr.valid, _bs_adr_valid_T_3 node _bs_adr_bits_noop_T = eq(c_q.io.deq.valid, UInt<1>(0h0)) connect bs_adr.bits.noop, _bs_adr_bits_noop_T connect bs_adr.bits.way, io.way connect bs_adr.bits.set, io.set node _bs_adr_bits_beat_T = add(beat, bs_adr.ready) node _bs_adr_bits_beat_T_1 = tail(_bs_adr_bits_beat_T, 1) reg bs_adr_bits_beat_r : UInt<2>, clock when c_q.io.deq.valid : connect bs_adr_bits_beat_r, _bs_adr_bits_beat_T_1 node _bs_adr_bits_beat_T_2 = mux(c_q.io.deq.valid, beat, bs_adr_bits_beat_r) connect bs_adr.bits.beat, _bs_adr_bits_beat_T_2 node _bs_adr_bits_mask_T = not(UInt<2>(0h0)) connect bs_adr.bits.mask, _bs_adr_bits_mask_T node _T_6 = eq(bs_adr.ready, UInt<1>(0h0)) node _T_7 = and(bs_adr.valid, _T_6) node _io_resp_valid_T = and(resp, c_q.io.deq.valid) node _io_resp_valid_T_1 = or(first, last) node _io_resp_valid_T_2 = and(_io_resp_valid_T, _io_resp_valid_T_1) node _io_resp_valid_T_3 = eq(hasData, UInt<1>(0h0)) node _io_resp_valid_T_4 = or(_io_resp_valid_T_3, bs_adr.ready) node _io_resp_valid_T_5 = and(_io_resp_valid_T_2, _io_resp_valid_T_4) connect io.resp.valid, _io_resp_valid_T_5 connect io.resp.bits.last, last connect io.resp.bits.set, set_1 connect io.resp.bits.tag, tag_1 connect io.resp.bits.source, c_q.io.deq.bits.source connect io.resp.bits.param, c_q.io.deq.bits.param connect io.resp.bits.data, hasData inst putbuffer of ListBuffer_PutBufferCEntry_q2_e8_6 connect putbuffer.clock, clock connect putbuffer.reset, reset regreset lists : UInt<2>, clock, reset, UInt<2>(0h0) wire lists_set : UInt<2> connect lists_set, UInt<2>(0h0) wire lists_clr : UInt<2> connect lists_clr, UInt<2>(0h0) node _lists_T = or(lists, lists_set) node _lists_T_1 = not(lists_clr) node _lists_T_2 = and(_lists_T, _lists_T_1) connect lists, _lists_T_2 node _free_T = andr(lists) node free = eq(_free_T, UInt<1>(0h0)) node _freeOH_T = not(lists) node _freeOH_T_1 = shl(_freeOH_T, 1) node _freeOH_T_2 = bits(_freeOH_T_1, 1, 0) node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2) node _freeOH_T_4 = bits(_freeOH_T_3, 1, 0) node _freeOH_T_5 = shl(_freeOH_T_4, 1) node _freeOH_T_6 = not(_freeOH_T_5) node _freeOH_T_7 = not(lists) node freeOH = and(_freeOH_T_6, _freeOH_T_7) node freeIdx_hi = bits(freeOH, 2, 2) node freeIdx_lo = bits(freeOH, 1, 0) node _freeIdx_T = orr(freeIdx_hi) node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo) node _freeIdx_T_2 = bits(_freeIdx_T_1, 1, 1) node freeIdx = cat(_freeIdx_T, _freeIdx_T_2) node _req_block_T = eq(io.req.ready, UInt<1>(0h0)) node req_block = and(first, _req_block_T) node _buf_block_T = eq(putbuffer.io.push.ready, UInt<1>(0h0)) node buf_block = and(hasData, _buf_block_T) node _set_block_T = and(hasData, first) node _set_block_T_1 = eq(free, UInt<1>(0h0)) node set_block = and(_set_block_T, _set_block_T_1) node _T_8 = eq(raw_resp, UInt<1>(0h0)) node _T_9 = and(c_q.io.deq.valid, _T_8) node _T_10 = and(_T_9, req_block) node _T_11 = eq(raw_resp, UInt<1>(0h0)) node _T_12 = and(c_q.io.deq.valid, _T_11) node _T_13 = and(_T_12, buf_block) node _T_14 = eq(raw_resp, UInt<1>(0h0)) node _T_15 = and(c_q.io.deq.valid, _T_14) node _T_16 = and(_T_15, set_block) node _q_io_deq_ready_T = eq(hasData, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(_q_io_deq_ready_T, bs_adr.ready) node _q_io_deq_ready_T_2 = eq(req_block, UInt<1>(0h0)) node _q_io_deq_ready_T_3 = eq(buf_block, UInt<1>(0h0)) node _q_io_deq_ready_T_4 = and(_q_io_deq_ready_T_2, _q_io_deq_ready_T_3) node _q_io_deq_ready_T_5 = eq(set_block, UInt<1>(0h0)) node _q_io_deq_ready_T_6 = and(_q_io_deq_ready_T_4, _q_io_deq_ready_T_5) node _q_io_deq_ready_T_7 = mux(raw_resp, _q_io_deq_ready_T_1, _q_io_deq_ready_T_6) connect c_q.io.deq.ready, _q_io_deq_ready_T_7 node _io_req_valid_T = eq(resp, UInt<1>(0h0)) node _io_req_valid_T_1 = and(_io_req_valid_T, c_q.io.deq.valid) node _io_req_valid_T_2 = and(_io_req_valid_T_1, first) node _io_req_valid_T_3 = eq(buf_block, UInt<1>(0h0)) node _io_req_valid_T_4 = and(_io_req_valid_T_2, _io_req_valid_T_3) node _io_req_valid_T_5 = eq(set_block, UInt<1>(0h0)) node _io_req_valid_T_6 = and(_io_req_valid_T_4, _io_req_valid_T_5) connect io.req.valid, _io_req_valid_T_6 node _putbuffer_io_push_valid_T = eq(resp, UInt<1>(0h0)) node _putbuffer_io_push_valid_T_1 = and(_putbuffer_io_push_valid_T, c_q.io.deq.valid) node _putbuffer_io_push_valid_T_2 = and(_putbuffer_io_push_valid_T_1, hasData) node _putbuffer_io_push_valid_T_3 = eq(req_block, UInt<1>(0h0)) node _putbuffer_io_push_valid_T_4 = and(_putbuffer_io_push_valid_T_2, _putbuffer_io_push_valid_T_3) node _putbuffer_io_push_valid_T_5 = eq(set_block, UInt<1>(0h0)) node _putbuffer_io_push_valid_T_6 = and(_putbuffer_io_push_valid_T_4, _putbuffer_io_push_valid_T_5) connect putbuffer.io.push.valid, _putbuffer_io_push_valid_T_6 node _T_17 = eq(resp, UInt<1>(0h0)) node _T_18 = and(_T_17, c_q.io.deq.valid) node _T_19 = and(_T_18, first) node _T_20 = and(_T_19, hasData) node _T_21 = eq(req_block, UInt<1>(0h0)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(buf_block, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) when _T_24 : connect lists_set, freeOH reg put_r : UInt<2>, clock when first : connect put_r, freeIdx node put = mux(first, freeIdx, put_r) wire _WIRE : UInt<1>[3] connect _WIRE[0], UInt<1>(0h0) connect _WIRE[1], UInt<1>(0h0) connect _WIRE[2], UInt<1>(0h1) connect io.req.bits.prio, _WIRE connect io.req.bits.control, UInt<1>(0h0) connect io.req.bits.opcode, c_q.io.deq.bits.opcode connect io.req.bits.param, c_q.io.deq.bits.param connect io.req.bits.size, c_q.io.deq.bits.size connect io.req.bits.source, c_q.io.deq.bits.source connect io.req.bits.offset, offset_1 connect io.req.bits.set, set_1 connect io.req.bits.tag, tag_1 connect io.req.bits.put, put connect putbuffer.io.push.bits.index, put connect putbuffer.io.push.bits.data.data, c_q.io.deq.bits.data connect putbuffer.io.push.bits.data.corrupt, c_q.io.deq.bits.corrupt connect putbuffer.io.pop.bits, io.rel_pop.bits.index node _putbuffer_io_pop_valid_T = and(io.rel_pop.ready, io.rel_pop.valid) connect putbuffer.io.pop.valid, _putbuffer_io_pop_valid_T node _io_rel_pop_ready_T = bits(io.rel_pop.bits.index, 0, 0) node _io_rel_pop_ready_T_1 = dshr(putbuffer.io.valid, _io_rel_pop_ready_T) node _io_rel_pop_ready_T_2 = bits(_io_rel_pop_ready_T_1, 0, 0) connect io.rel_pop.ready, _io_rel_pop_ready_T_2 connect io.rel_beat, putbuffer.io.data node _T_25 = and(io.rel_pop.ready, io.rel_pop.valid) node _T_26 = and(_T_25, io.rel_pop.bits.last) when _T_26 : node lists_clr_shiftAmount = bits(io.rel_pop.bits.index, 0, 0) node _lists_clr_T = dshl(UInt<1>(0h1), lists_clr_shiftAmount) node _lists_clr_T_1 = bits(_lists_clr_T, 1, 0) connect lists_clr, _lists_clr_T_1
module SinkC_6( // @[SinkC.scala:41:7] input clock, // @[SinkC.scala:41:7] input reset, // @[SinkC.scala:41:7] input io_req_ready, // @[SinkC.scala:43:14] output io_req_valid, // @[SinkC.scala:43:14] output [2:0] io_req_bits_opcode, // @[SinkC.scala:43:14] output [2:0] io_req_bits_param, // @[SinkC.scala:43:14] output [2:0] io_req_bits_size, // @[SinkC.scala:43:14] output [5:0] io_req_bits_source, // @[SinkC.scala:43:14] output [8:0] io_req_bits_tag, // @[SinkC.scala:43:14] output [5:0] io_req_bits_offset, // @[SinkC.scala:43:14] output [5:0] io_req_bits_put, // @[SinkC.scala:43:14] output [10:0] io_req_bits_set, // @[SinkC.scala:43:14] output io_resp_valid, // @[SinkC.scala:43:14] output io_resp_bits_last, // @[SinkC.scala:43:14] output [10:0] io_resp_bits_set, // @[SinkC.scala:43:14] output [8:0] io_resp_bits_tag, // @[SinkC.scala:43:14] output [5:0] io_resp_bits_source, // @[SinkC.scala:43:14] output [2:0] io_resp_bits_param, // @[SinkC.scala:43:14] output io_resp_bits_data, // @[SinkC.scala:43:14] output io_c_ready, // @[SinkC.scala:43:14] input io_c_valid, // @[SinkC.scala:43:14] input [2:0] io_c_bits_opcode, // @[SinkC.scala:43:14] input [2:0] io_c_bits_param, // @[SinkC.scala:43:14] input [2:0] io_c_bits_size, // @[SinkC.scala:43:14] input [5:0] io_c_bits_source, // @[SinkC.scala:43:14] input [31:0] io_c_bits_address, // @[SinkC.scala:43:14] input [127:0] io_c_bits_data, // @[SinkC.scala:43:14] input io_c_bits_corrupt, // @[SinkC.scala:43:14] output [10:0] io_set, // @[SinkC.scala:43:14] input [3:0] io_way, // @[SinkC.scala:43:14] input io_bs_adr_ready, // @[SinkC.scala:43:14] output io_bs_adr_valid, // @[SinkC.scala:43:14] output io_bs_adr_bits_noop, // @[SinkC.scala:43:14] output [3:0] io_bs_adr_bits_way, // @[SinkC.scala:43:14] output [10:0] io_bs_adr_bits_set, // @[SinkC.scala:43:14] output [1:0] io_bs_adr_bits_beat, // @[SinkC.scala:43:14] output [1:0] io_bs_adr_bits_mask, // @[SinkC.scala:43:14] output [127:0] io_bs_dat_data, // @[SinkC.scala:43:14] output io_rel_pop_ready, // @[SinkC.scala:43:14] input io_rel_pop_valid, // @[SinkC.scala:43:14] input [5:0] io_rel_pop_bits_index, // @[SinkC.scala:43:14] input io_rel_pop_bits_last, // @[SinkC.scala:43:14] output [127:0] io_rel_beat_data, // @[SinkC.scala:43:14] output io_rel_beat_corrupt // @[SinkC.scala:43:14] ); wire [10:0] io_set_0; // @[SinkC.scala:41:7] wire _putbuffer_io_push_ready; // @[SinkC.scala:115:27] wire [1:0] _putbuffer_io_valid; // @[SinkC.scala:115:27] wire _c_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _c_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [2:0] _c_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [5:0] _c_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [31:0] _c_q_io_deq_bits_address; // @[Decoupled.scala:362:21] wire [127:0] _c_q_io_deq_bits_data; // @[Decoupled.scala:362:21] wire _c_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire io_req_ready_0 = io_req_ready; // @[SinkC.scala:41:7] wire io_c_valid_0 = io_c_valid; // @[SinkC.scala:41:7] wire [2:0] io_c_bits_opcode_0 = io_c_bits_opcode; // @[SinkC.scala:41:7] wire [2:0] io_c_bits_param_0 = io_c_bits_param; // @[SinkC.scala:41:7] wire [2:0] io_c_bits_size_0 = io_c_bits_size; // @[SinkC.scala:41:7] wire [5:0] io_c_bits_source_0 = io_c_bits_source; // @[SinkC.scala:41:7] wire [31:0] io_c_bits_address_0 = io_c_bits_address; // @[SinkC.scala:41:7] wire [127:0] io_c_bits_data_0 = io_c_bits_data; // @[SinkC.scala:41:7] wire io_c_bits_corrupt_0 = io_c_bits_corrupt; // @[SinkC.scala:41:7] wire [3:0] io_way_0 = io_way; // @[SinkC.scala:41:7] wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SinkC.scala:41:7] wire io_rel_pop_valid_0 = io_rel_pop_valid; // @[SinkC.scala:41:7] wire [5:0] io_rel_pop_bits_index_0 = io_rel_pop_bits_index; // @[SinkC.scala:41:7] wire io_rel_pop_bits_last_0 = io_rel_pop_bits_last; // @[SinkC.scala:41:7] wire io_req_bits_prio_0 = 1'h0; // @[SinkC.scala:41:7] wire io_req_bits_prio_1 = 1'h0; // @[SinkC.scala:41:7] wire io_req_bits_control = 1'h0; // @[SinkC.scala:41:7] wire io_req_bits_prio_2 = 1'h1; // @[SinkC.scala:41:7] wire [1:0] bs_adr_bits_mask = 2'h3; // @[SinkC.scala:96:22] wire [1:0] _bs_adr_bits_mask_T = 2'h3; // @[SinkC.scala:104:25] wire _io_req_valid_T_6; // @[SinkC.scala:136:61] wire [8:0] tag_1; // @[Parameters.scala:217:9] wire [5:0] offset_1; // @[Parameters.scala:217:50] wire [10:0] set_1; // @[Parameters.scala:217:28] wire _io_resp_valid_T_5; // @[SinkC.scala:107:57] wire last; // @[Edges.scala:232:33] wire hasData; // @[Edges.scala:102:36] wire [10:0] _io_set_T; // @[SinkC.scala:92:18] wire [10:0] bs_adr_bits_set = io_set_0; // @[SinkC.scala:41:7, :96:22] wire [3:0] bs_adr_bits_way = io_way_0; // @[SinkC.scala:41:7, :96:22] wire _io_rel_pop_ready_T_2; // @[SinkC.scala:160:43] wire [2:0] io_req_bits_opcode_0; // @[SinkC.scala:41:7] wire [2:0] io_req_bits_param_0; // @[SinkC.scala:41:7] wire [2:0] io_req_bits_size_0; // @[SinkC.scala:41:7] wire [5:0] io_req_bits_source_0; // @[SinkC.scala:41:7] wire [8:0] io_req_bits_tag_0; // @[SinkC.scala:41:7] wire [5:0] io_req_bits_offset_0; // @[SinkC.scala:41:7] wire [5:0] io_req_bits_put_0; // @[SinkC.scala:41:7] wire [10:0] io_req_bits_set_0; // @[SinkC.scala:41:7] wire io_req_valid_0; // @[SinkC.scala:41:7] wire io_resp_bits_last_0; // @[SinkC.scala:41:7] wire [10:0] io_resp_bits_set_0; // @[SinkC.scala:41:7] wire [8:0] io_resp_bits_tag_0; // @[SinkC.scala:41:7] wire [5:0] io_resp_bits_source_0; // @[SinkC.scala:41:7] wire [2:0] io_resp_bits_param_0; // @[SinkC.scala:41:7] wire io_resp_bits_data_0; // @[SinkC.scala:41:7] wire io_resp_valid_0; // @[SinkC.scala:41:7] wire io_c_ready_0; // @[SinkC.scala:41:7] wire io_bs_adr_bits_noop_0; // @[SinkC.scala:41:7] wire [3:0] io_bs_adr_bits_way_0; // @[SinkC.scala:41:7] wire [10:0] io_bs_adr_bits_set_0; // @[SinkC.scala:41:7] wire [1:0] io_bs_adr_bits_beat_0; // @[SinkC.scala:41:7] wire [1:0] io_bs_adr_bits_mask_0; // @[SinkC.scala:41:7] wire io_bs_adr_valid_0; // @[SinkC.scala:41:7] wire [127:0] io_bs_dat_data_0; // @[SinkC.scala:41:7] wire io_rel_pop_ready_0; // @[SinkC.scala:41:7] wire [127:0] io_rel_beat_data_0; // @[SinkC.scala:41:7] wire io_rel_beat_corrupt_0; // @[SinkC.scala:41:7] wire _offset_T = _c_q_io_deq_bits_address[0]; // @[Decoupled.scala:362:21] wire _offset_T_1 = _c_q_io_deq_bits_address[1]; // @[Decoupled.scala:362:21] wire _offset_T_2 = _c_q_io_deq_bits_address[2]; // @[Decoupled.scala:362:21] wire _offset_T_3 = _c_q_io_deq_bits_address[3]; // @[Decoupled.scala:362:21] wire _offset_T_4 = _c_q_io_deq_bits_address[4]; // @[Decoupled.scala:362:21] wire _offset_T_5 = _c_q_io_deq_bits_address[5]; // @[Decoupled.scala:362:21] wire _offset_T_6 = _c_q_io_deq_bits_address[9]; // @[Decoupled.scala:362:21] wire _offset_T_7 = _c_q_io_deq_bits_address[10]; // @[Decoupled.scala:362:21] wire _offset_T_8 = _c_q_io_deq_bits_address[11]; // @[Decoupled.scala:362:21] wire _offset_T_9 = _c_q_io_deq_bits_address[12]; // @[Decoupled.scala:362:21] wire _offset_T_10 = _c_q_io_deq_bits_address[13]; // @[Decoupled.scala:362:21] wire _offset_T_11 = _c_q_io_deq_bits_address[14]; // @[Decoupled.scala:362:21] wire _offset_T_12 = _c_q_io_deq_bits_address[15]; // @[Decoupled.scala:362:21] wire _offset_T_13 = _c_q_io_deq_bits_address[16]; // @[Decoupled.scala:362:21] wire _offset_T_14 = _c_q_io_deq_bits_address[17]; // @[Decoupled.scala:362:21] wire _offset_T_15 = _c_q_io_deq_bits_address[18]; // @[Decoupled.scala:362:21] wire _offset_T_16 = _c_q_io_deq_bits_address[19]; // @[Decoupled.scala:362:21] wire _offset_T_17 = _c_q_io_deq_bits_address[20]; // @[Decoupled.scala:362:21] wire _offset_T_18 = _c_q_io_deq_bits_address[21]; // @[Decoupled.scala:362:21] wire _offset_T_19 = _c_q_io_deq_bits_address[22]; // @[Decoupled.scala:362:21] wire _offset_T_20 = _c_q_io_deq_bits_address[23]; // @[Decoupled.scala:362:21] wire _offset_T_21 = _c_q_io_deq_bits_address[24]; // @[Decoupled.scala:362:21] wire _offset_T_22 = _c_q_io_deq_bits_address[25]; // @[Decoupled.scala:362:21] wire _offset_T_23 = _c_q_io_deq_bits_address[26]; // @[Decoupled.scala:362:21] wire _offset_T_24 = _c_q_io_deq_bits_address[27]; // @[Decoupled.scala:362:21] wire _offset_T_25 = _c_q_io_deq_bits_address[31]; // @[Decoupled.scala:362:21] wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_hi = {_offset_T_5, _offset_T_4}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, _offset_T_3}; // @[Parameters.scala:214:{21,47}] wire [5:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_lo_hi_lo_hi = {_offset_T_8, _offset_T_7}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_6}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_lo = {_offset_T_10, _offset_T_9}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_hi = {_offset_T_12, _offset_T_11}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21] wire [12:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_lo_lo_hi = {_offset_T_15, _offset_T_14}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_13}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_hi = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, _offset_T_16}; // @[Parameters.scala:214:{21,47}] wire [5:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_lo_hi = {_offset_T_21, _offset_T_20}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, _offset_T_19}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_lo = {_offset_T_23, _offset_T_22}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_hi = {_offset_T_25, _offset_T_24}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21] wire [12:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21] wire [25:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21] wire [19:0] set = offset[25:6]; // @[Parameters.scala:214:21, :215:22] wire [8:0] tag = set[19:11]; // @[Parameters.scala:215:22, :216:19] assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9] assign io_req_bits_tag_0 = tag_1; // @[SinkC.scala:41:7] assign io_resp_bits_tag_0 = tag_1; // @[SinkC.scala:41:7] assign set_1 = set[10:0]; // @[Parameters.scala:215:22, :217:28] assign io_req_bits_set_0 = set_1; // @[SinkC.scala:41:7] assign io_resp_bits_set_0 = set_1; // @[SinkC.scala:41:7] assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50] assign io_req_bits_offset_0 = offset_1; // @[SinkC.scala:41:7] wire _q_io_deq_ready_T_7; // @[SinkC.scala:134:19] wire _T = _q_io_deq_ready_T_7 & _c_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [12:0] _r_beats1_decode_T = 13'h3F << _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] r_beats1_decode = _r_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire r_beats1_opdata = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] assign hasData = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] wire [1:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] r_counter; // @[Edges.scala:229:27] wire [2:0] _r_counter1_T = {1'h0, r_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] r_counter1 = _r_counter1_T[1:0]; // @[Edges.scala:230:28] wire first = r_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] assign last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] assign io_resp_bits_last_0 = last; // @[Edges.scala:232:33] wire r_3 = last & _T; // @[Decoupled.scala:51:35] wire [1:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] beat = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _r_counter_T = first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] assign io_resp_bits_data_0 = hasData; // @[Edges.scala:102:36] wire _raw_resp_T = _c_q_io_deq_bits_opcode == 3'h4; // @[Decoupled.scala:362:21] wire _raw_resp_T_1 = _c_q_io_deq_bits_opcode == 3'h5; // @[Decoupled.scala:362:21] wire raw_resp = _raw_resp_T | _raw_resp_T_1; // @[SinkC.scala:78:{34,58,75}] reg resp_r; // @[SinkC.scala:79:48] wire resp = _c_q_io_deq_valid ? raw_resp : resp_r; // @[Decoupled.scala:362:21]
Generate the Verilog code corresponding to this FIRRTL code module TLAToNoC_6 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst q of Queue1_TLBundleA_a32d64s6k5z4c_6 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 3) node _head_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2) node head_beats1_opdata = eq(_head_beats1_opdata_T, UInt<1>(0h0)) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3) node _tail_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2) node tail_beats1_opdata = eq(_tail_beats1_opdata_T, UInt<1>(0h0)) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body_hi = cat(q.io.deq.bits.mask, q.io.deq.bits.data) node body = cat(body_hi, q.io.deq.bits.corrupt) node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T) node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<33>(0h8c000000))) node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_5 = xor(q.io.deq.bits.address, UInt<17>(0h10000)) node _io_flit_bits_egress_id_requestOH_T_6 = cvt(_io_flit_bits_egress_id_requestOH_T_5) node _io_flit_bits_egress_id_requestOH_T_7 = and(_io_flit_bits_egress_id_requestOH_T_6, asSInt(UInt<33>(0h8c011000))) node _io_flit_bits_egress_id_requestOH_T_8 = asSInt(_io_flit_bits_egress_id_requestOH_T_7) node _io_flit_bits_egress_id_requestOH_T_9 = eq(_io_flit_bits_egress_id_requestOH_T_8, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_10 = xor(q.io.deq.bits.address, UInt<28>(0hc000000)) node _io_flit_bits_egress_id_requestOH_T_11 = cvt(_io_flit_bits_egress_id_requestOH_T_10) node _io_flit_bits_egress_id_requestOH_T_12 = and(_io_flit_bits_egress_id_requestOH_T_11, asSInt(UInt<33>(0h8c000000))) node _io_flit_bits_egress_id_requestOH_T_13 = asSInt(_io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = eq(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_15 = or(_io_flit_bits_egress_id_requestOH_T_4, _io_flit_bits_egress_id_requestOH_T_9) node _io_flit_bits_egress_id_requestOH_T_16 = or(_io_flit_bits_egress_id_requestOH_T_15, _io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16) node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<28>(0h8000000)) node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18) node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<33>(0h8c0100c0))) node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20) node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_23 = xor(q.io.deq.bits.address, UInt<32>(0h80000000)) node _io_flit_bits_egress_id_requestOH_T_24 = cvt(_io_flit_bits_egress_id_requestOH_T_23) node _io_flit_bits_egress_id_requestOH_T_25 = and(_io_flit_bits_egress_id_requestOH_T_24, asSInt(UInt<33>(0h800000c0))) node _io_flit_bits_egress_id_requestOH_T_26 = asSInt(_io_flit_bits_egress_id_requestOH_T_25) node _io_flit_bits_egress_id_requestOH_T_27 = eq(_io_flit_bits_egress_id_requestOH_T_26, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_28 = or(_io_flit_bits_egress_id_requestOH_T_22, _io_flit_bits_egress_id_requestOH_T_27) node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28) node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_requestOH_T_30 = xor(q.io.deq.bits.address, UInt<28>(0h8000040)) node _io_flit_bits_egress_id_requestOH_T_31 = cvt(_io_flit_bits_egress_id_requestOH_T_30) node _io_flit_bits_egress_id_requestOH_T_32 = and(_io_flit_bits_egress_id_requestOH_T_31, asSInt(UInt<33>(0h8c0100c0))) node _io_flit_bits_egress_id_requestOH_T_33 = asSInt(_io_flit_bits_egress_id_requestOH_T_32) node _io_flit_bits_egress_id_requestOH_T_34 = eq(_io_flit_bits_egress_id_requestOH_T_33, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_35 = xor(q.io.deq.bits.address, UInt<32>(0h80000040)) node _io_flit_bits_egress_id_requestOH_T_36 = cvt(_io_flit_bits_egress_id_requestOH_T_35) node _io_flit_bits_egress_id_requestOH_T_37 = and(_io_flit_bits_egress_id_requestOH_T_36, asSInt(UInt<33>(0h800000c0))) node _io_flit_bits_egress_id_requestOH_T_38 = asSInt(_io_flit_bits_egress_id_requestOH_T_37) node _io_flit_bits_egress_id_requestOH_T_39 = eq(_io_flit_bits_egress_id_requestOH_T_38, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_40 = or(_io_flit_bits_egress_id_requestOH_T_34, _io_flit_bits_egress_id_requestOH_T_39) node _io_flit_bits_egress_id_requestOH_T_41 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_40) node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_41) node _io_flit_bits_egress_id_requestOH_T_42 = xor(q.io.deq.bits.address, UInt<28>(0h8000080)) node _io_flit_bits_egress_id_requestOH_T_43 = cvt(_io_flit_bits_egress_id_requestOH_T_42) node _io_flit_bits_egress_id_requestOH_T_44 = and(_io_flit_bits_egress_id_requestOH_T_43, asSInt(UInt<33>(0h8c0100c0))) node _io_flit_bits_egress_id_requestOH_T_45 = asSInt(_io_flit_bits_egress_id_requestOH_T_44) node _io_flit_bits_egress_id_requestOH_T_46 = eq(_io_flit_bits_egress_id_requestOH_T_45, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_47 = xor(q.io.deq.bits.address, UInt<32>(0h80000080)) node _io_flit_bits_egress_id_requestOH_T_48 = cvt(_io_flit_bits_egress_id_requestOH_T_47) node _io_flit_bits_egress_id_requestOH_T_49 = and(_io_flit_bits_egress_id_requestOH_T_48, asSInt(UInt<33>(0h800000c0))) node _io_flit_bits_egress_id_requestOH_T_50 = asSInt(_io_flit_bits_egress_id_requestOH_T_49) node _io_flit_bits_egress_id_requestOH_T_51 = eq(_io_flit_bits_egress_id_requestOH_T_50, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_52 = or(_io_flit_bits_egress_id_requestOH_T_46, _io_flit_bits_egress_id_requestOH_T_51) node _io_flit_bits_egress_id_requestOH_T_53 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_52) node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_53) node _io_flit_bits_egress_id_requestOH_T_54 = xor(q.io.deq.bits.address, UInt<28>(0h80000c0)) node _io_flit_bits_egress_id_requestOH_T_55 = cvt(_io_flit_bits_egress_id_requestOH_T_54) node _io_flit_bits_egress_id_requestOH_T_56 = and(_io_flit_bits_egress_id_requestOH_T_55, asSInt(UInt<33>(0h8c0100c0))) node _io_flit_bits_egress_id_requestOH_T_57 = asSInt(_io_flit_bits_egress_id_requestOH_T_56) node _io_flit_bits_egress_id_requestOH_T_58 = eq(_io_flit_bits_egress_id_requestOH_T_57, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_59 = xor(q.io.deq.bits.address, UInt<32>(0h800000c0)) node _io_flit_bits_egress_id_requestOH_T_60 = cvt(_io_flit_bits_egress_id_requestOH_T_59) node _io_flit_bits_egress_id_requestOH_T_61 = and(_io_flit_bits_egress_id_requestOH_T_60, asSInt(UInt<33>(0h800000c0))) node _io_flit_bits_egress_id_requestOH_T_62 = asSInt(_io_flit_bits_egress_id_requestOH_T_61) node _io_flit_bits_egress_id_requestOH_T_63 = eq(_io_flit_bits_egress_id_requestOH_T_62, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_64 = or(_io_flit_bits_egress_id_requestOH_T_58, _io_flit_bits_egress_id_requestOH_T_63) node _io_flit_bits_egress_id_requestOH_T_65 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_64) node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_65) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0h9), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<4>(0hb), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<4>(0hd), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<4>(0hf), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h11), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) wire _io_flit_bits_egress_id_WIRE : UInt<5> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node _has_body_opdata_T = bits(q.io.deq.bits.opcode, 2, 2) node has_body_opdata = eq(_has_body_opdata_T, UInt<1>(0h0)) node _has_body_T = not(q.io.deq.bits.mask) node _has_body_T_1 = neq(_has_body_T, UInt<1>(0h0)) node _has_body_T_2 = or(has_body_opdata, _has_body_T_1) connect has_body, _has_body_T_2 connect q.io.enq, io.protocol node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<6>(0h28)) connect q.io.enq.bits.source, _q_io_enq_bits_source_T
module TLAToNoC_6( // @[TilelinkAdapters.scala:112:7] input clock, // @[TilelinkAdapters.scala:112:7] input reset, // @[TilelinkAdapters.scala:112:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [72:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire [8:0] _GEN; // @[TilelinkAdapters.scala:119:{45,69}] wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [7:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3]); // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire _io_flit_bits_tail_T = _GEN == 9'h0; // @[TilelinkAdapters.scala:119:{45,69}] wire q_io_deq_ready = io_flit_ready & (is_body | _io_flit_bits_tail_T); // @[TilelinkAdapters.scala:39:24, :41:{35,47}, :119:{45,69}] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | _io_flit_bits_tail_T); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}] wire [21:0] _GEN_0 = _q_io_deq_bits_address[27:6] ^ 22'h200001; // @[Parameters.scala:137:31] wire [25:0] _io_flit_bits_egress_id_requestOH_T_35 = _q_io_deq_bits_address[31:6] ^ 26'h2000001; // @[Parameters.scala:137:31] wire [21:0] _GEN_1 = _q_io_deq_bits_address[27:6] ^ 22'h200002; // @[Parameters.scala:137:31] wire [25:0] _io_flit_bits_egress_id_requestOH_T_47 = _q_io_deq_bits_address[31:6] ^ 26'h2000002; // @[Parameters.scala:137:31] wire [21:0] _GEN_2 = _q_io_deq_bits_address[27:6] ^ 22'h200003; // @[Parameters.scala:137:31] wire [25:0] _io_flit_bits_egress_id_requestOH_T_59 = _q_io_deq_bits_address[31:6] ^ 26'h2000003; // @[Parameters.scala:137:31] assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[Edges.scala:92:{28,37}] wire _GEN_3 = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:112:7] if (reset) begin // @[TilelinkAdapters.scala:112:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :112:7] end else begin // @[TilelinkAdapters.scala:112:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3])) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN_3 & io_flit_bits_tail_0) & (_GEN_3 & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module PE_287 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_31 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_287( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_31 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_101 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_112 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_101( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_112 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulDiv_3 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { fn : UInt<5>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, full_data : UInt<128>, tag : UInt<5>}}} regreset state : UInt<3>, clock, reset, UInt<3>(0h0) reg req : { fn : UInt<5>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clock reg count : UInt<7>, clock reg neg_out : UInt<1>, clock reg isHi : UInt<1>, clock reg resHi : UInt<1>, clock reg divisor : UInt<65>, clock reg remainder : UInt<130>, clock wire decoded_plaInput : UInt<3> node decoded_invInputs = not(decoded_plaInput) wire decoded : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_3_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_4_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 2, 2) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 2, 2) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_1_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_plaInput, 2, 2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node _decoded_orMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_4_2) node decoded_orMatrixOutputs_lo = cat(_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_hi = cat(_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node decoded_invMatrixOutputs_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded, decoded_invMatrixOutputs connect decoded_plaInput, io.req.bits.fn node _T = bits(decoded, 3, 3) node _T_1 = bits(decoded, 2, 2) node _T_2 = bits(decoded, 1, 1) node _T_3 = bits(decoded, 0, 0) node cmdMul = bits(_T, 0, 0) node cmdHi = bits(_T_1, 0, 0) node lhsSigned = bits(_T_2, 0, 0) node rhsSigned = bits(_T_3, 0, 0) node _T_4 = eq(io.req.bits.dw, UInt<1>(0h0)) node _T_5 = and(UInt<1>(0h1), _T_4) node _sign_T = bits(io.req.bits.in1, 31, 31) node _sign_T_1 = bits(io.req.bits.in1, 63, 63) node _sign_T_2 = mux(_T_5, _sign_T, _sign_T_1) node lhs_sign = and(lhsSigned, _sign_T_2) node _hi_T = mux(lhs_sign, UInt<32>(0hffffffff), UInt<32>(0h0)) node _hi_T_1 = bits(io.req.bits.in1, 63, 32) node hi = mux(_T_5, _hi_T, _hi_T_1) node _T_6 = bits(io.req.bits.in1, 31, 0) node lhs_in = cat(hi, _T_6) node _T_7 = eq(io.req.bits.dw, UInt<1>(0h0)) node _T_8 = and(UInt<1>(0h1), _T_7) node _sign_T_3 = bits(io.req.bits.in2, 31, 31) node _sign_T_4 = bits(io.req.bits.in2, 63, 63) node _sign_T_5 = mux(_T_8, _sign_T_3, _sign_T_4) node rhs_sign = and(rhsSigned, _sign_T_5) node _hi_T_2 = mux(rhs_sign, UInt<32>(0hffffffff), UInt<32>(0h0)) node _hi_T_3 = bits(io.req.bits.in2, 63, 32) node hi_1 = mux(_T_8, _hi_T_2, _hi_T_3) node _T_9 = bits(io.req.bits.in2, 31, 0) node rhs_in = cat(hi_1, _T_9) node _subtractor_T = bits(remainder, 128, 64) node _subtractor_T_1 = sub(_subtractor_T, divisor) node subtractor = tail(_subtractor_T_1, 1) node _result_T = bits(remainder, 128, 65) node _result_T_1 = bits(remainder, 63, 0) node result = mux(resHi, _result_T, _result_T_1) node _negated_remainder_T = sub(UInt<1>(0h0), result) node negated_remainder = tail(_negated_remainder_T, 1) node _T_10 = eq(state, UInt<3>(0h1)) when _T_10 : node _T_11 = bits(remainder, 63, 63) when _T_11 : connect remainder, negated_remainder node _T_12 = bits(divisor, 63, 63) when _T_12 : connect divisor, subtractor connect state, UInt<3>(0h3) node _T_13 = eq(state, UInt<3>(0h5)) when _T_13 : connect remainder, negated_remainder connect state, UInt<3>(0h7) connect resHi, UInt<1>(0h0) node _T_14 = eq(state, UInt<3>(0h2)) when _T_14 : node _mulReg_T = bits(remainder, 129, 65) node _mulReg_T_1 = bits(remainder, 63, 0) node mulReg = cat(_mulReg_T, _mulReg_T_1) node mplierSign = bits(remainder, 64, 64) node mplier = bits(mulReg, 63, 0) node _accum_T = bits(mulReg, 128, 64) node accum = asSInt(_accum_T) node mpcand = asSInt(divisor) node _prod_T = bits(mplier, 0, 0) node _prod_T_1 = cat(mplierSign, _prod_T) node _prod_T_2 = asSInt(_prod_T_1) node _prod_T_3 = mul(_prod_T_2, mpcand) node _prod_T_4 = add(_prod_T_3, accum) node _prod_T_5 = tail(_prod_T_4, 1) node prod = asSInt(_prod_T_5) node _nextMulReg_T = bits(mplier, 63, 1) node nextMulReg_hi = asUInt(prod) node nextMulReg = cat(nextMulReg_hi, _nextMulReg_T) node _nextMplierSign_T = eq(count, UInt<6>(0h3e)) node nextMplierSign = and(_nextMplierSign_T, neg_out) node _eOutMask_T = mul(count, UInt<1>(0h1)) node _eOutMask_T_1 = bits(_eOutMask_T, 5, 0) node _eOutMask_T_2 = dshr(asSInt(UInt<65>(0h10000000000000000)), _eOutMask_T_1) node eOutMask = bits(_eOutMask_T_2, 63, 0) node _eOut_T = neq(count, UInt<6>(0h3f)) node _eOut_T_1 = and(UInt<1>(0h0), _eOut_T) node _eOut_T_2 = neq(count, UInt<1>(0h0)) node _eOut_T_3 = and(_eOut_T_1, _eOut_T_2) node _eOut_T_4 = eq(isHi, UInt<1>(0h0)) node _eOut_T_5 = and(_eOut_T_3, _eOut_T_4) node _eOut_T_6 = not(eOutMask) node _eOut_T_7 = and(mplier, _eOut_T_6) node _eOut_T_8 = eq(_eOut_T_7, UInt<1>(0h0)) node eOut = and(_eOut_T_5, _eOut_T_8) node _eOutRes_T = mul(count, UInt<1>(0h1)) node _eOutRes_T_1 = sub(UInt<7>(0h40), _eOutRes_T) node _eOutRes_T_2 = tail(_eOutRes_T_1, 1) node _eOutRes_T_3 = bits(_eOutRes_T_2, 5, 0) node eOutRes = dshr(mulReg, _eOutRes_T_3) node _nextMulReg1_T = bits(nextMulReg, 128, 64) node _nextMulReg1_T_1 = mux(eOut, eOutRes, nextMulReg) node _nextMulReg1_T_2 = bits(_nextMulReg1_T_1, 63, 0) node nextMulReg1 = cat(_nextMulReg1_T, _nextMulReg1_T_2) node _remainder_T = shr(nextMulReg1, 64) node _remainder_T_1 = bits(nextMulReg1, 63, 0) node remainder_hi = cat(_remainder_T, nextMplierSign) node _remainder_T_2 = cat(remainder_hi, _remainder_T_1) connect remainder, _remainder_T_2 node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 node _T_15 = eq(count, UInt<6>(0h3f)) node _T_16 = or(eOut, _T_15) when _T_16 : connect state, UInt<3>(0h6) connect resHi, isHi node _T_17 = eq(state, UInt<3>(0h3)) when _T_17 : node unrolls_less = bits(subtractor, 64, 64) node _unrolls_T = bits(remainder, 127, 64) node _unrolls_T_1 = bits(subtractor, 63, 0) node _unrolls_T_2 = mux(unrolls_less, _unrolls_T, _unrolls_T_1) node _unrolls_T_3 = bits(remainder, 63, 0) node _unrolls_T_4 = eq(unrolls_less, UInt<1>(0h0)) node unrolls_hi = cat(_unrolls_T_2, _unrolls_T_3) node unrolls_0 = cat(unrolls_hi, _unrolls_T_4) connect remainder, unrolls_0 node _T_18 = eq(count, UInt<7>(0h40)) when _T_18 : node _state_T = mux(neg_out, UInt<3>(0h5), UInt<3>(0h7)) connect state, _state_T connect resHi, isHi node _count_T_2 = add(count, UInt<1>(0h1)) node _count_T_3 = tail(_count_T_2, 1) connect count, _count_T_3 node _divby0_T = eq(count, UInt<1>(0h0)) node _divby0_T_1 = bits(subtractor, 64, 64) node _divby0_T_2 = eq(_divby0_T_1, UInt<1>(0h0)) node divby0 = and(_divby0_T, _divby0_T_2) node alignMask = not(UInt<6>(0h0)) node _divisorMSB_T = bits(divisor, 63, 0) node divisorMSB_hi = bits(_divisorMSB_T, 63, 32) node divisorMSB_lo = bits(_divisorMSB_T, 31, 0) node divisorMSB_useHi = orr(divisorMSB_hi) node divisorMSB_hi_1 = bits(divisorMSB_hi, 31, 16) node divisorMSB_lo_1 = bits(divisorMSB_hi, 15, 0) node divisorMSB_useHi_1 = orr(divisorMSB_hi_1) node divisorMSB_hi_2 = bits(divisorMSB_hi_1, 15, 8) node divisorMSB_lo_2 = bits(divisorMSB_hi_1, 7, 0) node divisorMSB_useHi_2 = orr(divisorMSB_hi_2) node divisorMSB_hi_3 = bits(divisorMSB_hi_2, 7, 4) node divisorMSB_lo_3 = bits(divisorMSB_hi_2, 3, 0) node divisorMSB_useHi_3 = orr(divisorMSB_hi_3) node _divisorMSB_T_1 = bits(divisorMSB_hi_3, 3, 3) node _divisorMSB_T_2 = bits(divisorMSB_hi_3, 2, 2) node _divisorMSB_T_3 = bits(divisorMSB_hi_3, 1, 1) node _divisorMSB_T_4 = mux(_divisorMSB_T_2, UInt<2>(0h2), _divisorMSB_T_3) node _divisorMSB_T_5 = mux(_divisorMSB_T_1, UInt<2>(0h3), _divisorMSB_T_4) node _divisorMSB_T_6 = bits(divisorMSB_lo_3, 3, 3) node _divisorMSB_T_7 = bits(divisorMSB_lo_3, 2, 2) node _divisorMSB_T_8 = bits(divisorMSB_lo_3, 1, 1) node _divisorMSB_T_9 = mux(_divisorMSB_T_7, UInt<2>(0h2), _divisorMSB_T_8) node _divisorMSB_T_10 = mux(_divisorMSB_T_6, UInt<2>(0h3), _divisorMSB_T_9) node _divisorMSB_T_11 = mux(divisorMSB_useHi_3, _divisorMSB_T_5, _divisorMSB_T_10) node _divisorMSB_T_12 = cat(divisorMSB_useHi_3, _divisorMSB_T_11) node divisorMSB_hi_4 = bits(divisorMSB_lo_2, 7, 4) node divisorMSB_lo_4 = bits(divisorMSB_lo_2, 3, 0) node divisorMSB_useHi_4 = orr(divisorMSB_hi_4) node _divisorMSB_T_13 = bits(divisorMSB_hi_4, 3, 3) node _divisorMSB_T_14 = bits(divisorMSB_hi_4, 2, 2) node _divisorMSB_T_15 = bits(divisorMSB_hi_4, 1, 1) node _divisorMSB_T_16 = mux(_divisorMSB_T_14, UInt<2>(0h2), _divisorMSB_T_15) node _divisorMSB_T_17 = mux(_divisorMSB_T_13, UInt<2>(0h3), _divisorMSB_T_16) node _divisorMSB_T_18 = bits(divisorMSB_lo_4, 3, 3) node _divisorMSB_T_19 = bits(divisorMSB_lo_4, 2, 2) node _divisorMSB_T_20 = bits(divisorMSB_lo_4, 1, 1) node _divisorMSB_T_21 = mux(_divisorMSB_T_19, UInt<2>(0h2), _divisorMSB_T_20) node _divisorMSB_T_22 = mux(_divisorMSB_T_18, UInt<2>(0h3), _divisorMSB_T_21) node _divisorMSB_T_23 = mux(divisorMSB_useHi_4, _divisorMSB_T_17, _divisorMSB_T_22) node _divisorMSB_T_24 = cat(divisorMSB_useHi_4, _divisorMSB_T_23) node _divisorMSB_T_25 = mux(divisorMSB_useHi_2, _divisorMSB_T_12, _divisorMSB_T_24) node _divisorMSB_T_26 = cat(divisorMSB_useHi_2, _divisorMSB_T_25) node divisorMSB_hi_5 = bits(divisorMSB_lo_1, 15, 8) node divisorMSB_lo_5 = bits(divisorMSB_lo_1, 7, 0) node divisorMSB_useHi_5 = orr(divisorMSB_hi_5) node divisorMSB_hi_6 = bits(divisorMSB_hi_5, 7, 4) node divisorMSB_lo_6 = bits(divisorMSB_hi_5, 3, 0) node divisorMSB_useHi_6 = orr(divisorMSB_hi_6) node _divisorMSB_T_27 = bits(divisorMSB_hi_6, 3, 3) node _divisorMSB_T_28 = bits(divisorMSB_hi_6, 2, 2) node _divisorMSB_T_29 = bits(divisorMSB_hi_6, 1, 1) node _divisorMSB_T_30 = mux(_divisorMSB_T_28, UInt<2>(0h2), _divisorMSB_T_29) node _divisorMSB_T_31 = mux(_divisorMSB_T_27, UInt<2>(0h3), _divisorMSB_T_30) node _divisorMSB_T_32 = bits(divisorMSB_lo_6, 3, 3) node _divisorMSB_T_33 = bits(divisorMSB_lo_6, 2, 2) node _divisorMSB_T_34 = bits(divisorMSB_lo_6, 1, 1) node _divisorMSB_T_35 = mux(_divisorMSB_T_33, UInt<2>(0h2), _divisorMSB_T_34) node _divisorMSB_T_36 = mux(_divisorMSB_T_32, UInt<2>(0h3), _divisorMSB_T_35) node _divisorMSB_T_37 = mux(divisorMSB_useHi_6, _divisorMSB_T_31, _divisorMSB_T_36) node _divisorMSB_T_38 = cat(divisorMSB_useHi_6, _divisorMSB_T_37) node divisorMSB_hi_7 = bits(divisorMSB_lo_5, 7, 4) node divisorMSB_lo_7 = bits(divisorMSB_lo_5, 3, 0) node divisorMSB_useHi_7 = orr(divisorMSB_hi_7) node _divisorMSB_T_39 = bits(divisorMSB_hi_7, 3, 3) node _divisorMSB_T_40 = bits(divisorMSB_hi_7, 2, 2) node _divisorMSB_T_41 = bits(divisorMSB_hi_7, 1, 1) node _divisorMSB_T_42 = mux(_divisorMSB_T_40, UInt<2>(0h2), _divisorMSB_T_41) node _divisorMSB_T_43 = mux(_divisorMSB_T_39, UInt<2>(0h3), _divisorMSB_T_42) node _divisorMSB_T_44 = bits(divisorMSB_lo_7, 3, 3) node _divisorMSB_T_45 = bits(divisorMSB_lo_7, 2, 2) node _divisorMSB_T_46 = bits(divisorMSB_lo_7, 1, 1) node _divisorMSB_T_47 = mux(_divisorMSB_T_45, UInt<2>(0h2), _divisorMSB_T_46) node _divisorMSB_T_48 = mux(_divisorMSB_T_44, UInt<2>(0h3), _divisorMSB_T_47) node _divisorMSB_T_49 = mux(divisorMSB_useHi_7, _divisorMSB_T_43, _divisorMSB_T_48) node _divisorMSB_T_50 = cat(divisorMSB_useHi_7, _divisorMSB_T_49) node _divisorMSB_T_51 = mux(divisorMSB_useHi_5, _divisorMSB_T_38, _divisorMSB_T_50) node _divisorMSB_T_52 = cat(divisorMSB_useHi_5, _divisorMSB_T_51) node _divisorMSB_T_53 = mux(divisorMSB_useHi_1, _divisorMSB_T_26, _divisorMSB_T_52) node _divisorMSB_T_54 = cat(divisorMSB_useHi_1, _divisorMSB_T_53) node divisorMSB_hi_8 = bits(divisorMSB_lo, 31, 16) node divisorMSB_lo_8 = bits(divisorMSB_lo, 15, 0) node divisorMSB_useHi_8 = orr(divisorMSB_hi_8) node divisorMSB_hi_9 = bits(divisorMSB_hi_8, 15, 8) node divisorMSB_lo_9 = bits(divisorMSB_hi_8, 7, 0) node divisorMSB_useHi_9 = orr(divisorMSB_hi_9) node divisorMSB_hi_10 = bits(divisorMSB_hi_9, 7, 4) node divisorMSB_lo_10 = bits(divisorMSB_hi_9, 3, 0) node divisorMSB_useHi_10 = orr(divisorMSB_hi_10) node _divisorMSB_T_55 = bits(divisorMSB_hi_10, 3, 3) node _divisorMSB_T_56 = bits(divisorMSB_hi_10, 2, 2) node _divisorMSB_T_57 = bits(divisorMSB_hi_10, 1, 1) node _divisorMSB_T_58 = mux(_divisorMSB_T_56, UInt<2>(0h2), _divisorMSB_T_57) node _divisorMSB_T_59 = mux(_divisorMSB_T_55, UInt<2>(0h3), _divisorMSB_T_58) node _divisorMSB_T_60 = bits(divisorMSB_lo_10, 3, 3) node _divisorMSB_T_61 = bits(divisorMSB_lo_10, 2, 2) node _divisorMSB_T_62 = bits(divisorMSB_lo_10, 1, 1) node _divisorMSB_T_63 = mux(_divisorMSB_T_61, UInt<2>(0h2), _divisorMSB_T_62) node _divisorMSB_T_64 = mux(_divisorMSB_T_60, UInt<2>(0h3), _divisorMSB_T_63) node _divisorMSB_T_65 = mux(divisorMSB_useHi_10, _divisorMSB_T_59, _divisorMSB_T_64) node _divisorMSB_T_66 = cat(divisorMSB_useHi_10, _divisorMSB_T_65) node divisorMSB_hi_11 = bits(divisorMSB_lo_9, 7, 4) node divisorMSB_lo_11 = bits(divisorMSB_lo_9, 3, 0) node divisorMSB_useHi_11 = orr(divisorMSB_hi_11) node _divisorMSB_T_67 = bits(divisorMSB_hi_11, 3, 3) node _divisorMSB_T_68 = bits(divisorMSB_hi_11, 2, 2) node _divisorMSB_T_69 = bits(divisorMSB_hi_11, 1, 1) node _divisorMSB_T_70 = mux(_divisorMSB_T_68, UInt<2>(0h2), _divisorMSB_T_69) node _divisorMSB_T_71 = mux(_divisorMSB_T_67, UInt<2>(0h3), _divisorMSB_T_70) node _divisorMSB_T_72 = bits(divisorMSB_lo_11, 3, 3) node _divisorMSB_T_73 = bits(divisorMSB_lo_11, 2, 2) node _divisorMSB_T_74 = bits(divisorMSB_lo_11, 1, 1) node _divisorMSB_T_75 = mux(_divisorMSB_T_73, UInt<2>(0h2), _divisorMSB_T_74) node _divisorMSB_T_76 = mux(_divisorMSB_T_72, UInt<2>(0h3), _divisorMSB_T_75) node _divisorMSB_T_77 = mux(divisorMSB_useHi_11, _divisorMSB_T_71, _divisorMSB_T_76) node _divisorMSB_T_78 = cat(divisorMSB_useHi_11, _divisorMSB_T_77) node _divisorMSB_T_79 = mux(divisorMSB_useHi_9, _divisorMSB_T_66, _divisorMSB_T_78) node _divisorMSB_T_80 = cat(divisorMSB_useHi_9, _divisorMSB_T_79) node divisorMSB_hi_12 = bits(divisorMSB_lo_8, 15, 8) node divisorMSB_lo_12 = bits(divisorMSB_lo_8, 7, 0) node divisorMSB_useHi_12 = orr(divisorMSB_hi_12) node divisorMSB_hi_13 = bits(divisorMSB_hi_12, 7, 4) node divisorMSB_lo_13 = bits(divisorMSB_hi_12, 3, 0) node divisorMSB_useHi_13 = orr(divisorMSB_hi_13) node _divisorMSB_T_81 = bits(divisorMSB_hi_13, 3, 3) node _divisorMSB_T_82 = bits(divisorMSB_hi_13, 2, 2) node _divisorMSB_T_83 = bits(divisorMSB_hi_13, 1, 1) node _divisorMSB_T_84 = mux(_divisorMSB_T_82, UInt<2>(0h2), _divisorMSB_T_83) node _divisorMSB_T_85 = mux(_divisorMSB_T_81, UInt<2>(0h3), _divisorMSB_T_84) node _divisorMSB_T_86 = bits(divisorMSB_lo_13, 3, 3) node _divisorMSB_T_87 = bits(divisorMSB_lo_13, 2, 2) node _divisorMSB_T_88 = bits(divisorMSB_lo_13, 1, 1) node _divisorMSB_T_89 = mux(_divisorMSB_T_87, UInt<2>(0h2), _divisorMSB_T_88) node _divisorMSB_T_90 = mux(_divisorMSB_T_86, UInt<2>(0h3), _divisorMSB_T_89) node _divisorMSB_T_91 = mux(divisorMSB_useHi_13, _divisorMSB_T_85, _divisorMSB_T_90) node _divisorMSB_T_92 = cat(divisorMSB_useHi_13, _divisorMSB_T_91) node divisorMSB_hi_14 = bits(divisorMSB_lo_12, 7, 4) node divisorMSB_lo_14 = bits(divisorMSB_lo_12, 3, 0) node divisorMSB_useHi_14 = orr(divisorMSB_hi_14) node _divisorMSB_T_93 = bits(divisorMSB_hi_14, 3, 3) node _divisorMSB_T_94 = bits(divisorMSB_hi_14, 2, 2) node _divisorMSB_T_95 = bits(divisorMSB_hi_14, 1, 1) node _divisorMSB_T_96 = mux(_divisorMSB_T_94, UInt<2>(0h2), _divisorMSB_T_95) node _divisorMSB_T_97 = mux(_divisorMSB_T_93, UInt<2>(0h3), _divisorMSB_T_96) node _divisorMSB_T_98 = bits(divisorMSB_lo_14, 3, 3) node _divisorMSB_T_99 = bits(divisorMSB_lo_14, 2, 2) node _divisorMSB_T_100 = bits(divisorMSB_lo_14, 1, 1) node _divisorMSB_T_101 = mux(_divisorMSB_T_99, UInt<2>(0h2), _divisorMSB_T_100) node _divisorMSB_T_102 = mux(_divisorMSB_T_98, UInt<2>(0h3), _divisorMSB_T_101) node _divisorMSB_T_103 = mux(divisorMSB_useHi_14, _divisorMSB_T_97, _divisorMSB_T_102) node _divisorMSB_T_104 = cat(divisorMSB_useHi_14, _divisorMSB_T_103) node _divisorMSB_T_105 = mux(divisorMSB_useHi_12, _divisorMSB_T_92, _divisorMSB_T_104) node _divisorMSB_T_106 = cat(divisorMSB_useHi_12, _divisorMSB_T_105) node _divisorMSB_T_107 = mux(divisorMSB_useHi_8, _divisorMSB_T_80, _divisorMSB_T_106) node _divisorMSB_T_108 = cat(divisorMSB_useHi_8, _divisorMSB_T_107) node _divisorMSB_T_109 = mux(divisorMSB_useHi, _divisorMSB_T_54, _divisorMSB_T_108) node _divisorMSB_T_110 = cat(divisorMSB_useHi, _divisorMSB_T_109) node divisorMSB = and(_divisorMSB_T_110, alignMask) node _dividendMSB_T = bits(remainder, 63, 0) node dividendMSB_hi = bits(_dividendMSB_T, 63, 32) node dividendMSB_lo = bits(_dividendMSB_T, 31, 0) node dividendMSB_useHi = orr(dividendMSB_hi) node dividendMSB_hi_1 = bits(dividendMSB_hi, 31, 16) node dividendMSB_lo_1 = bits(dividendMSB_hi, 15, 0) node dividendMSB_useHi_1 = orr(dividendMSB_hi_1) node dividendMSB_hi_2 = bits(dividendMSB_hi_1, 15, 8) node dividendMSB_lo_2 = bits(dividendMSB_hi_1, 7, 0) node dividendMSB_useHi_2 = orr(dividendMSB_hi_2) node dividendMSB_hi_3 = bits(dividendMSB_hi_2, 7, 4) node dividendMSB_lo_3 = bits(dividendMSB_hi_2, 3, 0) node dividendMSB_useHi_3 = orr(dividendMSB_hi_3) node _dividendMSB_T_1 = bits(dividendMSB_hi_3, 3, 3) node _dividendMSB_T_2 = bits(dividendMSB_hi_3, 2, 2) node _dividendMSB_T_3 = bits(dividendMSB_hi_3, 1, 1) node _dividendMSB_T_4 = mux(_dividendMSB_T_2, UInt<2>(0h2), _dividendMSB_T_3) node _dividendMSB_T_5 = mux(_dividendMSB_T_1, UInt<2>(0h3), _dividendMSB_T_4) node _dividendMSB_T_6 = bits(dividendMSB_lo_3, 3, 3) node _dividendMSB_T_7 = bits(dividendMSB_lo_3, 2, 2) node _dividendMSB_T_8 = bits(dividendMSB_lo_3, 1, 1) node _dividendMSB_T_9 = mux(_dividendMSB_T_7, UInt<2>(0h2), _dividendMSB_T_8) node _dividendMSB_T_10 = mux(_dividendMSB_T_6, UInt<2>(0h3), _dividendMSB_T_9) node _dividendMSB_T_11 = mux(dividendMSB_useHi_3, _dividendMSB_T_5, _dividendMSB_T_10) node _dividendMSB_T_12 = cat(dividendMSB_useHi_3, _dividendMSB_T_11) node dividendMSB_hi_4 = bits(dividendMSB_lo_2, 7, 4) node dividendMSB_lo_4 = bits(dividendMSB_lo_2, 3, 0) node dividendMSB_useHi_4 = orr(dividendMSB_hi_4) node _dividendMSB_T_13 = bits(dividendMSB_hi_4, 3, 3) node _dividendMSB_T_14 = bits(dividendMSB_hi_4, 2, 2) node _dividendMSB_T_15 = bits(dividendMSB_hi_4, 1, 1) node _dividendMSB_T_16 = mux(_dividendMSB_T_14, UInt<2>(0h2), _dividendMSB_T_15) node _dividendMSB_T_17 = mux(_dividendMSB_T_13, UInt<2>(0h3), _dividendMSB_T_16) node _dividendMSB_T_18 = bits(dividendMSB_lo_4, 3, 3) node _dividendMSB_T_19 = bits(dividendMSB_lo_4, 2, 2) node _dividendMSB_T_20 = bits(dividendMSB_lo_4, 1, 1) node _dividendMSB_T_21 = mux(_dividendMSB_T_19, UInt<2>(0h2), _dividendMSB_T_20) node _dividendMSB_T_22 = mux(_dividendMSB_T_18, UInt<2>(0h3), _dividendMSB_T_21) node _dividendMSB_T_23 = mux(dividendMSB_useHi_4, _dividendMSB_T_17, _dividendMSB_T_22) node _dividendMSB_T_24 = cat(dividendMSB_useHi_4, _dividendMSB_T_23) node _dividendMSB_T_25 = mux(dividendMSB_useHi_2, _dividendMSB_T_12, _dividendMSB_T_24) node _dividendMSB_T_26 = cat(dividendMSB_useHi_2, _dividendMSB_T_25) node dividendMSB_hi_5 = bits(dividendMSB_lo_1, 15, 8) node dividendMSB_lo_5 = bits(dividendMSB_lo_1, 7, 0) node dividendMSB_useHi_5 = orr(dividendMSB_hi_5) node dividendMSB_hi_6 = bits(dividendMSB_hi_5, 7, 4) node dividendMSB_lo_6 = bits(dividendMSB_hi_5, 3, 0) node dividendMSB_useHi_6 = orr(dividendMSB_hi_6) node _dividendMSB_T_27 = bits(dividendMSB_hi_6, 3, 3) node _dividendMSB_T_28 = bits(dividendMSB_hi_6, 2, 2) node _dividendMSB_T_29 = bits(dividendMSB_hi_6, 1, 1) node _dividendMSB_T_30 = mux(_dividendMSB_T_28, UInt<2>(0h2), _dividendMSB_T_29) node _dividendMSB_T_31 = mux(_dividendMSB_T_27, UInt<2>(0h3), _dividendMSB_T_30) node _dividendMSB_T_32 = bits(dividendMSB_lo_6, 3, 3) node _dividendMSB_T_33 = bits(dividendMSB_lo_6, 2, 2) node _dividendMSB_T_34 = bits(dividendMSB_lo_6, 1, 1) node _dividendMSB_T_35 = mux(_dividendMSB_T_33, UInt<2>(0h2), _dividendMSB_T_34) node _dividendMSB_T_36 = mux(_dividendMSB_T_32, UInt<2>(0h3), _dividendMSB_T_35) node _dividendMSB_T_37 = mux(dividendMSB_useHi_6, _dividendMSB_T_31, _dividendMSB_T_36) node _dividendMSB_T_38 = cat(dividendMSB_useHi_6, _dividendMSB_T_37) node dividendMSB_hi_7 = bits(dividendMSB_lo_5, 7, 4) node dividendMSB_lo_7 = bits(dividendMSB_lo_5, 3, 0) node dividendMSB_useHi_7 = orr(dividendMSB_hi_7) node _dividendMSB_T_39 = bits(dividendMSB_hi_7, 3, 3) node _dividendMSB_T_40 = bits(dividendMSB_hi_7, 2, 2) node _dividendMSB_T_41 = bits(dividendMSB_hi_7, 1, 1) node _dividendMSB_T_42 = mux(_dividendMSB_T_40, UInt<2>(0h2), _dividendMSB_T_41) node _dividendMSB_T_43 = mux(_dividendMSB_T_39, UInt<2>(0h3), _dividendMSB_T_42) node _dividendMSB_T_44 = bits(dividendMSB_lo_7, 3, 3) node _dividendMSB_T_45 = bits(dividendMSB_lo_7, 2, 2) node _dividendMSB_T_46 = bits(dividendMSB_lo_7, 1, 1) node _dividendMSB_T_47 = mux(_dividendMSB_T_45, UInt<2>(0h2), _dividendMSB_T_46) node _dividendMSB_T_48 = mux(_dividendMSB_T_44, UInt<2>(0h3), _dividendMSB_T_47) node _dividendMSB_T_49 = mux(dividendMSB_useHi_7, _dividendMSB_T_43, _dividendMSB_T_48) node _dividendMSB_T_50 = cat(dividendMSB_useHi_7, _dividendMSB_T_49) node _dividendMSB_T_51 = mux(dividendMSB_useHi_5, _dividendMSB_T_38, _dividendMSB_T_50) node _dividendMSB_T_52 = cat(dividendMSB_useHi_5, _dividendMSB_T_51) node _dividendMSB_T_53 = mux(dividendMSB_useHi_1, _dividendMSB_T_26, _dividendMSB_T_52) node _dividendMSB_T_54 = cat(dividendMSB_useHi_1, _dividendMSB_T_53) node dividendMSB_hi_8 = bits(dividendMSB_lo, 31, 16) node dividendMSB_lo_8 = bits(dividendMSB_lo, 15, 0) node dividendMSB_useHi_8 = orr(dividendMSB_hi_8) node dividendMSB_hi_9 = bits(dividendMSB_hi_8, 15, 8) node dividendMSB_lo_9 = bits(dividendMSB_hi_8, 7, 0) node dividendMSB_useHi_9 = orr(dividendMSB_hi_9) node dividendMSB_hi_10 = bits(dividendMSB_hi_9, 7, 4) node dividendMSB_lo_10 = bits(dividendMSB_hi_9, 3, 0) node dividendMSB_useHi_10 = orr(dividendMSB_hi_10) node _dividendMSB_T_55 = bits(dividendMSB_hi_10, 3, 3) node _dividendMSB_T_56 = bits(dividendMSB_hi_10, 2, 2) node _dividendMSB_T_57 = bits(dividendMSB_hi_10, 1, 1) node _dividendMSB_T_58 = mux(_dividendMSB_T_56, UInt<2>(0h2), _dividendMSB_T_57) node _dividendMSB_T_59 = mux(_dividendMSB_T_55, UInt<2>(0h3), _dividendMSB_T_58) node _dividendMSB_T_60 = bits(dividendMSB_lo_10, 3, 3) node _dividendMSB_T_61 = bits(dividendMSB_lo_10, 2, 2) node _dividendMSB_T_62 = bits(dividendMSB_lo_10, 1, 1) node _dividendMSB_T_63 = mux(_dividendMSB_T_61, UInt<2>(0h2), _dividendMSB_T_62) node _dividendMSB_T_64 = mux(_dividendMSB_T_60, UInt<2>(0h3), _dividendMSB_T_63) node _dividendMSB_T_65 = mux(dividendMSB_useHi_10, _dividendMSB_T_59, _dividendMSB_T_64) node _dividendMSB_T_66 = cat(dividendMSB_useHi_10, _dividendMSB_T_65) node dividendMSB_hi_11 = bits(dividendMSB_lo_9, 7, 4) node dividendMSB_lo_11 = bits(dividendMSB_lo_9, 3, 0) node dividendMSB_useHi_11 = orr(dividendMSB_hi_11) node _dividendMSB_T_67 = bits(dividendMSB_hi_11, 3, 3) node _dividendMSB_T_68 = bits(dividendMSB_hi_11, 2, 2) node _dividendMSB_T_69 = bits(dividendMSB_hi_11, 1, 1) node _dividendMSB_T_70 = mux(_dividendMSB_T_68, UInt<2>(0h2), _dividendMSB_T_69) node _dividendMSB_T_71 = mux(_dividendMSB_T_67, UInt<2>(0h3), _dividendMSB_T_70) node _dividendMSB_T_72 = bits(dividendMSB_lo_11, 3, 3) node _dividendMSB_T_73 = bits(dividendMSB_lo_11, 2, 2) node _dividendMSB_T_74 = bits(dividendMSB_lo_11, 1, 1) node _dividendMSB_T_75 = mux(_dividendMSB_T_73, UInt<2>(0h2), _dividendMSB_T_74) node _dividendMSB_T_76 = mux(_dividendMSB_T_72, UInt<2>(0h3), _dividendMSB_T_75) node _dividendMSB_T_77 = mux(dividendMSB_useHi_11, _dividendMSB_T_71, _dividendMSB_T_76) node _dividendMSB_T_78 = cat(dividendMSB_useHi_11, _dividendMSB_T_77) node _dividendMSB_T_79 = mux(dividendMSB_useHi_9, _dividendMSB_T_66, _dividendMSB_T_78) node _dividendMSB_T_80 = cat(dividendMSB_useHi_9, _dividendMSB_T_79) node dividendMSB_hi_12 = bits(dividendMSB_lo_8, 15, 8) node dividendMSB_lo_12 = bits(dividendMSB_lo_8, 7, 0) node dividendMSB_useHi_12 = orr(dividendMSB_hi_12) node dividendMSB_hi_13 = bits(dividendMSB_hi_12, 7, 4) node dividendMSB_lo_13 = bits(dividendMSB_hi_12, 3, 0) node dividendMSB_useHi_13 = orr(dividendMSB_hi_13) node _dividendMSB_T_81 = bits(dividendMSB_hi_13, 3, 3) node _dividendMSB_T_82 = bits(dividendMSB_hi_13, 2, 2) node _dividendMSB_T_83 = bits(dividendMSB_hi_13, 1, 1) node _dividendMSB_T_84 = mux(_dividendMSB_T_82, UInt<2>(0h2), _dividendMSB_T_83) node _dividendMSB_T_85 = mux(_dividendMSB_T_81, UInt<2>(0h3), _dividendMSB_T_84) node _dividendMSB_T_86 = bits(dividendMSB_lo_13, 3, 3) node _dividendMSB_T_87 = bits(dividendMSB_lo_13, 2, 2) node _dividendMSB_T_88 = bits(dividendMSB_lo_13, 1, 1) node _dividendMSB_T_89 = mux(_dividendMSB_T_87, UInt<2>(0h2), _dividendMSB_T_88) node _dividendMSB_T_90 = mux(_dividendMSB_T_86, UInt<2>(0h3), _dividendMSB_T_89) node _dividendMSB_T_91 = mux(dividendMSB_useHi_13, _dividendMSB_T_85, _dividendMSB_T_90) node _dividendMSB_T_92 = cat(dividendMSB_useHi_13, _dividendMSB_T_91) node dividendMSB_hi_14 = bits(dividendMSB_lo_12, 7, 4) node dividendMSB_lo_14 = bits(dividendMSB_lo_12, 3, 0) node dividendMSB_useHi_14 = orr(dividendMSB_hi_14) node _dividendMSB_T_93 = bits(dividendMSB_hi_14, 3, 3) node _dividendMSB_T_94 = bits(dividendMSB_hi_14, 2, 2) node _dividendMSB_T_95 = bits(dividendMSB_hi_14, 1, 1) node _dividendMSB_T_96 = mux(_dividendMSB_T_94, UInt<2>(0h2), _dividendMSB_T_95) node _dividendMSB_T_97 = mux(_dividendMSB_T_93, UInt<2>(0h3), _dividendMSB_T_96) node _dividendMSB_T_98 = bits(dividendMSB_lo_14, 3, 3) node _dividendMSB_T_99 = bits(dividendMSB_lo_14, 2, 2) node _dividendMSB_T_100 = bits(dividendMSB_lo_14, 1, 1) node _dividendMSB_T_101 = mux(_dividendMSB_T_99, UInt<2>(0h2), _dividendMSB_T_100) node _dividendMSB_T_102 = mux(_dividendMSB_T_98, UInt<2>(0h3), _dividendMSB_T_101) node _dividendMSB_T_103 = mux(dividendMSB_useHi_14, _dividendMSB_T_97, _dividendMSB_T_102) node _dividendMSB_T_104 = cat(dividendMSB_useHi_14, _dividendMSB_T_103) node _dividendMSB_T_105 = mux(dividendMSB_useHi_12, _dividendMSB_T_92, _dividendMSB_T_104) node _dividendMSB_T_106 = cat(dividendMSB_useHi_12, _dividendMSB_T_105) node _dividendMSB_T_107 = mux(dividendMSB_useHi_8, _dividendMSB_T_80, _dividendMSB_T_106) node _dividendMSB_T_108 = cat(dividendMSB_useHi_8, _dividendMSB_T_107) node _dividendMSB_T_109 = mux(dividendMSB_useHi, _dividendMSB_T_54, _dividendMSB_T_108) node _dividendMSB_T_110 = cat(dividendMSB_useHi, _dividendMSB_T_109) node _dividendMSB_T_111 = not(alignMask) node dividendMSB = or(_dividendMSB_T_110, _dividendMSB_T_111) node _eOutPos_T = sub(dividendMSB, divisorMSB) node _eOutPos_T_1 = tail(_eOutPos_T, 1) node eOutPos = not(_eOutPos_T_1) node _eOut_T_9 = eq(count, UInt<1>(0h0)) node _eOut_T_10 = eq(divby0, UInt<1>(0h0)) node _eOut_T_11 = and(_eOut_T_9, _eOut_T_10) node _eOut_T_12 = geq(eOutPos, UInt<1>(0h1)) node eOut_1 = and(_eOut_T_11, _eOut_T_12) when eOut_1 : node _remainder_T_3 = bits(remainder, 63, 0) node _remainder_T_4 = dshl(_remainder_T_3, eOutPos) connect remainder, _remainder_T_4 node _count_T_4 = shr(eOutPos, 0) connect count, _count_T_4 node _T_19 = eq(isHi, UInt<1>(0h0)) node _T_20 = and(divby0, _T_19) when _T_20 : connect neg_out, UInt<1>(0h0) node _T_21 = and(io.resp.ready, io.resp.valid) node _T_22 = or(_T_21, io.kill) when _T_22 : connect state, UInt<3>(0h0) node _T_23 = and(io.req.ready, io.req.valid) when _T_23 : node _state_T_1 = or(lhs_sign, rhs_sign) node _state_T_2 = mux(_state_T_1, UInt<3>(0h1), UInt<3>(0h3)) node _state_T_3 = mux(cmdMul, UInt<3>(0h2), _state_T_2) connect state, _state_T_3 connect isHi, cmdHi connect resHi, UInt<1>(0h0) node _count_T_5 = eq(io.req.bits.dw, UInt<1>(0h0)) node _count_T_6 = and(UInt<1>(0h1), _count_T_5) node _count_T_7 = and(cmdMul, _count_T_6) node _count_T_8 = mux(_count_T_7, UInt<6>(0h20), UInt<1>(0h0)) connect count, _count_T_8 node _neg_out_T = neq(lhs_sign, rhs_sign) node _neg_out_T_1 = mux(cmdHi, lhs_sign, _neg_out_T) connect neg_out, _neg_out_T_1 node _divisor_T = cat(rhs_sign, rhs_in) connect divisor, _divisor_T connect remainder, lhs_in connect req, io.req.bits node _outMul_T = xor(UInt<3>(0h6), UInt<3>(0h7)) node _outMul_T_1 = and(state, _outMul_T) node _outMul_T_2 = not(UInt<3>(0h7)) node _outMul_T_3 = and(UInt<3>(0h6), _outMul_T_2) node outMul = eq(_outMul_T_1, _outMul_T_3) node _loOut_T = eq(req.dw, UInt<1>(0h0)) node _loOut_T_1 = and(UInt<1>(0h1), _loOut_T) node _loOut_T_2 = and(UInt<1>(0h1), _loOut_T_1) node _loOut_T_3 = and(_loOut_T_2, outMul) node _loOut_T_4 = bits(result, 63, 32) node _loOut_T_5 = bits(result, 31, 0) node loOut = mux(_loOut_T_3, _loOut_T_4, _loOut_T_5) node _hiOut_T = eq(req.dw, UInt<1>(0h0)) node _hiOut_T_1 = and(UInt<1>(0h1), _hiOut_T) node _hiOut_T_2 = bits(loOut, 31, 31) node _hiOut_T_3 = mux(_hiOut_T_2, UInt<32>(0hffffffff), UInt<32>(0h0)) node _hiOut_T_4 = bits(result, 63, 32) node hiOut = mux(_hiOut_T_1, _hiOut_T_3, _hiOut_T_4) connect io.resp.bits.tag, req.tag node _io_resp_bits_data_T = cat(hiOut, loOut) connect io.resp.bits.data, _io_resp_bits_data_T node _io_resp_bits_full_data_T = bits(remainder, 128, 65) node _io_resp_bits_full_data_T_1 = bits(remainder, 63, 0) node _io_resp_bits_full_data_T_2 = cat(_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1) connect io.resp.bits.full_data, _io_resp_bits_full_data_T_2 node _io_resp_valid_T = eq(state, UInt<3>(0h6)) node _io_resp_valid_T_1 = eq(state, UInt<3>(0h7)) node _io_resp_valid_T_2 = or(_io_resp_valid_T, _io_resp_valid_T_1) connect io.resp.valid, _io_resp_valid_T_2 node _io_req_ready_T = eq(state, UInt<3>(0h0)) connect io.req.ready, _io_req_ready_T
module MulDiv_3( // @[Multiplier.scala:40:7] input clock, // @[Multiplier.scala:40:7] input reset, // @[Multiplier.scala:40:7] output io_req_ready, // @[Multiplier.scala:45:14] input io_req_valid, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_fn, // @[Multiplier.scala:45:14] input io_req_bits_dw, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in1, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in2, // @[Multiplier.scala:45:14] input io_kill, // @[Multiplier.scala:45:14] input io_resp_ready, // @[Multiplier.scala:45:14] output io_resp_valid, // @[Multiplier.scala:45:14] output [63:0] io_resp_bits_data // @[Multiplier.scala:45:14] ); wire io_req_valid_0 = io_req_valid; // @[Multiplier.scala:40:7] wire [4:0] io_req_bits_fn_0 = io_req_bits_fn; // @[Multiplier.scala:40:7] wire io_req_bits_dw_0 = io_req_bits_dw; // @[Multiplier.scala:40:7] wire [63:0] io_req_bits_in1_0 = io_req_bits_in1; // @[Multiplier.scala:40:7] wire [63:0] io_req_bits_in2_0 = io_req_bits_in2; // @[Multiplier.scala:40:7] wire io_kill_0 = io_kill; // @[Multiplier.scala:40:7] wire io_resp_ready_0 = io_resp_ready; // @[Multiplier.scala:40:7] wire _eOut_T_1 = 1'h0; // @[Multiplier.scala:117:36] wire _eOut_T_3 = 1'h0; // @[Multiplier.scala:117:74] wire _eOut_T_5 = 1'h0; // @[Multiplier.scala:117:91] wire eOut = 1'h0; // @[Multiplier.scala:118:13] wire [5:0] alignMask = 6'h3F; // @[Multiplier.scala:149:23] wire [5:0] _dividendMSB_T_111 = 6'h0; // @[Multiplier.scala:151:53] wire [2:0] _outMul_T = 3'h1; // @[Multiplier.scala:175:37] wire [2:0] _outMul_T_2 = 3'h0; // @[Multiplier.scala:175:70] wire [2:0] _outMul_T_3 = 3'h0; // @[Multiplier.scala:175:68] wire [4:0] io_req_bits_tag = 5'h0; // @[Multiplier.scala:40:7] wire [4:0] io_resp_bits_tag = 5'h0; // @[Multiplier.scala:40:7] wire _io_req_ready_T; // @[Multiplier.scala:183:25] wire _io_resp_valid_T_2; // @[Multiplier.scala:182:42] wire [63:0] _io_resp_bits_data_T; // @[Multiplier.scala:180:27] wire [127:0] _io_resp_bits_full_data_T_2; // @[Multiplier.scala:181:32] wire io_req_ready_0; // @[Multiplier.scala:40:7] wire [63:0] io_resp_bits_data_0; // @[Multiplier.scala:40:7] wire [127:0] io_resp_bits_full_data; // @[Multiplier.scala:40:7] wire io_resp_valid_0; // @[Multiplier.scala:40:7] reg [2:0] state; // @[Multiplier.scala:51:22] reg [4:0] req_fn; // @[Multiplier.scala:53:16] reg req_dw; // @[Multiplier.scala:53:16] reg [63:0] req_in1; // @[Multiplier.scala:53:16] reg [63:0] req_in2; // @[Multiplier.scala:53:16] reg [6:0] count; // @[Multiplier.scala:54:18] reg neg_out; // @[Multiplier.scala:57:20] reg isHi; // @[Multiplier.scala:58:17] reg resHi; // @[Multiplier.scala:59:18] reg [64:0] divisor; // @[Multiplier.scala:60:20] wire [64:0] mpcand = divisor; // @[Multiplier.scala:60:20, :111:26] reg [129:0] remainder; // @[Multiplier.scala:61:22] wire [2:0] decoded_plaInput; // @[pla.scala:77:22] wire [2:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [3:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [3:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_3_2 = decoded_andMatrixOutputs_andMatrixInput_0; // @[pla.scala:91:29, :98:70] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_4_2 = decoded_andMatrixOutputs_andMatrixInput_0_1; // @[pla.scala:91:29, :98:70] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire [1:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_1_2 = decoded_andMatrixOutputs_andMatrixInput_0_4; // @[pla.scala:90:45, :98:70] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T = {decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_1 = |_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _decoded_orMatrixOutputs_T_2 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_3 = |_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _decoded_orMatrixOutputs_T_4 = {decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_5 = |_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo = {_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_plaInput = io_req_bits_fn_0[2:0]; // @[pla.scala:77:22] wire cmdMul = decoded[3]; // @[pla.scala:81:23] wire cmdHi = decoded[2]; // @[pla.scala:81:23] wire lhsSigned = decoded[1]; // @[pla.scala:81:23] wire rhsSigned = decoded[0]; // @[pla.scala:81:23] wire _count_T_5 = ~io_req_bits_dw_0; // @[Multiplier.scala:40:7, :78:60] wire _sign_T = io_req_bits_in1_0[31]; // @[Multiplier.scala:40:7, :81:38] wire _sign_T_1 = io_req_bits_in1_0[63]; // @[Multiplier.scala:40:7, :81:48] wire _sign_T_2 = io_req_bits_dw_0 ? _sign_T_1 : _sign_T; // @[Multiplier.scala:40:7, :81:{29,38,48}] wire lhs_sign = lhsSigned & _sign_T_2; // @[Multiplier.scala:75:107, :81:{23,29}] wire [31:0] _hi_T = {32{lhs_sign}}; // @[Multiplier.scala:81:23, :82:29] wire [31:0] _hi_T_1 = io_req_bits_in1_0[63:32]; // @[Multiplier.scala:40:7, :82:43] wire [31:0] hi = io_req_bits_dw_0 ? _hi_T_1 : _hi_T; // @[Multiplier.scala:40:7, :82:{17,29,43}] wire [63:0] lhs_in = {hi, io_req_bits_in1_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}] wire _sign_T_3 = io_req_bits_in2_0[31]; // @[Multiplier.scala:40:7, :81:38] wire _sign_T_4 = io_req_bits_in2_0[63]; // @[Multiplier.scala:40:7, :81:48] wire _sign_T_5 = io_req_bits_dw_0 ? _sign_T_4 : _sign_T_3; // @[Multiplier.scala:40:7, :81:{29,38,48}] wire rhs_sign = rhsSigned & _sign_T_5; // @[Multiplier.scala:75:107, :81:{23,29}] wire [31:0] _hi_T_2 = {32{rhs_sign}}; // @[Multiplier.scala:81:23, :82:29] wire [31:0] _hi_T_3 = io_req_bits_in2_0[63:32]; // @[Multiplier.scala:40:7, :82:43] wire [31:0] hi_1 = io_req_bits_dw_0 ? _hi_T_3 : _hi_T_2; // @[Multiplier.scala:40:7, :82:{17,29,43}] wire [63:0] rhs_in = {hi_1, io_req_bits_in2_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}] wire [64:0] _subtractor_T = remainder[128:64]; // @[Multiplier.scala:61:22, :88:29] wire [65:0] _subtractor_T_1 = {1'h0, _subtractor_T} - {1'h0, divisor}; // @[Multiplier.scala:60:20, :88:{29,37}] wire [64:0] subtractor = _subtractor_T_1[64:0]; // @[Multiplier.scala:88:37] wire [63:0] _result_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36] wire [63:0] _io_resp_bits_full_data_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36, :181:42] wire [63:0] _result_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57] wire [63:0] _mulReg_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :107:55] wire [63:0] _unrolls_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :134:58] wire [63:0] _dividendMSB_T = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :151:39] wire [63:0] _remainder_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :155:31] wire [63:0] _io_resp_bits_full_data_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :181:63] wire [63:0] result = resHi ? _result_T : _result_T_1; // @[Multiplier.scala:59:18, :89:{19,36,57}] wire [64:0] _negated_remainder_T = 65'h0 - {1'h0, result}; // @[Multiplier.scala:89:19, :90:27] wire [63:0] negated_remainder = _negated_remainder_T[63:0]; // @[Multiplier.scala:90:27] wire [64:0] _mulReg_T = remainder[129:65]; // @[Multiplier.scala:61:22, :107:31] wire [128:0] mulReg = {_mulReg_T, _mulReg_T_1}; // @[Multiplier.scala:107:{21,31,55}] wire mplierSign = remainder[64]; // @[Multiplier.scala:61:22, :108:31] wire [63:0] mplier = mulReg[63:0]; // @[Multiplier.scala:107:21, :109:24] wire [64:0] _accum_T = mulReg[128:64]; // @[Multiplier.scala:107:21, :110:23] wire [64:0] accum = _accum_T; // @[Multiplier.scala:110:{23,37}] wire _prod_T = mplier[0]; // @[Multiplier.scala:109:24, :112:38] wire [1:0] _prod_T_1 = {mplierSign, _prod_T}; // @[Multiplier.scala:108:31, :112:{19,38}] wire [1:0] _prod_T_2 = _prod_T_1; // @[Multiplier.scala:112:{19,60}] wire [66:0] _prod_T_3 = {{65{_prod_T_2[1]}}, _prod_T_2} * {{2{mpcand[64]}}, mpcand}; // @[Multiplier.scala:111:26, :112:{60,67}] wire [67:0] _prod_T_4 = {_prod_T_3[66], _prod_T_3} + {{3{accum[64]}}, accum}; // @[Multiplier.scala:110:37, :112:{67,76}] wire [66:0] _prod_T_5 = _prod_T_4[66:0]; // @[Multiplier.scala:112:76] wire [66:0] prod = _prod_T_5; // @[Multiplier.scala:112:76] wire [66:0] nextMulReg_hi = prod; // @[Multiplier.scala:112:76, :113:25] wire [62:0] _nextMulReg_T = mplier[63:1]; // @[Multiplier.scala:109:24, :113:38] wire [129:0] nextMulReg = {nextMulReg_hi, _nextMulReg_T}; // @[Multiplier.scala:113:{25,38}] wire [129:0] _nextMulReg1_T_1 = nextMulReg; // @[Multiplier.scala:113:25, :120:55] wire _nextMplierSign_T = count == 7'h3E; // @[Multiplier.scala:54:18, :114:32] wire nextMplierSign = _nextMplierSign_T & neg_out; // @[Multiplier.scala:57:20, :114:{32,61}] wire [7:0] _GEN = {1'h0, count}; // @[Multiplier.scala:54:18, :116:54] wire [7:0] _eOutMask_T; // @[Multiplier.scala:116:54] assign _eOutMask_T = _GEN; // @[Multiplier.scala:116:54] wire [7:0] _eOutRes_T; // @[Multiplier.scala:119:46] assign _eOutRes_T = _GEN; // @[Multiplier.scala:116:54, :119:46] wire [5:0] _eOutMask_T_1 = _eOutMask_T[5:0]; // @[Multiplier.scala:116:{54,72}] wire [64:0] _eOutMask_T_2 = $signed(65'sh10000000000000000 >>> _eOutMask_T_1); // @[Multiplier.scala:116:{44,72}] wire [63:0] eOutMask = _eOutMask_T_2[63:0]; // @[Multiplier.scala:116:{44,91}] wire _eOut_T = count != 7'h3F; // @[Multiplier.scala:54:18, :117:45] wire _eOut_T_2 = |count; // @[Multiplier.scala:54:18, :117:83] wire _eOut_T_4 = ~isHi; // @[Multiplier.scala:58:17, :118:7] wire [63:0] _eOut_T_6 = ~eOutMask; // @[Multiplier.scala:116:91, :118:26] wire [63:0] _eOut_T_7 = mplier & _eOut_T_6; // @[Multiplier.scala:109:24, :118:{24,26}] wire _eOut_T_8 = _eOut_T_7 == 64'h0; // @[Multiplier.scala:118:{24,37}] wire [8:0] _eOutRes_T_1 = 9'h40 - {1'h0, _eOutRes_T}; // @[Multiplier.scala:119:{38,46}] wire [7:0] _eOutRes_T_2 = _eOutRes_T_1[7:0]; // @[Multiplier.scala:119:38] wire [5:0] _eOutRes_T_3 = _eOutRes_T_2[5:0]; // @[Multiplier.scala:119:{38,64}] wire [128:0] eOutRes = mulReg >> _eOutRes_T_3; // @[Multiplier.scala:107:21, :119:{27,64}] wire [64:0] _nextMulReg1_T = nextMulReg[128:64]; // @[Multiplier.scala:113:25, :120:37] wire [63:0] _nextMulReg1_T_2 = _nextMulReg1_T_1[63:0]; // @[Multiplier.scala:120:{55,82}] wire [128:0] nextMulReg1 = {_nextMulReg1_T, _nextMulReg1_T_2}; // @[Multiplier.scala:120:{26,37,82}] wire [64:0] _remainder_T = nextMulReg1[128:64]; // @[Multiplier.scala:120:26, :121:34] wire [63:0] _remainder_T_1 = nextMulReg1[63:0]; // @[Multiplier.scala:120:26, :121:67] wire [65:0] remainder_hi = {_remainder_T, nextMplierSign}; // @[Multiplier.scala:114:61, :121:{21,34}] wire [129:0] _remainder_T_2 = {remainder_hi, _remainder_T_1}; // @[Multiplier.scala:121:{21,67}] wire [7:0] _GEN_0 = _GEN + 8'h1; // @[Multiplier.scala:116:54, :123:20] wire [7:0] _count_T; // @[Multiplier.scala:123:20] assign _count_T = _GEN_0; // @[Multiplier.scala:123:20] wire [7:0] _count_T_2; // @[Multiplier.scala:144:20] assign _count_T_2 = _GEN_0; // @[Multiplier.scala:123:20, :144:20] wire [6:0] _count_T_1 = _count_T[6:0]; // @[Multiplier.scala:123:20] wire unrolls_less = subtractor[64]; // @[Multiplier.scala:88:37, :133:28] wire _divby0_T_1 = subtractor[64]; // @[Multiplier.scala:88:37, :133:28, :146:46] wire [63:0] _unrolls_T = remainder[127:64]; // @[Multiplier.scala:61:22, :134:24] wire [63:0] _unrolls_T_1 = subtractor[63:0]; // @[Multiplier.scala:88:37, :134:45] wire [63:0] _unrolls_T_2 = unrolls_less ? _unrolls_T : _unrolls_T_1; // @[Multiplier.scala:133:28, :134:{14,24,45}] wire _unrolls_T_4 = ~unrolls_less; // @[Multiplier.scala:133:28, :134:67] wire [127:0] unrolls_hi = {_unrolls_T_2, _unrolls_T_3}; // @[Multiplier.scala:134:{10,14,58}] wire [128:0] unrolls_0 = {unrolls_hi, _unrolls_T_4}; // @[Multiplier.scala:134:{10,67}] wire [2:0] _state_T = {1'h1, ~neg_out, 1'h1}; // @[Multiplier.scala:57:20, :139:19] wire [6:0] _count_T_3 = _count_T_2[6:0]; // @[Multiplier.scala:144:20] wire _divby0_T = ~(|count); // @[Multiplier.scala:54:18, :117:83, :146:24] wire _divby0_T_2 = ~_divby0_T_1; // @[Multiplier.scala:146:{35,46}] wire divby0 = _divby0_T & _divby0_T_2; // @[Multiplier.scala:146:{24,32,35}] wire [63:0] _divisorMSB_T = divisor[63:0]; // @[Multiplier.scala:60:20, :150:36] wire [31:0] divisorMSB_hi = _divisorMSB_T[63:32]; // @[CircuitMath.scala:33:17] wire [31:0] divisorMSB_lo = _divisorMSB_T[31:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi = |divisorMSB_hi; // @[CircuitMath.scala:33:17, :35:22] wire [15:0] divisorMSB_hi_1 = divisorMSB_hi[31:16]; // @[CircuitMath.scala:33:17] wire [15:0] divisorMSB_lo_1 = divisorMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_1 = |divisorMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] divisorMSB_hi_2 = divisorMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] divisorMSB_lo_2 = divisorMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_2 = |divisorMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_3 = divisorMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_3 = divisorMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_3 = |divisorMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_1 = divisorMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_2 = divisorMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_3 = divisorMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_4 = _divisorMSB_T_2 ? 2'h2 : {1'h0, _divisorMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_5 = _divisorMSB_T_1 ? 2'h3 : _divisorMSB_T_4; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_6 = divisorMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_7 = divisorMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_8 = divisorMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_9 = _divisorMSB_T_7 ? 2'h2 : {1'h0, _divisorMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_10 = _divisorMSB_T_6 ? 2'h3 : _divisorMSB_T_9; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_11 = divisorMSB_useHi_3 ? _divisorMSB_T_5 : _divisorMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_12 = {divisorMSB_useHi_3, _divisorMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_4 = divisorMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_4 = divisorMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_4 = |divisorMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_13 = divisorMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_14 = divisorMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_15 = divisorMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_16 = _divisorMSB_T_14 ? 2'h2 : {1'h0, _divisorMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_17 = _divisorMSB_T_13 ? 2'h3 : _divisorMSB_T_16; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_18 = divisorMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_19 = divisorMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_20 = divisorMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_21 = _divisorMSB_T_19 ? 2'h2 : {1'h0, _divisorMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_22 = _divisorMSB_T_18 ? 2'h3 : _divisorMSB_T_21; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_23 = divisorMSB_useHi_4 ? _divisorMSB_T_17 : _divisorMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_24 = {divisorMSB_useHi_4, _divisorMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_25 = divisorMSB_useHi_2 ? _divisorMSB_T_12 : _divisorMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_26 = {divisorMSB_useHi_2, _divisorMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] divisorMSB_hi_5 = divisorMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] divisorMSB_lo_5 = divisorMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_5 = |divisorMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_6 = divisorMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_6 = divisorMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_6 = |divisorMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_27 = divisorMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_28 = divisorMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_29 = divisorMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_30 = _divisorMSB_T_28 ? 2'h2 : {1'h0, _divisorMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_31 = _divisorMSB_T_27 ? 2'h3 : _divisorMSB_T_30; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_32 = divisorMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_33 = divisorMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_34 = divisorMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_35 = _divisorMSB_T_33 ? 2'h2 : {1'h0, _divisorMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_36 = _divisorMSB_T_32 ? 2'h3 : _divisorMSB_T_35; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_37 = divisorMSB_useHi_6 ? _divisorMSB_T_31 : _divisorMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_38 = {divisorMSB_useHi_6, _divisorMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_7 = divisorMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_7 = divisorMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_7 = |divisorMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_39 = divisorMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_40 = divisorMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_41 = divisorMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_42 = _divisorMSB_T_40 ? 2'h2 : {1'h0, _divisorMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_43 = _divisorMSB_T_39 ? 2'h3 : _divisorMSB_T_42; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_44 = divisorMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_45 = divisorMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_46 = divisorMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_47 = _divisorMSB_T_45 ? 2'h2 : {1'h0, _divisorMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_48 = _divisorMSB_T_44 ? 2'h3 : _divisorMSB_T_47; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_49 = divisorMSB_useHi_7 ? _divisorMSB_T_43 : _divisorMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_50 = {divisorMSB_useHi_7, _divisorMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_51 = divisorMSB_useHi_5 ? _divisorMSB_T_38 : _divisorMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_52 = {divisorMSB_useHi_5, _divisorMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_53 = divisorMSB_useHi_1 ? _divisorMSB_T_26 : _divisorMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_54 = {divisorMSB_useHi_1, _divisorMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [15:0] divisorMSB_hi_8 = divisorMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17] wire [15:0] divisorMSB_lo_8 = divisorMSB_lo[15:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_8 = |divisorMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] divisorMSB_hi_9 = divisorMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] divisorMSB_lo_9 = divisorMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_9 = |divisorMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_10 = divisorMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_10 = divisorMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_10 = |divisorMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_55 = divisorMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_56 = divisorMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_57 = divisorMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_58 = _divisorMSB_T_56 ? 2'h2 : {1'h0, _divisorMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_59 = _divisorMSB_T_55 ? 2'h3 : _divisorMSB_T_58; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_60 = divisorMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_61 = divisorMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_62 = divisorMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_63 = _divisorMSB_T_61 ? 2'h2 : {1'h0, _divisorMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_64 = _divisorMSB_T_60 ? 2'h3 : _divisorMSB_T_63; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_65 = divisorMSB_useHi_10 ? _divisorMSB_T_59 : _divisorMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_66 = {divisorMSB_useHi_10, _divisorMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_11 = divisorMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_11 = divisorMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_11 = |divisorMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_67 = divisorMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_68 = divisorMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_69 = divisorMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_70 = _divisorMSB_T_68 ? 2'h2 : {1'h0, _divisorMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_71 = _divisorMSB_T_67 ? 2'h3 : _divisorMSB_T_70; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_72 = divisorMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_73 = divisorMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_74 = divisorMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_75 = _divisorMSB_T_73 ? 2'h2 : {1'h0, _divisorMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_76 = _divisorMSB_T_72 ? 2'h3 : _divisorMSB_T_75; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_77 = divisorMSB_useHi_11 ? _divisorMSB_T_71 : _divisorMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_78 = {divisorMSB_useHi_11, _divisorMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_79 = divisorMSB_useHi_9 ? _divisorMSB_T_66 : _divisorMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_80 = {divisorMSB_useHi_9, _divisorMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] divisorMSB_hi_12 = divisorMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] divisorMSB_lo_12 = divisorMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_12 = |divisorMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_13 = divisorMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_13 = divisorMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_13 = |divisorMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_81 = divisorMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_82 = divisorMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_83 = divisorMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_84 = _divisorMSB_T_82 ? 2'h2 : {1'h0, _divisorMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_85 = _divisorMSB_T_81 ? 2'h3 : _divisorMSB_T_84; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_86 = divisorMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_87 = divisorMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_88 = divisorMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_89 = _divisorMSB_T_87 ? 2'h2 : {1'h0, _divisorMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_90 = _divisorMSB_T_86 ? 2'h3 : _divisorMSB_T_89; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_91 = divisorMSB_useHi_13 ? _divisorMSB_T_85 : _divisorMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_92 = {divisorMSB_useHi_13, _divisorMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_14 = divisorMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_14 = divisorMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_14 = |divisorMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_93 = divisorMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_94 = divisorMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_95 = divisorMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_96 = _divisorMSB_T_94 ? 2'h2 : {1'h0, _divisorMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_97 = _divisorMSB_T_93 ? 2'h3 : _divisorMSB_T_96; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_98 = divisorMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_99 = divisorMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_100 = divisorMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_101 = _divisorMSB_T_99 ? 2'h2 : {1'h0, _divisorMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_102 = _divisorMSB_T_98 ? 2'h3 : _divisorMSB_T_101; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_103 = divisorMSB_useHi_14 ? _divisorMSB_T_97 : _divisorMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_104 = {divisorMSB_useHi_14, _divisorMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_105 = divisorMSB_useHi_12 ? _divisorMSB_T_92 : _divisorMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_106 = {divisorMSB_useHi_12, _divisorMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_107 = divisorMSB_useHi_8 ? _divisorMSB_T_80 : _divisorMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_108 = {divisorMSB_useHi_8, _divisorMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_109 = divisorMSB_useHi ? _divisorMSB_T_54 : _divisorMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] _divisorMSB_T_110 = {divisorMSB_useHi, _divisorMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] divisorMSB = _divisorMSB_T_110; // @[CircuitMath.scala:36:10] wire [31:0] dividendMSB_hi = _dividendMSB_T[63:32]; // @[CircuitMath.scala:33:17] wire [31:0] dividendMSB_lo = _dividendMSB_T[31:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi = |dividendMSB_hi; // @[CircuitMath.scala:33:17, :35:22] wire [15:0] dividendMSB_hi_1 = dividendMSB_hi[31:16]; // @[CircuitMath.scala:33:17] wire [15:0] dividendMSB_lo_1 = dividendMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_1 = |dividendMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] dividendMSB_hi_2 = dividendMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] dividendMSB_lo_2 = dividendMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_2 = |dividendMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_3 = dividendMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_3 = dividendMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_3 = |dividendMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_1 = dividendMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_2 = dividendMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_3 = dividendMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_4 = _dividendMSB_T_2 ? 2'h2 : {1'h0, _dividendMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_5 = _dividendMSB_T_1 ? 2'h3 : _dividendMSB_T_4; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_6 = dividendMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_7 = dividendMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_8 = dividendMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_9 = _dividendMSB_T_7 ? 2'h2 : {1'h0, _dividendMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_10 = _dividendMSB_T_6 ? 2'h3 : _dividendMSB_T_9; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_11 = dividendMSB_useHi_3 ? _dividendMSB_T_5 : _dividendMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_12 = {dividendMSB_useHi_3, _dividendMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_4 = dividendMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_4 = dividendMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_4 = |dividendMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_13 = dividendMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_14 = dividendMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_15 = dividendMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_16 = _dividendMSB_T_14 ? 2'h2 : {1'h0, _dividendMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_17 = _dividendMSB_T_13 ? 2'h3 : _dividendMSB_T_16; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_18 = dividendMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_19 = dividendMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_20 = dividendMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_21 = _dividendMSB_T_19 ? 2'h2 : {1'h0, _dividendMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_22 = _dividendMSB_T_18 ? 2'h3 : _dividendMSB_T_21; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_23 = dividendMSB_useHi_4 ? _dividendMSB_T_17 : _dividendMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_24 = {dividendMSB_useHi_4, _dividendMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_25 = dividendMSB_useHi_2 ? _dividendMSB_T_12 : _dividendMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_26 = {dividendMSB_useHi_2, _dividendMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] dividendMSB_hi_5 = dividendMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] dividendMSB_lo_5 = dividendMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_5 = |dividendMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_6 = dividendMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_6 = dividendMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_6 = |dividendMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_27 = dividendMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_28 = dividendMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_29 = dividendMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_30 = _dividendMSB_T_28 ? 2'h2 : {1'h0, _dividendMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_31 = _dividendMSB_T_27 ? 2'h3 : _dividendMSB_T_30; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_32 = dividendMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_33 = dividendMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_34 = dividendMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_35 = _dividendMSB_T_33 ? 2'h2 : {1'h0, _dividendMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_36 = _dividendMSB_T_32 ? 2'h3 : _dividendMSB_T_35; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_37 = dividendMSB_useHi_6 ? _dividendMSB_T_31 : _dividendMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_38 = {dividendMSB_useHi_6, _dividendMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_7 = dividendMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_7 = dividendMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_7 = |dividendMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_39 = dividendMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_40 = dividendMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_41 = dividendMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_42 = _dividendMSB_T_40 ? 2'h2 : {1'h0, _dividendMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_43 = _dividendMSB_T_39 ? 2'h3 : _dividendMSB_T_42; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_44 = dividendMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_45 = dividendMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_46 = dividendMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_47 = _dividendMSB_T_45 ? 2'h2 : {1'h0, _dividendMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_48 = _dividendMSB_T_44 ? 2'h3 : _dividendMSB_T_47; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_49 = dividendMSB_useHi_7 ? _dividendMSB_T_43 : _dividendMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_50 = {dividendMSB_useHi_7, _dividendMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_51 = dividendMSB_useHi_5 ? _dividendMSB_T_38 : _dividendMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_52 = {dividendMSB_useHi_5, _dividendMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_53 = dividendMSB_useHi_1 ? _dividendMSB_T_26 : _dividendMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_54 = {dividendMSB_useHi_1, _dividendMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [15:0] dividendMSB_hi_8 = dividendMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17] wire [15:0] dividendMSB_lo_8 = dividendMSB_lo[15:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_8 = |dividendMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] dividendMSB_hi_9 = dividendMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] dividendMSB_lo_9 = dividendMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_9 = |dividendMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_10 = dividendMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_10 = dividendMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_10 = |dividendMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_55 = dividendMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_56 = dividendMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_57 = dividendMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_58 = _dividendMSB_T_56 ? 2'h2 : {1'h0, _dividendMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_59 = _dividendMSB_T_55 ? 2'h3 : _dividendMSB_T_58; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_60 = dividendMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_61 = dividendMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_62 = dividendMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_63 = _dividendMSB_T_61 ? 2'h2 : {1'h0, _dividendMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_64 = _dividendMSB_T_60 ? 2'h3 : _dividendMSB_T_63; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_65 = dividendMSB_useHi_10 ? _dividendMSB_T_59 : _dividendMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_66 = {dividendMSB_useHi_10, _dividendMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_11 = dividendMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_11 = dividendMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_11 = |dividendMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_67 = dividendMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_68 = dividendMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_69 = dividendMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_70 = _dividendMSB_T_68 ? 2'h2 : {1'h0, _dividendMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_71 = _dividendMSB_T_67 ? 2'h3 : _dividendMSB_T_70; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_72 = dividendMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_73 = dividendMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_74 = dividendMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_75 = _dividendMSB_T_73 ? 2'h2 : {1'h0, _dividendMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_76 = _dividendMSB_T_72 ? 2'h3 : _dividendMSB_T_75; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_77 = dividendMSB_useHi_11 ? _dividendMSB_T_71 : _dividendMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_78 = {dividendMSB_useHi_11, _dividendMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_79 = dividendMSB_useHi_9 ? _dividendMSB_T_66 : _dividendMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_80 = {dividendMSB_useHi_9, _dividendMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] dividendMSB_hi_12 = dividendMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] dividendMSB_lo_12 = dividendMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_12 = |dividendMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_13 = dividendMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_13 = dividendMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_13 = |dividendMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_81 = dividendMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_82 = dividendMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_83 = dividendMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_84 = _dividendMSB_T_82 ? 2'h2 : {1'h0, _dividendMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_85 = _dividendMSB_T_81 ? 2'h3 : _dividendMSB_T_84; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_86 = dividendMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_87 = dividendMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_88 = dividendMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_89 = _dividendMSB_T_87 ? 2'h2 : {1'h0, _dividendMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_90 = _dividendMSB_T_86 ? 2'h3 : _dividendMSB_T_89; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_91 = dividendMSB_useHi_13 ? _dividendMSB_T_85 : _dividendMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_92 = {dividendMSB_useHi_13, _dividendMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_14 = dividendMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_14 = dividendMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_14 = |dividendMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_93 = dividendMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_94 = dividendMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_95 = dividendMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_96 = _dividendMSB_T_94 ? 2'h2 : {1'h0, _dividendMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_97 = _dividendMSB_T_93 ? 2'h3 : _dividendMSB_T_96; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_98 = dividendMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_99 = dividendMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_100 = dividendMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_101 = _dividendMSB_T_99 ? 2'h2 : {1'h0, _dividendMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_102 = _dividendMSB_T_98 ? 2'h3 : _dividendMSB_T_101; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_103 = dividendMSB_useHi_14 ? _dividendMSB_T_97 : _dividendMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_104 = {dividendMSB_useHi_14, _dividendMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_105 = dividendMSB_useHi_12 ? _dividendMSB_T_92 : _dividendMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_106 = {dividendMSB_useHi_12, _dividendMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_107 = dividendMSB_useHi_8 ? _dividendMSB_T_80 : _dividendMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_108 = {dividendMSB_useHi_8, _dividendMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_109 = dividendMSB_useHi ? _dividendMSB_T_54 : _dividendMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] _dividendMSB_T_110 = {dividendMSB_useHi, _dividendMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] dividendMSB = _dividendMSB_T_110; // @[CircuitMath.scala:36:10] wire [6:0] _eOutPos_T = {1'h0, dividendMSB} - {1'h0, divisorMSB}; // @[Multiplier.scala:150:48, :151:51, :152:35] wire [5:0] _eOutPos_T_1 = _eOutPos_T[5:0]; // @[Multiplier.scala:152:35] wire [5:0] eOutPos = ~_eOutPos_T_1; // @[Multiplier.scala:152:{21,35}] wire [5:0] _count_T_4 = eOutPos; // @[Multiplier.scala:152:21, :156:26] wire _eOut_T_9 = ~(|count); // @[Multiplier.scala:54:18, :117:83, :146:24, :153:24] wire _eOut_T_10 = ~divby0; // @[Multiplier.scala:146:32, :153:35] wire _eOut_T_11 = _eOut_T_9 & _eOut_T_10; // @[Multiplier.scala:153:{24,32,35}] wire _eOut_T_12 = |eOutPos; // @[Multiplier.scala:152:21, :153:54] wire eOut_1 = _eOut_T_11 & _eOut_T_12; // @[Multiplier.scala:153:{32,43,54}] wire [126:0] _remainder_T_4 = {63'h0, _remainder_T_3} << eOutPos; // @[Multiplier.scala:152:21, :155:{31,39}] wire _state_T_1 = lhs_sign | rhs_sign; // @[Multiplier.scala:81:23, :165:46] wire [2:0] _state_T_2 = {1'h0, ~_state_T_1, 1'h1}; // @[Multiplier.scala:165:{36,46}] wire [2:0] _state_T_3 = cmdMul ? 3'h2 : _state_T_2; // @[Multiplier.scala:75:107, :165:{17,36}] wire _count_T_6 = _count_T_5; // @[Multiplier.scala:78:{50,60}] wire _count_T_7 = cmdMul & _count_T_6; // @[Multiplier.scala:75:107, :78:50, :168:46] wire [5:0] _count_T_8 = {_count_T_7, 5'h0}; // @[Multiplier.scala:168:{38,46}] wire _neg_out_T = lhs_sign != rhs_sign; // @[Multiplier.scala:81:23, :169:46] wire _neg_out_T_1 = cmdHi ? lhs_sign : _neg_out_T; // @[Multiplier.scala:75:107, :81:23, :169:{19,46}] wire [64:0] _divisor_T = {rhs_sign, rhs_in}; // @[Multiplier.scala:81:23, :83:9, :170:19] wire [2:0] _outMul_T_1 = state & 3'h1; // @[Multiplier.scala:51:22, :175:23] wire outMul = _outMul_T_1 == 3'h0; // @[Multiplier.scala:175:{23,52}] wire _loOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60] wire _loOut_T_1 = _loOut_T; // @[Multiplier.scala:78:{50,60}] wire _loOut_T_2 = _loOut_T_1; // @[Multiplier.scala:78:50, :176:30] wire _loOut_T_3 = _loOut_T_2 & outMul; // @[Multiplier.scala:175:52, :176:{30,48}] wire [31:0] _loOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65] wire [31:0] _hiOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65, :177:66] wire [31:0] _loOut_T_5 = result[31:0]; // @[Multiplier.scala:89:19, :176:82] wire [31:0] loOut = _loOut_T_3 ? _loOut_T_4 : _loOut_T_5; // @[Multiplier.scala:176:{18,48,65,82}] wire _hiOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60] wire _hiOut_T_1 = _hiOut_T; // @[Multiplier.scala:78:{50,60}] wire _hiOut_T_2 = loOut[31]; // @[Multiplier.scala:176:18, :177:50] wire [31:0] _hiOut_T_3 = {32{_hiOut_T_2}}; // @[Multiplier.scala:177:{39,50}] wire [31:0] hiOut = _hiOut_T_1 ? _hiOut_T_3 : _hiOut_T_4; // @[Multiplier.scala:78:50, :177:{18,39,66}] assign _io_resp_bits_data_T = {hiOut, loOut}; // @[Multiplier.scala:176:18, :177:18, :180:27] assign io_resp_bits_data_0 = _io_resp_bits_data_T; // @[Multiplier.scala:40:7, :180:27] assign _io_resp_bits_full_data_T_2 = {_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1}; // @[Multiplier.scala:181:{32,42,63}] assign io_resp_bits_full_data = _io_resp_bits_full_data_T_2; // @[Multiplier.scala:40:7, :181:32] wire _io_resp_valid_T = state == 3'h6; // @[Multiplier.scala:51:22, :182:27] wire _io_resp_valid_T_1 = &state; // @[Multiplier.scala:51:22, :182:51] assign _io_resp_valid_T_2 = _io_resp_valid_T | _io_resp_valid_T_1; // @[Multiplier.scala:182:{27,42,51}] assign io_resp_valid_0 = _io_resp_valid_T_2; // @[Multiplier.scala:40:7, :182:42] assign _io_req_ready_T = state == 3'h0; // @[Multiplier.scala:51:22, :183:25] assign io_req_ready_0 = _io_req_ready_T; // @[Multiplier.scala:40:7, :183:25] wire _T_10 = state == 3'h1; // @[Multiplier.scala:51:22, :92:39] wire _T_13 = state == 3'h5; // @[Multiplier.scala:51:22, :101:39] wire _T_14 = state == 3'h2; // @[Multiplier.scala:51:22, :106:39] wire _GEN_1 = _T_14 & count == 7'h3F; // @[Multiplier.scala:54:18, :101:57, :106:{39,50}, :124:{25,55}, :125:13] wire _T_17 = state == 3'h3; // @[Multiplier.scala:51:22, :129:39] wire _T_18 = count == 7'h40; // @[Multiplier.scala:54:18, :138:17] wire _T_23 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Multiplier.scala:40:7] if (reset) // @[Multiplier.scala:40:7] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_T_23) // @[Decoupled.scala:51:35] state <= _state_T_3; // @[Multiplier.scala:51:22, :165:17] else if (io_resp_ready_0 & io_resp_valid_0 | io_kill_0) // @[Decoupled.scala:51:35] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_T_17 & _T_18) // @[Multiplier.scala:106:50, :129:{39,50}, :138:{17,42}, :139:13] state <= _state_T; // @[Multiplier.scala:51:22, :139:19] else if (_GEN_1) // @[Multiplier.scala:101:57, :106:50, :124:55, :125:13] state <= 3'h6; // @[Multiplier.scala:51:22] else if (_T_13) // @[Multiplier.scala:101:39] state <= 3'h7; // @[Multiplier.scala:51:22] else if (_T_10) // @[Multiplier.scala:92:39] state <= 3'h3; // @[Multiplier.scala:51:22] if (_T_23) begin // @[Decoupled.scala:51:35] req_fn <= io_req_bits_fn_0; // @[Multiplier.scala:40:7, :53:16] req_dw <= io_req_bits_dw_0; // @[Multiplier.scala:40:7, :53:16] req_in1 <= io_req_bits_in1_0; // @[Multiplier.scala:40:7, :53:16] req_in2 <= io_req_bits_in2_0; // @[Multiplier.scala:40:7, :53:16] count <= {1'h0, _count_T_8}; // @[Multiplier.scala:54:18, :168:{11,38}] isHi <= cmdHi; // @[Multiplier.scala:58:17, :75:107] divisor <= _divisor_T; // @[Multiplier.scala:60:20, :170:19] remainder <= {66'h0, lhs_in}; // @[Multiplier.scala:61:22, :83:9, :94:17, :171:15] end else begin // @[Decoupled.scala:51:35] if (_T_17) begin // @[Multiplier.scala:129:39] count <= eOut_1 ? {1'h0, _count_T_4} : _count_T_3; // @[Multiplier.scala:54:18, :144:{11,20}, :153:43, :154:19, :156:{15,26}] remainder <= eOut_1 ? {3'h0, _remainder_T_4} : {1'h0, unrolls_0}; // @[Multiplier.scala:61:22, :134:10, :137:15, :153:43, :154:19, :155:{19,39}] end else if (_T_14) begin // @[Multiplier.scala:106:39] count <= _count_T_1; // @[Multiplier.scala:54:18, :123:20] remainder <= _remainder_T_2; // @[Multiplier.scala:61:22, :121:21] end else if (_T_13 | _T_10 & remainder[63]) // @[Multiplier.scala:61:22, :92:{39,57}, :93:{20,27}, :94:17, :101:{39,57}, :102:15] remainder <= {66'h0, negated_remainder}; // @[Multiplier.scala:61:22, :90:27, :94:17] if (_T_10 & divisor[63]) // @[Multiplier.scala:60:20, :92:{39,57}, :96:{18,25}, :97:15] divisor <= subtractor; // @[Multiplier.scala:60:20, :88:37] end neg_out <= _T_23 ? _neg_out_T_1 : ~(_T_17 & divby0 & ~isHi) & neg_out; // @[Decoupled.scala:51:35] resHi <= ~_T_23 & (_T_17 & _T_18 | _GEN_1 ? isHi : ~_T_13 & resHi); // @[Decoupled.scala:51:35] always @(posedge) assign io_req_ready = io_req_ready_0; // @[Multiplier.scala:40:7] assign io_resp_valid = io_resp_valid_0; // @[Multiplier.scala:40:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[Multiplier.scala:40:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_319 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_319( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_12 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_12( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSource_TLBundleA_a9d32s1k1z2u : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, async : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} wire sink_ready : UInt<1> connect sink_ready, UInt<1>(0h1) reg mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], clock node _widx_T = asAsyncReset(reset) node _widx_T_1 = and(io.enq.ready, io.enq.valid) node _widx_T_2 = eq(sink_ready, UInt<1>(0h0)) wire widx_incremented : UInt<1> regreset widx_widx_bin : UInt, clock, _widx_T, UInt<1>(0h0) connect widx_widx_bin, widx_incremented node _widx_incremented_T = add(widx_widx_bin, _widx_T_1) node _widx_incremented_T_1 = tail(_widx_incremented_T, 1) node _widx_incremented_T_2 = mux(_widx_T_2, UInt<1>(0h0), _widx_incremented_T_1) connect widx_incremented, _widx_incremented_T_2 node _widx_T_3 = shr(widx_incremented, 1) node widx = xor(widx_incremented, _widx_T_3) inst ridx_ridx_gray of AsyncResetSynchronizerShiftReg_w1_d3_i0 connect ridx_ridx_gray.clock, clock connect ridx_ridx_gray.reset, reset connect ridx_ridx_gray.io.d, io.async.ridx wire ridx : UInt<1> connect ridx, ridx_ridx_gray.io.q node _ready_T = xor(ridx, UInt<1>(0h1)) node _ready_T_1 = neq(widx, _ready_T) node ready = and(sink_ready, _ready_T_1) node _T = and(io.enq.ready, io.enq.valid) when _T : connect mem[0], io.enq.bits node _ready_reg_T = asAsyncReset(reset) regreset ready_reg : UInt<1>, clock, _ready_reg_T, UInt<1>(0h0) connect ready_reg, ready node _io_enq_ready_T = and(ready_reg, sink_ready) connect io.enq.ready, _io_enq_ready_T node _widx_reg_T = asAsyncReset(reset) regreset widx_gray : UInt, clock, _widx_reg_T, UInt<1>(0h0) connect widx_gray, widx connect io.async.widx, widx_gray connect io.async.mem, mem inst source_valid_0 of AsyncValidSync inst source_valid_1 of AsyncValidSync_1 inst sink_extend of AsyncValidSync_2 inst sink_valid of AsyncValidSync_3 node _source_valid_0_reset_T = asUInt(reset) node _source_valid_0_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) node _source_valid_0_reset_T_2 = or(_source_valid_0_reset_T, _source_valid_0_reset_T_1) node _source_valid_0_reset_T_3 = asAsyncReset(_source_valid_0_reset_T_2) connect source_valid_0.reset, _source_valid_0_reset_T_3 node _source_valid_1_reset_T = asUInt(reset) node _source_valid_1_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) node _source_valid_1_reset_T_2 = or(_source_valid_1_reset_T, _source_valid_1_reset_T_1) node _source_valid_1_reset_T_3 = asAsyncReset(_source_valid_1_reset_T_2) connect source_valid_1.reset, _source_valid_1_reset_T_3 node _sink_extend_reset_T = asUInt(reset) node _sink_extend_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) node _sink_extend_reset_T_2 = or(_sink_extend_reset_T, _sink_extend_reset_T_1) node _sink_extend_reset_T_3 = asAsyncReset(_sink_extend_reset_T_2) connect sink_extend.reset, _sink_extend_reset_T_3 node _sink_valid_reset_T = asAsyncReset(reset) connect sink_valid.reset, _sink_valid_reset_T connect source_valid_0.clock, clock connect source_valid_1.clock, clock connect sink_extend.clock, clock connect sink_valid.clock, clock connect source_valid_0.io.in, UInt<1>(0h1) connect source_valid_1.io.in, source_valid_0.io.out connect io.async.safe.widx_valid, source_valid_1.io.out connect sink_extend.io.in, io.async.safe.ridx_valid connect sink_valid.io.in, sink_extend.io.out connect sink_ready, sink_valid.io.out node _io_async_safe_source_reset_n_T = asUInt(reset) node _io_async_safe_source_reset_n_T_1 = eq(_io_async_safe_source_reset_n_T, UInt<1>(0h0)) connect io.async.safe.source_reset_n, _io_async_safe_source_reset_n_T_1
module AsyncQueueSource_TLBundleA_a9d32s1k1z2u( // @[AsyncQueue.scala:70:7] input clock, // @[AsyncQueue.scala:70:7] input reset, // @[AsyncQueue.scala:70:7] output io_enq_ready, // @[AsyncQueue.scala:73:14] input io_enq_valid, // @[AsyncQueue.scala:73:14] input [2:0] io_enq_bits_opcode, // @[AsyncQueue.scala:73:14] input [8:0] io_enq_bits_address, // @[AsyncQueue.scala:73:14] input [31:0] io_enq_bits_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_0_opcode, // @[AsyncQueue.scala:73:14] output [8:0] io_async_mem_0_address, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_0_data, // @[AsyncQueue.scala:73:14] input io_async_ridx, // @[AsyncQueue.scala:73:14] output io_async_widx, // @[AsyncQueue.scala:73:14] input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14] input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14] ); wire io_enq_ready_0; // @[AsyncQueue.scala:91:29] wire _sink_valid_io_out; // @[AsyncQueue.scala:106:30] wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30] wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32] wire _ridx_ridx_gray_io_q; // @[ShiftReg.scala:45:23] reg [2:0] mem_0_opcode; // @[AsyncQueue.scala:82:16] reg [8:0] mem_0_address; // @[AsyncQueue.scala:82:16] reg [31:0] mem_0_data; // @[AsyncQueue.scala:82:16] wire _widx_T_1 = io_enq_ready_0 & io_enq_valid; // @[Decoupled.scala:51:35] reg widx_widx_bin; // @[AsyncQueue.scala:52:25] reg ready_reg; // @[AsyncQueue.scala:90:56] assign io_enq_ready_0 = ready_reg & _sink_valid_io_out; // @[AsyncQueue.scala:90:56, :91:29, :106:30] reg widx_gray; // @[AsyncQueue.scala:93:55] always @(posedge clock) begin // @[AsyncQueue.scala:70:7] if (_widx_T_1) begin // @[Decoupled.scala:51:35] mem_0_opcode <= io_enq_bits_opcode; // @[AsyncQueue.scala:82:16] mem_0_address <= io_enq_bits_address; // @[AsyncQueue.scala:82:16] mem_0_data <= io_enq_bits_data; // @[AsyncQueue.scala:82:16] end always @(posedge) wire widx = _sink_valid_io_out & widx_widx_bin + _widx_T_1; // @[Decoupled.scala:51:35] always @(posedge clock or posedge reset) begin // @[AsyncQueue.scala:70:7] if (reset) begin // @[AsyncQueue.scala:70:7] widx_widx_bin <= 1'h0; // @[AsyncQueue.scala:52:25, :70:7] ready_reg <= 1'h0; // @[AsyncQueue.scala:70:7, :90:56] widx_gray <= 1'h0; // @[AsyncQueue.scala:70:7, :93:55] end else begin // @[AsyncQueue.scala:70:7] widx_widx_bin <= widx; // @[AsyncQueue.scala:52:25, :53:23] ready_reg <= _sink_valid_io_out & widx != ~_ridx_ridx_gray_io_q; // @[ShiftReg.scala:45:23] widx_gray <= widx; // @[AsyncQueue.scala:53:23, :93:55] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module Tile_65 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_321 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_65( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_321 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_3 : input clock : Clock input reset : Reset output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmp0_WIRE.mask, UInt<32>(0h0) connect _pmp0_WIRE.addr, UInt<30>(0h0) connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp0, _pmp0_WIRE connect pmp0.cfg.r, UInt<1>(0h1) connect pmp0.cfg.w, UInt<1>(0h1) connect pmp0.cfg.x, UInt<1>(0h1) connect io.r, pmp0.cfg.r connect io.w, pmp0.cfg.w connect io.x, pmp0.cfg.x
module PMPChecker_s3_3( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [31:0] io_addr, // @[PMP.scala:146:14] input [1:0] io_size // @[PMP.scala:146:14] ); wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire io_r = 1'h1; // @[PMP.scala:143:7] wire io_w = 1'h1; // @[PMP.scala:143:7] wire io_x = 1'h1; // @[PMP.scala:143:7] wire pmp0_cfg_x = 1'h1; // @[PMP.scala:157:22] wire pmp0_cfg_w = 1'h1; // @[PMP.scala:157:22] wire pmp0_cfg_r = 1'h1; // @[PMP.scala:157:22] wire [1:0] io_prv = 2'h1; // @[PMP.scala:143:7, :146:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_48 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_304 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_48( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_304 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BoomDuplicatedDataArray_1 : input clock : Clock input reset : Reset output io : { flip read : { valid : UInt<1>, bits : { way_en : UInt<2>, addr : UInt<10>}}[1], flip write : { valid : UInt<1>, bits : { way_en : UInt<2>, addr : UInt<10>, wmask : UInt<1>, data : UInt<64>}}, resp : UInt<64>[2][1], s1_nacks : UInt<1>[1]} node waddr = shr(io.write.bits.addr, 3) node raddr = shr(io.read[0].bits.addr, 3) smem array_0_0 : UInt<64>[1] [128] node _T = bits(io.write.bits.way_en, 0, 0) node _T_1 = and(_T, io.write.valid) when _T_1 : node _data_T = bits(io.write.bits.data, 63, 0) wire data : UInt<64>[1] connect data[0], _data_T node _T_2 = bits(io.write.bits.wmask, 0, 0) write mport MPORT = array_0_0[waddr], clock when _T_2 : connect MPORT[0], data[0] wire _io_resp_0_0_WIRE : UInt<7> invalidate _io_resp_0_0_WIRE when io.read[0].valid : connect _io_resp_0_0_WIRE, raddr read mport io_resp_0_0_MPORT = array_0_0[_io_resp_0_0_WIRE], clock reg io_resp_0_0_REG : UInt, clock connect io_resp_0_0_REG, io_resp_0_0_MPORT[0] connect io.resp[0][0], io_resp_0_0_REG smem array_1_0 : UInt<64>[1] [128] node _T_3 = bits(io.write.bits.way_en, 1, 1) node _T_4 = and(_T_3, io.write.valid) when _T_4 : node _data_T_1 = bits(io.write.bits.data, 63, 0) wire data_1 : UInt<64>[1] connect data_1[0], _data_T_1 node _T_5 = bits(io.write.bits.wmask, 0, 0) write mport MPORT_1 = array_1_0[waddr], clock when _T_5 : connect MPORT_1[0], data_1[0] wire _io_resp_0_1_WIRE : UInt<7> invalidate _io_resp_0_1_WIRE when io.read[0].valid : connect _io_resp_0_1_WIRE, raddr read mport io_resp_0_1_MPORT = array_1_0[_io_resp_0_1_WIRE], clock reg io_resp_0_1_REG : UInt, clock connect io_resp_0_1_REG, io_resp_0_1_MPORT[0] connect io.resp[0][1], io_resp_0_1_REG connect io.s1_nacks[0], UInt<1>(0h0)
module BoomDuplicatedDataArray_1( // @[dcache.scala:281:7] input clock, // @[dcache.scala:281:7] input reset, // @[dcache.scala:281:7] input io_read_0_valid, // @[dcache.scala:270:14] input [1:0] io_read_0_bits_way_en, // @[dcache.scala:270:14] input [9:0] io_read_0_bits_addr, // @[dcache.scala:270:14] input io_write_valid, // @[dcache.scala:270:14] input [1:0] io_write_bits_way_en, // @[dcache.scala:270:14] input [9:0] io_write_bits_addr, // @[dcache.scala:270:14] input [63:0] io_write_bits_data, // @[dcache.scala:270:14] output [63:0] io_resp_0_0, // @[dcache.scala:270:14] output [63:0] io_resp_0_1 // @[dcache.scala:270:14] ); wire [63:0] _array_1_0_0_R0_data; // @[DescribedSRAM.scala:17:26] wire [63:0] _array_0_0_0_R0_data; // @[DescribedSRAM.scala:17:26] wire io_read_0_valid_0 = io_read_0_valid; // @[dcache.scala:281:7] wire [1:0] io_read_0_bits_way_en_0 = io_read_0_bits_way_en; // @[dcache.scala:281:7] wire [9:0] io_read_0_bits_addr_0 = io_read_0_bits_addr; // @[dcache.scala:281:7] wire io_write_valid_0 = io_write_valid; // @[dcache.scala:281:7] wire [1:0] io_write_bits_way_en_0 = io_write_bits_way_en; // @[dcache.scala:281:7] wire [9:0] io_write_bits_addr_0 = io_write_bits_addr; // @[dcache.scala:281:7] wire [63:0] io_write_bits_data_0 = io_write_bits_data; // @[dcache.scala:281:7] wire io_s1_nacks_0 = 1'h0; // @[dcache.scala:281:7] wire io_write_bits_wmask = 1'h1; // @[DescribedSRAM.scala:17:26] wire [63:0] _data_T = io_write_bits_data_0; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_1 = io_write_bits_data_0; // @[dcache.scala:281:7, :296:75] wire [63:0] io_resp_0_0_0; // @[dcache.scala:281:7] wire [63:0] io_resp_0_1_0; // @[dcache.scala:281:7] wire [6:0] waddr = io_write_bits_addr_0[9:3]; // @[dcache.scala:281:7, :284:34] wire [6:0] raddr = io_read_0_bits_addr_0[9:3]; // @[dcache.scala:281:7, :287:38] wire [6:0] _io_resp_0_0_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [6:0] _io_resp_0_1_WIRE = raddr; // @[dcache.scala:287:38, :302:44] wire [63:0] data_0 = _data_T; // @[dcache.scala:296:{27,75}] reg [63:0] io_resp_0_0_REG; // @[dcache.scala:302:33] assign io_resp_0_0_0 = io_resp_0_0_REG; // @[dcache.scala:281:7, :302:33] wire [63:0] data_1_0 = _data_T_1; // @[dcache.scala:296:{27,75}] reg [63:0] io_resp_0_1_REG; // @[dcache.scala:302:33] assign io_resp_0_1_0 = io_resp_0_1_REG; // @[dcache.scala:281:7, :302:33] always @(posedge clock) begin // @[dcache.scala:281:7] io_resp_0_0_REG <= _array_0_0_0_R0_data; // @[DescribedSRAM.scala:17:26] io_resp_0_1_REG <= _array_1_0_0_R0_data; // @[DescribedSRAM.scala:17:26] always @(posedge) array_0_0_0_0 array_0_0_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_0_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_array_0_0_0_R0_data), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[0] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data (data_0) // @[dcache.scala:296:27] ); // @[DescribedSRAM.scala:17:26] array_1_0_0_0 array_1_0_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_1_WIRE), // @[dcache.scala:302:44] .R0_en (io_read_0_valid_0), // @[dcache.scala:281:7] .R0_clk (clock), .R0_data (_array_1_0_0_R0_data), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[1] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data (data_1_0) // @[dcache.scala:296:27] ); // @[DescribedSRAM.scala:17:26] assign io_resp_0_0 = io_resp_0_0_0; // @[dcache.scala:281:7] assign io_resp_0_1 = io_resp_0_1_0; // @[dcache.scala:281:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_7 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_7( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_60 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_60( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_40 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_80 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_81 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/shuttle/src/main/scala/common/Tile.scala:159:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_40( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [7:0] io_in_a_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_a_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [3:0] mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi = 4'hF; // @[Misc.scala:222:10] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [8:0] a_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_1 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_2 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_2; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_2; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_3 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1184 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1153 = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :673:46, :674:74, :678:{25,70}] assign d_clr = _T_1153 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1153 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1153 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1238 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :783:46, :788:{25,70}] assign d_clr_1 = _T_1238 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1238 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1238 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_37 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_74 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_37 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<2>(0h2), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h14), io.in.bits.egress_id) node _T_2 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _T_3 = eq(UInt<3>(0h5), io.in.bits.egress_id) node _T_4 = eq(UInt<5>(0h17), io.in.bits.egress_id) node _T_5 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _T_6 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _T_7 = eq(UInt<4>(0he), io.in.bits.egress_id) node _T_8 = or(_T, _T_1) node _T_9 = or(_T_8, _T_2) node _T_10 = or(_T_9, _T_3) node _T_11 = or(_T_10, _T_4) node _T_12 = or(_T_11, _T_5) node _T_13 = or(_T_12, _T_6) node _T_14 = or(_T_13, _T_7) node _T_15 = eq(_T_14, UInt<1>(0h0)) node _T_16 = and(io.in.valid, _T_15) node _T_17 = eq(_T_16, UInt<1>(0h0)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_17, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<3>(0h4) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<2>(0h2), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h14), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<3>(0h5), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<5>(0h17), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h7), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<4>(0h8), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_5, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_6, UInt<2>(0h3), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_7, UInt<3>(0h4), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_16 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_9) node _route_buffer_io_enq_bits_flow_egress_node_T_17 = or(_route_buffer_io_enq_bits_flow_egress_node_T_16, _route_buffer_io_enq_bits_flow_egress_node_T_10) node _route_buffer_io_enq_bits_flow_egress_node_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_T_17, _route_buffer_io_enq_bits_flow_egress_node_T_11) node _route_buffer_io_enq_bits_flow_egress_node_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_T_18, _route_buffer_io_enq_bits_flow_egress_node_T_12) node _route_buffer_io_enq_bits_flow_egress_node_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_T_19, _route_buffer_io_enq_bits_flow_egress_node_T_13) node _route_buffer_io_enq_bits_flow_egress_node_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_T_20, _route_buffer_io_enq_bits_flow_egress_node_T_14) node _route_buffer_io_enq_bits_flow_egress_node_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_T_21, _route_buffer_io_enq_bits_flow_egress_node_T_15) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_22 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<2>(0h2), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h14), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<3>(0h5), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<5>(0h17), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_6, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_7, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_16 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_9) node _route_buffer_io_enq_bits_flow_egress_node_id_T_17 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_16, _route_buffer_io_enq_bits_flow_egress_node_id_T_10) node _route_buffer_io_enq_bits_flow_egress_node_id_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_17, _route_buffer_io_enq_bits_flow_egress_node_id_T_11) node _route_buffer_io_enq_bits_flow_egress_node_id_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_18, _route_buffer_io_enq_bits_flow_egress_node_id_T_12) node _route_buffer_io_enq_bits_flow_egress_node_id_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_19, _route_buffer_io_enq_bits_flow_egress_node_id_T_13) node _route_buffer_io_enq_bits_flow_egress_node_id_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_20, _route_buffer_io_enq_bits_flow_egress_node_id_T_14) node _route_buffer_io_enq_bits_flow_egress_node_id_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_21, _route_buffer_io_enq_bits_flow_egress_node_id_T_15) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_22 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_21 = and(io.in.ready, io.in.valid) node _T_22 = and(_T_21, io.in.bits.head) node _T_23 = and(_T_22, at_dest) when _T_23 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_24 = eq(UInt<1>(0h0), io.in.bits.egress_id) when _T_24 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_25 = eq(UInt<1>(0h1), io.in.bits.egress_id) when _T_25 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_26 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_27 = and(route_q.io.enq.valid, _T_26) node _T_28 = eq(_T_27, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_28, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_75 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_37 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_32 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_33 = and(vcalloc_q.io.enq.valid, _T_32) node _T_34 = eq(_T_33, UInt<1>(0h0)) node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : node _T_37 = eq(_T_34, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_34, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _c_T = cat(c_hi, c_lo) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _c_T_1 = cat(c_hi_1, _c_T) node c_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_hi_2 = cat(c_hi_hi_1, io.out_credit_available.`0`[2]) node _c_T_2 = cat(c_hi_2, c_lo_1) node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _c_T_3 = cat(c_hi_3, _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_channel_oh_0 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 4, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_11 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_10) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_12 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1
module IngressUnit_37( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h2; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h14; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'hB; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h5; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h17; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h8; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72] wire [2:0] _route_buffer_io_enq_bits_flow_egress_node_T_17 = {2'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T} | {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_1}} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 3'h5 : 3'h0); // @[Mux.scala:30:73] wire [2:0] _GEN = {_route_buffer_io_enq_bits_flow_egress_node_T_17[2], _route_buffer_io_enq_bits_flow_egress_node_T_17[1:0] | {_route_buffer_io_enq_bits_flow_egress_node_id_T_3, 1'h0}} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 3'h6 : 3'h0); // @[Mux.scala:30:73] wire [1:0] _GEN_0 = _GEN[1:0] | {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_6}}; // @[Mux.scala:30:73] wire _GEN_1 = _GEN[2] | _route_buffer_io_enq_bits_flow_egress_node_id_T_7; // @[Mux.scala:30:73] wire [3:0] _GEN_2 = {_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _GEN_1, _GEN_0}; // @[Mux.scala:30:73] wire _GEN_3 = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & ~(|_GEN_2); // @[Decoupled.scala:51:35] wire route_q_io_enq_valid = _GEN_3 | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & (|_GEN_2); // @[Decoupled.scala:51:35] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_33 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[30] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[2]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[3]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[4]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[5]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[6]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[7]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[8]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[9]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[10]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[11]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[12]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[13]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[14]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[15]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[16]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[17]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[18]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[19]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[20]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[21]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[22]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[23]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[24]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[25]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[26]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[27]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[28]) node source_ok = or(_source_ok_T_77, _source_ok_WIRE[29]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = and(_T_11, _T_24) node _T_265 = and(_T_264, _T_37) node _T_266 = and(_T_265, _T_50) node _T_267 = and(_T_266, _T_63) node _T_268 = and(_T_267, _T_71) node _T_269 = and(_T_268, _T_79) node _T_270 = and(_T_269, _T_87) node _T_271 = and(_T_270, _T_95) node _T_272 = and(_T_271, _T_103) node _T_273 = and(_T_272, _T_111) node _T_274 = and(_T_273, _T_119) node _T_275 = and(_T_274, _T_127) node _T_276 = and(_T_275, _T_135) node _T_277 = and(_T_276, _T_143) node _T_278 = and(_T_277, _T_151) node _T_279 = and(_T_278, _T_159) node _T_280 = and(_T_279, _T_167) node _T_281 = and(_T_280, _T_175) node _T_282 = and(_T_281, _T_183) node _T_283 = and(_T_282, _T_191) node _T_284 = and(_T_283, _T_199) node _T_285 = and(_T_284, _T_207) node _T_286 = and(_T_285, _T_215) node _T_287 = and(_T_286, _T_223) node _T_288 = and(_T_287, _T_231) node _T_289 = and(_T_288, _T_239) node _T_290 = and(_T_289, _T_247) node _T_291 = and(_T_290, _T_255) node _T_292 = and(_T_291, _T_263) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_292, UInt<1>(0h1), "") : assert_1 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_296 : node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<1>(0h0)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_4) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<1>(0h1)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_5) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<2>(0h2)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_6) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<2>(0h3)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_7) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_342 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_343 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_350 = or(_T_300, _T_306) node _T_351 = or(_T_350, _T_312) node _T_352 = or(_T_351, _T_318) node _T_353 = or(_T_352, _T_324) node _T_354 = or(_T_353, _T_325) node _T_355 = or(_T_354, _T_326) node _T_356 = or(_T_355, _T_327) node _T_357 = or(_T_356, _T_328) node _T_358 = or(_T_357, _T_329) node _T_359 = or(_T_358, _T_330) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_332) node _T_362 = or(_T_361, _T_333) node _T_363 = or(_T_362, _T_334) node _T_364 = or(_T_363, _T_335) node _T_365 = or(_T_364, _T_336) node _T_366 = or(_T_365, _T_337) node _T_367 = or(_T_366, _T_338) node _T_368 = or(_T_367, _T_339) node _T_369 = or(_T_368, _T_340) node _T_370 = or(_T_369, _T_341) node _T_371 = or(_T_370, _T_342) node _T_372 = or(_T_371, _T_343) node _T_373 = or(_T_372, _T_344) node _T_374 = or(_T_373, _T_345) node _T_375 = or(_T_374, _T_346) node _T_376 = or(_T_375, _T_347) node _T_377 = or(_T_376, _T_348) node _T_378 = or(_T_377, _T_349) node _T_379 = and(_T_299, _T_378) node _T_380 = or(UInt<1>(0h0), _T_379) node _T_381 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = and(_T_381, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = and(_T_380, _T_388) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_389, UInt<1>(0h1), "") : assert_2 node _T_393 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_394 = shr(io.in.a.bits.source, 2) node _T_395 = eq(_T_394, UInt<1>(0h0)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_8) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_400 = shr(io.in.a.bits.source, 2) node _T_401 = eq(_T_400, UInt<1>(0h1)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_9) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_406 = shr(io.in.a.bits.source, 2) node _T_407 = eq(_T_406, UInt<2>(0h2)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_10) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_412 = shr(io.in.a.bits.source, 2) node _T_413 = eq(_T_412, UInt<2>(0h3)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_11) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_424 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_425 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_426 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_427 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_428 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_429 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_431 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_432 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_433 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[30] connect _WIRE[0], _T_393 connect _WIRE[1], _T_399 connect _WIRE[2], _T_405 connect _WIRE[3], _T_411 connect _WIRE[4], _T_417 connect _WIRE[5], _T_418 connect _WIRE[6], _T_419 connect _WIRE[7], _T_420 connect _WIRE[8], _T_421 connect _WIRE[9], _T_422 connect _WIRE[10], _T_423 connect _WIRE[11], _T_424 connect _WIRE[12], _T_425 connect _WIRE[13], _T_426 connect _WIRE[14], _T_427 connect _WIRE[15], _T_428 connect _WIRE[16], _T_429 connect _WIRE[17], _T_430 connect _WIRE[18], _T_431 connect _WIRE[19], _T_432 connect _WIRE[20], _T_433 connect _WIRE[21], _T_434 connect _WIRE[22], _T_435 connect _WIRE[23], _T_436 connect _WIRE[24], _T_437 connect _WIRE[25], _T_438 connect _WIRE[26], _T_439 connect _WIRE[27], _T_440 connect _WIRE[28], _T_441 connect _WIRE[29], _T_442 node _T_443 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_444 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_445 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_446 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_447 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_448 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_449 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_450 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_451 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_452 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_453 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_454 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_455 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_456 = mux(_WIRE[5], _T_443, UInt<1>(0h0)) node _T_457 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_458 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_459 = mux(_WIRE[8], _T_444, UInt<1>(0h0)) node _T_460 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_462 = mux(_WIRE[11], _T_445, UInt<1>(0h0)) node _T_463 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_464 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = mux(_WIRE[14], _T_446, UInt<1>(0h0)) node _T_466 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_468 = mux(_WIRE[17], _T_447, UInt<1>(0h0)) node _T_469 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_471 = mux(_WIRE[20], _T_448, UInt<1>(0h0)) node _T_472 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_473 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_474 = mux(_WIRE[23], _T_449, UInt<1>(0h0)) node _T_475 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_476 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_477 = mux(_WIRE[26], _T_450, UInt<1>(0h0)) node _T_478 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_479 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_480 = mux(_WIRE[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_481 = or(_T_451, _T_452) node _T_482 = or(_T_481, _T_453) node _T_483 = or(_T_482, _T_454) node _T_484 = or(_T_483, _T_455) node _T_485 = or(_T_484, _T_456) node _T_486 = or(_T_485, _T_457) node _T_487 = or(_T_486, _T_458) node _T_488 = or(_T_487, _T_459) node _T_489 = or(_T_488, _T_460) node _T_490 = or(_T_489, _T_461) node _T_491 = or(_T_490, _T_462) node _T_492 = or(_T_491, _T_463) node _T_493 = or(_T_492, _T_464) node _T_494 = or(_T_493, _T_465) node _T_495 = or(_T_494, _T_466) node _T_496 = or(_T_495, _T_467) node _T_497 = or(_T_496, _T_468) node _T_498 = or(_T_497, _T_469) node _T_499 = or(_T_498, _T_470) node _T_500 = or(_T_499, _T_471) node _T_501 = or(_T_500, _T_472) node _T_502 = or(_T_501, _T_473) node _T_503 = or(_T_502, _T_474) node _T_504 = or(_T_503, _T_475) node _T_505 = or(_T_504, _T_476) node _T_506 = or(_T_505, _T_477) node _T_507 = or(_T_506, _T_478) node _T_508 = or(_T_507, _T_479) node _T_509 = or(_T_508, _T_480) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_509 node _T_510 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_511 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_512 = and(_T_510, _T_511) node _T_513 = or(UInt<1>(0h0), _T_512) node _T_514 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<17>(0h10000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_WIRE_1, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_521, UInt<1>(0h1), "") : assert_3 node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(source_ok, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_528 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_528, UInt<1>(0h1), "") : assert_5 node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(is_aligned, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_535 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_535, UInt<1>(0h1), "") : assert_7 node _T_539 = not(io.in.a.bits.mask) node _T_540 = eq(_T_539, UInt<1>(0h0)) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_540, UInt<1>(0h1), "") : assert_8 node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_544, UInt<1>(0h1), "") : assert_9 node _T_548 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_548 : node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_553 = shr(io.in.a.bits.source, 2) node _T_554 = eq(_T_553, UInt<1>(0h0)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_12) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_558 = and(_T_556, _T_557) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_559 = shr(io.in.a.bits.source, 2) node _T_560 = eq(_T_559, UInt<1>(0h1)) node _T_561 = leq(UInt<1>(0h0), uncommonBits_13) node _T_562 = and(_T_560, _T_561) node _T_563 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_564 = and(_T_562, _T_563) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_565 = shr(io.in.a.bits.source, 2) node _T_566 = eq(_T_565, UInt<2>(0h2)) node _T_567 = leq(UInt<1>(0h0), uncommonBits_14) node _T_568 = and(_T_566, _T_567) node _T_569 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_570 = and(_T_568, _T_569) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_571 = shr(io.in.a.bits.source, 2) node _T_572 = eq(_T_571, UInt<2>(0h3)) node _T_573 = leq(UInt<1>(0h0), uncommonBits_15) node _T_574 = and(_T_572, _T_573) node _T_575 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_576 = and(_T_574, _T_575) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_586 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_587 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_591 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_592 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_601 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_602 = or(_T_552, _T_558) node _T_603 = or(_T_602, _T_564) node _T_604 = or(_T_603, _T_570) node _T_605 = or(_T_604, _T_576) node _T_606 = or(_T_605, _T_577) node _T_607 = or(_T_606, _T_578) node _T_608 = or(_T_607, _T_579) node _T_609 = or(_T_608, _T_580) node _T_610 = or(_T_609, _T_581) node _T_611 = or(_T_610, _T_582) node _T_612 = or(_T_611, _T_583) node _T_613 = or(_T_612, _T_584) node _T_614 = or(_T_613, _T_585) node _T_615 = or(_T_614, _T_586) node _T_616 = or(_T_615, _T_587) node _T_617 = or(_T_616, _T_588) node _T_618 = or(_T_617, _T_589) node _T_619 = or(_T_618, _T_590) node _T_620 = or(_T_619, _T_591) node _T_621 = or(_T_620, _T_592) node _T_622 = or(_T_621, _T_593) node _T_623 = or(_T_622, _T_594) node _T_624 = or(_T_623, _T_595) node _T_625 = or(_T_624, _T_596) node _T_626 = or(_T_625, _T_597) node _T_627 = or(_T_626, _T_598) node _T_628 = or(_T_627, _T_599) node _T_629 = or(_T_628, _T_600) node _T_630 = or(_T_629, _T_601) node _T_631 = and(_T_551, _T_630) node _T_632 = or(UInt<1>(0h0), _T_631) node _T_633 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<17>(0h10000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = and(_T_633, _T_638) node _T_640 = or(UInt<1>(0h0), _T_639) node _T_641 = and(_T_632, _T_640) node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(_T_641, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_641, UInt<1>(0h1), "") : assert_10 node _T_645 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_646 = shr(io.in.a.bits.source, 2) node _T_647 = eq(_T_646, UInt<1>(0h0)) node _T_648 = leq(UInt<1>(0h0), uncommonBits_16) node _T_649 = and(_T_647, _T_648) node _T_650 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_651 = and(_T_649, _T_650) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_652 = shr(io.in.a.bits.source, 2) node _T_653 = eq(_T_652, UInt<1>(0h1)) node _T_654 = leq(UInt<1>(0h0), uncommonBits_17) node _T_655 = and(_T_653, _T_654) node _T_656 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_657 = and(_T_655, _T_656) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_658 = shr(io.in.a.bits.source, 2) node _T_659 = eq(_T_658, UInt<2>(0h2)) node _T_660 = leq(UInt<1>(0h0), uncommonBits_18) node _T_661 = and(_T_659, _T_660) node _T_662 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_663 = and(_T_661, _T_662) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_664 = shr(io.in.a.bits.source, 2) node _T_665 = eq(_T_664, UInt<2>(0h3)) node _T_666 = leq(UInt<1>(0h0), uncommonBits_19) node _T_667 = and(_T_665, _T_666) node _T_668 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_669 = and(_T_667, _T_668) node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_673 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_674 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_675 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_678 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_679 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_680 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_682 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_685 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_694 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[30] connect _WIRE_2[0], _T_645 connect _WIRE_2[1], _T_651 connect _WIRE_2[2], _T_657 connect _WIRE_2[3], _T_663 connect _WIRE_2[4], _T_669 connect _WIRE_2[5], _T_670 connect _WIRE_2[6], _T_671 connect _WIRE_2[7], _T_672 connect _WIRE_2[8], _T_673 connect _WIRE_2[9], _T_674 connect _WIRE_2[10], _T_675 connect _WIRE_2[11], _T_676 connect _WIRE_2[12], _T_677 connect _WIRE_2[13], _T_678 connect _WIRE_2[14], _T_679 connect _WIRE_2[15], _T_680 connect _WIRE_2[16], _T_681 connect _WIRE_2[17], _T_682 connect _WIRE_2[18], _T_683 connect _WIRE_2[19], _T_684 connect _WIRE_2[20], _T_685 connect _WIRE_2[21], _T_686 connect _WIRE_2[22], _T_687 connect _WIRE_2[23], _T_688 connect _WIRE_2[24], _T_689 connect _WIRE_2[25], _T_690 connect _WIRE_2[26], _T_691 connect _WIRE_2[27], _T_692 connect _WIRE_2[28], _T_693 connect _WIRE_2[29], _T_694 node _T_695 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_696 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_697 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_698 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_699 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_700 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_701 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_702 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_703 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_704 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_705 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_707 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_708 = mux(_WIRE_2[5], _T_695, UInt<1>(0h0)) node _T_709 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_710 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_711 = mux(_WIRE_2[8], _T_696, UInt<1>(0h0)) node _T_712 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_713 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_714 = mux(_WIRE_2[11], _T_697, UInt<1>(0h0)) node _T_715 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_716 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_717 = mux(_WIRE_2[14], _T_698, UInt<1>(0h0)) node _T_718 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_720 = mux(_WIRE_2[17], _T_699, UInt<1>(0h0)) node _T_721 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_722 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_723 = mux(_WIRE_2[20], _T_700, UInt<1>(0h0)) node _T_724 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_725 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_726 = mux(_WIRE_2[23], _T_701, UInt<1>(0h0)) node _T_727 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_729 = mux(_WIRE_2[26], _T_702, UInt<1>(0h0)) node _T_730 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_731 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_732 = mux(_WIRE_2[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_733 = or(_T_703, _T_704) node _T_734 = or(_T_733, _T_705) node _T_735 = or(_T_734, _T_706) node _T_736 = or(_T_735, _T_707) node _T_737 = or(_T_736, _T_708) node _T_738 = or(_T_737, _T_709) node _T_739 = or(_T_738, _T_710) node _T_740 = or(_T_739, _T_711) node _T_741 = or(_T_740, _T_712) node _T_742 = or(_T_741, _T_713) node _T_743 = or(_T_742, _T_714) node _T_744 = or(_T_743, _T_715) node _T_745 = or(_T_744, _T_716) node _T_746 = or(_T_745, _T_717) node _T_747 = or(_T_746, _T_718) node _T_748 = or(_T_747, _T_719) node _T_749 = or(_T_748, _T_720) node _T_750 = or(_T_749, _T_721) node _T_751 = or(_T_750, _T_722) node _T_752 = or(_T_751, _T_723) node _T_753 = or(_T_752, _T_724) node _T_754 = or(_T_753, _T_725) node _T_755 = or(_T_754, _T_726) node _T_756 = or(_T_755, _T_727) node _T_757 = or(_T_756, _T_728) node _T_758 = or(_T_757, _T_729) node _T_759 = or(_T_758, _T_730) node _T_760 = or(_T_759, _T_731) node _T_761 = or(_T_760, _T_732) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_761 node _T_762 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_763 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_764 = and(_T_762, _T_763) node _T_765 = or(UInt<1>(0h0), _T_764) node _T_766 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<17>(0h10000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = and(_T_765, _T_770) node _T_772 = or(UInt<1>(0h0), _T_771) node _T_773 = and(_WIRE_3, _T_772) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_773, UInt<1>(0h1), "") : assert_11 node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(source_ok, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_780 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(_T_780, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_780, UInt<1>(0h1), "") : assert_13 node _T_784 = asUInt(reset) node _T_785 = eq(_T_784, UInt<1>(0h0)) when _T_785 : node _T_786 = eq(is_aligned, UInt<1>(0h0)) when _T_786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_787 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_T_787, UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_787, UInt<1>(0h1), "") : assert_15 node _T_791 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(_T_791, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_791, UInt<1>(0h1), "") : assert_16 node _T_795 = not(io.in.a.bits.mask) node _T_796 = eq(_T_795, UInt<1>(0h0)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_796, UInt<1>(0h1), "") : assert_17 node _T_800 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_800, UInt<1>(0h1), "") : assert_18 node _T_804 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<1>(0h0)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_20) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_815 = shr(io.in.a.bits.source, 2) node _T_816 = eq(_T_815, UInt<1>(0h1)) node _T_817 = leq(UInt<1>(0h0), uncommonBits_21) node _T_818 = and(_T_816, _T_817) node _T_819 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_820 = and(_T_818, _T_819) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_821 = shr(io.in.a.bits.source, 2) node _T_822 = eq(_T_821, UInt<2>(0h2)) node _T_823 = leq(UInt<1>(0h0), uncommonBits_22) node _T_824 = and(_T_822, _T_823) node _T_825 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_826 = and(_T_824, _T_825) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_827 = shr(io.in.a.bits.source, 2) node _T_828 = eq(_T_827, UInt<2>(0h3)) node _T_829 = leq(UInt<1>(0h0), uncommonBits_23) node _T_830 = and(_T_828, _T_829) node _T_831 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_832 = and(_T_830, _T_831) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_850 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_854 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_855 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_857 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_858 = or(_T_808, _T_814) node _T_859 = or(_T_858, _T_820) node _T_860 = or(_T_859, _T_826) node _T_861 = or(_T_860, _T_832) node _T_862 = or(_T_861, _T_833) node _T_863 = or(_T_862, _T_834) node _T_864 = or(_T_863, _T_835) node _T_865 = or(_T_864, _T_836) node _T_866 = or(_T_865, _T_837) node _T_867 = or(_T_866, _T_838) node _T_868 = or(_T_867, _T_839) node _T_869 = or(_T_868, _T_840) node _T_870 = or(_T_869, _T_841) node _T_871 = or(_T_870, _T_842) node _T_872 = or(_T_871, _T_843) node _T_873 = or(_T_872, _T_844) node _T_874 = or(_T_873, _T_845) node _T_875 = or(_T_874, _T_846) node _T_876 = or(_T_875, _T_847) node _T_877 = or(_T_876, _T_848) node _T_878 = or(_T_877, _T_849) node _T_879 = or(_T_878, _T_850) node _T_880 = or(_T_879, _T_851) node _T_881 = or(_T_880, _T_852) node _T_882 = or(_T_881, _T_853) node _T_883 = or(_T_882, _T_854) node _T_884 = or(_T_883, _T_855) node _T_885 = or(_T_884, _T_856) node _T_886 = or(_T_885, _T_857) node _T_887 = and(_T_807, _T_886) node _T_888 = or(UInt<1>(0h0), _T_887) node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(_T_888, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_888, UInt<1>(0h1), "") : assert_19 node _T_892 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_893 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_894 = and(_T_892, _T_893) node _T_895 = or(UInt<1>(0h0), _T_894) node _T_896 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<17>(0h10000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = and(_T_895, _T_900) node _T_902 = or(UInt<1>(0h0), _T_901) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_902, UInt<1>(0h1), "") : assert_20 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(source_ok, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(is_aligned, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_912 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_912, UInt<1>(0h1), "") : assert_23 node _T_916 = eq(io.in.a.bits.mask, mask) node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(_T_916, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_916, UInt<1>(0h1), "") : assert_24 node _T_920 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_920, UInt<1>(0h1), "") : assert_25 node _T_924 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_924 : node _T_925 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_926 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_927 = and(_T_925, _T_926) node _T_928 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_929 = shr(io.in.a.bits.source, 2) node _T_930 = eq(_T_929, UInt<1>(0h0)) node _T_931 = leq(UInt<1>(0h0), uncommonBits_24) node _T_932 = and(_T_930, _T_931) node _T_933 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_934 = and(_T_932, _T_933) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_935 = shr(io.in.a.bits.source, 2) node _T_936 = eq(_T_935, UInt<1>(0h1)) node _T_937 = leq(UInt<1>(0h0), uncommonBits_25) node _T_938 = and(_T_936, _T_937) node _T_939 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_940 = and(_T_938, _T_939) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_941 = shr(io.in.a.bits.source, 2) node _T_942 = eq(_T_941, UInt<2>(0h2)) node _T_943 = leq(UInt<1>(0h0), uncommonBits_26) node _T_944 = and(_T_942, _T_943) node _T_945 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_946 = and(_T_944, _T_945) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_947 = shr(io.in.a.bits.source, 2) node _T_948 = eq(_T_947, UInt<2>(0h3)) node _T_949 = leq(UInt<1>(0h0), uncommonBits_27) node _T_950 = and(_T_948, _T_949) node _T_951 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_952 = and(_T_950, _T_951) node _T_953 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_954 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_955 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_956 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_957 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_960 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_961 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_962 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_963 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_964 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_965 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_966 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_969 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_974 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_977 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_978 = or(_T_928, _T_934) node _T_979 = or(_T_978, _T_940) node _T_980 = or(_T_979, _T_946) node _T_981 = or(_T_980, _T_952) node _T_982 = or(_T_981, _T_953) node _T_983 = or(_T_982, _T_954) node _T_984 = or(_T_983, _T_955) node _T_985 = or(_T_984, _T_956) node _T_986 = or(_T_985, _T_957) node _T_987 = or(_T_986, _T_958) node _T_988 = or(_T_987, _T_959) node _T_989 = or(_T_988, _T_960) node _T_990 = or(_T_989, _T_961) node _T_991 = or(_T_990, _T_962) node _T_992 = or(_T_991, _T_963) node _T_993 = or(_T_992, _T_964) node _T_994 = or(_T_993, _T_965) node _T_995 = or(_T_994, _T_966) node _T_996 = or(_T_995, _T_967) node _T_997 = or(_T_996, _T_968) node _T_998 = or(_T_997, _T_969) node _T_999 = or(_T_998, _T_970) node _T_1000 = or(_T_999, _T_971) node _T_1001 = or(_T_1000, _T_972) node _T_1002 = or(_T_1001, _T_973) node _T_1003 = or(_T_1002, _T_974) node _T_1004 = or(_T_1003, _T_975) node _T_1005 = or(_T_1004, _T_976) node _T_1006 = or(_T_1005, _T_977) node _T_1007 = and(_T_927, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1010 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1011 = cvt(_T_1010) node _T_1012 = and(_T_1011, asSInt(UInt<17>(0h10000))) node _T_1013 = asSInt(_T_1012) node _T_1014 = eq(_T_1013, asSInt(UInt<1>(0h0))) node _T_1015 = and(_T_1009, _T_1014) node _T_1016 = or(UInt<1>(0h0), _T_1015) node _T_1017 = and(_T_1008, _T_1016) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_26 node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(source_ok, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(is_aligned, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1027 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_29 node _T_1031 = eq(io.in.a.bits.mask, mask) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_30 node _T_1035 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1037 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1038 = and(_T_1036, _T_1037) node _T_1039 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1040 = shr(io.in.a.bits.source, 2) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) node _T_1042 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1045 = and(_T_1043, _T_1044) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1046 = shr(io.in.a.bits.source, 2) node _T_1047 = eq(_T_1046, UInt<1>(0h1)) node _T_1048 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1051 = and(_T_1049, _T_1050) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1052 = shr(io.in.a.bits.source, 2) node _T_1053 = eq(_T_1052, UInt<2>(0h2)) node _T_1054 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1055 = and(_T_1053, _T_1054) node _T_1056 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1057 = and(_T_1055, _T_1056) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1058 = shr(io.in.a.bits.source, 2) node _T_1059 = eq(_T_1058, UInt<2>(0h3)) node _T_1060 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1061 = and(_T_1059, _T_1060) node _T_1062 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1065 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1066 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1067 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1068 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1069 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1070 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1071 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1074 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1075 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1076 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1077 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1078 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1079 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1080 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1088 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1089 = or(_T_1039, _T_1045) node _T_1090 = or(_T_1089, _T_1051) node _T_1091 = or(_T_1090, _T_1057) node _T_1092 = or(_T_1091, _T_1063) node _T_1093 = or(_T_1092, _T_1064) node _T_1094 = or(_T_1093, _T_1065) node _T_1095 = or(_T_1094, _T_1066) node _T_1096 = or(_T_1095, _T_1067) node _T_1097 = or(_T_1096, _T_1068) node _T_1098 = or(_T_1097, _T_1069) node _T_1099 = or(_T_1098, _T_1070) node _T_1100 = or(_T_1099, _T_1071) node _T_1101 = or(_T_1100, _T_1072) node _T_1102 = or(_T_1101, _T_1073) node _T_1103 = or(_T_1102, _T_1074) node _T_1104 = or(_T_1103, _T_1075) node _T_1105 = or(_T_1104, _T_1076) node _T_1106 = or(_T_1105, _T_1077) node _T_1107 = or(_T_1106, _T_1078) node _T_1108 = or(_T_1107, _T_1079) node _T_1109 = or(_T_1108, _T_1080) node _T_1110 = or(_T_1109, _T_1081) node _T_1111 = or(_T_1110, _T_1082) node _T_1112 = or(_T_1111, _T_1083) node _T_1113 = or(_T_1112, _T_1084) node _T_1114 = or(_T_1113, _T_1085) node _T_1115 = or(_T_1114, _T_1086) node _T_1116 = or(_T_1115, _T_1087) node _T_1117 = or(_T_1116, _T_1088) node _T_1118 = and(_T_1038, _T_1117) node _T_1119 = or(UInt<1>(0h0), _T_1118) node _T_1120 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1121 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1122 = cvt(_T_1121) node _T_1123 = and(_T_1122, asSInt(UInt<17>(0h10000))) node _T_1124 = asSInt(_T_1123) node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0))) node _T_1126 = and(_T_1120, _T_1125) node _T_1127 = or(UInt<1>(0h0), _T_1126) node _T_1128 = and(_T_1119, _T_1127) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_31 node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(source_ok, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(is_aligned, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1138 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_34 node _T_1142 = not(mask) node _T_1143 = and(io.in.a.bits.mask, _T_1142) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_35 node _T_1148 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1148 : node _T_1149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1151 = and(_T_1149, _T_1150) node _T_1152 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1153 = shr(io.in.a.bits.source, 2) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) node _T_1155 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1156 = and(_T_1154, _T_1155) node _T_1157 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1158 = and(_T_1156, _T_1157) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1159 = shr(io.in.a.bits.source, 2) node _T_1160 = eq(_T_1159, UInt<1>(0h1)) node _T_1161 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1164 = and(_T_1162, _T_1163) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1165 = shr(io.in.a.bits.source, 2) node _T_1166 = eq(_T_1165, UInt<2>(0h2)) node _T_1167 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1170 = and(_T_1168, _T_1169) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1171 = shr(io.in.a.bits.source, 2) node _T_1172 = eq(_T_1171, UInt<2>(0h3)) node _T_1173 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1176 = and(_T_1174, _T_1175) node _T_1177 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1178 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1179 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1180 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1181 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1182 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1183 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1184 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1185 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1186 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1187 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1188 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1192 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1193 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1194 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1195 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1196 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1197 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1198 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1199 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1200 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1201 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1202 = or(_T_1152, _T_1158) node _T_1203 = or(_T_1202, _T_1164) node _T_1204 = or(_T_1203, _T_1170) node _T_1205 = or(_T_1204, _T_1176) node _T_1206 = or(_T_1205, _T_1177) node _T_1207 = or(_T_1206, _T_1178) node _T_1208 = or(_T_1207, _T_1179) node _T_1209 = or(_T_1208, _T_1180) node _T_1210 = or(_T_1209, _T_1181) node _T_1211 = or(_T_1210, _T_1182) node _T_1212 = or(_T_1211, _T_1183) node _T_1213 = or(_T_1212, _T_1184) node _T_1214 = or(_T_1213, _T_1185) node _T_1215 = or(_T_1214, _T_1186) node _T_1216 = or(_T_1215, _T_1187) node _T_1217 = or(_T_1216, _T_1188) node _T_1218 = or(_T_1217, _T_1189) node _T_1219 = or(_T_1218, _T_1190) node _T_1220 = or(_T_1219, _T_1191) node _T_1221 = or(_T_1220, _T_1192) node _T_1222 = or(_T_1221, _T_1193) node _T_1223 = or(_T_1222, _T_1194) node _T_1224 = or(_T_1223, _T_1195) node _T_1225 = or(_T_1224, _T_1196) node _T_1226 = or(_T_1225, _T_1197) node _T_1227 = or(_T_1226, _T_1198) node _T_1228 = or(_T_1227, _T_1199) node _T_1229 = or(_T_1228, _T_1200) node _T_1230 = or(_T_1229, _T_1201) node _T_1231 = and(_T_1151, _T_1230) node _T_1232 = or(UInt<1>(0h0), _T_1231) node _T_1233 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1234 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1235 = cvt(_T_1234) node _T_1236 = and(_T_1235, asSInt(UInt<17>(0h10000))) node _T_1237 = asSInt(_T_1236) node _T_1238 = eq(_T_1237, asSInt(UInt<1>(0h0))) node _T_1239 = and(_T_1233, _T_1238) node _T_1240 = or(UInt<1>(0h0), _T_1239) node _T_1241 = and(_T_1232, _T_1240) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_36 node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(source_ok, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(is_aligned, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1251 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_39 node _T_1255 = eq(io.in.a.bits.mask, mask) node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(_T_1255, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1255, UInt<1>(0h1), "") : assert_40 node _T_1259 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1259 : node _T_1260 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1261 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1262 = and(_T_1260, _T_1261) node _T_1263 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1264 = shr(io.in.a.bits.source, 2) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) node _T_1266 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1267 = and(_T_1265, _T_1266) node _T_1268 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1269 = and(_T_1267, _T_1268) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1270 = shr(io.in.a.bits.source, 2) node _T_1271 = eq(_T_1270, UInt<1>(0h1)) node _T_1272 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1273 = and(_T_1271, _T_1272) node _T_1274 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1275 = and(_T_1273, _T_1274) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1276 = shr(io.in.a.bits.source, 2) node _T_1277 = eq(_T_1276, UInt<2>(0h2)) node _T_1278 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1279 = and(_T_1277, _T_1278) node _T_1280 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1281 = and(_T_1279, _T_1280) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1282 = shr(io.in.a.bits.source, 2) node _T_1283 = eq(_T_1282, UInt<2>(0h3)) node _T_1284 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1285 = and(_T_1283, _T_1284) node _T_1286 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1287 = and(_T_1285, _T_1286) node _T_1288 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1289 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1290 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1291 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1292 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1293 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1294 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1295 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1296 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1297 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1298 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1299 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1300 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1301 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1302 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1303 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1304 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1305 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1306 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1307 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1308 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1309 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1310 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1311 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1312 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1313 = or(_T_1263, _T_1269) node _T_1314 = or(_T_1313, _T_1275) node _T_1315 = or(_T_1314, _T_1281) node _T_1316 = or(_T_1315, _T_1287) node _T_1317 = or(_T_1316, _T_1288) node _T_1318 = or(_T_1317, _T_1289) node _T_1319 = or(_T_1318, _T_1290) node _T_1320 = or(_T_1319, _T_1291) node _T_1321 = or(_T_1320, _T_1292) node _T_1322 = or(_T_1321, _T_1293) node _T_1323 = or(_T_1322, _T_1294) node _T_1324 = or(_T_1323, _T_1295) node _T_1325 = or(_T_1324, _T_1296) node _T_1326 = or(_T_1325, _T_1297) node _T_1327 = or(_T_1326, _T_1298) node _T_1328 = or(_T_1327, _T_1299) node _T_1329 = or(_T_1328, _T_1300) node _T_1330 = or(_T_1329, _T_1301) node _T_1331 = or(_T_1330, _T_1302) node _T_1332 = or(_T_1331, _T_1303) node _T_1333 = or(_T_1332, _T_1304) node _T_1334 = or(_T_1333, _T_1305) node _T_1335 = or(_T_1334, _T_1306) node _T_1336 = or(_T_1335, _T_1307) node _T_1337 = or(_T_1336, _T_1308) node _T_1338 = or(_T_1337, _T_1309) node _T_1339 = or(_T_1338, _T_1310) node _T_1340 = or(_T_1339, _T_1311) node _T_1341 = or(_T_1340, _T_1312) node _T_1342 = and(_T_1262, _T_1341) node _T_1343 = or(UInt<1>(0h0), _T_1342) node _T_1344 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1345 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1346 = cvt(_T_1345) node _T_1347 = and(_T_1346, asSInt(UInt<17>(0h10000))) node _T_1348 = asSInt(_T_1347) node _T_1349 = eq(_T_1348, asSInt(UInt<1>(0h0))) node _T_1350 = and(_T_1344, _T_1349) node _T_1351 = or(UInt<1>(0h0), _T_1350) node _T_1352 = and(_T_1343, _T_1351) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_41 node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(source_ok, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(is_aligned, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1362 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(_T_1362, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1362, UInt<1>(0h1), "") : assert_44 node _T_1366 = eq(io.in.a.bits.mask, mask) node _T_1367 = asUInt(reset) node _T_1368 = eq(_T_1367, UInt<1>(0h0)) when _T_1368 : node _T_1369 = eq(_T_1366, UInt<1>(0h0)) when _T_1369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1366, UInt<1>(0h1), "") : assert_45 node _T_1370 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1370 : node _T_1371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1373 = and(_T_1371, _T_1372) node _T_1374 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1375 = shr(io.in.a.bits.source, 2) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) node _T_1377 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1378 = and(_T_1376, _T_1377) node _T_1379 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1380 = and(_T_1378, _T_1379) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1381 = shr(io.in.a.bits.source, 2) node _T_1382 = eq(_T_1381, UInt<1>(0h1)) node _T_1383 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1386 = and(_T_1384, _T_1385) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1387 = shr(io.in.a.bits.source, 2) node _T_1388 = eq(_T_1387, UInt<2>(0h2)) node _T_1389 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1390 = and(_T_1388, _T_1389) node _T_1391 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1392 = and(_T_1390, _T_1391) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1393 = shr(io.in.a.bits.source, 2) node _T_1394 = eq(_T_1393, UInt<2>(0h3)) node _T_1395 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1396 = and(_T_1394, _T_1395) node _T_1397 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1398 = and(_T_1396, _T_1397) node _T_1399 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1400 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1401 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1402 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1403 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1404 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1405 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1406 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1407 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1408 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1409 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1410 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1411 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1412 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1413 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1414 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1415 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1416 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1417 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1418 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1419 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1424 = or(_T_1374, _T_1380) node _T_1425 = or(_T_1424, _T_1386) node _T_1426 = or(_T_1425, _T_1392) node _T_1427 = or(_T_1426, _T_1398) node _T_1428 = or(_T_1427, _T_1399) node _T_1429 = or(_T_1428, _T_1400) node _T_1430 = or(_T_1429, _T_1401) node _T_1431 = or(_T_1430, _T_1402) node _T_1432 = or(_T_1431, _T_1403) node _T_1433 = or(_T_1432, _T_1404) node _T_1434 = or(_T_1433, _T_1405) node _T_1435 = or(_T_1434, _T_1406) node _T_1436 = or(_T_1435, _T_1407) node _T_1437 = or(_T_1436, _T_1408) node _T_1438 = or(_T_1437, _T_1409) node _T_1439 = or(_T_1438, _T_1410) node _T_1440 = or(_T_1439, _T_1411) node _T_1441 = or(_T_1440, _T_1412) node _T_1442 = or(_T_1441, _T_1413) node _T_1443 = or(_T_1442, _T_1414) node _T_1444 = or(_T_1443, _T_1415) node _T_1445 = or(_T_1444, _T_1416) node _T_1446 = or(_T_1445, _T_1417) node _T_1447 = or(_T_1446, _T_1418) node _T_1448 = or(_T_1447, _T_1419) node _T_1449 = or(_T_1448, _T_1420) node _T_1450 = or(_T_1449, _T_1421) node _T_1451 = or(_T_1450, _T_1422) node _T_1452 = or(_T_1451, _T_1423) node _T_1453 = and(_T_1373, _T_1452) node _T_1454 = or(UInt<1>(0h0), _T_1453) node _T_1455 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1456 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1457 = cvt(_T_1456) node _T_1458 = and(_T_1457, asSInt(UInt<17>(0h10000))) node _T_1459 = asSInt(_T_1458) node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0))) node _T_1461 = and(_T_1455, _T_1460) node _T_1462 = or(UInt<1>(0h0), _T_1461) node _T_1463 = and(_T_1454, _T_1462) node _T_1464 = asUInt(reset) node _T_1465 = eq(_T_1464, UInt<1>(0h0)) when _T_1465 : node _T_1466 = eq(_T_1463, UInt<1>(0h0)) when _T_1466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1463, UInt<1>(0h1), "") : assert_46 node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(source_ok, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(is_aligned, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1473 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(_T_1473, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1473, UInt<1>(0h1), "") : assert_49 node _T_1477 = eq(io.in.a.bits.mask, mask) node _T_1478 = asUInt(reset) node _T_1479 = eq(_T_1478, UInt<1>(0h0)) when _T_1479 : node _T_1480 = eq(_T_1477, UInt<1>(0h0)) when _T_1480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1477, UInt<1>(0h1), "") : assert_50 node _T_1481 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(_T_1481, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1481, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1485 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_52 node _source_ok_T_78 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_85 = shr(io.in.d.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_91 = shr(io.in.d.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_97 = shr(io.in.d.bits.source, 2) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[30] connect _source_ok_WIRE_1[0], _source_ok_T_78 connect _source_ok_WIRE_1[1], _source_ok_T_84 connect _source_ok_WIRE_1[2], _source_ok_T_90 connect _source_ok_WIRE_1[3], _source_ok_T_96 connect _source_ok_WIRE_1[4], _source_ok_T_102 connect _source_ok_WIRE_1[5], _source_ok_T_103 connect _source_ok_WIRE_1[6], _source_ok_T_104 connect _source_ok_WIRE_1[7], _source_ok_T_105 connect _source_ok_WIRE_1[8], _source_ok_T_106 connect _source_ok_WIRE_1[9], _source_ok_T_107 connect _source_ok_WIRE_1[10], _source_ok_T_108 connect _source_ok_WIRE_1[11], _source_ok_T_109 connect _source_ok_WIRE_1[12], _source_ok_T_110 connect _source_ok_WIRE_1[13], _source_ok_T_111 connect _source_ok_WIRE_1[14], _source_ok_T_112 connect _source_ok_WIRE_1[15], _source_ok_T_113 connect _source_ok_WIRE_1[16], _source_ok_T_114 connect _source_ok_WIRE_1[17], _source_ok_T_115 connect _source_ok_WIRE_1[18], _source_ok_T_116 connect _source_ok_WIRE_1[19], _source_ok_T_117 connect _source_ok_WIRE_1[20], _source_ok_T_118 connect _source_ok_WIRE_1[21], _source_ok_T_119 connect _source_ok_WIRE_1[22], _source_ok_T_120 connect _source_ok_WIRE_1[23], _source_ok_T_121 connect _source_ok_WIRE_1[24], _source_ok_T_122 connect _source_ok_WIRE_1[25], _source_ok_T_123 connect _source_ok_WIRE_1[26], _source_ok_T_124 connect _source_ok_WIRE_1[27], _source_ok_T_125 connect _source_ok_WIRE_1[28], _source_ok_T_126 connect _source_ok_WIRE_1[29], _source_ok_T_127 node _source_ok_T_128 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[2]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[3]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[4]) node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[5]) node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[6]) node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[7]) node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[8]) node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[9]) node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[10]) node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[11]) node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[12]) node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[13]) node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[14]) node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[15]) node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[16]) node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[17]) node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[18]) node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[19]) node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[20]) node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[21]) node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[22]) node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[23]) node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[24]) node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE_1[25]) node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE_1[26]) node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE_1[27]) node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE_1[28]) node source_ok_1 = or(_source_ok_T_155, _source_ok_WIRE_1[29]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1489 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1489 : node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(source_ok_1, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1493 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1494 = asUInt(reset) node _T_1495 = eq(_T_1494, UInt<1>(0h0)) when _T_1495 : node _T_1496 = eq(_T_1493, UInt<1>(0h0)) when _T_1496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1493, UInt<1>(0h1), "") : assert_54 node _T_1497 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1498 = asUInt(reset) node _T_1499 = eq(_T_1498, UInt<1>(0h0)) when _T_1499 : node _T_1500 = eq(_T_1497, UInt<1>(0h0)) when _T_1500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1497, UInt<1>(0h1), "") : assert_55 node _T_1501 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1502 = asUInt(reset) node _T_1503 = eq(_T_1502, UInt<1>(0h0)) when _T_1503 : node _T_1504 = eq(_T_1501, UInt<1>(0h0)) when _T_1504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1501, UInt<1>(0h1), "") : assert_56 node _T_1505 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1506 = asUInt(reset) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) when _T_1507 : node _T_1508 = eq(_T_1505, UInt<1>(0h0)) when _T_1508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1505, UInt<1>(0h1), "") : assert_57 node _T_1509 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1509 : node _T_1510 = asUInt(reset) node _T_1511 = eq(_T_1510, UInt<1>(0h0)) when _T_1511 : node _T_1512 = eq(source_ok_1, UInt<1>(0h0)) when _T_1512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(sink_ok, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1516 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_60 node _T_1520 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_61 node _T_1524 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(_T_1524, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1524, UInt<1>(0h1), "") : assert_62 node _T_1528 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_63 node _T_1532 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1533 = or(UInt<1>(0h0), _T_1532) node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(_T_1533, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1533, UInt<1>(0h1), "") : assert_64 node _T_1537 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1537 : node _T_1538 = asUInt(reset) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) when _T_1539 : node _T_1540 = eq(source_ok_1, UInt<1>(0h0)) when _T_1540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1541 = asUInt(reset) node _T_1542 = eq(_T_1541, UInt<1>(0h0)) when _T_1542 : node _T_1543 = eq(sink_ok, UInt<1>(0h0)) when _T_1543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1544 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1545 = asUInt(reset) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) when _T_1546 : node _T_1547 = eq(_T_1544, UInt<1>(0h0)) when _T_1547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1544, UInt<1>(0h1), "") : assert_67 node _T_1548 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(_T_1548, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1548, UInt<1>(0h1), "") : assert_68 node _T_1552 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(_T_1552, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1552, UInt<1>(0h1), "") : assert_69 node _T_1556 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1557 = or(_T_1556, io.in.d.bits.corrupt) node _T_1558 = asUInt(reset) node _T_1559 = eq(_T_1558, UInt<1>(0h0)) when _T_1559 : node _T_1560 = eq(_T_1557, UInt<1>(0h0)) when _T_1560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1557, UInt<1>(0h1), "") : assert_70 node _T_1561 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1562 = or(UInt<1>(0h0), _T_1561) node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(_T_1562, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1562, UInt<1>(0h1), "") : assert_71 node _T_1566 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1566 : node _T_1567 = asUInt(reset) node _T_1568 = eq(_T_1567, UInt<1>(0h0)) when _T_1568 : node _T_1569 = eq(source_ok_1, UInt<1>(0h0)) when _T_1569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1570 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1571 = asUInt(reset) node _T_1572 = eq(_T_1571, UInt<1>(0h0)) when _T_1572 : node _T_1573 = eq(_T_1570, UInt<1>(0h0)) when _T_1573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1570, UInt<1>(0h1), "") : assert_73 node _T_1574 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1575 = asUInt(reset) node _T_1576 = eq(_T_1575, UInt<1>(0h0)) when _T_1576 : node _T_1577 = eq(_T_1574, UInt<1>(0h0)) when _T_1577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1574, UInt<1>(0h1), "") : assert_74 node _T_1578 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1579 = or(UInt<1>(0h0), _T_1578) node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(_T_1579, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1579, UInt<1>(0h1), "") : assert_75 node _T_1583 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1583 : node _T_1584 = asUInt(reset) node _T_1585 = eq(_T_1584, UInt<1>(0h0)) when _T_1585 : node _T_1586 = eq(source_ok_1, UInt<1>(0h0)) when _T_1586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1587 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(_T_1587, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1587, UInt<1>(0h1), "") : assert_77 node _T_1591 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1592 = or(_T_1591, io.in.d.bits.corrupt) node _T_1593 = asUInt(reset) node _T_1594 = eq(_T_1593, UInt<1>(0h0)) when _T_1594 : node _T_1595 = eq(_T_1592, UInt<1>(0h0)) when _T_1595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1592, UInt<1>(0h1), "") : assert_78 node _T_1596 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1597 = or(UInt<1>(0h0), _T_1596) node _T_1598 = asUInt(reset) node _T_1599 = eq(_T_1598, UInt<1>(0h0)) when _T_1599 : node _T_1600 = eq(_T_1597, UInt<1>(0h0)) when _T_1600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1597, UInt<1>(0h1), "") : assert_79 node _T_1601 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1601 : node _T_1602 = asUInt(reset) node _T_1603 = eq(_T_1602, UInt<1>(0h0)) when _T_1603 : node _T_1604 = eq(source_ok_1, UInt<1>(0h0)) when _T_1604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1605 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1606 = asUInt(reset) node _T_1607 = eq(_T_1606, UInt<1>(0h0)) when _T_1607 : node _T_1608 = eq(_T_1605, UInt<1>(0h0)) when _T_1608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1605, UInt<1>(0h1), "") : assert_81 node _T_1609 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1610 = asUInt(reset) node _T_1611 = eq(_T_1610, UInt<1>(0h0)) when _T_1611 : node _T_1612 = eq(_T_1609, UInt<1>(0h0)) when _T_1612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1609, UInt<1>(0h1), "") : assert_82 node _T_1613 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1614 = or(UInt<1>(0h0), _T_1613) node _T_1615 = asUInt(reset) node _T_1616 = eq(_T_1615, UInt<1>(0h0)) when _T_1616 : node _T_1617 = eq(_T_1614, UInt<1>(0h0)) when _T_1617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1614, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<17>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1618 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1619 = asUInt(reset) node _T_1620 = eq(_T_1619, UInt<1>(0h0)) when _T_1620 : node _T_1621 = eq(_T_1618, UInt<1>(0h0)) when _T_1621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1618, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1622 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1623 = asUInt(reset) node _T_1624 = eq(_T_1623, UInt<1>(0h0)) when _T_1624 : node _T_1625 = eq(_T_1622, UInt<1>(0h0)) when _T_1625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1622, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1626 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1627 = asUInt(reset) node _T_1628 = eq(_T_1627, UInt<1>(0h0)) when _T_1628 : node _T_1629 = eq(_T_1626, UInt<1>(0h0)) when _T_1629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1626, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1630 = eq(a_first, UInt<1>(0h0)) node _T_1631 = and(io.in.a.valid, _T_1630) when _T_1631 : node _T_1632 = eq(io.in.a.bits.opcode, opcode) node _T_1633 = asUInt(reset) node _T_1634 = eq(_T_1633, UInt<1>(0h0)) when _T_1634 : node _T_1635 = eq(_T_1632, UInt<1>(0h0)) when _T_1635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1632, UInt<1>(0h1), "") : assert_87 node _T_1636 = eq(io.in.a.bits.param, param) node _T_1637 = asUInt(reset) node _T_1638 = eq(_T_1637, UInt<1>(0h0)) when _T_1638 : node _T_1639 = eq(_T_1636, UInt<1>(0h0)) when _T_1639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1636, UInt<1>(0h1), "") : assert_88 node _T_1640 = eq(io.in.a.bits.size, size) node _T_1641 = asUInt(reset) node _T_1642 = eq(_T_1641, UInt<1>(0h0)) when _T_1642 : node _T_1643 = eq(_T_1640, UInt<1>(0h0)) when _T_1643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1640, UInt<1>(0h1), "") : assert_89 node _T_1644 = eq(io.in.a.bits.source, source) node _T_1645 = asUInt(reset) node _T_1646 = eq(_T_1645, UInt<1>(0h0)) when _T_1646 : node _T_1647 = eq(_T_1644, UInt<1>(0h0)) when _T_1647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1644, UInt<1>(0h1), "") : assert_90 node _T_1648 = eq(io.in.a.bits.address, address) node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(_T_1648, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1648, UInt<1>(0h1), "") : assert_91 node _T_1652 = and(io.in.a.ready, io.in.a.valid) node _T_1653 = and(_T_1652, a_first) when _T_1653 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1654 = eq(d_first, UInt<1>(0h0)) node _T_1655 = and(io.in.d.valid, _T_1654) when _T_1655 : node _T_1656 = eq(io.in.d.bits.opcode, opcode_1) node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(_T_1656, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1656, UInt<1>(0h1), "") : assert_92 node _T_1660 = eq(io.in.d.bits.param, param_1) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_93 node _T_1664 = eq(io.in.d.bits.size, size_1) node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(_T_1664, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1664, UInt<1>(0h1), "") : assert_94 node _T_1668 = eq(io.in.d.bits.source, source_1) node _T_1669 = asUInt(reset) node _T_1670 = eq(_T_1669, UInt<1>(0h0)) when _T_1670 : node _T_1671 = eq(_T_1668, UInt<1>(0h0)) when _T_1671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1668, UInt<1>(0h1), "") : assert_95 node _T_1672 = eq(io.in.d.bits.sink, sink) node _T_1673 = asUInt(reset) node _T_1674 = eq(_T_1673, UInt<1>(0h0)) when _T_1674 : node _T_1675 = eq(_T_1672, UInt<1>(0h0)) when _T_1675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1672, UInt<1>(0h1), "") : assert_96 node _T_1676 = eq(io.in.d.bits.denied, denied) node _T_1677 = asUInt(reset) node _T_1678 = eq(_T_1677, UInt<1>(0h0)) when _T_1678 : node _T_1679 = eq(_T_1676, UInt<1>(0h0)) when _T_1679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1676, UInt<1>(0h1), "") : assert_97 node _T_1680 = and(io.in.d.ready, io.in.d.valid) node _T_1681 = and(_T_1680, d_first) when _T_1681 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1682 = and(io.in.a.valid, a_first_1) node _T_1683 = and(_T_1682, UInt<1>(0h1)) when _T_1683 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1684 = and(io.in.a.ready, io.in.a.valid) node _T_1685 = and(_T_1684, a_first_1) node _T_1686 = and(_T_1685, UInt<1>(0h1)) when _T_1686 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1687 = dshr(inflight, io.in.a.bits.source) node _T_1688 = bits(_T_1687, 0, 0) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) node _T_1690 = asUInt(reset) node _T_1691 = eq(_T_1690, UInt<1>(0h0)) when _T_1691 : node _T_1692 = eq(_T_1689, UInt<1>(0h0)) when _T_1692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1689, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1693 = and(io.in.d.valid, d_first_1) node _T_1694 = and(_T_1693, UInt<1>(0h1)) node _T_1695 = eq(d_release_ack, UInt<1>(0h0)) node _T_1696 = and(_T_1694, _T_1695) when _T_1696 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1697 = and(io.in.d.ready, io.in.d.valid) node _T_1698 = and(_T_1697, d_first_1) node _T_1699 = and(_T_1698, UInt<1>(0h1)) node _T_1700 = eq(d_release_ack, UInt<1>(0h0)) node _T_1701 = and(_T_1699, _T_1700) when _T_1701 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1702 = and(io.in.d.valid, d_first_1) node _T_1703 = and(_T_1702, UInt<1>(0h1)) node _T_1704 = eq(d_release_ack, UInt<1>(0h0)) node _T_1705 = and(_T_1703, _T_1704) when _T_1705 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1706 = dshr(inflight, io.in.d.bits.source) node _T_1707 = bits(_T_1706, 0, 0) node _T_1708 = or(_T_1707, same_cycle_resp) node _T_1709 = asUInt(reset) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) when _T_1710 : node _T_1711 = eq(_T_1708, UInt<1>(0h0)) when _T_1711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1708, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1712 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1713 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1714 = or(_T_1712, _T_1713) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_100 node _T_1718 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1719 = asUInt(reset) node _T_1720 = eq(_T_1719, UInt<1>(0h0)) when _T_1720 : node _T_1721 = eq(_T_1718, UInt<1>(0h0)) when _T_1721 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1718, UInt<1>(0h1), "") : assert_101 else : node _T_1722 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1723 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1724 = or(_T_1722, _T_1723) node _T_1725 = asUInt(reset) node _T_1726 = eq(_T_1725, UInt<1>(0h0)) when _T_1726 : node _T_1727 = eq(_T_1724, UInt<1>(0h0)) when _T_1727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1724, UInt<1>(0h1), "") : assert_102 node _T_1728 = eq(io.in.d.bits.size, a_size_lookup) node _T_1729 = asUInt(reset) node _T_1730 = eq(_T_1729, UInt<1>(0h0)) when _T_1730 : node _T_1731 = eq(_T_1728, UInt<1>(0h0)) when _T_1731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1728, UInt<1>(0h1), "") : assert_103 node _T_1732 = and(io.in.d.valid, d_first_1) node _T_1733 = and(_T_1732, a_first_1) node _T_1734 = and(_T_1733, io.in.a.valid) node _T_1735 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1736 = and(_T_1734, _T_1735) node _T_1737 = eq(d_release_ack, UInt<1>(0h0)) node _T_1738 = and(_T_1736, _T_1737) when _T_1738 : node _T_1739 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1740 = or(_T_1739, io.in.a.ready) node _T_1741 = asUInt(reset) node _T_1742 = eq(_T_1741, UInt<1>(0h0)) when _T_1742 : node _T_1743 = eq(_T_1740, UInt<1>(0h0)) when _T_1743 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1740, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_92 node _T_1744 = orr(inflight) node _T_1745 = eq(_T_1744, UInt<1>(0h0)) node _T_1746 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1747 = or(_T_1745, _T_1746) node _T_1748 = lt(watchdog, plusarg_reader.out) node _T_1749 = or(_T_1747, _T_1748) node _T_1750 = asUInt(reset) node _T_1751 = eq(_T_1750, UInt<1>(0h0)) when _T_1751 : node _T_1752 = eq(_T_1749, UInt<1>(0h0)) when _T_1752 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1749, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1753 = and(io.in.a.ready, io.in.a.valid) node _T_1754 = and(io.in.d.ready, io.in.d.valid) node _T_1755 = or(_T_1753, _T_1754) when _T_1755 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1756 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1757 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1758 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1759 = and(_T_1757, _T_1758) node _T_1760 = and(_T_1756, _T_1759) when _T_1760 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1761 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1762 = and(_T_1761, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1763 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1764 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1765 = and(_T_1763, _T_1764) node _T_1766 = and(_T_1762, _T_1765) when _T_1766 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1767 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1768 = bits(_T_1767, 0, 0) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1773 = and(io.in.d.valid, d_first_2) node _T_1774 = and(_T_1773, UInt<1>(0h1)) node _T_1775 = and(_T_1774, d_release_ack_1) when _T_1775 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1776 = and(io.in.d.ready, io.in.d.valid) node _T_1777 = and(_T_1776, d_first_2) node _T_1778 = and(_T_1777, UInt<1>(0h1)) node _T_1779 = and(_T_1778, d_release_ack_1) when _T_1779 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1780 = and(io.in.d.valid, d_first_2) node _T_1781 = and(_T_1780, UInt<1>(0h1)) node _T_1782 = and(_T_1781, d_release_ack_1) when _T_1782 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1783 = dshr(inflight_1, io.in.d.bits.source) node _T_1784 = bits(_T_1783, 0, 0) node _T_1785 = or(_T_1784, same_cycle_resp_1) node _T_1786 = asUInt(reset) node _T_1787 = eq(_T_1786, UInt<1>(0h0)) when _T_1787 : node _T_1788 = eq(_T_1785, UInt<1>(0h0)) when _T_1788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1785, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1789 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1790 = asUInt(reset) node _T_1791 = eq(_T_1790, UInt<1>(0h0)) when _T_1791 : node _T_1792 = eq(_T_1789, UInt<1>(0h0)) when _T_1792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1789, UInt<1>(0h1), "") : assert_108 else : node _T_1793 = eq(io.in.d.bits.size, c_size_lookup) node _T_1794 = asUInt(reset) node _T_1795 = eq(_T_1794, UInt<1>(0h0)) when _T_1795 : node _T_1796 = eq(_T_1793, UInt<1>(0h0)) when _T_1796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1793, UInt<1>(0h1), "") : assert_109 node _T_1797 = and(io.in.d.valid, d_first_2) node _T_1798 = and(_T_1797, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1799 = and(_T_1798, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1800 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1801 = and(_T_1799, _T_1800) node _T_1802 = and(_T_1801, d_release_ack_1) node _T_1803 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1804 = and(_T_1802, _T_1803) when _T_1804 : node _T_1805 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<17>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1806 = or(_T_1805, _WIRE_27.ready) node _T_1807 = asUInt(reset) node _T_1808 = eq(_T_1807, UInt<1>(0h0)) when _T_1808 : node _T_1809 = eq(_T_1806, UInt<1>(0h0)) when _T_1809 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1806, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_93 node _T_1810 = orr(inflight_1) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) node _T_1812 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1813 = or(_T_1811, _T_1812) node _T_1814 = lt(watchdog_1, plusarg_reader_1.out) node _T_1815 = or(_T_1813, _T_1814) node _T_1816 = asUInt(reset) node _T_1817 = eq(_T_1816, UInt<1>(0h0)) when _T_1817 : node _T_1818 = eq(_T_1815, UInt<1>(0h0)) when _T_1818 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1815, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<17>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1819 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1820 = and(io.in.d.ready, io.in.d.valid) node _T_1821 = or(_T_1819, _T_1820) when _T_1821 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_33( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN = a_first_done & a_first_1; // @[Decoupled.scala:51:35] reg [31:0] watchdog; // @[Monitor.scala:709:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_16 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_129 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<14>(0h2000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<13>(0h1000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_156 = cvt(_T_155) node _T_157 = and(_T_156, asSInt(UInt<17>(0h10000))) node _T_158 = asSInt(_T_157) node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0))) node _T_160 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<18>(0h2f000))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_166 = cvt(_T_165) node _T_167 = and(_T_166, asSInt(UInt<17>(0h10000))) node _T_168 = asSInt(_T_167) node _T_169 = eq(_T_168, asSInt(UInt<1>(0h0))) node _T_170 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<13>(0h1000))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<27>(0h4000000))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_181 = cvt(_T_180) node _T_182 = and(_T_181, asSInt(UInt<13>(0h1000))) node _T_183 = asSInt(_T_182) node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0))) node _T_185 = or(_T_144, _T_149) node _T_186 = or(_T_185, _T_154) node _T_187 = or(_T_186, _T_159) node _T_188 = or(_T_187, _T_164) node _T_189 = or(_T_188, _T_169) node _T_190 = or(_T_189, _T_174) node _T_191 = or(_T_190, _T_179) node _T_192 = or(_T_191, _T_184) node _T_193 = and(_T_139, _T_192) node _T_194 = or(UInt<1>(0h0), _T_193) node _T_195 = and(_T_138, _T_194) node _T_196 = asUInt(reset) node _T_197 = eq(_T_196, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(_T_195, UInt<1>(0h0)) when _T_198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_195, UInt<1>(0h1), "") : assert_2 node _T_199 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_200 = shr(io.in.a.bits.source, 2) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = leq(UInt<1>(0h0), uncommonBits_8) node _T_203 = and(_T_201, _T_202) node _T_204 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_205 = and(_T_203, _T_204) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_206 = shr(io.in.a.bits.source, 2) node _T_207 = eq(_T_206, UInt<1>(0h1)) node _T_208 = leq(UInt<1>(0h0), uncommonBits_9) node _T_209 = and(_T_207, _T_208) node _T_210 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_211 = and(_T_209, _T_210) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_212 = shr(io.in.a.bits.source, 2) node _T_213 = eq(_T_212, UInt<2>(0h2)) node _T_214 = leq(UInt<1>(0h0), uncommonBits_10) node _T_215 = and(_T_213, _T_214) node _T_216 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_217 = and(_T_215, _T_216) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_218 = shr(io.in.a.bits.source, 2) node _T_219 = eq(_T_218, UInt<2>(0h3)) node _T_220 = leq(UInt<1>(0h0), uncommonBits_11) node _T_221 = and(_T_219, _T_220) node _T_222 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_223 = and(_T_221, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_225 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_226 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE : UInt<1>[8] connect _WIRE[0], _T_199 connect _WIRE[1], _T_205 connect _WIRE[2], _T_211 connect _WIRE[3], _T_217 connect _WIRE[4], _T_223 connect _WIRE[5], _T_224 connect _WIRE[6], _T_225 connect _WIRE[7], _T_226 node _T_227 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_228 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_229 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_230 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_231 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_232 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_233 = mux(_WIRE[5], _T_227, UInt<1>(0h0)) node _T_234 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_235 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_236 = or(_T_228, _T_229) node _T_237 = or(_T_236, _T_230) node _T_238 = or(_T_237, _T_231) node _T_239 = or(_T_238, _T_232) node _T_240 = or(_T_239, _T_233) node _T_241 = or(_T_240, _T_234) node _T_242 = or(_T_241, _T_235) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_242 node _T_243 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_244 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_245 = and(_T_243, _T_244) node _T_246 = or(UInt<1>(0h0), _T_245) node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_248 = cvt(_T_247) node _T_249 = and(_T_248, asSInt(UInt<14>(0h2000))) node _T_250 = asSInt(_T_249) node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0))) node _T_252 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_258 = cvt(_T_257) node _T_259 = and(_T_258, asSInt(UInt<13>(0h1000))) node _T_260 = asSInt(_T_259) node _T_261 = eq(_T_260, asSInt(UInt<1>(0h0))) node _T_262 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_263 = cvt(_T_262) node _T_264 = and(_T_263, asSInt(UInt<17>(0h10000))) node _T_265 = asSInt(_T_264) node _T_266 = eq(_T_265, asSInt(UInt<1>(0h0))) node _T_267 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_268 = cvt(_T_267) node _T_269 = and(_T_268, asSInt(UInt<18>(0h2f000))) node _T_270 = asSInt(_T_269) node _T_271 = eq(_T_270, asSInt(UInt<1>(0h0))) node _T_272 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_273 = cvt(_T_272) node _T_274 = and(_T_273, asSInt(UInt<17>(0h10000))) node _T_275 = asSInt(_T_274) node _T_276 = eq(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_278 = cvt(_T_277) node _T_279 = and(_T_278, asSInt(UInt<13>(0h1000))) node _T_280 = asSInt(_T_279) node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<27>(0h4000000))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_288 = cvt(_T_287) node _T_289 = and(_T_288, asSInt(UInt<13>(0h1000))) node _T_290 = asSInt(_T_289) node _T_291 = eq(_T_290, asSInt(UInt<1>(0h0))) node _T_292 = or(_T_251, _T_256) node _T_293 = or(_T_292, _T_261) node _T_294 = or(_T_293, _T_266) node _T_295 = or(_T_294, _T_271) node _T_296 = or(_T_295, _T_276) node _T_297 = or(_T_296, _T_281) node _T_298 = or(_T_297, _T_286) node _T_299 = or(_T_298, _T_291) node _T_300 = and(_T_246, _T_299) node _T_301 = or(UInt<1>(0h0), _T_300) node _T_302 = and(_WIRE_1, _T_301) node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_T_302, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_302, UInt<1>(0h1), "") : assert_3 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(source_ok, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_309 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_309, UInt<1>(0h1), "") : assert_5 node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(is_aligned, UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_316 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_317 = asUInt(reset) node _T_318 = eq(_T_317, UInt<1>(0h0)) when _T_318 : node _T_319 = eq(_T_316, UInt<1>(0h0)) when _T_319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_316, UInt<1>(0h1), "") : assert_7 node _T_320 = not(io.in.a.bits.mask) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = asUInt(reset) node _T_323 = eq(_T_322, UInt<1>(0h0)) when _T_323 : node _T_324 = eq(_T_321, UInt<1>(0h0)) when _T_324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_321, UInt<1>(0h1), "") : assert_8 node _T_325 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_325, UInt<1>(0h1), "") : assert_9 node _T_329 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_329 : node _T_330 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_331 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_332 = and(_T_330, _T_331) node _T_333 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_334 = shr(io.in.a.bits.source, 2) node _T_335 = eq(_T_334, UInt<1>(0h0)) node _T_336 = leq(UInt<1>(0h0), uncommonBits_12) node _T_337 = and(_T_335, _T_336) node _T_338 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_339 = and(_T_337, _T_338) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_340 = shr(io.in.a.bits.source, 2) node _T_341 = eq(_T_340, UInt<1>(0h1)) node _T_342 = leq(UInt<1>(0h0), uncommonBits_13) node _T_343 = and(_T_341, _T_342) node _T_344 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_345 = and(_T_343, _T_344) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_346 = shr(io.in.a.bits.source, 2) node _T_347 = eq(_T_346, UInt<2>(0h2)) node _T_348 = leq(UInt<1>(0h0), uncommonBits_14) node _T_349 = and(_T_347, _T_348) node _T_350 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_351 = and(_T_349, _T_350) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_352 = shr(io.in.a.bits.source, 2) node _T_353 = eq(_T_352, UInt<2>(0h3)) node _T_354 = leq(UInt<1>(0h0), uncommonBits_15) node _T_355 = and(_T_353, _T_354) node _T_356 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_357 = and(_T_355, _T_356) node _T_358 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_359 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_360 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_361 = or(_T_333, _T_339) node _T_362 = or(_T_361, _T_345) node _T_363 = or(_T_362, _T_351) node _T_364 = or(_T_363, _T_357) node _T_365 = or(_T_364, _T_358) node _T_366 = or(_T_365, _T_359) node _T_367 = or(_T_366, _T_360) node _T_368 = and(_T_332, _T_367) node _T_369 = or(UInt<1>(0h0), _T_368) node _T_370 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_371 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_372 = cvt(_T_371) node _T_373 = and(_T_372, asSInt(UInt<14>(0h2000))) node _T_374 = asSInt(_T_373) node _T_375 = eq(_T_374, asSInt(UInt<1>(0h0))) node _T_376 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_377 = cvt(_T_376) node _T_378 = and(_T_377, asSInt(UInt<13>(0h1000))) node _T_379 = asSInt(_T_378) node _T_380 = eq(_T_379, asSInt(UInt<1>(0h0))) node _T_381 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_382 = cvt(_T_381) node _T_383 = and(_T_382, asSInt(UInt<13>(0h1000))) node _T_384 = asSInt(_T_383) node _T_385 = eq(_T_384, asSInt(UInt<1>(0h0))) node _T_386 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_387 = cvt(_T_386) node _T_388 = and(_T_387, asSInt(UInt<17>(0h10000))) node _T_389 = asSInt(_T_388) node _T_390 = eq(_T_389, asSInt(UInt<1>(0h0))) node _T_391 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_392 = cvt(_T_391) node _T_393 = and(_T_392, asSInt(UInt<18>(0h2f000))) node _T_394 = asSInt(_T_393) node _T_395 = eq(_T_394, asSInt(UInt<1>(0h0))) node _T_396 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_397 = cvt(_T_396) node _T_398 = and(_T_397, asSInt(UInt<17>(0h10000))) node _T_399 = asSInt(_T_398) node _T_400 = eq(_T_399, asSInt(UInt<1>(0h0))) node _T_401 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_402 = cvt(_T_401) node _T_403 = and(_T_402, asSInt(UInt<13>(0h1000))) node _T_404 = asSInt(_T_403) node _T_405 = eq(_T_404, asSInt(UInt<1>(0h0))) node _T_406 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_407 = cvt(_T_406) node _T_408 = and(_T_407, asSInt(UInt<27>(0h4000000))) node _T_409 = asSInt(_T_408) node _T_410 = eq(_T_409, asSInt(UInt<1>(0h0))) node _T_411 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_412 = cvt(_T_411) node _T_413 = and(_T_412, asSInt(UInt<13>(0h1000))) node _T_414 = asSInt(_T_413) node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0))) node _T_416 = or(_T_375, _T_380) node _T_417 = or(_T_416, _T_385) node _T_418 = or(_T_417, _T_390) node _T_419 = or(_T_418, _T_395) node _T_420 = or(_T_419, _T_400) node _T_421 = or(_T_420, _T_405) node _T_422 = or(_T_421, _T_410) node _T_423 = or(_T_422, _T_415) node _T_424 = and(_T_370, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_369, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_426, UInt<1>(0h1), "") : assert_10 node _T_430 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_431 = shr(io.in.a.bits.source, 2) node _T_432 = eq(_T_431, UInt<1>(0h0)) node _T_433 = leq(UInt<1>(0h0), uncommonBits_16) node _T_434 = and(_T_432, _T_433) node _T_435 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_436 = and(_T_434, _T_435) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_437 = shr(io.in.a.bits.source, 2) node _T_438 = eq(_T_437, UInt<1>(0h1)) node _T_439 = leq(UInt<1>(0h0), uncommonBits_17) node _T_440 = and(_T_438, _T_439) node _T_441 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_442 = and(_T_440, _T_441) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_443 = shr(io.in.a.bits.source, 2) node _T_444 = eq(_T_443, UInt<2>(0h2)) node _T_445 = leq(UInt<1>(0h0), uncommonBits_18) node _T_446 = and(_T_444, _T_445) node _T_447 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_448 = and(_T_446, _T_447) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_449 = shr(io.in.a.bits.source, 2) node _T_450 = eq(_T_449, UInt<2>(0h3)) node _T_451 = leq(UInt<1>(0h0), uncommonBits_19) node _T_452 = and(_T_450, _T_451) node _T_453 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_454 = and(_T_452, _T_453) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE_2 : UInt<1>[8] connect _WIRE_2[0], _T_430 connect _WIRE_2[1], _T_436 connect _WIRE_2[2], _T_442 connect _WIRE_2[3], _T_448 connect _WIRE_2[4], _T_454 connect _WIRE_2[5], _T_455 connect _WIRE_2[6], _T_456 connect _WIRE_2[7], _T_457 node _T_458 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_459 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_460 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_462 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_463 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_464 = mux(_WIRE_2[5], _T_458, UInt<1>(0h0)) node _T_465 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_466 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = or(_T_459, _T_460) node _T_468 = or(_T_467, _T_461) node _T_469 = or(_T_468, _T_462) node _T_470 = or(_T_469, _T_463) node _T_471 = or(_T_470, _T_464) node _T_472 = or(_T_471, _T_465) node _T_473 = or(_T_472, _T_466) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_473 node _T_474 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_475 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_476 = and(_T_474, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_479 = cvt(_T_478) node _T_480 = and(_T_479, asSInt(UInt<14>(0h2000))) node _T_481 = asSInt(_T_480) node _T_482 = eq(_T_481, asSInt(UInt<1>(0h0))) node _T_483 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_484 = cvt(_T_483) node _T_485 = and(_T_484, asSInt(UInt<13>(0h1000))) node _T_486 = asSInt(_T_485) node _T_487 = eq(_T_486, asSInt(UInt<1>(0h0))) node _T_488 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_489 = cvt(_T_488) node _T_490 = and(_T_489, asSInt(UInt<13>(0h1000))) node _T_491 = asSInt(_T_490) node _T_492 = eq(_T_491, asSInt(UInt<1>(0h0))) node _T_493 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_494 = cvt(_T_493) node _T_495 = and(_T_494, asSInt(UInt<17>(0h10000))) node _T_496 = asSInt(_T_495) node _T_497 = eq(_T_496, asSInt(UInt<1>(0h0))) node _T_498 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_499 = cvt(_T_498) node _T_500 = and(_T_499, asSInt(UInt<18>(0h2f000))) node _T_501 = asSInt(_T_500) node _T_502 = eq(_T_501, asSInt(UInt<1>(0h0))) node _T_503 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_504 = cvt(_T_503) node _T_505 = and(_T_504, asSInt(UInt<17>(0h10000))) node _T_506 = asSInt(_T_505) node _T_507 = eq(_T_506, asSInt(UInt<1>(0h0))) node _T_508 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_509 = cvt(_T_508) node _T_510 = and(_T_509, asSInt(UInt<13>(0h1000))) node _T_511 = asSInt(_T_510) node _T_512 = eq(_T_511, asSInt(UInt<1>(0h0))) node _T_513 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_514 = cvt(_T_513) node _T_515 = and(_T_514, asSInt(UInt<27>(0h4000000))) node _T_516 = asSInt(_T_515) node _T_517 = eq(_T_516, asSInt(UInt<1>(0h0))) node _T_518 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_519 = cvt(_T_518) node _T_520 = and(_T_519, asSInt(UInt<13>(0h1000))) node _T_521 = asSInt(_T_520) node _T_522 = eq(_T_521, asSInt(UInt<1>(0h0))) node _T_523 = or(_T_482, _T_487) node _T_524 = or(_T_523, _T_492) node _T_525 = or(_T_524, _T_497) node _T_526 = or(_T_525, _T_502) node _T_527 = or(_T_526, _T_507) node _T_528 = or(_T_527, _T_512) node _T_529 = or(_T_528, _T_517) node _T_530 = or(_T_529, _T_522) node _T_531 = and(_T_477, _T_530) node _T_532 = or(UInt<1>(0h0), _T_531) node _T_533 = and(_WIRE_3, _T_532) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_533, UInt<1>(0h1), "") : assert_11 node _T_537 = asUInt(reset) node _T_538 = eq(_T_537, UInt<1>(0h0)) when _T_538 : node _T_539 = eq(source_ok, UInt<1>(0h0)) when _T_539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_540 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_540, UInt<1>(0h1), "") : assert_13 node _T_544 = asUInt(reset) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(is_aligned, UInt<1>(0h0)) when _T_546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_547 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_548 = asUInt(reset) node _T_549 = eq(_T_548, UInt<1>(0h0)) when _T_549 : node _T_550 = eq(_T_547, UInt<1>(0h0)) when _T_550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_547, UInt<1>(0h1), "") : assert_15 node _T_551 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_551, UInt<1>(0h1), "") : assert_16 node _T_555 = not(io.in.a.bits.mask) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_556, UInt<1>(0h1), "") : assert_17 node _T_560 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_560, UInt<1>(0h1), "") : assert_18 node _T_564 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_564 : node _T_565 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_566 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_567 = and(_T_565, _T_566) node _T_568 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_569 = shr(io.in.a.bits.source, 2) node _T_570 = eq(_T_569, UInt<1>(0h0)) node _T_571 = leq(UInt<1>(0h0), uncommonBits_20) node _T_572 = and(_T_570, _T_571) node _T_573 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_574 = and(_T_572, _T_573) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_575 = shr(io.in.a.bits.source, 2) node _T_576 = eq(_T_575, UInt<1>(0h1)) node _T_577 = leq(UInt<1>(0h0), uncommonBits_21) node _T_578 = and(_T_576, _T_577) node _T_579 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_580 = and(_T_578, _T_579) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_581 = shr(io.in.a.bits.source, 2) node _T_582 = eq(_T_581, UInt<2>(0h2)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_22) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_586 = and(_T_584, _T_585) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_587 = shr(io.in.a.bits.source, 2) node _T_588 = eq(_T_587, UInt<2>(0h3)) node _T_589 = leq(UInt<1>(0h0), uncommonBits_23) node _T_590 = and(_T_588, _T_589) node _T_591 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_592 = and(_T_590, _T_591) node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_596 = or(_T_568, _T_574) node _T_597 = or(_T_596, _T_580) node _T_598 = or(_T_597, _T_586) node _T_599 = or(_T_598, _T_592) node _T_600 = or(_T_599, _T_593) node _T_601 = or(_T_600, _T_594) node _T_602 = or(_T_601, _T_595) node _T_603 = and(_T_567, _T_602) node _T_604 = or(UInt<1>(0h0), _T_603) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_604, UInt<1>(0h1), "") : assert_19 node _T_608 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_609 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_610 = and(_T_608, _T_609) node _T_611 = or(UInt<1>(0h0), _T_610) node _T_612 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_613 = cvt(_T_612) node _T_614 = and(_T_613, asSInt(UInt<13>(0h1000))) node _T_615 = asSInt(_T_614) node _T_616 = eq(_T_615, asSInt(UInt<1>(0h0))) node _T_617 = and(_T_611, _T_616) node _T_618 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_619 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_620 = and(_T_618, _T_619) node _T_621 = or(UInt<1>(0h0), _T_620) node _T_622 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_623 = cvt(_T_622) node _T_624 = and(_T_623, asSInt(UInt<14>(0h2000))) node _T_625 = asSInt(_T_624) node _T_626 = eq(_T_625, asSInt(UInt<1>(0h0))) node _T_627 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_628 = cvt(_T_627) node _T_629 = and(_T_628, asSInt(UInt<13>(0h1000))) node _T_630 = asSInt(_T_629) node _T_631 = eq(_T_630, asSInt(UInt<1>(0h0))) node _T_632 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_633 = cvt(_T_632) node _T_634 = and(_T_633, asSInt(UInt<17>(0h10000))) node _T_635 = asSInt(_T_634) node _T_636 = eq(_T_635, asSInt(UInt<1>(0h0))) node _T_637 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_638 = cvt(_T_637) node _T_639 = and(_T_638, asSInt(UInt<18>(0h2f000))) node _T_640 = asSInt(_T_639) node _T_641 = eq(_T_640, asSInt(UInt<1>(0h0))) node _T_642 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_643 = cvt(_T_642) node _T_644 = and(_T_643, asSInt(UInt<17>(0h10000))) node _T_645 = asSInt(_T_644) node _T_646 = eq(_T_645, asSInt(UInt<1>(0h0))) node _T_647 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_648 = cvt(_T_647) node _T_649 = and(_T_648, asSInt(UInt<13>(0h1000))) node _T_650 = asSInt(_T_649) node _T_651 = eq(_T_650, asSInt(UInt<1>(0h0))) node _T_652 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_653 = cvt(_T_652) node _T_654 = and(_T_653, asSInt(UInt<27>(0h4000000))) node _T_655 = asSInt(_T_654) node _T_656 = eq(_T_655, asSInt(UInt<1>(0h0))) node _T_657 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_658 = cvt(_T_657) node _T_659 = and(_T_658, asSInt(UInt<13>(0h1000))) node _T_660 = asSInt(_T_659) node _T_661 = eq(_T_660, asSInt(UInt<1>(0h0))) node _T_662 = or(_T_626, _T_631) node _T_663 = or(_T_662, _T_636) node _T_664 = or(_T_663, _T_641) node _T_665 = or(_T_664, _T_646) node _T_666 = or(_T_665, _T_651) node _T_667 = or(_T_666, _T_656) node _T_668 = or(_T_667, _T_661) node _T_669 = and(_T_621, _T_668) node _T_670 = or(UInt<1>(0h0), _T_617) node _T_671 = or(_T_670, _T_669) node _T_672 = asUInt(reset) node _T_673 = eq(_T_672, UInt<1>(0h0)) when _T_673 : node _T_674 = eq(_T_671, UInt<1>(0h0)) when _T_674 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_671, UInt<1>(0h1), "") : assert_20 node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(source_ok, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(is_aligned, UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_681 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_681, UInt<1>(0h1), "") : assert_23 node _T_685 = eq(io.in.a.bits.mask, mask) node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(_T_685, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_685, UInt<1>(0h1), "") : assert_24 node _T_689 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_689, UInt<1>(0h1), "") : assert_25 node _T_693 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_693 : node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_696 = and(_T_694, _T_695) node _T_697 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_698 = shr(io.in.a.bits.source, 2) node _T_699 = eq(_T_698, UInt<1>(0h0)) node _T_700 = leq(UInt<1>(0h0), uncommonBits_24) node _T_701 = and(_T_699, _T_700) node _T_702 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_703 = and(_T_701, _T_702) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_704 = shr(io.in.a.bits.source, 2) node _T_705 = eq(_T_704, UInt<1>(0h1)) node _T_706 = leq(UInt<1>(0h0), uncommonBits_25) node _T_707 = and(_T_705, _T_706) node _T_708 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_709 = and(_T_707, _T_708) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_710 = shr(io.in.a.bits.source, 2) node _T_711 = eq(_T_710, UInt<2>(0h2)) node _T_712 = leq(UInt<1>(0h0), uncommonBits_26) node _T_713 = and(_T_711, _T_712) node _T_714 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_715 = and(_T_713, _T_714) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_716 = shr(io.in.a.bits.source, 2) node _T_717 = eq(_T_716, UInt<2>(0h3)) node _T_718 = leq(UInt<1>(0h0), uncommonBits_27) node _T_719 = and(_T_717, _T_718) node _T_720 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_721 = and(_T_719, _T_720) node _T_722 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_725 = or(_T_697, _T_703) node _T_726 = or(_T_725, _T_709) node _T_727 = or(_T_726, _T_715) node _T_728 = or(_T_727, _T_721) node _T_729 = or(_T_728, _T_722) node _T_730 = or(_T_729, _T_723) node _T_731 = or(_T_730, _T_724) node _T_732 = and(_T_696, _T_731) node _T_733 = or(UInt<1>(0h0), _T_732) node _T_734 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_735 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_736 = and(_T_734, _T_735) node _T_737 = or(UInt<1>(0h0), _T_736) node _T_738 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<13>(0h1000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = and(_T_737, _T_742) node _T_744 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_745 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_746 = and(_T_744, _T_745) node _T_747 = or(UInt<1>(0h0), _T_746) node _T_748 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_749 = cvt(_T_748) node _T_750 = and(_T_749, asSInt(UInt<14>(0h2000))) node _T_751 = asSInt(_T_750) node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0))) node _T_753 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<13>(0h1000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<18>(0h2f000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_764 = cvt(_T_763) node _T_765 = and(_T_764, asSInt(UInt<17>(0h10000))) node _T_766 = asSInt(_T_765) node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0))) node _T_768 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_769 = cvt(_T_768) node _T_770 = and(_T_769, asSInt(UInt<13>(0h1000))) node _T_771 = asSInt(_T_770) node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0))) node _T_773 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_774 = cvt(_T_773) node _T_775 = and(_T_774, asSInt(UInt<27>(0h4000000))) node _T_776 = asSInt(_T_775) node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0))) node _T_778 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<13>(0h1000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = or(_T_752, _T_757) node _T_784 = or(_T_783, _T_762) node _T_785 = or(_T_784, _T_767) node _T_786 = or(_T_785, _T_772) node _T_787 = or(_T_786, _T_777) node _T_788 = or(_T_787, _T_782) node _T_789 = and(_T_747, _T_788) node _T_790 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_791 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_792 = cvt(_T_791) node _T_793 = and(_T_792, asSInt(UInt<17>(0h10000))) node _T_794 = asSInt(_T_793) node _T_795 = eq(_T_794, asSInt(UInt<1>(0h0))) node _T_796 = and(_T_790, _T_795) node _T_797 = or(UInt<1>(0h0), _T_743) node _T_798 = or(_T_797, _T_789) node _T_799 = or(_T_798, _T_796) node _T_800 = and(_T_733, _T_799) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_800, UInt<1>(0h1), "") : assert_26 node _T_804 = asUInt(reset) node _T_805 = eq(_T_804, UInt<1>(0h0)) when _T_805 : node _T_806 = eq(source_ok, UInt<1>(0h0)) when _T_806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(is_aligned, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_810 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(_T_810, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_810, UInt<1>(0h1), "") : assert_29 node _T_814 = eq(io.in.a.bits.mask, mask) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_814, UInt<1>(0h1), "") : assert_30 node _T_818 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_818 : node _T_819 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_820 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_821 = and(_T_819, _T_820) node _T_822 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_823 = shr(io.in.a.bits.source, 2) node _T_824 = eq(_T_823, UInt<1>(0h0)) node _T_825 = leq(UInt<1>(0h0), uncommonBits_28) node _T_826 = and(_T_824, _T_825) node _T_827 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_828 = and(_T_826, _T_827) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_829 = shr(io.in.a.bits.source, 2) node _T_830 = eq(_T_829, UInt<1>(0h1)) node _T_831 = leq(UInt<1>(0h0), uncommonBits_29) node _T_832 = and(_T_830, _T_831) node _T_833 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_834 = and(_T_832, _T_833) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_835 = shr(io.in.a.bits.source, 2) node _T_836 = eq(_T_835, UInt<2>(0h2)) node _T_837 = leq(UInt<1>(0h0), uncommonBits_30) node _T_838 = and(_T_836, _T_837) node _T_839 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_840 = and(_T_838, _T_839) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_841 = shr(io.in.a.bits.source, 2) node _T_842 = eq(_T_841, UInt<2>(0h3)) node _T_843 = leq(UInt<1>(0h0), uncommonBits_31) node _T_844 = and(_T_842, _T_843) node _T_845 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_846 = and(_T_844, _T_845) node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_850 = or(_T_822, _T_828) node _T_851 = or(_T_850, _T_834) node _T_852 = or(_T_851, _T_840) node _T_853 = or(_T_852, _T_846) node _T_854 = or(_T_853, _T_847) node _T_855 = or(_T_854, _T_848) node _T_856 = or(_T_855, _T_849) node _T_857 = and(_T_821, _T_856) node _T_858 = or(UInt<1>(0h0), _T_857) node _T_859 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_860 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_861 = and(_T_859, _T_860) node _T_862 = or(UInt<1>(0h0), _T_861) node _T_863 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_864 = cvt(_T_863) node _T_865 = and(_T_864, asSInt(UInt<13>(0h1000))) node _T_866 = asSInt(_T_865) node _T_867 = eq(_T_866, asSInt(UInt<1>(0h0))) node _T_868 = and(_T_862, _T_867) node _T_869 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_870 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_871 = and(_T_869, _T_870) node _T_872 = or(UInt<1>(0h0), _T_871) node _T_873 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<14>(0h2000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_879 = cvt(_T_878) node _T_880 = and(_T_879, asSInt(UInt<13>(0h1000))) node _T_881 = asSInt(_T_880) node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0))) node _T_883 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_884 = cvt(_T_883) node _T_885 = and(_T_884, asSInt(UInt<18>(0h2f000))) node _T_886 = asSInt(_T_885) node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0))) node _T_888 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_889 = cvt(_T_888) node _T_890 = and(_T_889, asSInt(UInt<17>(0h10000))) node _T_891 = asSInt(_T_890) node _T_892 = eq(_T_891, asSInt(UInt<1>(0h0))) node _T_893 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_894 = cvt(_T_893) node _T_895 = and(_T_894, asSInt(UInt<13>(0h1000))) node _T_896 = asSInt(_T_895) node _T_897 = eq(_T_896, asSInt(UInt<1>(0h0))) node _T_898 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_899 = cvt(_T_898) node _T_900 = and(_T_899, asSInt(UInt<27>(0h4000000))) node _T_901 = asSInt(_T_900) node _T_902 = eq(_T_901, asSInt(UInt<1>(0h0))) node _T_903 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_904 = cvt(_T_903) node _T_905 = and(_T_904, asSInt(UInt<13>(0h1000))) node _T_906 = asSInt(_T_905) node _T_907 = eq(_T_906, asSInt(UInt<1>(0h0))) node _T_908 = or(_T_877, _T_882) node _T_909 = or(_T_908, _T_887) node _T_910 = or(_T_909, _T_892) node _T_911 = or(_T_910, _T_897) node _T_912 = or(_T_911, _T_902) node _T_913 = or(_T_912, _T_907) node _T_914 = and(_T_872, _T_913) node _T_915 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_916 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_917 = cvt(_T_916) node _T_918 = and(_T_917, asSInt(UInt<17>(0h10000))) node _T_919 = asSInt(_T_918) node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0))) node _T_921 = and(_T_915, _T_920) node _T_922 = or(UInt<1>(0h0), _T_868) node _T_923 = or(_T_922, _T_914) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_858, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_925, UInt<1>(0h1), "") : assert_31 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(source_ok, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_935 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_935, UInt<1>(0h1), "") : assert_34 node _T_939 = not(mask) node _T_940 = and(io.in.a.bits.mask, _T_939) node _T_941 = eq(_T_940, UInt<1>(0h0)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_941, UInt<1>(0h1), "") : assert_35 node _T_945 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_945 : node _T_946 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_947 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_948 = and(_T_946, _T_947) node _T_949 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_950 = shr(io.in.a.bits.source, 2) node _T_951 = eq(_T_950, UInt<1>(0h0)) node _T_952 = leq(UInt<1>(0h0), uncommonBits_32) node _T_953 = and(_T_951, _T_952) node _T_954 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_955 = and(_T_953, _T_954) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_956 = shr(io.in.a.bits.source, 2) node _T_957 = eq(_T_956, UInt<1>(0h1)) node _T_958 = leq(UInt<1>(0h0), uncommonBits_33) node _T_959 = and(_T_957, _T_958) node _T_960 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_961 = and(_T_959, _T_960) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_962 = shr(io.in.a.bits.source, 2) node _T_963 = eq(_T_962, UInt<2>(0h2)) node _T_964 = leq(UInt<1>(0h0), uncommonBits_34) node _T_965 = and(_T_963, _T_964) node _T_966 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_967 = and(_T_965, _T_966) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_968 = shr(io.in.a.bits.source, 2) node _T_969 = eq(_T_968, UInt<2>(0h3)) node _T_970 = leq(UInt<1>(0h0), uncommonBits_35) node _T_971 = and(_T_969, _T_970) node _T_972 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_973 = and(_T_971, _T_972) node _T_974 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_977 = or(_T_949, _T_955) node _T_978 = or(_T_977, _T_961) node _T_979 = or(_T_978, _T_967) node _T_980 = or(_T_979, _T_973) node _T_981 = or(_T_980, _T_974) node _T_982 = or(_T_981, _T_975) node _T_983 = or(_T_982, _T_976) node _T_984 = and(_T_948, _T_983) node _T_985 = or(UInt<1>(0h0), _T_984) node _T_986 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_987 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_988 = and(_T_986, _T_987) node _T_989 = or(UInt<1>(0h0), _T_988) node _T_990 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_991 = cvt(_T_990) node _T_992 = and(_T_991, asSInt(UInt<14>(0h2000))) node _T_993 = asSInt(_T_992) node _T_994 = eq(_T_993, asSInt(UInt<1>(0h0))) node _T_995 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_996 = cvt(_T_995) node _T_997 = and(_T_996, asSInt(UInt<13>(0h1000))) node _T_998 = asSInt(_T_997) node _T_999 = eq(_T_998, asSInt(UInt<1>(0h0))) node _T_1000 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<13>(0h1000))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<18>(0h2f000))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1011 = cvt(_T_1010) node _T_1012 = and(_T_1011, asSInt(UInt<17>(0h10000))) node _T_1013 = asSInt(_T_1012) node _T_1014 = eq(_T_1013, asSInt(UInt<1>(0h0))) node _T_1015 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1016 = cvt(_T_1015) node _T_1017 = and(_T_1016, asSInt(UInt<13>(0h1000))) node _T_1018 = asSInt(_T_1017) node _T_1019 = eq(_T_1018, asSInt(UInt<1>(0h0))) node _T_1020 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1021 = cvt(_T_1020) node _T_1022 = and(_T_1021, asSInt(UInt<27>(0h4000000))) node _T_1023 = asSInt(_T_1022) node _T_1024 = eq(_T_1023, asSInt(UInt<1>(0h0))) node _T_1025 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1026 = cvt(_T_1025) node _T_1027 = and(_T_1026, asSInt(UInt<13>(0h1000))) node _T_1028 = asSInt(_T_1027) node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0))) node _T_1030 = or(_T_994, _T_999) node _T_1031 = or(_T_1030, _T_1004) node _T_1032 = or(_T_1031, _T_1009) node _T_1033 = or(_T_1032, _T_1014) node _T_1034 = or(_T_1033, _T_1019) node _T_1035 = or(_T_1034, _T_1024) node _T_1036 = or(_T_1035, _T_1029) node _T_1037 = and(_T_989, _T_1036) node _T_1038 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1039 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1040 = cvt(_T_1039) node _T_1041 = and(_T_1040, asSInt(UInt<17>(0h10000))) node _T_1042 = asSInt(_T_1041) node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0))) node _T_1044 = and(_T_1038, _T_1043) node _T_1045 = or(UInt<1>(0h0), _T_1037) node _T_1046 = or(_T_1045, _T_1044) node _T_1047 = and(_T_985, _T_1046) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_36 node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(source_ok, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(is_aligned, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1057 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_39 node _T_1061 = eq(io.in.a.bits.mask, mask) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_40 node _T_1065 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1065 : node _T_1066 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1067 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1070 = shr(io.in.a.bits.source, 2) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) node _T_1072 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1073 = and(_T_1071, _T_1072) node _T_1074 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1075 = and(_T_1073, _T_1074) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1076 = shr(io.in.a.bits.source, 2) node _T_1077 = eq(_T_1076, UInt<1>(0h1)) node _T_1078 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1079 = and(_T_1077, _T_1078) node _T_1080 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1081 = and(_T_1079, _T_1080) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1082 = shr(io.in.a.bits.source, 2) node _T_1083 = eq(_T_1082, UInt<2>(0h2)) node _T_1084 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1085 = and(_T_1083, _T_1084) node _T_1086 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1087 = and(_T_1085, _T_1086) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1088 = shr(io.in.a.bits.source, 2) node _T_1089 = eq(_T_1088, UInt<2>(0h3)) node _T_1090 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1091 = and(_T_1089, _T_1090) node _T_1092 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1093 = and(_T_1091, _T_1092) node _T_1094 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1095 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1096 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1097 = or(_T_1069, _T_1075) node _T_1098 = or(_T_1097, _T_1081) node _T_1099 = or(_T_1098, _T_1087) node _T_1100 = or(_T_1099, _T_1093) node _T_1101 = or(_T_1100, _T_1094) node _T_1102 = or(_T_1101, _T_1095) node _T_1103 = or(_T_1102, _T_1096) node _T_1104 = and(_T_1068, _T_1103) node _T_1105 = or(UInt<1>(0h0), _T_1104) node _T_1106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1107 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = or(UInt<1>(0h0), _T_1108) node _T_1110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1111 = cvt(_T_1110) node _T_1112 = and(_T_1111, asSInt(UInt<14>(0h2000))) node _T_1113 = asSInt(_T_1112) node _T_1114 = eq(_T_1113, asSInt(UInt<1>(0h0))) node _T_1115 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1116 = cvt(_T_1115) node _T_1117 = and(_T_1116, asSInt(UInt<13>(0h1000))) node _T_1118 = asSInt(_T_1117) node _T_1119 = eq(_T_1118, asSInt(UInt<1>(0h0))) node _T_1120 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_1121 = cvt(_T_1120) node _T_1122 = and(_T_1121, asSInt(UInt<13>(0h1000))) node _T_1123 = asSInt(_T_1122) node _T_1124 = eq(_T_1123, asSInt(UInt<1>(0h0))) node _T_1125 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1126 = cvt(_T_1125) node _T_1127 = and(_T_1126, asSInt(UInt<18>(0h2f000))) node _T_1128 = asSInt(_T_1127) node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0))) node _T_1130 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1131 = cvt(_T_1130) node _T_1132 = and(_T_1131, asSInt(UInt<17>(0h10000))) node _T_1133 = asSInt(_T_1132) node _T_1134 = eq(_T_1133, asSInt(UInt<1>(0h0))) node _T_1135 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1136 = cvt(_T_1135) node _T_1137 = and(_T_1136, asSInt(UInt<13>(0h1000))) node _T_1138 = asSInt(_T_1137) node _T_1139 = eq(_T_1138, asSInt(UInt<1>(0h0))) node _T_1140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1141 = cvt(_T_1140) node _T_1142 = and(_T_1141, asSInt(UInt<27>(0h4000000))) node _T_1143 = asSInt(_T_1142) node _T_1144 = eq(_T_1143, asSInt(UInt<1>(0h0))) node _T_1145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1146 = cvt(_T_1145) node _T_1147 = and(_T_1146, asSInt(UInt<13>(0h1000))) node _T_1148 = asSInt(_T_1147) node _T_1149 = eq(_T_1148, asSInt(UInt<1>(0h0))) node _T_1150 = or(_T_1114, _T_1119) node _T_1151 = or(_T_1150, _T_1124) node _T_1152 = or(_T_1151, _T_1129) node _T_1153 = or(_T_1152, _T_1134) node _T_1154 = or(_T_1153, _T_1139) node _T_1155 = or(_T_1154, _T_1144) node _T_1156 = or(_T_1155, _T_1149) node _T_1157 = and(_T_1109, _T_1156) node _T_1158 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1159 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1160 = cvt(_T_1159) node _T_1161 = and(_T_1160, asSInt(UInt<17>(0h10000))) node _T_1162 = asSInt(_T_1161) node _T_1163 = eq(_T_1162, asSInt(UInt<1>(0h0))) node _T_1164 = and(_T_1158, _T_1163) node _T_1165 = or(UInt<1>(0h0), _T_1157) node _T_1166 = or(_T_1165, _T_1164) node _T_1167 = and(_T_1105, _T_1166) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_41 node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(source_ok, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(is_aligned, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1177 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_44 node _T_1181 = eq(io.in.a.bits.mask, mask) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_45 node _T_1185 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1185 : node _T_1186 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1187 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1190 = shr(io.in.a.bits.source, 2) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) node _T_1192 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1193 = and(_T_1191, _T_1192) node _T_1194 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1195 = and(_T_1193, _T_1194) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1196 = shr(io.in.a.bits.source, 2) node _T_1197 = eq(_T_1196, UInt<1>(0h1)) node _T_1198 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1199 = and(_T_1197, _T_1198) node _T_1200 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1201 = and(_T_1199, _T_1200) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1202 = shr(io.in.a.bits.source, 2) node _T_1203 = eq(_T_1202, UInt<2>(0h2)) node _T_1204 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1205 = and(_T_1203, _T_1204) node _T_1206 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1207 = and(_T_1205, _T_1206) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1208 = shr(io.in.a.bits.source, 2) node _T_1209 = eq(_T_1208, UInt<2>(0h3)) node _T_1210 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1211 = and(_T_1209, _T_1210) node _T_1212 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1213 = and(_T_1211, _T_1212) node _T_1214 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1215 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1216 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1217 = or(_T_1189, _T_1195) node _T_1218 = or(_T_1217, _T_1201) node _T_1219 = or(_T_1218, _T_1207) node _T_1220 = or(_T_1219, _T_1213) node _T_1221 = or(_T_1220, _T_1214) node _T_1222 = or(_T_1221, _T_1215) node _T_1223 = or(_T_1222, _T_1216) node _T_1224 = and(_T_1188, _T_1223) node _T_1225 = or(UInt<1>(0h0), _T_1224) node _T_1226 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1227 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = or(UInt<1>(0h0), _T_1228) node _T_1230 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<13>(0h1000))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = and(_T_1229, _T_1234) node _T_1236 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1237 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1238 = cvt(_T_1237) node _T_1239 = and(_T_1238, asSInt(UInt<14>(0h2000))) node _T_1240 = asSInt(_T_1239) node _T_1241 = eq(_T_1240, asSInt(UInt<1>(0h0))) node _T_1242 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_1243 = cvt(_T_1242) node _T_1244 = and(_T_1243, asSInt(UInt<13>(0h1000))) node _T_1245 = asSInt(_T_1244) node _T_1246 = eq(_T_1245, asSInt(UInt<1>(0h0))) node _T_1247 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1248 = cvt(_T_1247) node _T_1249 = and(_T_1248, asSInt(UInt<17>(0h10000))) node _T_1250 = asSInt(_T_1249) node _T_1251 = eq(_T_1250, asSInt(UInt<1>(0h0))) node _T_1252 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1253 = cvt(_T_1252) node _T_1254 = and(_T_1253, asSInt(UInt<18>(0h2f000))) node _T_1255 = asSInt(_T_1254) node _T_1256 = eq(_T_1255, asSInt(UInt<1>(0h0))) node _T_1257 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1258 = cvt(_T_1257) node _T_1259 = and(_T_1258, asSInt(UInt<17>(0h10000))) node _T_1260 = asSInt(_T_1259) node _T_1261 = eq(_T_1260, asSInt(UInt<1>(0h0))) node _T_1262 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1263 = cvt(_T_1262) node _T_1264 = and(_T_1263, asSInt(UInt<13>(0h1000))) node _T_1265 = asSInt(_T_1264) node _T_1266 = eq(_T_1265, asSInt(UInt<1>(0h0))) node _T_1267 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1268 = cvt(_T_1267) node _T_1269 = and(_T_1268, asSInt(UInt<27>(0h4000000))) node _T_1270 = asSInt(_T_1269) node _T_1271 = eq(_T_1270, asSInt(UInt<1>(0h0))) node _T_1272 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1273 = cvt(_T_1272) node _T_1274 = and(_T_1273, asSInt(UInt<13>(0h1000))) node _T_1275 = asSInt(_T_1274) node _T_1276 = eq(_T_1275, asSInt(UInt<1>(0h0))) node _T_1277 = or(_T_1241, _T_1246) node _T_1278 = or(_T_1277, _T_1251) node _T_1279 = or(_T_1278, _T_1256) node _T_1280 = or(_T_1279, _T_1261) node _T_1281 = or(_T_1280, _T_1266) node _T_1282 = or(_T_1281, _T_1271) node _T_1283 = or(_T_1282, _T_1276) node _T_1284 = and(_T_1236, _T_1283) node _T_1285 = or(UInt<1>(0h0), _T_1235) node _T_1286 = or(_T_1285, _T_1284) node _T_1287 = and(_T_1225, _T_1286) node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(_T_1287, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1287, UInt<1>(0h1), "") : assert_46 node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(source_ok, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(is_aligned, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1297 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_49 node _T_1301 = eq(io.in.a.bits.mask, mask) node _T_1302 = asUInt(reset) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) when _T_1303 : node _T_1304 = eq(_T_1301, UInt<1>(0h0)) when _T_1304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1301, UInt<1>(0h1), "") : assert_50 node _T_1305 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1306 = asUInt(reset) node _T_1307 = eq(_T_1306, UInt<1>(0h0)) when _T_1307 : node _T_1308 = eq(_T_1305, UInt<1>(0h0)) when _T_1308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1305, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1309 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1310 = asUInt(reset) node _T_1311 = eq(_T_1310, UInt<1>(0h0)) when _T_1311 : node _T_1312 = eq(_T_1309, UInt<1>(0h0)) when _T_1312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1309, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1313 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1313 : node _T_1314 = asUInt(reset) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) when _T_1315 : node _T_1316 = eq(source_ok_1, UInt<1>(0h0)) when _T_1316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1317 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1318 = asUInt(reset) node _T_1319 = eq(_T_1318, UInt<1>(0h0)) when _T_1319 : node _T_1320 = eq(_T_1317, UInt<1>(0h0)) when _T_1320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1317, UInt<1>(0h1), "") : assert_54 node _T_1321 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1322 = asUInt(reset) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) when _T_1323 : node _T_1324 = eq(_T_1321, UInt<1>(0h0)) when _T_1324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1321, UInt<1>(0h1), "") : assert_55 node _T_1325 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1326 = asUInt(reset) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) when _T_1327 : node _T_1328 = eq(_T_1325, UInt<1>(0h0)) when _T_1328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1325, UInt<1>(0h1), "") : assert_56 node _T_1329 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1330 = asUInt(reset) node _T_1331 = eq(_T_1330, UInt<1>(0h0)) when _T_1331 : node _T_1332 = eq(_T_1329, UInt<1>(0h0)) when _T_1332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1329, UInt<1>(0h1), "") : assert_57 node _T_1333 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1333 : node _T_1334 = asUInt(reset) node _T_1335 = eq(_T_1334, UInt<1>(0h0)) when _T_1335 : node _T_1336 = eq(source_ok_1, UInt<1>(0h0)) when _T_1336 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1337 = asUInt(reset) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) when _T_1338 : node _T_1339 = eq(sink_ok, UInt<1>(0h0)) when _T_1339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1340 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_60 node _T_1344 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1345 = asUInt(reset) node _T_1346 = eq(_T_1345, UInt<1>(0h0)) when _T_1346 : node _T_1347 = eq(_T_1344, UInt<1>(0h0)) when _T_1347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1344, UInt<1>(0h1), "") : assert_61 node _T_1348 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1349 = asUInt(reset) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(_T_1348, UInt<1>(0h0)) when _T_1351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1348, UInt<1>(0h1), "") : assert_62 node _T_1352 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_63 node _T_1356 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1357 = or(UInt<1>(0h1), _T_1356) node _T_1358 = asUInt(reset) node _T_1359 = eq(_T_1358, UInt<1>(0h0)) when _T_1359 : node _T_1360 = eq(_T_1357, UInt<1>(0h0)) when _T_1360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1357, UInt<1>(0h1), "") : assert_64 node _T_1361 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1361 : node _T_1362 = asUInt(reset) node _T_1363 = eq(_T_1362, UInt<1>(0h0)) when _T_1363 : node _T_1364 = eq(source_ok_1, UInt<1>(0h0)) when _T_1364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(sink_ok, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1368 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_67 node _T_1372 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(_T_1372, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1372, UInt<1>(0h1), "") : assert_68 node _T_1376 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1377 = asUInt(reset) node _T_1378 = eq(_T_1377, UInt<1>(0h0)) when _T_1378 : node _T_1379 = eq(_T_1376, UInt<1>(0h0)) when _T_1379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1376, UInt<1>(0h1), "") : assert_69 node _T_1380 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1381 = or(_T_1380, io.in.d.bits.corrupt) node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(_T_1381, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1381, UInt<1>(0h1), "") : assert_70 node _T_1385 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1386 = or(UInt<1>(0h1), _T_1385) node _T_1387 = asUInt(reset) node _T_1388 = eq(_T_1387, UInt<1>(0h0)) when _T_1388 : node _T_1389 = eq(_T_1386, UInt<1>(0h0)) when _T_1389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1386, UInt<1>(0h1), "") : assert_71 node _T_1390 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1390 : node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(source_ok_1, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1394 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1395 = asUInt(reset) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) when _T_1396 : node _T_1397 = eq(_T_1394, UInt<1>(0h0)) when _T_1397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1394, UInt<1>(0h1), "") : assert_73 node _T_1398 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_74 node _T_1402 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1403 = or(UInt<1>(0h1), _T_1402) node _T_1404 = asUInt(reset) node _T_1405 = eq(_T_1404, UInt<1>(0h0)) when _T_1405 : node _T_1406 = eq(_T_1403, UInt<1>(0h0)) when _T_1406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1403, UInt<1>(0h1), "") : assert_75 node _T_1407 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1407 : node _T_1408 = asUInt(reset) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(source_ok_1, UInt<1>(0h0)) when _T_1410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1411 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1412 = asUInt(reset) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) when _T_1413 : node _T_1414 = eq(_T_1411, UInt<1>(0h0)) when _T_1414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1411, UInt<1>(0h1), "") : assert_77 node _T_1415 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1416 = or(_T_1415, io.in.d.bits.corrupt) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_78 node _T_1420 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1421 = or(UInt<1>(0h1), _T_1420) node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(_T_1421, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1421, UInt<1>(0h1), "") : assert_79 node _T_1425 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1425 : node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(source_ok_1, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1429 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_81 node _T_1433 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(_T_1433, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1433, UInt<1>(0h1), "") : assert_82 node _T_1437 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1438 = or(UInt<1>(0h1), _T_1437) node _T_1439 = asUInt(reset) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) when _T_1440 : node _T_1441 = eq(_T_1438, UInt<1>(0h0)) when _T_1441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1438, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<6>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1442 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1446 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1447 = asUInt(reset) node _T_1448 = eq(_T_1447, UInt<1>(0h0)) when _T_1448 : node _T_1449 = eq(_T_1446, UInt<1>(0h0)) when _T_1449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1446, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1450 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(_T_1450, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1450, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1454 = eq(a_first, UInt<1>(0h0)) node _T_1455 = and(io.in.a.valid, _T_1454) when _T_1455 : node _T_1456 = eq(io.in.a.bits.opcode, opcode) node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(_T_1456, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1456, UInt<1>(0h1), "") : assert_87 node _T_1460 = eq(io.in.a.bits.param, param) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_88 node _T_1464 = eq(io.in.a.bits.size, size) node _T_1465 = asUInt(reset) node _T_1466 = eq(_T_1465, UInt<1>(0h0)) when _T_1466 : node _T_1467 = eq(_T_1464, UInt<1>(0h0)) when _T_1467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1464, UInt<1>(0h1), "") : assert_89 node _T_1468 = eq(io.in.a.bits.source, source) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_90 node _T_1472 = eq(io.in.a.bits.address, address) node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(_T_1472, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1472, UInt<1>(0h1), "") : assert_91 node _T_1476 = and(io.in.a.ready, io.in.a.valid) node _T_1477 = and(_T_1476, a_first) when _T_1477 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1478 = eq(d_first, UInt<1>(0h0)) node _T_1479 = and(io.in.d.valid, _T_1478) when _T_1479 : node _T_1480 = eq(io.in.d.bits.opcode, opcode_1) node _T_1481 = asUInt(reset) node _T_1482 = eq(_T_1481, UInt<1>(0h0)) when _T_1482 : node _T_1483 = eq(_T_1480, UInt<1>(0h0)) when _T_1483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1480, UInt<1>(0h1), "") : assert_92 node _T_1484 = eq(io.in.d.bits.param, param_1) node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(_T_1484, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1484, UInt<1>(0h1), "") : assert_93 node _T_1488 = eq(io.in.d.bits.size, size_1) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_94 node _T_1492 = eq(io.in.d.bits.source, source_1) node _T_1493 = asUInt(reset) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) when _T_1494 : node _T_1495 = eq(_T_1492, UInt<1>(0h0)) when _T_1495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1492, UInt<1>(0h1), "") : assert_95 node _T_1496 = eq(io.in.d.bits.sink, sink) node _T_1497 = asUInt(reset) node _T_1498 = eq(_T_1497, UInt<1>(0h0)) when _T_1498 : node _T_1499 = eq(_T_1496, UInt<1>(0h0)) when _T_1499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1496, UInt<1>(0h1), "") : assert_96 node _T_1500 = eq(io.in.d.bits.denied, denied) node _T_1501 = asUInt(reset) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) when _T_1502 : node _T_1503 = eq(_T_1500, UInt<1>(0h0)) when _T_1503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1500, UInt<1>(0h1), "") : assert_97 node _T_1504 = and(io.in.d.ready, io.in.d.valid) node _T_1505 = and(_T_1504, d_first) when _T_1505 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<35>, clock, reset, UInt<35>(0h0) regreset inflight_opcodes : UInt<140>, clock, reset, UInt<140>(0h0) regreset inflight_sizes : UInt<280>, clock, reset, UInt<280>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<35> connect a_set, UInt<35>(0h0) wire a_set_wo_ready : UInt<35> connect a_set_wo_ready, UInt<35>(0h0) wire a_opcodes_set : UInt<140> connect a_opcodes_set, UInt<140>(0h0) wire a_sizes_set : UInt<280> connect a_sizes_set, UInt<280>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1506 = and(io.in.a.valid, a_first_1) node _T_1507 = and(_T_1506, UInt<1>(0h1)) when _T_1507 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1508 = and(io.in.a.ready, io.in.a.valid) node _T_1509 = and(_T_1508, a_first_1) node _T_1510 = and(_T_1509, UInt<1>(0h1)) when _T_1510 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1511 = dshr(inflight, io.in.a.bits.source) node _T_1512 = bits(_T_1511, 0, 0) node _T_1513 = eq(_T_1512, UInt<1>(0h0)) node _T_1514 = asUInt(reset) node _T_1515 = eq(_T_1514, UInt<1>(0h0)) when _T_1515 : node _T_1516 = eq(_T_1513, UInt<1>(0h0)) when _T_1516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1513, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<35> connect d_clr, UInt<35>(0h0) wire d_clr_wo_ready : UInt<35> connect d_clr_wo_ready, UInt<35>(0h0) wire d_opcodes_clr : UInt<140> connect d_opcodes_clr, UInt<140>(0h0) wire d_sizes_clr : UInt<280> connect d_sizes_clr, UInt<280>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1517 = and(io.in.d.valid, d_first_1) node _T_1518 = and(_T_1517, UInt<1>(0h1)) node _T_1519 = eq(d_release_ack, UInt<1>(0h0)) node _T_1520 = and(_T_1518, _T_1519) when _T_1520 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1521 = and(io.in.d.ready, io.in.d.valid) node _T_1522 = and(_T_1521, d_first_1) node _T_1523 = and(_T_1522, UInt<1>(0h1)) node _T_1524 = eq(d_release_ack, UInt<1>(0h0)) node _T_1525 = and(_T_1523, _T_1524) when _T_1525 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1526 = and(io.in.d.valid, d_first_1) node _T_1527 = and(_T_1526, UInt<1>(0h1)) node _T_1528 = eq(d_release_ack, UInt<1>(0h0)) node _T_1529 = and(_T_1527, _T_1528) when _T_1529 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1530 = dshr(inflight, io.in.d.bits.source) node _T_1531 = bits(_T_1530, 0, 0) node _T_1532 = or(_T_1531, same_cycle_resp) node _T_1533 = asUInt(reset) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) when _T_1534 : node _T_1535 = eq(_T_1532, UInt<1>(0h0)) when _T_1535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1532, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1536 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1537 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1538 = or(_T_1536, _T_1537) node _T_1539 = asUInt(reset) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) when _T_1540 : node _T_1541 = eq(_T_1538, UInt<1>(0h0)) when _T_1541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1538, UInt<1>(0h1), "") : assert_100 node _T_1542 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1543 = asUInt(reset) node _T_1544 = eq(_T_1543, UInt<1>(0h0)) when _T_1544 : node _T_1545 = eq(_T_1542, UInt<1>(0h0)) when _T_1545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1542, UInt<1>(0h1), "") : assert_101 else : node _T_1546 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1547 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1548 = or(_T_1546, _T_1547) node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(_T_1548, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1548, UInt<1>(0h1), "") : assert_102 node _T_1552 = eq(io.in.d.bits.size, a_size_lookup) node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(_T_1552, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1552, UInt<1>(0h1), "") : assert_103 node _T_1556 = and(io.in.d.valid, d_first_1) node _T_1557 = and(_T_1556, a_first_1) node _T_1558 = and(_T_1557, io.in.a.valid) node _T_1559 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1560 = and(_T_1558, _T_1559) node _T_1561 = eq(d_release_ack, UInt<1>(0h0)) node _T_1562 = and(_T_1560, _T_1561) when _T_1562 : node _T_1563 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1564 = or(_T_1563, io.in.a.ready) node _T_1565 = asUInt(reset) node _T_1566 = eq(_T_1565, UInt<1>(0h0)) when _T_1566 : node _T_1567 = eq(_T_1564, UInt<1>(0h0)) when _T_1567 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1564, UInt<1>(0h1), "") : assert_104 node _T_1568 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1569 = orr(a_set_wo_ready) node _T_1570 = eq(_T_1569, UInt<1>(0h0)) node _T_1571 = or(_T_1568, _T_1570) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_32 node _T_1575 = orr(inflight) node _T_1576 = eq(_T_1575, UInt<1>(0h0)) node _T_1577 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1578 = or(_T_1576, _T_1577) node _T_1579 = lt(watchdog, plusarg_reader.out) node _T_1580 = or(_T_1578, _T_1579) node _T_1581 = asUInt(reset) node _T_1582 = eq(_T_1581, UInt<1>(0h0)) when _T_1582 : node _T_1583 = eq(_T_1580, UInt<1>(0h0)) when _T_1583 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1580, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1584 = and(io.in.a.ready, io.in.a.valid) node _T_1585 = and(io.in.d.ready, io.in.d.valid) node _T_1586 = or(_T_1584, _T_1585) when _T_1586 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<35>, clock, reset, UInt<35>(0h0) regreset inflight_opcodes_1 : UInt<140>, clock, reset, UInt<140>(0h0) regreset inflight_sizes_1 : UInt<280>, clock, reset, UInt<280>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<6>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<6>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<35> connect c_set, UInt<35>(0h0) wire c_set_wo_ready : UInt<35> connect c_set_wo_ready, UInt<35>(0h0) wire c_opcodes_set : UInt<140> connect c_opcodes_set, UInt<140>(0h0) wire c_sizes_set : UInt<280> connect c_sizes_set, UInt<280>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<6>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1587 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1588 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1589 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1590 = and(_T_1588, _T_1589) node _T_1591 = and(_T_1587, _T_1590) when _T_1591 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<6>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1592 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1593 = and(_T_1592, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<6>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1594 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1595 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1596 = and(_T_1594, _T_1595) node _T_1597 = and(_T_1593, _T_1596) when _T_1597 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<6>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<6>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1598 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1599 = bits(_T_1598, 0, 0) node _T_1600 = eq(_T_1599, UInt<1>(0h0)) node _T_1601 = asUInt(reset) node _T_1602 = eq(_T_1601, UInt<1>(0h0)) when _T_1602 : node _T_1603 = eq(_T_1600, UInt<1>(0h0)) when _T_1603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1600, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<35> connect d_clr_1, UInt<35>(0h0) wire d_clr_wo_ready_1 : UInt<35> connect d_clr_wo_ready_1, UInt<35>(0h0) wire d_opcodes_clr_1 : UInt<140> connect d_opcodes_clr_1, UInt<140>(0h0) wire d_sizes_clr_1 : UInt<280> connect d_sizes_clr_1, UInt<280>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1604 = and(io.in.d.valid, d_first_2) node _T_1605 = and(_T_1604, UInt<1>(0h1)) node _T_1606 = and(_T_1605, d_release_ack_1) when _T_1606 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1607 = and(io.in.d.ready, io.in.d.valid) node _T_1608 = and(_T_1607, d_first_2) node _T_1609 = and(_T_1608, UInt<1>(0h1)) node _T_1610 = and(_T_1609, d_release_ack_1) when _T_1610 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1611 = and(io.in.d.valid, d_first_2) node _T_1612 = and(_T_1611, UInt<1>(0h1)) node _T_1613 = and(_T_1612, d_release_ack_1) when _T_1613 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1614 = dshr(inflight_1, io.in.d.bits.source) node _T_1615 = bits(_T_1614, 0, 0) node _T_1616 = or(_T_1615, same_cycle_resp_1) node _T_1617 = asUInt(reset) node _T_1618 = eq(_T_1617, UInt<1>(0h0)) when _T_1618 : node _T_1619 = eq(_T_1616, UInt<1>(0h0)) when _T_1619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1616, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<6>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1620 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1621 = asUInt(reset) node _T_1622 = eq(_T_1621, UInt<1>(0h0)) when _T_1622 : node _T_1623 = eq(_T_1620, UInt<1>(0h0)) when _T_1623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1620, UInt<1>(0h1), "") : assert_109 else : node _T_1624 = eq(io.in.d.bits.size, c_size_lookup) node _T_1625 = asUInt(reset) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) when _T_1626 : node _T_1627 = eq(_T_1624, UInt<1>(0h0)) when _T_1627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1624, UInt<1>(0h1), "") : assert_110 node _T_1628 = and(io.in.d.valid, d_first_2) node _T_1629 = and(_T_1628, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<6>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1630 = and(_T_1629, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1631 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1632 = and(_T_1630, _T_1631) node _T_1633 = and(_T_1632, d_release_ack_1) node _T_1634 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1635 = and(_T_1633, _T_1634) when _T_1635 : node _T_1636 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<6>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1637 = or(_T_1636, _WIRE_27.ready) node _T_1638 = asUInt(reset) node _T_1639 = eq(_T_1638, UInt<1>(0h0)) when _T_1639 : node _T_1640 = eq(_T_1637, UInt<1>(0h0)) when _T_1640 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1637, UInt<1>(0h1), "") : assert_111 node _T_1641 = orr(c_set_wo_ready) when _T_1641 : node _T_1642 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1643 = asUInt(reset) node _T_1644 = eq(_T_1643, UInt<1>(0h0)) when _T_1644 : node _T_1645 = eq(_T_1642, UInt<1>(0h0)) when _T_1645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1642, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_33 node _T_1646 = orr(inflight_1) node _T_1647 = eq(_T_1646, UInt<1>(0h0)) node _T_1648 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1649 = or(_T_1647, _T_1648) node _T_1650 = lt(watchdog_1, plusarg_reader_1.out) node _T_1651 = or(_T_1649, _T_1650) node _T_1652 = asUInt(reset) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) when _T_1653 : node _T_1654 = eq(_T_1651, UInt<1>(0h0)) when _T_1654 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1651, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<6>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1655 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1656 = and(io.in.d.ready, io.in.d.valid) node _T_1657 = or(_T_1655, _T_1656) when _T_1657 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_34 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_35 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_16( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [34:0] inflight; // @[Monitor.scala:614:27] reg [139:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [279:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_0 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_3 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [34:0] inflight_1; // @[Monitor.scala:726:35] reg [279:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_92 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_92( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ZstdCompressorLitRotBuf_3 : input clock : Clock input reset : Reset output io : { flip memwrites_in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>, validbytes : UInt<6>, end_of_message : UInt<1>}}, consumer : { flip user_consumed_bytes : UInt<6>, available_output_bytes : UInt<6>, output_valid : UInt<1>, flip output_ready : UInt<1>, output_data : UInt<256>, output_last_chunk : UInt<1>}} inst incoming_writes_Q of Queue4_WriterBundle_13 connect incoming_writes_Q.clock, clock connect incoming_writes_Q.reset, reset connect incoming_writes_Q.io.enq, io.memwrites_in node _T = and(incoming_writes_Q.io.deq.ready, incoming_writes_Q.io.deq.valid) when _T : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "[lit-rot-buf] dat: 0x%x, bytes: 0x%x, EOM: %d\n", incoming_writes_Q.io.deq.bits.data, incoming_writes_Q.io.deq.bits.validbytes, incoming_writes_Q.io.deq.bits.end_of_message) : printf_1 regreset write_start_index : UInt<6>, clock, reset, UInt<6>(0h0) inst Queue10_UInt8 of Queue10_UInt8_128 connect Queue10_UInt8.clock, clock connect Queue10_UInt8.reset, reset inst Queue10_UInt8_1 of Queue10_UInt8_129 connect Queue10_UInt8_1.clock, clock connect Queue10_UInt8_1.reset, reset inst Queue10_UInt8_2 of Queue10_UInt8_130 connect Queue10_UInt8_2.clock, clock connect Queue10_UInt8_2.reset, reset inst Queue10_UInt8_3 of Queue10_UInt8_131 connect Queue10_UInt8_3.clock, clock connect Queue10_UInt8_3.reset, reset inst Queue10_UInt8_4 of Queue10_UInt8_132 connect Queue10_UInt8_4.clock, clock connect Queue10_UInt8_4.reset, reset inst Queue10_UInt8_5 of Queue10_UInt8_133 connect Queue10_UInt8_5.clock, clock connect Queue10_UInt8_5.reset, reset inst Queue10_UInt8_6 of Queue10_UInt8_134 connect Queue10_UInt8_6.clock, clock connect Queue10_UInt8_6.reset, reset inst Queue10_UInt8_7 of Queue10_UInt8_135 connect Queue10_UInt8_7.clock, clock connect Queue10_UInt8_7.reset, reset inst Queue10_UInt8_8 of Queue10_UInt8_136 connect Queue10_UInt8_8.clock, clock connect Queue10_UInt8_8.reset, reset inst Queue10_UInt8_9 of Queue10_UInt8_137 connect Queue10_UInt8_9.clock, clock connect Queue10_UInt8_9.reset, reset inst Queue10_UInt8_10 of Queue10_UInt8_138 connect Queue10_UInt8_10.clock, clock connect Queue10_UInt8_10.reset, reset inst Queue10_UInt8_11 of Queue10_UInt8_139 connect Queue10_UInt8_11.clock, clock connect Queue10_UInt8_11.reset, reset inst Queue10_UInt8_12 of Queue10_UInt8_140 connect Queue10_UInt8_12.clock, clock connect Queue10_UInt8_12.reset, reset inst Queue10_UInt8_13 of Queue10_UInt8_141 connect Queue10_UInt8_13.clock, clock connect Queue10_UInt8_13.reset, reset inst Queue10_UInt8_14 of Queue10_UInt8_142 connect Queue10_UInt8_14.clock, clock connect Queue10_UInt8_14.reset, reset inst Queue10_UInt8_15 of Queue10_UInt8_143 connect Queue10_UInt8_15.clock, clock connect Queue10_UInt8_15.reset, reset inst Queue10_UInt8_16 of Queue10_UInt8_144 connect Queue10_UInt8_16.clock, clock connect Queue10_UInt8_16.reset, reset inst Queue10_UInt8_17 of Queue10_UInt8_145 connect Queue10_UInt8_17.clock, clock connect Queue10_UInt8_17.reset, reset inst Queue10_UInt8_18 of Queue10_UInt8_146 connect Queue10_UInt8_18.clock, clock connect Queue10_UInt8_18.reset, reset inst Queue10_UInt8_19 of Queue10_UInt8_147 connect Queue10_UInt8_19.clock, clock connect Queue10_UInt8_19.reset, reset inst Queue10_UInt8_20 of Queue10_UInt8_148 connect Queue10_UInt8_20.clock, clock connect Queue10_UInt8_20.reset, reset inst Queue10_UInt8_21 of Queue10_UInt8_149 connect Queue10_UInt8_21.clock, clock connect Queue10_UInt8_21.reset, reset inst Queue10_UInt8_22 of Queue10_UInt8_150 connect Queue10_UInt8_22.clock, clock connect Queue10_UInt8_22.reset, reset inst Queue10_UInt8_23 of Queue10_UInt8_151 connect Queue10_UInt8_23.clock, clock connect Queue10_UInt8_23.reset, reset inst Queue10_UInt8_24 of Queue10_UInt8_152 connect Queue10_UInt8_24.clock, clock connect Queue10_UInt8_24.reset, reset inst Queue10_UInt8_25 of Queue10_UInt8_153 connect Queue10_UInt8_25.clock, clock connect Queue10_UInt8_25.reset, reset inst Queue10_UInt8_26 of Queue10_UInt8_154 connect Queue10_UInt8_26.clock, clock connect Queue10_UInt8_26.reset, reset inst Queue10_UInt8_27 of Queue10_UInt8_155 connect Queue10_UInt8_27.clock, clock connect Queue10_UInt8_27.reset, reset inst Queue10_UInt8_28 of Queue10_UInt8_156 connect Queue10_UInt8_28.clock, clock connect Queue10_UInt8_28.reset, reset inst Queue10_UInt8_29 of Queue10_UInt8_157 connect Queue10_UInt8_29.clock, clock connect Queue10_UInt8_29.reset, reset inst Queue10_UInt8_30 of Queue10_UInt8_158 connect Queue10_UInt8_30.clock, clock connect Queue10_UInt8_30.reset, reset inst Queue10_UInt8_31 of Queue10_UInt8_159 connect Queue10_UInt8_31.clock, clock connect Queue10_UInt8_31.reset, reset connect Queue10_UInt8.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_1.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_2.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_3.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_4.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_5.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_6.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_7.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_8.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_9.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_10.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_11.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_12.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_13.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_14.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_15.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_16.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_17.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_18.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_19.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_20.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_21.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_22.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_23.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_24.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_25.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_26.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_27.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_28.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_29.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_30.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_31.io.enq.bits, UInt<1>(0h0) node _idx_T = add(write_start_index, UInt<1>(0h0)) node idx = rem(_idx_T, UInt<6>(0h20)) node _T_5 = eq(UInt<1>(0h0), idx) when _T_5 : node _T_6 = shl(UInt<1>(0h0), 3) node _T_7 = dshr(incoming_writes_Q.io.deq.bits.data, _T_6) connect Queue10_UInt8.io.enq.bits, _T_7 node _T_8 = eq(UInt<1>(0h1), idx) when _T_8 : node _T_9 = shl(UInt<1>(0h0), 3) node _T_10 = dshr(incoming_writes_Q.io.deq.bits.data, _T_9) connect Queue10_UInt8_1.io.enq.bits, _T_10 node _T_11 = eq(UInt<2>(0h2), idx) when _T_11 : node _T_12 = shl(UInt<1>(0h0), 3) node _T_13 = dshr(incoming_writes_Q.io.deq.bits.data, _T_12) connect Queue10_UInt8_2.io.enq.bits, _T_13 node _T_14 = eq(UInt<2>(0h3), idx) when _T_14 : node _T_15 = shl(UInt<1>(0h0), 3) node _T_16 = dshr(incoming_writes_Q.io.deq.bits.data, _T_15) connect Queue10_UInt8_3.io.enq.bits, _T_16 node _T_17 = eq(UInt<3>(0h4), idx) when _T_17 : node _T_18 = shl(UInt<1>(0h0), 3) node _T_19 = dshr(incoming_writes_Q.io.deq.bits.data, _T_18) connect Queue10_UInt8_4.io.enq.bits, _T_19 node _T_20 = eq(UInt<3>(0h5), idx) when _T_20 : node _T_21 = shl(UInt<1>(0h0), 3) node _T_22 = dshr(incoming_writes_Q.io.deq.bits.data, _T_21) connect Queue10_UInt8_5.io.enq.bits, _T_22 node _T_23 = eq(UInt<3>(0h6), idx) when _T_23 : node _T_24 = shl(UInt<1>(0h0), 3) node _T_25 = dshr(incoming_writes_Q.io.deq.bits.data, _T_24) connect Queue10_UInt8_6.io.enq.bits, _T_25 node _T_26 = eq(UInt<3>(0h7), idx) when _T_26 : node _T_27 = shl(UInt<1>(0h0), 3) node _T_28 = dshr(incoming_writes_Q.io.deq.bits.data, _T_27) connect Queue10_UInt8_7.io.enq.bits, _T_28 node _T_29 = eq(UInt<4>(0h8), idx) when _T_29 : node _T_30 = shl(UInt<1>(0h0), 3) node _T_31 = dshr(incoming_writes_Q.io.deq.bits.data, _T_30) connect Queue10_UInt8_8.io.enq.bits, _T_31 node _T_32 = eq(UInt<4>(0h9), idx) when _T_32 : node _T_33 = shl(UInt<1>(0h0), 3) node _T_34 = dshr(incoming_writes_Q.io.deq.bits.data, _T_33) connect Queue10_UInt8_9.io.enq.bits, _T_34 node _T_35 = eq(UInt<4>(0ha), idx) when _T_35 : node _T_36 = shl(UInt<1>(0h0), 3) node _T_37 = dshr(incoming_writes_Q.io.deq.bits.data, _T_36) connect Queue10_UInt8_10.io.enq.bits, _T_37 node _T_38 = eq(UInt<4>(0hb), idx) when _T_38 : node _T_39 = shl(UInt<1>(0h0), 3) node _T_40 = dshr(incoming_writes_Q.io.deq.bits.data, _T_39) connect Queue10_UInt8_11.io.enq.bits, _T_40 node _T_41 = eq(UInt<4>(0hc), idx) when _T_41 : node _T_42 = shl(UInt<1>(0h0), 3) node _T_43 = dshr(incoming_writes_Q.io.deq.bits.data, _T_42) connect Queue10_UInt8_12.io.enq.bits, _T_43 node _T_44 = eq(UInt<4>(0hd), idx) when _T_44 : node _T_45 = shl(UInt<1>(0h0), 3) node _T_46 = dshr(incoming_writes_Q.io.deq.bits.data, _T_45) connect Queue10_UInt8_13.io.enq.bits, _T_46 node _T_47 = eq(UInt<4>(0he), idx) when _T_47 : node _T_48 = shl(UInt<1>(0h0), 3) node _T_49 = dshr(incoming_writes_Q.io.deq.bits.data, _T_48) connect Queue10_UInt8_14.io.enq.bits, _T_49 node _T_50 = eq(UInt<4>(0hf), idx) when _T_50 : node _T_51 = shl(UInt<1>(0h0), 3) node _T_52 = dshr(incoming_writes_Q.io.deq.bits.data, _T_51) connect Queue10_UInt8_15.io.enq.bits, _T_52 node _T_53 = eq(UInt<5>(0h10), idx) when _T_53 : node _T_54 = shl(UInt<1>(0h0), 3) node _T_55 = dshr(incoming_writes_Q.io.deq.bits.data, _T_54) connect Queue10_UInt8_16.io.enq.bits, _T_55 node _T_56 = eq(UInt<5>(0h11), idx) when _T_56 : node _T_57 = shl(UInt<1>(0h0), 3) node _T_58 = dshr(incoming_writes_Q.io.deq.bits.data, _T_57) connect Queue10_UInt8_17.io.enq.bits, _T_58 node _T_59 = eq(UInt<5>(0h12), idx) when _T_59 : node _T_60 = shl(UInt<1>(0h0), 3) node _T_61 = dshr(incoming_writes_Q.io.deq.bits.data, _T_60) connect Queue10_UInt8_18.io.enq.bits, _T_61 node _T_62 = eq(UInt<5>(0h13), idx) when _T_62 : node _T_63 = shl(UInt<1>(0h0), 3) node _T_64 = dshr(incoming_writes_Q.io.deq.bits.data, _T_63) connect Queue10_UInt8_19.io.enq.bits, _T_64 node _T_65 = eq(UInt<5>(0h14), idx) when _T_65 : node _T_66 = shl(UInt<1>(0h0), 3) node _T_67 = dshr(incoming_writes_Q.io.deq.bits.data, _T_66) connect Queue10_UInt8_20.io.enq.bits, _T_67 node _T_68 = eq(UInt<5>(0h15), idx) when _T_68 : node _T_69 = shl(UInt<1>(0h0), 3) node _T_70 = dshr(incoming_writes_Q.io.deq.bits.data, _T_69) connect Queue10_UInt8_21.io.enq.bits, _T_70 node _T_71 = eq(UInt<5>(0h16), idx) when _T_71 : node _T_72 = shl(UInt<1>(0h0), 3) node _T_73 = dshr(incoming_writes_Q.io.deq.bits.data, _T_72) connect Queue10_UInt8_22.io.enq.bits, _T_73 node _T_74 = eq(UInt<5>(0h17), idx) when _T_74 : node _T_75 = shl(UInt<1>(0h0), 3) node _T_76 = dshr(incoming_writes_Q.io.deq.bits.data, _T_75) connect Queue10_UInt8_23.io.enq.bits, _T_76 node _T_77 = eq(UInt<5>(0h18), idx) when _T_77 : node _T_78 = shl(UInt<1>(0h0), 3) node _T_79 = dshr(incoming_writes_Q.io.deq.bits.data, _T_78) connect Queue10_UInt8_24.io.enq.bits, _T_79 node _T_80 = eq(UInt<5>(0h19), idx) when _T_80 : node _T_81 = shl(UInt<1>(0h0), 3) node _T_82 = dshr(incoming_writes_Q.io.deq.bits.data, _T_81) connect Queue10_UInt8_25.io.enq.bits, _T_82 node _T_83 = eq(UInt<5>(0h1a), idx) when _T_83 : node _T_84 = shl(UInt<1>(0h0), 3) node _T_85 = dshr(incoming_writes_Q.io.deq.bits.data, _T_84) connect Queue10_UInt8_26.io.enq.bits, _T_85 node _T_86 = eq(UInt<5>(0h1b), idx) when _T_86 : node _T_87 = shl(UInt<1>(0h0), 3) node _T_88 = dshr(incoming_writes_Q.io.deq.bits.data, _T_87) connect Queue10_UInt8_27.io.enq.bits, _T_88 node _T_89 = eq(UInt<5>(0h1c), idx) when _T_89 : node _T_90 = shl(UInt<1>(0h0), 3) node _T_91 = dshr(incoming_writes_Q.io.deq.bits.data, _T_90) connect Queue10_UInt8_28.io.enq.bits, _T_91 node _T_92 = eq(UInt<5>(0h1d), idx) when _T_92 : node _T_93 = shl(UInt<1>(0h0), 3) node _T_94 = dshr(incoming_writes_Q.io.deq.bits.data, _T_93) connect Queue10_UInt8_29.io.enq.bits, _T_94 node _T_95 = eq(UInt<5>(0h1e), idx) when _T_95 : node _T_96 = shl(UInt<1>(0h0), 3) node _T_97 = dshr(incoming_writes_Q.io.deq.bits.data, _T_96) connect Queue10_UInt8_30.io.enq.bits, _T_97 node _T_98 = eq(UInt<5>(0h1f), idx) when _T_98 : node _T_99 = shl(UInt<1>(0h0), 3) node _T_100 = dshr(incoming_writes_Q.io.deq.bits.data, _T_99) connect Queue10_UInt8_31.io.enq.bits, _T_100 node _idx_T_1 = add(write_start_index, UInt<1>(0h1)) node idx_1 = rem(_idx_T_1, UInt<6>(0h20)) node _T_101 = eq(UInt<1>(0h0), idx_1) when _T_101 : node _T_102 = shl(UInt<1>(0h1), 3) node _T_103 = dshr(incoming_writes_Q.io.deq.bits.data, _T_102) connect Queue10_UInt8.io.enq.bits, _T_103 node _T_104 = eq(UInt<1>(0h1), idx_1) when _T_104 : node _T_105 = shl(UInt<1>(0h1), 3) node _T_106 = dshr(incoming_writes_Q.io.deq.bits.data, _T_105) connect Queue10_UInt8_1.io.enq.bits, _T_106 node _T_107 = eq(UInt<2>(0h2), idx_1) when _T_107 : node _T_108 = shl(UInt<1>(0h1), 3) node _T_109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_108) connect Queue10_UInt8_2.io.enq.bits, _T_109 node _T_110 = eq(UInt<2>(0h3), idx_1) when _T_110 : node _T_111 = shl(UInt<1>(0h1), 3) node _T_112 = dshr(incoming_writes_Q.io.deq.bits.data, _T_111) connect Queue10_UInt8_3.io.enq.bits, _T_112 node _T_113 = eq(UInt<3>(0h4), idx_1) when _T_113 : node _T_114 = shl(UInt<1>(0h1), 3) node _T_115 = dshr(incoming_writes_Q.io.deq.bits.data, _T_114) connect Queue10_UInt8_4.io.enq.bits, _T_115 node _T_116 = eq(UInt<3>(0h5), idx_1) when _T_116 : node _T_117 = shl(UInt<1>(0h1), 3) node _T_118 = dshr(incoming_writes_Q.io.deq.bits.data, _T_117) connect Queue10_UInt8_5.io.enq.bits, _T_118 node _T_119 = eq(UInt<3>(0h6), idx_1) when _T_119 : node _T_120 = shl(UInt<1>(0h1), 3) node _T_121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_120) connect Queue10_UInt8_6.io.enq.bits, _T_121 node _T_122 = eq(UInt<3>(0h7), idx_1) when _T_122 : node _T_123 = shl(UInt<1>(0h1), 3) node _T_124 = dshr(incoming_writes_Q.io.deq.bits.data, _T_123) connect Queue10_UInt8_7.io.enq.bits, _T_124 node _T_125 = eq(UInt<4>(0h8), idx_1) when _T_125 : node _T_126 = shl(UInt<1>(0h1), 3) node _T_127 = dshr(incoming_writes_Q.io.deq.bits.data, _T_126) connect Queue10_UInt8_8.io.enq.bits, _T_127 node _T_128 = eq(UInt<4>(0h9), idx_1) when _T_128 : node _T_129 = shl(UInt<1>(0h1), 3) node _T_130 = dshr(incoming_writes_Q.io.deq.bits.data, _T_129) connect Queue10_UInt8_9.io.enq.bits, _T_130 node _T_131 = eq(UInt<4>(0ha), idx_1) when _T_131 : node _T_132 = shl(UInt<1>(0h1), 3) node _T_133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_132) connect Queue10_UInt8_10.io.enq.bits, _T_133 node _T_134 = eq(UInt<4>(0hb), idx_1) when _T_134 : node _T_135 = shl(UInt<1>(0h1), 3) node _T_136 = dshr(incoming_writes_Q.io.deq.bits.data, _T_135) connect Queue10_UInt8_11.io.enq.bits, _T_136 node _T_137 = eq(UInt<4>(0hc), idx_1) when _T_137 : node _T_138 = shl(UInt<1>(0h1), 3) node _T_139 = dshr(incoming_writes_Q.io.deq.bits.data, _T_138) connect Queue10_UInt8_12.io.enq.bits, _T_139 node _T_140 = eq(UInt<4>(0hd), idx_1) when _T_140 : node _T_141 = shl(UInt<1>(0h1), 3) node _T_142 = dshr(incoming_writes_Q.io.deq.bits.data, _T_141) connect Queue10_UInt8_13.io.enq.bits, _T_142 node _T_143 = eq(UInt<4>(0he), idx_1) when _T_143 : node _T_144 = shl(UInt<1>(0h1), 3) node _T_145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_144) connect Queue10_UInt8_14.io.enq.bits, _T_145 node _T_146 = eq(UInt<4>(0hf), idx_1) when _T_146 : node _T_147 = shl(UInt<1>(0h1), 3) node _T_148 = dshr(incoming_writes_Q.io.deq.bits.data, _T_147) connect Queue10_UInt8_15.io.enq.bits, _T_148 node _T_149 = eq(UInt<5>(0h10), idx_1) when _T_149 : node _T_150 = shl(UInt<1>(0h1), 3) node _T_151 = dshr(incoming_writes_Q.io.deq.bits.data, _T_150) connect Queue10_UInt8_16.io.enq.bits, _T_151 node _T_152 = eq(UInt<5>(0h11), idx_1) when _T_152 : node _T_153 = shl(UInt<1>(0h1), 3) node _T_154 = dshr(incoming_writes_Q.io.deq.bits.data, _T_153) connect Queue10_UInt8_17.io.enq.bits, _T_154 node _T_155 = eq(UInt<5>(0h12), idx_1) when _T_155 : node _T_156 = shl(UInt<1>(0h1), 3) node _T_157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_156) connect Queue10_UInt8_18.io.enq.bits, _T_157 node _T_158 = eq(UInt<5>(0h13), idx_1) when _T_158 : node _T_159 = shl(UInt<1>(0h1), 3) node _T_160 = dshr(incoming_writes_Q.io.deq.bits.data, _T_159) connect Queue10_UInt8_19.io.enq.bits, _T_160 node _T_161 = eq(UInt<5>(0h14), idx_1) when _T_161 : node _T_162 = shl(UInt<1>(0h1), 3) node _T_163 = dshr(incoming_writes_Q.io.deq.bits.data, _T_162) connect Queue10_UInt8_20.io.enq.bits, _T_163 node _T_164 = eq(UInt<5>(0h15), idx_1) when _T_164 : node _T_165 = shl(UInt<1>(0h1), 3) node _T_166 = dshr(incoming_writes_Q.io.deq.bits.data, _T_165) connect Queue10_UInt8_21.io.enq.bits, _T_166 node _T_167 = eq(UInt<5>(0h16), idx_1) when _T_167 : node _T_168 = shl(UInt<1>(0h1), 3) node _T_169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_168) connect Queue10_UInt8_22.io.enq.bits, _T_169 node _T_170 = eq(UInt<5>(0h17), idx_1) when _T_170 : node _T_171 = shl(UInt<1>(0h1), 3) node _T_172 = dshr(incoming_writes_Q.io.deq.bits.data, _T_171) connect Queue10_UInt8_23.io.enq.bits, _T_172 node _T_173 = eq(UInt<5>(0h18), idx_1) when _T_173 : node _T_174 = shl(UInt<1>(0h1), 3) node _T_175 = dshr(incoming_writes_Q.io.deq.bits.data, _T_174) connect Queue10_UInt8_24.io.enq.bits, _T_175 node _T_176 = eq(UInt<5>(0h19), idx_1) when _T_176 : node _T_177 = shl(UInt<1>(0h1), 3) node _T_178 = dshr(incoming_writes_Q.io.deq.bits.data, _T_177) connect Queue10_UInt8_25.io.enq.bits, _T_178 node _T_179 = eq(UInt<5>(0h1a), idx_1) when _T_179 : node _T_180 = shl(UInt<1>(0h1), 3) node _T_181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_180) connect Queue10_UInt8_26.io.enq.bits, _T_181 node _T_182 = eq(UInt<5>(0h1b), idx_1) when _T_182 : node _T_183 = shl(UInt<1>(0h1), 3) node _T_184 = dshr(incoming_writes_Q.io.deq.bits.data, _T_183) connect Queue10_UInt8_27.io.enq.bits, _T_184 node _T_185 = eq(UInt<5>(0h1c), idx_1) when _T_185 : node _T_186 = shl(UInt<1>(0h1), 3) node _T_187 = dshr(incoming_writes_Q.io.deq.bits.data, _T_186) connect Queue10_UInt8_28.io.enq.bits, _T_187 node _T_188 = eq(UInt<5>(0h1d), idx_1) when _T_188 : node _T_189 = shl(UInt<1>(0h1), 3) node _T_190 = dshr(incoming_writes_Q.io.deq.bits.data, _T_189) connect Queue10_UInt8_29.io.enq.bits, _T_190 node _T_191 = eq(UInt<5>(0h1e), idx_1) when _T_191 : node _T_192 = shl(UInt<1>(0h1), 3) node _T_193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_192) connect Queue10_UInt8_30.io.enq.bits, _T_193 node _T_194 = eq(UInt<5>(0h1f), idx_1) when _T_194 : node _T_195 = shl(UInt<1>(0h1), 3) node _T_196 = dshr(incoming_writes_Q.io.deq.bits.data, _T_195) connect Queue10_UInt8_31.io.enq.bits, _T_196 node _idx_T_2 = add(write_start_index, UInt<2>(0h2)) node idx_2 = rem(_idx_T_2, UInt<6>(0h20)) node _T_197 = eq(UInt<1>(0h0), idx_2) when _T_197 : node _T_198 = shl(UInt<2>(0h2), 3) node _T_199 = dshr(incoming_writes_Q.io.deq.bits.data, _T_198) connect Queue10_UInt8.io.enq.bits, _T_199 node _T_200 = eq(UInt<1>(0h1), idx_2) when _T_200 : node _T_201 = shl(UInt<2>(0h2), 3) node _T_202 = dshr(incoming_writes_Q.io.deq.bits.data, _T_201) connect Queue10_UInt8_1.io.enq.bits, _T_202 node _T_203 = eq(UInt<2>(0h2), idx_2) when _T_203 : node _T_204 = shl(UInt<2>(0h2), 3) node _T_205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_204) connect Queue10_UInt8_2.io.enq.bits, _T_205 node _T_206 = eq(UInt<2>(0h3), idx_2) when _T_206 : node _T_207 = shl(UInt<2>(0h2), 3) node _T_208 = dshr(incoming_writes_Q.io.deq.bits.data, _T_207) connect Queue10_UInt8_3.io.enq.bits, _T_208 node _T_209 = eq(UInt<3>(0h4), idx_2) when _T_209 : node _T_210 = shl(UInt<2>(0h2), 3) node _T_211 = dshr(incoming_writes_Q.io.deq.bits.data, _T_210) connect Queue10_UInt8_4.io.enq.bits, _T_211 node _T_212 = eq(UInt<3>(0h5), idx_2) when _T_212 : node _T_213 = shl(UInt<2>(0h2), 3) node _T_214 = dshr(incoming_writes_Q.io.deq.bits.data, _T_213) connect Queue10_UInt8_5.io.enq.bits, _T_214 node _T_215 = eq(UInt<3>(0h6), idx_2) when _T_215 : node _T_216 = shl(UInt<2>(0h2), 3) node _T_217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_216) connect Queue10_UInt8_6.io.enq.bits, _T_217 node _T_218 = eq(UInt<3>(0h7), idx_2) when _T_218 : node _T_219 = shl(UInt<2>(0h2), 3) node _T_220 = dshr(incoming_writes_Q.io.deq.bits.data, _T_219) connect Queue10_UInt8_7.io.enq.bits, _T_220 node _T_221 = eq(UInt<4>(0h8), idx_2) when _T_221 : node _T_222 = shl(UInt<2>(0h2), 3) node _T_223 = dshr(incoming_writes_Q.io.deq.bits.data, _T_222) connect Queue10_UInt8_8.io.enq.bits, _T_223 node _T_224 = eq(UInt<4>(0h9), idx_2) when _T_224 : node _T_225 = shl(UInt<2>(0h2), 3) node _T_226 = dshr(incoming_writes_Q.io.deq.bits.data, _T_225) connect Queue10_UInt8_9.io.enq.bits, _T_226 node _T_227 = eq(UInt<4>(0ha), idx_2) when _T_227 : node _T_228 = shl(UInt<2>(0h2), 3) node _T_229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_228) connect Queue10_UInt8_10.io.enq.bits, _T_229 node _T_230 = eq(UInt<4>(0hb), idx_2) when _T_230 : node _T_231 = shl(UInt<2>(0h2), 3) node _T_232 = dshr(incoming_writes_Q.io.deq.bits.data, _T_231) connect Queue10_UInt8_11.io.enq.bits, _T_232 node _T_233 = eq(UInt<4>(0hc), idx_2) when _T_233 : node _T_234 = shl(UInt<2>(0h2), 3) node _T_235 = dshr(incoming_writes_Q.io.deq.bits.data, _T_234) connect Queue10_UInt8_12.io.enq.bits, _T_235 node _T_236 = eq(UInt<4>(0hd), idx_2) when _T_236 : node _T_237 = shl(UInt<2>(0h2), 3) node _T_238 = dshr(incoming_writes_Q.io.deq.bits.data, _T_237) connect Queue10_UInt8_13.io.enq.bits, _T_238 node _T_239 = eq(UInt<4>(0he), idx_2) when _T_239 : node _T_240 = shl(UInt<2>(0h2), 3) node _T_241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_240) connect Queue10_UInt8_14.io.enq.bits, _T_241 node _T_242 = eq(UInt<4>(0hf), idx_2) when _T_242 : node _T_243 = shl(UInt<2>(0h2), 3) node _T_244 = dshr(incoming_writes_Q.io.deq.bits.data, _T_243) connect Queue10_UInt8_15.io.enq.bits, _T_244 node _T_245 = eq(UInt<5>(0h10), idx_2) when _T_245 : node _T_246 = shl(UInt<2>(0h2), 3) node _T_247 = dshr(incoming_writes_Q.io.deq.bits.data, _T_246) connect Queue10_UInt8_16.io.enq.bits, _T_247 node _T_248 = eq(UInt<5>(0h11), idx_2) when _T_248 : node _T_249 = shl(UInt<2>(0h2), 3) node _T_250 = dshr(incoming_writes_Q.io.deq.bits.data, _T_249) connect Queue10_UInt8_17.io.enq.bits, _T_250 node _T_251 = eq(UInt<5>(0h12), idx_2) when _T_251 : node _T_252 = shl(UInt<2>(0h2), 3) node _T_253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_252) connect Queue10_UInt8_18.io.enq.bits, _T_253 node _T_254 = eq(UInt<5>(0h13), idx_2) when _T_254 : node _T_255 = shl(UInt<2>(0h2), 3) node _T_256 = dshr(incoming_writes_Q.io.deq.bits.data, _T_255) connect Queue10_UInt8_19.io.enq.bits, _T_256 node _T_257 = eq(UInt<5>(0h14), idx_2) when _T_257 : node _T_258 = shl(UInt<2>(0h2), 3) node _T_259 = dshr(incoming_writes_Q.io.deq.bits.data, _T_258) connect Queue10_UInt8_20.io.enq.bits, _T_259 node _T_260 = eq(UInt<5>(0h15), idx_2) when _T_260 : node _T_261 = shl(UInt<2>(0h2), 3) node _T_262 = dshr(incoming_writes_Q.io.deq.bits.data, _T_261) connect Queue10_UInt8_21.io.enq.bits, _T_262 node _T_263 = eq(UInt<5>(0h16), idx_2) when _T_263 : node _T_264 = shl(UInt<2>(0h2), 3) node _T_265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_264) connect Queue10_UInt8_22.io.enq.bits, _T_265 node _T_266 = eq(UInt<5>(0h17), idx_2) when _T_266 : node _T_267 = shl(UInt<2>(0h2), 3) node _T_268 = dshr(incoming_writes_Q.io.deq.bits.data, _T_267) connect Queue10_UInt8_23.io.enq.bits, _T_268 node _T_269 = eq(UInt<5>(0h18), idx_2) when _T_269 : node _T_270 = shl(UInt<2>(0h2), 3) node _T_271 = dshr(incoming_writes_Q.io.deq.bits.data, _T_270) connect Queue10_UInt8_24.io.enq.bits, _T_271 node _T_272 = eq(UInt<5>(0h19), idx_2) when _T_272 : node _T_273 = shl(UInt<2>(0h2), 3) node _T_274 = dshr(incoming_writes_Q.io.deq.bits.data, _T_273) connect Queue10_UInt8_25.io.enq.bits, _T_274 node _T_275 = eq(UInt<5>(0h1a), idx_2) when _T_275 : node _T_276 = shl(UInt<2>(0h2), 3) node _T_277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_276) connect Queue10_UInt8_26.io.enq.bits, _T_277 node _T_278 = eq(UInt<5>(0h1b), idx_2) when _T_278 : node _T_279 = shl(UInt<2>(0h2), 3) node _T_280 = dshr(incoming_writes_Q.io.deq.bits.data, _T_279) connect Queue10_UInt8_27.io.enq.bits, _T_280 node _T_281 = eq(UInt<5>(0h1c), idx_2) when _T_281 : node _T_282 = shl(UInt<2>(0h2), 3) node _T_283 = dshr(incoming_writes_Q.io.deq.bits.data, _T_282) connect Queue10_UInt8_28.io.enq.bits, _T_283 node _T_284 = eq(UInt<5>(0h1d), idx_2) when _T_284 : node _T_285 = shl(UInt<2>(0h2), 3) node _T_286 = dshr(incoming_writes_Q.io.deq.bits.data, _T_285) connect Queue10_UInt8_29.io.enq.bits, _T_286 node _T_287 = eq(UInt<5>(0h1e), idx_2) when _T_287 : node _T_288 = shl(UInt<2>(0h2), 3) node _T_289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_288) connect Queue10_UInt8_30.io.enq.bits, _T_289 node _T_290 = eq(UInt<5>(0h1f), idx_2) when _T_290 : node _T_291 = shl(UInt<2>(0h2), 3) node _T_292 = dshr(incoming_writes_Q.io.deq.bits.data, _T_291) connect Queue10_UInt8_31.io.enq.bits, _T_292 node _idx_T_3 = add(write_start_index, UInt<2>(0h3)) node idx_3 = rem(_idx_T_3, UInt<6>(0h20)) node _T_293 = eq(UInt<1>(0h0), idx_3) when _T_293 : node _T_294 = shl(UInt<2>(0h3), 3) node _T_295 = dshr(incoming_writes_Q.io.deq.bits.data, _T_294) connect Queue10_UInt8.io.enq.bits, _T_295 node _T_296 = eq(UInt<1>(0h1), idx_3) when _T_296 : node _T_297 = shl(UInt<2>(0h3), 3) node _T_298 = dshr(incoming_writes_Q.io.deq.bits.data, _T_297) connect Queue10_UInt8_1.io.enq.bits, _T_298 node _T_299 = eq(UInt<2>(0h2), idx_3) when _T_299 : node _T_300 = shl(UInt<2>(0h3), 3) node _T_301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_300) connect Queue10_UInt8_2.io.enq.bits, _T_301 node _T_302 = eq(UInt<2>(0h3), idx_3) when _T_302 : node _T_303 = shl(UInt<2>(0h3), 3) node _T_304 = dshr(incoming_writes_Q.io.deq.bits.data, _T_303) connect Queue10_UInt8_3.io.enq.bits, _T_304 node _T_305 = eq(UInt<3>(0h4), idx_3) when _T_305 : node _T_306 = shl(UInt<2>(0h3), 3) node _T_307 = dshr(incoming_writes_Q.io.deq.bits.data, _T_306) connect Queue10_UInt8_4.io.enq.bits, _T_307 node _T_308 = eq(UInt<3>(0h5), idx_3) when _T_308 : node _T_309 = shl(UInt<2>(0h3), 3) node _T_310 = dshr(incoming_writes_Q.io.deq.bits.data, _T_309) connect Queue10_UInt8_5.io.enq.bits, _T_310 node _T_311 = eq(UInt<3>(0h6), idx_3) when _T_311 : node _T_312 = shl(UInt<2>(0h3), 3) node _T_313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_312) connect Queue10_UInt8_6.io.enq.bits, _T_313 node _T_314 = eq(UInt<3>(0h7), idx_3) when _T_314 : node _T_315 = shl(UInt<2>(0h3), 3) node _T_316 = dshr(incoming_writes_Q.io.deq.bits.data, _T_315) connect Queue10_UInt8_7.io.enq.bits, _T_316 node _T_317 = eq(UInt<4>(0h8), idx_3) when _T_317 : node _T_318 = shl(UInt<2>(0h3), 3) node _T_319 = dshr(incoming_writes_Q.io.deq.bits.data, _T_318) connect Queue10_UInt8_8.io.enq.bits, _T_319 node _T_320 = eq(UInt<4>(0h9), idx_3) when _T_320 : node _T_321 = shl(UInt<2>(0h3), 3) node _T_322 = dshr(incoming_writes_Q.io.deq.bits.data, _T_321) connect Queue10_UInt8_9.io.enq.bits, _T_322 node _T_323 = eq(UInt<4>(0ha), idx_3) when _T_323 : node _T_324 = shl(UInt<2>(0h3), 3) node _T_325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_324) connect Queue10_UInt8_10.io.enq.bits, _T_325 node _T_326 = eq(UInt<4>(0hb), idx_3) when _T_326 : node _T_327 = shl(UInt<2>(0h3), 3) node _T_328 = dshr(incoming_writes_Q.io.deq.bits.data, _T_327) connect Queue10_UInt8_11.io.enq.bits, _T_328 node _T_329 = eq(UInt<4>(0hc), idx_3) when _T_329 : node _T_330 = shl(UInt<2>(0h3), 3) node _T_331 = dshr(incoming_writes_Q.io.deq.bits.data, _T_330) connect Queue10_UInt8_12.io.enq.bits, _T_331 node _T_332 = eq(UInt<4>(0hd), idx_3) when _T_332 : node _T_333 = shl(UInt<2>(0h3), 3) node _T_334 = dshr(incoming_writes_Q.io.deq.bits.data, _T_333) connect Queue10_UInt8_13.io.enq.bits, _T_334 node _T_335 = eq(UInt<4>(0he), idx_3) when _T_335 : node _T_336 = shl(UInt<2>(0h3), 3) node _T_337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_336) connect Queue10_UInt8_14.io.enq.bits, _T_337 node _T_338 = eq(UInt<4>(0hf), idx_3) when _T_338 : node _T_339 = shl(UInt<2>(0h3), 3) node _T_340 = dshr(incoming_writes_Q.io.deq.bits.data, _T_339) connect Queue10_UInt8_15.io.enq.bits, _T_340 node _T_341 = eq(UInt<5>(0h10), idx_3) when _T_341 : node _T_342 = shl(UInt<2>(0h3), 3) node _T_343 = dshr(incoming_writes_Q.io.deq.bits.data, _T_342) connect Queue10_UInt8_16.io.enq.bits, _T_343 node _T_344 = eq(UInt<5>(0h11), idx_3) when _T_344 : node _T_345 = shl(UInt<2>(0h3), 3) node _T_346 = dshr(incoming_writes_Q.io.deq.bits.data, _T_345) connect Queue10_UInt8_17.io.enq.bits, _T_346 node _T_347 = eq(UInt<5>(0h12), idx_3) when _T_347 : node _T_348 = shl(UInt<2>(0h3), 3) node _T_349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_348) connect Queue10_UInt8_18.io.enq.bits, _T_349 node _T_350 = eq(UInt<5>(0h13), idx_3) when _T_350 : node _T_351 = shl(UInt<2>(0h3), 3) node _T_352 = dshr(incoming_writes_Q.io.deq.bits.data, _T_351) connect Queue10_UInt8_19.io.enq.bits, _T_352 node _T_353 = eq(UInt<5>(0h14), idx_3) when _T_353 : node _T_354 = shl(UInt<2>(0h3), 3) node _T_355 = dshr(incoming_writes_Q.io.deq.bits.data, _T_354) connect Queue10_UInt8_20.io.enq.bits, _T_355 node _T_356 = eq(UInt<5>(0h15), idx_3) when _T_356 : node _T_357 = shl(UInt<2>(0h3), 3) node _T_358 = dshr(incoming_writes_Q.io.deq.bits.data, _T_357) connect Queue10_UInt8_21.io.enq.bits, _T_358 node _T_359 = eq(UInt<5>(0h16), idx_3) when _T_359 : node _T_360 = shl(UInt<2>(0h3), 3) node _T_361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_360) connect Queue10_UInt8_22.io.enq.bits, _T_361 node _T_362 = eq(UInt<5>(0h17), idx_3) when _T_362 : node _T_363 = shl(UInt<2>(0h3), 3) node _T_364 = dshr(incoming_writes_Q.io.deq.bits.data, _T_363) connect Queue10_UInt8_23.io.enq.bits, _T_364 node _T_365 = eq(UInt<5>(0h18), idx_3) when _T_365 : node _T_366 = shl(UInt<2>(0h3), 3) node _T_367 = dshr(incoming_writes_Q.io.deq.bits.data, _T_366) connect Queue10_UInt8_24.io.enq.bits, _T_367 node _T_368 = eq(UInt<5>(0h19), idx_3) when _T_368 : node _T_369 = shl(UInt<2>(0h3), 3) node _T_370 = dshr(incoming_writes_Q.io.deq.bits.data, _T_369) connect Queue10_UInt8_25.io.enq.bits, _T_370 node _T_371 = eq(UInt<5>(0h1a), idx_3) when _T_371 : node _T_372 = shl(UInt<2>(0h3), 3) node _T_373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_372) connect Queue10_UInt8_26.io.enq.bits, _T_373 node _T_374 = eq(UInt<5>(0h1b), idx_3) when _T_374 : node _T_375 = shl(UInt<2>(0h3), 3) node _T_376 = dshr(incoming_writes_Q.io.deq.bits.data, _T_375) connect Queue10_UInt8_27.io.enq.bits, _T_376 node _T_377 = eq(UInt<5>(0h1c), idx_3) when _T_377 : node _T_378 = shl(UInt<2>(0h3), 3) node _T_379 = dshr(incoming_writes_Q.io.deq.bits.data, _T_378) connect Queue10_UInt8_28.io.enq.bits, _T_379 node _T_380 = eq(UInt<5>(0h1d), idx_3) when _T_380 : node _T_381 = shl(UInt<2>(0h3), 3) node _T_382 = dshr(incoming_writes_Q.io.deq.bits.data, _T_381) connect Queue10_UInt8_29.io.enq.bits, _T_382 node _T_383 = eq(UInt<5>(0h1e), idx_3) when _T_383 : node _T_384 = shl(UInt<2>(0h3), 3) node _T_385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_384) connect Queue10_UInt8_30.io.enq.bits, _T_385 node _T_386 = eq(UInt<5>(0h1f), idx_3) when _T_386 : node _T_387 = shl(UInt<2>(0h3), 3) node _T_388 = dshr(incoming_writes_Q.io.deq.bits.data, _T_387) connect Queue10_UInt8_31.io.enq.bits, _T_388 node _idx_T_4 = add(write_start_index, UInt<3>(0h4)) node idx_4 = rem(_idx_T_4, UInt<6>(0h20)) node _T_389 = eq(UInt<1>(0h0), idx_4) when _T_389 : node _T_390 = shl(UInt<3>(0h4), 3) node _T_391 = dshr(incoming_writes_Q.io.deq.bits.data, _T_390) connect Queue10_UInt8.io.enq.bits, _T_391 node _T_392 = eq(UInt<1>(0h1), idx_4) when _T_392 : node _T_393 = shl(UInt<3>(0h4), 3) node _T_394 = dshr(incoming_writes_Q.io.deq.bits.data, _T_393) connect Queue10_UInt8_1.io.enq.bits, _T_394 node _T_395 = eq(UInt<2>(0h2), idx_4) when _T_395 : node _T_396 = shl(UInt<3>(0h4), 3) node _T_397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_396) connect Queue10_UInt8_2.io.enq.bits, _T_397 node _T_398 = eq(UInt<2>(0h3), idx_4) when _T_398 : node _T_399 = shl(UInt<3>(0h4), 3) node _T_400 = dshr(incoming_writes_Q.io.deq.bits.data, _T_399) connect Queue10_UInt8_3.io.enq.bits, _T_400 node _T_401 = eq(UInt<3>(0h4), idx_4) when _T_401 : node _T_402 = shl(UInt<3>(0h4), 3) node _T_403 = dshr(incoming_writes_Q.io.deq.bits.data, _T_402) connect Queue10_UInt8_4.io.enq.bits, _T_403 node _T_404 = eq(UInt<3>(0h5), idx_4) when _T_404 : node _T_405 = shl(UInt<3>(0h4), 3) node _T_406 = dshr(incoming_writes_Q.io.deq.bits.data, _T_405) connect Queue10_UInt8_5.io.enq.bits, _T_406 node _T_407 = eq(UInt<3>(0h6), idx_4) when _T_407 : node _T_408 = shl(UInt<3>(0h4), 3) node _T_409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_408) connect Queue10_UInt8_6.io.enq.bits, _T_409 node _T_410 = eq(UInt<3>(0h7), idx_4) when _T_410 : node _T_411 = shl(UInt<3>(0h4), 3) node _T_412 = dshr(incoming_writes_Q.io.deq.bits.data, _T_411) connect Queue10_UInt8_7.io.enq.bits, _T_412 node _T_413 = eq(UInt<4>(0h8), idx_4) when _T_413 : node _T_414 = shl(UInt<3>(0h4), 3) node _T_415 = dshr(incoming_writes_Q.io.deq.bits.data, _T_414) connect Queue10_UInt8_8.io.enq.bits, _T_415 node _T_416 = eq(UInt<4>(0h9), idx_4) when _T_416 : node _T_417 = shl(UInt<3>(0h4), 3) node _T_418 = dshr(incoming_writes_Q.io.deq.bits.data, _T_417) connect Queue10_UInt8_9.io.enq.bits, _T_418 node _T_419 = eq(UInt<4>(0ha), idx_4) when _T_419 : node _T_420 = shl(UInt<3>(0h4), 3) node _T_421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_420) connect Queue10_UInt8_10.io.enq.bits, _T_421 node _T_422 = eq(UInt<4>(0hb), idx_4) when _T_422 : node _T_423 = shl(UInt<3>(0h4), 3) node _T_424 = dshr(incoming_writes_Q.io.deq.bits.data, _T_423) connect Queue10_UInt8_11.io.enq.bits, _T_424 node _T_425 = eq(UInt<4>(0hc), idx_4) when _T_425 : node _T_426 = shl(UInt<3>(0h4), 3) node _T_427 = dshr(incoming_writes_Q.io.deq.bits.data, _T_426) connect Queue10_UInt8_12.io.enq.bits, _T_427 node _T_428 = eq(UInt<4>(0hd), idx_4) when _T_428 : node _T_429 = shl(UInt<3>(0h4), 3) node _T_430 = dshr(incoming_writes_Q.io.deq.bits.data, _T_429) connect Queue10_UInt8_13.io.enq.bits, _T_430 node _T_431 = eq(UInt<4>(0he), idx_4) when _T_431 : node _T_432 = shl(UInt<3>(0h4), 3) node _T_433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_432) connect Queue10_UInt8_14.io.enq.bits, _T_433 node _T_434 = eq(UInt<4>(0hf), idx_4) when _T_434 : node _T_435 = shl(UInt<3>(0h4), 3) node _T_436 = dshr(incoming_writes_Q.io.deq.bits.data, _T_435) connect Queue10_UInt8_15.io.enq.bits, _T_436 node _T_437 = eq(UInt<5>(0h10), idx_4) when _T_437 : node _T_438 = shl(UInt<3>(0h4), 3) node _T_439 = dshr(incoming_writes_Q.io.deq.bits.data, _T_438) connect Queue10_UInt8_16.io.enq.bits, _T_439 node _T_440 = eq(UInt<5>(0h11), idx_4) when _T_440 : node _T_441 = shl(UInt<3>(0h4), 3) node _T_442 = dshr(incoming_writes_Q.io.deq.bits.data, _T_441) connect Queue10_UInt8_17.io.enq.bits, _T_442 node _T_443 = eq(UInt<5>(0h12), idx_4) when _T_443 : node _T_444 = shl(UInt<3>(0h4), 3) node _T_445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_444) connect Queue10_UInt8_18.io.enq.bits, _T_445 node _T_446 = eq(UInt<5>(0h13), idx_4) when _T_446 : node _T_447 = shl(UInt<3>(0h4), 3) node _T_448 = dshr(incoming_writes_Q.io.deq.bits.data, _T_447) connect Queue10_UInt8_19.io.enq.bits, _T_448 node _T_449 = eq(UInt<5>(0h14), idx_4) when _T_449 : node _T_450 = shl(UInt<3>(0h4), 3) node _T_451 = dshr(incoming_writes_Q.io.deq.bits.data, _T_450) connect Queue10_UInt8_20.io.enq.bits, _T_451 node _T_452 = eq(UInt<5>(0h15), idx_4) when _T_452 : node _T_453 = shl(UInt<3>(0h4), 3) node _T_454 = dshr(incoming_writes_Q.io.deq.bits.data, _T_453) connect Queue10_UInt8_21.io.enq.bits, _T_454 node _T_455 = eq(UInt<5>(0h16), idx_4) when _T_455 : node _T_456 = shl(UInt<3>(0h4), 3) node _T_457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_456) connect Queue10_UInt8_22.io.enq.bits, _T_457 node _T_458 = eq(UInt<5>(0h17), idx_4) when _T_458 : node _T_459 = shl(UInt<3>(0h4), 3) node _T_460 = dshr(incoming_writes_Q.io.deq.bits.data, _T_459) connect Queue10_UInt8_23.io.enq.bits, _T_460 node _T_461 = eq(UInt<5>(0h18), idx_4) when _T_461 : node _T_462 = shl(UInt<3>(0h4), 3) node _T_463 = dshr(incoming_writes_Q.io.deq.bits.data, _T_462) connect Queue10_UInt8_24.io.enq.bits, _T_463 node _T_464 = eq(UInt<5>(0h19), idx_4) when _T_464 : node _T_465 = shl(UInt<3>(0h4), 3) node _T_466 = dshr(incoming_writes_Q.io.deq.bits.data, _T_465) connect Queue10_UInt8_25.io.enq.bits, _T_466 node _T_467 = eq(UInt<5>(0h1a), idx_4) when _T_467 : node _T_468 = shl(UInt<3>(0h4), 3) node _T_469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_468) connect Queue10_UInt8_26.io.enq.bits, _T_469 node _T_470 = eq(UInt<5>(0h1b), idx_4) when _T_470 : node _T_471 = shl(UInt<3>(0h4), 3) node _T_472 = dshr(incoming_writes_Q.io.deq.bits.data, _T_471) connect Queue10_UInt8_27.io.enq.bits, _T_472 node _T_473 = eq(UInt<5>(0h1c), idx_4) when _T_473 : node _T_474 = shl(UInt<3>(0h4), 3) node _T_475 = dshr(incoming_writes_Q.io.deq.bits.data, _T_474) connect Queue10_UInt8_28.io.enq.bits, _T_475 node _T_476 = eq(UInt<5>(0h1d), idx_4) when _T_476 : node _T_477 = shl(UInt<3>(0h4), 3) node _T_478 = dshr(incoming_writes_Q.io.deq.bits.data, _T_477) connect Queue10_UInt8_29.io.enq.bits, _T_478 node _T_479 = eq(UInt<5>(0h1e), idx_4) when _T_479 : node _T_480 = shl(UInt<3>(0h4), 3) node _T_481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_480) connect Queue10_UInt8_30.io.enq.bits, _T_481 node _T_482 = eq(UInt<5>(0h1f), idx_4) when _T_482 : node _T_483 = shl(UInt<3>(0h4), 3) node _T_484 = dshr(incoming_writes_Q.io.deq.bits.data, _T_483) connect Queue10_UInt8_31.io.enq.bits, _T_484 node _idx_T_5 = add(write_start_index, UInt<3>(0h5)) node idx_5 = rem(_idx_T_5, UInt<6>(0h20)) node _T_485 = eq(UInt<1>(0h0), idx_5) when _T_485 : node _T_486 = shl(UInt<3>(0h5), 3) node _T_487 = dshr(incoming_writes_Q.io.deq.bits.data, _T_486) connect Queue10_UInt8.io.enq.bits, _T_487 node _T_488 = eq(UInt<1>(0h1), idx_5) when _T_488 : node _T_489 = shl(UInt<3>(0h5), 3) node _T_490 = dshr(incoming_writes_Q.io.deq.bits.data, _T_489) connect Queue10_UInt8_1.io.enq.bits, _T_490 node _T_491 = eq(UInt<2>(0h2), idx_5) when _T_491 : node _T_492 = shl(UInt<3>(0h5), 3) node _T_493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_492) connect Queue10_UInt8_2.io.enq.bits, _T_493 node _T_494 = eq(UInt<2>(0h3), idx_5) when _T_494 : node _T_495 = shl(UInt<3>(0h5), 3) node _T_496 = dshr(incoming_writes_Q.io.deq.bits.data, _T_495) connect Queue10_UInt8_3.io.enq.bits, _T_496 node _T_497 = eq(UInt<3>(0h4), idx_5) when _T_497 : node _T_498 = shl(UInt<3>(0h5), 3) node _T_499 = dshr(incoming_writes_Q.io.deq.bits.data, _T_498) connect Queue10_UInt8_4.io.enq.bits, _T_499 node _T_500 = eq(UInt<3>(0h5), idx_5) when _T_500 : node _T_501 = shl(UInt<3>(0h5), 3) node _T_502 = dshr(incoming_writes_Q.io.deq.bits.data, _T_501) connect Queue10_UInt8_5.io.enq.bits, _T_502 node _T_503 = eq(UInt<3>(0h6), idx_5) when _T_503 : node _T_504 = shl(UInt<3>(0h5), 3) node _T_505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_504) connect Queue10_UInt8_6.io.enq.bits, _T_505 node _T_506 = eq(UInt<3>(0h7), idx_5) when _T_506 : node _T_507 = shl(UInt<3>(0h5), 3) node _T_508 = dshr(incoming_writes_Q.io.deq.bits.data, _T_507) connect Queue10_UInt8_7.io.enq.bits, _T_508 node _T_509 = eq(UInt<4>(0h8), idx_5) when _T_509 : node _T_510 = shl(UInt<3>(0h5), 3) node _T_511 = dshr(incoming_writes_Q.io.deq.bits.data, _T_510) connect Queue10_UInt8_8.io.enq.bits, _T_511 node _T_512 = eq(UInt<4>(0h9), idx_5) when _T_512 : node _T_513 = shl(UInt<3>(0h5), 3) node _T_514 = dshr(incoming_writes_Q.io.deq.bits.data, _T_513) connect Queue10_UInt8_9.io.enq.bits, _T_514 node _T_515 = eq(UInt<4>(0ha), idx_5) when _T_515 : node _T_516 = shl(UInt<3>(0h5), 3) node _T_517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_516) connect Queue10_UInt8_10.io.enq.bits, _T_517 node _T_518 = eq(UInt<4>(0hb), idx_5) when _T_518 : node _T_519 = shl(UInt<3>(0h5), 3) node _T_520 = dshr(incoming_writes_Q.io.deq.bits.data, _T_519) connect Queue10_UInt8_11.io.enq.bits, _T_520 node _T_521 = eq(UInt<4>(0hc), idx_5) when _T_521 : node _T_522 = shl(UInt<3>(0h5), 3) node _T_523 = dshr(incoming_writes_Q.io.deq.bits.data, _T_522) connect Queue10_UInt8_12.io.enq.bits, _T_523 node _T_524 = eq(UInt<4>(0hd), idx_5) when _T_524 : node _T_525 = shl(UInt<3>(0h5), 3) node _T_526 = dshr(incoming_writes_Q.io.deq.bits.data, _T_525) connect Queue10_UInt8_13.io.enq.bits, _T_526 node _T_527 = eq(UInt<4>(0he), idx_5) when _T_527 : node _T_528 = shl(UInt<3>(0h5), 3) node _T_529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_528) connect Queue10_UInt8_14.io.enq.bits, _T_529 node _T_530 = eq(UInt<4>(0hf), idx_5) when _T_530 : node _T_531 = shl(UInt<3>(0h5), 3) node _T_532 = dshr(incoming_writes_Q.io.deq.bits.data, _T_531) connect Queue10_UInt8_15.io.enq.bits, _T_532 node _T_533 = eq(UInt<5>(0h10), idx_5) when _T_533 : node _T_534 = shl(UInt<3>(0h5), 3) node _T_535 = dshr(incoming_writes_Q.io.deq.bits.data, _T_534) connect Queue10_UInt8_16.io.enq.bits, _T_535 node _T_536 = eq(UInt<5>(0h11), idx_5) when _T_536 : node _T_537 = shl(UInt<3>(0h5), 3) node _T_538 = dshr(incoming_writes_Q.io.deq.bits.data, _T_537) connect Queue10_UInt8_17.io.enq.bits, _T_538 node _T_539 = eq(UInt<5>(0h12), idx_5) when _T_539 : node _T_540 = shl(UInt<3>(0h5), 3) node _T_541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_540) connect Queue10_UInt8_18.io.enq.bits, _T_541 node _T_542 = eq(UInt<5>(0h13), idx_5) when _T_542 : node _T_543 = shl(UInt<3>(0h5), 3) node _T_544 = dshr(incoming_writes_Q.io.deq.bits.data, _T_543) connect Queue10_UInt8_19.io.enq.bits, _T_544 node _T_545 = eq(UInt<5>(0h14), idx_5) when _T_545 : node _T_546 = shl(UInt<3>(0h5), 3) node _T_547 = dshr(incoming_writes_Q.io.deq.bits.data, _T_546) connect Queue10_UInt8_20.io.enq.bits, _T_547 node _T_548 = eq(UInt<5>(0h15), idx_5) when _T_548 : node _T_549 = shl(UInt<3>(0h5), 3) node _T_550 = dshr(incoming_writes_Q.io.deq.bits.data, _T_549) connect Queue10_UInt8_21.io.enq.bits, _T_550 node _T_551 = eq(UInt<5>(0h16), idx_5) when _T_551 : node _T_552 = shl(UInt<3>(0h5), 3) node _T_553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_552) connect Queue10_UInt8_22.io.enq.bits, _T_553 node _T_554 = eq(UInt<5>(0h17), idx_5) when _T_554 : node _T_555 = shl(UInt<3>(0h5), 3) node _T_556 = dshr(incoming_writes_Q.io.deq.bits.data, _T_555) connect Queue10_UInt8_23.io.enq.bits, _T_556 node _T_557 = eq(UInt<5>(0h18), idx_5) when _T_557 : node _T_558 = shl(UInt<3>(0h5), 3) node _T_559 = dshr(incoming_writes_Q.io.deq.bits.data, _T_558) connect Queue10_UInt8_24.io.enq.bits, _T_559 node _T_560 = eq(UInt<5>(0h19), idx_5) when _T_560 : node _T_561 = shl(UInt<3>(0h5), 3) node _T_562 = dshr(incoming_writes_Q.io.deq.bits.data, _T_561) connect Queue10_UInt8_25.io.enq.bits, _T_562 node _T_563 = eq(UInt<5>(0h1a), idx_5) when _T_563 : node _T_564 = shl(UInt<3>(0h5), 3) node _T_565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_564) connect Queue10_UInt8_26.io.enq.bits, _T_565 node _T_566 = eq(UInt<5>(0h1b), idx_5) when _T_566 : node _T_567 = shl(UInt<3>(0h5), 3) node _T_568 = dshr(incoming_writes_Q.io.deq.bits.data, _T_567) connect Queue10_UInt8_27.io.enq.bits, _T_568 node _T_569 = eq(UInt<5>(0h1c), idx_5) when _T_569 : node _T_570 = shl(UInt<3>(0h5), 3) node _T_571 = dshr(incoming_writes_Q.io.deq.bits.data, _T_570) connect Queue10_UInt8_28.io.enq.bits, _T_571 node _T_572 = eq(UInt<5>(0h1d), idx_5) when _T_572 : node _T_573 = shl(UInt<3>(0h5), 3) node _T_574 = dshr(incoming_writes_Q.io.deq.bits.data, _T_573) connect Queue10_UInt8_29.io.enq.bits, _T_574 node _T_575 = eq(UInt<5>(0h1e), idx_5) when _T_575 : node _T_576 = shl(UInt<3>(0h5), 3) node _T_577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_576) connect Queue10_UInt8_30.io.enq.bits, _T_577 node _T_578 = eq(UInt<5>(0h1f), idx_5) when _T_578 : node _T_579 = shl(UInt<3>(0h5), 3) node _T_580 = dshr(incoming_writes_Q.io.deq.bits.data, _T_579) connect Queue10_UInt8_31.io.enq.bits, _T_580 node _idx_T_6 = add(write_start_index, UInt<3>(0h6)) node idx_6 = rem(_idx_T_6, UInt<6>(0h20)) node _T_581 = eq(UInt<1>(0h0), idx_6) when _T_581 : node _T_582 = shl(UInt<3>(0h6), 3) node _T_583 = dshr(incoming_writes_Q.io.deq.bits.data, _T_582) connect Queue10_UInt8.io.enq.bits, _T_583 node _T_584 = eq(UInt<1>(0h1), idx_6) when _T_584 : node _T_585 = shl(UInt<3>(0h6), 3) node _T_586 = dshr(incoming_writes_Q.io.deq.bits.data, _T_585) connect Queue10_UInt8_1.io.enq.bits, _T_586 node _T_587 = eq(UInt<2>(0h2), idx_6) when _T_587 : node _T_588 = shl(UInt<3>(0h6), 3) node _T_589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_588) connect Queue10_UInt8_2.io.enq.bits, _T_589 node _T_590 = eq(UInt<2>(0h3), idx_6) when _T_590 : node _T_591 = shl(UInt<3>(0h6), 3) node _T_592 = dshr(incoming_writes_Q.io.deq.bits.data, _T_591) connect Queue10_UInt8_3.io.enq.bits, _T_592 node _T_593 = eq(UInt<3>(0h4), idx_6) when _T_593 : node _T_594 = shl(UInt<3>(0h6), 3) node _T_595 = dshr(incoming_writes_Q.io.deq.bits.data, _T_594) connect Queue10_UInt8_4.io.enq.bits, _T_595 node _T_596 = eq(UInt<3>(0h5), idx_6) when _T_596 : node _T_597 = shl(UInt<3>(0h6), 3) node _T_598 = dshr(incoming_writes_Q.io.deq.bits.data, _T_597) connect Queue10_UInt8_5.io.enq.bits, _T_598 node _T_599 = eq(UInt<3>(0h6), idx_6) when _T_599 : node _T_600 = shl(UInt<3>(0h6), 3) node _T_601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_600) connect Queue10_UInt8_6.io.enq.bits, _T_601 node _T_602 = eq(UInt<3>(0h7), idx_6) when _T_602 : node _T_603 = shl(UInt<3>(0h6), 3) node _T_604 = dshr(incoming_writes_Q.io.deq.bits.data, _T_603) connect Queue10_UInt8_7.io.enq.bits, _T_604 node _T_605 = eq(UInt<4>(0h8), idx_6) when _T_605 : node _T_606 = shl(UInt<3>(0h6), 3) node _T_607 = dshr(incoming_writes_Q.io.deq.bits.data, _T_606) connect Queue10_UInt8_8.io.enq.bits, _T_607 node _T_608 = eq(UInt<4>(0h9), idx_6) when _T_608 : node _T_609 = shl(UInt<3>(0h6), 3) node _T_610 = dshr(incoming_writes_Q.io.deq.bits.data, _T_609) connect Queue10_UInt8_9.io.enq.bits, _T_610 node _T_611 = eq(UInt<4>(0ha), idx_6) when _T_611 : node _T_612 = shl(UInt<3>(0h6), 3) node _T_613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_612) connect Queue10_UInt8_10.io.enq.bits, _T_613 node _T_614 = eq(UInt<4>(0hb), idx_6) when _T_614 : node _T_615 = shl(UInt<3>(0h6), 3) node _T_616 = dshr(incoming_writes_Q.io.deq.bits.data, _T_615) connect Queue10_UInt8_11.io.enq.bits, _T_616 node _T_617 = eq(UInt<4>(0hc), idx_6) when _T_617 : node _T_618 = shl(UInt<3>(0h6), 3) node _T_619 = dshr(incoming_writes_Q.io.deq.bits.data, _T_618) connect Queue10_UInt8_12.io.enq.bits, _T_619 node _T_620 = eq(UInt<4>(0hd), idx_6) when _T_620 : node _T_621 = shl(UInt<3>(0h6), 3) node _T_622 = dshr(incoming_writes_Q.io.deq.bits.data, _T_621) connect Queue10_UInt8_13.io.enq.bits, _T_622 node _T_623 = eq(UInt<4>(0he), idx_6) when _T_623 : node _T_624 = shl(UInt<3>(0h6), 3) node _T_625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_624) connect Queue10_UInt8_14.io.enq.bits, _T_625 node _T_626 = eq(UInt<4>(0hf), idx_6) when _T_626 : node _T_627 = shl(UInt<3>(0h6), 3) node _T_628 = dshr(incoming_writes_Q.io.deq.bits.data, _T_627) connect Queue10_UInt8_15.io.enq.bits, _T_628 node _T_629 = eq(UInt<5>(0h10), idx_6) when _T_629 : node _T_630 = shl(UInt<3>(0h6), 3) node _T_631 = dshr(incoming_writes_Q.io.deq.bits.data, _T_630) connect Queue10_UInt8_16.io.enq.bits, _T_631 node _T_632 = eq(UInt<5>(0h11), idx_6) when _T_632 : node _T_633 = shl(UInt<3>(0h6), 3) node _T_634 = dshr(incoming_writes_Q.io.deq.bits.data, _T_633) connect Queue10_UInt8_17.io.enq.bits, _T_634 node _T_635 = eq(UInt<5>(0h12), idx_6) when _T_635 : node _T_636 = shl(UInt<3>(0h6), 3) node _T_637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_636) connect Queue10_UInt8_18.io.enq.bits, _T_637 node _T_638 = eq(UInt<5>(0h13), idx_6) when _T_638 : node _T_639 = shl(UInt<3>(0h6), 3) node _T_640 = dshr(incoming_writes_Q.io.deq.bits.data, _T_639) connect Queue10_UInt8_19.io.enq.bits, _T_640 node _T_641 = eq(UInt<5>(0h14), idx_6) when _T_641 : node _T_642 = shl(UInt<3>(0h6), 3) node _T_643 = dshr(incoming_writes_Q.io.deq.bits.data, _T_642) connect Queue10_UInt8_20.io.enq.bits, _T_643 node _T_644 = eq(UInt<5>(0h15), idx_6) when _T_644 : node _T_645 = shl(UInt<3>(0h6), 3) node _T_646 = dshr(incoming_writes_Q.io.deq.bits.data, _T_645) connect Queue10_UInt8_21.io.enq.bits, _T_646 node _T_647 = eq(UInt<5>(0h16), idx_6) when _T_647 : node _T_648 = shl(UInt<3>(0h6), 3) node _T_649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_648) connect Queue10_UInt8_22.io.enq.bits, _T_649 node _T_650 = eq(UInt<5>(0h17), idx_6) when _T_650 : node _T_651 = shl(UInt<3>(0h6), 3) node _T_652 = dshr(incoming_writes_Q.io.deq.bits.data, _T_651) connect Queue10_UInt8_23.io.enq.bits, _T_652 node _T_653 = eq(UInt<5>(0h18), idx_6) when _T_653 : node _T_654 = shl(UInt<3>(0h6), 3) node _T_655 = dshr(incoming_writes_Q.io.deq.bits.data, _T_654) connect Queue10_UInt8_24.io.enq.bits, _T_655 node _T_656 = eq(UInt<5>(0h19), idx_6) when _T_656 : node _T_657 = shl(UInt<3>(0h6), 3) node _T_658 = dshr(incoming_writes_Q.io.deq.bits.data, _T_657) connect Queue10_UInt8_25.io.enq.bits, _T_658 node _T_659 = eq(UInt<5>(0h1a), idx_6) when _T_659 : node _T_660 = shl(UInt<3>(0h6), 3) node _T_661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_660) connect Queue10_UInt8_26.io.enq.bits, _T_661 node _T_662 = eq(UInt<5>(0h1b), idx_6) when _T_662 : node _T_663 = shl(UInt<3>(0h6), 3) node _T_664 = dshr(incoming_writes_Q.io.deq.bits.data, _T_663) connect Queue10_UInt8_27.io.enq.bits, _T_664 node _T_665 = eq(UInt<5>(0h1c), idx_6) when _T_665 : node _T_666 = shl(UInt<3>(0h6), 3) node _T_667 = dshr(incoming_writes_Q.io.deq.bits.data, _T_666) connect Queue10_UInt8_28.io.enq.bits, _T_667 node _T_668 = eq(UInt<5>(0h1d), idx_6) when _T_668 : node _T_669 = shl(UInt<3>(0h6), 3) node _T_670 = dshr(incoming_writes_Q.io.deq.bits.data, _T_669) connect Queue10_UInt8_29.io.enq.bits, _T_670 node _T_671 = eq(UInt<5>(0h1e), idx_6) when _T_671 : node _T_672 = shl(UInt<3>(0h6), 3) node _T_673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_672) connect Queue10_UInt8_30.io.enq.bits, _T_673 node _T_674 = eq(UInt<5>(0h1f), idx_6) when _T_674 : node _T_675 = shl(UInt<3>(0h6), 3) node _T_676 = dshr(incoming_writes_Q.io.deq.bits.data, _T_675) connect Queue10_UInt8_31.io.enq.bits, _T_676 node _idx_T_7 = add(write_start_index, UInt<3>(0h7)) node idx_7 = rem(_idx_T_7, UInt<6>(0h20)) node _T_677 = eq(UInt<1>(0h0), idx_7) when _T_677 : node _T_678 = shl(UInt<3>(0h7), 3) node _T_679 = dshr(incoming_writes_Q.io.deq.bits.data, _T_678) connect Queue10_UInt8.io.enq.bits, _T_679 node _T_680 = eq(UInt<1>(0h1), idx_7) when _T_680 : node _T_681 = shl(UInt<3>(0h7), 3) node _T_682 = dshr(incoming_writes_Q.io.deq.bits.data, _T_681) connect Queue10_UInt8_1.io.enq.bits, _T_682 node _T_683 = eq(UInt<2>(0h2), idx_7) when _T_683 : node _T_684 = shl(UInt<3>(0h7), 3) node _T_685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_684) connect Queue10_UInt8_2.io.enq.bits, _T_685 node _T_686 = eq(UInt<2>(0h3), idx_7) when _T_686 : node _T_687 = shl(UInt<3>(0h7), 3) node _T_688 = dshr(incoming_writes_Q.io.deq.bits.data, _T_687) connect Queue10_UInt8_3.io.enq.bits, _T_688 node _T_689 = eq(UInt<3>(0h4), idx_7) when _T_689 : node _T_690 = shl(UInt<3>(0h7), 3) node _T_691 = dshr(incoming_writes_Q.io.deq.bits.data, _T_690) connect Queue10_UInt8_4.io.enq.bits, _T_691 node _T_692 = eq(UInt<3>(0h5), idx_7) when _T_692 : node _T_693 = shl(UInt<3>(0h7), 3) node _T_694 = dshr(incoming_writes_Q.io.deq.bits.data, _T_693) connect Queue10_UInt8_5.io.enq.bits, _T_694 node _T_695 = eq(UInt<3>(0h6), idx_7) when _T_695 : node _T_696 = shl(UInt<3>(0h7), 3) node _T_697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_696) connect Queue10_UInt8_6.io.enq.bits, _T_697 node _T_698 = eq(UInt<3>(0h7), idx_7) when _T_698 : node _T_699 = shl(UInt<3>(0h7), 3) node _T_700 = dshr(incoming_writes_Q.io.deq.bits.data, _T_699) connect Queue10_UInt8_7.io.enq.bits, _T_700 node _T_701 = eq(UInt<4>(0h8), idx_7) when _T_701 : node _T_702 = shl(UInt<3>(0h7), 3) node _T_703 = dshr(incoming_writes_Q.io.deq.bits.data, _T_702) connect Queue10_UInt8_8.io.enq.bits, _T_703 node _T_704 = eq(UInt<4>(0h9), idx_7) when _T_704 : node _T_705 = shl(UInt<3>(0h7), 3) node _T_706 = dshr(incoming_writes_Q.io.deq.bits.data, _T_705) connect Queue10_UInt8_9.io.enq.bits, _T_706 node _T_707 = eq(UInt<4>(0ha), idx_7) when _T_707 : node _T_708 = shl(UInt<3>(0h7), 3) node _T_709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_708) connect Queue10_UInt8_10.io.enq.bits, _T_709 node _T_710 = eq(UInt<4>(0hb), idx_7) when _T_710 : node _T_711 = shl(UInt<3>(0h7), 3) node _T_712 = dshr(incoming_writes_Q.io.deq.bits.data, _T_711) connect Queue10_UInt8_11.io.enq.bits, _T_712 node _T_713 = eq(UInt<4>(0hc), idx_7) when _T_713 : node _T_714 = shl(UInt<3>(0h7), 3) node _T_715 = dshr(incoming_writes_Q.io.deq.bits.data, _T_714) connect Queue10_UInt8_12.io.enq.bits, _T_715 node _T_716 = eq(UInt<4>(0hd), idx_7) when _T_716 : node _T_717 = shl(UInt<3>(0h7), 3) node _T_718 = dshr(incoming_writes_Q.io.deq.bits.data, _T_717) connect Queue10_UInt8_13.io.enq.bits, _T_718 node _T_719 = eq(UInt<4>(0he), idx_7) when _T_719 : node _T_720 = shl(UInt<3>(0h7), 3) node _T_721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_720) connect Queue10_UInt8_14.io.enq.bits, _T_721 node _T_722 = eq(UInt<4>(0hf), idx_7) when _T_722 : node _T_723 = shl(UInt<3>(0h7), 3) node _T_724 = dshr(incoming_writes_Q.io.deq.bits.data, _T_723) connect Queue10_UInt8_15.io.enq.bits, _T_724 node _T_725 = eq(UInt<5>(0h10), idx_7) when _T_725 : node _T_726 = shl(UInt<3>(0h7), 3) node _T_727 = dshr(incoming_writes_Q.io.deq.bits.data, _T_726) connect Queue10_UInt8_16.io.enq.bits, _T_727 node _T_728 = eq(UInt<5>(0h11), idx_7) when _T_728 : node _T_729 = shl(UInt<3>(0h7), 3) node _T_730 = dshr(incoming_writes_Q.io.deq.bits.data, _T_729) connect Queue10_UInt8_17.io.enq.bits, _T_730 node _T_731 = eq(UInt<5>(0h12), idx_7) when _T_731 : node _T_732 = shl(UInt<3>(0h7), 3) node _T_733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_732) connect Queue10_UInt8_18.io.enq.bits, _T_733 node _T_734 = eq(UInt<5>(0h13), idx_7) when _T_734 : node _T_735 = shl(UInt<3>(0h7), 3) node _T_736 = dshr(incoming_writes_Q.io.deq.bits.data, _T_735) connect Queue10_UInt8_19.io.enq.bits, _T_736 node _T_737 = eq(UInt<5>(0h14), idx_7) when _T_737 : node _T_738 = shl(UInt<3>(0h7), 3) node _T_739 = dshr(incoming_writes_Q.io.deq.bits.data, _T_738) connect Queue10_UInt8_20.io.enq.bits, _T_739 node _T_740 = eq(UInt<5>(0h15), idx_7) when _T_740 : node _T_741 = shl(UInt<3>(0h7), 3) node _T_742 = dshr(incoming_writes_Q.io.deq.bits.data, _T_741) connect Queue10_UInt8_21.io.enq.bits, _T_742 node _T_743 = eq(UInt<5>(0h16), idx_7) when _T_743 : node _T_744 = shl(UInt<3>(0h7), 3) node _T_745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_744) connect Queue10_UInt8_22.io.enq.bits, _T_745 node _T_746 = eq(UInt<5>(0h17), idx_7) when _T_746 : node _T_747 = shl(UInt<3>(0h7), 3) node _T_748 = dshr(incoming_writes_Q.io.deq.bits.data, _T_747) connect Queue10_UInt8_23.io.enq.bits, _T_748 node _T_749 = eq(UInt<5>(0h18), idx_7) when _T_749 : node _T_750 = shl(UInt<3>(0h7), 3) node _T_751 = dshr(incoming_writes_Q.io.deq.bits.data, _T_750) connect Queue10_UInt8_24.io.enq.bits, _T_751 node _T_752 = eq(UInt<5>(0h19), idx_7) when _T_752 : node _T_753 = shl(UInt<3>(0h7), 3) node _T_754 = dshr(incoming_writes_Q.io.deq.bits.data, _T_753) connect Queue10_UInt8_25.io.enq.bits, _T_754 node _T_755 = eq(UInt<5>(0h1a), idx_7) when _T_755 : node _T_756 = shl(UInt<3>(0h7), 3) node _T_757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_756) connect Queue10_UInt8_26.io.enq.bits, _T_757 node _T_758 = eq(UInt<5>(0h1b), idx_7) when _T_758 : node _T_759 = shl(UInt<3>(0h7), 3) node _T_760 = dshr(incoming_writes_Q.io.deq.bits.data, _T_759) connect Queue10_UInt8_27.io.enq.bits, _T_760 node _T_761 = eq(UInt<5>(0h1c), idx_7) when _T_761 : node _T_762 = shl(UInt<3>(0h7), 3) node _T_763 = dshr(incoming_writes_Q.io.deq.bits.data, _T_762) connect Queue10_UInt8_28.io.enq.bits, _T_763 node _T_764 = eq(UInt<5>(0h1d), idx_7) when _T_764 : node _T_765 = shl(UInt<3>(0h7), 3) node _T_766 = dshr(incoming_writes_Q.io.deq.bits.data, _T_765) connect Queue10_UInt8_29.io.enq.bits, _T_766 node _T_767 = eq(UInt<5>(0h1e), idx_7) when _T_767 : node _T_768 = shl(UInt<3>(0h7), 3) node _T_769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_768) connect Queue10_UInt8_30.io.enq.bits, _T_769 node _T_770 = eq(UInt<5>(0h1f), idx_7) when _T_770 : node _T_771 = shl(UInt<3>(0h7), 3) node _T_772 = dshr(incoming_writes_Q.io.deq.bits.data, _T_771) connect Queue10_UInt8_31.io.enq.bits, _T_772 node _idx_T_8 = add(write_start_index, UInt<4>(0h8)) node idx_8 = rem(_idx_T_8, UInt<6>(0h20)) node _T_773 = eq(UInt<1>(0h0), idx_8) when _T_773 : node _T_774 = shl(UInt<4>(0h8), 3) node _T_775 = dshr(incoming_writes_Q.io.deq.bits.data, _T_774) connect Queue10_UInt8.io.enq.bits, _T_775 node _T_776 = eq(UInt<1>(0h1), idx_8) when _T_776 : node _T_777 = shl(UInt<4>(0h8), 3) node _T_778 = dshr(incoming_writes_Q.io.deq.bits.data, _T_777) connect Queue10_UInt8_1.io.enq.bits, _T_778 node _T_779 = eq(UInt<2>(0h2), idx_8) when _T_779 : node _T_780 = shl(UInt<4>(0h8), 3) node _T_781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_780) connect Queue10_UInt8_2.io.enq.bits, _T_781 node _T_782 = eq(UInt<2>(0h3), idx_8) when _T_782 : node _T_783 = shl(UInt<4>(0h8), 3) node _T_784 = dshr(incoming_writes_Q.io.deq.bits.data, _T_783) connect Queue10_UInt8_3.io.enq.bits, _T_784 node _T_785 = eq(UInt<3>(0h4), idx_8) when _T_785 : node _T_786 = shl(UInt<4>(0h8), 3) node _T_787 = dshr(incoming_writes_Q.io.deq.bits.data, _T_786) connect Queue10_UInt8_4.io.enq.bits, _T_787 node _T_788 = eq(UInt<3>(0h5), idx_8) when _T_788 : node _T_789 = shl(UInt<4>(0h8), 3) node _T_790 = dshr(incoming_writes_Q.io.deq.bits.data, _T_789) connect Queue10_UInt8_5.io.enq.bits, _T_790 node _T_791 = eq(UInt<3>(0h6), idx_8) when _T_791 : node _T_792 = shl(UInt<4>(0h8), 3) node _T_793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_792) connect Queue10_UInt8_6.io.enq.bits, _T_793 node _T_794 = eq(UInt<3>(0h7), idx_8) when _T_794 : node _T_795 = shl(UInt<4>(0h8), 3) node _T_796 = dshr(incoming_writes_Q.io.deq.bits.data, _T_795) connect Queue10_UInt8_7.io.enq.bits, _T_796 node _T_797 = eq(UInt<4>(0h8), idx_8) when _T_797 : node _T_798 = shl(UInt<4>(0h8), 3) node _T_799 = dshr(incoming_writes_Q.io.deq.bits.data, _T_798) connect Queue10_UInt8_8.io.enq.bits, _T_799 node _T_800 = eq(UInt<4>(0h9), idx_8) when _T_800 : node _T_801 = shl(UInt<4>(0h8), 3) node _T_802 = dshr(incoming_writes_Q.io.deq.bits.data, _T_801) connect Queue10_UInt8_9.io.enq.bits, _T_802 node _T_803 = eq(UInt<4>(0ha), idx_8) when _T_803 : node _T_804 = shl(UInt<4>(0h8), 3) node _T_805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_804) connect Queue10_UInt8_10.io.enq.bits, _T_805 node _T_806 = eq(UInt<4>(0hb), idx_8) when _T_806 : node _T_807 = shl(UInt<4>(0h8), 3) node _T_808 = dshr(incoming_writes_Q.io.deq.bits.data, _T_807) connect Queue10_UInt8_11.io.enq.bits, _T_808 node _T_809 = eq(UInt<4>(0hc), idx_8) when _T_809 : node _T_810 = shl(UInt<4>(0h8), 3) node _T_811 = dshr(incoming_writes_Q.io.deq.bits.data, _T_810) connect Queue10_UInt8_12.io.enq.bits, _T_811 node _T_812 = eq(UInt<4>(0hd), idx_8) when _T_812 : node _T_813 = shl(UInt<4>(0h8), 3) node _T_814 = dshr(incoming_writes_Q.io.deq.bits.data, _T_813) connect Queue10_UInt8_13.io.enq.bits, _T_814 node _T_815 = eq(UInt<4>(0he), idx_8) when _T_815 : node _T_816 = shl(UInt<4>(0h8), 3) node _T_817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_816) connect Queue10_UInt8_14.io.enq.bits, _T_817 node _T_818 = eq(UInt<4>(0hf), idx_8) when _T_818 : node _T_819 = shl(UInt<4>(0h8), 3) node _T_820 = dshr(incoming_writes_Q.io.deq.bits.data, _T_819) connect Queue10_UInt8_15.io.enq.bits, _T_820 node _T_821 = eq(UInt<5>(0h10), idx_8) when _T_821 : node _T_822 = shl(UInt<4>(0h8), 3) node _T_823 = dshr(incoming_writes_Q.io.deq.bits.data, _T_822) connect Queue10_UInt8_16.io.enq.bits, _T_823 node _T_824 = eq(UInt<5>(0h11), idx_8) when _T_824 : node _T_825 = shl(UInt<4>(0h8), 3) node _T_826 = dshr(incoming_writes_Q.io.deq.bits.data, _T_825) connect Queue10_UInt8_17.io.enq.bits, _T_826 node _T_827 = eq(UInt<5>(0h12), idx_8) when _T_827 : node _T_828 = shl(UInt<4>(0h8), 3) node _T_829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_828) connect Queue10_UInt8_18.io.enq.bits, _T_829 node _T_830 = eq(UInt<5>(0h13), idx_8) when _T_830 : node _T_831 = shl(UInt<4>(0h8), 3) node _T_832 = dshr(incoming_writes_Q.io.deq.bits.data, _T_831) connect Queue10_UInt8_19.io.enq.bits, _T_832 node _T_833 = eq(UInt<5>(0h14), idx_8) when _T_833 : node _T_834 = shl(UInt<4>(0h8), 3) node _T_835 = dshr(incoming_writes_Q.io.deq.bits.data, _T_834) connect Queue10_UInt8_20.io.enq.bits, _T_835 node _T_836 = eq(UInt<5>(0h15), idx_8) when _T_836 : node _T_837 = shl(UInt<4>(0h8), 3) node _T_838 = dshr(incoming_writes_Q.io.deq.bits.data, _T_837) connect Queue10_UInt8_21.io.enq.bits, _T_838 node _T_839 = eq(UInt<5>(0h16), idx_8) when _T_839 : node _T_840 = shl(UInt<4>(0h8), 3) node _T_841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_840) connect Queue10_UInt8_22.io.enq.bits, _T_841 node _T_842 = eq(UInt<5>(0h17), idx_8) when _T_842 : node _T_843 = shl(UInt<4>(0h8), 3) node _T_844 = dshr(incoming_writes_Q.io.deq.bits.data, _T_843) connect Queue10_UInt8_23.io.enq.bits, _T_844 node _T_845 = eq(UInt<5>(0h18), idx_8) when _T_845 : node _T_846 = shl(UInt<4>(0h8), 3) node _T_847 = dshr(incoming_writes_Q.io.deq.bits.data, _T_846) connect Queue10_UInt8_24.io.enq.bits, _T_847 node _T_848 = eq(UInt<5>(0h19), idx_8) when _T_848 : node _T_849 = shl(UInt<4>(0h8), 3) node _T_850 = dshr(incoming_writes_Q.io.deq.bits.data, _T_849) connect Queue10_UInt8_25.io.enq.bits, _T_850 node _T_851 = eq(UInt<5>(0h1a), idx_8) when _T_851 : node _T_852 = shl(UInt<4>(0h8), 3) node _T_853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_852) connect Queue10_UInt8_26.io.enq.bits, _T_853 node _T_854 = eq(UInt<5>(0h1b), idx_8) when _T_854 : node _T_855 = shl(UInt<4>(0h8), 3) node _T_856 = dshr(incoming_writes_Q.io.deq.bits.data, _T_855) connect Queue10_UInt8_27.io.enq.bits, _T_856 node _T_857 = eq(UInt<5>(0h1c), idx_8) when _T_857 : node _T_858 = shl(UInt<4>(0h8), 3) node _T_859 = dshr(incoming_writes_Q.io.deq.bits.data, _T_858) connect Queue10_UInt8_28.io.enq.bits, _T_859 node _T_860 = eq(UInt<5>(0h1d), idx_8) when _T_860 : node _T_861 = shl(UInt<4>(0h8), 3) node _T_862 = dshr(incoming_writes_Q.io.deq.bits.data, _T_861) connect Queue10_UInt8_29.io.enq.bits, _T_862 node _T_863 = eq(UInt<5>(0h1e), idx_8) when _T_863 : node _T_864 = shl(UInt<4>(0h8), 3) node _T_865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_864) connect Queue10_UInt8_30.io.enq.bits, _T_865 node _T_866 = eq(UInt<5>(0h1f), idx_8) when _T_866 : node _T_867 = shl(UInt<4>(0h8), 3) node _T_868 = dshr(incoming_writes_Q.io.deq.bits.data, _T_867) connect Queue10_UInt8_31.io.enq.bits, _T_868 node _idx_T_9 = add(write_start_index, UInt<4>(0h9)) node idx_9 = rem(_idx_T_9, UInt<6>(0h20)) node _T_869 = eq(UInt<1>(0h0), idx_9) when _T_869 : node _T_870 = shl(UInt<4>(0h9), 3) node _T_871 = dshr(incoming_writes_Q.io.deq.bits.data, _T_870) connect Queue10_UInt8.io.enq.bits, _T_871 node _T_872 = eq(UInt<1>(0h1), idx_9) when _T_872 : node _T_873 = shl(UInt<4>(0h9), 3) node _T_874 = dshr(incoming_writes_Q.io.deq.bits.data, _T_873) connect Queue10_UInt8_1.io.enq.bits, _T_874 node _T_875 = eq(UInt<2>(0h2), idx_9) when _T_875 : node _T_876 = shl(UInt<4>(0h9), 3) node _T_877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_876) connect Queue10_UInt8_2.io.enq.bits, _T_877 node _T_878 = eq(UInt<2>(0h3), idx_9) when _T_878 : node _T_879 = shl(UInt<4>(0h9), 3) node _T_880 = dshr(incoming_writes_Q.io.deq.bits.data, _T_879) connect Queue10_UInt8_3.io.enq.bits, _T_880 node _T_881 = eq(UInt<3>(0h4), idx_9) when _T_881 : node _T_882 = shl(UInt<4>(0h9), 3) node _T_883 = dshr(incoming_writes_Q.io.deq.bits.data, _T_882) connect Queue10_UInt8_4.io.enq.bits, _T_883 node _T_884 = eq(UInt<3>(0h5), idx_9) when _T_884 : node _T_885 = shl(UInt<4>(0h9), 3) node _T_886 = dshr(incoming_writes_Q.io.deq.bits.data, _T_885) connect Queue10_UInt8_5.io.enq.bits, _T_886 node _T_887 = eq(UInt<3>(0h6), idx_9) when _T_887 : node _T_888 = shl(UInt<4>(0h9), 3) node _T_889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_888) connect Queue10_UInt8_6.io.enq.bits, _T_889 node _T_890 = eq(UInt<3>(0h7), idx_9) when _T_890 : node _T_891 = shl(UInt<4>(0h9), 3) node _T_892 = dshr(incoming_writes_Q.io.deq.bits.data, _T_891) connect Queue10_UInt8_7.io.enq.bits, _T_892 node _T_893 = eq(UInt<4>(0h8), idx_9) when _T_893 : node _T_894 = shl(UInt<4>(0h9), 3) node _T_895 = dshr(incoming_writes_Q.io.deq.bits.data, _T_894) connect Queue10_UInt8_8.io.enq.bits, _T_895 node _T_896 = eq(UInt<4>(0h9), idx_9) when _T_896 : node _T_897 = shl(UInt<4>(0h9), 3) node _T_898 = dshr(incoming_writes_Q.io.deq.bits.data, _T_897) connect Queue10_UInt8_9.io.enq.bits, _T_898 node _T_899 = eq(UInt<4>(0ha), idx_9) when _T_899 : node _T_900 = shl(UInt<4>(0h9), 3) node _T_901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_900) connect Queue10_UInt8_10.io.enq.bits, _T_901 node _T_902 = eq(UInt<4>(0hb), idx_9) when _T_902 : node _T_903 = shl(UInt<4>(0h9), 3) node _T_904 = dshr(incoming_writes_Q.io.deq.bits.data, _T_903) connect Queue10_UInt8_11.io.enq.bits, _T_904 node _T_905 = eq(UInt<4>(0hc), idx_9) when _T_905 : node _T_906 = shl(UInt<4>(0h9), 3) node _T_907 = dshr(incoming_writes_Q.io.deq.bits.data, _T_906) connect Queue10_UInt8_12.io.enq.bits, _T_907 node _T_908 = eq(UInt<4>(0hd), idx_9) when _T_908 : node _T_909 = shl(UInt<4>(0h9), 3) node _T_910 = dshr(incoming_writes_Q.io.deq.bits.data, _T_909) connect Queue10_UInt8_13.io.enq.bits, _T_910 node _T_911 = eq(UInt<4>(0he), idx_9) when _T_911 : node _T_912 = shl(UInt<4>(0h9), 3) node _T_913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_912) connect Queue10_UInt8_14.io.enq.bits, _T_913 node _T_914 = eq(UInt<4>(0hf), idx_9) when _T_914 : node _T_915 = shl(UInt<4>(0h9), 3) node _T_916 = dshr(incoming_writes_Q.io.deq.bits.data, _T_915) connect Queue10_UInt8_15.io.enq.bits, _T_916 node _T_917 = eq(UInt<5>(0h10), idx_9) when _T_917 : node _T_918 = shl(UInt<4>(0h9), 3) node _T_919 = dshr(incoming_writes_Q.io.deq.bits.data, _T_918) connect Queue10_UInt8_16.io.enq.bits, _T_919 node _T_920 = eq(UInt<5>(0h11), idx_9) when _T_920 : node _T_921 = shl(UInt<4>(0h9), 3) node _T_922 = dshr(incoming_writes_Q.io.deq.bits.data, _T_921) connect Queue10_UInt8_17.io.enq.bits, _T_922 node _T_923 = eq(UInt<5>(0h12), idx_9) when _T_923 : node _T_924 = shl(UInt<4>(0h9), 3) node _T_925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_924) connect Queue10_UInt8_18.io.enq.bits, _T_925 node _T_926 = eq(UInt<5>(0h13), idx_9) when _T_926 : node _T_927 = shl(UInt<4>(0h9), 3) node _T_928 = dshr(incoming_writes_Q.io.deq.bits.data, _T_927) connect Queue10_UInt8_19.io.enq.bits, _T_928 node _T_929 = eq(UInt<5>(0h14), idx_9) when _T_929 : node _T_930 = shl(UInt<4>(0h9), 3) node _T_931 = dshr(incoming_writes_Q.io.deq.bits.data, _T_930) connect Queue10_UInt8_20.io.enq.bits, _T_931 node _T_932 = eq(UInt<5>(0h15), idx_9) when _T_932 : node _T_933 = shl(UInt<4>(0h9), 3) node _T_934 = dshr(incoming_writes_Q.io.deq.bits.data, _T_933) connect Queue10_UInt8_21.io.enq.bits, _T_934 node _T_935 = eq(UInt<5>(0h16), idx_9) when _T_935 : node _T_936 = shl(UInt<4>(0h9), 3) node _T_937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_936) connect Queue10_UInt8_22.io.enq.bits, _T_937 node _T_938 = eq(UInt<5>(0h17), idx_9) when _T_938 : node _T_939 = shl(UInt<4>(0h9), 3) node _T_940 = dshr(incoming_writes_Q.io.deq.bits.data, _T_939) connect Queue10_UInt8_23.io.enq.bits, _T_940 node _T_941 = eq(UInt<5>(0h18), idx_9) when _T_941 : node _T_942 = shl(UInt<4>(0h9), 3) node _T_943 = dshr(incoming_writes_Q.io.deq.bits.data, _T_942) connect Queue10_UInt8_24.io.enq.bits, _T_943 node _T_944 = eq(UInt<5>(0h19), idx_9) when _T_944 : node _T_945 = shl(UInt<4>(0h9), 3) node _T_946 = dshr(incoming_writes_Q.io.deq.bits.data, _T_945) connect Queue10_UInt8_25.io.enq.bits, _T_946 node _T_947 = eq(UInt<5>(0h1a), idx_9) when _T_947 : node _T_948 = shl(UInt<4>(0h9), 3) node _T_949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_948) connect Queue10_UInt8_26.io.enq.bits, _T_949 node _T_950 = eq(UInt<5>(0h1b), idx_9) when _T_950 : node _T_951 = shl(UInt<4>(0h9), 3) node _T_952 = dshr(incoming_writes_Q.io.deq.bits.data, _T_951) connect Queue10_UInt8_27.io.enq.bits, _T_952 node _T_953 = eq(UInt<5>(0h1c), idx_9) when _T_953 : node _T_954 = shl(UInt<4>(0h9), 3) node _T_955 = dshr(incoming_writes_Q.io.deq.bits.data, _T_954) connect Queue10_UInt8_28.io.enq.bits, _T_955 node _T_956 = eq(UInt<5>(0h1d), idx_9) when _T_956 : node _T_957 = shl(UInt<4>(0h9), 3) node _T_958 = dshr(incoming_writes_Q.io.deq.bits.data, _T_957) connect Queue10_UInt8_29.io.enq.bits, _T_958 node _T_959 = eq(UInt<5>(0h1e), idx_9) when _T_959 : node _T_960 = shl(UInt<4>(0h9), 3) node _T_961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_960) connect Queue10_UInt8_30.io.enq.bits, _T_961 node _T_962 = eq(UInt<5>(0h1f), idx_9) when _T_962 : node _T_963 = shl(UInt<4>(0h9), 3) node _T_964 = dshr(incoming_writes_Q.io.deq.bits.data, _T_963) connect Queue10_UInt8_31.io.enq.bits, _T_964 node _idx_T_10 = add(write_start_index, UInt<4>(0ha)) node idx_10 = rem(_idx_T_10, UInt<6>(0h20)) node _T_965 = eq(UInt<1>(0h0), idx_10) when _T_965 : node _T_966 = shl(UInt<4>(0ha), 3) node _T_967 = dshr(incoming_writes_Q.io.deq.bits.data, _T_966) connect Queue10_UInt8.io.enq.bits, _T_967 node _T_968 = eq(UInt<1>(0h1), idx_10) when _T_968 : node _T_969 = shl(UInt<4>(0ha), 3) node _T_970 = dshr(incoming_writes_Q.io.deq.bits.data, _T_969) connect Queue10_UInt8_1.io.enq.bits, _T_970 node _T_971 = eq(UInt<2>(0h2), idx_10) when _T_971 : node _T_972 = shl(UInt<4>(0ha), 3) node _T_973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_972) connect Queue10_UInt8_2.io.enq.bits, _T_973 node _T_974 = eq(UInt<2>(0h3), idx_10) when _T_974 : node _T_975 = shl(UInt<4>(0ha), 3) node _T_976 = dshr(incoming_writes_Q.io.deq.bits.data, _T_975) connect Queue10_UInt8_3.io.enq.bits, _T_976 node _T_977 = eq(UInt<3>(0h4), idx_10) when _T_977 : node _T_978 = shl(UInt<4>(0ha), 3) node _T_979 = dshr(incoming_writes_Q.io.deq.bits.data, _T_978) connect Queue10_UInt8_4.io.enq.bits, _T_979 node _T_980 = eq(UInt<3>(0h5), idx_10) when _T_980 : node _T_981 = shl(UInt<4>(0ha), 3) node _T_982 = dshr(incoming_writes_Q.io.deq.bits.data, _T_981) connect Queue10_UInt8_5.io.enq.bits, _T_982 node _T_983 = eq(UInt<3>(0h6), idx_10) when _T_983 : node _T_984 = shl(UInt<4>(0ha), 3) node _T_985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_984) connect Queue10_UInt8_6.io.enq.bits, _T_985 node _T_986 = eq(UInt<3>(0h7), idx_10) when _T_986 : node _T_987 = shl(UInt<4>(0ha), 3) node _T_988 = dshr(incoming_writes_Q.io.deq.bits.data, _T_987) connect Queue10_UInt8_7.io.enq.bits, _T_988 node _T_989 = eq(UInt<4>(0h8), idx_10) when _T_989 : node _T_990 = shl(UInt<4>(0ha), 3) node _T_991 = dshr(incoming_writes_Q.io.deq.bits.data, _T_990) connect Queue10_UInt8_8.io.enq.bits, _T_991 node _T_992 = eq(UInt<4>(0h9), idx_10) when _T_992 : node _T_993 = shl(UInt<4>(0ha), 3) node _T_994 = dshr(incoming_writes_Q.io.deq.bits.data, _T_993) connect Queue10_UInt8_9.io.enq.bits, _T_994 node _T_995 = eq(UInt<4>(0ha), idx_10) when _T_995 : node _T_996 = shl(UInt<4>(0ha), 3) node _T_997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_996) connect Queue10_UInt8_10.io.enq.bits, _T_997 node _T_998 = eq(UInt<4>(0hb), idx_10) when _T_998 : node _T_999 = shl(UInt<4>(0ha), 3) node _T_1000 = dshr(incoming_writes_Q.io.deq.bits.data, _T_999) connect Queue10_UInt8_11.io.enq.bits, _T_1000 node _T_1001 = eq(UInt<4>(0hc), idx_10) when _T_1001 : node _T_1002 = shl(UInt<4>(0ha), 3) node _T_1003 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1002) connect Queue10_UInt8_12.io.enq.bits, _T_1003 node _T_1004 = eq(UInt<4>(0hd), idx_10) when _T_1004 : node _T_1005 = shl(UInt<4>(0ha), 3) node _T_1006 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1005) connect Queue10_UInt8_13.io.enq.bits, _T_1006 node _T_1007 = eq(UInt<4>(0he), idx_10) when _T_1007 : node _T_1008 = shl(UInt<4>(0ha), 3) node _T_1009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1008) connect Queue10_UInt8_14.io.enq.bits, _T_1009 node _T_1010 = eq(UInt<4>(0hf), idx_10) when _T_1010 : node _T_1011 = shl(UInt<4>(0ha), 3) node _T_1012 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1011) connect Queue10_UInt8_15.io.enq.bits, _T_1012 node _T_1013 = eq(UInt<5>(0h10), idx_10) when _T_1013 : node _T_1014 = shl(UInt<4>(0ha), 3) node _T_1015 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1014) connect Queue10_UInt8_16.io.enq.bits, _T_1015 node _T_1016 = eq(UInt<5>(0h11), idx_10) when _T_1016 : node _T_1017 = shl(UInt<4>(0ha), 3) node _T_1018 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1017) connect Queue10_UInt8_17.io.enq.bits, _T_1018 node _T_1019 = eq(UInt<5>(0h12), idx_10) when _T_1019 : node _T_1020 = shl(UInt<4>(0ha), 3) node _T_1021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1020) connect Queue10_UInt8_18.io.enq.bits, _T_1021 node _T_1022 = eq(UInt<5>(0h13), idx_10) when _T_1022 : node _T_1023 = shl(UInt<4>(0ha), 3) node _T_1024 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1023) connect Queue10_UInt8_19.io.enq.bits, _T_1024 node _T_1025 = eq(UInt<5>(0h14), idx_10) when _T_1025 : node _T_1026 = shl(UInt<4>(0ha), 3) node _T_1027 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1026) connect Queue10_UInt8_20.io.enq.bits, _T_1027 node _T_1028 = eq(UInt<5>(0h15), idx_10) when _T_1028 : node _T_1029 = shl(UInt<4>(0ha), 3) node _T_1030 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1029) connect Queue10_UInt8_21.io.enq.bits, _T_1030 node _T_1031 = eq(UInt<5>(0h16), idx_10) when _T_1031 : node _T_1032 = shl(UInt<4>(0ha), 3) node _T_1033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1032) connect Queue10_UInt8_22.io.enq.bits, _T_1033 node _T_1034 = eq(UInt<5>(0h17), idx_10) when _T_1034 : node _T_1035 = shl(UInt<4>(0ha), 3) node _T_1036 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1035) connect Queue10_UInt8_23.io.enq.bits, _T_1036 node _T_1037 = eq(UInt<5>(0h18), idx_10) when _T_1037 : node _T_1038 = shl(UInt<4>(0ha), 3) node _T_1039 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1038) connect Queue10_UInt8_24.io.enq.bits, _T_1039 node _T_1040 = eq(UInt<5>(0h19), idx_10) when _T_1040 : node _T_1041 = shl(UInt<4>(0ha), 3) node _T_1042 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1041) connect Queue10_UInt8_25.io.enq.bits, _T_1042 node _T_1043 = eq(UInt<5>(0h1a), idx_10) when _T_1043 : node _T_1044 = shl(UInt<4>(0ha), 3) node _T_1045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1044) connect Queue10_UInt8_26.io.enq.bits, _T_1045 node _T_1046 = eq(UInt<5>(0h1b), idx_10) when _T_1046 : node _T_1047 = shl(UInt<4>(0ha), 3) node _T_1048 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1047) connect Queue10_UInt8_27.io.enq.bits, _T_1048 node _T_1049 = eq(UInt<5>(0h1c), idx_10) when _T_1049 : node _T_1050 = shl(UInt<4>(0ha), 3) node _T_1051 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1050) connect Queue10_UInt8_28.io.enq.bits, _T_1051 node _T_1052 = eq(UInt<5>(0h1d), idx_10) when _T_1052 : node _T_1053 = shl(UInt<4>(0ha), 3) node _T_1054 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1053) connect Queue10_UInt8_29.io.enq.bits, _T_1054 node _T_1055 = eq(UInt<5>(0h1e), idx_10) when _T_1055 : node _T_1056 = shl(UInt<4>(0ha), 3) node _T_1057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1056) connect Queue10_UInt8_30.io.enq.bits, _T_1057 node _T_1058 = eq(UInt<5>(0h1f), idx_10) when _T_1058 : node _T_1059 = shl(UInt<4>(0ha), 3) node _T_1060 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1059) connect Queue10_UInt8_31.io.enq.bits, _T_1060 node _idx_T_11 = add(write_start_index, UInt<4>(0hb)) node idx_11 = rem(_idx_T_11, UInt<6>(0h20)) node _T_1061 = eq(UInt<1>(0h0), idx_11) when _T_1061 : node _T_1062 = shl(UInt<4>(0hb), 3) node _T_1063 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1062) connect Queue10_UInt8.io.enq.bits, _T_1063 node _T_1064 = eq(UInt<1>(0h1), idx_11) when _T_1064 : node _T_1065 = shl(UInt<4>(0hb), 3) node _T_1066 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1065) connect Queue10_UInt8_1.io.enq.bits, _T_1066 node _T_1067 = eq(UInt<2>(0h2), idx_11) when _T_1067 : node _T_1068 = shl(UInt<4>(0hb), 3) node _T_1069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1068) connect Queue10_UInt8_2.io.enq.bits, _T_1069 node _T_1070 = eq(UInt<2>(0h3), idx_11) when _T_1070 : node _T_1071 = shl(UInt<4>(0hb), 3) node _T_1072 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1071) connect Queue10_UInt8_3.io.enq.bits, _T_1072 node _T_1073 = eq(UInt<3>(0h4), idx_11) when _T_1073 : node _T_1074 = shl(UInt<4>(0hb), 3) node _T_1075 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1074) connect Queue10_UInt8_4.io.enq.bits, _T_1075 node _T_1076 = eq(UInt<3>(0h5), idx_11) when _T_1076 : node _T_1077 = shl(UInt<4>(0hb), 3) node _T_1078 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1077) connect Queue10_UInt8_5.io.enq.bits, _T_1078 node _T_1079 = eq(UInt<3>(0h6), idx_11) when _T_1079 : node _T_1080 = shl(UInt<4>(0hb), 3) node _T_1081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1080) connect Queue10_UInt8_6.io.enq.bits, _T_1081 node _T_1082 = eq(UInt<3>(0h7), idx_11) when _T_1082 : node _T_1083 = shl(UInt<4>(0hb), 3) node _T_1084 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1083) connect Queue10_UInt8_7.io.enq.bits, _T_1084 node _T_1085 = eq(UInt<4>(0h8), idx_11) when _T_1085 : node _T_1086 = shl(UInt<4>(0hb), 3) node _T_1087 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1086) connect Queue10_UInt8_8.io.enq.bits, _T_1087 node _T_1088 = eq(UInt<4>(0h9), idx_11) when _T_1088 : node _T_1089 = shl(UInt<4>(0hb), 3) node _T_1090 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1089) connect Queue10_UInt8_9.io.enq.bits, _T_1090 node _T_1091 = eq(UInt<4>(0ha), idx_11) when _T_1091 : node _T_1092 = shl(UInt<4>(0hb), 3) node _T_1093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1092) connect Queue10_UInt8_10.io.enq.bits, _T_1093 node _T_1094 = eq(UInt<4>(0hb), idx_11) when _T_1094 : node _T_1095 = shl(UInt<4>(0hb), 3) node _T_1096 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1095) connect Queue10_UInt8_11.io.enq.bits, _T_1096 node _T_1097 = eq(UInt<4>(0hc), idx_11) when _T_1097 : node _T_1098 = shl(UInt<4>(0hb), 3) node _T_1099 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1098) connect Queue10_UInt8_12.io.enq.bits, _T_1099 node _T_1100 = eq(UInt<4>(0hd), idx_11) when _T_1100 : node _T_1101 = shl(UInt<4>(0hb), 3) node _T_1102 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1101) connect Queue10_UInt8_13.io.enq.bits, _T_1102 node _T_1103 = eq(UInt<4>(0he), idx_11) when _T_1103 : node _T_1104 = shl(UInt<4>(0hb), 3) node _T_1105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1104) connect Queue10_UInt8_14.io.enq.bits, _T_1105 node _T_1106 = eq(UInt<4>(0hf), idx_11) when _T_1106 : node _T_1107 = shl(UInt<4>(0hb), 3) node _T_1108 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1107) connect Queue10_UInt8_15.io.enq.bits, _T_1108 node _T_1109 = eq(UInt<5>(0h10), idx_11) when _T_1109 : node _T_1110 = shl(UInt<4>(0hb), 3) node _T_1111 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1110) connect Queue10_UInt8_16.io.enq.bits, _T_1111 node _T_1112 = eq(UInt<5>(0h11), idx_11) when _T_1112 : node _T_1113 = shl(UInt<4>(0hb), 3) node _T_1114 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1113) connect Queue10_UInt8_17.io.enq.bits, _T_1114 node _T_1115 = eq(UInt<5>(0h12), idx_11) when _T_1115 : node _T_1116 = shl(UInt<4>(0hb), 3) node _T_1117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1116) connect Queue10_UInt8_18.io.enq.bits, _T_1117 node _T_1118 = eq(UInt<5>(0h13), idx_11) when _T_1118 : node _T_1119 = shl(UInt<4>(0hb), 3) node _T_1120 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1119) connect Queue10_UInt8_19.io.enq.bits, _T_1120 node _T_1121 = eq(UInt<5>(0h14), idx_11) when _T_1121 : node _T_1122 = shl(UInt<4>(0hb), 3) node _T_1123 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1122) connect Queue10_UInt8_20.io.enq.bits, _T_1123 node _T_1124 = eq(UInt<5>(0h15), idx_11) when _T_1124 : node _T_1125 = shl(UInt<4>(0hb), 3) node _T_1126 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1125) connect Queue10_UInt8_21.io.enq.bits, _T_1126 node _T_1127 = eq(UInt<5>(0h16), idx_11) when _T_1127 : node _T_1128 = shl(UInt<4>(0hb), 3) node _T_1129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1128) connect Queue10_UInt8_22.io.enq.bits, _T_1129 node _T_1130 = eq(UInt<5>(0h17), idx_11) when _T_1130 : node _T_1131 = shl(UInt<4>(0hb), 3) node _T_1132 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1131) connect Queue10_UInt8_23.io.enq.bits, _T_1132 node _T_1133 = eq(UInt<5>(0h18), idx_11) when _T_1133 : node _T_1134 = shl(UInt<4>(0hb), 3) node _T_1135 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1134) connect Queue10_UInt8_24.io.enq.bits, _T_1135 node _T_1136 = eq(UInt<5>(0h19), idx_11) when _T_1136 : node _T_1137 = shl(UInt<4>(0hb), 3) node _T_1138 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1137) connect Queue10_UInt8_25.io.enq.bits, _T_1138 node _T_1139 = eq(UInt<5>(0h1a), idx_11) when _T_1139 : node _T_1140 = shl(UInt<4>(0hb), 3) node _T_1141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1140) connect Queue10_UInt8_26.io.enq.bits, _T_1141 node _T_1142 = eq(UInt<5>(0h1b), idx_11) when _T_1142 : node _T_1143 = shl(UInt<4>(0hb), 3) node _T_1144 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1143) connect Queue10_UInt8_27.io.enq.bits, _T_1144 node _T_1145 = eq(UInt<5>(0h1c), idx_11) when _T_1145 : node _T_1146 = shl(UInt<4>(0hb), 3) node _T_1147 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1146) connect Queue10_UInt8_28.io.enq.bits, _T_1147 node _T_1148 = eq(UInt<5>(0h1d), idx_11) when _T_1148 : node _T_1149 = shl(UInt<4>(0hb), 3) node _T_1150 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1149) connect Queue10_UInt8_29.io.enq.bits, _T_1150 node _T_1151 = eq(UInt<5>(0h1e), idx_11) when _T_1151 : node _T_1152 = shl(UInt<4>(0hb), 3) node _T_1153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1152) connect Queue10_UInt8_30.io.enq.bits, _T_1153 node _T_1154 = eq(UInt<5>(0h1f), idx_11) when _T_1154 : node _T_1155 = shl(UInt<4>(0hb), 3) node _T_1156 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1155) connect Queue10_UInt8_31.io.enq.bits, _T_1156 node _idx_T_12 = add(write_start_index, UInt<4>(0hc)) node idx_12 = rem(_idx_T_12, UInt<6>(0h20)) node _T_1157 = eq(UInt<1>(0h0), idx_12) when _T_1157 : node _T_1158 = shl(UInt<4>(0hc), 3) node _T_1159 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1158) connect Queue10_UInt8.io.enq.bits, _T_1159 node _T_1160 = eq(UInt<1>(0h1), idx_12) when _T_1160 : node _T_1161 = shl(UInt<4>(0hc), 3) node _T_1162 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1161) connect Queue10_UInt8_1.io.enq.bits, _T_1162 node _T_1163 = eq(UInt<2>(0h2), idx_12) when _T_1163 : node _T_1164 = shl(UInt<4>(0hc), 3) node _T_1165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1164) connect Queue10_UInt8_2.io.enq.bits, _T_1165 node _T_1166 = eq(UInt<2>(0h3), idx_12) when _T_1166 : node _T_1167 = shl(UInt<4>(0hc), 3) node _T_1168 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1167) connect Queue10_UInt8_3.io.enq.bits, _T_1168 node _T_1169 = eq(UInt<3>(0h4), idx_12) when _T_1169 : node _T_1170 = shl(UInt<4>(0hc), 3) node _T_1171 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1170) connect Queue10_UInt8_4.io.enq.bits, _T_1171 node _T_1172 = eq(UInt<3>(0h5), idx_12) when _T_1172 : node _T_1173 = shl(UInt<4>(0hc), 3) node _T_1174 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1173) connect Queue10_UInt8_5.io.enq.bits, _T_1174 node _T_1175 = eq(UInt<3>(0h6), idx_12) when _T_1175 : node _T_1176 = shl(UInt<4>(0hc), 3) node _T_1177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1176) connect Queue10_UInt8_6.io.enq.bits, _T_1177 node _T_1178 = eq(UInt<3>(0h7), idx_12) when _T_1178 : node _T_1179 = shl(UInt<4>(0hc), 3) node _T_1180 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1179) connect Queue10_UInt8_7.io.enq.bits, _T_1180 node _T_1181 = eq(UInt<4>(0h8), idx_12) when _T_1181 : node _T_1182 = shl(UInt<4>(0hc), 3) node _T_1183 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1182) connect Queue10_UInt8_8.io.enq.bits, _T_1183 node _T_1184 = eq(UInt<4>(0h9), idx_12) when _T_1184 : node _T_1185 = shl(UInt<4>(0hc), 3) node _T_1186 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1185) connect Queue10_UInt8_9.io.enq.bits, _T_1186 node _T_1187 = eq(UInt<4>(0ha), idx_12) when _T_1187 : node _T_1188 = shl(UInt<4>(0hc), 3) node _T_1189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1188) connect Queue10_UInt8_10.io.enq.bits, _T_1189 node _T_1190 = eq(UInt<4>(0hb), idx_12) when _T_1190 : node _T_1191 = shl(UInt<4>(0hc), 3) node _T_1192 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1191) connect Queue10_UInt8_11.io.enq.bits, _T_1192 node _T_1193 = eq(UInt<4>(0hc), idx_12) when _T_1193 : node _T_1194 = shl(UInt<4>(0hc), 3) node _T_1195 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1194) connect Queue10_UInt8_12.io.enq.bits, _T_1195 node _T_1196 = eq(UInt<4>(0hd), idx_12) when _T_1196 : node _T_1197 = shl(UInt<4>(0hc), 3) node _T_1198 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1197) connect Queue10_UInt8_13.io.enq.bits, _T_1198 node _T_1199 = eq(UInt<4>(0he), idx_12) when _T_1199 : node _T_1200 = shl(UInt<4>(0hc), 3) node _T_1201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1200) connect Queue10_UInt8_14.io.enq.bits, _T_1201 node _T_1202 = eq(UInt<4>(0hf), idx_12) when _T_1202 : node _T_1203 = shl(UInt<4>(0hc), 3) node _T_1204 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1203) connect Queue10_UInt8_15.io.enq.bits, _T_1204 node _T_1205 = eq(UInt<5>(0h10), idx_12) when _T_1205 : node _T_1206 = shl(UInt<4>(0hc), 3) node _T_1207 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1206) connect Queue10_UInt8_16.io.enq.bits, _T_1207 node _T_1208 = eq(UInt<5>(0h11), idx_12) when _T_1208 : node _T_1209 = shl(UInt<4>(0hc), 3) node _T_1210 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1209) connect Queue10_UInt8_17.io.enq.bits, _T_1210 node _T_1211 = eq(UInt<5>(0h12), idx_12) when _T_1211 : node _T_1212 = shl(UInt<4>(0hc), 3) node _T_1213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1212) connect Queue10_UInt8_18.io.enq.bits, _T_1213 node _T_1214 = eq(UInt<5>(0h13), idx_12) when _T_1214 : node _T_1215 = shl(UInt<4>(0hc), 3) node _T_1216 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1215) connect Queue10_UInt8_19.io.enq.bits, _T_1216 node _T_1217 = eq(UInt<5>(0h14), idx_12) when _T_1217 : node _T_1218 = shl(UInt<4>(0hc), 3) node _T_1219 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1218) connect Queue10_UInt8_20.io.enq.bits, _T_1219 node _T_1220 = eq(UInt<5>(0h15), idx_12) when _T_1220 : node _T_1221 = shl(UInt<4>(0hc), 3) node _T_1222 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1221) connect Queue10_UInt8_21.io.enq.bits, _T_1222 node _T_1223 = eq(UInt<5>(0h16), idx_12) when _T_1223 : node _T_1224 = shl(UInt<4>(0hc), 3) node _T_1225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1224) connect Queue10_UInt8_22.io.enq.bits, _T_1225 node _T_1226 = eq(UInt<5>(0h17), idx_12) when _T_1226 : node _T_1227 = shl(UInt<4>(0hc), 3) node _T_1228 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1227) connect Queue10_UInt8_23.io.enq.bits, _T_1228 node _T_1229 = eq(UInt<5>(0h18), idx_12) when _T_1229 : node _T_1230 = shl(UInt<4>(0hc), 3) node _T_1231 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1230) connect Queue10_UInt8_24.io.enq.bits, _T_1231 node _T_1232 = eq(UInt<5>(0h19), idx_12) when _T_1232 : node _T_1233 = shl(UInt<4>(0hc), 3) node _T_1234 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1233) connect Queue10_UInt8_25.io.enq.bits, _T_1234 node _T_1235 = eq(UInt<5>(0h1a), idx_12) when _T_1235 : node _T_1236 = shl(UInt<4>(0hc), 3) node _T_1237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1236) connect Queue10_UInt8_26.io.enq.bits, _T_1237 node _T_1238 = eq(UInt<5>(0h1b), idx_12) when _T_1238 : node _T_1239 = shl(UInt<4>(0hc), 3) node _T_1240 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1239) connect Queue10_UInt8_27.io.enq.bits, _T_1240 node _T_1241 = eq(UInt<5>(0h1c), idx_12) when _T_1241 : node _T_1242 = shl(UInt<4>(0hc), 3) node _T_1243 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1242) connect Queue10_UInt8_28.io.enq.bits, _T_1243 node _T_1244 = eq(UInt<5>(0h1d), idx_12) when _T_1244 : node _T_1245 = shl(UInt<4>(0hc), 3) node _T_1246 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1245) connect Queue10_UInt8_29.io.enq.bits, _T_1246 node _T_1247 = eq(UInt<5>(0h1e), idx_12) when _T_1247 : node _T_1248 = shl(UInt<4>(0hc), 3) node _T_1249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1248) connect Queue10_UInt8_30.io.enq.bits, _T_1249 node _T_1250 = eq(UInt<5>(0h1f), idx_12) when _T_1250 : node _T_1251 = shl(UInt<4>(0hc), 3) node _T_1252 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1251) connect Queue10_UInt8_31.io.enq.bits, _T_1252 node _idx_T_13 = add(write_start_index, UInt<4>(0hd)) node idx_13 = rem(_idx_T_13, UInt<6>(0h20)) node _T_1253 = eq(UInt<1>(0h0), idx_13) when _T_1253 : node _T_1254 = shl(UInt<4>(0hd), 3) node _T_1255 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1254) connect Queue10_UInt8.io.enq.bits, _T_1255 node _T_1256 = eq(UInt<1>(0h1), idx_13) when _T_1256 : node _T_1257 = shl(UInt<4>(0hd), 3) node _T_1258 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1257) connect Queue10_UInt8_1.io.enq.bits, _T_1258 node _T_1259 = eq(UInt<2>(0h2), idx_13) when _T_1259 : node _T_1260 = shl(UInt<4>(0hd), 3) node _T_1261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1260) connect Queue10_UInt8_2.io.enq.bits, _T_1261 node _T_1262 = eq(UInt<2>(0h3), idx_13) when _T_1262 : node _T_1263 = shl(UInt<4>(0hd), 3) node _T_1264 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1263) connect Queue10_UInt8_3.io.enq.bits, _T_1264 node _T_1265 = eq(UInt<3>(0h4), idx_13) when _T_1265 : node _T_1266 = shl(UInt<4>(0hd), 3) node _T_1267 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1266) connect Queue10_UInt8_4.io.enq.bits, _T_1267 node _T_1268 = eq(UInt<3>(0h5), idx_13) when _T_1268 : node _T_1269 = shl(UInt<4>(0hd), 3) node _T_1270 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1269) connect Queue10_UInt8_5.io.enq.bits, _T_1270 node _T_1271 = eq(UInt<3>(0h6), idx_13) when _T_1271 : node _T_1272 = shl(UInt<4>(0hd), 3) node _T_1273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1272) connect Queue10_UInt8_6.io.enq.bits, _T_1273 node _T_1274 = eq(UInt<3>(0h7), idx_13) when _T_1274 : node _T_1275 = shl(UInt<4>(0hd), 3) node _T_1276 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1275) connect Queue10_UInt8_7.io.enq.bits, _T_1276 node _T_1277 = eq(UInt<4>(0h8), idx_13) when _T_1277 : node _T_1278 = shl(UInt<4>(0hd), 3) node _T_1279 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1278) connect Queue10_UInt8_8.io.enq.bits, _T_1279 node _T_1280 = eq(UInt<4>(0h9), idx_13) when _T_1280 : node _T_1281 = shl(UInt<4>(0hd), 3) node _T_1282 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1281) connect Queue10_UInt8_9.io.enq.bits, _T_1282 node _T_1283 = eq(UInt<4>(0ha), idx_13) when _T_1283 : node _T_1284 = shl(UInt<4>(0hd), 3) node _T_1285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1284) connect Queue10_UInt8_10.io.enq.bits, _T_1285 node _T_1286 = eq(UInt<4>(0hb), idx_13) when _T_1286 : node _T_1287 = shl(UInt<4>(0hd), 3) node _T_1288 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1287) connect Queue10_UInt8_11.io.enq.bits, _T_1288 node _T_1289 = eq(UInt<4>(0hc), idx_13) when _T_1289 : node _T_1290 = shl(UInt<4>(0hd), 3) node _T_1291 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1290) connect Queue10_UInt8_12.io.enq.bits, _T_1291 node _T_1292 = eq(UInt<4>(0hd), idx_13) when _T_1292 : node _T_1293 = shl(UInt<4>(0hd), 3) node _T_1294 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1293) connect Queue10_UInt8_13.io.enq.bits, _T_1294 node _T_1295 = eq(UInt<4>(0he), idx_13) when _T_1295 : node _T_1296 = shl(UInt<4>(0hd), 3) node _T_1297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1296) connect Queue10_UInt8_14.io.enq.bits, _T_1297 node _T_1298 = eq(UInt<4>(0hf), idx_13) when _T_1298 : node _T_1299 = shl(UInt<4>(0hd), 3) node _T_1300 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1299) connect Queue10_UInt8_15.io.enq.bits, _T_1300 node _T_1301 = eq(UInt<5>(0h10), idx_13) when _T_1301 : node _T_1302 = shl(UInt<4>(0hd), 3) node _T_1303 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1302) connect Queue10_UInt8_16.io.enq.bits, _T_1303 node _T_1304 = eq(UInt<5>(0h11), idx_13) when _T_1304 : node _T_1305 = shl(UInt<4>(0hd), 3) node _T_1306 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1305) connect Queue10_UInt8_17.io.enq.bits, _T_1306 node _T_1307 = eq(UInt<5>(0h12), idx_13) when _T_1307 : node _T_1308 = shl(UInt<4>(0hd), 3) node _T_1309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1308) connect Queue10_UInt8_18.io.enq.bits, _T_1309 node _T_1310 = eq(UInt<5>(0h13), idx_13) when _T_1310 : node _T_1311 = shl(UInt<4>(0hd), 3) node _T_1312 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1311) connect Queue10_UInt8_19.io.enq.bits, _T_1312 node _T_1313 = eq(UInt<5>(0h14), idx_13) when _T_1313 : node _T_1314 = shl(UInt<4>(0hd), 3) node _T_1315 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1314) connect Queue10_UInt8_20.io.enq.bits, _T_1315 node _T_1316 = eq(UInt<5>(0h15), idx_13) when _T_1316 : node _T_1317 = shl(UInt<4>(0hd), 3) node _T_1318 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1317) connect Queue10_UInt8_21.io.enq.bits, _T_1318 node _T_1319 = eq(UInt<5>(0h16), idx_13) when _T_1319 : node _T_1320 = shl(UInt<4>(0hd), 3) node _T_1321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1320) connect Queue10_UInt8_22.io.enq.bits, _T_1321 node _T_1322 = eq(UInt<5>(0h17), idx_13) when _T_1322 : node _T_1323 = shl(UInt<4>(0hd), 3) node _T_1324 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1323) connect Queue10_UInt8_23.io.enq.bits, _T_1324 node _T_1325 = eq(UInt<5>(0h18), idx_13) when _T_1325 : node _T_1326 = shl(UInt<4>(0hd), 3) node _T_1327 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1326) connect Queue10_UInt8_24.io.enq.bits, _T_1327 node _T_1328 = eq(UInt<5>(0h19), idx_13) when _T_1328 : node _T_1329 = shl(UInt<4>(0hd), 3) node _T_1330 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1329) connect Queue10_UInt8_25.io.enq.bits, _T_1330 node _T_1331 = eq(UInt<5>(0h1a), idx_13) when _T_1331 : node _T_1332 = shl(UInt<4>(0hd), 3) node _T_1333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1332) connect Queue10_UInt8_26.io.enq.bits, _T_1333 node _T_1334 = eq(UInt<5>(0h1b), idx_13) when _T_1334 : node _T_1335 = shl(UInt<4>(0hd), 3) node _T_1336 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1335) connect Queue10_UInt8_27.io.enq.bits, _T_1336 node _T_1337 = eq(UInt<5>(0h1c), idx_13) when _T_1337 : node _T_1338 = shl(UInt<4>(0hd), 3) node _T_1339 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1338) connect Queue10_UInt8_28.io.enq.bits, _T_1339 node _T_1340 = eq(UInt<5>(0h1d), idx_13) when _T_1340 : node _T_1341 = shl(UInt<4>(0hd), 3) node _T_1342 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1341) connect Queue10_UInt8_29.io.enq.bits, _T_1342 node _T_1343 = eq(UInt<5>(0h1e), idx_13) when _T_1343 : node _T_1344 = shl(UInt<4>(0hd), 3) node _T_1345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1344) connect Queue10_UInt8_30.io.enq.bits, _T_1345 node _T_1346 = eq(UInt<5>(0h1f), idx_13) when _T_1346 : node _T_1347 = shl(UInt<4>(0hd), 3) node _T_1348 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1347) connect Queue10_UInt8_31.io.enq.bits, _T_1348 node _idx_T_14 = add(write_start_index, UInt<4>(0he)) node idx_14 = rem(_idx_T_14, UInt<6>(0h20)) node _T_1349 = eq(UInt<1>(0h0), idx_14) when _T_1349 : node _T_1350 = shl(UInt<4>(0he), 3) node _T_1351 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1350) connect Queue10_UInt8.io.enq.bits, _T_1351 node _T_1352 = eq(UInt<1>(0h1), idx_14) when _T_1352 : node _T_1353 = shl(UInt<4>(0he), 3) node _T_1354 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1353) connect Queue10_UInt8_1.io.enq.bits, _T_1354 node _T_1355 = eq(UInt<2>(0h2), idx_14) when _T_1355 : node _T_1356 = shl(UInt<4>(0he), 3) node _T_1357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1356) connect Queue10_UInt8_2.io.enq.bits, _T_1357 node _T_1358 = eq(UInt<2>(0h3), idx_14) when _T_1358 : node _T_1359 = shl(UInt<4>(0he), 3) node _T_1360 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1359) connect Queue10_UInt8_3.io.enq.bits, _T_1360 node _T_1361 = eq(UInt<3>(0h4), idx_14) when _T_1361 : node _T_1362 = shl(UInt<4>(0he), 3) node _T_1363 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1362) connect Queue10_UInt8_4.io.enq.bits, _T_1363 node _T_1364 = eq(UInt<3>(0h5), idx_14) when _T_1364 : node _T_1365 = shl(UInt<4>(0he), 3) node _T_1366 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1365) connect Queue10_UInt8_5.io.enq.bits, _T_1366 node _T_1367 = eq(UInt<3>(0h6), idx_14) when _T_1367 : node _T_1368 = shl(UInt<4>(0he), 3) node _T_1369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1368) connect Queue10_UInt8_6.io.enq.bits, _T_1369 node _T_1370 = eq(UInt<3>(0h7), idx_14) when _T_1370 : node _T_1371 = shl(UInt<4>(0he), 3) node _T_1372 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1371) connect Queue10_UInt8_7.io.enq.bits, _T_1372 node _T_1373 = eq(UInt<4>(0h8), idx_14) when _T_1373 : node _T_1374 = shl(UInt<4>(0he), 3) node _T_1375 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1374) connect Queue10_UInt8_8.io.enq.bits, _T_1375 node _T_1376 = eq(UInt<4>(0h9), idx_14) when _T_1376 : node _T_1377 = shl(UInt<4>(0he), 3) node _T_1378 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1377) connect Queue10_UInt8_9.io.enq.bits, _T_1378 node _T_1379 = eq(UInt<4>(0ha), idx_14) when _T_1379 : node _T_1380 = shl(UInt<4>(0he), 3) node _T_1381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1380) connect Queue10_UInt8_10.io.enq.bits, _T_1381 node _T_1382 = eq(UInt<4>(0hb), idx_14) when _T_1382 : node _T_1383 = shl(UInt<4>(0he), 3) node _T_1384 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1383) connect Queue10_UInt8_11.io.enq.bits, _T_1384 node _T_1385 = eq(UInt<4>(0hc), idx_14) when _T_1385 : node _T_1386 = shl(UInt<4>(0he), 3) node _T_1387 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1386) connect Queue10_UInt8_12.io.enq.bits, _T_1387 node _T_1388 = eq(UInt<4>(0hd), idx_14) when _T_1388 : node _T_1389 = shl(UInt<4>(0he), 3) node _T_1390 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1389) connect Queue10_UInt8_13.io.enq.bits, _T_1390 node _T_1391 = eq(UInt<4>(0he), idx_14) when _T_1391 : node _T_1392 = shl(UInt<4>(0he), 3) node _T_1393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1392) connect Queue10_UInt8_14.io.enq.bits, _T_1393 node _T_1394 = eq(UInt<4>(0hf), idx_14) when _T_1394 : node _T_1395 = shl(UInt<4>(0he), 3) node _T_1396 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1395) connect Queue10_UInt8_15.io.enq.bits, _T_1396 node _T_1397 = eq(UInt<5>(0h10), idx_14) when _T_1397 : node _T_1398 = shl(UInt<4>(0he), 3) node _T_1399 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1398) connect Queue10_UInt8_16.io.enq.bits, _T_1399 node _T_1400 = eq(UInt<5>(0h11), idx_14) when _T_1400 : node _T_1401 = shl(UInt<4>(0he), 3) node _T_1402 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1401) connect Queue10_UInt8_17.io.enq.bits, _T_1402 node _T_1403 = eq(UInt<5>(0h12), idx_14) when _T_1403 : node _T_1404 = shl(UInt<4>(0he), 3) node _T_1405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1404) connect Queue10_UInt8_18.io.enq.bits, _T_1405 node _T_1406 = eq(UInt<5>(0h13), idx_14) when _T_1406 : node _T_1407 = shl(UInt<4>(0he), 3) node _T_1408 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1407) connect Queue10_UInt8_19.io.enq.bits, _T_1408 node _T_1409 = eq(UInt<5>(0h14), idx_14) when _T_1409 : node _T_1410 = shl(UInt<4>(0he), 3) node _T_1411 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1410) connect Queue10_UInt8_20.io.enq.bits, _T_1411 node _T_1412 = eq(UInt<5>(0h15), idx_14) when _T_1412 : node _T_1413 = shl(UInt<4>(0he), 3) node _T_1414 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1413) connect Queue10_UInt8_21.io.enq.bits, _T_1414 node _T_1415 = eq(UInt<5>(0h16), idx_14) when _T_1415 : node _T_1416 = shl(UInt<4>(0he), 3) node _T_1417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1416) connect Queue10_UInt8_22.io.enq.bits, _T_1417 node _T_1418 = eq(UInt<5>(0h17), idx_14) when _T_1418 : node _T_1419 = shl(UInt<4>(0he), 3) node _T_1420 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1419) connect Queue10_UInt8_23.io.enq.bits, _T_1420 node _T_1421 = eq(UInt<5>(0h18), idx_14) when _T_1421 : node _T_1422 = shl(UInt<4>(0he), 3) node _T_1423 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1422) connect Queue10_UInt8_24.io.enq.bits, _T_1423 node _T_1424 = eq(UInt<5>(0h19), idx_14) when _T_1424 : node _T_1425 = shl(UInt<4>(0he), 3) node _T_1426 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1425) connect Queue10_UInt8_25.io.enq.bits, _T_1426 node _T_1427 = eq(UInt<5>(0h1a), idx_14) when _T_1427 : node _T_1428 = shl(UInt<4>(0he), 3) node _T_1429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1428) connect Queue10_UInt8_26.io.enq.bits, _T_1429 node _T_1430 = eq(UInt<5>(0h1b), idx_14) when _T_1430 : node _T_1431 = shl(UInt<4>(0he), 3) node _T_1432 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1431) connect Queue10_UInt8_27.io.enq.bits, _T_1432 node _T_1433 = eq(UInt<5>(0h1c), idx_14) when _T_1433 : node _T_1434 = shl(UInt<4>(0he), 3) node _T_1435 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1434) connect Queue10_UInt8_28.io.enq.bits, _T_1435 node _T_1436 = eq(UInt<5>(0h1d), idx_14) when _T_1436 : node _T_1437 = shl(UInt<4>(0he), 3) node _T_1438 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1437) connect Queue10_UInt8_29.io.enq.bits, _T_1438 node _T_1439 = eq(UInt<5>(0h1e), idx_14) when _T_1439 : node _T_1440 = shl(UInt<4>(0he), 3) node _T_1441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1440) connect Queue10_UInt8_30.io.enq.bits, _T_1441 node _T_1442 = eq(UInt<5>(0h1f), idx_14) when _T_1442 : node _T_1443 = shl(UInt<4>(0he), 3) node _T_1444 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1443) connect Queue10_UInt8_31.io.enq.bits, _T_1444 node _idx_T_15 = add(write_start_index, UInt<4>(0hf)) node idx_15 = rem(_idx_T_15, UInt<6>(0h20)) node _T_1445 = eq(UInt<1>(0h0), idx_15) when _T_1445 : node _T_1446 = shl(UInt<4>(0hf), 3) node _T_1447 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1446) connect Queue10_UInt8.io.enq.bits, _T_1447 node _T_1448 = eq(UInt<1>(0h1), idx_15) when _T_1448 : node _T_1449 = shl(UInt<4>(0hf), 3) node _T_1450 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1449) connect Queue10_UInt8_1.io.enq.bits, _T_1450 node _T_1451 = eq(UInt<2>(0h2), idx_15) when _T_1451 : node _T_1452 = shl(UInt<4>(0hf), 3) node _T_1453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1452) connect Queue10_UInt8_2.io.enq.bits, _T_1453 node _T_1454 = eq(UInt<2>(0h3), idx_15) when _T_1454 : node _T_1455 = shl(UInt<4>(0hf), 3) node _T_1456 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1455) connect Queue10_UInt8_3.io.enq.bits, _T_1456 node _T_1457 = eq(UInt<3>(0h4), idx_15) when _T_1457 : node _T_1458 = shl(UInt<4>(0hf), 3) node _T_1459 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1458) connect Queue10_UInt8_4.io.enq.bits, _T_1459 node _T_1460 = eq(UInt<3>(0h5), idx_15) when _T_1460 : node _T_1461 = shl(UInt<4>(0hf), 3) node _T_1462 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1461) connect Queue10_UInt8_5.io.enq.bits, _T_1462 node _T_1463 = eq(UInt<3>(0h6), idx_15) when _T_1463 : node _T_1464 = shl(UInt<4>(0hf), 3) node _T_1465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1464) connect Queue10_UInt8_6.io.enq.bits, _T_1465 node _T_1466 = eq(UInt<3>(0h7), idx_15) when _T_1466 : node _T_1467 = shl(UInt<4>(0hf), 3) node _T_1468 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1467) connect Queue10_UInt8_7.io.enq.bits, _T_1468 node _T_1469 = eq(UInt<4>(0h8), idx_15) when _T_1469 : node _T_1470 = shl(UInt<4>(0hf), 3) node _T_1471 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1470) connect Queue10_UInt8_8.io.enq.bits, _T_1471 node _T_1472 = eq(UInt<4>(0h9), idx_15) when _T_1472 : node _T_1473 = shl(UInt<4>(0hf), 3) node _T_1474 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1473) connect Queue10_UInt8_9.io.enq.bits, _T_1474 node _T_1475 = eq(UInt<4>(0ha), idx_15) when _T_1475 : node _T_1476 = shl(UInt<4>(0hf), 3) node _T_1477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1476) connect Queue10_UInt8_10.io.enq.bits, _T_1477 node _T_1478 = eq(UInt<4>(0hb), idx_15) when _T_1478 : node _T_1479 = shl(UInt<4>(0hf), 3) node _T_1480 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1479) connect Queue10_UInt8_11.io.enq.bits, _T_1480 node _T_1481 = eq(UInt<4>(0hc), idx_15) when _T_1481 : node _T_1482 = shl(UInt<4>(0hf), 3) node _T_1483 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1482) connect Queue10_UInt8_12.io.enq.bits, _T_1483 node _T_1484 = eq(UInt<4>(0hd), idx_15) when _T_1484 : node _T_1485 = shl(UInt<4>(0hf), 3) node _T_1486 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1485) connect Queue10_UInt8_13.io.enq.bits, _T_1486 node _T_1487 = eq(UInt<4>(0he), idx_15) when _T_1487 : node _T_1488 = shl(UInt<4>(0hf), 3) node _T_1489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1488) connect Queue10_UInt8_14.io.enq.bits, _T_1489 node _T_1490 = eq(UInt<4>(0hf), idx_15) when _T_1490 : node _T_1491 = shl(UInt<4>(0hf), 3) node _T_1492 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1491) connect Queue10_UInt8_15.io.enq.bits, _T_1492 node _T_1493 = eq(UInt<5>(0h10), idx_15) when _T_1493 : node _T_1494 = shl(UInt<4>(0hf), 3) node _T_1495 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1494) connect Queue10_UInt8_16.io.enq.bits, _T_1495 node _T_1496 = eq(UInt<5>(0h11), idx_15) when _T_1496 : node _T_1497 = shl(UInt<4>(0hf), 3) node _T_1498 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1497) connect Queue10_UInt8_17.io.enq.bits, _T_1498 node _T_1499 = eq(UInt<5>(0h12), idx_15) when _T_1499 : node _T_1500 = shl(UInt<4>(0hf), 3) node _T_1501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1500) connect Queue10_UInt8_18.io.enq.bits, _T_1501 node _T_1502 = eq(UInt<5>(0h13), idx_15) when _T_1502 : node _T_1503 = shl(UInt<4>(0hf), 3) node _T_1504 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1503) connect Queue10_UInt8_19.io.enq.bits, _T_1504 node _T_1505 = eq(UInt<5>(0h14), idx_15) when _T_1505 : node _T_1506 = shl(UInt<4>(0hf), 3) node _T_1507 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1506) connect Queue10_UInt8_20.io.enq.bits, _T_1507 node _T_1508 = eq(UInt<5>(0h15), idx_15) when _T_1508 : node _T_1509 = shl(UInt<4>(0hf), 3) node _T_1510 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1509) connect Queue10_UInt8_21.io.enq.bits, _T_1510 node _T_1511 = eq(UInt<5>(0h16), idx_15) when _T_1511 : node _T_1512 = shl(UInt<4>(0hf), 3) node _T_1513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1512) connect Queue10_UInt8_22.io.enq.bits, _T_1513 node _T_1514 = eq(UInt<5>(0h17), idx_15) when _T_1514 : node _T_1515 = shl(UInt<4>(0hf), 3) node _T_1516 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1515) connect Queue10_UInt8_23.io.enq.bits, _T_1516 node _T_1517 = eq(UInt<5>(0h18), idx_15) when _T_1517 : node _T_1518 = shl(UInt<4>(0hf), 3) node _T_1519 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1518) connect Queue10_UInt8_24.io.enq.bits, _T_1519 node _T_1520 = eq(UInt<5>(0h19), idx_15) when _T_1520 : node _T_1521 = shl(UInt<4>(0hf), 3) node _T_1522 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1521) connect Queue10_UInt8_25.io.enq.bits, _T_1522 node _T_1523 = eq(UInt<5>(0h1a), idx_15) when _T_1523 : node _T_1524 = shl(UInt<4>(0hf), 3) node _T_1525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1524) connect Queue10_UInt8_26.io.enq.bits, _T_1525 node _T_1526 = eq(UInt<5>(0h1b), idx_15) when _T_1526 : node _T_1527 = shl(UInt<4>(0hf), 3) node _T_1528 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1527) connect Queue10_UInt8_27.io.enq.bits, _T_1528 node _T_1529 = eq(UInt<5>(0h1c), idx_15) when _T_1529 : node _T_1530 = shl(UInt<4>(0hf), 3) node _T_1531 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1530) connect Queue10_UInt8_28.io.enq.bits, _T_1531 node _T_1532 = eq(UInt<5>(0h1d), idx_15) when _T_1532 : node _T_1533 = shl(UInt<4>(0hf), 3) node _T_1534 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1533) connect Queue10_UInt8_29.io.enq.bits, _T_1534 node _T_1535 = eq(UInt<5>(0h1e), idx_15) when _T_1535 : node _T_1536 = shl(UInt<4>(0hf), 3) node _T_1537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1536) connect Queue10_UInt8_30.io.enq.bits, _T_1537 node _T_1538 = eq(UInt<5>(0h1f), idx_15) when _T_1538 : node _T_1539 = shl(UInt<4>(0hf), 3) node _T_1540 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1539) connect Queue10_UInt8_31.io.enq.bits, _T_1540 node _idx_T_16 = add(write_start_index, UInt<5>(0h10)) node idx_16 = rem(_idx_T_16, UInt<6>(0h20)) node _T_1541 = eq(UInt<1>(0h0), idx_16) when _T_1541 : node _T_1542 = shl(UInt<5>(0h10), 3) node _T_1543 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1542) connect Queue10_UInt8.io.enq.bits, _T_1543 node _T_1544 = eq(UInt<1>(0h1), idx_16) when _T_1544 : node _T_1545 = shl(UInt<5>(0h10), 3) node _T_1546 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1545) connect Queue10_UInt8_1.io.enq.bits, _T_1546 node _T_1547 = eq(UInt<2>(0h2), idx_16) when _T_1547 : node _T_1548 = shl(UInt<5>(0h10), 3) node _T_1549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1548) connect Queue10_UInt8_2.io.enq.bits, _T_1549 node _T_1550 = eq(UInt<2>(0h3), idx_16) when _T_1550 : node _T_1551 = shl(UInt<5>(0h10), 3) node _T_1552 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1551) connect Queue10_UInt8_3.io.enq.bits, _T_1552 node _T_1553 = eq(UInt<3>(0h4), idx_16) when _T_1553 : node _T_1554 = shl(UInt<5>(0h10), 3) node _T_1555 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1554) connect Queue10_UInt8_4.io.enq.bits, _T_1555 node _T_1556 = eq(UInt<3>(0h5), idx_16) when _T_1556 : node _T_1557 = shl(UInt<5>(0h10), 3) node _T_1558 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1557) connect Queue10_UInt8_5.io.enq.bits, _T_1558 node _T_1559 = eq(UInt<3>(0h6), idx_16) when _T_1559 : node _T_1560 = shl(UInt<5>(0h10), 3) node _T_1561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1560) connect Queue10_UInt8_6.io.enq.bits, _T_1561 node _T_1562 = eq(UInt<3>(0h7), idx_16) when _T_1562 : node _T_1563 = shl(UInt<5>(0h10), 3) node _T_1564 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1563) connect Queue10_UInt8_7.io.enq.bits, _T_1564 node _T_1565 = eq(UInt<4>(0h8), idx_16) when _T_1565 : node _T_1566 = shl(UInt<5>(0h10), 3) node _T_1567 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1566) connect Queue10_UInt8_8.io.enq.bits, _T_1567 node _T_1568 = eq(UInt<4>(0h9), idx_16) when _T_1568 : node _T_1569 = shl(UInt<5>(0h10), 3) node _T_1570 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1569) connect Queue10_UInt8_9.io.enq.bits, _T_1570 node _T_1571 = eq(UInt<4>(0ha), idx_16) when _T_1571 : node _T_1572 = shl(UInt<5>(0h10), 3) node _T_1573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1572) connect Queue10_UInt8_10.io.enq.bits, _T_1573 node _T_1574 = eq(UInt<4>(0hb), idx_16) when _T_1574 : node _T_1575 = shl(UInt<5>(0h10), 3) node _T_1576 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1575) connect Queue10_UInt8_11.io.enq.bits, _T_1576 node _T_1577 = eq(UInt<4>(0hc), idx_16) when _T_1577 : node _T_1578 = shl(UInt<5>(0h10), 3) node _T_1579 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1578) connect Queue10_UInt8_12.io.enq.bits, _T_1579 node _T_1580 = eq(UInt<4>(0hd), idx_16) when _T_1580 : node _T_1581 = shl(UInt<5>(0h10), 3) node _T_1582 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1581) connect Queue10_UInt8_13.io.enq.bits, _T_1582 node _T_1583 = eq(UInt<4>(0he), idx_16) when _T_1583 : node _T_1584 = shl(UInt<5>(0h10), 3) node _T_1585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1584) connect Queue10_UInt8_14.io.enq.bits, _T_1585 node _T_1586 = eq(UInt<4>(0hf), idx_16) when _T_1586 : node _T_1587 = shl(UInt<5>(0h10), 3) node _T_1588 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1587) connect Queue10_UInt8_15.io.enq.bits, _T_1588 node _T_1589 = eq(UInt<5>(0h10), idx_16) when _T_1589 : node _T_1590 = shl(UInt<5>(0h10), 3) node _T_1591 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1590) connect Queue10_UInt8_16.io.enq.bits, _T_1591 node _T_1592 = eq(UInt<5>(0h11), idx_16) when _T_1592 : node _T_1593 = shl(UInt<5>(0h10), 3) node _T_1594 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1593) connect Queue10_UInt8_17.io.enq.bits, _T_1594 node _T_1595 = eq(UInt<5>(0h12), idx_16) when _T_1595 : node _T_1596 = shl(UInt<5>(0h10), 3) node _T_1597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1596) connect Queue10_UInt8_18.io.enq.bits, _T_1597 node _T_1598 = eq(UInt<5>(0h13), idx_16) when _T_1598 : node _T_1599 = shl(UInt<5>(0h10), 3) node _T_1600 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1599) connect Queue10_UInt8_19.io.enq.bits, _T_1600 node _T_1601 = eq(UInt<5>(0h14), idx_16) when _T_1601 : node _T_1602 = shl(UInt<5>(0h10), 3) node _T_1603 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1602) connect Queue10_UInt8_20.io.enq.bits, _T_1603 node _T_1604 = eq(UInt<5>(0h15), idx_16) when _T_1604 : node _T_1605 = shl(UInt<5>(0h10), 3) node _T_1606 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1605) connect Queue10_UInt8_21.io.enq.bits, _T_1606 node _T_1607 = eq(UInt<5>(0h16), idx_16) when _T_1607 : node _T_1608 = shl(UInt<5>(0h10), 3) node _T_1609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1608) connect Queue10_UInt8_22.io.enq.bits, _T_1609 node _T_1610 = eq(UInt<5>(0h17), idx_16) when _T_1610 : node _T_1611 = shl(UInt<5>(0h10), 3) node _T_1612 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1611) connect Queue10_UInt8_23.io.enq.bits, _T_1612 node _T_1613 = eq(UInt<5>(0h18), idx_16) when _T_1613 : node _T_1614 = shl(UInt<5>(0h10), 3) node _T_1615 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1614) connect Queue10_UInt8_24.io.enq.bits, _T_1615 node _T_1616 = eq(UInt<5>(0h19), idx_16) when _T_1616 : node _T_1617 = shl(UInt<5>(0h10), 3) node _T_1618 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1617) connect Queue10_UInt8_25.io.enq.bits, _T_1618 node _T_1619 = eq(UInt<5>(0h1a), idx_16) when _T_1619 : node _T_1620 = shl(UInt<5>(0h10), 3) node _T_1621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1620) connect Queue10_UInt8_26.io.enq.bits, _T_1621 node _T_1622 = eq(UInt<5>(0h1b), idx_16) when _T_1622 : node _T_1623 = shl(UInt<5>(0h10), 3) node _T_1624 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1623) connect Queue10_UInt8_27.io.enq.bits, _T_1624 node _T_1625 = eq(UInt<5>(0h1c), idx_16) when _T_1625 : node _T_1626 = shl(UInt<5>(0h10), 3) node _T_1627 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1626) connect Queue10_UInt8_28.io.enq.bits, _T_1627 node _T_1628 = eq(UInt<5>(0h1d), idx_16) when _T_1628 : node _T_1629 = shl(UInt<5>(0h10), 3) node _T_1630 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1629) connect Queue10_UInt8_29.io.enq.bits, _T_1630 node _T_1631 = eq(UInt<5>(0h1e), idx_16) when _T_1631 : node _T_1632 = shl(UInt<5>(0h10), 3) node _T_1633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1632) connect Queue10_UInt8_30.io.enq.bits, _T_1633 node _T_1634 = eq(UInt<5>(0h1f), idx_16) when _T_1634 : node _T_1635 = shl(UInt<5>(0h10), 3) node _T_1636 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1635) connect Queue10_UInt8_31.io.enq.bits, _T_1636 node _idx_T_17 = add(write_start_index, UInt<5>(0h11)) node idx_17 = rem(_idx_T_17, UInt<6>(0h20)) node _T_1637 = eq(UInt<1>(0h0), idx_17) when _T_1637 : node _T_1638 = shl(UInt<5>(0h11), 3) node _T_1639 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1638) connect Queue10_UInt8.io.enq.bits, _T_1639 node _T_1640 = eq(UInt<1>(0h1), idx_17) when _T_1640 : node _T_1641 = shl(UInt<5>(0h11), 3) node _T_1642 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1641) connect Queue10_UInt8_1.io.enq.bits, _T_1642 node _T_1643 = eq(UInt<2>(0h2), idx_17) when _T_1643 : node _T_1644 = shl(UInt<5>(0h11), 3) node _T_1645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1644) connect Queue10_UInt8_2.io.enq.bits, _T_1645 node _T_1646 = eq(UInt<2>(0h3), idx_17) when _T_1646 : node _T_1647 = shl(UInt<5>(0h11), 3) node _T_1648 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1647) connect Queue10_UInt8_3.io.enq.bits, _T_1648 node _T_1649 = eq(UInt<3>(0h4), idx_17) when _T_1649 : node _T_1650 = shl(UInt<5>(0h11), 3) node _T_1651 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1650) connect Queue10_UInt8_4.io.enq.bits, _T_1651 node _T_1652 = eq(UInt<3>(0h5), idx_17) when _T_1652 : node _T_1653 = shl(UInt<5>(0h11), 3) node _T_1654 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1653) connect Queue10_UInt8_5.io.enq.bits, _T_1654 node _T_1655 = eq(UInt<3>(0h6), idx_17) when _T_1655 : node _T_1656 = shl(UInt<5>(0h11), 3) node _T_1657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1656) connect Queue10_UInt8_6.io.enq.bits, _T_1657 node _T_1658 = eq(UInt<3>(0h7), idx_17) when _T_1658 : node _T_1659 = shl(UInt<5>(0h11), 3) node _T_1660 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1659) connect Queue10_UInt8_7.io.enq.bits, _T_1660 node _T_1661 = eq(UInt<4>(0h8), idx_17) when _T_1661 : node _T_1662 = shl(UInt<5>(0h11), 3) node _T_1663 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1662) connect Queue10_UInt8_8.io.enq.bits, _T_1663 node _T_1664 = eq(UInt<4>(0h9), idx_17) when _T_1664 : node _T_1665 = shl(UInt<5>(0h11), 3) node _T_1666 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1665) connect Queue10_UInt8_9.io.enq.bits, _T_1666 node _T_1667 = eq(UInt<4>(0ha), idx_17) when _T_1667 : node _T_1668 = shl(UInt<5>(0h11), 3) node _T_1669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1668) connect Queue10_UInt8_10.io.enq.bits, _T_1669 node _T_1670 = eq(UInt<4>(0hb), idx_17) when _T_1670 : node _T_1671 = shl(UInt<5>(0h11), 3) node _T_1672 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1671) connect Queue10_UInt8_11.io.enq.bits, _T_1672 node _T_1673 = eq(UInt<4>(0hc), idx_17) when _T_1673 : node _T_1674 = shl(UInt<5>(0h11), 3) node _T_1675 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1674) connect Queue10_UInt8_12.io.enq.bits, _T_1675 node _T_1676 = eq(UInt<4>(0hd), idx_17) when _T_1676 : node _T_1677 = shl(UInt<5>(0h11), 3) node _T_1678 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1677) connect Queue10_UInt8_13.io.enq.bits, _T_1678 node _T_1679 = eq(UInt<4>(0he), idx_17) when _T_1679 : node _T_1680 = shl(UInt<5>(0h11), 3) node _T_1681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1680) connect Queue10_UInt8_14.io.enq.bits, _T_1681 node _T_1682 = eq(UInt<4>(0hf), idx_17) when _T_1682 : node _T_1683 = shl(UInt<5>(0h11), 3) node _T_1684 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1683) connect Queue10_UInt8_15.io.enq.bits, _T_1684 node _T_1685 = eq(UInt<5>(0h10), idx_17) when _T_1685 : node _T_1686 = shl(UInt<5>(0h11), 3) node _T_1687 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1686) connect Queue10_UInt8_16.io.enq.bits, _T_1687 node _T_1688 = eq(UInt<5>(0h11), idx_17) when _T_1688 : node _T_1689 = shl(UInt<5>(0h11), 3) node _T_1690 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1689) connect Queue10_UInt8_17.io.enq.bits, _T_1690 node _T_1691 = eq(UInt<5>(0h12), idx_17) when _T_1691 : node _T_1692 = shl(UInt<5>(0h11), 3) node _T_1693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1692) connect Queue10_UInt8_18.io.enq.bits, _T_1693 node _T_1694 = eq(UInt<5>(0h13), idx_17) when _T_1694 : node _T_1695 = shl(UInt<5>(0h11), 3) node _T_1696 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1695) connect Queue10_UInt8_19.io.enq.bits, _T_1696 node _T_1697 = eq(UInt<5>(0h14), idx_17) when _T_1697 : node _T_1698 = shl(UInt<5>(0h11), 3) node _T_1699 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1698) connect Queue10_UInt8_20.io.enq.bits, _T_1699 node _T_1700 = eq(UInt<5>(0h15), idx_17) when _T_1700 : node _T_1701 = shl(UInt<5>(0h11), 3) node _T_1702 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1701) connect Queue10_UInt8_21.io.enq.bits, _T_1702 node _T_1703 = eq(UInt<5>(0h16), idx_17) when _T_1703 : node _T_1704 = shl(UInt<5>(0h11), 3) node _T_1705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1704) connect Queue10_UInt8_22.io.enq.bits, _T_1705 node _T_1706 = eq(UInt<5>(0h17), idx_17) when _T_1706 : node _T_1707 = shl(UInt<5>(0h11), 3) node _T_1708 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1707) connect Queue10_UInt8_23.io.enq.bits, _T_1708 node _T_1709 = eq(UInt<5>(0h18), idx_17) when _T_1709 : node _T_1710 = shl(UInt<5>(0h11), 3) node _T_1711 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1710) connect Queue10_UInt8_24.io.enq.bits, _T_1711 node _T_1712 = eq(UInt<5>(0h19), idx_17) when _T_1712 : node _T_1713 = shl(UInt<5>(0h11), 3) node _T_1714 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1713) connect Queue10_UInt8_25.io.enq.bits, _T_1714 node _T_1715 = eq(UInt<5>(0h1a), idx_17) when _T_1715 : node _T_1716 = shl(UInt<5>(0h11), 3) node _T_1717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1716) connect Queue10_UInt8_26.io.enq.bits, _T_1717 node _T_1718 = eq(UInt<5>(0h1b), idx_17) when _T_1718 : node _T_1719 = shl(UInt<5>(0h11), 3) node _T_1720 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1719) connect Queue10_UInt8_27.io.enq.bits, _T_1720 node _T_1721 = eq(UInt<5>(0h1c), idx_17) when _T_1721 : node _T_1722 = shl(UInt<5>(0h11), 3) node _T_1723 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1722) connect Queue10_UInt8_28.io.enq.bits, _T_1723 node _T_1724 = eq(UInt<5>(0h1d), idx_17) when _T_1724 : node _T_1725 = shl(UInt<5>(0h11), 3) node _T_1726 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1725) connect Queue10_UInt8_29.io.enq.bits, _T_1726 node _T_1727 = eq(UInt<5>(0h1e), idx_17) when _T_1727 : node _T_1728 = shl(UInt<5>(0h11), 3) node _T_1729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1728) connect Queue10_UInt8_30.io.enq.bits, _T_1729 node _T_1730 = eq(UInt<5>(0h1f), idx_17) when _T_1730 : node _T_1731 = shl(UInt<5>(0h11), 3) node _T_1732 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1731) connect Queue10_UInt8_31.io.enq.bits, _T_1732 node _idx_T_18 = add(write_start_index, UInt<5>(0h12)) node idx_18 = rem(_idx_T_18, UInt<6>(0h20)) node _T_1733 = eq(UInt<1>(0h0), idx_18) when _T_1733 : node _T_1734 = shl(UInt<5>(0h12), 3) node _T_1735 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1734) connect Queue10_UInt8.io.enq.bits, _T_1735 node _T_1736 = eq(UInt<1>(0h1), idx_18) when _T_1736 : node _T_1737 = shl(UInt<5>(0h12), 3) node _T_1738 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1737) connect Queue10_UInt8_1.io.enq.bits, _T_1738 node _T_1739 = eq(UInt<2>(0h2), idx_18) when _T_1739 : node _T_1740 = shl(UInt<5>(0h12), 3) node _T_1741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1740) connect Queue10_UInt8_2.io.enq.bits, _T_1741 node _T_1742 = eq(UInt<2>(0h3), idx_18) when _T_1742 : node _T_1743 = shl(UInt<5>(0h12), 3) node _T_1744 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1743) connect Queue10_UInt8_3.io.enq.bits, _T_1744 node _T_1745 = eq(UInt<3>(0h4), idx_18) when _T_1745 : node _T_1746 = shl(UInt<5>(0h12), 3) node _T_1747 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1746) connect Queue10_UInt8_4.io.enq.bits, _T_1747 node _T_1748 = eq(UInt<3>(0h5), idx_18) when _T_1748 : node _T_1749 = shl(UInt<5>(0h12), 3) node _T_1750 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1749) connect Queue10_UInt8_5.io.enq.bits, _T_1750 node _T_1751 = eq(UInt<3>(0h6), idx_18) when _T_1751 : node _T_1752 = shl(UInt<5>(0h12), 3) node _T_1753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1752) connect Queue10_UInt8_6.io.enq.bits, _T_1753 node _T_1754 = eq(UInt<3>(0h7), idx_18) when _T_1754 : node _T_1755 = shl(UInt<5>(0h12), 3) node _T_1756 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1755) connect Queue10_UInt8_7.io.enq.bits, _T_1756 node _T_1757 = eq(UInt<4>(0h8), idx_18) when _T_1757 : node _T_1758 = shl(UInt<5>(0h12), 3) node _T_1759 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1758) connect Queue10_UInt8_8.io.enq.bits, _T_1759 node _T_1760 = eq(UInt<4>(0h9), idx_18) when _T_1760 : node _T_1761 = shl(UInt<5>(0h12), 3) node _T_1762 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1761) connect Queue10_UInt8_9.io.enq.bits, _T_1762 node _T_1763 = eq(UInt<4>(0ha), idx_18) when _T_1763 : node _T_1764 = shl(UInt<5>(0h12), 3) node _T_1765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1764) connect Queue10_UInt8_10.io.enq.bits, _T_1765 node _T_1766 = eq(UInt<4>(0hb), idx_18) when _T_1766 : node _T_1767 = shl(UInt<5>(0h12), 3) node _T_1768 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1767) connect Queue10_UInt8_11.io.enq.bits, _T_1768 node _T_1769 = eq(UInt<4>(0hc), idx_18) when _T_1769 : node _T_1770 = shl(UInt<5>(0h12), 3) node _T_1771 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1770) connect Queue10_UInt8_12.io.enq.bits, _T_1771 node _T_1772 = eq(UInt<4>(0hd), idx_18) when _T_1772 : node _T_1773 = shl(UInt<5>(0h12), 3) node _T_1774 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1773) connect Queue10_UInt8_13.io.enq.bits, _T_1774 node _T_1775 = eq(UInt<4>(0he), idx_18) when _T_1775 : node _T_1776 = shl(UInt<5>(0h12), 3) node _T_1777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1776) connect Queue10_UInt8_14.io.enq.bits, _T_1777 node _T_1778 = eq(UInt<4>(0hf), idx_18) when _T_1778 : node _T_1779 = shl(UInt<5>(0h12), 3) node _T_1780 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1779) connect Queue10_UInt8_15.io.enq.bits, _T_1780 node _T_1781 = eq(UInt<5>(0h10), idx_18) when _T_1781 : node _T_1782 = shl(UInt<5>(0h12), 3) node _T_1783 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1782) connect Queue10_UInt8_16.io.enq.bits, _T_1783 node _T_1784 = eq(UInt<5>(0h11), idx_18) when _T_1784 : node _T_1785 = shl(UInt<5>(0h12), 3) node _T_1786 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1785) connect Queue10_UInt8_17.io.enq.bits, _T_1786 node _T_1787 = eq(UInt<5>(0h12), idx_18) when _T_1787 : node _T_1788 = shl(UInt<5>(0h12), 3) node _T_1789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1788) connect Queue10_UInt8_18.io.enq.bits, _T_1789 node _T_1790 = eq(UInt<5>(0h13), idx_18) when _T_1790 : node _T_1791 = shl(UInt<5>(0h12), 3) node _T_1792 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1791) connect Queue10_UInt8_19.io.enq.bits, _T_1792 node _T_1793 = eq(UInt<5>(0h14), idx_18) when _T_1793 : node _T_1794 = shl(UInt<5>(0h12), 3) node _T_1795 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1794) connect Queue10_UInt8_20.io.enq.bits, _T_1795 node _T_1796 = eq(UInt<5>(0h15), idx_18) when _T_1796 : node _T_1797 = shl(UInt<5>(0h12), 3) node _T_1798 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1797) connect Queue10_UInt8_21.io.enq.bits, _T_1798 node _T_1799 = eq(UInt<5>(0h16), idx_18) when _T_1799 : node _T_1800 = shl(UInt<5>(0h12), 3) node _T_1801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1800) connect Queue10_UInt8_22.io.enq.bits, _T_1801 node _T_1802 = eq(UInt<5>(0h17), idx_18) when _T_1802 : node _T_1803 = shl(UInt<5>(0h12), 3) node _T_1804 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1803) connect Queue10_UInt8_23.io.enq.bits, _T_1804 node _T_1805 = eq(UInt<5>(0h18), idx_18) when _T_1805 : node _T_1806 = shl(UInt<5>(0h12), 3) node _T_1807 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1806) connect Queue10_UInt8_24.io.enq.bits, _T_1807 node _T_1808 = eq(UInt<5>(0h19), idx_18) when _T_1808 : node _T_1809 = shl(UInt<5>(0h12), 3) node _T_1810 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1809) connect Queue10_UInt8_25.io.enq.bits, _T_1810 node _T_1811 = eq(UInt<5>(0h1a), idx_18) when _T_1811 : node _T_1812 = shl(UInt<5>(0h12), 3) node _T_1813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1812) connect Queue10_UInt8_26.io.enq.bits, _T_1813 node _T_1814 = eq(UInt<5>(0h1b), idx_18) when _T_1814 : node _T_1815 = shl(UInt<5>(0h12), 3) node _T_1816 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1815) connect Queue10_UInt8_27.io.enq.bits, _T_1816 node _T_1817 = eq(UInt<5>(0h1c), idx_18) when _T_1817 : node _T_1818 = shl(UInt<5>(0h12), 3) node _T_1819 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1818) connect Queue10_UInt8_28.io.enq.bits, _T_1819 node _T_1820 = eq(UInt<5>(0h1d), idx_18) when _T_1820 : node _T_1821 = shl(UInt<5>(0h12), 3) node _T_1822 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1821) connect Queue10_UInt8_29.io.enq.bits, _T_1822 node _T_1823 = eq(UInt<5>(0h1e), idx_18) when _T_1823 : node _T_1824 = shl(UInt<5>(0h12), 3) node _T_1825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1824) connect Queue10_UInt8_30.io.enq.bits, _T_1825 node _T_1826 = eq(UInt<5>(0h1f), idx_18) when _T_1826 : node _T_1827 = shl(UInt<5>(0h12), 3) node _T_1828 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1827) connect Queue10_UInt8_31.io.enq.bits, _T_1828 node _idx_T_19 = add(write_start_index, UInt<5>(0h13)) node idx_19 = rem(_idx_T_19, UInt<6>(0h20)) node _T_1829 = eq(UInt<1>(0h0), idx_19) when _T_1829 : node _T_1830 = shl(UInt<5>(0h13), 3) node _T_1831 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1830) connect Queue10_UInt8.io.enq.bits, _T_1831 node _T_1832 = eq(UInt<1>(0h1), idx_19) when _T_1832 : node _T_1833 = shl(UInt<5>(0h13), 3) node _T_1834 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1833) connect Queue10_UInt8_1.io.enq.bits, _T_1834 node _T_1835 = eq(UInt<2>(0h2), idx_19) when _T_1835 : node _T_1836 = shl(UInt<5>(0h13), 3) node _T_1837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1836) connect Queue10_UInt8_2.io.enq.bits, _T_1837 node _T_1838 = eq(UInt<2>(0h3), idx_19) when _T_1838 : node _T_1839 = shl(UInt<5>(0h13), 3) node _T_1840 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1839) connect Queue10_UInt8_3.io.enq.bits, _T_1840 node _T_1841 = eq(UInt<3>(0h4), idx_19) when _T_1841 : node _T_1842 = shl(UInt<5>(0h13), 3) node _T_1843 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1842) connect Queue10_UInt8_4.io.enq.bits, _T_1843 node _T_1844 = eq(UInt<3>(0h5), idx_19) when _T_1844 : node _T_1845 = shl(UInt<5>(0h13), 3) node _T_1846 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1845) connect Queue10_UInt8_5.io.enq.bits, _T_1846 node _T_1847 = eq(UInt<3>(0h6), idx_19) when _T_1847 : node _T_1848 = shl(UInt<5>(0h13), 3) node _T_1849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1848) connect Queue10_UInt8_6.io.enq.bits, _T_1849 node _T_1850 = eq(UInt<3>(0h7), idx_19) when _T_1850 : node _T_1851 = shl(UInt<5>(0h13), 3) node _T_1852 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1851) connect Queue10_UInt8_7.io.enq.bits, _T_1852 node _T_1853 = eq(UInt<4>(0h8), idx_19) when _T_1853 : node _T_1854 = shl(UInt<5>(0h13), 3) node _T_1855 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1854) connect Queue10_UInt8_8.io.enq.bits, _T_1855 node _T_1856 = eq(UInt<4>(0h9), idx_19) when _T_1856 : node _T_1857 = shl(UInt<5>(0h13), 3) node _T_1858 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1857) connect Queue10_UInt8_9.io.enq.bits, _T_1858 node _T_1859 = eq(UInt<4>(0ha), idx_19) when _T_1859 : node _T_1860 = shl(UInt<5>(0h13), 3) node _T_1861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1860) connect Queue10_UInt8_10.io.enq.bits, _T_1861 node _T_1862 = eq(UInt<4>(0hb), idx_19) when _T_1862 : node _T_1863 = shl(UInt<5>(0h13), 3) node _T_1864 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1863) connect Queue10_UInt8_11.io.enq.bits, _T_1864 node _T_1865 = eq(UInt<4>(0hc), idx_19) when _T_1865 : node _T_1866 = shl(UInt<5>(0h13), 3) node _T_1867 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1866) connect Queue10_UInt8_12.io.enq.bits, _T_1867 node _T_1868 = eq(UInt<4>(0hd), idx_19) when _T_1868 : node _T_1869 = shl(UInt<5>(0h13), 3) node _T_1870 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1869) connect Queue10_UInt8_13.io.enq.bits, _T_1870 node _T_1871 = eq(UInt<4>(0he), idx_19) when _T_1871 : node _T_1872 = shl(UInt<5>(0h13), 3) node _T_1873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1872) connect Queue10_UInt8_14.io.enq.bits, _T_1873 node _T_1874 = eq(UInt<4>(0hf), idx_19) when _T_1874 : node _T_1875 = shl(UInt<5>(0h13), 3) node _T_1876 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1875) connect Queue10_UInt8_15.io.enq.bits, _T_1876 node _T_1877 = eq(UInt<5>(0h10), idx_19) when _T_1877 : node _T_1878 = shl(UInt<5>(0h13), 3) node _T_1879 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1878) connect Queue10_UInt8_16.io.enq.bits, _T_1879 node _T_1880 = eq(UInt<5>(0h11), idx_19) when _T_1880 : node _T_1881 = shl(UInt<5>(0h13), 3) node _T_1882 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1881) connect Queue10_UInt8_17.io.enq.bits, _T_1882 node _T_1883 = eq(UInt<5>(0h12), idx_19) when _T_1883 : node _T_1884 = shl(UInt<5>(0h13), 3) node _T_1885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1884) connect Queue10_UInt8_18.io.enq.bits, _T_1885 node _T_1886 = eq(UInt<5>(0h13), idx_19) when _T_1886 : node _T_1887 = shl(UInt<5>(0h13), 3) node _T_1888 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1887) connect Queue10_UInt8_19.io.enq.bits, _T_1888 node _T_1889 = eq(UInt<5>(0h14), idx_19) when _T_1889 : node _T_1890 = shl(UInt<5>(0h13), 3) node _T_1891 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1890) connect Queue10_UInt8_20.io.enq.bits, _T_1891 node _T_1892 = eq(UInt<5>(0h15), idx_19) when _T_1892 : node _T_1893 = shl(UInt<5>(0h13), 3) node _T_1894 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1893) connect Queue10_UInt8_21.io.enq.bits, _T_1894 node _T_1895 = eq(UInt<5>(0h16), idx_19) when _T_1895 : node _T_1896 = shl(UInt<5>(0h13), 3) node _T_1897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1896) connect Queue10_UInt8_22.io.enq.bits, _T_1897 node _T_1898 = eq(UInt<5>(0h17), idx_19) when _T_1898 : node _T_1899 = shl(UInt<5>(0h13), 3) node _T_1900 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1899) connect Queue10_UInt8_23.io.enq.bits, _T_1900 node _T_1901 = eq(UInt<5>(0h18), idx_19) when _T_1901 : node _T_1902 = shl(UInt<5>(0h13), 3) node _T_1903 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1902) connect Queue10_UInt8_24.io.enq.bits, _T_1903 node _T_1904 = eq(UInt<5>(0h19), idx_19) when _T_1904 : node _T_1905 = shl(UInt<5>(0h13), 3) node _T_1906 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1905) connect Queue10_UInt8_25.io.enq.bits, _T_1906 node _T_1907 = eq(UInt<5>(0h1a), idx_19) when _T_1907 : node _T_1908 = shl(UInt<5>(0h13), 3) node _T_1909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1908) connect Queue10_UInt8_26.io.enq.bits, _T_1909 node _T_1910 = eq(UInt<5>(0h1b), idx_19) when _T_1910 : node _T_1911 = shl(UInt<5>(0h13), 3) node _T_1912 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1911) connect Queue10_UInt8_27.io.enq.bits, _T_1912 node _T_1913 = eq(UInt<5>(0h1c), idx_19) when _T_1913 : node _T_1914 = shl(UInt<5>(0h13), 3) node _T_1915 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1914) connect Queue10_UInt8_28.io.enq.bits, _T_1915 node _T_1916 = eq(UInt<5>(0h1d), idx_19) when _T_1916 : node _T_1917 = shl(UInt<5>(0h13), 3) node _T_1918 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1917) connect Queue10_UInt8_29.io.enq.bits, _T_1918 node _T_1919 = eq(UInt<5>(0h1e), idx_19) when _T_1919 : node _T_1920 = shl(UInt<5>(0h13), 3) node _T_1921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1920) connect Queue10_UInt8_30.io.enq.bits, _T_1921 node _T_1922 = eq(UInt<5>(0h1f), idx_19) when _T_1922 : node _T_1923 = shl(UInt<5>(0h13), 3) node _T_1924 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1923) connect Queue10_UInt8_31.io.enq.bits, _T_1924 node _idx_T_20 = add(write_start_index, UInt<5>(0h14)) node idx_20 = rem(_idx_T_20, UInt<6>(0h20)) node _T_1925 = eq(UInt<1>(0h0), idx_20) when _T_1925 : node _T_1926 = shl(UInt<5>(0h14), 3) node _T_1927 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1926) connect Queue10_UInt8.io.enq.bits, _T_1927 node _T_1928 = eq(UInt<1>(0h1), idx_20) when _T_1928 : node _T_1929 = shl(UInt<5>(0h14), 3) node _T_1930 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1929) connect Queue10_UInt8_1.io.enq.bits, _T_1930 node _T_1931 = eq(UInt<2>(0h2), idx_20) when _T_1931 : node _T_1932 = shl(UInt<5>(0h14), 3) node _T_1933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1932) connect Queue10_UInt8_2.io.enq.bits, _T_1933 node _T_1934 = eq(UInt<2>(0h3), idx_20) when _T_1934 : node _T_1935 = shl(UInt<5>(0h14), 3) node _T_1936 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1935) connect Queue10_UInt8_3.io.enq.bits, _T_1936 node _T_1937 = eq(UInt<3>(0h4), idx_20) when _T_1937 : node _T_1938 = shl(UInt<5>(0h14), 3) node _T_1939 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1938) connect Queue10_UInt8_4.io.enq.bits, _T_1939 node _T_1940 = eq(UInt<3>(0h5), idx_20) when _T_1940 : node _T_1941 = shl(UInt<5>(0h14), 3) node _T_1942 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1941) connect Queue10_UInt8_5.io.enq.bits, _T_1942 node _T_1943 = eq(UInt<3>(0h6), idx_20) when _T_1943 : node _T_1944 = shl(UInt<5>(0h14), 3) node _T_1945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1944) connect Queue10_UInt8_6.io.enq.bits, _T_1945 node _T_1946 = eq(UInt<3>(0h7), idx_20) when _T_1946 : node _T_1947 = shl(UInt<5>(0h14), 3) node _T_1948 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1947) connect Queue10_UInt8_7.io.enq.bits, _T_1948 node _T_1949 = eq(UInt<4>(0h8), idx_20) when _T_1949 : node _T_1950 = shl(UInt<5>(0h14), 3) node _T_1951 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1950) connect Queue10_UInt8_8.io.enq.bits, _T_1951 node _T_1952 = eq(UInt<4>(0h9), idx_20) when _T_1952 : node _T_1953 = shl(UInt<5>(0h14), 3) node _T_1954 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1953) connect Queue10_UInt8_9.io.enq.bits, _T_1954 node _T_1955 = eq(UInt<4>(0ha), idx_20) when _T_1955 : node _T_1956 = shl(UInt<5>(0h14), 3) node _T_1957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1956) connect Queue10_UInt8_10.io.enq.bits, _T_1957 node _T_1958 = eq(UInt<4>(0hb), idx_20) when _T_1958 : node _T_1959 = shl(UInt<5>(0h14), 3) node _T_1960 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1959) connect Queue10_UInt8_11.io.enq.bits, _T_1960 node _T_1961 = eq(UInt<4>(0hc), idx_20) when _T_1961 : node _T_1962 = shl(UInt<5>(0h14), 3) node _T_1963 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1962) connect Queue10_UInt8_12.io.enq.bits, _T_1963 node _T_1964 = eq(UInt<4>(0hd), idx_20) when _T_1964 : node _T_1965 = shl(UInt<5>(0h14), 3) node _T_1966 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1965) connect Queue10_UInt8_13.io.enq.bits, _T_1966 node _T_1967 = eq(UInt<4>(0he), idx_20) when _T_1967 : node _T_1968 = shl(UInt<5>(0h14), 3) node _T_1969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1968) connect Queue10_UInt8_14.io.enq.bits, _T_1969 node _T_1970 = eq(UInt<4>(0hf), idx_20) when _T_1970 : node _T_1971 = shl(UInt<5>(0h14), 3) node _T_1972 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1971) connect Queue10_UInt8_15.io.enq.bits, _T_1972 node _T_1973 = eq(UInt<5>(0h10), idx_20) when _T_1973 : node _T_1974 = shl(UInt<5>(0h14), 3) node _T_1975 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1974) connect Queue10_UInt8_16.io.enq.bits, _T_1975 node _T_1976 = eq(UInt<5>(0h11), idx_20) when _T_1976 : node _T_1977 = shl(UInt<5>(0h14), 3) node _T_1978 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1977) connect Queue10_UInt8_17.io.enq.bits, _T_1978 node _T_1979 = eq(UInt<5>(0h12), idx_20) when _T_1979 : node _T_1980 = shl(UInt<5>(0h14), 3) node _T_1981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1980) connect Queue10_UInt8_18.io.enq.bits, _T_1981 node _T_1982 = eq(UInt<5>(0h13), idx_20) when _T_1982 : node _T_1983 = shl(UInt<5>(0h14), 3) node _T_1984 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1983) connect Queue10_UInt8_19.io.enq.bits, _T_1984 node _T_1985 = eq(UInt<5>(0h14), idx_20) when _T_1985 : node _T_1986 = shl(UInt<5>(0h14), 3) node _T_1987 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1986) connect Queue10_UInt8_20.io.enq.bits, _T_1987 node _T_1988 = eq(UInt<5>(0h15), idx_20) when _T_1988 : node _T_1989 = shl(UInt<5>(0h14), 3) node _T_1990 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1989) connect Queue10_UInt8_21.io.enq.bits, _T_1990 node _T_1991 = eq(UInt<5>(0h16), idx_20) when _T_1991 : node _T_1992 = shl(UInt<5>(0h14), 3) node _T_1993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1992) connect Queue10_UInt8_22.io.enq.bits, _T_1993 node _T_1994 = eq(UInt<5>(0h17), idx_20) when _T_1994 : node _T_1995 = shl(UInt<5>(0h14), 3) node _T_1996 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1995) connect Queue10_UInt8_23.io.enq.bits, _T_1996 node _T_1997 = eq(UInt<5>(0h18), idx_20) when _T_1997 : node _T_1998 = shl(UInt<5>(0h14), 3) node _T_1999 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1998) connect Queue10_UInt8_24.io.enq.bits, _T_1999 node _T_2000 = eq(UInt<5>(0h19), idx_20) when _T_2000 : node _T_2001 = shl(UInt<5>(0h14), 3) node _T_2002 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2001) connect Queue10_UInt8_25.io.enq.bits, _T_2002 node _T_2003 = eq(UInt<5>(0h1a), idx_20) when _T_2003 : node _T_2004 = shl(UInt<5>(0h14), 3) node _T_2005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2004) connect Queue10_UInt8_26.io.enq.bits, _T_2005 node _T_2006 = eq(UInt<5>(0h1b), idx_20) when _T_2006 : node _T_2007 = shl(UInt<5>(0h14), 3) node _T_2008 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2007) connect Queue10_UInt8_27.io.enq.bits, _T_2008 node _T_2009 = eq(UInt<5>(0h1c), idx_20) when _T_2009 : node _T_2010 = shl(UInt<5>(0h14), 3) node _T_2011 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2010) connect Queue10_UInt8_28.io.enq.bits, _T_2011 node _T_2012 = eq(UInt<5>(0h1d), idx_20) when _T_2012 : node _T_2013 = shl(UInt<5>(0h14), 3) node _T_2014 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2013) connect Queue10_UInt8_29.io.enq.bits, _T_2014 node _T_2015 = eq(UInt<5>(0h1e), idx_20) when _T_2015 : node _T_2016 = shl(UInt<5>(0h14), 3) node _T_2017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2016) connect Queue10_UInt8_30.io.enq.bits, _T_2017 node _T_2018 = eq(UInt<5>(0h1f), idx_20) when _T_2018 : node _T_2019 = shl(UInt<5>(0h14), 3) node _T_2020 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2019) connect Queue10_UInt8_31.io.enq.bits, _T_2020 node _idx_T_21 = add(write_start_index, UInt<5>(0h15)) node idx_21 = rem(_idx_T_21, UInt<6>(0h20)) node _T_2021 = eq(UInt<1>(0h0), idx_21) when _T_2021 : node _T_2022 = shl(UInt<5>(0h15), 3) node _T_2023 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2022) connect Queue10_UInt8.io.enq.bits, _T_2023 node _T_2024 = eq(UInt<1>(0h1), idx_21) when _T_2024 : node _T_2025 = shl(UInt<5>(0h15), 3) node _T_2026 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2025) connect Queue10_UInt8_1.io.enq.bits, _T_2026 node _T_2027 = eq(UInt<2>(0h2), idx_21) when _T_2027 : node _T_2028 = shl(UInt<5>(0h15), 3) node _T_2029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2028) connect Queue10_UInt8_2.io.enq.bits, _T_2029 node _T_2030 = eq(UInt<2>(0h3), idx_21) when _T_2030 : node _T_2031 = shl(UInt<5>(0h15), 3) node _T_2032 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2031) connect Queue10_UInt8_3.io.enq.bits, _T_2032 node _T_2033 = eq(UInt<3>(0h4), idx_21) when _T_2033 : node _T_2034 = shl(UInt<5>(0h15), 3) node _T_2035 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2034) connect Queue10_UInt8_4.io.enq.bits, _T_2035 node _T_2036 = eq(UInt<3>(0h5), idx_21) when _T_2036 : node _T_2037 = shl(UInt<5>(0h15), 3) node _T_2038 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2037) connect Queue10_UInt8_5.io.enq.bits, _T_2038 node _T_2039 = eq(UInt<3>(0h6), idx_21) when _T_2039 : node _T_2040 = shl(UInt<5>(0h15), 3) node _T_2041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2040) connect Queue10_UInt8_6.io.enq.bits, _T_2041 node _T_2042 = eq(UInt<3>(0h7), idx_21) when _T_2042 : node _T_2043 = shl(UInt<5>(0h15), 3) node _T_2044 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2043) connect Queue10_UInt8_7.io.enq.bits, _T_2044 node _T_2045 = eq(UInt<4>(0h8), idx_21) when _T_2045 : node _T_2046 = shl(UInt<5>(0h15), 3) node _T_2047 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2046) connect Queue10_UInt8_8.io.enq.bits, _T_2047 node _T_2048 = eq(UInt<4>(0h9), idx_21) when _T_2048 : node _T_2049 = shl(UInt<5>(0h15), 3) node _T_2050 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2049) connect Queue10_UInt8_9.io.enq.bits, _T_2050 node _T_2051 = eq(UInt<4>(0ha), idx_21) when _T_2051 : node _T_2052 = shl(UInt<5>(0h15), 3) node _T_2053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2052) connect Queue10_UInt8_10.io.enq.bits, _T_2053 node _T_2054 = eq(UInt<4>(0hb), idx_21) when _T_2054 : node _T_2055 = shl(UInt<5>(0h15), 3) node _T_2056 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2055) connect Queue10_UInt8_11.io.enq.bits, _T_2056 node _T_2057 = eq(UInt<4>(0hc), idx_21) when _T_2057 : node _T_2058 = shl(UInt<5>(0h15), 3) node _T_2059 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2058) connect Queue10_UInt8_12.io.enq.bits, _T_2059 node _T_2060 = eq(UInt<4>(0hd), idx_21) when _T_2060 : node _T_2061 = shl(UInt<5>(0h15), 3) node _T_2062 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2061) connect Queue10_UInt8_13.io.enq.bits, _T_2062 node _T_2063 = eq(UInt<4>(0he), idx_21) when _T_2063 : node _T_2064 = shl(UInt<5>(0h15), 3) node _T_2065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2064) connect Queue10_UInt8_14.io.enq.bits, _T_2065 node _T_2066 = eq(UInt<4>(0hf), idx_21) when _T_2066 : node _T_2067 = shl(UInt<5>(0h15), 3) node _T_2068 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2067) connect Queue10_UInt8_15.io.enq.bits, _T_2068 node _T_2069 = eq(UInt<5>(0h10), idx_21) when _T_2069 : node _T_2070 = shl(UInt<5>(0h15), 3) node _T_2071 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2070) connect Queue10_UInt8_16.io.enq.bits, _T_2071 node _T_2072 = eq(UInt<5>(0h11), idx_21) when _T_2072 : node _T_2073 = shl(UInt<5>(0h15), 3) node _T_2074 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2073) connect Queue10_UInt8_17.io.enq.bits, _T_2074 node _T_2075 = eq(UInt<5>(0h12), idx_21) when _T_2075 : node _T_2076 = shl(UInt<5>(0h15), 3) node _T_2077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2076) connect Queue10_UInt8_18.io.enq.bits, _T_2077 node _T_2078 = eq(UInt<5>(0h13), idx_21) when _T_2078 : node _T_2079 = shl(UInt<5>(0h15), 3) node _T_2080 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2079) connect Queue10_UInt8_19.io.enq.bits, _T_2080 node _T_2081 = eq(UInt<5>(0h14), idx_21) when _T_2081 : node _T_2082 = shl(UInt<5>(0h15), 3) node _T_2083 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2082) connect Queue10_UInt8_20.io.enq.bits, _T_2083 node _T_2084 = eq(UInt<5>(0h15), idx_21) when _T_2084 : node _T_2085 = shl(UInt<5>(0h15), 3) node _T_2086 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2085) connect Queue10_UInt8_21.io.enq.bits, _T_2086 node _T_2087 = eq(UInt<5>(0h16), idx_21) when _T_2087 : node _T_2088 = shl(UInt<5>(0h15), 3) node _T_2089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2088) connect Queue10_UInt8_22.io.enq.bits, _T_2089 node _T_2090 = eq(UInt<5>(0h17), idx_21) when _T_2090 : node _T_2091 = shl(UInt<5>(0h15), 3) node _T_2092 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2091) connect Queue10_UInt8_23.io.enq.bits, _T_2092 node _T_2093 = eq(UInt<5>(0h18), idx_21) when _T_2093 : node _T_2094 = shl(UInt<5>(0h15), 3) node _T_2095 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2094) connect Queue10_UInt8_24.io.enq.bits, _T_2095 node _T_2096 = eq(UInt<5>(0h19), idx_21) when _T_2096 : node _T_2097 = shl(UInt<5>(0h15), 3) node _T_2098 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2097) connect Queue10_UInt8_25.io.enq.bits, _T_2098 node _T_2099 = eq(UInt<5>(0h1a), idx_21) when _T_2099 : node _T_2100 = shl(UInt<5>(0h15), 3) node _T_2101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2100) connect Queue10_UInt8_26.io.enq.bits, _T_2101 node _T_2102 = eq(UInt<5>(0h1b), idx_21) when _T_2102 : node _T_2103 = shl(UInt<5>(0h15), 3) node _T_2104 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2103) connect Queue10_UInt8_27.io.enq.bits, _T_2104 node _T_2105 = eq(UInt<5>(0h1c), idx_21) when _T_2105 : node _T_2106 = shl(UInt<5>(0h15), 3) node _T_2107 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2106) connect Queue10_UInt8_28.io.enq.bits, _T_2107 node _T_2108 = eq(UInt<5>(0h1d), idx_21) when _T_2108 : node _T_2109 = shl(UInt<5>(0h15), 3) node _T_2110 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2109) connect Queue10_UInt8_29.io.enq.bits, _T_2110 node _T_2111 = eq(UInt<5>(0h1e), idx_21) when _T_2111 : node _T_2112 = shl(UInt<5>(0h15), 3) node _T_2113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2112) connect Queue10_UInt8_30.io.enq.bits, _T_2113 node _T_2114 = eq(UInt<5>(0h1f), idx_21) when _T_2114 : node _T_2115 = shl(UInt<5>(0h15), 3) node _T_2116 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2115) connect Queue10_UInt8_31.io.enq.bits, _T_2116 node _idx_T_22 = add(write_start_index, UInt<5>(0h16)) node idx_22 = rem(_idx_T_22, UInt<6>(0h20)) node _T_2117 = eq(UInt<1>(0h0), idx_22) when _T_2117 : node _T_2118 = shl(UInt<5>(0h16), 3) node _T_2119 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2118) connect Queue10_UInt8.io.enq.bits, _T_2119 node _T_2120 = eq(UInt<1>(0h1), idx_22) when _T_2120 : node _T_2121 = shl(UInt<5>(0h16), 3) node _T_2122 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2121) connect Queue10_UInt8_1.io.enq.bits, _T_2122 node _T_2123 = eq(UInt<2>(0h2), idx_22) when _T_2123 : node _T_2124 = shl(UInt<5>(0h16), 3) node _T_2125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2124) connect Queue10_UInt8_2.io.enq.bits, _T_2125 node _T_2126 = eq(UInt<2>(0h3), idx_22) when _T_2126 : node _T_2127 = shl(UInt<5>(0h16), 3) node _T_2128 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2127) connect Queue10_UInt8_3.io.enq.bits, _T_2128 node _T_2129 = eq(UInt<3>(0h4), idx_22) when _T_2129 : node _T_2130 = shl(UInt<5>(0h16), 3) node _T_2131 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2130) connect Queue10_UInt8_4.io.enq.bits, _T_2131 node _T_2132 = eq(UInt<3>(0h5), idx_22) when _T_2132 : node _T_2133 = shl(UInt<5>(0h16), 3) node _T_2134 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2133) connect Queue10_UInt8_5.io.enq.bits, _T_2134 node _T_2135 = eq(UInt<3>(0h6), idx_22) when _T_2135 : node _T_2136 = shl(UInt<5>(0h16), 3) node _T_2137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2136) connect Queue10_UInt8_6.io.enq.bits, _T_2137 node _T_2138 = eq(UInt<3>(0h7), idx_22) when _T_2138 : node _T_2139 = shl(UInt<5>(0h16), 3) node _T_2140 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2139) connect Queue10_UInt8_7.io.enq.bits, _T_2140 node _T_2141 = eq(UInt<4>(0h8), idx_22) when _T_2141 : node _T_2142 = shl(UInt<5>(0h16), 3) node _T_2143 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2142) connect Queue10_UInt8_8.io.enq.bits, _T_2143 node _T_2144 = eq(UInt<4>(0h9), idx_22) when _T_2144 : node _T_2145 = shl(UInt<5>(0h16), 3) node _T_2146 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2145) connect Queue10_UInt8_9.io.enq.bits, _T_2146 node _T_2147 = eq(UInt<4>(0ha), idx_22) when _T_2147 : node _T_2148 = shl(UInt<5>(0h16), 3) node _T_2149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2148) connect Queue10_UInt8_10.io.enq.bits, _T_2149 node _T_2150 = eq(UInt<4>(0hb), idx_22) when _T_2150 : node _T_2151 = shl(UInt<5>(0h16), 3) node _T_2152 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2151) connect Queue10_UInt8_11.io.enq.bits, _T_2152 node _T_2153 = eq(UInt<4>(0hc), idx_22) when _T_2153 : node _T_2154 = shl(UInt<5>(0h16), 3) node _T_2155 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2154) connect Queue10_UInt8_12.io.enq.bits, _T_2155 node _T_2156 = eq(UInt<4>(0hd), idx_22) when _T_2156 : node _T_2157 = shl(UInt<5>(0h16), 3) node _T_2158 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2157) connect Queue10_UInt8_13.io.enq.bits, _T_2158 node _T_2159 = eq(UInt<4>(0he), idx_22) when _T_2159 : node _T_2160 = shl(UInt<5>(0h16), 3) node _T_2161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2160) connect Queue10_UInt8_14.io.enq.bits, _T_2161 node _T_2162 = eq(UInt<4>(0hf), idx_22) when _T_2162 : node _T_2163 = shl(UInt<5>(0h16), 3) node _T_2164 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2163) connect Queue10_UInt8_15.io.enq.bits, _T_2164 node _T_2165 = eq(UInt<5>(0h10), idx_22) when _T_2165 : node _T_2166 = shl(UInt<5>(0h16), 3) node _T_2167 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2166) connect Queue10_UInt8_16.io.enq.bits, _T_2167 node _T_2168 = eq(UInt<5>(0h11), idx_22) when _T_2168 : node _T_2169 = shl(UInt<5>(0h16), 3) node _T_2170 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2169) connect Queue10_UInt8_17.io.enq.bits, _T_2170 node _T_2171 = eq(UInt<5>(0h12), idx_22) when _T_2171 : node _T_2172 = shl(UInt<5>(0h16), 3) node _T_2173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2172) connect Queue10_UInt8_18.io.enq.bits, _T_2173 node _T_2174 = eq(UInt<5>(0h13), idx_22) when _T_2174 : node _T_2175 = shl(UInt<5>(0h16), 3) node _T_2176 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2175) connect Queue10_UInt8_19.io.enq.bits, _T_2176 node _T_2177 = eq(UInt<5>(0h14), idx_22) when _T_2177 : node _T_2178 = shl(UInt<5>(0h16), 3) node _T_2179 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2178) connect Queue10_UInt8_20.io.enq.bits, _T_2179 node _T_2180 = eq(UInt<5>(0h15), idx_22) when _T_2180 : node _T_2181 = shl(UInt<5>(0h16), 3) node _T_2182 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2181) connect Queue10_UInt8_21.io.enq.bits, _T_2182 node _T_2183 = eq(UInt<5>(0h16), idx_22) when _T_2183 : node _T_2184 = shl(UInt<5>(0h16), 3) node _T_2185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2184) connect Queue10_UInt8_22.io.enq.bits, _T_2185 node _T_2186 = eq(UInt<5>(0h17), idx_22) when _T_2186 : node _T_2187 = shl(UInt<5>(0h16), 3) node _T_2188 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2187) connect Queue10_UInt8_23.io.enq.bits, _T_2188 node _T_2189 = eq(UInt<5>(0h18), idx_22) when _T_2189 : node _T_2190 = shl(UInt<5>(0h16), 3) node _T_2191 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2190) connect Queue10_UInt8_24.io.enq.bits, _T_2191 node _T_2192 = eq(UInt<5>(0h19), idx_22) when _T_2192 : node _T_2193 = shl(UInt<5>(0h16), 3) node _T_2194 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2193) connect Queue10_UInt8_25.io.enq.bits, _T_2194 node _T_2195 = eq(UInt<5>(0h1a), idx_22) when _T_2195 : node _T_2196 = shl(UInt<5>(0h16), 3) node _T_2197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2196) connect Queue10_UInt8_26.io.enq.bits, _T_2197 node _T_2198 = eq(UInt<5>(0h1b), idx_22) when _T_2198 : node _T_2199 = shl(UInt<5>(0h16), 3) node _T_2200 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2199) connect Queue10_UInt8_27.io.enq.bits, _T_2200 node _T_2201 = eq(UInt<5>(0h1c), idx_22) when _T_2201 : node _T_2202 = shl(UInt<5>(0h16), 3) node _T_2203 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2202) connect Queue10_UInt8_28.io.enq.bits, _T_2203 node _T_2204 = eq(UInt<5>(0h1d), idx_22) when _T_2204 : node _T_2205 = shl(UInt<5>(0h16), 3) node _T_2206 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2205) connect Queue10_UInt8_29.io.enq.bits, _T_2206 node _T_2207 = eq(UInt<5>(0h1e), idx_22) when _T_2207 : node _T_2208 = shl(UInt<5>(0h16), 3) node _T_2209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2208) connect Queue10_UInt8_30.io.enq.bits, _T_2209 node _T_2210 = eq(UInt<5>(0h1f), idx_22) when _T_2210 : node _T_2211 = shl(UInt<5>(0h16), 3) node _T_2212 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2211) connect Queue10_UInt8_31.io.enq.bits, _T_2212 node _idx_T_23 = add(write_start_index, UInt<5>(0h17)) node idx_23 = rem(_idx_T_23, UInt<6>(0h20)) node _T_2213 = eq(UInt<1>(0h0), idx_23) when _T_2213 : node _T_2214 = shl(UInt<5>(0h17), 3) node _T_2215 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2214) connect Queue10_UInt8.io.enq.bits, _T_2215 node _T_2216 = eq(UInt<1>(0h1), idx_23) when _T_2216 : node _T_2217 = shl(UInt<5>(0h17), 3) node _T_2218 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2217) connect Queue10_UInt8_1.io.enq.bits, _T_2218 node _T_2219 = eq(UInt<2>(0h2), idx_23) when _T_2219 : node _T_2220 = shl(UInt<5>(0h17), 3) node _T_2221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2220) connect Queue10_UInt8_2.io.enq.bits, _T_2221 node _T_2222 = eq(UInt<2>(0h3), idx_23) when _T_2222 : node _T_2223 = shl(UInt<5>(0h17), 3) node _T_2224 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2223) connect Queue10_UInt8_3.io.enq.bits, _T_2224 node _T_2225 = eq(UInt<3>(0h4), idx_23) when _T_2225 : node _T_2226 = shl(UInt<5>(0h17), 3) node _T_2227 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2226) connect Queue10_UInt8_4.io.enq.bits, _T_2227 node _T_2228 = eq(UInt<3>(0h5), idx_23) when _T_2228 : node _T_2229 = shl(UInt<5>(0h17), 3) node _T_2230 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2229) connect Queue10_UInt8_5.io.enq.bits, _T_2230 node _T_2231 = eq(UInt<3>(0h6), idx_23) when _T_2231 : node _T_2232 = shl(UInt<5>(0h17), 3) node _T_2233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2232) connect Queue10_UInt8_6.io.enq.bits, _T_2233 node _T_2234 = eq(UInt<3>(0h7), idx_23) when _T_2234 : node _T_2235 = shl(UInt<5>(0h17), 3) node _T_2236 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2235) connect Queue10_UInt8_7.io.enq.bits, _T_2236 node _T_2237 = eq(UInt<4>(0h8), idx_23) when _T_2237 : node _T_2238 = shl(UInt<5>(0h17), 3) node _T_2239 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2238) connect Queue10_UInt8_8.io.enq.bits, _T_2239 node _T_2240 = eq(UInt<4>(0h9), idx_23) when _T_2240 : node _T_2241 = shl(UInt<5>(0h17), 3) node _T_2242 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2241) connect Queue10_UInt8_9.io.enq.bits, _T_2242 node _T_2243 = eq(UInt<4>(0ha), idx_23) when _T_2243 : node _T_2244 = shl(UInt<5>(0h17), 3) node _T_2245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2244) connect Queue10_UInt8_10.io.enq.bits, _T_2245 node _T_2246 = eq(UInt<4>(0hb), idx_23) when _T_2246 : node _T_2247 = shl(UInt<5>(0h17), 3) node _T_2248 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2247) connect Queue10_UInt8_11.io.enq.bits, _T_2248 node _T_2249 = eq(UInt<4>(0hc), idx_23) when _T_2249 : node _T_2250 = shl(UInt<5>(0h17), 3) node _T_2251 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2250) connect Queue10_UInt8_12.io.enq.bits, _T_2251 node _T_2252 = eq(UInt<4>(0hd), idx_23) when _T_2252 : node _T_2253 = shl(UInt<5>(0h17), 3) node _T_2254 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2253) connect Queue10_UInt8_13.io.enq.bits, _T_2254 node _T_2255 = eq(UInt<4>(0he), idx_23) when _T_2255 : node _T_2256 = shl(UInt<5>(0h17), 3) node _T_2257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2256) connect Queue10_UInt8_14.io.enq.bits, _T_2257 node _T_2258 = eq(UInt<4>(0hf), idx_23) when _T_2258 : node _T_2259 = shl(UInt<5>(0h17), 3) node _T_2260 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2259) connect Queue10_UInt8_15.io.enq.bits, _T_2260 node _T_2261 = eq(UInt<5>(0h10), idx_23) when _T_2261 : node _T_2262 = shl(UInt<5>(0h17), 3) node _T_2263 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2262) connect Queue10_UInt8_16.io.enq.bits, _T_2263 node _T_2264 = eq(UInt<5>(0h11), idx_23) when _T_2264 : node _T_2265 = shl(UInt<5>(0h17), 3) node _T_2266 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2265) connect Queue10_UInt8_17.io.enq.bits, _T_2266 node _T_2267 = eq(UInt<5>(0h12), idx_23) when _T_2267 : node _T_2268 = shl(UInt<5>(0h17), 3) node _T_2269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2268) connect Queue10_UInt8_18.io.enq.bits, _T_2269 node _T_2270 = eq(UInt<5>(0h13), idx_23) when _T_2270 : node _T_2271 = shl(UInt<5>(0h17), 3) node _T_2272 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2271) connect Queue10_UInt8_19.io.enq.bits, _T_2272 node _T_2273 = eq(UInt<5>(0h14), idx_23) when _T_2273 : node _T_2274 = shl(UInt<5>(0h17), 3) node _T_2275 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2274) connect Queue10_UInt8_20.io.enq.bits, _T_2275 node _T_2276 = eq(UInt<5>(0h15), idx_23) when _T_2276 : node _T_2277 = shl(UInt<5>(0h17), 3) node _T_2278 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2277) connect Queue10_UInt8_21.io.enq.bits, _T_2278 node _T_2279 = eq(UInt<5>(0h16), idx_23) when _T_2279 : node _T_2280 = shl(UInt<5>(0h17), 3) node _T_2281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2280) connect Queue10_UInt8_22.io.enq.bits, _T_2281 node _T_2282 = eq(UInt<5>(0h17), idx_23) when _T_2282 : node _T_2283 = shl(UInt<5>(0h17), 3) node _T_2284 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2283) connect Queue10_UInt8_23.io.enq.bits, _T_2284 node _T_2285 = eq(UInt<5>(0h18), idx_23) when _T_2285 : node _T_2286 = shl(UInt<5>(0h17), 3) node _T_2287 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2286) connect Queue10_UInt8_24.io.enq.bits, _T_2287 node _T_2288 = eq(UInt<5>(0h19), idx_23) when _T_2288 : node _T_2289 = shl(UInt<5>(0h17), 3) node _T_2290 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2289) connect Queue10_UInt8_25.io.enq.bits, _T_2290 node _T_2291 = eq(UInt<5>(0h1a), idx_23) when _T_2291 : node _T_2292 = shl(UInt<5>(0h17), 3) node _T_2293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2292) connect Queue10_UInt8_26.io.enq.bits, _T_2293 node _T_2294 = eq(UInt<5>(0h1b), idx_23) when _T_2294 : node _T_2295 = shl(UInt<5>(0h17), 3) node _T_2296 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2295) connect Queue10_UInt8_27.io.enq.bits, _T_2296 node _T_2297 = eq(UInt<5>(0h1c), idx_23) when _T_2297 : node _T_2298 = shl(UInt<5>(0h17), 3) node _T_2299 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2298) connect Queue10_UInt8_28.io.enq.bits, _T_2299 node _T_2300 = eq(UInt<5>(0h1d), idx_23) when _T_2300 : node _T_2301 = shl(UInt<5>(0h17), 3) node _T_2302 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2301) connect Queue10_UInt8_29.io.enq.bits, _T_2302 node _T_2303 = eq(UInt<5>(0h1e), idx_23) when _T_2303 : node _T_2304 = shl(UInt<5>(0h17), 3) node _T_2305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2304) connect Queue10_UInt8_30.io.enq.bits, _T_2305 node _T_2306 = eq(UInt<5>(0h1f), idx_23) when _T_2306 : node _T_2307 = shl(UInt<5>(0h17), 3) node _T_2308 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2307) connect Queue10_UInt8_31.io.enq.bits, _T_2308 node _idx_T_24 = add(write_start_index, UInt<5>(0h18)) node idx_24 = rem(_idx_T_24, UInt<6>(0h20)) node _T_2309 = eq(UInt<1>(0h0), idx_24) when _T_2309 : node _T_2310 = shl(UInt<5>(0h18), 3) node _T_2311 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2310) connect Queue10_UInt8.io.enq.bits, _T_2311 node _T_2312 = eq(UInt<1>(0h1), idx_24) when _T_2312 : node _T_2313 = shl(UInt<5>(0h18), 3) node _T_2314 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2313) connect Queue10_UInt8_1.io.enq.bits, _T_2314 node _T_2315 = eq(UInt<2>(0h2), idx_24) when _T_2315 : node _T_2316 = shl(UInt<5>(0h18), 3) node _T_2317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2316) connect Queue10_UInt8_2.io.enq.bits, _T_2317 node _T_2318 = eq(UInt<2>(0h3), idx_24) when _T_2318 : node _T_2319 = shl(UInt<5>(0h18), 3) node _T_2320 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2319) connect Queue10_UInt8_3.io.enq.bits, _T_2320 node _T_2321 = eq(UInt<3>(0h4), idx_24) when _T_2321 : node _T_2322 = shl(UInt<5>(0h18), 3) node _T_2323 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2322) connect Queue10_UInt8_4.io.enq.bits, _T_2323 node _T_2324 = eq(UInt<3>(0h5), idx_24) when _T_2324 : node _T_2325 = shl(UInt<5>(0h18), 3) node _T_2326 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2325) connect Queue10_UInt8_5.io.enq.bits, _T_2326 node _T_2327 = eq(UInt<3>(0h6), idx_24) when _T_2327 : node _T_2328 = shl(UInt<5>(0h18), 3) node _T_2329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2328) connect Queue10_UInt8_6.io.enq.bits, _T_2329 node _T_2330 = eq(UInt<3>(0h7), idx_24) when _T_2330 : node _T_2331 = shl(UInt<5>(0h18), 3) node _T_2332 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2331) connect Queue10_UInt8_7.io.enq.bits, _T_2332 node _T_2333 = eq(UInt<4>(0h8), idx_24) when _T_2333 : node _T_2334 = shl(UInt<5>(0h18), 3) node _T_2335 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2334) connect Queue10_UInt8_8.io.enq.bits, _T_2335 node _T_2336 = eq(UInt<4>(0h9), idx_24) when _T_2336 : node _T_2337 = shl(UInt<5>(0h18), 3) node _T_2338 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2337) connect Queue10_UInt8_9.io.enq.bits, _T_2338 node _T_2339 = eq(UInt<4>(0ha), idx_24) when _T_2339 : node _T_2340 = shl(UInt<5>(0h18), 3) node _T_2341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2340) connect Queue10_UInt8_10.io.enq.bits, _T_2341 node _T_2342 = eq(UInt<4>(0hb), idx_24) when _T_2342 : node _T_2343 = shl(UInt<5>(0h18), 3) node _T_2344 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2343) connect Queue10_UInt8_11.io.enq.bits, _T_2344 node _T_2345 = eq(UInt<4>(0hc), idx_24) when _T_2345 : node _T_2346 = shl(UInt<5>(0h18), 3) node _T_2347 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2346) connect Queue10_UInt8_12.io.enq.bits, _T_2347 node _T_2348 = eq(UInt<4>(0hd), idx_24) when _T_2348 : node _T_2349 = shl(UInt<5>(0h18), 3) node _T_2350 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2349) connect Queue10_UInt8_13.io.enq.bits, _T_2350 node _T_2351 = eq(UInt<4>(0he), idx_24) when _T_2351 : node _T_2352 = shl(UInt<5>(0h18), 3) node _T_2353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2352) connect Queue10_UInt8_14.io.enq.bits, _T_2353 node _T_2354 = eq(UInt<4>(0hf), idx_24) when _T_2354 : node _T_2355 = shl(UInt<5>(0h18), 3) node _T_2356 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2355) connect Queue10_UInt8_15.io.enq.bits, _T_2356 node _T_2357 = eq(UInt<5>(0h10), idx_24) when _T_2357 : node _T_2358 = shl(UInt<5>(0h18), 3) node _T_2359 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2358) connect Queue10_UInt8_16.io.enq.bits, _T_2359 node _T_2360 = eq(UInt<5>(0h11), idx_24) when _T_2360 : node _T_2361 = shl(UInt<5>(0h18), 3) node _T_2362 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2361) connect Queue10_UInt8_17.io.enq.bits, _T_2362 node _T_2363 = eq(UInt<5>(0h12), idx_24) when _T_2363 : node _T_2364 = shl(UInt<5>(0h18), 3) node _T_2365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2364) connect Queue10_UInt8_18.io.enq.bits, _T_2365 node _T_2366 = eq(UInt<5>(0h13), idx_24) when _T_2366 : node _T_2367 = shl(UInt<5>(0h18), 3) node _T_2368 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2367) connect Queue10_UInt8_19.io.enq.bits, _T_2368 node _T_2369 = eq(UInt<5>(0h14), idx_24) when _T_2369 : node _T_2370 = shl(UInt<5>(0h18), 3) node _T_2371 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2370) connect Queue10_UInt8_20.io.enq.bits, _T_2371 node _T_2372 = eq(UInt<5>(0h15), idx_24) when _T_2372 : node _T_2373 = shl(UInt<5>(0h18), 3) node _T_2374 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2373) connect Queue10_UInt8_21.io.enq.bits, _T_2374 node _T_2375 = eq(UInt<5>(0h16), idx_24) when _T_2375 : node _T_2376 = shl(UInt<5>(0h18), 3) node _T_2377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2376) connect Queue10_UInt8_22.io.enq.bits, _T_2377 node _T_2378 = eq(UInt<5>(0h17), idx_24) when _T_2378 : node _T_2379 = shl(UInt<5>(0h18), 3) node _T_2380 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2379) connect Queue10_UInt8_23.io.enq.bits, _T_2380 node _T_2381 = eq(UInt<5>(0h18), idx_24) when _T_2381 : node _T_2382 = shl(UInt<5>(0h18), 3) node _T_2383 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2382) connect Queue10_UInt8_24.io.enq.bits, _T_2383 node _T_2384 = eq(UInt<5>(0h19), idx_24) when _T_2384 : node _T_2385 = shl(UInt<5>(0h18), 3) node _T_2386 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2385) connect Queue10_UInt8_25.io.enq.bits, _T_2386 node _T_2387 = eq(UInt<5>(0h1a), idx_24) when _T_2387 : node _T_2388 = shl(UInt<5>(0h18), 3) node _T_2389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2388) connect Queue10_UInt8_26.io.enq.bits, _T_2389 node _T_2390 = eq(UInt<5>(0h1b), idx_24) when _T_2390 : node _T_2391 = shl(UInt<5>(0h18), 3) node _T_2392 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2391) connect Queue10_UInt8_27.io.enq.bits, _T_2392 node _T_2393 = eq(UInt<5>(0h1c), idx_24) when _T_2393 : node _T_2394 = shl(UInt<5>(0h18), 3) node _T_2395 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2394) connect Queue10_UInt8_28.io.enq.bits, _T_2395 node _T_2396 = eq(UInt<5>(0h1d), idx_24) when _T_2396 : node _T_2397 = shl(UInt<5>(0h18), 3) node _T_2398 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2397) connect Queue10_UInt8_29.io.enq.bits, _T_2398 node _T_2399 = eq(UInt<5>(0h1e), idx_24) when _T_2399 : node _T_2400 = shl(UInt<5>(0h18), 3) node _T_2401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2400) connect Queue10_UInt8_30.io.enq.bits, _T_2401 node _T_2402 = eq(UInt<5>(0h1f), idx_24) when _T_2402 : node _T_2403 = shl(UInt<5>(0h18), 3) node _T_2404 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2403) connect Queue10_UInt8_31.io.enq.bits, _T_2404 node _idx_T_25 = add(write_start_index, UInt<5>(0h19)) node idx_25 = rem(_idx_T_25, UInt<6>(0h20)) node _T_2405 = eq(UInt<1>(0h0), idx_25) when _T_2405 : node _T_2406 = shl(UInt<5>(0h19), 3) node _T_2407 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2406) connect Queue10_UInt8.io.enq.bits, _T_2407 node _T_2408 = eq(UInt<1>(0h1), idx_25) when _T_2408 : node _T_2409 = shl(UInt<5>(0h19), 3) node _T_2410 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2409) connect Queue10_UInt8_1.io.enq.bits, _T_2410 node _T_2411 = eq(UInt<2>(0h2), idx_25) when _T_2411 : node _T_2412 = shl(UInt<5>(0h19), 3) node _T_2413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2412) connect Queue10_UInt8_2.io.enq.bits, _T_2413 node _T_2414 = eq(UInt<2>(0h3), idx_25) when _T_2414 : node _T_2415 = shl(UInt<5>(0h19), 3) node _T_2416 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2415) connect Queue10_UInt8_3.io.enq.bits, _T_2416 node _T_2417 = eq(UInt<3>(0h4), idx_25) when _T_2417 : node _T_2418 = shl(UInt<5>(0h19), 3) node _T_2419 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2418) connect Queue10_UInt8_4.io.enq.bits, _T_2419 node _T_2420 = eq(UInt<3>(0h5), idx_25) when _T_2420 : node _T_2421 = shl(UInt<5>(0h19), 3) node _T_2422 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2421) connect Queue10_UInt8_5.io.enq.bits, _T_2422 node _T_2423 = eq(UInt<3>(0h6), idx_25) when _T_2423 : node _T_2424 = shl(UInt<5>(0h19), 3) node _T_2425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2424) connect Queue10_UInt8_6.io.enq.bits, _T_2425 node _T_2426 = eq(UInt<3>(0h7), idx_25) when _T_2426 : node _T_2427 = shl(UInt<5>(0h19), 3) node _T_2428 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2427) connect Queue10_UInt8_7.io.enq.bits, _T_2428 node _T_2429 = eq(UInt<4>(0h8), idx_25) when _T_2429 : node _T_2430 = shl(UInt<5>(0h19), 3) node _T_2431 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2430) connect Queue10_UInt8_8.io.enq.bits, _T_2431 node _T_2432 = eq(UInt<4>(0h9), idx_25) when _T_2432 : node _T_2433 = shl(UInt<5>(0h19), 3) node _T_2434 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2433) connect Queue10_UInt8_9.io.enq.bits, _T_2434 node _T_2435 = eq(UInt<4>(0ha), idx_25) when _T_2435 : node _T_2436 = shl(UInt<5>(0h19), 3) node _T_2437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2436) connect Queue10_UInt8_10.io.enq.bits, _T_2437 node _T_2438 = eq(UInt<4>(0hb), idx_25) when _T_2438 : node _T_2439 = shl(UInt<5>(0h19), 3) node _T_2440 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2439) connect Queue10_UInt8_11.io.enq.bits, _T_2440 node _T_2441 = eq(UInt<4>(0hc), idx_25) when _T_2441 : node _T_2442 = shl(UInt<5>(0h19), 3) node _T_2443 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2442) connect Queue10_UInt8_12.io.enq.bits, _T_2443 node _T_2444 = eq(UInt<4>(0hd), idx_25) when _T_2444 : node _T_2445 = shl(UInt<5>(0h19), 3) node _T_2446 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2445) connect Queue10_UInt8_13.io.enq.bits, _T_2446 node _T_2447 = eq(UInt<4>(0he), idx_25) when _T_2447 : node _T_2448 = shl(UInt<5>(0h19), 3) node _T_2449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2448) connect Queue10_UInt8_14.io.enq.bits, _T_2449 node _T_2450 = eq(UInt<4>(0hf), idx_25) when _T_2450 : node _T_2451 = shl(UInt<5>(0h19), 3) node _T_2452 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2451) connect Queue10_UInt8_15.io.enq.bits, _T_2452 node _T_2453 = eq(UInt<5>(0h10), idx_25) when _T_2453 : node _T_2454 = shl(UInt<5>(0h19), 3) node _T_2455 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2454) connect Queue10_UInt8_16.io.enq.bits, _T_2455 node _T_2456 = eq(UInt<5>(0h11), idx_25) when _T_2456 : node _T_2457 = shl(UInt<5>(0h19), 3) node _T_2458 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2457) connect Queue10_UInt8_17.io.enq.bits, _T_2458 node _T_2459 = eq(UInt<5>(0h12), idx_25) when _T_2459 : node _T_2460 = shl(UInt<5>(0h19), 3) node _T_2461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2460) connect Queue10_UInt8_18.io.enq.bits, _T_2461 node _T_2462 = eq(UInt<5>(0h13), idx_25) when _T_2462 : node _T_2463 = shl(UInt<5>(0h19), 3) node _T_2464 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2463) connect Queue10_UInt8_19.io.enq.bits, _T_2464 node _T_2465 = eq(UInt<5>(0h14), idx_25) when _T_2465 : node _T_2466 = shl(UInt<5>(0h19), 3) node _T_2467 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2466) connect Queue10_UInt8_20.io.enq.bits, _T_2467 node _T_2468 = eq(UInt<5>(0h15), idx_25) when _T_2468 : node _T_2469 = shl(UInt<5>(0h19), 3) node _T_2470 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2469) connect Queue10_UInt8_21.io.enq.bits, _T_2470 node _T_2471 = eq(UInt<5>(0h16), idx_25) when _T_2471 : node _T_2472 = shl(UInt<5>(0h19), 3) node _T_2473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2472) connect Queue10_UInt8_22.io.enq.bits, _T_2473 node _T_2474 = eq(UInt<5>(0h17), idx_25) when _T_2474 : node _T_2475 = shl(UInt<5>(0h19), 3) node _T_2476 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2475) connect Queue10_UInt8_23.io.enq.bits, _T_2476 node _T_2477 = eq(UInt<5>(0h18), idx_25) when _T_2477 : node _T_2478 = shl(UInt<5>(0h19), 3) node _T_2479 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2478) connect Queue10_UInt8_24.io.enq.bits, _T_2479 node _T_2480 = eq(UInt<5>(0h19), idx_25) when _T_2480 : node _T_2481 = shl(UInt<5>(0h19), 3) node _T_2482 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2481) connect Queue10_UInt8_25.io.enq.bits, _T_2482 node _T_2483 = eq(UInt<5>(0h1a), idx_25) when _T_2483 : node _T_2484 = shl(UInt<5>(0h19), 3) node _T_2485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2484) connect Queue10_UInt8_26.io.enq.bits, _T_2485 node _T_2486 = eq(UInt<5>(0h1b), idx_25) when _T_2486 : node _T_2487 = shl(UInt<5>(0h19), 3) node _T_2488 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2487) connect Queue10_UInt8_27.io.enq.bits, _T_2488 node _T_2489 = eq(UInt<5>(0h1c), idx_25) when _T_2489 : node _T_2490 = shl(UInt<5>(0h19), 3) node _T_2491 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2490) connect Queue10_UInt8_28.io.enq.bits, _T_2491 node _T_2492 = eq(UInt<5>(0h1d), idx_25) when _T_2492 : node _T_2493 = shl(UInt<5>(0h19), 3) node _T_2494 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2493) connect Queue10_UInt8_29.io.enq.bits, _T_2494 node _T_2495 = eq(UInt<5>(0h1e), idx_25) when _T_2495 : node _T_2496 = shl(UInt<5>(0h19), 3) node _T_2497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2496) connect Queue10_UInt8_30.io.enq.bits, _T_2497 node _T_2498 = eq(UInt<5>(0h1f), idx_25) when _T_2498 : node _T_2499 = shl(UInt<5>(0h19), 3) node _T_2500 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2499) connect Queue10_UInt8_31.io.enq.bits, _T_2500 node _idx_T_26 = add(write_start_index, UInt<5>(0h1a)) node idx_26 = rem(_idx_T_26, UInt<6>(0h20)) node _T_2501 = eq(UInt<1>(0h0), idx_26) when _T_2501 : node _T_2502 = shl(UInt<5>(0h1a), 3) node _T_2503 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2502) connect Queue10_UInt8.io.enq.bits, _T_2503 node _T_2504 = eq(UInt<1>(0h1), idx_26) when _T_2504 : node _T_2505 = shl(UInt<5>(0h1a), 3) node _T_2506 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2505) connect Queue10_UInt8_1.io.enq.bits, _T_2506 node _T_2507 = eq(UInt<2>(0h2), idx_26) when _T_2507 : node _T_2508 = shl(UInt<5>(0h1a), 3) node _T_2509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2508) connect Queue10_UInt8_2.io.enq.bits, _T_2509 node _T_2510 = eq(UInt<2>(0h3), idx_26) when _T_2510 : node _T_2511 = shl(UInt<5>(0h1a), 3) node _T_2512 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2511) connect Queue10_UInt8_3.io.enq.bits, _T_2512 node _T_2513 = eq(UInt<3>(0h4), idx_26) when _T_2513 : node _T_2514 = shl(UInt<5>(0h1a), 3) node _T_2515 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2514) connect Queue10_UInt8_4.io.enq.bits, _T_2515 node _T_2516 = eq(UInt<3>(0h5), idx_26) when _T_2516 : node _T_2517 = shl(UInt<5>(0h1a), 3) node _T_2518 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2517) connect Queue10_UInt8_5.io.enq.bits, _T_2518 node _T_2519 = eq(UInt<3>(0h6), idx_26) when _T_2519 : node _T_2520 = shl(UInt<5>(0h1a), 3) node _T_2521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2520) connect Queue10_UInt8_6.io.enq.bits, _T_2521 node _T_2522 = eq(UInt<3>(0h7), idx_26) when _T_2522 : node _T_2523 = shl(UInt<5>(0h1a), 3) node _T_2524 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2523) connect Queue10_UInt8_7.io.enq.bits, _T_2524 node _T_2525 = eq(UInt<4>(0h8), idx_26) when _T_2525 : node _T_2526 = shl(UInt<5>(0h1a), 3) node _T_2527 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2526) connect Queue10_UInt8_8.io.enq.bits, _T_2527 node _T_2528 = eq(UInt<4>(0h9), idx_26) when _T_2528 : node _T_2529 = shl(UInt<5>(0h1a), 3) node _T_2530 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2529) connect Queue10_UInt8_9.io.enq.bits, _T_2530 node _T_2531 = eq(UInt<4>(0ha), idx_26) when _T_2531 : node _T_2532 = shl(UInt<5>(0h1a), 3) node _T_2533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2532) connect Queue10_UInt8_10.io.enq.bits, _T_2533 node _T_2534 = eq(UInt<4>(0hb), idx_26) when _T_2534 : node _T_2535 = shl(UInt<5>(0h1a), 3) node _T_2536 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2535) connect Queue10_UInt8_11.io.enq.bits, _T_2536 node _T_2537 = eq(UInt<4>(0hc), idx_26) when _T_2537 : node _T_2538 = shl(UInt<5>(0h1a), 3) node _T_2539 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2538) connect Queue10_UInt8_12.io.enq.bits, _T_2539 node _T_2540 = eq(UInt<4>(0hd), idx_26) when _T_2540 : node _T_2541 = shl(UInt<5>(0h1a), 3) node _T_2542 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2541) connect Queue10_UInt8_13.io.enq.bits, _T_2542 node _T_2543 = eq(UInt<4>(0he), idx_26) when _T_2543 : node _T_2544 = shl(UInt<5>(0h1a), 3) node _T_2545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2544) connect Queue10_UInt8_14.io.enq.bits, _T_2545 node _T_2546 = eq(UInt<4>(0hf), idx_26) when _T_2546 : node _T_2547 = shl(UInt<5>(0h1a), 3) node _T_2548 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2547) connect Queue10_UInt8_15.io.enq.bits, _T_2548 node _T_2549 = eq(UInt<5>(0h10), idx_26) when _T_2549 : node _T_2550 = shl(UInt<5>(0h1a), 3) node _T_2551 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2550) connect Queue10_UInt8_16.io.enq.bits, _T_2551 node _T_2552 = eq(UInt<5>(0h11), idx_26) when _T_2552 : node _T_2553 = shl(UInt<5>(0h1a), 3) node _T_2554 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2553) connect Queue10_UInt8_17.io.enq.bits, _T_2554 node _T_2555 = eq(UInt<5>(0h12), idx_26) when _T_2555 : node _T_2556 = shl(UInt<5>(0h1a), 3) node _T_2557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2556) connect Queue10_UInt8_18.io.enq.bits, _T_2557 node _T_2558 = eq(UInt<5>(0h13), idx_26) when _T_2558 : node _T_2559 = shl(UInt<5>(0h1a), 3) node _T_2560 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2559) connect Queue10_UInt8_19.io.enq.bits, _T_2560 node _T_2561 = eq(UInt<5>(0h14), idx_26) when _T_2561 : node _T_2562 = shl(UInt<5>(0h1a), 3) node _T_2563 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2562) connect Queue10_UInt8_20.io.enq.bits, _T_2563 node _T_2564 = eq(UInt<5>(0h15), idx_26) when _T_2564 : node _T_2565 = shl(UInt<5>(0h1a), 3) node _T_2566 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2565) connect Queue10_UInt8_21.io.enq.bits, _T_2566 node _T_2567 = eq(UInt<5>(0h16), idx_26) when _T_2567 : node _T_2568 = shl(UInt<5>(0h1a), 3) node _T_2569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2568) connect Queue10_UInt8_22.io.enq.bits, _T_2569 node _T_2570 = eq(UInt<5>(0h17), idx_26) when _T_2570 : node _T_2571 = shl(UInt<5>(0h1a), 3) node _T_2572 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2571) connect Queue10_UInt8_23.io.enq.bits, _T_2572 node _T_2573 = eq(UInt<5>(0h18), idx_26) when _T_2573 : node _T_2574 = shl(UInt<5>(0h1a), 3) node _T_2575 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2574) connect Queue10_UInt8_24.io.enq.bits, _T_2575 node _T_2576 = eq(UInt<5>(0h19), idx_26) when _T_2576 : node _T_2577 = shl(UInt<5>(0h1a), 3) node _T_2578 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2577) connect Queue10_UInt8_25.io.enq.bits, _T_2578 node _T_2579 = eq(UInt<5>(0h1a), idx_26) when _T_2579 : node _T_2580 = shl(UInt<5>(0h1a), 3) node _T_2581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2580) connect Queue10_UInt8_26.io.enq.bits, _T_2581 node _T_2582 = eq(UInt<5>(0h1b), idx_26) when _T_2582 : node _T_2583 = shl(UInt<5>(0h1a), 3) node _T_2584 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2583) connect Queue10_UInt8_27.io.enq.bits, _T_2584 node _T_2585 = eq(UInt<5>(0h1c), idx_26) when _T_2585 : node _T_2586 = shl(UInt<5>(0h1a), 3) node _T_2587 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2586) connect Queue10_UInt8_28.io.enq.bits, _T_2587 node _T_2588 = eq(UInt<5>(0h1d), idx_26) when _T_2588 : node _T_2589 = shl(UInt<5>(0h1a), 3) node _T_2590 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2589) connect Queue10_UInt8_29.io.enq.bits, _T_2590 node _T_2591 = eq(UInt<5>(0h1e), idx_26) when _T_2591 : node _T_2592 = shl(UInt<5>(0h1a), 3) node _T_2593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2592) connect Queue10_UInt8_30.io.enq.bits, _T_2593 node _T_2594 = eq(UInt<5>(0h1f), idx_26) when _T_2594 : node _T_2595 = shl(UInt<5>(0h1a), 3) node _T_2596 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2595) connect Queue10_UInt8_31.io.enq.bits, _T_2596 node _idx_T_27 = add(write_start_index, UInt<5>(0h1b)) node idx_27 = rem(_idx_T_27, UInt<6>(0h20)) node _T_2597 = eq(UInt<1>(0h0), idx_27) when _T_2597 : node _T_2598 = shl(UInt<5>(0h1b), 3) node _T_2599 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2598) connect Queue10_UInt8.io.enq.bits, _T_2599 node _T_2600 = eq(UInt<1>(0h1), idx_27) when _T_2600 : node _T_2601 = shl(UInt<5>(0h1b), 3) node _T_2602 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2601) connect Queue10_UInt8_1.io.enq.bits, _T_2602 node _T_2603 = eq(UInt<2>(0h2), idx_27) when _T_2603 : node _T_2604 = shl(UInt<5>(0h1b), 3) node _T_2605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2604) connect Queue10_UInt8_2.io.enq.bits, _T_2605 node _T_2606 = eq(UInt<2>(0h3), idx_27) when _T_2606 : node _T_2607 = shl(UInt<5>(0h1b), 3) node _T_2608 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2607) connect Queue10_UInt8_3.io.enq.bits, _T_2608 node _T_2609 = eq(UInt<3>(0h4), idx_27) when _T_2609 : node _T_2610 = shl(UInt<5>(0h1b), 3) node _T_2611 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2610) connect Queue10_UInt8_4.io.enq.bits, _T_2611 node _T_2612 = eq(UInt<3>(0h5), idx_27) when _T_2612 : node _T_2613 = shl(UInt<5>(0h1b), 3) node _T_2614 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2613) connect Queue10_UInt8_5.io.enq.bits, _T_2614 node _T_2615 = eq(UInt<3>(0h6), idx_27) when _T_2615 : node _T_2616 = shl(UInt<5>(0h1b), 3) node _T_2617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2616) connect Queue10_UInt8_6.io.enq.bits, _T_2617 node _T_2618 = eq(UInt<3>(0h7), idx_27) when _T_2618 : node _T_2619 = shl(UInt<5>(0h1b), 3) node _T_2620 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2619) connect Queue10_UInt8_7.io.enq.bits, _T_2620 node _T_2621 = eq(UInt<4>(0h8), idx_27) when _T_2621 : node _T_2622 = shl(UInt<5>(0h1b), 3) node _T_2623 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2622) connect Queue10_UInt8_8.io.enq.bits, _T_2623 node _T_2624 = eq(UInt<4>(0h9), idx_27) when _T_2624 : node _T_2625 = shl(UInt<5>(0h1b), 3) node _T_2626 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2625) connect Queue10_UInt8_9.io.enq.bits, _T_2626 node _T_2627 = eq(UInt<4>(0ha), idx_27) when _T_2627 : node _T_2628 = shl(UInt<5>(0h1b), 3) node _T_2629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2628) connect Queue10_UInt8_10.io.enq.bits, _T_2629 node _T_2630 = eq(UInt<4>(0hb), idx_27) when _T_2630 : node _T_2631 = shl(UInt<5>(0h1b), 3) node _T_2632 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2631) connect Queue10_UInt8_11.io.enq.bits, _T_2632 node _T_2633 = eq(UInt<4>(0hc), idx_27) when _T_2633 : node _T_2634 = shl(UInt<5>(0h1b), 3) node _T_2635 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2634) connect Queue10_UInt8_12.io.enq.bits, _T_2635 node _T_2636 = eq(UInt<4>(0hd), idx_27) when _T_2636 : node _T_2637 = shl(UInt<5>(0h1b), 3) node _T_2638 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2637) connect Queue10_UInt8_13.io.enq.bits, _T_2638 node _T_2639 = eq(UInt<4>(0he), idx_27) when _T_2639 : node _T_2640 = shl(UInt<5>(0h1b), 3) node _T_2641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2640) connect Queue10_UInt8_14.io.enq.bits, _T_2641 node _T_2642 = eq(UInt<4>(0hf), idx_27) when _T_2642 : node _T_2643 = shl(UInt<5>(0h1b), 3) node _T_2644 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2643) connect Queue10_UInt8_15.io.enq.bits, _T_2644 node _T_2645 = eq(UInt<5>(0h10), idx_27) when _T_2645 : node _T_2646 = shl(UInt<5>(0h1b), 3) node _T_2647 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2646) connect Queue10_UInt8_16.io.enq.bits, _T_2647 node _T_2648 = eq(UInt<5>(0h11), idx_27) when _T_2648 : node _T_2649 = shl(UInt<5>(0h1b), 3) node _T_2650 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2649) connect Queue10_UInt8_17.io.enq.bits, _T_2650 node _T_2651 = eq(UInt<5>(0h12), idx_27) when _T_2651 : node _T_2652 = shl(UInt<5>(0h1b), 3) node _T_2653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2652) connect Queue10_UInt8_18.io.enq.bits, _T_2653 node _T_2654 = eq(UInt<5>(0h13), idx_27) when _T_2654 : node _T_2655 = shl(UInt<5>(0h1b), 3) node _T_2656 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2655) connect Queue10_UInt8_19.io.enq.bits, _T_2656 node _T_2657 = eq(UInt<5>(0h14), idx_27) when _T_2657 : node _T_2658 = shl(UInt<5>(0h1b), 3) node _T_2659 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2658) connect Queue10_UInt8_20.io.enq.bits, _T_2659 node _T_2660 = eq(UInt<5>(0h15), idx_27) when _T_2660 : node _T_2661 = shl(UInt<5>(0h1b), 3) node _T_2662 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2661) connect Queue10_UInt8_21.io.enq.bits, _T_2662 node _T_2663 = eq(UInt<5>(0h16), idx_27) when _T_2663 : node _T_2664 = shl(UInt<5>(0h1b), 3) node _T_2665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2664) connect Queue10_UInt8_22.io.enq.bits, _T_2665 node _T_2666 = eq(UInt<5>(0h17), idx_27) when _T_2666 : node _T_2667 = shl(UInt<5>(0h1b), 3) node _T_2668 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2667) connect Queue10_UInt8_23.io.enq.bits, _T_2668 node _T_2669 = eq(UInt<5>(0h18), idx_27) when _T_2669 : node _T_2670 = shl(UInt<5>(0h1b), 3) node _T_2671 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2670) connect Queue10_UInt8_24.io.enq.bits, _T_2671 node _T_2672 = eq(UInt<5>(0h19), idx_27) when _T_2672 : node _T_2673 = shl(UInt<5>(0h1b), 3) node _T_2674 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2673) connect Queue10_UInt8_25.io.enq.bits, _T_2674 node _T_2675 = eq(UInt<5>(0h1a), idx_27) when _T_2675 : node _T_2676 = shl(UInt<5>(0h1b), 3) node _T_2677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2676) connect Queue10_UInt8_26.io.enq.bits, _T_2677 node _T_2678 = eq(UInt<5>(0h1b), idx_27) when _T_2678 : node _T_2679 = shl(UInt<5>(0h1b), 3) node _T_2680 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2679) connect Queue10_UInt8_27.io.enq.bits, _T_2680 node _T_2681 = eq(UInt<5>(0h1c), idx_27) when _T_2681 : node _T_2682 = shl(UInt<5>(0h1b), 3) node _T_2683 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2682) connect Queue10_UInt8_28.io.enq.bits, _T_2683 node _T_2684 = eq(UInt<5>(0h1d), idx_27) when _T_2684 : node _T_2685 = shl(UInt<5>(0h1b), 3) node _T_2686 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2685) connect Queue10_UInt8_29.io.enq.bits, _T_2686 node _T_2687 = eq(UInt<5>(0h1e), idx_27) when _T_2687 : node _T_2688 = shl(UInt<5>(0h1b), 3) node _T_2689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2688) connect Queue10_UInt8_30.io.enq.bits, _T_2689 node _T_2690 = eq(UInt<5>(0h1f), idx_27) when _T_2690 : node _T_2691 = shl(UInt<5>(0h1b), 3) node _T_2692 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2691) connect Queue10_UInt8_31.io.enq.bits, _T_2692 node _idx_T_28 = add(write_start_index, UInt<5>(0h1c)) node idx_28 = rem(_idx_T_28, UInt<6>(0h20)) node _T_2693 = eq(UInt<1>(0h0), idx_28) when _T_2693 : node _T_2694 = shl(UInt<5>(0h1c), 3) node _T_2695 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2694) connect Queue10_UInt8.io.enq.bits, _T_2695 node _T_2696 = eq(UInt<1>(0h1), idx_28) when _T_2696 : node _T_2697 = shl(UInt<5>(0h1c), 3) node _T_2698 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2697) connect Queue10_UInt8_1.io.enq.bits, _T_2698 node _T_2699 = eq(UInt<2>(0h2), idx_28) when _T_2699 : node _T_2700 = shl(UInt<5>(0h1c), 3) node _T_2701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2700) connect Queue10_UInt8_2.io.enq.bits, _T_2701 node _T_2702 = eq(UInt<2>(0h3), idx_28) when _T_2702 : node _T_2703 = shl(UInt<5>(0h1c), 3) node _T_2704 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2703) connect Queue10_UInt8_3.io.enq.bits, _T_2704 node _T_2705 = eq(UInt<3>(0h4), idx_28) when _T_2705 : node _T_2706 = shl(UInt<5>(0h1c), 3) node _T_2707 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2706) connect Queue10_UInt8_4.io.enq.bits, _T_2707 node _T_2708 = eq(UInt<3>(0h5), idx_28) when _T_2708 : node _T_2709 = shl(UInt<5>(0h1c), 3) node _T_2710 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2709) connect Queue10_UInt8_5.io.enq.bits, _T_2710 node _T_2711 = eq(UInt<3>(0h6), idx_28) when _T_2711 : node _T_2712 = shl(UInt<5>(0h1c), 3) node _T_2713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2712) connect Queue10_UInt8_6.io.enq.bits, _T_2713 node _T_2714 = eq(UInt<3>(0h7), idx_28) when _T_2714 : node _T_2715 = shl(UInt<5>(0h1c), 3) node _T_2716 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2715) connect Queue10_UInt8_7.io.enq.bits, _T_2716 node _T_2717 = eq(UInt<4>(0h8), idx_28) when _T_2717 : node _T_2718 = shl(UInt<5>(0h1c), 3) node _T_2719 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2718) connect Queue10_UInt8_8.io.enq.bits, _T_2719 node _T_2720 = eq(UInt<4>(0h9), idx_28) when _T_2720 : node _T_2721 = shl(UInt<5>(0h1c), 3) node _T_2722 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2721) connect Queue10_UInt8_9.io.enq.bits, _T_2722 node _T_2723 = eq(UInt<4>(0ha), idx_28) when _T_2723 : node _T_2724 = shl(UInt<5>(0h1c), 3) node _T_2725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2724) connect Queue10_UInt8_10.io.enq.bits, _T_2725 node _T_2726 = eq(UInt<4>(0hb), idx_28) when _T_2726 : node _T_2727 = shl(UInt<5>(0h1c), 3) node _T_2728 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2727) connect Queue10_UInt8_11.io.enq.bits, _T_2728 node _T_2729 = eq(UInt<4>(0hc), idx_28) when _T_2729 : node _T_2730 = shl(UInt<5>(0h1c), 3) node _T_2731 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2730) connect Queue10_UInt8_12.io.enq.bits, _T_2731 node _T_2732 = eq(UInt<4>(0hd), idx_28) when _T_2732 : node _T_2733 = shl(UInt<5>(0h1c), 3) node _T_2734 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2733) connect Queue10_UInt8_13.io.enq.bits, _T_2734 node _T_2735 = eq(UInt<4>(0he), idx_28) when _T_2735 : node _T_2736 = shl(UInt<5>(0h1c), 3) node _T_2737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2736) connect Queue10_UInt8_14.io.enq.bits, _T_2737 node _T_2738 = eq(UInt<4>(0hf), idx_28) when _T_2738 : node _T_2739 = shl(UInt<5>(0h1c), 3) node _T_2740 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2739) connect Queue10_UInt8_15.io.enq.bits, _T_2740 node _T_2741 = eq(UInt<5>(0h10), idx_28) when _T_2741 : node _T_2742 = shl(UInt<5>(0h1c), 3) node _T_2743 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2742) connect Queue10_UInt8_16.io.enq.bits, _T_2743 node _T_2744 = eq(UInt<5>(0h11), idx_28) when _T_2744 : node _T_2745 = shl(UInt<5>(0h1c), 3) node _T_2746 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2745) connect Queue10_UInt8_17.io.enq.bits, _T_2746 node _T_2747 = eq(UInt<5>(0h12), idx_28) when _T_2747 : node _T_2748 = shl(UInt<5>(0h1c), 3) node _T_2749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2748) connect Queue10_UInt8_18.io.enq.bits, _T_2749 node _T_2750 = eq(UInt<5>(0h13), idx_28) when _T_2750 : node _T_2751 = shl(UInt<5>(0h1c), 3) node _T_2752 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2751) connect Queue10_UInt8_19.io.enq.bits, _T_2752 node _T_2753 = eq(UInt<5>(0h14), idx_28) when _T_2753 : node _T_2754 = shl(UInt<5>(0h1c), 3) node _T_2755 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2754) connect Queue10_UInt8_20.io.enq.bits, _T_2755 node _T_2756 = eq(UInt<5>(0h15), idx_28) when _T_2756 : node _T_2757 = shl(UInt<5>(0h1c), 3) node _T_2758 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2757) connect Queue10_UInt8_21.io.enq.bits, _T_2758 node _T_2759 = eq(UInt<5>(0h16), idx_28) when _T_2759 : node _T_2760 = shl(UInt<5>(0h1c), 3) node _T_2761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2760) connect Queue10_UInt8_22.io.enq.bits, _T_2761 node _T_2762 = eq(UInt<5>(0h17), idx_28) when _T_2762 : node _T_2763 = shl(UInt<5>(0h1c), 3) node _T_2764 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2763) connect Queue10_UInt8_23.io.enq.bits, _T_2764 node _T_2765 = eq(UInt<5>(0h18), idx_28) when _T_2765 : node _T_2766 = shl(UInt<5>(0h1c), 3) node _T_2767 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2766) connect Queue10_UInt8_24.io.enq.bits, _T_2767 node _T_2768 = eq(UInt<5>(0h19), idx_28) when _T_2768 : node _T_2769 = shl(UInt<5>(0h1c), 3) node _T_2770 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2769) connect Queue10_UInt8_25.io.enq.bits, _T_2770 node _T_2771 = eq(UInt<5>(0h1a), idx_28) when _T_2771 : node _T_2772 = shl(UInt<5>(0h1c), 3) node _T_2773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2772) connect Queue10_UInt8_26.io.enq.bits, _T_2773 node _T_2774 = eq(UInt<5>(0h1b), idx_28) when _T_2774 : node _T_2775 = shl(UInt<5>(0h1c), 3) node _T_2776 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2775) connect Queue10_UInt8_27.io.enq.bits, _T_2776 node _T_2777 = eq(UInt<5>(0h1c), idx_28) when _T_2777 : node _T_2778 = shl(UInt<5>(0h1c), 3) node _T_2779 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2778) connect Queue10_UInt8_28.io.enq.bits, _T_2779 node _T_2780 = eq(UInt<5>(0h1d), idx_28) when _T_2780 : node _T_2781 = shl(UInt<5>(0h1c), 3) node _T_2782 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2781) connect Queue10_UInt8_29.io.enq.bits, _T_2782 node _T_2783 = eq(UInt<5>(0h1e), idx_28) when _T_2783 : node _T_2784 = shl(UInt<5>(0h1c), 3) node _T_2785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2784) connect Queue10_UInt8_30.io.enq.bits, _T_2785 node _T_2786 = eq(UInt<5>(0h1f), idx_28) when _T_2786 : node _T_2787 = shl(UInt<5>(0h1c), 3) node _T_2788 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2787) connect Queue10_UInt8_31.io.enq.bits, _T_2788 node _idx_T_29 = add(write_start_index, UInt<5>(0h1d)) node idx_29 = rem(_idx_T_29, UInt<6>(0h20)) node _T_2789 = eq(UInt<1>(0h0), idx_29) when _T_2789 : node _T_2790 = shl(UInt<5>(0h1d), 3) node _T_2791 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2790) connect Queue10_UInt8.io.enq.bits, _T_2791 node _T_2792 = eq(UInt<1>(0h1), idx_29) when _T_2792 : node _T_2793 = shl(UInt<5>(0h1d), 3) node _T_2794 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2793) connect Queue10_UInt8_1.io.enq.bits, _T_2794 node _T_2795 = eq(UInt<2>(0h2), idx_29) when _T_2795 : node _T_2796 = shl(UInt<5>(0h1d), 3) node _T_2797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2796) connect Queue10_UInt8_2.io.enq.bits, _T_2797 node _T_2798 = eq(UInt<2>(0h3), idx_29) when _T_2798 : node _T_2799 = shl(UInt<5>(0h1d), 3) node _T_2800 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2799) connect Queue10_UInt8_3.io.enq.bits, _T_2800 node _T_2801 = eq(UInt<3>(0h4), idx_29) when _T_2801 : node _T_2802 = shl(UInt<5>(0h1d), 3) node _T_2803 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2802) connect Queue10_UInt8_4.io.enq.bits, _T_2803 node _T_2804 = eq(UInt<3>(0h5), idx_29) when _T_2804 : node _T_2805 = shl(UInt<5>(0h1d), 3) node _T_2806 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2805) connect Queue10_UInt8_5.io.enq.bits, _T_2806 node _T_2807 = eq(UInt<3>(0h6), idx_29) when _T_2807 : node _T_2808 = shl(UInt<5>(0h1d), 3) node _T_2809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2808) connect Queue10_UInt8_6.io.enq.bits, _T_2809 node _T_2810 = eq(UInt<3>(0h7), idx_29) when _T_2810 : node _T_2811 = shl(UInt<5>(0h1d), 3) node _T_2812 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2811) connect Queue10_UInt8_7.io.enq.bits, _T_2812 node _T_2813 = eq(UInt<4>(0h8), idx_29) when _T_2813 : node _T_2814 = shl(UInt<5>(0h1d), 3) node _T_2815 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2814) connect Queue10_UInt8_8.io.enq.bits, _T_2815 node _T_2816 = eq(UInt<4>(0h9), idx_29) when _T_2816 : node _T_2817 = shl(UInt<5>(0h1d), 3) node _T_2818 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2817) connect Queue10_UInt8_9.io.enq.bits, _T_2818 node _T_2819 = eq(UInt<4>(0ha), idx_29) when _T_2819 : node _T_2820 = shl(UInt<5>(0h1d), 3) node _T_2821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2820) connect Queue10_UInt8_10.io.enq.bits, _T_2821 node _T_2822 = eq(UInt<4>(0hb), idx_29) when _T_2822 : node _T_2823 = shl(UInt<5>(0h1d), 3) node _T_2824 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2823) connect Queue10_UInt8_11.io.enq.bits, _T_2824 node _T_2825 = eq(UInt<4>(0hc), idx_29) when _T_2825 : node _T_2826 = shl(UInt<5>(0h1d), 3) node _T_2827 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2826) connect Queue10_UInt8_12.io.enq.bits, _T_2827 node _T_2828 = eq(UInt<4>(0hd), idx_29) when _T_2828 : node _T_2829 = shl(UInt<5>(0h1d), 3) node _T_2830 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2829) connect Queue10_UInt8_13.io.enq.bits, _T_2830 node _T_2831 = eq(UInt<4>(0he), idx_29) when _T_2831 : node _T_2832 = shl(UInt<5>(0h1d), 3) node _T_2833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2832) connect Queue10_UInt8_14.io.enq.bits, _T_2833 node _T_2834 = eq(UInt<4>(0hf), idx_29) when _T_2834 : node _T_2835 = shl(UInt<5>(0h1d), 3) node _T_2836 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2835) connect Queue10_UInt8_15.io.enq.bits, _T_2836 node _T_2837 = eq(UInt<5>(0h10), idx_29) when _T_2837 : node _T_2838 = shl(UInt<5>(0h1d), 3) node _T_2839 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2838) connect Queue10_UInt8_16.io.enq.bits, _T_2839 node _T_2840 = eq(UInt<5>(0h11), idx_29) when _T_2840 : node _T_2841 = shl(UInt<5>(0h1d), 3) node _T_2842 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2841) connect Queue10_UInt8_17.io.enq.bits, _T_2842 node _T_2843 = eq(UInt<5>(0h12), idx_29) when _T_2843 : node _T_2844 = shl(UInt<5>(0h1d), 3) node _T_2845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2844) connect Queue10_UInt8_18.io.enq.bits, _T_2845 node _T_2846 = eq(UInt<5>(0h13), idx_29) when _T_2846 : node _T_2847 = shl(UInt<5>(0h1d), 3) node _T_2848 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2847) connect Queue10_UInt8_19.io.enq.bits, _T_2848 node _T_2849 = eq(UInt<5>(0h14), idx_29) when _T_2849 : node _T_2850 = shl(UInt<5>(0h1d), 3) node _T_2851 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2850) connect Queue10_UInt8_20.io.enq.bits, _T_2851 node _T_2852 = eq(UInt<5>(0h15), idx_29) when _T_2852 : node _T_2853 = shl(UInt<5>(0h1d), 3) node _T_2854 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2853) connect Queue10_UInt8_21.io.enq.bits, _T_2854 node _T_2855 = eq(UInt<5>(0h16), idx_29) when _T_2855 : node _T_2856 = shl(UInt<5>(0h1d), 3) node _T_2857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2856) connect Queue10_UInt8_22.io.enq.bits, _T_2857 node _T_2858 = eq(UInt<5>(0h17), idx_29) when _T_2858 : node _T_2859 = shl(UInt<5>(0h1d), 3) node _T_2860 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2859) connect Queue10_UInt8_23.io.enq.bits, _T_2860 node _T_2861 = eq(UInt<5>(0h18), idx_29) when _T_2861 : node _T_2862 = shl(UInt<5>(0h1d), 3) node _T_2863 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2862) connect Queue10_UInt8_24.io.enq.bits, _T_2863 node _T_2864 = eq(UInt<5>(0h19), idx_29) when _T_2864 : node _T_2865 = shl(UInt<5>(0h1d), 3) node _T_2866 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2865) connect Queue10_UInt8_25.io.enq.bits, _T_2866 node _T_2867 = eq(UInt<5>(0h1a), idx_29) when _T_2867 : node _T_2868 = shl(UInt<5>(0h1d), 3) node _T_2869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2868) connect Queue10_UInt8_26.io.enq.bits, _T_2869 node _T_2870 = eq(UInt<5>(0h1b), idx_29) when _T_2870 : node _T_2871 = shl(UInt<5>(0h1d), 3) node _T_2872 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2871) connect Queue10_UInt8_27.io.enq.bits, _T_2872 node _T_2873 = eq(UInt<5>(0h1c), idx_29) when _T_2873 : node _T_2874 = shl(UInt<5>(0h1d), 3) node _T_2875 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2874) connect Queue10_UInt8_28.io.enq.bits, _T_2875 node _T_2876 = eq(UInt<5>(0h1d), idx_29) when _T_2876 : node _T_2877 = shl(UInt<5>(0h1d), 3) node _T_2878 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2877) connect Queue10_UInt8_29.io.enq.bits, _T_2878 node _T_2879 = eq(UInt<5>(0h1e), idx_29) when _T_2879 : node _T_2880 = shl(UInt<5>(0h1d), 3) node _T_2881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2880) connect Queue10_UInt8_30.io.enq.bits, _T_2881 node _T_2882 = eq(UInt<5>(0h1f), idx_29) when _T_2882 : node _T_2883 = shl(UInt<5>(0h1d), 3) node _T_2884 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2883) connect Queue10_UInt8_31.io.enq.bits, _T_2884 node _idx_T_30 = add(write_start_index, UInt<5>(0h1e)) node idx_30 = rem(_idx_T_30, UInt<6>(0h20)) node _T_2885 = eq(UInt<1>(0h0), idx_30) when _T_2885 : node _T_2886 = shl(UInt<5>(0h1e), 3) node _T_2887 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2886) connect Queue10_UInt8.io.enq.bits, _T_2887 node _T_2888 = eq(UInt<1>(0h1), idx_30) when _T_2888 : node _T_2889 = shl(UInt<5>(0h1e), 3) node _T_2890 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2889) connect Queue10_UInt8_1.io.enq.bits, _T_2890 node _T_2891 = eq(UInt<2>(0h2), idx_30) when _T_2891 : node _T_2892 = shl(UInt<5>(0h1e), 3) node _T_2893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2892) connect Queue10_UInt8_2.io.enq.bits, _T_2893 node _T_2894 = eq(UInt<2>(0h3), idx_30) when _T_2894 : node _T_2895 = shl(UInt<5>(0h1e), 3) node _T_2896 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2895) connect Queue10_UInt8_3.io.enq.bits, _T_2896 node _T_2897 = eq(UInt<3>(0h4), idx_30) when _T_2897 : node _T_2898 = shl(UInt<5>(0h1e), 3) node _T_2899 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2898) connect Queue10_UInt8_4.io.enq.bits, _T_2899 node _T_2900 = eq(UInt<3>(0h5), idx_30) when _T_2900 : node _T_2901 = shl(UInt<5>(0h1e), 3) node _T_2902 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2901) connect Queue10_UInt8_5.io.enq.bits, _T_2902 node _T_2903 = eq(UInt<3>(0h6), idx_30) when _T_2903 : node _T_2904 = shl(UInt<5>(0h1e), 3) node _T_2905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2904) connect Queue10_UInt8_6.io.enq.bits, _T_2905 node _T_2906 = eq(UInt<3>(0h7), idx_30) when _T_2906 : node _T_2907 = shl(UInt<5>(0h1e), 3) node _T_2908 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2907) connect Queue10_UInt8_7.io.enq.bits, _T_2908 node _T_2909 = eq(UInt<4>(0h8), idx_30) when _T_2909 : node _T_2910 = shl(UInt<5>(0h1e), 3) node _T_2911 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2910) connect Queue10_UInt8_8.io.enq.bits, _T_2911 node _T_2912 = eq(UInt<4>(0h9), idx_30) when _T_2912 : node _T_2913 = shl(UInt<5>(0h1e), 3) node _T_2914 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2913) connect Queue10_UInt8_9.io.enq.bits, _T_2914 node _T_2915 = eq(UInt<4>(0ha), idx_30) when _T_2915 : node _T_2916 = shl(UInt<5>(0h1e), 3) node _T_2917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2916) connect Queue10_UInt8_10.io.enq.bits, _T_2917 node _T_2918 = eq(UInt<4>(0hb), idx_30) when _T_2918 : node _T_2919 = shl(UInt<5>(0h1e), 3) node _T_2920 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2919) connect Queue10_UInt8_11.io.enq.bits, _T_2920 node _T_2921 = eq(UInt<4>(0hc), idx_30) when _T_2921 : node _T_2922 = shl(UInt<5>(0h1e), 3) node _T_2923 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2922) connect Queue10_UInt8_12.io.enq.bits, _T_2923 node _T_2924 = eq(UInt<4>(0hd), idx_30) when _T_2924 : node _T_2925 = shl(UInt<5>(0h1e), 3) node _T_2926 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2925) connect Queue10_UInt8_13.io.enq.bits, _T_2926 node _T_2927 = eq(UInt<4>(0he), idx_30) when _T_2927 : node _T_2928 = shl(UInt<5>(0h1e), 3) node _T_2929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2928) connect Queue10_UInt8_14.io.enq.bits, _T_2929 node _T_2930 = eq(UInt<4>(0hf), idx_30) when _T_2930 : node _T_2931 = shl(UInt<5>(0h1e), 3) node _T_2932 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2931) connect Queue10_UInt8_15.io.enq.bits, _T_2932 node _T_2933 = eq(UInt<5>(0h10), idx_30) when _T_2933 : node _T_2934 = shl(UInt<5>(0h1e), 3) node _T_2935 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2934) connect Queue10_UInt8_16.io.enq.bits, _T_2935 node _T_2936 = eq(UInt<5>(0h11), idx_30) when _T_2936 : node _T_2937 = shl(UInt<5>(0h1e), 3) node _T_2938 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2937) connect Queue10_UInt8_17.io.enq.bits, _T_2938 node _T_2939 = eq(UInt<5>(0h12), idx_30) when _T_2939 : node _T_2940 = shl(UInt<5>(0h1e), 3) node _T_2941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2940) connect Queue10_UInt8_18.io.enq.bits, _T_2941 node _T_2942 = eq(UInt<5>(0h13), idx_30) when _T_2942 : node _T_2943 = shl(UInt<5>(0h1e), 3) node _T_2944 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2943) connect Queue10_UInt8_19.io.enq.bits, _T_2944 node _T_2945 = eq(UInt<5>(0h14), idx_30) when _T_2945 : node _T_2946 = shl(UInt<5>(0h1e), 3) node _T_2947 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2946) connect Queue10_UInt8_20.io.enq.bits, _T_2947 node _T_2948 = eq(UInt<5>(0h15), idx_30) when _T_2948 : node _T_2949 = shl(UInt<5>(0h1e), 3) node _T_2950 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2949) connect Queue10_UInt8_21.io.enq.bits, _T_2950 node _T_2951 = eq(UInt<5>(0h16), idx_30) when _T_2951 : node _T_2952 = shl(UInt<5>(0h1e), 3) node _T_2953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2952) connect Queue10_UInt8_22.io.enq.bits, _T_2953 node _T_2954 = eq(UInt<5>(0h17), idx_30) when _T_2954 : node _T_2955 = shl(UInt<5>(0h1e), 3) node _T_2956 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2955) connect Queue10_UInt8_23.io.enq.bits, _T_2956 node _T_2957 = eq(UInt<5>(0h18), idx_30) when _T_2957 : node _T_2958 = shl(UInt<5>(0h1e), 3) node _T_2959 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2958) connect Queue10_UInt8_24.io.enq.bits, _T_2959 node _T_2960 = eq(UInt<5>(0h19), idx_30) when _T_2960 : node _T_2961 = shl(UInt<5>(0h1e), 3) node _T_2962 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2961) connect Queue10_UInt8_25.io.enq.bits, _T_2962 node _T_2963 = eq(UInt<5>(0h1a), idx_30) when _T_2963 : node _T_2964 = shl(UInt<5>(0h1e), 3) node _T_2965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2964) connect Queue10_UInt8_26.io.enq.bits, _T_2965 node _T_2966 = eq(UInt<5>(0h1b), idx_30) when _T_2966 : node _T_2967 = shl(UInt<5>(0h1e), 3) node _T_2968 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2967) connect Queue10_UInt8_27.io.enq.bits, _T_2968 node _T_2969 = eq(UInt<5>(0h1c), idx_30) when _T_2969 : node _T_2970 = shl(UInt<5>(0h1e), 3) node _T_2971 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2970) connect Queue10_UInt8_28.io.enq.bits, _T_2971 node _T_2972 = eq(UInt<5>(0h1d), idx_30) when _T_2972 : node _T_2973 = shl(UInt<5>(0h1e), 3) node _T_2974 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2973) connect Queue10_UInt8_29.io.enq.bits, _T_2974 node _T_2975 = eq(UInt<5>(0h1e), idx_30) when _T_2975 : node _T_2976 = shl(UInt<5>(0h1e), 3) node _T_2977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2976) connect Queue10_UInt8_30.io.enq.bits, _T_2977 node _T_2978 = eq(UInt<5>(0h1f), idx_30) when _T_2978 : node _T_2979 = shl(UInt<5>(0h1e), 3) node _T_2980 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2979) connect Queue10_UInt8_31.io.enq.bits, _T_2980 node _idx_T_31 = add(write_start_index, UInt<5>(0h1f)) node idx_31 = rem(_idx_T_31, UInt<6>(0h20)) node _T_2981 = eq(UInt<1>(0h0), idx_31) when _T_2981 : node _T_2982 = shl(UInt<5>(0h1f), 3) node _T_2983 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2982) connect Queue10_UInt8.io.enq.bits, _T_2983 node _T_2984 = eq(UInt<1>(0h1), idx_31) when _T_2984 : node _T_2985 = shl(UInt<5>(0h1f), 3) node _T_2986 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2985) connect Queue10_UInt8_1.io.enq.bits, _T_2986 node _T_2987 = eq(UInt<2>(0h2), idx_31) when _T_2987 : node _T_2988 = shl(UInt<5>(0h1f), 3) node _T_2989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2988) connect Queue10_UInt8_2.io.enq.bits, _T_2989 node _T_2990 = eq(UInt<2>(0h3), idx_31) when _T_2990 : node _T_2991 = shl(UInt<5>(0h1f), 3) node _T_2992 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2991) connect Queue10_UInt8_3.io.enq.bits, _T_2992 node _T_2993 = eq(UInt<3>(0h4), idx_31) when _T_2993 : node _T_2994 = shl(UInt<5>(0h1f), 3) node _T_2995 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2994) connect Queue10_UInt8_4.io.enq.bits, _T_2995 node _T_2996 = eq(UInt<3>(0h5), idx_31) when _T_2996 : node _T_2997 = shl(UInt<5>(0h1f), 3) node _T_2998 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2997) connect Queue10_UInt8_5.io.enq.bits, _T_2998 node _T_2999 = eq(UInt<3>(0h6), idx_31) when _T_2999 : node _T_3000 = shl(UInt<5>(0h1f), 3) node _T_3001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3000) connect Queue10_UInt8_6.io.enq.bits, _T_3001 node _T_3002 = eq(UInt<3>(0h7), idx_31) when _T_3002 : node _T_3003 = shl(UInt<5>(0h1f), 3) node _T_3004 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3003) connect Queue10_UInt8_7.io.enq.bits, _T_3004 node _T_3005 = eq(UInt<4>(0h8), idx_31) when _T_3005 : node _T_3006 = shl(UInt<5>(0h1f), 3) node _T_3007 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3006) connect Queue10_UInt8_8.io.enq.bits, _T_3007 node _T_3008 = eq(UInt<4>(0h9), idx_31) when _T_3008 : node _T_3009 = shl(UInt<5>(0h1f), 3) node _T_3010 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3009) connect Queue10_UInt8_9.io.enq.bits, _T_3010 node _T_3011 = eq(UInt<4>(0ha), idx_31) when _T_3011 : node _T_3012 = shl(UInt<5>(0h1f), 3) node _T_3013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3012) connect Queue10_UInt8_10.io.enq.bits, _T_3013 node _T_3014 = eq(UInt<4>(0hb), idx_31) when _T_3014 : node _T_3015 = shl(UInt<5>(0h1f), 3) node _T_3016 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3015) connect Queue10_UInt8_11.io.enq.bits, _T_3016 node _T_3017 = eq(UInt<4>(0hc), idx_31) when _T_3017 : node _T_3018 = shl(UInt<5>(0h1f), 3) node _T_3019 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3018) connect Queue10_UInt8_12.io.enq.bits, _T_3019 node _T_3020 = eq(UInt<4>(0hd), idx_31) when _T_3020 : node _T_3021 = shl(UInt<5>(0h1f), 3) node _T_3022 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3021) connect Queue10_UInt8_13.io.enq.bits, _T_3022 node _T_3023 = eq(UInt<4>(0he), idx_31) when _T_3023 : node _T_3024 = shl(UInt<5>(0h1f), 3) node _T_3025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3024) connect Queue10_UInt8_14.io.enq.bits, _T_3025 node _T_3026 = eq(UInt<4>(0hf), idx_31) when _T_3026 : node _T_3027 = shl(UInt<5>(0h1f), 3) node _T_3028 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3027) connect Queue10_UInt8_15.io.enq.bits, _T_3028 node _T_3029 = eq(UInt<5>(0h10), idx_31) when _T_3029 : node _T_3030 = shl(UInt<5>(0h1f), 3) node _T_3031 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3030) connect Queue10_UInt8_16.io.enq.bits, _T_3031 node _T_3032 = eq(UInt<5>(0h11), idx_31) when _T_3032 : node _T_3033 = shl(UInt<5>(0h1f), 3) node _T_3034 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3033) connect Queue10_UInt8_17.io.enq.bits, _T_3034 node _T_3035 = eq(UInt<5>(0h12), idx_31) when _T_3035 : node _T_3036 = shl(UInt<5>(0h1f), 3) node _T_3037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3036) connect Queue10_UInt8_18.io.enq.bits, _T_3037 node _T_3038 = eq(UInt<5>(0h13), idx_31) when _T_3038 : node _T_3039 = shl(UInt<5>(0h1f), 3) node _T_3040 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3039) connect Queue10_UInt8_19.io.enq.bits, _T_3040 node _T_3041 = eq(UInt<5>(0h14), idx_31) when _T_3041 : node _T_3042 = shl(UInt<5>(0h1f), 3) node _T_3043 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3042) connect Queue10_UInt8_20.io.enq.bits, _T_3043 node _T_3044 = eq(UInt<5>(0h15), idx_31) when _T_3044 : node _T_3045 = shl(UInt<5>(0h1f), 3) node _T_3046 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3045) connect Queue10_UInt8_21.io.enq.bits, _T_3046 node _T_3047 = eq(UInt<5>(0h16), idx_31) when _T_3047 : node _T_3048 = shl(UInt<5>(0h1f), 3) node _T_3049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3048) connect Queue10_UInt8_22.io.enq.bits, _T_3049 node _T_3050 = eq(UInt<5>(0h17), idx_31) when _T_3050 : node _T_3051 = shl(UInt<5>(0h1f), 3) node _T_3052 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3051) connect Queue10_UInt8_23.io.enq.bits, _T_3052 node _T_3053 = eq(UInt<5>(0h18), idx_31) when _T_3053 : node _T_3054 = shl(UInt<5>(0h1f), 3) node _T_3055 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3054) connect Queue10_UInt8_24.io.enq.bits, _T_3055 node _T_3056 = eq(UInt<5>(0h19), idx_31) when _T_3056 : node _T_3057 = shl(UInt<5>(0h1f), 3) node _T_3058 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3057) connect Queue10_UInt8_25.io.enq.bits, _T_3058 node _T_3059 = eq(UInt<5>(0h1a), idx_31) when _T_3059 : node _T_3060 = shl(UInt<5>(0h1f), 3) node _T_3061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3060) connect Queue10_UInt8_26.io.enq.bits, _T_3061 node _T_3062 = eq(UInt<5>(0h1b), idx_31) when _T_3062 : node _T_3063 = shl(UInt<5>(0h1f), 3) node _T_3064 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3063) connect Queue10_UInt8_27.io.enq.bits, _T_3064 node _T_3065 = eq(UInt<5>(0h1c), idx_31) when _T_3065 : node _T_3066 = shl(UInt<5>(0h1f), 3) node _T_3067 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3066) connect Queue10_UInt8_28.io.enq.bits, _T_3067 node _T_3068 = eq(UInt<5>(0h1d), idx_31) when _T_3068 : node _T_3069 = shl(UInt<5>(0h1f), 3) node _T_3070 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3069) connect Queue10_UInt8_29.io.enq.bits, _T_3070 node _T_3071 = eq(UInt<5>(0h1e), idx_31) when _T_3071 : node _T_3072 = shl(UInt<5>(0h1f), 3) node _T_3073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3072) connect Queue10_UInt8_30.io.enq.bits, _T_3073 node _T_3074 = eq(UInt<5>(0h1f), idx_31) when _T_3074 : node _T_3075 = shl(UInt<5>(0h1f), 3) node _T_3076 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3075) connect Queue10_UInt8_31.io.enq.bits, _T_3076 node wrap_len_index_wide = add(write_start_index, incoming_writes_Q.io.deq.bits.validbytes) node wrap_len_index_end = rem(wrap_len_index_wide, UInt<6>(0h20)) node wrapped = geq(wrap_len_index_wide, UInt<6>(0h20)) node _all_queues_ready_T = and(Queue10_UInt8.io.enq.ready, Queue10_UInt8_1.io.enq.ready) node _all_queues_ready_T_1 = and(_all_queues_ready_T, Queue10_UInt8_2.io.enq.ready) node _all_queues_ready_T_2 = and(_all_queues_ready_T_1, Queue10_UInt8_3.io.enq.ready) node _all_queues_ready_T_3 = and(_all_queues_ready_T_2, Queue10_UInt8_4.io.enq.ready) node _all_queues_ready_T_4 = and(_all_queues_ready_T_3, Queue10_UInt8_5.io.enq.ready) node _all_queues_ready_T_5 = and(_all_queues_ready_T_4, Queue10_UInt8_6.io.enq.ready) node _all_queues_ready_T_6 = and(_all_queues_ready_T_5, Queue10_UInt8_7.io.enq.ready) node _all_queues_ready_T_7 = and(_all_queues_ready_T_6, Queue10_UInt8_8.io.enq.ready) node _all_queues_ready_T_8 = and(_all_queues_ready_T_7, Queue10_UInt8_9.io.enq.ready) node _all_queues_ready_T_9 = and(_all_queues_ready_T_8, Queue10_UInt8_10.io.enq.ready) node _all_queues_ready_T_10 = and(_all_queues_ready_T_9, Queue10_UInt8_11.io.enq.ready) node _all_queues_ready_T_11 = and(_all_queues_ready_T_10, Queue10_UInt8_12.io.enq.ready) node _all_queues_ready_T_12 = and(_all_queues_ready_T_11, Queue10_UInt8_13.io.enq.ready) node _all_queues_ready_T_13 = and(_all_queues_ready_T_12, Queue10_UInt8_14.io.enq.ready) node _all_queues_ready_T_14 = and(_all_queues_ready_T_13, Queue10_UInt8_15.io.enq.ready) node _all_queues_ready_T_15 = and(_all_queues_ready_T_14, Queue10_UInt8_16.io.enq.ready) node _all_queues_ready_T_16 = and(_all_queues_ready_T_15, Queue10_UInt8_17.io.enq.ready) node _all_queues_ready_T_17 = and(_all_queues_ready_T_16, Queue10_UInt8_18.io.enq.ready) node _all_queues_ready_T_18 = and(_all_queues_ready_T_17, Queue10_UInt8_19.io.enq.ready) node _all_queues_ready_T_19 = and(_all_queues_ready_T_18, Queue10_UInt8_20.io.enq.ready) node _all_queues_ready_T_20 = and(_all_queues_ready_T_19, Queue10_UInt8_21.io.enq.ready) node _all_queues_ready_T_21 = and(_all_queues_ready_T_20, Queue10_UInt8_22.io.enq.ready) node _all_queues_ready_T_22 = and(_all_queues_ready_T_21, Queue10_UInt8_23.io.enq.ready) node _all_queues_ready_T_23 = and(_all_queues_ready_T_22, Queue10_UInt8_24.io.enq.ready) node _all_queues_ready_T_24 = and(_all_queues_ready_T_23, Queue10_UInt8_25.io.enq.ready) node _all_queues_ready_T_25 = and(_all_queues_ready_T_24, Queue10_UInt8_26.io.enq.ready) node _all_queues_ready_T_26 = and(_all_queues_ready_T_25, Queue10_UInt8_27.io.enq.ready) node _all_queues_ready_T_27 = and(_all_queues_ready_T_26, Queue10_UInt8_28.io.enq.ready) node _all_queues_ready_T_28 = and(_all_queues_ready_T_27, Queue10_UInt8_29.io.enq.ready) node _all_queues_ready_T_29 = and(_all_queues_ready_T_28, Queue10_UInt8_30.io.enq.ready) node all_queues_ready = and(_all_queues_ready_T_29, Queue10_UInt8_31.io.enq.ready) connect incoming_writes_Q.io.deq.ready, all_queues_ready node _T_3077 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) when _T_3077 : connect write_start_index, wrap_len_index_end node _use_this_queue_T = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_1 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_2 = or(_use_this_queue_T, _use_this_queue_T_1) node _use_this_queue_T_3 = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_4 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_5 = and(_use_this_queue_T_3, _use_this_queue_T_4) node use_this_queue = mux(wrapped, _use_this_queue_T_2, _use_this_queue_T_5) node _T_3078 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3079 = and(_T_3078, use_this_queue) connect Queue10_UInt8.io.enq.valid, _T_3079 node _use_this_queue_T_6 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_7 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_8 = or(_use_this_queue_T_6, _use_this_queue_T_7) node _use_this_queue_T_9 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_10 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_11 = and(_use_this_queue_T_9, _use_this_queue_T_10) node use_this_queue_1 = mux(wrapped, _use_this_queue_T_8, _use_this_queue_T_11) node _T_3080 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3081 = and(_T_3080, use_this_queue_1) connect Queue10_UInt8_1.io.enq.valid, _T_3081 node _use_this_queue_T_12 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_13 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_14 = or(_use_this_queue_T_12, _use_this_queue_T_13) node _use_this_queue_T_15 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_16 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_17 = and(_use_this_queue_T_15, _use_this_queue_T_16) node use_this_queue_2 = mux(wrapped, _use_this_queue_T_14, _use_this_queue_T_17) node _T_3082 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3083 = and(_T_3082, use_this_queue_2) connect Queue10_UInt8_2.io.enq.valid, _T_3083 node _use_this_queue_T_18 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_19 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_20 = or(_use_this_queue_T_18, _use_this_queue_T_19) node _use_this_queue_T_21 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_22 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_23 = and(_use_this_queue_T_21, _use_this_queue_T_22) node use_this_queue_3 = mux(wrapped, _use_this_queue_T_20, _use_this_queue_T_23) node _T_3084 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3085 = and(_T_3084, use_this_queue_3) connect Queue10_UInt8_3.io.enq.valid, _T_3085 node _use_this_queue_T_24 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_25 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_26 = or(_use_this_queue_T_24, _use_this_queue_T_25) node _use_this_queue_T_27 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_28 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_29 = and(_use_this_queue_T_27, _use_this_queue_T_28) node use_this_queue_4 = mux(wrapped, _use_this_queue_T_26, _use_this_queue_T_29) node _T_3086 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3087 = and(_T_3086, use_this_queue_4) connect Queue10_UInt8_4.io.enq.valid, _T_3087 node _use_this_queue_T_30 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_31 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_32 = or(_use_this_queue_T_30, _use_this_queue_T_31) node _use_this_queue_T_33 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_34 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_35 = and(_use_this_queue_T_33, _use_this_queue_T_34) node use_this_queue_5 = mux(wrapped, _use_this_queue_T_32, _use_this_queue_T_35) node _T_3088 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3089 = and(_T_3088, use_this_queue_5) connect Queue10_UInt8_5.io.enq.valid, _T_3089 node _use_this_queue_T_36 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_37 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_38 = or(_use_this_queue_T_36, _use_this_queue_T_37) node _use_this_queue_T_39 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_40 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_41 = and(_use_this_queue_T_39, _use_this_queue_T_40) node use_this_queue_6 = mux(wrapped, _use_this_queue_T_38, _use_this_queue_T_41) node _T_3090 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3091 = and(_T_3090, use_this_queue_6) connect Queue10_UInt8_6.io.enq.valid, _T_3091 node _use_this_queue_T_42 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_43 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_44 = or(_use_this_queue_T_42, _use_this_queue_T_43) node _use_this_queue_T_45 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_46 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_47 = and(_use_this_queue_T_45, _use_this_queue_T_46) node use_this_queue_7 = mux(wrapped, _use_this_queue_T_44, _use_this_queue_T_47) node _T_3092 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3093 = and(_T_3092, use_this_queue_7) connect Queue10_UInt8_7.io.enq.valid, _T_3093 node _use_this_queue_T_48 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_49 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_50 = or(_use_this_queue_T_48, _use_this_queue_T_49) node _use_this_queue_T_51 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_52 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_53 = and(_use_this_queue_T_51, _use_this_queue_T_52) node use_this_queue_8 = mux(wrapped, _use_this_queue_T_50, _use_this_queue_T_53) node _T_3094 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3095 = and(_T_3094, use_this_queue_8) connect Queue10_UInt8_8.io.enq.valid, _T_3095 node _use_this_queue_T_54 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_55 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_56 = or(_use_this_queue_T_54, _use_this_queue_T_55) node _use_this_queue_T_57 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_58 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_59 = and(_use_this_queue_T_57, _use_this_queue_T_58) node use_this_queue_9 = mux(wrapped, _use_this_queue_T_56, _use_this_queue_T_59) node _T_3096 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3097 = and(_T_3096, use_this_queue_9) connect Queue10_UInt8_9.io.enq.valid, _T_3097 node _use_this_queue_T_60 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_61 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_62 = or(_use_this_queue_T_60, _use_this_queue_T_61) node _use_this_queue_T_63 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_64 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_65 = and(_use_this_queue_T_63, _use_this_queue_T_64) node use_this_queue_10 = mux(wrapped, _use_this_queue_T_62, _use_this_queue_T_65) node _T_3098 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3099 = and(_T_3098, use_this_queue_10) connect Queue10_UInt8_10.io.enq.valid, _T_3099 node _use_this_queue_T_66 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_67 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_68 = or(_use_this_queue_T_66, _use_this_queue_T_67) node _use_this_queue_T_69 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_70 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_71 = and(_use_this_queue_T_69, _use_this_queue_T_70) node use_this_queue_11 = mux(wrapped, _use_this_queue_T_68, _use_this_queue_T_71) node _T_3100 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3101 = and(_T_3100, use_this_queue_11) connect Queue10_UInt8_11.io.enq.valid, _T_3101 node _use_this_queue_T_72 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_73 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_74 = or(_use_this_queue_T_72, _use_this_queue_T_73) node _use_this_queue_T_75 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_76 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_77 = and(_use_this_queue_T_75, _use_this_queue_T_76) node use_this_queue_12 = mux(wrapped, _use_this_queue_T_74, _use_this_queue_T_77) node _T_3102 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3103 = and(_T_3102, use_this_queue_12) connect Queue10_UInt8_12.io.enq.valid, _T_3103 node _use_this_queue_T_78 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_79 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_80 = or(_use_this_queue_T_78, _use_this_queue_T_79) node _use_this_queue_T_81 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_82 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_83 = and(_use_this_queue_T_81, _use_this_queue_T_82) node use_this_queue_13 = mux(wrapped, _use_this_queue_T_80, _use_this_queue_T_83) node _T_3104 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3105 = and(_T_3104, use_this_queue_13) connect Queue10_UInt8_13.io.enq.valid, _T_3105 node _use_this_queue_T_84 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_85 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_86 = or(_use_this_queue_T_84, _use_this_queue_T_85) node _use_this_queue_T_87 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_88 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_89 = and(_use_this_queue_T_87, _use_this_queue_T_88) node use_this_queue_14 = mux(wrapped, _use_this_queue_T_86, _use_this_queue_T_89) node _T_3106 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3107 = and(_T_3106, use_this_queue_14) connect Queue10_UInt8_14.io.enq.valid, _T_3107 node _use_this_queue_T_90 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_91 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_92 = or(_use_this_queue_T_90, _use_this_queue_T_91) node _use_this_queue_T_93 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_94 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_95 = and(_use_this_queue_T_93, _use_this_queue_T_94) node use_this_queue_15 = mux(wrapped, _use_this_queue_T_92, _use_this_queue_T_95) node _T_3108 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3109 = and(_T_3108, use_this_queue_15) connect Queue10_UInt8_15.io.enq.valid, _T_3109 node _use_this_queue_T_96 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_97 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_98 = or(_use_this_queue_T_96, _use_this_queue_T_97) node _use_this_queue_T_99 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_100 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_101 = and(_use_this_queue_T_99, _use_this_queue_T_100) node use_this_queue_16 = mux(wrapped, _use_this_queue_T_98, _use_this_queue_T_101) node _T_3110 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3111 = and(_T_3110, use_this_queue_16) connect Queue10_UInt8_16.io.enq.valid, _T_3111 node _use_this_queue_T_102 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_103 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_104 = or(_use_this_queue_T_102, _use_this_queue_T_103) node _use_this_queue_T_105 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_106 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_107 = and(_use_this_queue_T_105, _use_this_queue_T_106) node use_this_queue_17 = mux(wrapped, _use_this_queue_T_104, _use_this_queue_T_107) node _T_3112 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3113 = and(_T_3112, use_this_queue_17) connect Queue10_UInt8_17.io.enq.valid, _T_3113 node _use_this_queue_T_108 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_109 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_110 = or(_use_this_queue_T_108, _use_this_queue_T_109) node _use_this_queue_T_111 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_112 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_113 = and(_use_this_queue_T_111, _use_this_queue_T_112) node use_this_queue_18 = mux(wrapped, _use_this_queue_T_110, _use_this_queue_T_113) node _T_3114 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3115 = and(_T_3114, use_this_queue_18) connect Queue10_UInt8_18.io.enq.valid, _T_3115 node _use_this_queue_T_114 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_115 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_116 = or(_use_this_queue_T_114, _use_this_queue_T_115) node _use_this_queue_T_117 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_118 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_119 = and(_use_this_queue_T_117, _use_this_queue_T_118) node use_this_queue_19 = mux(wrapped, _use_this_queue_T_116, _use_this_queue_T_119) node _T_3116 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3117 = and(_T_3116, use_this_queue_19) connect Queue10_UInt8_19.io.enq.valid, _T_3117 node _use_this_queue_T_120 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_121 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_122 = or(_use_this_queue_T_120, _use_this_queue_T_121) node _use_this_queue_T_123 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_124 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_125 = and(_use_this_queue_T_123, _use_this_queue_T_124) node use_this_queue_20 = mux(wrapped, _use_this_queue_T_122, _use_this_queue_T_125) node _T_3118 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3119 = and(_T_3118, use_this_queue_20) connect Queue10_UInt8_20.io.enq.valid, _T_3119 node _use_this_queue_T_126 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_127 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_128 = or(_use_this_queue_T_126, _use_this_queue_T_127) node _use_this_queue_T_129 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_130 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_131 = and(_use_this_queue_T_129, _use_this_queue_T_130) node use_this_queue_21 = mux(wrapped, _use_this_queue_T_128, _use_this_queue_T_131) node _T_3120 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3121 = and(_T_3120, use_this_queue_21) connect Queue10_UInt8_21.io.enq.valid, _T_3121 node _use_this_queue_T_132 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_133 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_134 = or(_use_this_queue_T_132, _use_this_queue_T_133) node _use_this_queue_T_135 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_136 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_137 = and(_use_this_queue_T_135, _use_this_queue_T_136) node use_this_queue_22 = mux(wrapped, _use_this_queue_T_134, _use_this_queue_T_137) node _T_3122 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3123 = and(_T_3122, use_this_queue_22) connect Queue10_UInt8_22.io.enq.valid, _T_3123 node _use_this_queue_T_138 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_139 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_140 = or(_use_this_queue_T_138, _use_this_queue_T_139) node _use_this_queue_T_141 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_142 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_143 = and(_use_this_queue_T_141, _use_this_queue_T_142) node use_this_queue_23 = mux(wrapped, _use_this_queue_T_140, _use_this_queue_T_143) node _T_3124 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3125 = and(_T_3124, use_this_queue_23) connect Queue10_UInt8_23.io.enq.valid, _T_3125 node _use_this_queue_T_144 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_145 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_146 = or(_use_this_queue_T_144, _use_this_queue_T_145) node _use_this_queue_T_147 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_148 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_149 = and(_use_this_queue_T_147, _use_this_queue_T_148) node use_this_queue_24 = mux(wrapped, _use_this_queue_T_146, _use_this_queue_T_149) node _T_3126 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3127 = and(_T_3126, use_this_queue_24) connect Queue10_UInt8_24.io.enq.valid, _T_3127 node _use_this_queue_T_150 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_151 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_152 = or(_use_this_queue_T_150, _use_this_queue_T_151) node _use_this_queue_T_153 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_154 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_155 = and(_use_this_queue_T_153, _use_this_queue_T_154) node use_this_queue_25 = mux(wrapped, _use_this_queue_T_152, _use_this_queue_T_155) node _T_3128 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3129 = and(_T_3128, use_this_queue_25) connect Queue10_UInt8_25.io.enq.valid, _T_3129 node _use_this_queue_T_156 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_157 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_158 = or(_use_this_queue_T_156, _use_this_queue_T_157) node _use_this_queue_T_159 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_160 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_161 = and(_use_this_queue_T_159, _use_this_queue_T_160) node use_this_queue_26 = mux(wrapped, _use_this_queue_T_158, _use_this_queue_T_161) node _T_3130 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3131 = and(_T_3130, use_this_queue_26) connect Queue10_UInt8_26.io.enq.valid, _T_3131 node _use_this_queue_T_162 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_163 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_164 = or(_use_this_queue_T_162, _use_this_queue_T_163) node _use_this_queue_T_165 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_166 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_167 = and(_use_this_queue_T_165, _use_this_queue_T_166) node use_this_queue_27 = mux(wrapped, _use_this_queue_T_164, _use_this_queue_T_167) node _T_3132 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3133 = and(_T_3132, use_this_queue_27) connect Queue10_UInt8_27.io.enq.valid, _T_3133 node _use_this_queue_T_168 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_169 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_170 = or(_use_this_queue_T_168, _use_this_queue_T_169) node _use_this_queue_T_171 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_172 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_173 = and(_use_this_queue_T_171, _use_this_queue_T_172) node use_this_queue_28 = mux(wrapped, _use_this_queue_T_170, _use_this_queue_T_173) node _T_3134 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3135 = and(_T_3134, use_this_queue_28) connect Queue10_UInt8_28.io.enq.valid, _T_3135 node _use_this_queue_T_174 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_175 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_176 = or(_use_this_queue_T_174, _use_this_queue_T_175) node _use_this_queue_T_177 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_178 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_179 = and(_use_this_queue_T_177, _use_this_queue_T_178) node use_this_queue_29 = mux(wrapped, _use_this_queue_T_176, _use_this_queue_T_179) node _T_3136 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3137 = and(_T_3136, use_this_queue_29) connect Queue10_UInt8_29.io.enq.valid, _T_3137 node _use_this_queue_T_180 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_181 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_182 = or(_use_this_queue_T_180, _use_this_queue_T_181) node _use_this_queue_T_183 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_184 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_185 = and(_use_this_queue_T_183, _use_this_queue_T_184) node use_this_queue_30 = mux(wrapped, _use_this_queue_T_182, _use_this_queue_T_185) node _T_3138 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3139 = and(_T_3138, use_this_queue_30) connect Queue10_UInt8_30.io.enq.valid, _T_3139 node _use_this_queue_T_186 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_187 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_188 = or(_use_this_queue_T_186, _use_this_queue_T_187) node _use_this_queue_T_189 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_190 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_191 = and(_use_this_queue_T_189, _use_this_queue_T_190) node use_this_queue_31 = mux(wrapped, _use_this_queue_T_188, _use_this_queue_T_191) node _T_3140 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3141 = and(_T_3140, use_this_queue_31) connect Queue10_UInt8_31.io.enq.valid, _T_3141 when Queue10_UInt8.io.deq.valid : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_3142 = asUInt(reset) node _T_3143 = eq(_T_3142, UInt<1>(0h0)) when _T_3143 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_3144 = asUInt(reset) node _T_3145 = eq(_T_3144, UInt<1>(0h0)) when _T_3145 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<1>(0h0), Queue10_UInt8.io.deq.bits) : printf_3 when Queue10_UInt8_1.io.deq.valid : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_3146 = asUInt(reset) node _T_3147 = eq(_T_3146, UInt<1>(0h0)) when _T_3147 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_3148 = asUInt(reset) node _T_3149 = eq(_T_3148, UInt<1>(0h0)) when _T_3149 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<1>(0h1), Queue10_UInt8_1.io.deq.bits) : printf_5 when Queue10_UInt8_2.io.deq.valid : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_3150 = asUInt(reset) node _T_3151 = eq(_T_3150, UInt<1>(0h0)) when _T_3151 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6 node _T_3152 = asUInt(reset) node _T_3153 = eq(_T_3152, UInt<1>(0h0)) when _T_3153 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<2>(0h2), Queue10_UInt8_2.io.deq.bits) : printf_7 when Queue10_UInt8_3.io.deq.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_3154 = asUInt(reset) node _T_3155 = eq(_T_3154, UInt<1>(0h0)) when _T_3155 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8 node _T_3156 = asUInt(reset) node _T_3157 = eq(_T_3156, UInt<1>(0h0)) when _T_3157 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<2>(0h3), Queue10_UInt8_3.io.deq.bits) : printf_9 when Queue10_UInt8_4.io.deq.valid : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_3158 = asUInt(reset) node _T_3159 = eq(_T_3158, UInt<1>(0h0)) when _T_3159 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10 node _T_3160 = asUInt(reset) node _T_3161 = eq(_T_3160, UInt<1>(0h0)) when _T_3161 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<3>(0h4), Queue10_UInt8_4.io.deq.bits) : printf_11 when Queue10_UInt8_5.io.deq.valid : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _T_3162 = asUInt(reset) node _T_3163 = eq(_T_3162, UInt<1>(0h0)) when _T_3163 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12 node _T_3164 = asUInt(reset) node _T_3165 = eq(_T_3164, UInt<1>(0h0)) when _T_3165 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<3>(0h5), Queue10_UInt8_5.io.deq.bits) : printf_13 when Queue10_UInt8_6.io.deq.valid : regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_3166 = asUInt(reset) node _T_3167 = eq(_T_3166, UInt<1>(0h0)) when _T_3167 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14 node _T_3168 = asUInt(reset) node _T_3169 = eq(_T_3168, UInt<1>(0h0)) when _T_3169 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<3>(0h6), Queue10_UInt8_6.io.deq.bits) : printf_15 when Queue10_UInt8_7.io.deq.valid : regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_3170 = asUInt(reset) node _T_3171 = eq(_T_3170, UInt<1>(0h0)) when _T_3171 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16 node _T_3172 = asUInt(reset) node _T_3173 = eq(_T_3172, UInt<1>(0h0)) when _T_3173 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<3>(0h7), Queue10_UInt8_7.io.deq.bits) : printf_17 when Queue10_UInt8_8.io.deq.valid : regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_3174 = asUInt(reset) node _T_3175 = eq(_T_3174, UInt<1>(0h0)) when _T_3175 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18 node _T_3176 = asUInt(reset) node _T_3177 = eq(_T_3176, UInt<1>(0h0)) when _T_3177 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0h8), Queue10_UInt8_8.io.deq.bits) : printf_19 when Queue10_UInt8_9.io.deq.valid : regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_3178 = asUInt(reset) node _T_3179 = eq(_T_3178, UInt<1>(0h0)) when _T_3179 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20 node _T_3180 = asUInt(reset) node _T_3181 = eq(_T_3180, UInt<1>(0h0)) when _T_3181 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0h9), Queue10_UInt8_9.io.deq.bits) : printf_21 when Queue10_UInt8_10.io.deq.valid : regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_3182 = asUInt(reset) node _T_3183 = eq(_T_3182, UInt<1>(0h0)) when _T_3183 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22 node _T_3184 = asUInt(reset) node _T_3185 = eq(_T_3184, UInt<1>(0h0)) when _T_3185 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0ha), Queue10_UInt8_10.io.deq.bits) : printf_23 when Queue10_UInt8_11.io.deq.valid : regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_3186 = asUInt(reset) node _T_3187 = eq(_T_3186, UInt<1>(0h0)) when _T_3187 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24 node _T_3188 = asUInt(reset) node _T_3189 = eq(_T_3188, UInt<1>(0h0)) when _T_3189 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0hb), Queue10_UInt8_11.io.deq.bits) : printf_25 when Queue10_UInt8_12.io.deq.valid : regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_3190 = asUInt(reset) node _T_3191 = eq(_T_3190, UInt<1>(0h0)) when _T_3191 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26 node _T_3192 = asUInt(reset) node _T_3193 = eq(_T_3192, UInt<1>(0h0)) when _T_3193 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0hc), Queue10_UInt8_12.io.deq.bits) : printf_27 when Queue10_UInt8_13.io.deq.valid : regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_3194 = asUInt(reset) node _T_3195 = eq(_T_3194, UInt<1>(0h0)) when _T_3195 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28 node _T_3196 = asUInt(reset) node _T_3197 = eq(_T_3196, UInt<1>(0h0)) when _T_3197 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0hd), Queue10_UInt8_13.io.deq.bits) : printf_29 when Queue10_UInt8_14.io.deq.valid : regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_3198 = asUInt(reset) node _T_3199 = eq(_T_3198, UInt<1>(0h0)) when _T_3199 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_30 node _T_3200 = asUInt(reset) node _T_3201 = eq(_T_3200, UInt<1>(0h0)) when _T_3201 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0he), Queue10_UInt8_14.io.deq.bits) : printf_31 when Queue10_UInt8_15.io.deq.valid : regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_3202 = asUInt(reset) node _T_3203 = eq(_T_3202, UInt<1>(0h0)) when _T_3203 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_32 node _T_3204 = asUInt(reset) node _T_3205 = eq(_T_3204, UInt<1>(0h0)) when _T_3205 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0hf), Queue10_UInt8_15.io.deq.bits) : printf_33 when Queue10_UInt8_16.io.deq.valid : regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_3206 = asUInt(reset) node _T_3207 = eq(_T_3206, UInt<1>(0h0)) when _T_3207 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_34 node _T_3208 = asUInt(reset) node _T_3209 = eq(_T_3208, UInt<1>(0h0)) when _T_3209 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h10), Queue10_UInt8_16.io.deq.bits) : printf_35 when Queue10_UInt8_17.io.deq.valid : regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_3210 = asUInt(reset) node _T_3211 = eq(_T_3210, UInt<1>(0h0)) when _T_3211 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_36 node _T_3212 = asUInt(reset) node _T_3213 = eq(_T_3212, UInt<1>(0h0)) when _T_3213 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h11), Queue10_UInt8_17.io.deq.bits) : printf_37 when Queue10_UInt8_18.io.deq.valid : regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_3214 = asUInt(reset) node _T_3215 = eq(_T_3214, UInt<1>(0h0)) when _T_3215 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_38 node _T_3216 = asUInt(reset) node _T_3217 = eq(_T_3216, UInt<1>(0h0)) when _T_3217 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h12), Queue10_UInt8_18.io.deq.bits) : printf_39 when Queue10_UInt8_19.io.deq.valid : regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1)) node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1) connect loginfo_cycles_20, _loginfo_cycles_T_41 node _T_3218 = asUInt(reset) node _T_3219 = eq(_T_3218, UInt<1>(0h0)) when _T_3219 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_40 node _T_3220 = asUInt(reset) node _T_3221 = eq(_T_3220, UInt<1>(0h0)) when _T_3221 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h13), Queue10_UInt8_19.io.deq.bits) : printf_41 when Queue10_UInt8_20.io.deq.valid : regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1)) node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1) connect loginfo_cycles_21, _loginfo_cycles_T_43 node _T_3222 = asUInt(reset) node _T_3223 = eq(_T_3222, UInt<1>(0h0)) when _T_3223 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_42 node _T_3224 = asUInt(reset) node _T_3225 = eq(_T_3224, UInt<1>(0h0)) when _T_3225 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h14), Queue10_UInt8_20.io.deq.bits) : printf_43 when Queue10_UInt8_21.io.deq.valid : regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1)) node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1) connect loginfo_cycles_22, _loginfo_cycles_T_45 node _T_3226 = asUInt(reset) node _T_3227 = eq(_T_3226, UInt<1>(0h0)) when _T_3227 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_44 node _T_3228 = asUInt(reset) node _T_3229 = eq(_T_3228, UInt<1>(0h0)) when _T_3229 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h15), Queue10_UInt8_21.io.deq.bits) : printf_45 when Queue10_UInt8_22.io.deq.valid : regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1)) node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1) connect loginfo_cycles_23, _loginfo_cycles_T_47 node _T_3230 = asUInt(reset) node _T_3231 = eq(_T_3230, UInt<1>(0h0)) when _T_3231 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_46 node _T_3232 = asUInt(reset) node _T_3233 = eq(_T_3232, UInt<1>(0h0)) when _T_3233 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h16), Queue10_UInt8_22.io.deq.bits) : printf_47 when Queue10_UInt8_23.io.deq.valid : regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1)) node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1) connect loginfo_cycles_24, _loginfo_cycles_T_49 node _T_3234 = asUInt(reset) node _T_3235 = eq(_T_3234, UInt<1>(0h0)) when _T_3235 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_48 node _T_3236 = asUInt(reset) node _T_3237 = eq(_T_3236, UInt<1>(0h0)) when _T_3237 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h17), Queue10_UInt8_23.io.deq.bits) : printf_49 when Queue10_UInt8_24.io.deq.valid : regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1)) node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1) connect loginfo_cycles_25, _loginfo_cycles_T_51 node _T_3238 = asUInt(reset) node _T_3239 = eq(_T_3238, UInt<1>(0h0)) when _T_3239 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_50 node _T_3240 = asUInt(reset) node _T_3241 = eq(_T_3240, UInt<1>(0h0)) when _T_3241 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h18), Queue10_UInt8_24.io.deq.bits) : printf_51 when Queue10_UInt8_25.io.deq.valid : regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1)) node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1) connect loginfo_cycles_26, _loginfo_cycles_T_53 node _T_3242 = asUInt(reset) node _T_3243 = eq(_T_3242, UInt<1>(0h0)) when _T_3243 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_52 node _T_3244 = asUInt(reset) node _T_3245 = eq(_T_3244, UInt<1>(0h0)) when _T_3245 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h19), Queue10_UInt8_25.io.deq.bits) : printf_53 when Queue10_UInt8_26.io.deq.valid : regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1)) node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1) connect loginfo_cycles_27, _loginfo_cycles_T_55 node _T_3246 = asUInt(reset) node _T_3247 = eq(_T_3246, UInt<1>(0h0)) when _T_3247 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_54 node _T_3248 = asUInt(reset) node _T_3249 = eq(_T_3248, UInt<1>(0h0)) when _T_3249 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1a), Queue10_UInt8_26.io.deq.bits) : printf_55 when Queue10_UInt8_27.io.deq.valid : regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1)) node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1) connect loginfo_cycles_28, _loginfo_cycles_T_57 node _T_3250 = asUInt(reset) node _T_3251 = eq(_T_3250, UInt<1>(0h0)) when _T_3251 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_56 node _T_3252 = asUInt(reset) node _T_3253 = eq(_T_3252, UInt<1>(0h0)) when _T_3253 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1b), Queue10_UInt8_27.io.deq.bits) : printf_57 when Queue10_UInt8_28.io.deq.valid : regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1)) node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1) connect loginfo_cycles_29, _loginfo_cycles_T_59 node _T_3254 = asUInt(reset) node _T_3255 = eq(_T_3254, UInt<1>(0h0)) when _T_3255 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_58 node _T_3256 = asUInt(reset) node _T_3257 = eq(_T_3256, UInt<1>(0h0)) when _T_3257 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1c), Queue10_UInt8_28.io.deq.bits) : printf_59 when Queue10_UInt8_29.io.deq.valid : regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1)) node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1) connect loginfo_cycles_30, _loginfo_cycles_T_61 node _T_3258 = asUInt(reset) node _T_3259 = eq(_T_3258, UInt<1>(0h0)) when _T_3259 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_60 node _T_3260 = asUInt(reset) node _T_3261 = eq(_T_3260, UInt<1>(0h0)) when _T_3261 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1d), Queue10_UInt8_29.io.deq.bits) : printf_61 when Queue10_UInt8_30.io.deq.valid : regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1)) node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1) connect loginfo_cycles_31, _loginfo_cycles_T_63 node _T_3262 = asUInt(reset) node _T_3263 = eq(_T_3262, UInt<1>(0h0)) when _T_3263 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_62 node _T_3264 = asUInt(reset) node _T_3265 = eq(_T_3264, UInt<1>(0h0)) when _T_3265 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1e), Queue10_UInt8_30.io.deq.bits) : printf_63 when Queue10_UInt8_31.io.deq.valid : regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1)) node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1) connect loginfo_cycles_32, _loginfo_cycles_T_65 node _T_3266 = asUInt(reset) node _T_3267 = eq(_T_3266, UInt<1>(0h0)) when _T_3267 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_64 node _T_3268 = asUInt(reset) node _T_3269 = eq(_T_3268, UInt<1>(0h0)) when _T_3269 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1f), Queue10_UInt8_31.io.deq.bits) : printf_65 regreset read_start_index : UInt<6>, clock, reset, UInt<6>(0h0) wire remapVecData : UInt<8>[32] wire remapVecValids : UInt<1>[32] wire remapVecReadys : UInt<1>[32] connect remapVecData[0], UInt<1>(0h0) connect remapVecValids[0], UInt<1>(0h0) connect Queue10_UInt8.io.deq.ready, UInt<1>(0h0) connect remapVecData[1], UInt<1>(0h0) connect remapVecValids[1], UInt<1>(0h0) connect Queue10_UInt8_1.io.deq.ready, UInt<1>(0h0) connect remapVecData[2], UInt<1>(0h0) connect remapVecValids[2], UInt<1>(0h0) connect Queue10_UInt8_2.io.deq.ready, UInt<1>(0h0) connect remapVecData[3], UInt<1>(0h0) connect remapVecValids[3], UInt<1>(0h0) connect Queue10_UInt8_3.io.deq.ready, UInt<1>(0h0) connect remapVecData[4], UInt<1>(0h0) connect remapVecValids[4], UInt<1>(0h0) connect Queue10_UInt8_4.io.deq.ready, UInt<1>(0h0) connect remapVecData[5], UInt<1>(0h0) connect remapVecValids[5], UInt<1>(0h0) connect Queue10_UInt8_5.io.deq.ready, UInt<1>(0h0) connect remapVecData[6], UInt<1>(0h0) connect remapVecValids[6], UInt<1>(0h0) connect Queue10_UInt8_6.io.deq.ready, UInt<1>(0h0) connect remapVecData[7], UInt<1>(0h0) connect remapVecValids[7], UInt<1>(0h0) connect Queue10_UInt8_7.io.deq.ready, UInt<1>(0h0) connect remapVecData[8], UInt<1>(0h0) connect remapVecValids[8], UInt<1>(0h0) connect Queue10_UInt8_8.io.deq.ready, UInt<1>(0h0) connect remapVecData[9], UInt<1>(0h0) connect remapVecValids[9], UInt<1>(0h0) connect Queue10_UInt8_9.io.deq.ready, UInt<1>(0h0) connect remapVecData[10], UInt<1>(0h0) connect remapVecValids[10], UInt<1>(0h0) connect Queue10_UInt8_10.io.deq.ready, UInt<1>(0h0) connect remapVecData[11], UInt<1>(0h0) connect remapVecValids[11], UInt<1>(0h0) connect Queue10_UInt8_11.io.deq.ready, UInt<1>(0h0) connect remapVecData[12], UInt<1>(0h0) connect remapVecValids[12], UInt<1>(0h0) connect Queue10_UInt8_12.io.deq.ready, UInt<1>(0h0) connect remapVecData[13], UInt<1>(0h0) connect remapVecValids[13], UInt<1>(0h0) connect Queue10_UInt8_13.io.deq.ready, UInt<1>(0h0) connect remapVecData[14], UInt<1>(0h0) connect remapVecValids[14], UInt<1>(0h0) connect Queue10_UInt8_14.io.deq.ready, UInt<1>(0h0) connect remapVecData[15], UInt<1>(0h0) connect remapVecValids[15], UInt<1>(0h0) connect Queue10_UInt8_15.io.deq.ready, UInt<1>(0h0) connect remapVecData[16], UInt<1>(0h0) connect remapVecValids[16], UInt<1>(0h0) connect Queue10_UInt8_16.io.deq.ready, UInt<1>(0h0) connect remapVecData[17], UInt<1>(0h0) connect remapVecValids[17], UInt<1>(0h0) connect Queue10_UInt8_17.io.deq.ready, UInt<1>(0h0) connect remapVecData[18], UInt<1>(0h0) connect remapVecValids[18], UInt<1>(0h0) connect Queue10_UInt8_18.io.deq.ready, UInt<1>(0h0) connect remapVecData[19], UInt<1>(0h0) connect remapVecValids[19], UInt<1>(0h0) connect Queue10_UInt8_19.io.deq.ready, UInt<1>(0h0) connect remapVecData[20], UInt<1>(0h0) connect remapVecValids[20], UInt<1>(0h0) connect Queue10_UInt8_20.io.deq.ready, UInt<1>(0h0) connect remapVecData[21], UInt<1>(0h0) connect remapVecValids[21], UInt<1>(0h0) connect Queue10_UInt8_21.io.deq.ready, UInt<1>(0h0) connect remapVecData[22], UInt<1>(0h0) connect remapVecValids[22], UInt<1>(0h0) connect Queue10_UInt8_22.io.deq.ready, UInt<1>(0h0) connect remapVecData[23], UInt<1>(0h0) connect remapVecValids[23], UInt<1>(0h0) connect Queue10_UInt8_23.io.deq.ready, UInt<1>(0h0) connect remapVecData[24], UInt<1>(0h0) connect remapVecValids[24], UInt<1>(0h0) connect Queue10_UInt8_24.io.deq.ready, UInt<1>(0h0) connect remapVecData[25], UInt<1>(0h0) connect remapVecValids[25], UInt<1>(0h0) connect Queue10_UInt8_25.io.deq.ready, UInt<1>(0h0) connect remapVecData[26], UInt<1>(0h0) connect remapVecValids[26], UInt<1>(0h0) connect Queue10_UInt8_26.io.deq.ready, UInt<1>(0h0) connect remapVecData[27], UInt<1>(0h0) connect remapVecValids[27], UInt<1>(0h0) connect Queue10_UInt8_27.io.deq.ready, UInt<1>(0h0) connect remapVecData[28], UInt<1>(0h0) connect remapVecValids[28], UInt<1>(0h0) connect Queue10_UInt8_28.io.deq.ready, UInt<1>(0h0) connect remapVecData[29], UInt<1>(0h0) connect remapVecValids[29], UInt<1>(0h0) connect Queue10_UInt8_29.io.deq.ready, UInt<1>(0h0) connect remapVecData[30], UInt<1>(0h0) connect remapVecValids[30], UInt<1>(0h0) connect Queue10_UInt8_30.io.deq.ready, UInt<1>(0h0) connect remapVecData[31], UInt<1>(0h0) connect remapVecValids[31], UInt<1>(0h0) connect Queue10_UInt8_31.io.deq.ready, UInt<1>(0h0) node _remapindex_T = add(UInt<1>(0h0), read_start_index) node remapindex = rem(_remapindex_T, UInt<6>(0h20)) node _T_3270 = eq(UInt<1>(0h0), remapindex) when _T_3270 : connect remapVecData[0], Queue10_UInt8.io.deq.bits connect remapVecValids[0], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[0] node _T_3271 = eq(UInt<1>(0h1), remapindex) when _T_3271 : connect remapVecData[0], Queue10_UInt8_1.io.deq.bits connect remapVecValids[0], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[0] node _T_3272 = eq(UInt<2>(0h2), remapindex) when _T_3272 : connect remapVecData[0], Queue10_UInt8_2.io.deq.bits connect remapVecValids[0], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[0] node _T_3273 = eq(UInt<2>(0h3), remapindex) when _T_3273 : connect remapVecData[0], Queue10_UInt8_3.io.deq.bits connect remapVecValids[0], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[0] node _T_3274 = eq(UInt<3>(0h4), remapindex) when _T_3274 : connect remapVecData[0], Queue10_UInt8_4.io.deq.bits connect remapVecValids[0], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[0] node _T_3275 = eq(UInt<3>(0h5), remapindex) when _T_3275 : connect remapVecData[0], Queue10_UInt8_5.io.deq.bits connect remapVecValids[0], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[0] node _T_3276 = eq(UInt<3>(0h6), remapindex) when _T_3276 : connect remapVecData[0], Queue10_UInt8_6.io.deq.bits connect remapVecValids[0], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[0] node _T_3277 = eq(UInt<3>(0h7), remapindex) when _T_3277 : connect remapVecData[0], Queue10_UInt8_7.io.deq.bits connect remapVecValids[0], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[0] node _T_3278 = eq(UInt<4>(0h8), remapindex) when _T_3278 : connect remapVecData[0], Queue10_UInt8_8.io.deq.bits connect remapVecValids[0], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[0] node _T_3279 = eq(UInt<4>(0h9), remapindex) when _T_3279 : connect remapVecData[0], Queue10_UInt8_9.io.deq.bits connect remapVecValids[0], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[0] node _T_3280 = eq(UInt<4>(0ha), remapindex) when _T_3280 : connect remapVecData[0], Queue10_UInt8_10.io.deq.bits connect remapVecValids[0], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[0] node _T_3281 = eq(UInt<4>(0hb), remapindex) when _T_3281 : connect remapVecData[0], Queue10_UInt8_11.io.deq.bits connect remapVecValids[0], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[0] node _T_3282 = eq(UInt<4>(0hc), remapindex) when _T_3282 : connect remapVecData[0], Queue10_UInt8_12.io.deq.bits connect remapVecValids[0], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[0] node _T_3283 = eq(UInt<4>(0hd), remapindex) when _T_3283 : connect remapVecData[0], Queue10_UInt8_13.io.deq.bits connect remapVecValids[0], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[0] node _T_3284 = eq(UInt<4>(0he), remapindex) when _T_3284 : connect remapVecData[0], Queue10_UInt8_14.io.deq.bits connect remapVecValids[0], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[0] node _T_3285 = eq(UInt<4>(0hf), remapindex) when _T_3285 : connect remapVecData[0], Queue10_UInt8_15.io.deq.bits connect remapVecValids[0], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[0] node _T_3286 = eq(UInt<5>(0h10), remapindex) when _T_3286 : connect remapVecData[0], Queue10_UInt8_16.io.deq.bits connect remapVecValids[0], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[0] node _T_3287 = eq(UInt<5>(0h11), remapindex) when _T_3287 : connect remapVecData[0], Queue10_UInt8_17.io.deq.bits connect remapVecValids[0], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[0] node _T_3288 = eq(UInt<5>(0h12), remapindex) when _T_3288 : connect remapVecData[0], Queue10_UInt8_18.io.deq.bits connect remapVecValids[0], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[0] node _T_3289 = eq(UInt<5>(0h13), remapindex) when _T_3289 : connect remapVecData[0], Queue10_UInt8_19.io.deq.bits connect remapVecValids[0], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[0] node _T_3290 = eq(UInt<5>(0h14), remapindex) when _T_3290 : connect remapVecData[0], Queue10_UInt8_20.io.deq.bits connect remapVecValids[0], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[0] node _T_3291 = eq(UInt<5>(0h15), remapindex) when _T_3291 : connect remapVecData[0], Queue10_UInt8_21.io.deq.bits connect remapVecValids[0], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[0] node _T_3292 = eq(UInt<5>(0h16), remapindex) when _T_3292 : connect remapVecData[0], Queue10_UInt8_22.io.deq.bits connect remapVecValids[0], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[0] node _T_3293 = eq(UInt<5>(0h17), remapindex) when _T_3293 : connect remapVecData[0], Queue10_UInt8_23.io.deq.bits connect remapVecValids[0], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[0] node _T_3294 = eq(UInt<5>(0h18), remapindex) when _T_3294 : connect remapVecData[0], Queue10_UInt8_24.io.deq.bits connect remapVecValids[0], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[0] node _T_3295 = eq(UInt<5>(0h19), remapindex) when _T_3295 : connect remapVecData[0], Queue10_UInt8_25.io.deq.bits connect remapVecValids[0], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[0] node _T_3296 = eq(UInt<5>(0h1a), remapindex) when _T_3296 : connect remapVecData[0], Queue10_UInt8_26.io.deq.bits connect remapVecValids[0], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[0] node _T_3297 = eq(UInt<5>(0h1b), remapindex) when _T_3297 : connect remapVecData[0], Queue10_UInt8_27.io.deq.bits connect remapVecValids[0], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[0] node _T_3298 = eq(UInt<5>(0h1c), remapindex) when _T_3298 : connect remapVecData[0], Queue10_UInt8_28.io.deq.bits connect remapVecValids[0], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[0] node _T_3299 = eq(UInt<5>(0h1d), remapindex) when _T_3299 : connect remapVecData[0], Queue10_UInt8_29.io.deq.bits connect remapVecValids[0], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[0] node _T_3300 = eq(UInt<5>(0h1e), remapindex) when _T_3300 : connect remapVecData[0], Queue10_UInt8_30.io.deq.bits connect remapVecValids[0], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[0] node _T_3301 = eq(UInt<5>(0h1f), remapindex) when _T_3301 : connect remapVecData[0], Queue10_UInt8_31.io.deq.bits connect remapVecValids[0], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[0] node _remapindex_T_1 = add(UInt<1>(0h1), read_start_index) node remapindex_1 = rem(_remapindex_T_1, UInt<6>(0h20)) node _T_3302 = eq(UInt<1>(0h0), remapindex_1) when _T_3302 : connect remapVecData[1], Queue10_UInt8.io.deq.bits connect remapVecValids[1], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[1] node _T_3303 = eq(UInt<1>(0h1), remapindex_1) when _T_3303 : connect remapVecData[1], Queue10_UInt8_1.io.deq.bits connect remapVecValids[1], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[1] node _T_3304 = eq(UInt<2>(0h2), remapindex_1) when _T_3304 : connect remapVecData[1], Queue10_UInt8_2.io.deq.bits connect remapVecValids[1], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[1] node _T_3305 = eq(UInt<2>(0h3), remapindex_1) when _T_3305 : connect remapVecData[1], Queue10_UInt8_3.io.deq.bits connect remapVecValids[1], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[1] node _T_3306 = eq(UInt<3>(0h4), remapindex_1) when _T_3306 : connect remapVecData[1], Queue10_UInt8_4.io.deq.bits connect remapVecValids[1], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[1] node _T_3307 = eq(UInt<3>(0h5), remapindex_1) when _T_3307 : connect remapVecData[1], Queue10_UInt8_5.io.deq.bits connect remapVecValids[1], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[1] node _T_3308 = eq(UInt<3>(0h6), remapindex_1) when _T_3308 : connect remapVecData[1], Queue10_UInt8_6.io.deq.bits connect remapVecValids[1], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[1] node _T_3309 = eq(UInt<3>(0h7), remapindex_1) when _T_3309 : connect remapVecData[1], Queue10_UInt8_7.io.deq.bits connect remapVecValids[1], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[1] node _T_3310 = eq(UInt<4>(0h8), remapindex_1) when _T_3310 : connect remapVecData[1], Queue10_UInt8_8.io.deq.bits connect remapVecValids[1], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[1] node _T_3311 = eq(UInt<4>(0h9), remapindex_1) when _T_3311 : connect remapVecData[1], Queue10_UInt8_9.io.deq.bits connect remapVecValids[1], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[1] node _T_3312 = eq(UInt<4>(0ha), remapindex_1) when _T_3312 : connect remapVecData[1], Queue10_UInt8_10.io.deq.bits connect remapVecValids[1], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[1] node _T_3313 = eq(UInt<4>(0hb), remapindex_1) when _T_3313 : connect remapVecData[1], Queue10_UInt8_11.io.deq.bits connect remapVecValids[1], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[1] node _T_3314 = eq(UInt<4>(0hc), remapindex_1) when _T_3314 : connect remapVecData[1], Queue10_UInt8_12.io.deq.bits connect remapVecValids[1], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[1] node _T_3315 = eq(UInt<4>(0hd), remapindex_1) when _T_3315 : connect remapVecData[1], Queue10_UInt8_13.io.deq.bits connect remapVecValids[1], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[1] node _T_3316 = eq(UInt<4>(0he), remapindex_1) when _T_3316 : connect remapVecData[1], Queue10_UInt8_14.io.deq.bits connect remapVecValids[1], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[1] node _T_3317 = eq(UInt<4>(0hf), remapindex_1) when _T_3317 : connect remapVecData[1], Queue10_UInt8_15.io.deq.bits connect remapVecValids[1], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[1] node _T_3318 = eq(UInt<5>(0h10), remapindex_1) when _T_3318 : connect remapVecData[1], Queue10_UInt8_16.io.deq.bits connect remapVecValids[1], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[1] node _T_3319 = eq(UInt<5>(0h11), remapindex_1) when _T_3319 : connect remapVecData[1], Queue10_UInt8_17.io.deq.bits connect remapVecValids[1], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[1] node _T_3320 = eq(UInt<5>(0h12), remapindex_1) when _T_3320 : connect remapVecData[1], Queue10_UInt8_18.io.deq.bits connect remapVecValids[1], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[1] node _T_3321 = eq(UInt<5>(0h13), remapindex_1) when _T_3321 : connect remapVecData[1], Queue10_UInt8_19.io.deq.bits connect remapVecValids[1], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[1] node _T_3322 = eq(UInt<5>(0h14), remapindex_1) when _T_3322 : connect remapVecData[1], Queue10_UInt8_20.io.deq.bits connect remapVecValids[1], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[1] node _T_3323 = eq(UInt<5>(0h15), remapindex_1) when _T_3323 : connect remapVecData[1], Queue10_UInt8_21.io.deq.bits connect remapVecValids[1], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[1] node _T_3324 = eq(UInt<5>(0h16), remapindex_1) when _T_3324 : connect remapVecData[1], Queue10_UInt8_22.io.deq.bits connect remapVecValids[1], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[1] node _T_3325 = eq(UInt<5>(0h17), remapindex_1) when _T_3325 : connect remapVecData[1], Queue10_UInt8_23.io.deq.bits connect remapVecValids[1], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[1] node _T_3326 = eq(UInt<5>(0h18), remapindex_1) when _T_3326 : connect remapVecData[1], Queue10_UInt8_24.io.deq.bits connect remapVecValids[1], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[1] node _T_3327 = eq(UInt<5>(0h19), remapindex_1) when _T_3327 : connect remapVecData[1], Queue10_UInt8_25.io.deq.bits connect remapVecValids[1], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[1] node _T_3328 = eq(UInt<5>(0h1a), remapindex_1) when _T_3328 : connect remapVecData[1], Queue10_UInt8_26.io.deq.bits connect remapVecValids[1], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[1] node _T_3329 = eq(UInt<5>(0h1b), remapindex_1) when _T_3329 : connect remapVecData[1], Queue10_UInt8_27.io.deq.bits connect remapVecValids[1], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[1] node _T_3330 = eq(UInt<5>(0h1c), remapindex_1) when _T_3330 : connect remapVecData[1], Queue10_UInt8_28.io.deq.bits connect remapVecValids[1], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[1] node _T_3331 = eq(UInt<5>(0h1d), remapindex_1) when _T_3331 : connect remapVecData[1], Queue10_UInt8_29.io.deq.bits connect remapVecValids[1], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[1] node _T_3332 = eq(UInt<5>(0h1e), remapindex_1) when _T_3332 : connect remapVecData[1], Queue10_UInt8_30.io.deq.bits connect remapVecValids[1], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[1] node _T_3333 = eq(UInt<5>(0h1f), remapindex_1) when _T_3333 : connect remapVecData[1], Queue10_UInt8_31.io.deq.bits connect remapVecValids[1], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[1] node _remapindex_T_2 = add(UInt<2>(0h2), read_start_index) node remapindex_2 = rem(_remapindex_T_2, UInt<6>(0h20)) node _T_3334 = eq(UInt<1>(0h0), remapindex_2) when _T_3334 : connect remapVecData[2], Queue10_UInt8.io.deq.bits connect remapVecValids[2], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[2] node _T_3335 = eq(UInt<1>(0h1), remapindex_2) when _T_3335 : connect remapVecData[2], Queue10_UInt8_1.io.deq.bits connect remapVecValids[2], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[2] node _T_3336 = eq(UInt<2>(0h2), remapindex_2) when _T_3336 : connect remapVecData[2], Queue10_UInt8_2.io.deq.bits connect remapVecValids[2], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[2] node _T_3337 = eq(UInt<2>(0h3), remapindex_2) when _T_3337 : connect remapVecData[2], Queue10_UInt8_3.io.deq.bits connect remapVecValids[2], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[2] node _T_3338 = eq(UInt<3>(0h4), remapindex_2) when _T_3338 : connect remapVecData[2], Queue10_UInt8_4.io.deq.bits connect remapVecValids[2], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[2] node _T_3339 = eq(UInt<3>(0h5), remapindex_2) when _T_3339 : connect remapVecData[2], Queue10_UInt8_5.io.deq.bits connect remapVecValids[2], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[2] node _T_3340 = eq(UInt<3>(0h6), remapindex_2) when _T_3340 : connect remapVecData[2], Queue10_UInt8_6.io.deq.bits connect remapVecValids[2], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[2] node _T_3341 = eq(UInt<3>(0h7), remapindex_2) when _T_3341 : connect remapVecData[2], Queue10_UInt8_7.io.deq.bits connect remapVecValids[2], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[2] node _T_3342 = eq(UInt<4>(0h8), remapindex_2) when _T_3342 : connect remapVecData[2], Queue10_UInt8_8.io.deq.bits connect remapVecValids[2], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[2] node _T_3343 = eq(UInt<4>(0h9), remapindex_2) when _T_3343 : connect remapVecData[2], Queue10_UInt8_9.io.deq.bits connect remapVecValids[2], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[2] node _T_3344 = eq(UInt<4>(0ha), remapindex_2) when _T_3344 : connect remapVecData[2], Queue10_UInt8_10.io.deq.bits connect remapVecValids[2], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[2] node _T_3345 = eq(UInt<4>(0hb), remapindex_2) when _T_3345 : connect remapVecData[2], Queue10_UInt8_11.io.deq.bits connect remapVecValids[2], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[2] node _T_3346 = eq(UInt<4>(0hc), remapindex_2) when _T_3346 : connect remapVecData[2], Queue10_UInt8_12.io.deq.bits connect remapVecValids[2], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[2] node _T_3347 = eq(UInt<4>(0hd), remapindex_2) when _T_3347 : connect remapVecData[2], Queue10_UInt8_13.io.deq.bits connect remapVecValids[2], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[2] node _T_3348 = eq(UInt<4>(0he), remapindex_2) when _T_3348 : connect remapVecData[2], Queue10_UInt8_14.io.deq.bits connect remapVecValids[2], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[2] node _T_3349 = eq(UInt<4>(0hf), remapindex_2) when _T_3349 : connect remapVecData[2], Queue10_UInt8_15.io.deq.bits connect remapVecValids[2], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[2] node _T_3350 = eq(UInt<5>(0h10), remapindex_2) when _T_3350 : connect remapVecData[2], Queue10_UInt8_16.io.deq.bits connect remapVecValids[2], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[2] node _T_3351 = eq(UInt<5>(0h11), remapindex_2) when _T_3351 : connect remapVecData[2], Queue10_UInt8_17.io.deq.bits connect remapVecValids[2], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[2] node _T_3352 = eq(UInt<5>(0h12), remapindex_2) when _T_3352 : connect remapVecData[2], Queue10_UInt8_18.io.deq.bits connect remapVecValids[2], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[2] node _T_3353 = eq(UInt<5>(0h13), remapindex_2) when _T_3353 : connect remapVecData[2], Queue10_UInt8_19.io.deq.bits connect remapVecValids[2], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[2] node _T_3354 = eq(UInt<5>(0h14), remapindex_2) when _T_3354 : connect remapVecData[2], Queue10_UInt8_20.io.deq.bits connect remapVecValids[2], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[2] node _T_3355 = eq(UInt<5>(0h15), remapindex_2) when _T_3355 : connect remapVecData[2], Queue10_UInt8_21.io.deq.bits connect remapVecValids[2], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[2] node _T_3356 = eq(UInt<5>(0h16), remapindex_2) when _T_3356 : connect remapVecData[2], Queue10_UInt8_22.io.deq.bits connect remapVecValids[2], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[2] node _T_3357 = eq(UInt<5>(0h17), remapindex_2) when _T_3357 : connect remapVecData[2], Queue10_UInt8_23.io.deq.bits connect remapVecValids[2], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[2] node _T_3358 = eq(UInt<5>(0h18), remapindex_2) when _T_3358 : connect remapVecData[2], Queue10_UInt8_24.io.deq.bits connect remapVecValids[2], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[2] node _T_3359 = eq(UInt<5>(0h19), remapindex_2) when _T_3359 : connect remapVecData[2], Queue10_UInt8_25.io.deq.bits connect remapVecValids[2], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[2] node _T_3360 = eq(UInt<5>(0h1a), remapindex_2) when _T_3360 : connect remapVecData[2], Queue10_UInt8_26.io.deq.bits connect remapVecValids[2], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[2] node _T_3361 = eq(UInt<5>(0h1b), remapindex_2) when _T_3361 : connect remapVecData[2], Queue10_UInt8_27.io.deq.bits connect remapVecValids[2], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[2] node _T_3362 = eq(UInt<5>(0h1c), remapindex_2) when _T_3362 : connect remapVecData[2], Queue10_UInt8_28.io.deq.bits connect remapVecValids[2], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[2] node _T_3363 = eq(UInt<5>(0h1d), remapindex_2) when _T_3363 : connect remapVecData[2], Queue10_UInt8_29.io.deq.bits connect remapVecValids[2], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[2] node _T_3364 = eq(UInt<5>(0h1e), remapindex_2) when _T_3364 : connect remapVecData[2], Queue10_UInt8_30.io.deq.bits connect remapVecValids[2], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[2] node _T_3365 = eq(UInt<5>(0h1f), remapindex_2) when _T_3365 : connect remapVecData[2], Queue10_UInt8_31.io.deq.bits connect remapVecValids[2], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[2] node _remapindex_T_3 = add(UInt<2>(0h3), read_start_index) node remapindex_3 = rem(_remapindex_T_3, UInt<6>(0h20)) node _T_3366 = eq(UInt<1>(0h0), remapindex_3) when _T_3366 : connect remapVecData[3], Queue10_UInt8.io.deq.bits connect remapVecValids[3], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[3] node _T_3367 = eq(UInt<1>(0h1), remapindex_3) when _T_3367 : connect remapVecData[3], Queue10_UInt8_1.io.deq.bits connect remapVecValids[3], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[3] node _T_3368 = eq(UInt<2>(0h2), remapindex_3) when _T_3368 : connect remapVecData[3], Queue10_UInt8_2.io.deq.bits connect remapVecValids[3], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[3] node _T_3369 = eq(UInt<2>(0h3), remapindex_3) when _T_3369 : connect remapVecData[3], Queue10_UInt8_3.io.deq.bits connect remapVecValids[3], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[3] node _T_3370 = eq(UInt<3>(0h4), remapindex_3) when _T_3370 : connect remapVecData[3], Queue10_UInt8_4.io.deq.bits connect remapVecValids[3], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[3] node _T_3371 = eq(UInt<3>(0h5), remapindex_3) when _T_3371 : connect remapVecData[3], Queue10_UInt8_5.io.deq.bits connect remapVecValids[3], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[3] node _T_3372 = eq(UInt<3>(0h6), remapindex_3) when _T_3372 : connect remapVecData[3], Queue10_UInt8_6.io.deq.bits connect remapVecValids[3], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[3] node _T_3373 = eq(UInt<3>(0h7), remapindex_3) when _T_3373 : connect remapVecData[3], Queue10_UInt8_7.io.deq.bits connect remapVecValids[3], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[3] node _T_3374 = eq(UInt<4>(0h8), remapindex_3) when _T_3374 : connect remapVecData[3], Queue10_UInt8_8.io.deq.bits connect remapVecValids[3], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[3] node _T_3375 = eq(UInt<4>(0h9), remapindex_3) when _T_3375 : connect remapVecData[3], Queue10_UInt8_9.io.deq.bits connect remapVecValids[3], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[3] node _T_3376 = eq(UInt<4>(0ha), remapindex_3) when _T_3376 : connect remapVecData[3], Queue10_UInt8_10.io.deq.bits connect remapVecValids[3], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[3] node _T_3377 = eq(UInt<4>(0hb), remapindex_3) when _T_3377 : connect remapVecData[3], Queue10_UInt8_11.io.deq.bits connect remapVecValids[3], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[3] node _T_3378 = eq(UInt<4>(0hc), remapindex_3) when _T_3378 : connect remapVecData[3], Queue10_UInt8_12.io.deq.bits connect remapVecValids[3], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[3] node _T_3379 = eq(UInt<4>(0hd), remapindex_3) when _T_3379 : connect remapVecData[3], Queue10_UInt8_13.io.deq.bits connect remapVecValids[3], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[3] node _T_3380 = eq(UInt<4>(0he), remapindex_3) when _T_3380 : connect remapVecData[3], Queue10_UInt8_14.io.deq.bits connect remapVecValids[3], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[3] node _T_3381 = eq(UInt<4>(0hf), remapindex_3) when _T_3381 : connect remapVecData[3], Queue10_UInt8_15.io.deq.bits connect remapVecValids[3], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[3] node _T_3382 = eq(UInt<5>(0h10), remapindex_3) when _T_3382 : connect remapVecData[3], Queue10_UInt8_16.io.deq.bits connect remapVecValids[3], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[3] node _T_3383 = eq(UInt<5>(0h11), remapindex_3) when _T_3383 : connect remapVecData[3], Queue10_UInt8_17.io.deq.bits connect remapVecValids[3], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[3] node _T_3384 = eq(UInt<5>(0h12), remapindex_3) when _T_3384 : connect remapVecData[3], Queue10_UInt8_18.io.deq.bits connect remapVecValids[3], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[3] node _T_3385 = eq(UInt<5>(0h13), remapindex_3) when _T_3385 : connect remapVecData[3], Queue10_UInt8_19.io.deq.bits connect remapVecValids[3], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[3] node _T_3386 = eq(UInt<5>(0h14), remapindex_3) when _T_3386 : connect remapVecData[3], Queue10_UInt8_20.io.deq.bits connect remapVecValids[3], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[3] node _T_3387 = eq(UInt<5>(0h15), remapindex_3) when _T_3387 : connect remapVecData[3], Queue10_UInt8_21.io.deq.bits connect remapVecValids[3], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[3] node _T_3388 = eq(UInt<5>(0h16), remapindex_3) when _T_3388 : connect remapVecData[3], Queue10_UInt8_22.io.deq.bits connect remapVecValids[3], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[3] node _T_3389 = eq(UInt<5>(0h17), remapindex_3) when _T_3389 : connect remapVecData[3], Queue10_UInt8_23.io.deq.bits connect remapVecValids[3], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[3] node _T_3390 = eq(UInt<5>(0h18), remapindex_3) when _T_3390 : connect remapVecData[3], Queue10_UInt8_24.io.deq.bits connect remapVecValids[3], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[3] node _T_3391 = eq(UInt<5>(0h19), remapindex_3) when _T_3391 : connect remapVecData[3], Queue10_UInt8_25.io.deq.bits connect remapVecValids[3], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[3] node _T_3392 = eq(UInt<5>(0h1a), remapindex_3) when _T_3392 : connect remapVecData[3], Queue10_UInt8_26.io.deq.bits connect remapVecValids[3], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[3] node _T_3393 = eq(UInt<5>(0h1b), remapindex_3) when _T_3393 : connect remapVecData[3], Queue10_UInt8_27.io.deq.bits connect remapVecValids[3], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[3] node _T_3394 = eq(UInt<5>(0h1c), remapindex_3) when _T_3394 : connect remapVecData[3], Queue10_UInt8_28.io.deq.bits connect remapVecValids[3], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[3] node _T_3395 = eq(UInt<5>(0h1d), remapindex_3) when _T_3395 : connect remapVecData[3], Queue10_UInt8_29.io.deq.bits connect remapVecValids[3], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[3] node _T_3396 = eq(UInt<5>(0h1e), remapindex_3) when _T_3396 : connect remapVecData[3], Queue10_UInt8_30.io.deq.bits connect remapVecValids[3], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[3] node _T_3397 = eq(UInt<5>(0h1f), remapindex_3) when _T_3397 : connect remapVecData[3], Queue10_UInt8_31.io.deq.bits connect remapVecValids[3], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[3] node _remapindex_T_4 = add(UInt<3>(0h4), read_start_index) node remapindex_4 = rem(_remapindex_T_4, UInt<6>(0h20)) node _T_3398 = eq(UInt<1>(0h0), remapindex_4) when _T_3398 : connect remapVecData[4], Queue10_UInt8.io.deq.bits connect remapVecValids[4], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[4] node _T_3399 = eq(UInt<1>(0h1), remapindex_4) when _T_3399 : connect remapVecData[4], Queue10_UInt8_1.io.deq.bits connect remapVecValids[4], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[4] node _T_3400 = eq(UInt<2>(0h2), remapindex_4) when _T_3400 : connect remapVecData[4], Queue10_UInt8_2.io.deq.bits connect remapVecValids[4], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[4] node _T_3401 = eq(UInt<2>(0h3), remapindex_4) when _T_3401 : connect remapVecData[4], Queue10_UInt8_3.io.deq.bits connect remapVecValids[4], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[4] node _T_3402 = eq(UInt<3>(0h4), remapindex_4) when _T_3402 : connect remapVecData[4], Queue10_UInt8_4.io.deq.bits connect remapVecValids[4], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[4] node _T_3403 = eq(UInt<3>(0h5), remapindex_4) when _T_3403 : connect remapVecData[4], Queue10_UInt8_5.io.deq.bits connect remapVecValids[4], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[4] node _T_3404 = eq(UInt<3>(0h6), remapindex_4) when _T_3404 : connect remapVecData[4], Queue10_UInt8_6.io.deq.bits connect remapVecValids[4], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[4] node _T_3405 = eq(UInt<3>(0h7), remapindex_4) when _T_3405 : connect remapVecData[4], Queue10_UInt8_7.io.deq.bits connect remapVecValids[4], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[4] node _T_3406 = eq(UInt<4>(0h8), remapindex_4) when _T_3406 : connect remapVecData[4], Queue10_UInt8_8.io.deq.bits connect remapVecValids[4], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[4] node _T_3407 = eq(UInt<4>(0h9), remapindex_4) when _T_3407 : connect remapVecData[4], Queue10_UInt8_9.io.deq.bits connect remapVecValids[4], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[4] node _T_3408 = eq(UInt<4>(0ha), remapindex_4) when _T_3408 : connect remapVecData[4], Queue10_UInt8_10.io.deq.bits connect remapVecValids[4], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[4] node _T_3409 = eq(UInt<4>(0hb), remapindex_4) when _T_3409 : connect remapVecData[4], Queue10_UInt8_11.io.deq.bits connect remapVecValids[4], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[4] node _T_3410 = eq(UInt<4>(0hc), remapindex_4) when _T_3410 : connect remapVecData[4], Queue10_UInt8_12.io.deq.bits connect remapVecValids[4], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[4] node _T_3411 = eq(UInt<4>(0hd), remapindex_4) when _T_3411 : connect remapVecData[4], Queue10_UInt8_13.io.deq.bits connect remapVecValids[4], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[4] node _T_3412 = eq(UInt<4>(0he), remapindex_4) when _T_3412 : connect remapVecData[4], Queue10_UInt8_14.io.deq.bits connect remapVecValids[4], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[4] node _T_3413 = eq(UInt<4>(0hf), remapindex_4) when _T_3413 : connect remapVecData[4], Queue10_UInt8_15.io.deq.bits connect remapVecValids[4], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[4] node _T_3414 = eq(UInt<5>(0h10), remapindex_4) when _T_3414 : connect remapVecData[4], Queue10_UInt8_16.io.deq.bits connect remapVecValids[4], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[4] node _T_3415 = eq(UInt<5>(0h11), remapindex_4) when _T_3415 : connect remapVecData[4], Queue10_UInt8_17.io.deq.bits connect remapVecValids[4], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[4] node _T_3416 = eq(UInt<5>(0h12), remapindex_4) when _T_3416 : connect remapVecData[4], Queue10_UInt8_18.io.deq.bits connect remapVecValids[4], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[4] node _T_3417 = eq(UInt<5>(0h13), remapindex_4) when _T_3417 : connect remapVecData[4], Queue10_UInt8_19.io.deq.bits connect remapVecValids[4], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[4] node _T_3418 = eq(UInt<5>(0h14), remapindex_4) when _T_3418 : connect remapVecData[4], Queue10_UInt8_20.io.deq.bits connect remapVecValids[4], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[4] node _T_3419 = eq(UInt<5>(0h15), remapindex_4) when _T_3419 : connect remapVecData[4], Queue10_UInt8_21.io.deq.bits connect remapVecValids[4], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[4] node _T_3420 = eq(UInt<5>(0h16), remapindex_4) when _T_3420 : connect remapVecData[4], Queue10_UInt8_22.io.deq.bits connect remapVecValids[4], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[4] node _T_3421 = eq(UInt<5>(0h17), remapindex_4) when _T_3421 : connect remapVecData[4], Queue10_UInt8_23.io.deq.bits connect remapVecValids[4], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[4] node _T_3422 = eq(UInt<5>(0h18), remapindex_4) when _T_3422 : connect remapVecData[4], Queue10_UInt8_24.io.deq.bits connect remapVecValids[4], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[4] node _T_3423 = eq(UInt<5>(0h19), remapindex_4) when _T_3423 : connect remapVecData[4], Queue10_UInt8_25.io.deq.bits connect remapVecValids[4], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[4] node _T_3424 = eq(UInt<5>(0h1a), remapindex_4) when _T_3424 : connect remapVecData[4], Queue10_UInt8_26.io.deq.bits connect remapVecValids[4], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[4] node _T_3425 = eq(UInt<5>(0h1b), remapindex_4) when _T_3425 : connect remapVecData[4], Queue10_UInt8_27.io.deq.bits connect remapVecValids[4], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[4] node _T_3426 = eq(UInt<5>(0h1c), remapindex_4) when _T_3426 : connect remapVecData[4], Queue10_UInt8_28.io.deq.bits connect remapVecValids[4], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[4] node _T_3427 = eq(UInt<5>(0h1d), remapindex_4) when _T_3427 : connect remapVecData[4], Queue10_UInt8_29.io.deq.bits connect remapVecValids[4], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[4] node _T_3428 = eq(UInt<5>(0h1e), remapindex_4) when _T_3428 : connect remapVecData[4], Queue10_UInt8_30.io.deq.bits connect remapVecValids[4], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[4] node _T_3429 = eq(UInt<5>(0h1f), remapindex_4) when _T_3429 : connect remapVecData[4], Queue10_UInt8_31.io.deq.bits connect remapVecValids[4], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[4] node _remapindex_T_5 = add(UInt<3>(0h5), read_start_index) node remapindex_5 = rem(_remapindex_T_5, UInt<6>(0h20)) node _T_3430 = eq(UInt<1>(0h0), remapindex_5) when _T_3430 : connect remapVecData[5], Queue10_UInt8.io.deq.bits connect remapVecValids[5], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[5] node _T_3431 = eq(UInt<1>(0h1), remapindex_5) when _T_3431 : connect remapVecData[5], Queue10_UInt8_1.io.deq.bits connect remapVecValids[5], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[5] node _T_3432 = eq(UInt<2>(0h2), remapindex_5) when _T_3432 : connect remapVecData[5], Queue10_UInt8_2.io.deq.bits connect remapVecValids[5], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[5] node _T_3433 = eq(UInt<2>(0h3), remapindex_5) when _T_3433 : connect remapVecData[5], Queue10_UInt8_3.io.deq.bits connect remapVecValids[5], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[5] node _T_3434 = eq(UInt<3>(0h4), remapindex_5) when _T_3434 : connect remapVecData[5], Queue10_UInt8_4.io.deq.bits connect remapVecValids[5], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[5] node _T_3435 = eq(UInt<3>(0h5), remapindex_5) when _T_3435 : connect remapVecData[5], Queue10_UInt8_5.io.deq.bits connect remapVecValids[5], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[5] node _T_3436 = eq(UInt<3>(0h6), remapindex_5) when _T_3436 : connect remapVecData[5], Queue10_UInt8_6.io.deq.bits connect remapVecValids[5], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[5] node _T_3437 = eq(UInt<3>(0h7), remapindex_5) when _T_3437 : connect remapVecData[5], Queue10_UInt8_7.io.deq.bits connect remapVecValids[5], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[5] node _T_3438 = eq(UInt<4>(0h8), remapindex_5) when _T_3438 : connect remapVecData[5], Queue10_UInt8_8.io.deq.bits connect remapVecValids[5], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[5] node _T_3439 = eq(UInt<4>(0h9), remapindex_5) when _T_3439 : connect remapVecData[5], Queue10_UInt8_9.io.deq.bits connect remapVecValids[5], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[5] node _T_3440 = eq(UInt<4>(0ha), remapindex_5) when _T_3440 : connect remapVecData[5], Queue10_UInt8_10.io.deq.bits connect remapVecValids[5], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[5] node _T_3441 = eq(UInt<4>(0hb), remapindex_5) when _T_3441 : connect remapVecData[5], Queue10_UInt8_11.io.deq.bits connect remapVecValids[5], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[5] node _T_3442 = eq(UInt<4>(0hc), remapindex_5) when _T_3442 : connect remapVecData[5], Queue10_UInt8_12.io.deq.bits connect remapVecValids[5], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[5] node _T_3443 = eq(UInt<4>(0hd), remapindex_5) when _T_3443 : connect remapVecData[5], Queue10_UInt8_13.io.deq.bits connect remapVecValids[5], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[5] node _T_3444 = eq(UInt<4>(0he), remapindex_5) when _T_3444 : connect remapVecData[5], Queue10_UInt8_14.io.deq.bits connect remapVecValids[5], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[5] node _T_3445 = eq(UInt<4>(0hf), remapindex_5) when _T_3445 : connect remapVecData[5], Queue10_UInt8_15.io.deq.bits connect remapVecValids[5], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[5] node _T_3446 = eq(UInt<5>(0h10), remapindex_5) when _T_3446 : connect remapVecData[5], Queue10_UInt8_16.io.deq.bits connect remapVecValids[5], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[5] node _T_3447 = eq(UInt<5>(0h11), remapindex_5) when _T_3447 : connect remapVecData[5], Queue10_UInt8_17.io.deq.bits connect remapVecValids[5], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[5] node _T_3448 = eq(UInt<5>(0h12), remapindex_5) when _T_3448 : connect remapVecData[5], Queue10_UInt8_18.io.deq.bits connect remapVecValids[5], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[5] node _T_3449 = eq(UInt<5>(0h13), remapindex_5) when _T_3449 : connect remapVecData[5], Queue10_UInt8_19.io.deq.bits connect remapVecValids[5], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[5] node _T_3450 = eq(UInt<5>(0h14), remapindex_5) when _T_3450 : connect remapVecData[5], Queue10_UInt8_20.io.deq.bits connect remapVecValids[5], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[5] node _T_3451 = eq(UInt<5>(0h15), remapindex_5) when _T_3451 : connect remapVecData[5], Queue10_UInt8_21.io.deq.bits connect remapVecValids[5], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[5] node _T_3452 = eq(UInt<5>(0h16), remapindex_5) when _T_3452 : connect remapVecData[5], Queue10_UInt8_22.io.deq.bits connect remapVecValids[5], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[5] node _T_3453 = eq(UInt<5>(0h17), remapindex_5) when _T_3453 : connect remapVecData[5], Queue10_UInt8_23.io.deq.bits connect remapVecValids[5], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[5] node _T_3454 = eq(UInt<5>(0h18), remapindex_5) when _T_3454 : connect remapVecData[5], Queue10_UInt8_24.io.deq.bits connect remapVecValids[5], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[5] node _T_3455 = eq(UInt<5>(0h19), remapindex_5) when _T_3455 : connect remapVecData[5], Queue10_UInt8_25.io.deq.bits connect remapVecValids[5], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[5] node _T_3456 = eq(UInt<5>(0h1a), remapindex_5) when _T_3456 : connect remapVecData[5], Queue10_UInt8_26.io.deq.bits connect remapVecValids[5], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[5] node _T_3457 = eq(UInt<5>(0h1b), remapindex_5) when _T_3457 : connect remapVecData[5], Queue10_UInt8_27.io.deq.bits connect remapVecValids[5], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[5] node _T_3458 = eq(UInt<5>(0h1c), remapindex_5) when _T_3458 : connect remapVecData[5], Queue10_UInt8_28.io.deq.bits connect remapVecValids[5], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[5] node _T_3459 = eq(UInt<5>(0h1d), remapindex_5) when _T_3459 : connect remapVecData[5], Queue10_UInt8_29.io.deq.bits connect remapVecValids[5], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[5] node _T_3460 = eq(UInt<5>(0h1e), remapindex_5) when _T_3460 : connect remapVecData[5], Queue10_UInt8_30.io.deq.bits connect remapVecValids[5], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[5] node _T_3461 = eq(UInt<5>(0h1f), remapindex_5) when _T_3461 : connect remapVecData[5], Queue10_UInt8_31.io.deq.bits connect remapVecValids[5], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[5] node _remapindex_T_6 = add(UInt<3>(0h6), read_start_index) node remapindex_6 = rem(_remapindex_T_6, UInt<6>(0h20)) node _T_3462 = eq(UInt<1>(0h0), remapindex_6) when _T_3462 : connect remapVecData[6], Queue10_UInt8.io.deq.bits connect remapVecValids[6], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[6] node _T_3463 = eq(UInt<1>(0h1), remapindex_6) when _T_3463 : connect remapVecData[6], Queue10_UInt8_1.io.deq.bits connect remapVecValids[6], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[6] node _T_3464 = eq(UInt<2>(0h2), remapindex_6) when _T_3464 : connect remapVecData[6], Queue10_UInt8_2.io.deq.bits connect remapVecValids[6], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[6] node _T_3465 = eq(UInt<2>(0h3), remapindex_6) when _T_3465 : connect remapVecData[6], Queue10_UInt8_3.io.deq.bits connect remapVecValids[6], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[6] node _T_3466 = eq(UInt<3>(0h4), remapindex_6) when _T_3466 : connect remapVecData[6], Queue10_UInt8_4.io.deq.bits connect remapVecValids[6], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[6] node _T_3467 = eq(UInt<3>(0h5), remapindex_6) when _T_3467 : connect remapVecData[6], Queue10_UInt8_5.io.deq.bits connect remapVecValids[6], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[6] node _T_3468 = eq(UInt<3>(0h6), remapindex_6) when _T_3468 : connect remapVecData[6], Queue10_UInt8_6.io.deq.bits connect remapVecValids[6], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[6] node _T_3469 = eq(UInt<3>(0h7), remapindex_6) when _T_3469 : connect remapVecData[6], Queue10_UInt8_7.io.deq.bits connect remapVecValids[6], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[6] node _T_3470 = eq(UInt<4>(0h8), remapindex_6) when _T_3470 : connect remapVecData[6], Queue10_UInt8_8.io.deq.bits connect remapVecValids[6], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[6] node _T_3471 = eq(UInt<4>(0h9), remapindex_6) when _T_3471 : connect remapVecData[6], Queue10_UInt8_9.io.deq.bits connect remapVecValids[6], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[6] node _T_3472 = eq(UInt<4>(0ha), remapindex_6) when _T_3472 : connect remapVecData[6], Queue10_UInt8_10.io.deq.bits connect remapVecValids[6], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[6] node _T_3473 = eq(UInt<4>(0hb), remapindex_6) when _T_3473 : connect remapVecData[6], Queue10_UInt8_11.io.deq.bits connect remapVecValids[6], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[6] node _T_3474 = eq(UInt<4>(0hc), remapindex_6) when _T_3474 : connect remapVecData[6], Queue10_UInt8_12.io.deq.bits connect remapVecValids[6], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[6] node _T_3475 = eq(UInt<4>(0hd), remapindex_6) when _T_3475 : connect remapVecData[6], Queue10_UInt8_13.io.deq.bits connect remapVecValids[6], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[6] node _T_3476 = eq(UInt<4>(0he), remapindex_6) when _T_3476 : connect remapVecData[6], Queue10_UInt8_14.io.deq.bits connect remapVecValids[6], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[6] node _T_3477 = eq(UInt<4>(0hf), remapindex_6) when _T_3477 : connect remapVecData[6], Queue10_UInt8_15.io.deq.bits connect remapVecValids[6], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[6] node _T_3478 = eq(UInt<5>(0h10), remapindex_6) when _T_3478 : connect remapVecData[6], Queue10_UInt8_16.io.deq.bits connect remapVecValids[6], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[6] node _T_3479 = eq(UInt<5>(0h11), remapindex_6) when _T_3479 : connect remapVecData[6], Queue10_UInt8_17.io.deq.bits connect remapVecValids[6], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[6] node _T_3480 = eq(UInt<5>(0h12), remapindex_6) when _T_3480 : connect remapVecData[6], Queue10_UInt8_18.io.deq.bits connect remapVecValids[6], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[6] node _T_3481 = eq(UInt<5>(0h13), remapindex_6) when _T_3481 : connect remapVecData[6], Queue10_UInt8_19.io.deq.bits connect remapVecValids[6], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[6] node _T_3482 = eq(UInt<5>(0h14), remapindex_6) when _T_3482 : connect remapVecData[6], Queue10_UInt8_20.io.deq.bits connect remapVecValids[6], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[6] node _T_3483 = eq(UInt<5>(0h15), remapindex_6) when _T_3483 : connect remapVecData[6], Queue10_UInt8_21.io.deq.bits connect remapVecValids[6], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[6] node _T_3484 = eq(UInt<5>(0h16), remapindex_6) when _T_3484 : connect remapVecData[6], Queue10_UInt8_22.io.deq.bits connect remapVecValids[6], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[6] node _T_3485 = eq(UInt<5>(0h17), remapindex_6) when _T_3485 : connect remapVecData[6], Queue10_UInt8_23.io.deq.bits connect remapVecValids[6], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[6] node _T_3486 = eq(UInt<5>(0h18), remapindex_6) when _T_3486 : connect remapVecData[6], Queue10_UInt8_24.io.deq.bits connect remapVecValids[6], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[6] node _T_3487 = eq(UInt<5>(0h19), remapindex_6) when _T_3487 : connect remapVecData[6], Queue10_UInt8_25.io.deq.bits connect remapVecValids[6], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[6] node _T_3488 = eq(UInt<5>(0h1a), remapindex_6) when _T_3488 : connect remapVecData[6], Queue10_UInt8_26.io.deq.bits connect remapVecValids[6], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[6] node _T_3489 = eq(UInt<5>(0h1b), remapindex_6) when _T_3489 : connect remapVecData[6], Queue10_UInt8_27.io.deq.bits connect remapVecValids[6], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[6] node _T_3490 = eq(UInt<5>(0h1c), remapindex_6) when _T_3490 : connect remapVecData[6], Queue10_UInt8_28.io.deq.bits connect remapVecValids[6], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[6] node _T_3491 = eq(UInt<5>(0h1d), remapindex_6) when _T_3491 : connect remapVecData[6], Queue10_UInt8_29.io.deq.bits connect remapVecValids[6], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[6] node _T_3492 = eq(UInt<5>(0h1e), remapindex_6) when _T_3492 : connect remapVecData[6], Queue10_UInt8_30.io.deq.bits connect remapVecValids[6], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[6] node _T_3493 = eq(UInt<5>(0h1f), remapindex_6) when _T_3493 : connect remapVecData[6], Queue10_UInt8_31.io.deq.bits connect remapVecValids[6], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[6] node _remapindex_T_7 = add(UInt<3>(0h7), read_start_index) node remapindex_7 = rem(_remapindex_T_7, UInt<6>(0h20)) node _T_3494 = eq(UInt<1>(0h0), remapindex_7) when _T_3494 : connect remapVecData[7], Queue10_UInt8.io.deq.bits connect remapVecValids[7], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[7] node _T_3495 = eq(UInt<1>(0h1), remapindex_7) when _T_3495 : connect remapVecData[7], Queue10_UInt8_1.io.deq.bits connect remapVecValids[7], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[7] node _T_3496 = eq(UInt<2>(0h2), remapindex_7) when _T_3496 : connect remapVecData[7], Queue10_UInt8_2.io.deq.bits connect remapVecValids[7], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[7] node _T_3497 = eq(UInt<2>(0h3), remapindex_7) when _T_3497 : connect remapVecData[7], Queue10_UInt8_3.io.deq.bits connect remapVecValids[7], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[7] node _T_3498 = eq(UInt<3>(0h4), remapindex_7) when _T_3498 : connect remapVecData[7], Queue10_UInt8_4.io.deq.bits connect remapVecValids[7], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[7] node _T_3499 = eq(UInt<3>(0h5), remapindex_7) when _T_3499 : connect remapVecData[7], Queue10_UInt8_5.io.deq.bits connect remapVecValids[7], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[7] node _T_3500 = eq(UInt<3>(0h6), remapindex_7) when _T_3500 : connect remapVecData[7], Queue10_UInt8_6.io.deq.bits connect remapVecValids[7], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[7] node _T_3501 = eq(UInt<3>(0h7), remapindex_7) when _T_3501 : connect remapVecData[7], Queue10_UInt8_7.io.deq.bits connect remapVecValids[7], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[7] node _T_3502 = eq(UInt<4>(0h8), remapindex_7) when _T_3502 : connect remapVecData[7], Queue10_UInt8_8.io.deq.bits connect remapVecValids[7], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[7] node _T_3503 = eq(UInt<4>(0h9), remapindex_7) when _T_3503 : connect remapVecData[7], Queue10_UInt8_9.io.deq.bits connect remapVecValids[7], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[7] node _T_3504 = eq(UInt<4>(0ha), remapindex_7) when _T_3504 : connect remapVecData[7], Queue10_UInt8_10.io.deq.bits connect remapVecValids[7], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[7] node _T_3505 = eq(UInt<4>(0hb), remapindex_7) when _T_3505 : connect remapVecData[7], Queue10_UInt8_11.io.deq.bits connect remapVecValids[7], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[7] node _T_3506 = eq(UInt<4>(0hc), remapindex_7) when _T_3506 : connect remapVecData[7], Queue10_UInt8_12.io.deq.bits connect remapVecValids[7], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[7] node _T_3507 = eq(UInt<4>(0hd), remapindex_7) when _T_3507 : connect remapVecData[7], Queue10_UInt8_13.io.deq.bits connect remapVecValids[7], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[7] node _T_3508 = eq(UInt<4>(0he), remapindex_7) when _T_3508 : connect remapVecData[7], Queue10_UInt8_14.io.deq.bits connect remapVecValids[7], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[7] node _T_3509 = eq(UInt<4>(0hf), remapindex_7) when _T_3509 : connect remapVecData[7], Queue10_UInt8_15.io.deq.bits connect remapVecValids[7], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[7] node _T_3510 = eq(UInt<5>(0h10), remapindex_7) when _T_3510 : connect remapVecData[7], Queue10_UInt8_16.io.deq.bits connect remapVecValids[7], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[7] node _T_3511 = eq(UInt<5>(0h11), remapindex_7) when _T_3511 : connect remapVecData[7], Queue10_UInt8_17.io.deq.bits connect remapVecValids[7], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[7] node _T_3512 = eq(UInt<5>(0h12), remapindex_7) when _T_3512 : connect remapVecData[7], Queue10_UInt8_18.io.deq.bits connect remapVecValids[7], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[7] node _T_3513 = eq(UInt<5>(0h13), remapindex_7) when _T_3513 : connect remapVecData[7], Queue10_UInt8_19.io.deq.bits connect remapVecValids[7], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[7] node _T_3514 = eq(UInt<5>(0h14), remapindex_7) when _T_3514 : connect remapVecData[7], Queue10_UInt8_20.io.deq.bits connect remapVecValids[7], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[7] node _T_3515 = eq(UInt<5>(0h15), remapindex_7) when _T_3515 : connect remapVecData[7], Queue10_UInt8_21.io.deq.bits connect remapVecValids[7], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[7] node _T_3516 = eq(UInt<5>(0h16), remapindex_7) when _T_3516 : connect remapVecData[7], Queue10_UInt8_22.io.deq.bits connect remapVecValids[7], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[7] node _T_3517 = eq(UInt<5>(0h17), remapindex_7) when _T_3517 : connect remapVecData[7], Queue10_UInt8_23.io.deq.bits connect remapVecValids[7], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[7] node _T_3518 = eq(UInt<5>(0h18), remapindex_7) when _T_3518 : connect remapVecData[7], Queue10_UInt8_24.io.deq.bits connect remapVecValids[7], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[7] node _T_3519 = eq(UInt<5>(0h19), remapindex_7) when _T_3519 : connect remapVecData[7], Queue10_UInt8_25.io.deq.bits connect remapVecValids[7], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[7] node _T_3520 = eq(UInt<5>(0h1a), remapindex_7) when _T_3520 : connect remapVecData[7], Queue10_UInt8_26.io.deq.bits connect remapVecValids[7], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[7] node _T_3521 = eq(UInt<5>(0h1b), remapindex_7) when _T_3521 : connect remapVecData[7], Queue10_UInt8_27.io.deq.bits connect remapVecValids[7], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[7] node _T_3522 = eq(UInt<5>(0h1c), remapindex_7) when _T_3522 : connect remapVecData[7], Queue10_UInt8_28.io.deq.bits connect remapVecValids[7], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[7] node _T_3523 = eq(UInt<5>(0h1d), remapindex_7) when _T_3523 : connect remapVecData[7], Queue10_UInt8_29.io.deq.bits connect remapVecValids[7], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[7] node _T_3524 = eq(UInt<5>(0h1e), remapindex_7) when _T_3524 : connect remapVecData[7], Queue10_UInt8_30.io.deq.bits connect remapVecValids[7], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[7] node _T_3525 = eq(UInt<5>(0h1f), remapindex_7) when _T_3525 : connect remapVecData[7], Queue10_UInt8_31.io.deq.bits connect remapVecValids[7], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[7] node _remapindex_T_8 = add(UInt<4>(0h8), read_start_index) node remapindex_8 = rem(_remapindex_T_8, UInt<6>(0h20)) node _T_3526 = eq(UInt<1>(0h0), remapindex_8) when _T_3526 : connect remapVecData[8], Queue10_UInt8.io.deq.bits connect remapVecValids[8], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[8] node _T_3527 = eq(UInt<1>(0h1), remapindex_8) when _T_3527 : connect remapVecData[8], Queue10_UInt8_1.io.deq.bits connect remapVecValids[8], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[8] node _T_3528 = eq(UInt<2>(0h2), remapindex_8) when _T_3528 : connect remapVecData[8], Queue10_UInt8_2.io.deq.bits connect remapVecValids[8], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[8] node _T_3529 = eq(UInt<2>(0h3), remapindex_8) when _T_3529 : connect remapVecData[8], Queue10_UInt8_3.io.deq.bits connect remapVecValids[8], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[8] node _T_3530 = eq(UInt<3>(0h4), remapindex_8) when _T_3530 : connect remapVecData[8], Queue10_UInt8_4.io.deq.bits connect remapVecValids[8], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[8] node _T_3531 = eq(UInt<3>(0h5), remapindex_8) when _T_3531 : connect remapVecData[8], Queue10_UInt8_5.io.deq.bits connect remapVecValids[8], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[8] node _T_3532 = eq(UInt<3>(0h6), remapindex_8) when _T_3532 : connect remapVecData[8], Queue10_UInt8_6.io.deq.bits connect remapVecValids[8], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[8] node _T_3533 = eq(UInt<3>(0h7), remapindex_8) when _T_3533 : connect remapVecData[8], Queue10_UInt8_7.io.deq.bits connect remapVecValids[8], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[8] node _T_3534 = eq(UInt<4>(0h8), remapindex_8) when _T_3534 : connect remapVecData[8], Queue10_UInt8_8.io.deq.bits connect remapVecValids[8], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[8] node _T_3535 = eq(UInt<4>(0h9), remapindex_8) when _T_3535 : connect remapVecData[8], Queue10_UInt8_9.io.deq.bits connect remapVecValids[8], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[8] node _T_3536 = eq(UInt<4>(0ha), remapindex_8) when _T_3536 : connect remapVecData[8], Queue10_UInt8_10.io.deq.bits connect remapVecValids[8], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[8] node _T_3537 = eq(UInt<4>(0hb), remapindex_8) when _T_3537 : connect remapVecData[8], Queue10_UInt8_11.io.deq.bits connect remapVecValids[8], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[8] node _T_3538 = eq(UInt<4>(0hc), remapindex_8) when _T_3538 : connect remapVecData[8], Queue10_UInt8_12.io.deq.bits connect remapVecValids[8], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[8] node _T_3539 = eq(UInt<4>(0hd), remapindex_8) when _T_3539 : connect remapVecData[8], Queue10_UInt8_13.io.deq.bits connect remapVecValids[8], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[8] node _T_3540 = eq(UInt<4>(0he), remapindex_8) when _T_3540 : connect remapVecData[8], Queue10_UInt8_14.io.deq.bits connect remapVecValids[8], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[8] node _T_3541 = eq(UInt<4>(0hf), remapindex_8) when _T_3541 : connect remapVecData[8], Queue10_UInt8_15.io.deq.bits connect remapVecValids[8], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[8] node _T_3542 = eq(UInt<5>(0h10), remapindex_8) when _T_3542 : connect remapVecData[8], Queue10_UInt8_16.io.deq.bits connect remapVecValids[8], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[8] node _T_3543 = eq(UInt<5>(0h11), remapindex_8) when _T_3543 : connect remapVecData[8], Queue10_UInt8_17.io.deq.bits connect remapVecValids[8], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[8] node _T_3544 = eq(UInt<5>(0h12), remapindex_8) when _T_3544 : connect remapVecData[8], Queue10_UInt8_18.io.deq.bits connect remapVecValids[8], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[8] node _T_3545 = eq(UInt<5>(0h13), remapindex_8) when _T_3545 : connect remapVecData[8], Queue10_UInt8_19.io.deq.bits connect remapVecValids[8], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[8] node _T_3546 = eq(UInt<5>(0h14), remapindex_8) when _T_3546 : connect remapVecData[8], Queue10_UInt8_20.io.deq.bits connect remapVecValids[8], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[8] node _T_3547 = eq(UInt<5>(0h15), remapindex_8) when _T_3547 : connect remapVecData[8], Queue10_UInt8_21.io.deq.bits connect remapVecValids[8], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[8] node _T_3548 = eq(UInt<5>(0h16), remapindex_8) when _T_3548 : connect remapVecData[8], Queue10_UInt8_22.io.deq.bits connect remapVecValids[8], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[8] node _T_3549 = eq(UInt<5>(0h17), remapindex_8) when _T_3549 : connect remapVecData[8], Queue10_UInt8_23.io.deq.bits connect remapVecValids[8], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[8] node _T_3550 = eq(UInt<5>(0h18), remapindex_8) when _T_3550 : connect remapVecData[8], Queue10_UInt8_24.io.deq.bits connect remapVecValids[8], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[8] node _T_3551 = eq(UInt<5>(0h19), remapindex_8) when _T_3551 : connect remapVecData[8], Queue10_UInt8_25.io.deq.bits connect remapVecValids[8], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[8] node _T_3552 = eq(UInt<5>(0h1a), remapindex_8) when _T_3552 : connect remapVecData[8], Queue10_UInt8_26.io.deq.bits connect remapVecValids[8], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[8] node _T_3553 = eq(UInt<5>(0h1b), remapindex_8) when _T_3553 : connect remapVecData[8], Queue10_UInt8_27.io.deq.bits connect remapVecValids[8], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[8] node _T_3554 = eq(UInt<5>(0h1c), remapindex_8) when _T_3554 : connect remapVecData[8], Queue10_UInt8_28.io.deq.bits connect remapVecValids[8], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[8] node _T_3555 = eq(UInt<5>(0h1d), remapindex_8) when _T_3555 : connect remapVecData[8], Queue10_UInt8_29.io.deq.bits connect remapVecValids[8], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[8] node _T_3556 = eq(UInt<5>(0h1e), remapindex_8) when _T_3556 : connect remapVecData[8], Queue10_UInt8_30.io.deq.bits connect remapVecValids[8], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[8] node _T_3557 = eq(UInt<5>(0h1f), remapindex_8) when _T_3557 : connect remapVecData[8], Queue10_UInt8_31.io.deq.bits connect remapVecValids[8], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[8] node _remapindex_T_9 = add(UInt<4>(0h9), read_start_index) node remapindex_9 = rem(_remapindex_T_9, UInt<6>(0h20)) node _T_3558 = eq(UInt<1>(0h0), remapindex_9) when _T_3558 : connect remapVecData[9], Queue10_UInt8.io.deq.bits connect remapVecValids[9], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[9] node _T_3559 = eq(UInt<1>(0h1), remapindex_9) when _T_3559 : connect remapVecData[9], Queue10_UInt8_1.io.deq.bits connect remapVecValids[9], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[9] node _T_3560 = eq(UInt<2>(0h2), remapindex_9) when _T_3560 : connect remapVecData[9], Queue10_UInt8_2.io.deq.bits connect remapVecValids[9], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[9] node _T_3561 = eq(UInt<2>(0h3), remapindex_9) when _T_3561 : connect remapVecData[9], Queue10_UInt8_3.io.deq.bits connect remapVecValids[9], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[9] node _T_3562 = eq(UInt<3>(0h4), remapindex_9) when _T_3562 : connect remapVecData[9], Queue10_UInt8_4.io.deq.bits connect remapVecValids[9], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[9] node _T_3563 = eq(UInt<3>(0h5), remapindex_9) when _T_3563 : connect remapVecData[9], Queue10_UInt8_5.io.deq.bits connect remapVecValids[9], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[9] node _T_3564 = eq(UInt<3>(0h6), remapindex_9) when _T_3564 : connect remapVecData[9], Queue10_UInt8_6.io.deq.bits connect remapVecValids[9], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[9] node _T_3565 = eq(UInt<3>(0h7), remapindex_9) when _T_3565 : connect remapVecData[9], Queue10_UInt8_7.io.deq.bits connect remapVecValids[9], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[9] node _T_3566 = eq(UInt<4>(0h8), remapindex_9) when _T_3566 : connect remapVecData[9], Queue10_UInt8_8.io.deq.bits connect remapVecValids[9], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[9] node _T_3567 = eq(UInt<4>(0h9), remapindex_9) when _T_3567 : connect remapVecData[9], Queue10_UInt8_9.io.deq.bits connect remapVecValids[9], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[9] node _T_3568 = eq(UInt<4>(0ha), remapindex_9) when _T_3568 : connect remapVecData[9], Queue10_UInt8_10.io.deq.bits connect remapVecValids[9], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[9] node _T_3569 = eq(UInt<4>(0hb), remapindex_9) when _T_3569 : connect remapVecData[9], Queue10_UInt8_11.io.deq.bits connect remapVecValids[9], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[9] node _T_3570 = eq(UInt<4>(0hc), remapindex_9) when _T_3570 : connect remapVecData[9], Queue10_UInt8_12.io.deq.bits connect remapVecValids[9], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[9] node _T_3571 = eq(UInt<4>(0hd), remapindex_9) when _T_3571 : connect remapVecData[9], Queue10_UInt8_13.io.deq.bits connect remapVecValids[9], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[9] node _T_3572 = eq(UInt<4>(0he), remapindex_9) when _T_3572 : connect remapVecData[9], Queue10_UInt8_14.io.deq.bits connect remapVecValids[9], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[9] node _T_3573 = eq(UInt<4>(0hf), remapindex_9) when _T_3573 : connect remapVecData[9], Queue10_UInt8_15.io.deq.bits connect remapVecValids[9], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[9] node _T_3574 = eq(UInt<5>(0h10), remapindex_9) when _T_3574 : connect remapVecData[9], Queue10_UInt8_16.io.deq.bits connect remapVecValids[9], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[9] node _T_3575 = eq(UInt<5>(0h11), remapindex_9) when _T_3575 : connect remapVecData[9], Queue10_UInt8_17.io.deq.bits connect remapVecValids[9], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[9] node _T_3576 = eq(UInt<5>(0h12), remapindex_9) when _T_3576 : connect remapVecData[9], Queue10_UInt8_18.io.deq.bits connect remapVecValids[9], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[9] node _T_3577 = eq(UInt<5>(0h13), remapindex_9) when _T_3577 : connect remapVecData[9], Queue10_UInt8_19.io.deq.bits connect remapVecValids[9], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[9] node _T_3578 = eq(UInt<5>(0h14), remapindex_9) when _T_3578 : connect remapVecData[9], Queue10_UInt8_20.io.deq.bits connect remapVecValids[9], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[9] node _T_3579 = eq(UInt<5>(0h15), remapindex_9) when _T_3579 : connect remapVecData[9], Queue10_UInt8_21.io.deq.bits connect remapVecValids[9], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[9] node _T_3580 = eq(UInt<5>(0h16), remapindex_9) when _T_3580 : connect remapVecData[9], Queue10_UInt8_22.io.deq.bits connect remapVecValids[9], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[9] node _T_3581 = eq(UInt<5>(0h17), remapindex_9) when _T_3581 : connect remapVecData[9], Queue10_UInt8_23.io.deq.bits connect remapVecValids[9], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[9] node _T_3582 = eq(UInt<5>(0h18), remapindex_9) when _T_3582 : connect remapVecData[9], Queue10_UInt8_24.io.deq.bits connect remapVecValids[9], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[9] node _T_3583 = eq(UInt<5>(0h19), remapindex_9) when _T_3583 : connect remapVecData[9], Queue10_UInt8_25.io.deq.bits connect remapVecValids[9], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[9] node _T_3584 = eq(UInt<5>(0h1a), remapindex_9) when _T_3584 : connect remapVecData[9], Queue10_UInt8_26.io.deq.bits connect remapVecValids[9], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[9] node _T_3585 = eq(UInt<5>(0h1b), remapindex_9) when _T_3585 : connect remapVecData[9], Queue10_UInt8_27.io.deq.bits connect remapVecValids[9], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[9] node _T_3586 = eq(UInt<5>(0h1c), remapindex_9) when _T_3586 : connect remapVecData[9], Queue10_UInt8_28.io.deq.bits connect remapVecValids[9], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[9] node _T_3587 = eq(UInt<5>(0h1d), remapindex_9) when _T_3587 : connect remapVecData[9], Queue10_UInt8_29.io.deq.bits connect remapVecValids[9], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[9] node _T_3588 = eq(UInt<5>(0h1e), remapindex_9) when _T_3588 : connect remapVecData[9], Queue10_UInt8_30.io.deq.bits connect remapVecValids[9], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[9] node _T_3589 = eq(UInt<5>(0h1f), remapindex_9) when _T_3589 : connect remapVecData[9], Queue10_UInt8_31.io.deq.bits connect remapVecValids[9], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[9] node _remapindex_T_10 = add(UInt<4>(0ha), read_start_index) node remapindex_10 = rem(_remapindex_T_10, UInt<6>(0h20)) node _T_3590 = eq(UInt<1>(0h0), remapindex_10) when _T_3590 : connect remapVecData[10], Queue10_UInt8.io.deq.bits connect remapVecValids[10], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[10] node _T_3591 = eq(UInt<1>(0h1), remapindex_10) when _T_3591 : connect remapVecData[10], Queue10_UInt8_1.io.deq.bits connect remapVecValids[10], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[10] node _T_3592 = eq(UInt<2>(0h2), remapindex_10) when _T_3592 : connect remapVecData[10], Queue10_UInt8_2.io.deq.bits connect remapVecValids[10], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[10] node _T_3593 = eq(UInt<2>(0h3), remapindex_10) when _T_3593 : connect remapVecData[10], Queue10_UInt8_3.io.deq.bits connect remapVecValids[10], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[10] node _T_3594 = eq(UInt<3>(0h4), remapindex_10) when _T_3594 : connect remapVecData[10], Queue10_UInt8_4.io.deq.bits connect remapVecValids[10], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[10] node _T_3595 = eq(UInt<3>(0h5), remapindex_10) when _T_3595 : connect remapVecData[10], Queue10_UInt8_5.io.deq.bits connect remapVecValids[10], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[10] node _T_3596 = eq(UInt<3>(0h6), remapindex_10) when _T_3596 : connect remapVecData[10], Queue10_UInt8_6.io.deq.bits connect remapVecValids[10], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[10] node _T_3597 = eq(UInt<3>(0h7), remapindex_10) when _T_3597 : connect remapVecData[10], Queue10_UInt8_7.io.deq.bits connect remapVecValids[10], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[10] node _T_3598 = eq(UInt<4>(0h8), remapindex_10) when _T_3598 : connect remapVecData[10], Queue10_UInt8_8.io.deq.bits connect remapVecValids[10], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[10] node _T_3599 = eq(UInt<4>(0h9), remapindex_10) when _T_3599 : connect remapVecData[10], Queue10_UInt8_9.io.deq.bits connect remapVecValids[10], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[10] node _T_3600 = eq(UInt<4>(0ha), remapindex_10) when _T_3600 : connect remapVecData[10], Queue10_UInt8_10.io.deq.bits connect remapVecValids[10], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[10] node _T_3601 = eq(UInt<4>(0hb), remapindex_10) when _T_3601 : connect remapVecData[10], Queue10_UInt8_11.io.deq.bits connect remapVecValids[10], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[10] node _T_3602 = eq(UInt<4>(0hc), remapindex_10) when _T_3602 : connect remapVecData[10], Queue10_UInt8_12.io.deq.bits connect remapVecValids[10], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[10] node _T_3603 = eq(UInt<4>(0hd), remapindex_10) when _T_3603 : connect remapVecData[10], Queue10_UInt8_13.io.deq.bits connect remapVecValids[10], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[10] node _T_3604 = eq(UInt<4>(0he), remapindex_10) when _T_3604 : connect remapVecData[10], Queue10_UInt8_14.io.deq.bits connect remapVecValids[10], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[10] node _T_3605 = eq(UInt<4>(0hf), remapindex_10) when _T_3605 : connect remapVecData[10], Queue10_UInt8_15.io.deq.bits connect remapVecValids[10], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[10] node _T_3606 = eq(UInt<5>(0h10), remapindex_10) when _T_3606 : connect remapVecData[10], Queue10_UInt8_16.io.deq.bits connect remapVecValids[10], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[10] node _T_3607 = eq(UInt<5>(0h11), remapindex_10) when _T_3607 : connect remapVecData[10], Queue10_UInt8_17.io.deq.bits connect remapVecValids[10], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[10] node _T_3608 = eq(UInt<5>(0h12), remapindex_10) when _T_3608 : connect remapVecData[10], Queue10_UInt8_18.io.deq.bits connect remapVecValids[10], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[10] node _T_3609 = eq(UInt<5>(0h13), remapindex_10) when _T_3609 : connect remapVecData[10], Queue10_UInt8_19.io.deq.bits connect remapVecValids[10], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[10] node _T_3610 = eq(UInt<5>(0h14), remapindex_10) when _T_3610 : connect remapVecData[10], Queue10_UInt8_20.io.deq.bits connect remapVecValids[10], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[10] node _T_3611 = eq(UInt<5>(0h15), remapindex_10) when _T_3611 : connect remapVecData[10], Queue10_UInt8_21.io.deq.bits connect remapVecValids[10], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[10] node _T_3612 = eq(UInt<5>(0h16), remapindex_10) when _T_3612 : connect remapVecData[10], Queue10_UInt8_22.io.deq.bits connect remapVecValids[10], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[10] node _T_3613 = eq(UInt<5>(0h17), remapindex_10) when _T_3613 : connect remapVecData[10], Queue10_UInt8_23.io.deq.bits connect remapVecValids[10], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[10] node _T_3614 = eq(UInt<5>(0h18), remapindex_10) when _T_3614 : connect remapVecData[10], Queue10_UInt8_24.io.deq.bits connect remapVecValids[10], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[10] node _T_3615 = eq(UInt<5>(0h19), remapindex_10) when _T_3615 : connect remapVecData[10], Queue10_UInt8_25.io.deq.bits connect remapVecValids[10], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[10] node _T_3616 = eq(UInt<5>(0h1a), remapindex_10) when _T_3616 : connect remapVecData[10], Queue10_UInt8_26.io.deq.bits connect remapVecValids[10], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[10] node _T_3617 = eq(UInt<5>(0h1b), remapindex_10) when _T_3617 : connect remapVecData[10], Queue10_UInt8_27.io.deq.bits connect remapVecValids[10], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[10] node _T_3618 = eq(UInt<5>(0h1c), remapindex_10) when _T_3618 : connect remapVecData[10], Queue10_UInt8_28.io.deq.bits connect remapVecValids[10], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[10] node _T_3619 = eq(UInt<5>(0h1d), remapindex_10) when _T_3619 : connect remapVecData[10], Queue10_UInt8_29.io.deq.bits connect remapVecValids[10], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[10] node _T_3620 = eq(UInt<5>(0h1e), remapindex_10) when _T_3620 : connect remapVecData[10], Queue10_UInt8_30.io.deq.bits connect remapVecValids[10], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[10] node _T_3621 = eq(UInt<5>(0h1f), remapindex_10) when _T_3621 : connect remapVecData[10], Queue10_UInt8_31.io.deq.bits connect remapVecValids[10], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[10] node _remapindex_T_11 = add(UInt<4>(0hb), read_start_index) node remapindex_11 = rem(_remapindex_T_11, UInt<6>(0h20)) node _T_3622 = eq(UInt<1>(0h0), remapindex_11) when _T_3622 : connect remapVecData[11], Queue10_UInt8.io.deq.bits connect remapVecValids[11], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[11] node _T_3623 = eq(UInt<1>(0h1), remapindex_11) when _T_3623 : connect remapVecData[11], Queue10_UInt8_1.io.deq.bits connect remapVecValids[11], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[11] node _T_3624 = eq(UInt<2>(0h2), remapindex_11) when _T_3624 : connect remapVecData[11], Queue10_UInt8_2.io.deq.bits connect remapVecValids[11], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[11] node _T_3625 = eq(UInt<2>(0h3), remapindex_11) when _T_3625 : connect remapVecData[11], Queue10_UInt8_3.io.deq.bits connect remapVecValids[11], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[11] node _T_3626 = eq(UInt<3>(0h4), remapindex_11) when _T_3626 : connect remapVecData[11], Queue10_UInt8_4.io.deq.bits connect remapVecValids[11], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[11] node _T_3627 = eq(UInt<3>(0h5), remapindex_11) when _T_3627 : connect remapVecData[11], Queue10_UInt8_5.io.deq.bits connect remapVecValids[11], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[11] node _T_3628 = eq(UInt<3>(0h6), remapindex_11) when _T_3628 : connect remapVecData[11], Queue10_UInt8_6.io.deq.bits connect remapVecValids[11], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[11] node _T_3629 = eq(UInt<3>(0h7), remapindex_11) when _T_3629 : connect remapVecData[11], Queue10_UInt8_7.io.deq.bits connect remapVecValids[11], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[11] node _T_3630 = eq(UInt<4>(0h8), remapindex_11) when _T_3630 : connect remapVecData[11], Queue10_UInt8_8.io.deq.bits connect remapVecValids[11], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[11] node _T_3631 = eq(UInt<4>(0h9), remapindex_11) when _T_3631 : connect remapVecData[11], Queue10_UInt8_9.io.deq.bits connect remapVecValids[11], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[11] node _T_3632 = eq(UInt<4>(0ha), remapindex_11) when _T_3632 : connect remapVecData[11], Queue10_UInt8_10.io.deq.bits connect remapVecValids[11], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[11] node _T_3633 = eq(UInt<4>(0hb), remapindex_11) when _T_3633 : connect remapVecData[11], Queue10_UInt8_11.io.deq.bits connect remapVecValids[11], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[11] node _T_3634 = eq(UInt<4>(0hc), remapindex_11) when _T_3634 : connect remapVecData[11], Queue10_UInt8_12.io.deq.bits connect remapVecValids[11], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[11] node _T_3635 = eq(UInt<4>(0hd), remapindex_11) when _T_3635 : connect remapVecData[11], Queue10_UInt8_13.io.deq.bits connect remapVecValids[11], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[11] node _T_3636 = eq(UInt<4>(0he), remapindex_11) when _T_3636 : connect remapVecData[11], Queue10_UInt8_14.io.deq.bits connect remapVecValids[11], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[11] node _T_3637 = eq(UInt<4>(0hf), remapindex_11) when _T_3637 : connect remapVecData[11], Queue10_UInt8_15.io.deq.bits connect remapVecValids[11], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[11] node _T_3638 = eq(UInt<5>(0h10), remapindex_11) when _T_3638 : connect remapVecData[11], Queue10_UInt8_16.io.deq.bits connect remapVecValids[11], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[11] node _T_3639 = eq(UInt<5>(0h11), remapindex_11) when _T_3639 : connect remapVecData[11], Queue10_UInt8_17.io.deq.bits connect remapVecValids[11], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[11] node _T_3640 = eq(UInt<5>(0h12), remapindex_11) when _T_3640 : connect remapVecData[11], Queue10_UInt8_18.io.deq.bits connect remapVecValids[11], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[11] node _T_3641 = eq(UInt<5>(0h13), remapindex_11) when _T_3641 : connect remapVecData[11], Queue10_UInt8_19.io.deq.bits connect remapVecValids[11], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[11] node _T_3642 = eq(UInt<5>(0h14), remapindex_11) when _T_3642 : connect remapVecData[11], Queue10_UInt8_20.io.deq.bits connect remapVecValids[11], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[11] node _T_3643 = eq(UInt<5>(0h15), remapindex_11) when _T_3643 : connect remapVecData[11], Queue10_UInt8_21.io.deq.bits connect remapVecValids[11], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[11] node _T_3644 = eq(UInt<5>(0h16), remapindex_11) when _T_3644 : connect remapVecData[11], Queue10_UInt8_22.io.deq.bits connect remapVecValids[11], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[11] node _T_3645 = eq(UInt<5>(0h17), remapindex_11) when _T_3645 : connect remapVecData[11], Queue10_UInt8_23.io.deq.bits connect remapVecValids[11], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[11] node _T_3646 = eq(UInt<5>(0h18), remapindex_11) when _T_3646 : connect remapVecData[11], Queue10_UInt8_24.io.deq.bits connect remapVecValids[11], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[11] node _T_3647 = eq(UInt<5>(0h19), remapindex_11) when _T_3647 : connect remapVecData[11], Queue10_UInt8_25.io.deq.bits connect remapVecValids[11], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[11] node _T_3648 = eq(UInt<5>(0h1a), remapindex_11) when _T_3648 : connect remapVecData[11], Queue10_UInt8_26.io.deq.bits connect remapVecValids[11], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[11] node _T_3649 = eq(UInt<5>(0h1b), remapindex_11) when _T_3649 : connect remapVecData[11], Queue10_UInt8_27.io.deq.bits connect remapVecValids[11], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[11] node _T_3650 = eq(UInt<5>(0h1c), remapindex_11) when _T_3650 : connect remapVecData[11], Queue10_UInt8_28.io.deq.bits connect remapVecValids[11], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[11] node _T_3651 = eq(UInt<5>(0h1d), remapindex_11) when _T_3651 : connect remapVecData[11], Queue10_UInt8_29.io.deq.bits connect remapVecValids[11], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[11] node _T_3652 = eq(UInt<5>(0h1e), remapindex_11) when _T_3652 : connect remapVecData[11], Queue10_UInt8_30.io.deq.bits connect remapVecValids[11], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[11] node _T_3653 = eq(UInt<5>(0h1f), remapindex_11) when _T_3653 : connect remapVecData[11], Queue10_UInt8_31.io.deq.bits connect remapVecValids[11], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[11] node _remapindex_T_12 = add(UInt<4>(0hc), read_start_index) node remapindex_12 = rem(_remapindex_T_12, UInt<6>(0h20)) node _T_3654 = eq(UInt<1>(0h0), remapindex_12) when _T_3654 : connect remapVecData[12], Queue10_UInt8.io.deq.bits connect remapVecValids[12], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[12] node _T_3655 = eq(UInt<1>(0h1), remapindex_12) when _T_3655 : connect remapVecData[12], Queue10_UInt8_1.io.deq.bits connect remapVecValids[12], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[12] node _T_3656 = eq(UInt<2>(0h2), remapindex_12) when _T_3656 : connect remapVecData[12], Queue10_UInt8_2.io.deq.bits connect remapVecValids[12], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[12] node _T_3657 = eq(UInt<2>(0h3), remapindex_12) when _T_3657 : connect remapVecData[12], Queue10_UInt8_3.io.deq.bits connect remapVecValids[12], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[12] node _T_3658 = eq(UInt<3>(0h4), remapindex_12) when _T_3658 : connect remapVecData[12], Queue10_UInt8_4.io.deq.bits connect remapVecValids[12], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[12] node _T_3659 = eq(UInt<3>(0h5), remapindex_12) when _T_3659 : connect remapVecData[12], Queue10_UInt8_5.io.deq.bits connect remapVecValids[12], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[12] node _T_3660 = eq(UInt<3>(0h6), remapindex_12) when _T_3660 : connect remapVecData[12], Queue10_UInt8_6.io.deq.bits connect remapVecValids[12], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[12] node _T_3661 = eq(UInt<3>(0h7), remapindex_12) when _T_3661 : connect remapVecData[12], Queue10_UInt8_7.io.deq.bits connect remapVecValids[12], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[12] node _T_3662 = eq(UInt<4>(0h8), remapindex_12) when _T_3662 : connect remapVecData[12], Queue10_UInt8_8.io.deq.bits connect remapVecValids[12], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[12] node _T_3663 = eq(UInt<4>(0h9), remapindex_12) when _T_3663 : connect remapVecData[12], Queue10_UInt8_9.io.deq.bits connect remapVecValids[12], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[12] node _T_3664 = eq(UInt<4>(0ha), remapindex_12) when _T_3664 : connect remapVecData[12], Queue10_UInt8_10.io.deq.bits connect remapVecValids[12], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[12] node _T_3665 = eq(UInt<4>(0hb), remapindex_12) when _T_3665 : connect remapVecData[12], Queue10_UInt8_11.io.deq.bits connect remapVecValids[12], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[12] node _T_3666 = eq(UInt<4>(0hc), remapindex_12) when _T_3666 : connect remapVecData[12], Queue10_UInt8_12.io.deq.bits connect remapVecValids[12], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[12] node _T_3667 = eq(UInt<4>(0hd), remapindex_12) when _T_3667 : connect remapVecData[12], Queue10_UInt8_13.io.deq.bits connect remapVecValids[12], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[12] node _T_3668 = eq(UInt<4>(0he), remapindex_12) when _T_3668 : connect remapVecData[12], Queue10_UInt8_14.io.deq.bits connect remapVecValids[12], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[12] node _T_3669 = eq(UInt<4>(0hf), remapindex_12) when _T_3669 : connect remapVecData[12], Queue10_UInt8_15.io.deq.bits connect remapVecValids[12], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[12] node _T_3670 = eq(UInt<5>(0h10), remapindex_12) when _T_3670 : connect remapVecData[12], Queue10_UInt8_16.io.deq.bits connect remapVecValids[12], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[12] node _T_3671 = eq(UInt<5>(0h11), remapindex_12) when _T_3671 : connect remapVecData[12], Queue10_UInt8_17.io.deq.bits connect remapVecValids[12], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[12] node _T_3672 = eq(UInt<5>(0h12), remapindex_12) when _T_3672 : connect remapVecData[12], Queue10_UInt8_18.io.deq.bits connect remapVecValids[12], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[12] node _T_3673 = eq(UInt<5>(0h13), remapindex_12) when _T_3673 : connect remapVecData[12], Queue10_UInt8_19.io.deq.bits connect remapVecValids[12], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[12] node _T_3674 = eq(UInt<5>(0h14), remapindex_12) when _T_3674 : connect remapVecData[12], Queue10_UInt8_20.io.deq.bits connect remapVecValids[12], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[12] node _T_3675 = eq(UInt<5>(0h15), remapindex_12) when _T_3675 : connect remapVecData[12], Queue10_UInt8_21.io.deq.bits connect remapVecValids[12], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[12] node _T_3676 = eq(UInt<5>(0h16), remapindex_12) when _T_3676 : connect remapVecData[12], Queue10_UInt8_22.io.deq.bits connect remapVecValids[12], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[12] node _T_3677 = eq(UInt<5>(0h17), remapindex_12) when _T_3677 : connect remapVecData[12], Queue10_UInt8_23.io.deq.bits connect remapVecValids[12], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[12] node _T_3678 = eq(UInt<5>(0h18), remapindex_12) when _T_3678 : connect remapVecData[12], Queue10_UInt8_24.io.deq.bits connect remapVecValids[12], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[12] node _T_3679 = eq(UInt<5>(0h19), remapindex_12) when _T_3679 : connect remapVecData[12], Queue10_UInt8_25.io.deq.bits connect remapVecValids[12], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[12] node _T_3680 = eq(UInt<5>(0h1a), remapindex_12) when _T_3680 : connect remapVecData[12], Queue10_UInt8_26.io.deq.bits connect remapVecValids[12], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[12] node _T_3681 = eq(UInt<5>(0h1b), remapindex_12) when _T_3681 : connect remapVecData[12], Queue10_UInt8_27.io.deq.bits connect remapVecValids[12], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[12] node _T_3682 = eq(UInt<5>(0h1c), remapindex_12) when _T_3682 : connect remapVecData[12], Queue10_UInt8_28.io.deq.bits connect remapVecValids[12], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[12] node _T_3683 = eq(UInt<5>(0h1d), remapindex_12) when _T_3683 : connect remapVecData[12], Queue10_UInt8_29.io.deq.bits connect remapVecValids[12], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[12] node _T_3684 = eq(UInt<5>(0h1e), remapindex_12) when _T_3684 : connect remapVecData[12], Queue10_UInt8_30.io.deq.bits connect remapVecValids[12], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[12] node _T_3685 = eq(UInt<5>(0h1f), remapindex_12) when _T_3685 : connect remapVecData[12], Queue10_UInt8_31.io.deq.bits connect remapVecValids[12], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[12] node _remapindex_T_13 = add(UInt<4>(0hd), read_start_index) node remapindex_13 = rem(_remapindex_T_13, UInt<6>(0h20)) node _T_3686 = eq(UInt<1>(0h0), remapindex_13) when _T_3686 : connect remapVecData[13], Queue10_UInt8.io.deq.bits connect remapVecValids[13], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[13] node _T_3687 = eq(UInt<1>(0h1), remapindex_13) when _T_3687 : connect remapVecData[13], Queue10_UInt8_1.io.deq.bits connect remapVecValids[13], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[13] node _T_3688 = eq(UInt<2>(0h2), remapindex_13) when _T_3688 : connect remapVecData[13], Queue10_UInt8_2.io.deq.bits connect remapVecValids[13], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[13] node _T_3689 = eq(UInt<2>(0h3), remapindex_13) when _T_3689 : connect remapVecData[13], Queue10_UInt8_3.io.deq.bits connect remapVecValids[13], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[13] node _T_3690 = eq(UInt<3>(0h4), remapindex_13) when _T_3690 : connect remapVecData[13], Queue10_UInt8_4.io.deq.bits connect remapVecValids[13], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[13] node _T_3691 = eq(UInt<3>(0h5), remapindex_13) when _T_3691 : connect remapVecData[13], Queue10_UInt8_5.io.deq.bits connect remapVecValids[13], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[13] node _T_3692 = eq(UInt<3>(0h6), remapindex_13) when _T_3692 : connect remapVecData[13], Queue10_UInt8_6.io.deq.bits connect remapVecValids[13], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[13] node _T_3693 = eq(UInt<3>(0h7), remapindex_13) when _T_3693 : connect remapVecData[13], Queue10_UInt8_7.io.deq.bits connect remapVecValids[13], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[13] node _T_3694 = eq(UInt<4>(0h8), remapindex_13) when _T_3694 : connect remapVecData[13], Queue10_UInt8_8.io.deq.bits connect remapVecValids[13], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[13] node _T_3695 = eq(UInt<4>(0h9), remapindex_13) when _T_3695 : connect remapVecData[13], Queue10_UInt8_9.io.deq.bits connect remapVecValids[13], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[13] node _T_3696 = eq(UInt<4>(0ha), remapindex_13) when _T_3696 : connect remapVecData[13], Queue10_UInt8_10.io.deq.bits connect remapVecValids[13], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[13] node _T_3697 = eq(UInt<4>(0hb), remapindex_13) when _T_3697 : connect remapVecData[13], Queue10_UInt8_11.io.deq.bits connect remapVecValids[13], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[13] node _T_3698 = eq(UInt<4>(0hc), remapindex_13) when _T_3698 : connect remapVecData[13], Queue10_UInt8_12.io.deq.bits connect remapVecValids[13], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[13] node _T_3699 = eq(UInt<4>(0hd), remapindex_13) when _T_3699 : connect remapVecData[13], Queue10_UInt8_13.io.deq.bits connect remapVecValids[13], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[13] node _T_3700 = eq(UInt<4>(0he), remapindex_13) when _T_3700 : connect remapVecData[13], Queue10_UInt8_14.io.deq.bits connect remapVecValids[13], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[13] node _T_3701 = eq(UInt<4>(0hf), remapindex_13) when _T_3701 : connect remapVecData[13], Queue10_UInt8_15.io.deq.bits connect remapVecValids[13], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[13] node _T_3702 = eq(UInt<5>(0h10), remapindex_13) when _T_3702 : connect remapVecData[13], Queue10_UInt8_16.io.deq.bits connect remapVecValids[13], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[13] node _T_3703 = eq(UInt<5>(0h11), remapindex_13) when _T_3703 : connect remapVecData[13], Queue10_UInt8_17.io.deq.bits connect remapVecValids[13], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[13] node _T_3704 = eq(UInt<5>(0h12), remapindex_13) when _T_3704 : connect remapVecData[13], Queue10_UInt8_18.io.deq.bits connect remapVecValids[13], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[13] node _T_3705 = eq(UInt<5>(0h13), remapindex_13) when _T_3705 : connect remapVecData[13], Queue10_UInt8_19.io.deq.bits connect remapVecValids[13], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[13] node _T_3706 = eq(UInt<5>(0h14), remapindex_13) when _T_3706 : connect remapVecData[13], Queue10_UInt8_20.io.deq.bits connect remapVecValids[13], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[13] node _T_3707 = eq(UInt<5>(0h15), remapindex_13) when _T_3707 : connect remapVecData[13], Queue10_UInt8_21.io.deq.bits connect remapVecValids[13], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[13] node _T_3708 = eq(UInt<5>(0h16), remapindex_13) when _T_3708 : connect remapVecData[13], Queue10_UInt8_22.io.deq.bits connect remapVecValids[13], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[13] node _T_3709 = eq(UInt<5>(0h17), remapindex_13) when _T_3709 : connect remapVecData[13], Queue10_UInt8_23.io.deq.bits connect remapVecValids[13], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[13] node _T_3710 = eq(UInt<5>(0h18), remapindex_13) when _T_3710 : connect remapVecData[13], Queue10_UInt8_24.io.deq.bits connect remapVecValids[13], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[13] node _T_3711 = eq(UInt<5>(0h19), remapindex_13) when _T_3711 : connect remapVecData[13], Queue10_UInt8_25.io.deq.bits connect remapVecValids[13], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[13] node _T_3712 = eq(UInt<5>(0h1a), remapindex_13) when _T_3712 : connect remapVecData[13], Queue10_UInt8_26.io.deq.bits connect remapVecValids[13], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[13] node _T_3713 = eq(UInt<5>(0h1b), remapindex_13) when _T_3713 : connect remapVecData[13], Queue10_UInt8_27.io.deq.bits connect remapVecValids[13], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[13] node _T_3714 = eq(UInt<5>(0h1c), remapindex_13) when _T_3714 : connect remapVecData[13], Queue10_UInt8_28.io.deq.bits connect remapVecValids[13], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[13] node _T_3715 = eq(UInt<5>(0h1d), remapindex_13) when _T_3715 : connect remapVecData[13], Queue10_UInt8_29.io.deq.bits connect remapVecValids[13], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[13] node _T_3716 = eq(UInt<5>(0h1e), remapindex_13) when _T_3716 : connect remapVecData[13], Queue10_UInt8_30.io.deq.bits connect remapVecValids[13], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[13] node _T_3717 = eq(UInt<5>(0h1f), remapindex_13) when _T_3717 : connect remapVecData[13], Queue10_UInt8_31.io.deq.bits connect remapVecValids[13], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[13] node _remapindex_T_14 = add(UInt<4>(0he), read_start_index) node remapindex_14 = rem(_remapindex_T_14, UInt<6>(0h20)) node _T_3718 = eq(UInt<1>(0h0), remapindex_14) when _T_3718 : connect remapVecData[14], Queue10_UInt8.io.deq.bits connect remapVecValids[14], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[14] node _T_3719 = eq(UInt<1>(0h1), remapindex_14) when _T_3719 : connect remapVecData[14], Queue10_UInt8_1.io.deq.bits connect remapVecValids[14], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[14] node _T_3720 = eq(UInt<2>(0h2), remapindex_14) when _T_3720 : connect remapVecData[14], Queue10_UInt8_2.io.deq.bits connect remapVecValids[14], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[14] node _T_3721 = eq(UInt<2>(0h3), remapindex_14) when _T_3721 : connect remapVecData[14], Queue10_UInt8_3.io.deq.bits connect remapVecValids[14], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[14] node _T_3722 = eq(UInt<3>(0h4), remapindex_14) when _T_3722 : connect remapVecData[14], Queue10_UInt8_4.io.deq.bits connect remapVecValids[14], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[14] node _T_3723 = eq(UInt<3>(0h5), remapindex_14) when _T_3723 : connect remapVecData[14], Queue10_UInt8_5.io.deq.bits connect remapVecValids[14], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[14] node _T_3724 = eq(UInt<3>(0h6), remapindex_14) when _T_3724 : connect remapVecData[14], Queue10_UInt8_6.io.deq.bits connect remapVecValids[14], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[14] node _T_3725 = eq(UInt<3>(0h7), remapindex_14) when _T_3725 : connect remapVecData[14], Queue10_UInt8_7.io.deq.bits connect remapVecValids[14], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[14] node _T_3726 = eq(UInt<4>(0h8), remapindex_14) when _T_3726 : connect remapVecData[14], Queue10_UInt8_8.io.deq.bits connect remapVecValids[14], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[14] node _T_3727 = eq(UInt<4>(0h9), remapindex_14) when _T_3727 : connect remapVecData[14], Queue10_UInt8_9.io.deq.bits connect remapVecValids[14], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[14] node _T_3728 = eq(UInt<4>(0ha), remapindex_14) when _T_3728 : connect remapVecData[14], Queue10_UInt8_10.io.deq.bits connect remapVecValids[14], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[14] node _T_3729 = eq(UInt<4>(0hb), remapindex_14) when _T_3729 : connect remapVecData[14], Queue10_UInt8_11.io.deq.bits connect remapVecValids[14], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[14] node _T_3730 = eq(UInt<4>(0hc), remapindex_14) when _T_3730 : connect remapVecData[14], Queue10_UInt8_12.io.deq.bits connect remapVecValids[14], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[14] node _T_3731 = eq(UInt<4>(0hd), remapindex_14) when _T_3731 : connect remapVecData[14], Queue10_UInt8_13.io.deq.bits connect remapVecValids[14], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[14] node _T_3732 = eq(UInt<4>(0he), remapindex_14) when _T_3732 : connect remapVecData[14], Queue10_UInt8_14.io.deq.bits connect remapVecValids[14], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[14] node _T_3733 = eq(UInt<4>(0hf), remapindex_14) when _T_3733 : connect remapVecData[14], Queue10_UInt8_15.io.deq.bits connect remapVecValids[14], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[14] node _T_3734 = eq(UInt<5>(0h10), remapindex_14) when _T_3734 : connect remapVecData[14], Queue10_UInt8_16.io.deq.bits connect remapVecValids[14], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[14] node _T_3735 = eq(UInt<5>(0h11), remapindex_14) when _T_3735 : connect remapVecData[14], Queue10_UInt8_17.io.deq.bits connect remapVecValids[14], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[14] node _T_3736 = eq(UInt<5>(0h12), remapindex_14) when _T_3736 : connect remapVecData[14], Queue10_UInt8_18.io.deq.bits connect remapVecValids[14], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[14] node _T_3737 = eq(UInt<5>(0h13), remapindex_14) when _T_3737 : connect remapVecData[14], Queue10_UInt8_19.io.deq.bits connect remapVecValids[14], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[14] node _T_3738 = eq(UInt<5>(0h14), remapindex_14) when _T_3738 : connect remapVecData[14], Queue10_UInt8_20.io.deq.bits connect remapVecValids[14], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[14] node _T_3739 = eq(UInt<5>(0h15), remapindex_14) when _T_3739 : connect remapVecData[14], Queue10_UInt8_21.io.deq.bits connect remapVecValids[14], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[14] node _T_3740 = eq(UInt<5>(0h16), remapindex_14) when _T_3740 : connect remapVecData[14], Queue10_UInt8_22.io.deq.bits connect remapVecValids[14], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[14] node _T_3741 = eq(UInt<5>(0h17), remapindex_14) when _T_3741 : connect remapVecData[14], Queue10_UInt8_23.io.deq.bits connect remapVecValids[14], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[14] node _T_3742 = eq(UInt<5>(0h18), remapindex_14) when _T_3742 : connect remapVecData[14], Queue10_UInt8_24.io.deq.bits connect remapVecValids[14], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[14] node _T_3743 = eq(UInt<5>(0h19), remapindex_14) when _T_3743 : connect remapVecData[14], Queue10_UInt8_25.io.deq.bits connect remapVecValids[14], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[14] node _T_3744 = eq(UInt<5>(0h1a), remapindex_14) when _T_3744 : connect remapVecData[14], Queue10_UInt8_26.io.deq.bits connect remapVecValids[14], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[14] node _T_3745 = eq(UInt<5>(0h1b), remapindex_14) when _T_3745 : connect remapVecData[14], Queue10_UInt8_27.io.deq.bits connect remapVecValids[14], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[14] node _T_3746 = eq(UInt<5>(0h1c), remapindex_14) when _T_3746 : connect remapVecData[14], Queue10_UInt8_28.io.deq.bits connect remapVecValids[14], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[14] node _T_3747 = eq(UInt<5>(0h1d), remapindex_14) when _T_3747 : connect remapVecData[14], Queue10_UInt8_29.io.deq.bits connect remapVecValids[14], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[14] node _T_3748 = eq(UInt<5>(0h1e), remapindex_14) when _T_3748 : connect remapVecData[14], Queue10_UInt8_30.io.deq.bits connect remapVecValids[14], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[14] node _T_3749 = eq(UInt<5>(0h1f), remapindex_14) when _T_3749 : connect remapVecData[14], Queue10_UInt8_31.io.deq.bits connect remapVecValids[14], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[14] node _remapindex_T_15 = add(UInt<4>(0hf), read_start_index) node remapindex_15 = rem(_remapindex_T_15, UInt<6>(0h20)) node _T_3750 = eq(UInt<1>(0h0), remapindex_15) when _T_3750 : connect remapVecData[15], Queue10_UInt8.io.deq.bits connect remapVecValids[15], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[15] node _T_3751 = eq(UInt<1>(0h1), remapindex_15) when _T_3751 : connect remapVecData[15], Queue10_UInt8_1.io.deq.bits connect remapVecValids[15], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[15] node _T_3752 = eq(UInt<2>(0h2), remapindex_15) when _T_3752 : connect remapVecData[15], Queue10_UInt8_2.io.deq.bits connect remapVecValids[15], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[15] node _T_3753 = eq(UInt<2>(0h3), remapindex_15) when _T_3753 : connect remapVecData[15], Queue10_UInt8_3.io.deq.bits connect remapVecValids[15], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[15] node _T_3754 = eq(UInt<3>(0h4), remapindex_15) when _T_3754 : connect remapVecData[15], Queue10_UInt8_4.io.deq.bits connect remapVecValids[15], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[15] node _T_3755 = eq(UInt<3>(0h5), remapindex_15) when _T_3755 : connect remapVecData[15], Queue10_UInt8_5.io.deq.bits connect remapVecValids[15], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[15] node _T_3756 = eq(UInt<3>(0h6), remapindex_15) when _T_3756 : connect remapVecData[15], Queue10_UInt8_6.io.deq.bits connect remapVecValids[15], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[15] node _T_3757 = eq(UInt<3>(0h7), remapindex_15) when _T_3757 : connect remapVecData[15], Queue10_UInt8_7.io.deq.bits connect remapVecValids[15], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[15] node _T_3758 = eq(UInt<4>(0h8), remapindex_15) when _T_3758 : connect remapVecData[15], Queue10_UInt8_8.io.deq.bits connect remapVecValids[15], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[15] node _T_3759 = eq(UInt<4>(0h9), remapindex_15) when _T_3759 : connect remapVecData[15], Queue10_UInt8_9.io.deq.bits connect remapVecValids[15], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[15] node _T_3760 = eq(UInt<4>(0ha), remapindex_15) when _T_3760 : connect remapVecData[15], Queue10_UInt8_10.io.deq.bits connect remapVecValids[15], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[15] node _T_3761 = eq(UInt<4>(0hb), remapindex_15) when _T_3761 : connect remapVecData[15], Queue10_UInt8_11.io.deq.bits connect remapVecValids[15], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[15] node _T_3762 = eq(UInt<4>(0hc), remapindex_15) when _T_3762 : connect remapVecData[15], Queue10_UInt8_12.io.deq.bits connect remapVecValids[15], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[15] node _T_3763 = eq(UInt<4>(0hd), remapindex_15) when _T_3763 : connect remapVecData[15], Queue10_UInt8_13.io.deq.bits connect remapVecValids[15], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[15] node _T_3764 = eq(UInt<4>(0he), remapindex_15) when _T_3764 : connect remapVecData[15], Queue10_UInt8_14.io.deq.bits connect remapVecValids[15], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[15] node _T_3765 = eq(UInt<4>(0hf), remapindex_15) when _T_3765 : connect remapVecData[15], Queue10_UInt8_15.io.deq.bits connect remapVecValids[15], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[15] node _T_3766 = eq(UInt<5>(0h10), remapindex_15) when _T_3766 : connect remapVecData[15], Queue10_UInt8_16.io.deq.bits connect remapVecValids[15], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[15] node _T_3767 = eq(UInt<5>(0h11), remapindex_15) when _T_3767 : connect remapVecData[15], Queue10_UInt8_17.io.deq.bits connect remapVecValids[15], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[15] node _T_3768 = eq(UInt<5>(0h12), remapindex_15) when _T_3768 : connect remapVecData[15], Queue10_UInt8_18.io.deq.bits connect remapVecValids[15], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[15] node _T_3769 = eq(UInt<5>(0h13), remapindex_15) when _T_3769 : connect remapVecData[15], Queue10_UInt8_19.io.deq.bits connect remapVecValids[15], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[15] node _T_3770 = eq(UInt<5>(0h14), remapindex_15) when _T_3770 : connect remapVecData[15], Queue10_UInt8_20.io.deq.bits connect remapVecValids[15], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[15] node _T_3771 = eq(UInt<5>(0h15), remapindex_15) when _T_3771 : connect remapVecData[15], Queue10_UInt8_21.io.deq.bits connect remapVecValids[15], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[15] node _T_3772 = eq(UInt<5>(0h16), remapindex_15) when _T_3772 : connect remapVecData[15], Queue10_UInt8_22.io.deq.bits connect remapVecValids[15], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[15] node _T_3773 = eq(UInt<5>(0h17), remapindex_15) when _T_3773 : connect remapVecData[15], Queue10_UInt8_23.io.deq.bits connect remapVecValids[15], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[15] node _T_3774 = eq(UInt<5>(0h18), remapindex_15) when _T_3774 : connect remapVecData[15], Queue10_UInt8_24.io.deq.bits connect remapVecValids[15], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[15] node _T_3775 = eq(UInt<5>(0h19), remapindex_15) when _T_3775 : connect remapVecData[15], Queue10_UInt8_25.io.deq.bits connect remapVecValids[15], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[15] node _T_3776 = eq(UInt<5>(0h1a), remapindex_15) when _T_3776 : connect remapVecData[15], Queue10_UInt8_26.io.deq.bits connect remapVecValids[15], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[15] node _T_3777 = eq(UInt<5>(0h1b), remapindex_15) when _T_3777 : connect remapVecData[15], Queue10_UInt8_27.io.deq.bits connect remapVecValids[15], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[15] node _T_3778 = eq(UInt<5>(0h1c), remapindex_15) when _T_3778 : connect remapVecData[15], Queue10_UInt8_28.io.deq.bits connect remapVecValids[15], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[15] node _T_3779 = eq(UInt<5>(0h1d), remapindex_15) when _T_3779 : connect remapVecData[15], Queue10_UInt8_29.io.deq.bits connect remapVecValids[15], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[15] node _T_3780 = eq(UInt<5>(0h1e), remapindex_15) when _T_3780 : connect remapVecData[15], Queue10_UInt8_30.io.deq.bits connect remapVecValids[15], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[15] node _T_3781 = eq(UInt<5>(0h1f), remapindex_15) when _T_3781 : connect remapVecData[15], Queue10_UInt8_31.io.deq.bits connect remapVecValids[15], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[15] node _remapindex_T_16 = add(UInt<5>(0h10), read_start_index) node remapindex_16 = rem(_remapindex_T_16, UInt<6>(0h20)) node _T_3782 = eq(UInt<1>(0h0), remapindex_16) when _T_3782 : connect remapVecData[16], Queue10_UInt8.io.deq.bits connect remapVecValids[16], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[16] node _T_3783 = eq(UInt<1>(0h1), remapindex_16) when _T_3783 : connect remapVecData[16], Queue10_UInt8_1.io.deq.bits connect remapVecValids[16], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[16] node _T_3784 = eq(UInt<2>(0h2), remapindex_16) when _T_3784 : connect remapVecData[16], Queue10_UInt8_2.io.deq.bits connect remapVecValids[16], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[16] node _T_3785 = eq(UInt<2>(0h3), remapindex_16) when _T_3785 : connect remapVecData[16], Queue10_UInt8_3.io.deq.bits connect remapVecValids[16], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[16] node _T_3786 = eq(UInt<3>(0h4), remapindex_16) when _T_3786 : connect remapVecData[16], Queue10_UInt8_4.io.deq.bits connect remapVecValids[16], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[16] node _T_3787 = eq(UInt<3>(0h5), remapindex_16) when _T_3787 : connect remapVecData[16], Queue10_UInt8_5.io.deq.bits connect remapVecValids[16], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[16] node _T_3788 = eq(UInt<3>(0h6), remapindex_16) when _T_3788 : connect remapVecData[16], Queue10_UInt8_6.io.deq.bits connect remapVecValids[16], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[16] node _T_3789 = eq(UInt<3>(0h7), remapindex_16) when _T_3789 : connect remapVecData[16], Queue10_UInt8_7.io.deq.bits connect remapVecValids[16], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[16] node _T_3790 = eq(UInt<4>(0h8), remapindex_16) when _T_3790 : connect remapVecData[16], Queue10_UInt8_8.io.deq.bits connect remapVecValids[16], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[16] node _T_3791 = eq(UInt<4>(0h9), remapindex_16) when _T_3791 : connect remapVecData[16], Queue10_UInt8_9.io.deq.bits connect remapVecValids[16], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[16] node _T_3792 = eq(UInt<4>(0ha), remapindex_16) when _T_3792 : connect remapVecData[16], Queue10_UInt8_10.io.deq.bits connect remapVecValids[16], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[16] node _T_3793 = eq(UInt<4>(0hb), remapindex_16) when _T_3793 : connect remapVecData[16], Queue10_UInt8_11.io.deq.bits connect remapVecValids[16], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[16] node _T_3794 = eq(UInt<4>(0hc), remapindex_16) when _T_3794 : connect remapVecData[16], Queue10_UInt8_12.io.deq.bits connect remapVecValids[16], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[16] node _T_3795 = eq(UInt<4>(0hd), remapindex_16) when _T_3795 : connect remapVecData[16], Queue10_UInt8_13.io.deq.bits connect remapVecValids[16], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[16] node _T_3796 = eq(UInt<4>(0he), remapindex_16) when _T_3796 : connect remapVecData[16], Queue10_UInt8_14.io.deq.bits connect remapVecValids[16], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[16] node _T_3797 = eq(UInt<4>(0hf), remapindex_16) when _T_3797 : connect remapVecData[16], Queue10_UInt8_15.io.deq.bits connect remapVecValids[16], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[16] node _T_3798 = eq(UInt<5>(0h10), remapindex_16) when _T_3798 : connect remapVecData[16], Queue10_UInt8_16.io.deq.bits connect remapVecValids[16], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[16] node _T_3799 = eq(UInt<5>(0h11), remapindex_16) when _T_3799 : connect remapVecData[16], Queue10_UInt8_17.io.deq.bits connect remapVecValids[16], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[16] node _T_3800 = eq(UInt<5>(0h12), remapindex_16) when _T_3800 : connect remapVecData[16], Queue10_UInt8_18.io.deq.bits connect remapVecValids[16], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[16] node _T_3801 = eq(UInt<5>(0h13), remapindex_16) when _T_3801 : connect remapVecData[16], Queue10_UInt8_19.io.deq.bits connect remapVecValids[16], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[16] node _T_3802 = eq(UInt<5>(0h14), remapindex_16) when _T_3802 : connect remapVecData[16], Queue10_UInt8_20.io.deq.bits connect remapVecValids[16], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[16] node _T_3803 = eq(UInt<5>(0h15), remapindex_16) when _T_3803 : connect remapVecData[16], Queue10_UInt8_21.io.deq.bits connect remapVecValids[16], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[16] node _T_3804 = eq(UInt<5>(0h16), remapindex_16) when _T_3804 : connect remapVecData[16], Queue10_UInt8_22.io.deq.bits connect remapVecValids[16], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[16] node _T_3805 = eq(UInt<5>(0h17), remapindex_16) when _T_3805 : connect remapVecData[16], Queue10_UInt8_23.io.deq.bits connect remapVecValids[16], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[16] node _T_3806 = eq(UInt<5>(0h18), remapindex_16) when _T_3806 : connect remapVecData[16], Queue10_UInt8_24.io.deq.bits connect remapVecValids[16], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[16] node _T_3807 = eq(UInt<5>(0h19), remapindex_16) when _T_3807 : connect remapVecData[16], Queue10_UInt8_25.io.deq.bits connect remapVecValids[16], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[16] node _T_3808 = eq(UInt<5>(0h1a), remapindex_16) when _T_3808 : connect remapVecData[16], Queue10_UInt8_26.io.deq.bits connect remapVecValids[16], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[16] node _T_3809 = eq(UInt<5>(0h1b), remapindex_16) when _T_3809 : connect remapVecData[16], Queue10_UInt8_27.io.deq.bits connect remapVecValids[16], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[16] node _T_3810 = eq(UInt<5>(0h1c), remapindex_16) when _T_3810 : connect remapVecData[16], Queue10_UInt8_28.io.deq.bits connect remapVecValids[16], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[16] node _T_3811 = eq(UInt<5>(0h1d), remapindex_16) when _T_3811 : connect remapVecData[16], Queue10_UInt8_29.io.deq.bits connect remapVecValids[16], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[16] node _T_3812 = eq(UInt<5>(0h1e), remapindex_16) when _T_3812 : connect remapVecData[16], Queue10_UInt8_30.io.deq.bits connect remapVecValids[16], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[16] node _T_3813 = eq(UInt<5>(0h1f), remapindex_16) when _T_3813 : connect remapVecData[16], Queue10_UInt8_31.io.deq.bits connect remapVecValids[16], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[16] node _remapindex_T_17 = add(UInt<5>(0h11), read_start_index) node remapindex_17 = rem(_remapindex_T_17, UInt<6>(0h20)) node _T_3814 = eq(UInt<1>(0h0), remapindex_17) when _T_3814 : connect remapVecData[17], Queue10_UInt8.io.deq.bits connect remapVecValids[17], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[17] node _T_3815 = eq(UInt<1>(0h1), remapindex_17) when _T_3815 : connect remapVecData[17], Queue10_UInt8_1.io.deq.bits connect remapVecValids[17], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[17] node _T_3816 = eq(UInt<2>(0h2), remapindex_17) when _T_3816 : connect remapVecData[17], Queue10_UInt8_2.io.deq.bits connect remapVecValids[17], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[17] node _T_3817 = eq(UInt<2>(0h3), remapindex_17) when _T_3817 : connect remapVecData[17], Queue10_UInt8_3.io.deq.bits connect remapVecValids[17], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[17] node _T_3818 = eq(UInt<3>(0h4), remapindex_17) when _T_3818 : connect remapVecData[17], Queue10_UInt8_4.io.deq.bits connect remapVecValids[17], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[17] node _T_3819 = eq(UInt<3>(0h5), remapindex_17) when _T_3819 : connect remapVecData[17], Queue10_UInt8_5.io.deq.bits connect remapVecValids[17], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[17] node _T_3820 = eq(UInt<3>(0h6), remapindex_17) when _T_3820 : connect remapVecData[17], Queue10_UInt8_6.io.deq.bits connect remapVecValids[17], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[17] node _T_3821 = eq(UInt<3>(0h7), remapindex_17) when _T_3821 : connect remapVecData[17], Queue10_UInt8_7.io.deq.bits connect remapVecValids[17], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[17] node _T_3822 = eq(UInt<4>(0h8), remapindex_17) when _T_3822 : connect remapVecData[17], Queue10_UInt8_8.io.deq.bits connect remapVecValids[17], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[17] node _T_3823 = eq(UInt<4>(0h9), remapindex_17) when _T_3823 : connect remapVecData[17], Queue10_UInt8_9.io.deq.bits connect remapVecValids[17], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[17] node _T_3824 = eq(UInt<4>(0ha), remapindex_17) when _T_3824 : connect remapVecData[17], Queue10_UInt8_10.io.deq.bits connect remapVecValids[17], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[17] node _T_3825 = eq(UInt<4>(0hb), remapindex_17) when _T_3825 : connect remapVecData[17], Queue10_UInt8_11.io.deq.bits connect remapVecValids[17], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[17] node _T_3826 = eq(UInt<4>(0hc), remapindex_17) when _T_3826 : connect remapVecData[17], Queue10_UInt8_12.io.deq.bits connect remapVecValids[17], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[17] node _T_3827 = eq(UInt<4>(0hd), remapindex_17) when _T_3827 : connect remapVecData[17], Queue10_UInt8_13.io.deq.bits connect remapVecValids[17], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[17] node _T_3828 = eq(UInt<4>(0he), remapindex_17) when _T_3828 : connect remapVecData[17], Queue10_UInt8_14.io.deq.bits connect remapVecValids[17], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[17] node _T_3829 = eq(UInt<4>(0hf), remapindex_17) when _T_3829 : connect remapVecData[17], Queue10_UInt8_15.io.deq.bits connect remapVecValids[17], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[17] node _T_3830 = eq(UInt<5>(0h10), remapindex_17) when _T_3830 : connect remapVecData[17], Queue10_UInt8_16.io.deq.bits connect remapVecValids[17], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[17] node _T_3831 = eq(UInt<5>(0h11), remapindex_17) when _T_3831 : connect remapVecData[17], Queue10_UInt8_17.io.deq.bits connect remapVecValids[17], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[17] node _T_3832 = eq(UInt<5>(0h12), remapindex_17) when _T_3832 : connect remapVecData[17], Queue10_UInt8_18.io.deq.bits connect remapVecValids[17], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[17] node _T_3833 = eq(UInt<5>(0h13), remapindex_17) when _T_3833 : connect remapVecData[17], Queue10_UInt8_19.io.deq.bits connect remapVecValids[17], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[17] node _T_3834 = eq(UInt<5>(0h14), remapindex_17) when _T_3834 : connect remapVecData[17], Queue10_UInt8_20.io.deq.bits connect remapVecValids[17], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[17] node _T_3835 = eq(UInt<5>(0h15), remapindex_17) when _T_3835 : connect remapVecData[17], Queue10_UInt8_21.io.deq.bits connect remapVecValids[17], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[17] node _T_3836 = eq(UInt<5>(0h16), remapindex_17) when _T_3836 : connect remapVecData[17], Queue10_UInt8_22.io.deq.bits connect remapVecValids[17], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[17] node _T_3837 = eq(UInt<5>(0h17), remapindex_17) when _T_3837 : connect remapVecData[17], Queue10_UInt8_23.io.deq.bits connect remapVecValids[17], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[17] node _T_3838 = eq(UInt<5>(0h18), remapindex_17) when _T_3838 : connect remapVecData[17], Queue10_UInt8_24.io.deq.bits connect remapVecValids[17], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[17] node _T_3839 = eq(UInt<5>(0h19), remapindex_17) when _T_3839 : connect remapVecData[17], Queue10_UInt8_25.io.deq.bits connect remapVecValids[17], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[17] node _T_3840 = eq(UInt<5>(0h1a), remapindex_17) when _T_3840 : connect remapVecData[17], Queue10_UInt8_26.io.deq.bits connect remapVecValids[17], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[17] node _T_3841 = eq(UInt<5>(0h1b), remapindex_17) when _T_3841 : connect remapVecData[17], Queue10_UInt8_27.io.deq.bits connect remapVecValids[17], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[17] node _T_3842 = eq(UInt<5>(0h1c), remapindex_17) when _T_3842 : connect remapVecData[17], Queue10_UInt8_28.io.deq.bits connect remapVecValids[17], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[17] node _T_3843 = eq(UInt<5>(0h1d), remapindex_17) when _T_3843 : connect remapVecData[17], Queue10_UInt8_29.io.deq.bits connect remapVecValids[17], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[17] node _T_3844 = eq(UInt<5>(0h1e), remapindex_17) when _T_3844 : connect remapVecData[17], Queue10_UInt8_30.io.deq.bits connect remapVecValids[17], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[17] node _T_3845 = eq(UInt<5>(0h1f), remapindex_17) when _T_3845 : connect remapVecData[17], Queue10_UInt8_31.io.deq.bits connect remapVecValids[17], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[17] node _remapindex_T_18 = add(UInt<5>(0h12), read_start_index) node remapindex_18 = rem(_remapindex_T_18, UInt<6>(0h20)) node _T_3846 = eq(UInt<1>(0h0), remapindex_18) when _T_3846 : connect remapVecData[18], Queue10_UInt8.io.deq.bits connect remapVecValids[18], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[18] node _T_3847 = eq(UInt<1>(0h1), remapindex_18) when _T_3847 : connect remapVecData[18], Queue10_UInt8_1.io.deq.bits connect remapVecValids[18], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[18] node _T_3848 = eq(UInt<2>(0h2), remapindex_18) when _T_3848 : connect remapVecData[18], Queue10_UInt8_2.io.deq.bits connect remapVecValids[18], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[18] node _T_3849 = eq(UInt<2>(0h3), remapindex_18) when _T_3849 : connect remapVecData[18], Queue10_UInt8_3.io.deq.bits connect remapVecValids[18], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[18] node _T_3850 = eq(UInt<3>(0h4), remapindex_18) when _T_3850 : connect remapVecData[18], Queue10_UInt8_4.io.deq.bits connect remapVecValids[18], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[18] node _T_3851 = eq(UInt<3>(0h5), remapindex_18) when _T_3851 : connect remapVecData[18], Queue10_UInt8_5.io.deq.bits connect remapVecValids[18], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[18] node _T_3852 = eq(UInt<3>(0h6), remapindex_18) when _T_3852 : connect remapVecData[18], Queue10_UInt8_6.io.deq.bits connect remapVecValids[18], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[18] node _T_3853 = eq(UInt<3>(0h7), remapindex_18) when _T_3853 : connect remapVecData[18], Queue10_UInt8_7.io.deq.bits connect remapVecValids[18], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[18] node _T_3854 = eq(UInt<4>(0h8), remapindex_18) when _T_3854 : connect remapVecData[18], Queue10_UInt8_8.io.deq.bits connect remapVecValids[18], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[18] node _T_3855 = eq(UInt<4>(0h9), remapindex_18) when _T_3855 : connect remapVecData[18], Queue10_UInt8_9.io.deq.bits connect remapVecValids[18], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[18] node _T_3856 = eq(UInt<4>(0ha), remapindex_18) when _T_3856 : connect remapVecData[18], Queue10_UInt8_10.io.deq.bits connect remapVecValids[18], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[18] node _T_3857 = eq(UInt<4>(0hb), remapindex_18) when _T_3857 : connect remapVecData[18], Queue10_UInt8_11.io.deq.bits connect remapVecValids[18], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[18] node _T_3858 = eq(UInt<4>(0hc), remapindex_18) when _T_3858 : connect remapVecData[18], Queue10_UInt8_12.io.deq.bits connect remapVecValids[18], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[18] node _T_3859 = eq(UInt<4>(0hd), remapindex_18) when _T_3859 : connect remapVecData[18], Queue10_UInt8_13.io.deq.bits connect remapVecValids[18], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[18] node _T_3860 = eq(UInt<4>(0he), remapindex_18) when _T_3860 : connect remapVecData[18], Queue10_UInt8_14.io.deq.bits connect remapVecValids[18], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[18] node _T_3861 = eq(UInt<4>(0hf), remapindex_18) when _T_3861 : connect remapVecData[18], Queue10_UInt8_15.io.deq.bits connect remapVecValids[18], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[18] node _T_3862 = eq(UInt<5>(0h10), remapindex_18) when _T_3862 : connect remapVecData[18], Queue10_UInt8_16.io.deq.bits connect remapVecValids[18], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[18] node _T_3863 = eq(UInt<5>(0h11), remapindex_18) when _T_3863 : connect remapVecData[18], Queue10_UInt8_17.io.deq.bits connect remapVecValids[18], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[18] node _T_3864 = eq(UInt<5>(0h12), remapindex_18) when _T_3864 : connect remapVecData[18], Queue10_UInt8_18.io.deq.bits connect remapVecValids[18], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[18] node _T_3865 = eq(UInt<5>(0h13), remapindex_18) when _T_3865 : connect remapVecData[18], Queue10_UInt8_19.io.deq.bits connect remapVecValids[18], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[18] node _T_3866 = eq(UInt<5>(0h14), remapindex_18) when _T_3866 : connect remapVecData[18], Queue10_UInt8_20.io.deq.bits connect remapVecValids[18], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[18] node _T_3867 = eq(UInt<5>(0h15), remapindex_18) when _T_3867 : connect remapVecData[18], Queue10_UInt8_21.io.deq.bits connect remapVecValids[18], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[18] node _T_3868 = eq(UInt<5>(0h16), remapindex_18) when _T_3868 : connect remapVecData[18], Queue10_UInt8_22.io.deq.bits connect remapVecValids[18], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[18] node _T_3869 = eq(UInt<5>(0h17), remapindex_18) when _T_3869 : connect remapVecData[18], Queue10_UInt8_23.io.deq.bits connect remapVecValids[18], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[18] node _T_3870 = eq(UInt<5>(0h18), remapindex_18) when _T_3870 : connect remapVecData[18], Queue10_UInt8_24.io.deq.bits connect remapVecValids[18], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[18] node _T_3871 = eq(UInt<5>(0h19), remapindex_18) when _T_3871 : connect remapVecData[18], Queue10_UInt8_25.io.deq.bits connect remapVecValids[18], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[18] node _T_3872 = eq(UInt<5>(0h1a), remapindex_18) when _T_3872 : connect remapVecData[18], Queue10_UInt8_26.io.deq.bits connect remapVecValids[18], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[18] node _T_3873 = eq(UInt<5>(0h1b), remapindex_18) when _T_3873 : connect remapVecData[18], Queue10_UInt8_27.io.deq.bits connect remapVecValids[18], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[18] node _T_3874 = eq(UInt<5>(0h1c), remapindex_18) when _T_3874 : connect remapVecData[18], Queue10_UInt8_28.io.deq.bits connect remapVecValids[18], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[18] node _T_3875 = eq(UInt<5>(0h1d), remapindex_18) when _T_3875 : connect remapVecData[18], Queue10_UInt8_29.io.deq.bits connect remapVecValids[18], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[18] node _T_3876 = eq(UInt<5>(0h1e), remapindex_18) when _T_3876 : connect remapVecData[18], Queue10_UInt8_30.io.deq.bits connect remapVecValids[18], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[18] node _T_3877 = eq(UInt<5>(0h1f), remapindex_18) when _T_3877 : connect remapVecData[18], Queue10_UInt8_31.io.deq.bits connect remapVecValids[18], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[18] node _remapindex_T_19 = add(UInt<5>(0h13), read_start_index) node remapindex_19 = rem(_remapindex_T_19, UInt<6>(0h20)) node _T_3878 = eq(UInt<1>(0h0), remapindex_19) when _T_3878 : connect remapVecData[19], Queue10_UInt8.io.deq.bits connect remapVecValids[19], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[19] node _T_3879 = eq(UInt<1>(0h1), remapindex_19) when _T_3879 : connect remapVecData[19], Queue10_UInt8_1.io.deq.bits connect remapVecValids[19], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[19] node _T_3880 = eq(UInt<2>(0h2), remapindex_19) when _T_3880 : connect remapVecData[19], Queue10_UInt8_2.io.deq.bits connect remapVecValids[19], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[19] node _T_3881 = eq(UInt<2>(0h3), remapindex_19) when _T_3881 : connect remapVecData[19], Queue10_UInt8_3.io.deq.bits connect remapVecValids[19], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[19] node _T_3882 = eq(UInt<3>(0h4), remapindex_19) when _T_3882 : connect remapVecData[19], Queue10_UInt8_4.io.deq.bits connect remapVecValids[19], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[19] node _T_3883 = eq(UInt<3>(0h5), remapindex_19) when _T_3883 : connect remapVecData[19], Queue10_UInt8_5.io.deq.bits connect remapVecValids[19], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[19] node _T_3884 = eq(UInt<3>(0h6), remapindex_19) when _T_3884 : connect remapVecData[19], Queue10_UInt8_6.io.deq.bits connect remapVecValids[19], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[19] node _T_3885 = eq(UInt<3>(0h7), remapindex_19) when _T_3885 : connect remapVecData[19], Queue10_UInt8_7.io.deq.bits connect remapVecValids[19], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[19] node _T_3886 = eq(UInt<4>(0h8), remapindex_19) when _T_3886 : connect remapVecData[19], Queue10_UInt8_8.io.deq.bits connect remapVecValids[19], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[19] node _T_3887 = eq(UInt<4>(0h9), remapindex_19) when _T_3887 : connect remapVecData[19], Queue10_UInt8_9.io.deq.bits connect remapVecValids[19], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[19] node _T_3888 = eq(UInt<4>(0ha), remapindex_19) when _T_3888 : connect remapVecData[19], Queue10_UInt8_10.io.deq.bits connect remapVecValids[19], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[19] node _T_3889 = eq(UInt<4>(0hb), remapindex_19) when _T_3889 : connect remapVecData[19], Queue10_UInt8_11.io.deq.bits connect remapVecValids[19], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[19] node _T_3890 = eq(UInt<4>(0hc), remapindex_19) when _T_3890 : connect remapVecData[19], Queue10_UInt8_12.io.deq.bits connect remapVecValids[19], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[19] node _T_3891 = eq(UInt<4>(0hd), remapindex_19) when _T_3891 : connect remapVecData[19], Queue10_UInt8_13.io.deq.bits connect remapVecValids[19], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[19] node _T_3892 = eq(UInt<4>(0he), remapindex_19) when _T_3892 : connect remapVecData[19], Queue10_UInt8_14.io.deq.bits connect remapVecValids[19], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[19] node _T_3893 = eq(UInt<4>(0hf), remapindex_19) when _T_3893 : connect remapVecData[19], Queue10_UInt8_15.io.deq.bits connect remapVecValids[19], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[19] node _T_3894 = eq(UInt<5>(0h10), remapindex_19) when _T_3894 : connect remapVecData[19], Queue10_UInt8_16.io.deq.bits connect remapVecValids[19], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[19] node _T_3895 = eq(UInt<5>(0h11), remapindex_19) when _T_3895 : connect remapVecData[19], Queue10_UInt8_17.io.deq.bits connect remapVecValids[19], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[19] node _T_3896 = eq(UInt<5>(0h12), remapindex_19) when _T_3896 : connect remapVecData[19], Queue10_UInt8_18.io.deq.bits connect remapVecValids[19], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[19] node _T_3897 = eq(UInt<5>(0h13), remapindex_19) when _T_3897 : connect remapVecData[19], Queue10_UInt8_19.io.deq.bits connect remapVecValids[19], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[19] node _T_3898 = eq(UInt<5>(0h14), remapindex_19) when _T_3898 : connect remapVecData[19], Queue10_UInt8_20.io.deq.bits connect remapVecValids[19], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[19] node _T_3899 = eq(UInt<5>(0h15), remapindex_19) when _T_3899 : connect remapVecData[19], Queue10_UInt8_21.io.deq.bits connect remapVecValids[19], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[19] node _T_3900 = eq(UInt<5>(0h16), remapindex_19) when _T_3900 : connect remapVecData[19], Queue10_UInt8_22.io.deq.bits connect remapVecValids[19], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[19] node _T_3901 = eq(UInt<5>(0h17), remapindex_19) when _T_3901 : connect remapVecData[19], Queue10_UInt8_23.io.deq.bits connect remapVecValids[19], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[19] node _T_3902 = eq(UInt<5>(0h18), remapindex_19) when _T_3902 : connect remapVecData[19], Queue10_UInt8_24.io.deq.bits connect remapVecValids[19], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[19] node _T_3903 = eq(UInt<5>(0h19), remapindex_19) when _T_3903 : connect remapVecData[19], Queue10_UInt8_25.io.deq.bits connect remapVecValids[19], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[19] node _T_3904 = eq(UInt<5>(0h1a), remapindex_19) when _T_3904 : connect remapVecData[19], Queue10_UInt8_26.io.deq.bits connect remapVecValids[19], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[19] node _T_3905 = eq(UInt<5>(0h1b), remapindex_19) when _T_3905 : connect remapVecData[19], Queue10_UInt8_27.io.deq.bits connect remapVecValids[19], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[19] node _T_3906 = eq(UInt<5>(0h1c), remapindex_19) when _T_3906 : connect remapVecData[19], Queue10_UInt8_28.io.deq.bits connect remapVecValids[19], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[19] node _T_3907 = eq(UInt<5>(0h1d), remapindex_19) when _T_3907 : connect remapVecData[19], Queue10_UInt8_29.io.deq.bits connect remapVecValids[19], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[19] node _T_3908 = eq(UInt<5>(0h1e), remapindex_19) when _T_3908 : connect remapVecData[19], Queue10_UInt8_30.io.deq.bits connect remapVecValids[19], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[19] node _T_3909 = eq(UInt<5>(0h1f), remapindex_19) when _T_3909 : connect remapVecData[19], Queue10_UInt8_31.io.deq.bits connect remapVecValids[19], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[19] node _remapindex_T_20 = add(UInt<5>(0h14), read_start_index) node remapindex_20 = rem(_remapindex_T_20, UInt<6>(0h20)) node _T_3910 = eq(UInt<1>(0h0), remapindex_20) when _T_3910 : connect remapVecData[20], Queue10_UInt8.io.deq.bits connect remapVecValids[20], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[20] node _T_3911 = eq(UInt<1>(0h1), remapindex_20) when _T_3911 : connect remapVecData[20], Queue10_UInt8_1.io.deq.bits connect remapVecValids[20], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[20] node _T_3912 = eq(UInt<2>(0h2), remapindex_20) when _T_3912 : connect remapVecData[20], Queue10_UInt8_2.io.deq.bits connect remapVecValids[20], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[20] node _T_3913 = eq(UInt<2>(0h3), remapindex_20) when _T_3913 : connect remapVecData[20], Queue10_UInt8_3.io.deq.bits connect remapVecValids[20], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[20] node _T_3914 = eq(UInt<3>(0h4), remapindex_20) when _T_3914 : connect remapVecData[20], Queue10_UInt8_4.io.deq.bits connect remapVecValids[20], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[20] node _T_3915 = eq(UInt<3>(0h5), remapindex_20) when _T_3915 : connect remapVecData[20], Queue10_UInt8_5.io.deq.bits connect remapVecValids[20], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[20] node _T_3916 = eq(UInt<3>(0h6), remapindex_20) when _T_3916 : connect remapVecData[20], Queue10_UInt8_6.io.deq.bits connect remapVecValids[20], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[20] node _T_3917 = eq(UInt<3>(0h7), remapindex_20) when _T_3917 : connect remapVecData[20], Queue10_UInt8_7.io.deq.bits connect remapVecValids[20], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[20] node _T_3918 = eq(UInt<4>(0h8), remapindex_20) when _T_3918 : connect remapVecData[20], Queue10_UInt8_8.io.deq.bits connect remapVecValids[20], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[20] node _T_3919 = eq(UInt<4>(0h9), remapindex_20) when _T_3919 : connect remapVecData[20], Queue10_UInt8_9.io.deq.bits connect remapVecValids[20], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[20] node _T_3920 = eq(UInt<4>(0ha), remapindex_20) when _T_3920 : connect remapVecData[20], Queue10_UInt8_10.io.deq.bits connect remapVecValids[20], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[20] node _T_3921 = eq(UInt<4>(0hb), remapindex_20) when _T_3921 : connect remapVecData[20], Queue10_UInt8_11.io.deq.bits connect remapVecValids[20], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[20] node _T_3922 = eq(UInt<4>(0hc), remapindex_20) when _T_3922 : connect remapVecData[20], Queue10_UInt8_12.io.deq.bits connect remapVecValids[20], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[20] node _T_3923 = eq(UInt<4>(0hd), remapindex_20) when _T_3923 : connect remapVecData[20], Queue10_UInt8_13.io.deq.bits connect remapVecValids[20], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[20] node _T_3924 = eq(UInt<4>(0he), remapindex_20) when _T_3924 : connect remapVecData[20], Queue10_UInt8_14.io.deq.bits connect remapVecValids[20], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[20] node _T_3925 = eq(UInt<4>(0hf), remapindex_20) when _T_3925 : connect remapVecData[20], Queue10_UInt8_15.io.deq.bits connect remapVecValids[20], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[20] node _T_3926 = eq(UInt<5>(0h10), remapindex_20) when _T_3926 : connect remapVecData[20], Queue10_UInt8_16.io.deq.bits connect remapVecValids[20], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[20] node _T_3927 = eq(UInt<5>(0h11), remapindex_20) when _T_3927 : connect remapVecData[20], Queue10_UInt8_17.io.deq.bits connect remapVecValids[20], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[20] node _T_3928 = eq(UInt<5>(0h12), remapindex_20) when _T_3928 : connect remapVecData[20], Queue10_UInt8_18.io.deq.bits connect remapVecValids[20], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[20] node _T_3929 = eq(UInt<5>(0h13), remapindex_20) when _T_3929 : connect remapVecData[20], Queue10_UInt8_19.io.deq.bits connect remapVecValids[20], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[20] node _T_3930 = eq(UInt<5>(0h14), remapindex_20) when _T_3930 : connect remapVecData[20], Queue10_UInt8_20.io.deq.bits connect remapVecValids[20], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[20] node _T_3931 = eq(UInt<5>(0h15), remapindex_20) when _T_3931 : connect remapVecData[20], Queue10_UInt8_21.io.deq.bits connect remapVecValids[20], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[20] node _T_3932 = eq(UInt<5>(0h16), remapindex_20) when _T_3932 : connect remapVecData[20], Queue10_UInt8_22.io.deq.bits connect remapVecValids[20], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[20] node _T_3933 = eq(UInt<5>(0h17), remapindex_20) when _T_3933 : connect remapVecData[20], Queue10_UInt8_23.io.deq.bits connect remapVecValids[20], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[20] node _T_3934 = eq(UInt<5>(0h18), remapindex_20) when _T_3934 : connect remapVecData[20], Queue10_UInt8_24.io.deq.bits connect remapVecValids[20], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[20] node _T_3935 = eq(UInt<5>(0h19), remapindex_20) when _T_3935 : connect remapVecData[20], Queue10_UInt8_25.io.deq.bits connect remapVecValids[20], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[20] node _T_3936 = eq(UInt<5>(0h1a), remapindex_20) when _T_3936 : connect remapVecData[20], Queue10_UInt8_26.io.deq.bits connect remapVecValids[20], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[20] node _T_3937 = eq(UInt<5>(0h1b), remapindex_20) when _T_3937 : connect remapVecData[20], Queue10_UInt8_27.io.deq.bits connect remapVecValids[20], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[20] node _T_3938 = eq(UInt<5>(0h1c), remapindex_20) when _T_3938 : connect remapVecData[20], Queue10_UInt8_28.io.deq.bits connect remapVecValids[20], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[20] node _T_3939 = eq(UInt<5>(0h1d), remapindex_20) when _T_3939 : connect remapVecData[20], Queue10_UInt8_29.io.deq.bits connect remapVecValids[20], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[20] node _T_3940 = eq(UInt<5>(0h1e), remapindex_20) when _T_3940 : connect remapVecData[20], Queue10_UInt8_30.io.deq.bits connect remapVecValids[20], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[20] node _T_3941 = eq(UInt<5>(0h1f), remapindex_20) when _T_3941 : connect remapVecData[20], Queue10_UInt8_31.io.deq.bits connect remapVecValids[20], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[20] node _remapindex_T_21 = add(UInt<5>(0h15), read_start_index) node remapindex_21 = rem(_remapindex_T_21, UInt<6>(0h20)) node _T_3942 = eq(UInt<1>(0h0), remapindex_21) when _T_3942 : connect remapVecData[21], Queue10_UInt8.io.deq.bits connect remapVecValids[21], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[21] node _T_3943 = eq(UInt<1>(0h1), remapindex_21) when _T_3943 : connect remapVecData[21], Queue10_UInt8_1.io.deq.bits connect remapVecValids[21], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[21] node _T_3944 = eq(UInt<2>(0h2), remapindex_21) when _T_3944 : connect remapVecData[21], Queue10_UInt8_2.io.deq.bits connect remapVecValids[21], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[21] node _T_3945 = eq(UInt<2>(0h3), remapindex_21) when _T_3945 : connect remapVecData[21], Queue10_UInt8_3.io.deq.bits connect remapVecValids[21], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[21] node _T_3946 = eq(UInt<3>(0h4), remapindex_21) when _T_3946 : connect remapVecData[21], Queue10_UInt8_4.io.deq.bits connect remapVecValids[21], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[21] node _T_3947 = eq(UInt<3>(0h5), remapindex_21) when _T_3947 : connect remapVecData[21], Queue10_UInt8_5.io.deq.bits connect remapVecValids[21], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[21] node _T_3948 = eq(UInt<3>(0h6), remapindex_21) when _T_3948 : connect remapVecData[21], Queue10_UInt8_6.io.deq.bits connect remapVecValids[21], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[21] node _T_3949 = eq(UInt<3>(0h7), remapindex_21) when _T_3949 : connect remapVecData[21], Queue10_UInt8_7.io.deq.bits connect remapVecValids[21], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[21] node _T_3950 = eq(UInt<4>(0h8), remapindex_21) when _T_3950 : connect remapVecData[21], Queue10_UInt8_8.io.deq.bits connect remapVecValids[21], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[21] node _T_3951 = eq(UInt<4>(0h9), remapindex_21) when _T_3951 : connect remapVecData[21], Queue10_UInt8_9.io.deq.bits connect remapVecValids[21], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[21] node _T_3952 = eq(UInt<4>(0ha), remapindex_21) when _T_3952 : connect remapVecData[21], Queue10_UInt8_10.io.deq.bits connect remapVecValids[21], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[21] node _T_3953 = eq(UInt<4>(0hb), remapindex_21) when _T_3953 : connect remapVecData[21], Queue10_UInt8_11.io.deq.bits connect remapVecValids[21], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[21] node _T_3954 = eq(UInt<4>(0hc), remapindex_21) when _T_3954 : connect remapVecData[21], Queue10_UInt8_12.io.deq.bits connect remapVecValids[21], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[21] node _T_3955 = eq(UInt<4>(0hd), remapindex_21) when _T_3955 : connect remapVecData[21], Queue10_UInt8_13.io.deq.bits connect remapVecValids[21], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[21] node _T_3956 = eq(UInt<4>(0he), remapindex_21) when _T_3956 : connect remapVecData[21], Queue10_UInt8_14.io.deq.bits connect remapVecValids[21], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[21] node _T_3957 = eq(UInt<4>(0hf), remapindex_21) when _T_3957 : connect remapVecData[21], Queue10_UInt8_15.io.deq.bits connect remapVecValids[21], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[21] node _T_3958 = eq(UInt<5>(0h10), remapindex_21) when _T_3958 : connect remapVecData[21], Queue10_UInt8_16.io.deq.bits connect remapVecValids[21], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[21] node _T_3959 = eq(UInt<5>(0h11), remapindex_21) when _T_3959 : connect remapVecData[21], Queue10_UInt8_17.io.deq.bits connect remapVecValids[21], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[21] node _T_3960 = eq(UInt<5>(0h12), remapindex_21) when _T_3960 : connect remapVecData[21], Queue10_UInt8_18.io.deq.bits connect remapVecValids[21], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[21] node _T_3961 = eq(UInt<5>(0h13), remapindex_21) when _T_3961 : connect remapVecData[21], Queue10_UInt8_19.io.deq.bits connect remapVecValids[21], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[21] node _T_3962 = eq(UInt<5>(0h14), remapindex_21) when _T_3962 : connect remapVecData[21], Queue10_UInt8_20.io.deq.bits connect remapVecValids[21], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[21] node _T_3963 = eq(UInt<5>(0h15), remapindex_21) when _T_3963 : connect remapVecData[21], Queue10_UInt8_21.io.deq.bits connect remapVecValids[21], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[21] node _T_3964 = eq(UInt<5>(0h16), remapindex_21) when _T_3964 : connect remapVecData[21], Queue10_UInt8_22.io.deq.bits connect remapVecValids[21], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[21] node _T_3965 = eq(UInt<5>(0h17), remapindex_21) when _T_3965 : connect remapVecData[21], Queue10_UInt8_23.io.deq.bits connect remapVecValids[21], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[21] node _T_3966 = eq(UInt<5>(0h18), remapindex_21) when _T_3966 : connect remapVecData[21], Queue10_UInt8_24.io.deq.bits connect remapVecValids[21], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[21] node _T_3967 = eq(UInt<5>(0h19), remapindex_21) when _T_3967 : connect remapVecData[21], Queue10_UInt8_25.io.deq.bits connect remapVecValids[21], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[21] node _T_3968 = eq(UInt<5>(0h1a), remapindex_21) when _T_3968 : connect remapVecData[21], Queue10_UInt8_26.io.deq.bits connect remapVecValids[21], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[21] node _T_3969 = eq(UInt<5>(0h1b), remapindex_21) when _T_3969 : connect remapVecData[21], Queue10_UInt8_27.io.deq.bits connect remapVecValids[21], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[21] node _T_3970 = eq(UInt<5>(0h1c), remapindex_21) when _T_3970 : connect remapVecData[21], Queue10_UInt8_28.io.deq.bits connect remapVecValids[21], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[21] node _T_3971 = eq(UInt<5>(0h1d), remapindex_21) when _T_3971 : connect remapVecData[21], Queue10_UInt8_29.io.deq.bits connect remapVecValids[21], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[21] node _T_3972 = eq(UInt<5>(0h1e), remapindex_21) when _T_3972 : connect remapVecData[21], Queue10_UInt8_30.io.deq.bits connect remapVecValids[21], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[21] node _T_3973 = eq(UInt<5>(0h1f), remapindex_21) when _T_3973 : connect remapVecData[21], Queue10_UInt8_31.io.deq.bits connect remapVecValids[21], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[21] node _remapindex_T_22 = add(UInt<5>(0h16), read_start_index) node remapindex_22 = rem(_remapindex_T_22, UInt<6>(0h20)) node _T_3974 = eq(UInt<1>(0h0), remapindex_22) when _T_3974 : connect remapVecData[22], Queue10_UInt8.io.deq.bits connect remapVecValids[22], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[22] node _T_3975 = eq(UInt<1>(0h1), remapindex_22) when _T_3975 : connect remapVecData[22], Queue10_UInt8_1.io.deq.bits connect remapVecValids[22], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[22] node _T_3976 = eq(UInt<2>(0h2), remapindex_22) when _T_3976 : connect remapVecData[22], Queue10_UInt8_2.io.deq.bits connect remapVecValids[22], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[22] node _T_3977 = eq(UInt<2>(0h3), remapindex_22) when _T_3977 : connect remapVecData[22], Queue10_UInt8_3.io.deq.bits connect remapVecValids[22], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[22] node _T_3978 = eq(UInt<3>(0h4), remapindex_22) when _T_3978 : connect remapVecData[22], Queue10_UInt8_4.io.deq.bits connect remapVecValids[22], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[22] node _T_3979 = eq(UInt<3>(0h5), remapindex_22) when _T_3979 : connect remapVecData[22], Queue10_UInt8_5.io.deq.bits connect remapVecValids[22], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[22] node _T_3980 = eq(UInt<3>(0h6), remapindex_22) when _T_3980 : connect remapVecData[22], Queue10_UInt8_6.io.deq.bits connect remapVecValids[22], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[22] node _T_3981 = eq(UInt<3>(0h7), remapindex_22) when _T_3981 : connect remapVecData[22], Queue10_UInt8_7.io.deq.bits connect remapVecValids[22], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[22] node _T_3982 = eq(UInt<4>(0h8), remapindex_22) when _T_3982 : connect remapVecData[22], Queue10_UInt8_8.io.deq.bits connect remapVecValids[22], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[22] node _T_3983 = eq(UInt<4>(0h9), remapindex_22) when _T_3983 : connect remapVecData[22], Queue10_UInt8_9.io.deq.bits connect remapVecValids[22], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[22] node _T_3984 = eq(UInt<4>(0ha), remapindex_22) when _T_3984 : connect remapVecData[22], Queue10_UInt8_10.io.deq.bits connect remapVecValids[22], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[22] node _T_3985 = eq(UInt<4>(0hb), remapindex_22) when _T_3985 : connect remapVecData[22], Queue10_UInt8_11.io.deq.bits connect remapVecValids[22], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[22] node _T_3986 = eq(UInt<4>(0hc), remapindex_22) when _T_3986 : connect remapVecData[22], Queue10_UInt8_12.io.deq.bits connect remapVecValids[22], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[22] node _T_3987 = eq(UInt<4>(0hd), remapindex_22) when _T_3987 : connect remapVecData[22], Queue10_UInt8_13.io.deq.bits connect remapVecValids[22], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[22] node _T_3988 = eq(UInt<4>(0he), remapindex_22) when _T_3988 : connect remapVecData[22], Queue10_UInt8_14.io.deq.bits connect remapVecValids[22], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[22] node _T_3989 = eq(UInt<4>(0hf), remapindex_22) when _T_3989 : connect remapVecData[22], Queue10_UInt8_15.io.deq.bits connect remapVecValids[22], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[22] node _T_3990 = eq(UInt<5>(0h10), remapindex_22) when _T_3990 : connect remapVecData[22], Queue10_UInt8_16.io.deq.bits connect remapVecValids[22], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[22] node _T_3991 = eq(UInt<5>(0h11), remapindex_22) when _T_3991 : connect remapVecData[22], Queue10_UInt8_17.io.deq.bits connect remapVecValids[22], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[22] node _T_3992 = eq(UInt<5>(0h12), remapindex_22) when _T_3992 : connect remapVecData[22], Queue10_UInt8_18.io.deq.bits connect remapVecValids[22], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[22] node _T_3993 = eq(UInt<5>(0h13), remapindex_22) when _T_3993 : connect remapVecData[22], Queue10_UInt8_19.io.deq.bits connect remapVecValids[22], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[22] node _T_3994 = eq(UInt<5>(0h14), remapindex_22) when _T_3994 : connect remapVecData[22], Queue10_UInt8_20.io.deq.bits connect remapVecValids[22], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[22] node _T_3995 = eq(UInt<5>(0h15), remapindex_22) when _T_3995 : connect remapVecData[22], Queue10_UInt8_21.io.deq.bits connect remapVecValids[22], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[22] node _T_3996 = eq(UInt<5>(0h16), remapindex_22) when _T_3996 : connect remapVecData[22], Queue10_UInt8_22.io.deq.bits connect remapVecValids[22], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[22] node _T_3997 = eq(UInt<5>(0h17), remapindex_22) when _T_3997 : connect remapVecData[22], Queue10_UInt8_23.io.deq.bits connect remapVecValids[22], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[22] node _T_3998 = eq(UInt<5>(0h18), remapindex_22) when _T_3998 : connect remapVecData[22], Queue10_UInt8_24.io.deq.bits connect remapVecValids[22], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[22] node _T_3999 = eq(UInt<5>(0h19), remapindex_22) when _T_3999 : connect remapVecData[22], Queue10_UInt8_25.io.deq.bits connect remapVecValids[22], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[22] node _T_4000 = eq(UInt<5>(0h1a), remapindex_22) when _T_4000 : connect remapVecData[22], Queue10_UInt8_26.io.deq.bits connect remapVecValids[22], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[22] node _T_4001 = eq(UInt<5>(0h1b), remapindex_22) when _T_4001 : connect remapVecData[22], Queue10_UInt8_27.io.deq.bits connect remapVecValids[22], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[22] node _T_4002 = eq(UInt<5>(0h1c), remapindex_22) when _T_4002 : connect remapVecData[22], Queue10_UInt8_28.io.deq.bits connect remapVecValids[22], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[22] node _T_4003 = eq(UInt<5>(0h1d), remapindex_22) when _T_4003 : connect remapVecData[22], Queue10_UInt8_29.io.deq.bits connect remapVecValids[22], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[22] node _T_4004 = eq(UInt<5>(0h1e), remapindex_22) when _T_4004 : connect remapVecData[22], Queue10_UInt8_30.io.deq.bits connect remapVecValids[22], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[22] node _T_4005 = eq(UInt<5>(0h1f), remapindex_22) when _T_4005 : connect remapVecData[22], Queue10_UInt8_31.io.deq.bits connect remapVecValids[22], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[22] node _remapindex_T_23 = add(UInt<5>(0h17), read_start_index) node remapindex_23 = rem(_remapindex_T_23, UInt<6>(0h20)) node _T_4006 = eq(UInt<1>(0h0), remapindex_23) when _T_4006 : connect remapVecData[23], Queue10_UInt8.io.deq.bits connect remapVecValids[23], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[23] node _T_4007 = eq(UInt<1>(0h1), remapindex_23) when _T_4007 : connect remapVecData[23], Queue10_UInt8_1.io.deq.bits connect remapVecValids[23], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[23] node _T_4008 = eq(UInt<2>(0h2), remapindex_23) when _T_4008 : connect remapVecData[23], Queue10_UInt8_2.io.deq.bits connect remapVecValids[23], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[23] node _T_4009 = eq(UInt<2>(0h3), remapindex_23) when _T_4009 : connect remapVecData[23], Queue10_UInt8_3.io.deq.bits connect remapVecValids[23], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[23] node _T_4010 = eq(UInt<3>(0h4), remapindex_23) when _T_4010 : connect remapVecData[23], Queue10_UInt8_4.io.deq.bits connect remapVecValids[23], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[23] node _T_4011 = eq(UInt<3>(0h5), remapindex_23) when _T_4011 : connect remapVecData[23], Queue10_UInt8_5.io.deq.bits connect remapVecValids[23], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[23] node _T_4012 = eq(UInt<3>(0h6), remapindex_23) when _T_4012 : connect remapVecData[23], Queue10_UInt8_6.io.deq.bits connect remapVecValids[23], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[23] node _T_4013 = eq(UInt<3>(0h7), remapindex_23) when _T_4013 : connect remapVecData[23], Queue10_UInt8_7.io.deq.bits connect remapVecValids[23], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[23] node _T_4014 = eq(UInt<4>(0h8), remapindex_23) when _T_4014 : connect remapVecData[23], Queue10_UInt8_8.io.deq.bits connect remapVecValids[23], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[23] node _T_4015 = eq(UInt<4>(0h9), remapindex_23) when _T_4015 : connect remapVecData[23], Queue10_UInt8_9.io.deq.bits connect remapVecValids[23], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[23] node _T_4016 = eq(UInt<4>(0ha), remapindex_23) when _T_4016 : connect remapVecData[23], Queue10_UInt8_10.io.deq.bits connect remapVecValids[23], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[23] node _T_4017 = eq(UInt<4>(0hb), remapindex_23) when _T_4017 : connect remapVecData[23], Queue10_UInt8_11.io.deq.bits connect remapVecValids[23], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[23] node _T_4018 = eq(UInt<4>(0hc), remapindex_23) when _T_4018 : connect remapVecData[23], Queue10_UInt8_12.io.deq.bits connect remapVecValids[23], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[23] node _T_4019 = eq(UInt<4>(0hd), remapindex_23) when _T_4019 : connect remapVecData[23], Queue10_UInt8_13.io.deq.bits connect remapVecValids[23], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[23] node _T_4020 = eq(UInt<4>(0he), remapindex_23) when _T_4020 : connect remapVecData[23], Queue10_UInt8_14.io.deq.bits connect remapVecValids[23], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[23] node _T_4021 = eq(UInt<4>(0hf), remapindex_23) when _T_4021 : connect remapVecData[23], Queue10_UInt8_15.io.deq.bits connect remapVecValids[23], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[23] node _T_4022 = eq(UInt<5>(0h10), remapindex_23) when _T_4022 : connect remapVecData[23], Queue10_UInt8_16.io.deq.bits connect remapVecValids[23], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[23] node _T_4023 = eq(UInt<5>(0h11), remapindex_23) when _T_4023 : connect remapVecData[23], Queue10_UInt8_17.io.deq.bits connect remapVecValids[23], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[23] node _T_4024 = eq(UInt<5>(0h12), remapindex_23) when _T_4024 : connect remapVecData[23], Queue10_UInt8_18.io.deq.bits connect remapVecValids[23], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[23] node _T_4025 = eq(UInt<5>(0h13), remapindex_23) when _T_4025 : connect remapVecData[23], Queue10_UInt8_19.io.deq.bits connect remapVecValids[23], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[23] node _T_4026 = eq(UInt<5>(0h14), remapindex_23) when _T_4026 : connect remapVecData[23], Queue10_UInt8_20.io.deq.bits connect remapVecValids[23], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[23] node _T_4027 = eq(UInt<5>(0h15), remapindex_23) when _T_4027 : connect remapVecData[23], Queue10_UInt8_21.io.deq.bits connect remapVecValids[23], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[23] node _T_4028 = eq(UInt<5>(0h16), remapindex_23) when _T_4028 : connect remapVecData[23], Queue10_UInt8_22.io.deq.bits connect remapVecValids[23], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[23] node _T_4029 = eq(UInt<5>(0h17), remapindex_23) when _T_4029 : connect remapVecData[23], Queue10_UInt8_23.io.deq.bits connect remapVecValids[23], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[23] node _T_4030 = eq(UInt<5>(0h18), remapindex_23) when _T_4030 : connect remapVecData[23], Queue10_UInt8_24.io.deq.bits connect remapVecValids[23], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[23] node _T_4031 = eq(UInt<5>(0h19), remapindex_23) when _T_4031 : connect remapVecData[23], Queue10_UInt8_25.io.deq.bits connect remapVecValids[23], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[23] node _T_4032 = eq(UInt<5>(0h1a), remapindex_23) when _T_4032 : connect remapVecData[23], Queue10_UInt8_26.io.deq.bits connect remapVecValids[23], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[23] node _T_4033 = eq(UInt<5>(0h1b), remapindex_23) when _T_4033 : connect remapVecData[23], Queue10_UInt8_27.io.deq.bits connect remapVecValids[23], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[23] node _T_4034 = eq(UInt<5>(0h1c), remapindex_23) when _T_4034 : connect remapVecData[23], Queue10_UInt8_28.io.deq.bits connect remapVecValids[23], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[23] node _T_4035 = eq(UInt<5>(0h1d), remapindex_23) when _T_4035 : connect remapVecData[23], Queue10_UInt8_29.io.deq.bits connect remapVecValids[23], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[23] node _T_4036 = eq(UInt<5>(0h1e), remapindex_23) when _T_4036 : connect remapVecData[23], Queue10_UInt8_30.io.deq.bits connect remapVecValids[23], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[23] node _T_4037 = eq(UInt<5>(0h1f), remapindex_23) when _T_4037 : connect remapVecData[23], Queue10_UInt8_31.io.deq.bits connect remapVecValids[23], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[23] node _remapindex_T_24 = add(UInt<5>(0h18), read_start_index) node remapindex_24 = rem(_remapindex_T_24, UInt<6>(0h20)) node _T_4038 = eq(UInt<1>(0h0), remapindex_24) when _T_4038 : connect remapVecData[24], Queue10_UInt8.io.deq.bits connect remapVecValids[24], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[24] node _T_4039 = eq(UInt<1>(0h1), remapindex_24) when _T_4039 : connect remapVecData[24], Queue10_UInt8_1.io.deq.bits connect remapVecValids[24], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[24] node _T_4040 = eq(UInt<2>(0h2), remapindex_24) when _T_4040 : connect remapVecData[24], Queue10_UInt8_2.io.deq.bits connect remapVecValids[24], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[24] node _T_4041 = eq(UInt<2>(0h3), remapindex_24) when _T_4041 : connect remapVecData[24], Queue10_UInt8_3.io.deq.bits connect remapVecValids[24], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[24] node _T_4042 = eq(UInt<3>(0h4), remapindex_24) when _T_4042 : connect remapVecData[24], Queue10_UInt8_4.io.deq.bits connect remapVecValids[24], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[24] node _T_4043 = eq(UInt<3>(0h5), remapindex_24) when _T_4043 : connect remapVecData[24], Queue10_UInt8_5.io.deq.bits connect remapVecValids[24], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[24] node _T_4044 = eq(UInt<3>(0h6), remapindex_24) when _T_4044 : connect remapVecData[24], Queue10_UInt8_6.io.deq.bits connect remapVecValids[24], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[24] node _T_4045 = eq(UInt<3>(0h7), remapindex_24) when _T_4045 : connect remapVecData[24], Queue10_UInt8_7.io.deq.bits connect remapVecValids[24], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[24] node _T_4046 = eq(UInt<4>(0h8), remapindex_24) when _T_4046 : connect remapVecData[24], Queue10_UInt8_8.io.deq.bits connect remapVecValids[24], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[24] node _T_4047 = eq(UInt<4>(0h9), remapindex_24) when _T_4047 : connect remapVecData[24], Queue10_UInt8_9.io.deq.bits connect remapVecValids[24], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[24] node _T_4048 = eq(UInt<4>(0ha), remapindex_24) when _T_4048 : connect remapVecData[24], Queue10_UInt8_10.io.deq.bits connect remapVecValids[24], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[24] node _T_4049 = eq(UInt<4>(0hb), remapindex_24) when _T_4049 : connect remapVecData[24], Queue10_UInt8_11.io.deq.bits connect remapVecValids[24], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[24] node _T_4050 = eq(UInt<4>(0hc), remapindex_24) when _T_4050 : connect remapVecData[24], Queue10_UInt8_12.io.deq.bits connect remapVecValids[24], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[24] node _T_4051 = eq(UInt<4>(0hd), remapindex_24) when _T_4051 : connect remapVecData[24], Queue10_UInt8_13.io.deq.bits connect remapVecValids[24], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[24] node _T_4052 = eq(UInt<4>(0he), remapindex_24) when _T_4052 : connect remapVecData[24], Queue10_UInt8_14.io.deq.bits connect remapVecValids[24], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[24] node _T_4053 = eq(UInt<4>(0hf), remapindex_24) when _T_4053 : connect remapVecData[24], Queue10_UInt8_15.io.deq.bits connect remapVecValids[24], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[24] node _T_4054 = eq(UInt<5>(0h10), remapindex_24) when _T_4054 : connect remapVecData[24], Queue10_UInt8_16.io.deq.bits connect remapVecValids[24], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[24] node _T_4055 = eq(UInt<5>(0h11), remapindex_24) when _T_4055 : connect remapVecData[24], Queue10_UInt8_17.io.deq.bits connect remapVecValids[24], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[24] node _T_4056 = eq(UInt<5>(0h12), remapindex_24) when _T_4056 : connect remapVecData[24], Queue10_UInt8_18.io.deq.bits connect remapVecValids[24], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[24] node _T_4057 = eq(UInt<5>(0h13), remapindex_24) when _T_4057 : connect remapVecData[24], Queue10_UInt8_19.io.deq.bits connect remapVecValids[24], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[24] node _T_4058 = eq(UInt<5>(0h14), remapindex_24) when _T_4058 : connect remapVecData[24], Queue10_UInt8_20.io.deq.bits connect remapVecValids[24], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[24] node _T_4059 = eq(UInt<5>(0h15), remapindex_24) when _T_4059 : connect remapVecData[24], Queue10_UInt8_21.io.deq.bits connect remapVecValids[24], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[24] node _T_4060 = eq(UInt<5>(0h16), remapindex_24) when _T_4060 : connect remapVecData[24], Queue10_UInt8_22.io.deq.bits connect remapVecValids[24], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[24] node _T_4061 = eq(UInt<5>(0h17), remapindex_24) when _T_4061 : connect remapVecData[24], Queue10_UInt8_23.io.deq.bits connect remapVecValids[24], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[24] node _T_4062 = eq(UInt<5>(0h18), remapindex_24) when _T_4062 : connect remapVecData[24], Queue10_UInt8_24.io.deq.bits connect remapVecValids[24], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[24] node _T_4063 = eq(UInt<5>(0h19), remapindex_24) when _T_4063 : connect remapVecData[24], Queue10_UInt8_25.io.deq.bits connect remapVecValids[24], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[24] node _T_4064 = eq(UInt<5>(0h1a), remapindex_24) when _T_4064 : connect remapVecData[24], Queue10_UInt8_26.io.deq.bits connect remapVecValids[24], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[24] node _T_4065 = eq(UInt<5>(0h1b), remapindex_24) when _T_4065 : connect remapVecData[24], Queue10_UInt8_27.io.deq.bits connect remapVecValids[24], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[24] node _T_4066 = eq(UInt<5>(0h1c), remapindex_24) when _T_4066 : connect remapVecData[24], Queue10_UInt8_28.io.deq.bits connect remapVecValids[24], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[24] node _T_4067 = eq(UInt<5>(0h1d), remapindex_24) when _T_4067 : connect remapVecData[24], Queue10_UInt8_29.io.deq.bits connect remapVecValids[24], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[24] node _T_4068 = eq(UInt<5>(0h1e), remapindex_24) when _T_4068 : connect remapVecData[24], Queue10_UInt8_30.io.deq.bits connect remapVecValids[24], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[24] node _T_4069 = eq(UInt<5>(0h1f), remapindex_24) when _T_4069 : connect remapVecData[24], Queue10_UInt8_31.io.deq.bits connect remapVecValids[24], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[24] node _remapindex_T_25 = add(UInt<5>(0h19), read_start_index) node remapindex_25 = rem(_remapindex_T_25, UInt<6>(0h20)) node _T_4070 = eq(UInt<1>(0h0), remapindex_25) when _T_4070 : connect remapVecData[25], Queue10_UInt8.io.deq.bits connect remapVecValids[25], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[25] node _T_4071 = eq(UInt<1>(0h1), remapindex_25) when _T_4071 : connect remapVecData[25], Queue10_UInt8_1.io.deq.bits connect remapVecValids[25], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[25] node _T_4072 = eq(UInt<2>(0h2), remapindex_25) when _T_4072 : connect remapVecData[25], Queue10_UInt8_2.io.deq.bits connect remapVecValids[25], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[25] node _T_4073 = eq(UInt<2>(0h3), remapindex_25) when _T_4073 : connect remapVecData[25], Queue10_UInt8_3.io.deq.bits connect remapVecValids[25], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[25] node _T_4074 = eq(UInt<3>(0h4), remapindex_25) when _T_4074 : connect remapVecData[25], Queue10_UInt8_4.io.deq.bits connect remapVecValids[25], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[25] node _T_4075 = eq(UInt<3>(0h5), remapindex_25) when _T_4075 : connect remapVecData[25], Queue10_UInt8_5.io.deq.bits connect remapVecValids[25], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[25] node _T_4076 = eq(UInt<3>(0h6), remapindex_25) when _T_4076 : connect remapVecData[25], Queue10_UInt8_6.io.deq.bits connect remapVecValids[25], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[25] node _T_4077 = eq(UInt<3>(0h7), remapindex_25) when _T_4077 : connect remapVecData[25], Queue10_UInt8_7.io.deq.bits connect remapVecValids[25], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[25] node _T_4078 = eq(UInt<4>(0h8), remapindex_25) when _T_4078 : connect remapVecData[25], Queue10_UInt8_8.io.deq.bits connect remapVecValids[25], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[25] node _T_4079 = eq(UInt<4>(0h9), remapindex_25) when _T_4079 : connect remapVecData[25], Queue10_UInt8_9.io.deq.bits connect remapVecValids[25], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[25] node _T_4080 = eq(UInt<4>(0ha), remapindex_25) when _T_4080 : connect remapVecData[25], Queue10_UInt8_10.io.deq.bits connect remapVecValids[25], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[25] node _T_4081 = eq(UInt<4>(0hb), remapindex_25) when _T_4081 : connect remapVecData[25], Queue10_UInt8_11.io.deq.bits connect remapVecValids[25], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[25] node _T_4082 = eq(UInt<4>(0hc), remapindex_25) when _T_4082 : connect remapVecData[25], Queue10_UInt8_12.io.deq.bits connect remapVecValids[25], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[25] node _T_4083 = eq(UInt<4>(0hd), remapindex_25) when _T_4083 : connect remapVecData[25], Queue10_UInt8_13.io.deq.bits connect remapVecValids[25], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[25] node _T_4084 = eq(UInt<4>(0he), remapindex_25) when _T_4084 : connect remapVecData[25], Queue10_UInt8_14.io.deq.bits connect remapVecValids[25], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[25] node _T_4085 = eq(UInt<4>(0hf), remapindex_25) when _T_4085 : connect remapVecData[25], Queue10_UInt8_15.io.deq.bits connect remapVecValids[25], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[25] node _T_4086 = eq(UInt<5>(0h10), remapindex_25) when _T_4086 : connect remapVecData[25], Queue10_UInt8_16.io.deq.bits connect remapVecValids[25], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[25] node _T_4087 = eq(UInt<5>(0h11), remapindex_25) when _T_4087 : connect remapVecData[25], Queue10_UInt8_17.io.deq.bits connect remapVecValids[25], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[25] node _T_4088 = eq(UInt<5>(0h12), remapindex_25) when _T_4088 : connect remapVecData[25], Queue10_UInt8_18.io.deq.bits connect remapVecValids[25], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[25] node _T_4089 = eq(UInt<5>(0h13), remapindex_25) when _T_4089 : connect remapVecData[25], Queue10_UInt8_19.io.deq.bits connect remapVecValids[25], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[25] node _T_4090 = eq(UInt<5>(0h14), remapindex_25) when _T_4090 : connect remapVecData[25], Queue10_UInt8_20.io.deq.bits connect remapVecValids[25], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[25] node _T_4091 = eq(UInt<5>(0h15), remapindex_25) when _T_4091 : connect remapVecData[25], Queue10_UInt8_21.io.deq.bits connect remapVecValids[25], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[25] node _T_4092 = eq(UInt<5>(0h16), remapindex_25) when _T_4092 : connect remapVecData[25], Queue10_UInt8_22.io.deq.bits connect remapVecValids[25], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[25] node _T_4093 = eq(UInt<5>(0h17), remapindex_25) when _T_4093 : connect remapVecData[25], Queue10_UInt8_23.io.deq.bits connect remapVecValids[25], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[25] node _T_4094 = eq(UInt<5>(0h18), remapindex_25) when _T_4094 : connect remapVecData[25], Queue10_UInt8_24.io.deq.bits connect remapVecValids[25], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[25] node _T_4095 = eq(UInt<5>(0h19), remapindex_25) when _T_4095 : connect remapVecData[25], Queue10_UInt8_25.io.deq.bits connect remapVecValids[25], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[25] node _T_4096 = eq(UInt<5>(0h1a), remapindex_25) when _T_4096 : connect remapVecData[25], Queue10_UInt8_26.io.deq.bits connect remapVecValids[25], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[25] node _T_4097 = eq(UInt<5>(0h1b), remapindex_25) when _T_4097 : connect remapVecData[25], Queue10_UInt8_27.io.deq.bits connect remapVecValids[25], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[25] node _T_4098 = eq(UInt<5>(0h1c), remapindex_25) when _T_4098 : connect remapVecData[25], Queue10_UInt8_28.io.deq.bits connect remapVecValids[25], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[25] node _T_4099 = eq(UInt<5>(0h1d), remapindex_25) when _T_4099 : connect remapVecData[25], Queue10_UInt8_29.io.deq.bits connect remapVecValids[25], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[25] node _T_4100 = eq(UInt<5>(0h1e), remapindex_25) when _T_4100 : connect remapVecData[25], Queue10_UInt8_30.io.deq.bits connect remapVecValids[25], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[25] node _T_4101 = eq(UInt<5>(0h1f), remapindex_25) when _T_4101 : connect remapVecData[25], Queue10_UInt8_31.io.deq.bits connect remapVecValids[25], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[25] node _remapindex_T_26 = add(UInt<5>(0h1a), read_start_index) node remapindex_26 = rem(_remapindex_T_26, UInt<6>(0h20)) node _T_4102 = eq(UInt<1>(0h0), remapindex_26) when _T_4102 : connect remapVecData[26], Queue10_UInt8.io.deq.bits connect remapVecValids[26], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[26] node _T_4103 = eq(UInt<1>(0h1), remapindex_26) when _T_4103 : connect remapVecData[26], Queue10_UInt8_1.io.deq.bits connect remapVecValids[26], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[26] node _T_4104 = eq(UInt<2>(0h2), remapindex_26) when _T_4104 : connect remapVecData[26], Queue10_UInt8_2.io.deq.bits connect remapVecValids[26], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[26] node _T_4105 = eq(UInt<2>(0h3), remapindex_26) when _T_4105 : connect remapVecData[26], Queue10_UInt8_3.io.deq.bits connect remapVecValids[26], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[26] node _T_4106 = eq(UInt<3>(0h4), remapindex_26) when _T_4106 : connect remapVecData[26], Queue10_UInt8_4.io.deq.bits connect remapVecValids[26], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[26] node _T_4107 = eq(UInt<3>(0h5), remapindex_26) when _T_4107 : connect remapVecData[26], Queue10_UInt8_5.io.deq.bits connect remapVecValids[26], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[26] node _T_4108 = eq(UInt<3>(0h6), remapindex_26) when _T_4108 : connect remapVecData[26], Queue10_UInt8_6.io.deq.bits connect remapVecValids[26], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[26] node _T_4109 = eq(UInt<3>(0h7), remapindex_26) when _T_4109 : connect remapVecData[26], Queue10_UInt8_7.io.deq.bits connect remapVecValids[26], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[26] node _T_4110 = eq(UInt<4>(0h8), remapindex_26) when _T_4110 : connect remapVecData[26], Queue10_UInt8_8.io.deq.bits connect remapVecValids[26], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[26] node _T_4111 = eq(UInt<4>(0h9), remapindex_26) when _T_4111 : connect remapVecData[26], Queue10_UInt8_9.io.deq.bits connect remapVecValids[26], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[26] node _T_4112 = eq(UInt<4>(0ha), remapindex_26) when _T_4112 : connect remapVecData[26], Queue10_UInt8_10.io.deq.bits connect remapVecValids[26], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[26] node _T_4113 = eq(UInt<4>(0hb), remapindex_26) when _T_4113 : connect remapVecData[26], Queue10_UInt8_11.io.deq.bits connect remapVecValids[26], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[26] node _T_4114 = eq(UInt<4>(0hc), remapindex_26) when _T_4114 : connect remapVecData[26], Queue10_UInt8_12.io.deq.bits connect remapVecValids[26], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[26] node _T_4115 = eq(UInt<4>(0hd), remapindex_26) when _T_4115 : connect remapVecData[26], Queue10_UInt8_13.io.deq.bits connect remapVecValids[26], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[26] node _T_4116 = eq(UInt<4>(0he), remapindex_26) when _T_4116 : connect remapVecData[26], Queue10_UInt8_14.io.deq.bits connect remapVecValids[26], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[26] node _T_4117 = eq(UInt<4>(0hf), remapindex_26) when _T_4117 : connect remapVecData[26], Queue10_UInt8_15.io.deq.bits connect remapVecValids[26], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[26] node _T_4118 = eq(UInt<5>(0h10), remapindex_26) when _T_4118 : connect remapVecData[26], Queue10_UInt8_16.io.deq.bits connect remapVecValids[26], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[26] node _T_4119 = eq(UInt<5>(0h11), remapindex_26) when _T_4119 : connect remapVecData[26], Queue10_UInt8_17.io.deq.bits connect remapVecValids[26], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[26] node _T_4120 = eq(UInt<5>(0h12), remapindex_26) when _T_4120 : connect remapVecData[26], Queue10_UInt8_18.io.deq.bits connect remapVecValids[26], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[26] node _T_4121 = eq(UInt<5>(0h13), remapindex_26) when _T_4121 : connect remapVecData[26], Queue10_UInt8_19.io.deq.bits connect remapVecValids[26], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[26] node _T_4122 = eq(UInt<5>(0h14), remapindex_26) when _T_4122 : connect remapVecData[26], Queue10_UInt8_20.io.deq.bits connect remapVecValids[26], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[26] node _T_4123 = eq(UInt<5>(0h15), remapindex_26) when _T_4123 : connect remapVecData[26], Queue10_UInt8_21.io.deq.bits connect remapVecValids[26], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[26] node _T_4124 = eq(UInt<5>(0h16), remapindex_26) when _T_4124 : connect remapVecData[26], Queue10_UInt8_22.io.deq.bits connect remapVecValids[26], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[26] node _T_4125 = eq(UInt<5>(0h17), remapindex_26) when _T_4125 : connect remapVecData[26], Queue10_UInt8_23.io.deq.bits connect remapVecValids[26], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[26] node _T_4126 = eq(UInt<5>(0h18), remapindex_26) when _T_4126 : connect remapVecData[26], Queue10_UInt8_24.io.deq.bits connect remapVecValids[26], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[26] node _T_4127 = eq(UInt<5>(0h19), remapindex_26) when _T_4127 : connect remapVecData[26], Queue10_UInt8_25.io.deq.bits connect remapVecValids[26], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[26] node _T_4128 = eq(UInt<5>(0h1a), remapindex_26) when _T_4128 : connect remapVecData[26], Queue10_UInt8_26.io.deq.bits connect remapVecValids[26], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[26] node _T_4129 = eq(UInt<5>(0h1b), remapindex_26) when _T_4129 : connect remapVecData[26], Queue10_UInt8_27.io.deq.bits connect remapVecValids[26], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[26] node _T_4130 = eq(UInt<5>(0h1c), remapindex_26) when _T_4130 : connect remapVecData[26], Queue10_UInt8_28.io.deq.bits connect remapVecValids[26], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[26] node _T_4131 = eq(UInt<5>(0h1d), remapindex_26) when _T_4131 : connect remapVecData[26], Queue10_UInt8_29.io.deq.bits connect remapVecValids[26], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[26] node _T_4132 = eq(UInt<5>(0h1e), remapindex_26) when _T_4132 : connect remapVecData[26], Queue10_UInt8_30.io.deq.bits connect remapVecValids[26], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[26] node _T_4133 = eq(UInt<5>(0h1f), remapindex_26) when _T_4133 : connect remapVecData[26], Queue10_UInt8_31.io.deq.bits connect remapVecValids[26], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[26] node _remapindex_T_27 = add(UInt<5>(0h1b), read_start_index) node remapindex_27 = rem(_remapindex_T_27, UInt<6>(0h20)) node _T_4134 = eq(UInt<1>(0h0), remapindex_27) when _T_4134 : connect remapVecData[27], Queue10_UInt8.io.deq.bits connect remapVecValids[27], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[27] node _T_4135 = eq(UInt<1>(0h1), remapindex_27) when _T_4135 : connect remapVecData[27], Queue10_UInt8_1.io.deq.bits connect remapVecValids[27], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[27] node _T_4136 = eq(UInt<2>(0h2), remapindex_27) when _T_4136 : connect remapVecData[27], Queue10_UInt8_2.io.deq.bits connect remapVecValids[27], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[27] node _T_4137 = eq(UInt<2>(0h3), remapindex_27) when _T_4137 : connect remapVecData[27], Queue10_UInt8_3.io.deq.bits connect remapVecValids[27], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[27] node _T_4138 = eq(UInt<3>(0h4), remapindex_27) when _T_4138 : connect remapVecData[27], Queue10_UInt8_4.io.deq.bits connect remapVecValids[27], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[27] node _T_4139 = eq(UInt<3>(0h5), remapindex_27) when _T_4139 : connect remapVecData[27], Queue10_UInt8_5.io.deq.bits connect remapVecValids[27], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[27] node _T_4140 = eq(UInt<3>(0h6), remapindex_27) when _T_4140 : connect remapVecData[27], Queue10_UInt8_6.io.deq.bits connect remapVecValids[27], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[27] node _T_4141 = eq(UInt<3>(0h7), remapindex_27) when _T_4141 : connect remapVecData[27], Queue10_UInt8_7.io.deq.bits connect remapVecValids[27], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[27] node _T_4142 = eq(UInt<4>(0h8), remapindex_27) when _T_4142 : connect remapVecData[27], Queue10_UInt8_8.io.deq.bits connect remapVecValids[27], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[27] node _T_4143 = eq(UInt<4>(0h9), remapindex_27) when _T_4143 : connect remapVecData[27], Queue10_UInt8_9.io.deq.bits connect remapVecValids[27], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[27] node _T_4144 = eq(UInt<4>(0ha), remapindex_27) when _T_4144 : connect remapVecData[27], Queue10_UInt8_10.io.deq.bits connect remapVecValids[27], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[27] node _T_4145 = eq(UInt<4>(0hb), remapindex_27) when _T_4145 : connect remapVecData[27], Queue10_UInt8_11.io.deq.bits connect remapVecValids[27], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[27] node _T_4146 = eq(UInt<4>(0hc), remapindex_27) when _T_4146 : connect remapVecData[27], Queue10_UInt8_12.io.deq.bits connect remapVecValids[27], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[27] node _T_4147 = eq(UInt<4>(0hd), remapindex_27) when _T_4147 : connect remapVecData[27], Queue10_UInt8_13.io.deq.bits connect remapVecValids[27], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[27] node _T_4148 = eq(UInt<4>(0he), remapindex_27) when _T_4148 : connect remapVecData[27], Queue10_UInt8_14.io.deq.bits connect remapVecValids[27], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[27] node _T_4149 = eq(UInt<4>(0hf), remapindex_27) when _T_4149 : connect remapVecData[27], Queue10_UInt8_15.io.deq.bits connect remapVecValids[27], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[27] node _T_4150 = eq(UInt<5>(0h10), remapindex_27) when _T_4150 : connect remapVecData[27], Queue10_UInt8_16.io.deq.bits connect remapVecValids[27], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[27] node _T_4151 = eq(UInt<5>(0h11), remapindex_27) when _T_4151 : connect remapVecData[27], Queue10_UInt8_17.io.deq.bits connect remapVecValids[27], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[27] node _T_4152 = eq(UInt<5>(0h12), remapindex_27) when _T_4152 : connect remapVecData[27], Queue10_UInt8_18.io.deq.bits connect remapVecValids[27], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[27] node _T_4153 = eq(UInt<5>(0h13), remapindex_27) when _T_4153 : connect remapVecData[27], Queue10_UInt8_19.io.deq.bits connect remapVecValids[27], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[27] node _T_4154 = eq(UInt<5>(0h14), remapindex_27) when _T_4154 : connect remapVecData[27], Queue10_UInt8_20.io.deq.bits connect remapVecValids[27], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[27] node _T_4155 = eq(UInt<5>(0h15), remapindex_27) when _T_4155 : connect remapVecData[27], Queue10_UInt8_21.io.deq.bits connect remapVecValids[27], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[27] node _T_4156 = eq(UInt<5>(0h16), remapindex_27) when _T_4156 : connect remapVecData[27], Queue10_UInt8_22.io.deq.bits connect remapVecValids[27], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[27] node _T_4157 = eq(UInt<5>(0h17), remapindex_27) when _T_4157 : connect remapVecData[27], Queue10_UInt8_23.io.deq.bits connect remapVecValids[27], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[27] node _T_4158 = eq(UInt<5>(0h18), remapindex_27) when _T_4158 : connect remapVecData[27], Queue10_UInt8_24.io.deq.bits connect remapVecValids[27], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[27] node _T_4159 = eq(UInt<5>(0h19), remapindex_27) when _T_4159 : connect remapVecData[27], Queue10_UInt8_25.io.deq.bits connect remapVecValids[27], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[27] node _T_4160 = eq(UInt<5>(0h1a), remapindex_27) when _T_4160 : connect remapVecData[27], Queue10_UInt8_26.io.deq.bits connect remapVecValids[27], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[27] node _T_4161 = eq(UInt<5>(0h1b), remapindex_27) when _T_4161 : connect remapVecData[27], Queue10_UInt8_27.io.deq.bits connect remapVecValids[27], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[27] node _T_4162 = eq(UInt<5>(0h1c), remapindex_27) when _T_4162 : connect remapVecData[27], Queue10_UInt8_28.io.deq.bits connect remapVecValids[27], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[27] node _T_4163 = eq(UInt<5>(0h1d), remapindex_27) when _T_4163 : connect remapVecData[27], Queue10_UInt8_29.io.deq.bits connect remapVecValids[27], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[27] node _T_4164 = eq(UInt<5>(0h1e), remapindex_27) when _T_4164 : connect remapVecData[27], Queue10_UInt8_30.io.deq.bits connect remapVecValids[27], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[27] node _T_4165 = eq(UInt<5>(0h1f), remapindex_27) when _T_4165 : connect remapVecData[27], Queue10_UInt8_31.io.deq.bits connect remapVecValids[27], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[27] node _remapindex_T_28 = add(UInt<5>(0h1c), read_start_index) node remapindex_28 = rem(_remapindex_T_28, UInt<6>(0h20)) node _T_4166 = eq(UInt<1>(0h0), remapindex_28) when _T_4166 : connect remapVecData[28], Queue10_UInt8.io.deq.bits connect remapVecValids[28], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[28] node _T_4167 = eq(UInt<1>(0h1), remapindex_28) when _T_4167 : connect remapVecData[28], Queue10_UInt8_1.io.deq.bits connect remapVecValids[28], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[28] node _T_4168 = eq(UInt<2>(0h2), remapindex_28) when _T_4168 : connect remapVecData[28], Queue10_UInt8_2.io.deq.bits connect remapVecValids[28], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[28] node _T_4169 = eq(UInt<2>(0h3), remapindex_28) when _T_4169 : connect remapVecData[28], Queue10_UInt8_3.io.deq.bits connect remapVecValids[28], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[28] node _T_4170 = eq(UInt<3>(0h4), remapindex_28) when _T_4170 : connect remapVecData[28], Queue10_UInt8_4.io.deq.bits connect remapVecValids[28], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[28] node _T_4171 = eq(UInt<3>(0h5), remapindex_28) when _T_4171 : connect remapVecData[28], Queue10_UInt8_5.io.deq.bits connect remapVecValids[28], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[28] node _T_4172 = eq(UInt<3>(0h6), remapindex_28) when _T_4172 : connect remapVecData[28], Queue10_UInt8_6.io.deq.bits connect remapVecValids[28], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[28] node _T_4173 = eq(UInt<3>(0h7), remapindex_28) when _T_4173 : connect remapVecData[28], Queue10_UInt8_7.io.deq.bits connect remapVecValids[28], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[28] node _T_4174 = eq(UInt<4>(0h8), remapindex_28) when _T_4174 : connect remapVecData[28], Queue10_UInt8_8.io.deq.bits connect remapVecValids[28], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[28] node _T_4175 = eq(UInt<4>(0h9), remapindex_28) when _T_4175 : connect remapVecData[28], Queue10_UInt8_9.io.deq.bits connect remapVecValids[28], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[28] node _T_4176 = eq(UInt<4>(0ha), remapindex_28) when _T_4176 : connect remapVecData[28], Queue10_UInt8_10.io.deq.bits connect remapVecValids[28], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[28] node _T_4177 = eq(UInt<4>(0hb), remapindex_28) when _T_4177 : connect remapVecData[28], Queue10_UInt8_11.io.deq.bits connect remapVecValids[28], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[28] node _T_4178 = eq(UInt<4>(0hc), remapindex_28) when _T_4178 : connect remapVecData[28], Queue10_UInt8_12.io.deq.bits connect remapVecValids[28], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[28] node _T_4179 = eq(UInt<4>(0hd), remapindex_28) when _T_4179 : connect remapVecData[28], Queue10_UInt8_13.io.deq.bits connect remapVecValids[28], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[28] node _T_4180 = eq(UInt<4>(0he), remapindex_28) when _T_4180 : connect remapVecData[28], Queue10_UInt8_14.io.deq.bits connect remapVecValids[28], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[28] node _T_4181 = eq(UInt<4>(0hf), remapindex_28) when _T_4181 : connect remapVecData[28], Queue10_UInt8_15.io.deq.bits connect remapVecValids[28], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[28] node _T_4182 = eq(UInt<5>(0h10), remapindex_28) when _T_4182 : connect remapVecData[28], Queue10_UInt8_16.io.deq.bits connect remapVecValids[28], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[28] node _T_4183 = eq(UInt<5>(0h11), remapindex_28) when _T_4183 : connect remapVecData[28], Queue10_UInt8_17.io.deq.bits connect remapVecValids[28], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[28] node _T_4184 = eq(UInt<5>(0h12), remapindex_28) when _T_4184 : connect remapVecData[28], Queue10_UInt8_18.io.deq.bits connect remapVecValids[28], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[28] node _T_4185 = eq(UInt<5>(0h13), remapindex_28) when _T_4185 : connect remapVecData[28], Queue10_UInt8_19.io.deq.bits connect remapVecValids[28], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[28] node _T_4186 = eq(UInt<5>(0h14), remapindex_28) when _T_4186 : connect remapVecData[28], Queue10_UInt8_20.io.deq.bits connect remapVecValids[28], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[28] node _T_4187 = eq(UInt<5>(0h15), remapindex_28) when _T_4187 : connect remapVecData[28], Queue10_UInt8_21.io.deq.bits connect remapVecValids[28], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[28] node _T_4188 = eq(UInt<5>(0h16), remapindex_28) when _T_4188 : connect remapVecData[28], Queue10_UInt8_22.io.deq.bits connect remapVecValids[28], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[28] node _T_4189 = eq(UInt<5>(0h17), remapindex_28) when _T_4189 : connect remapVecData[28], Queue10_UInt8_23.io.deq.bits connect remapVecValids[28], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[28] node _T_4190 = eq(UInt<5>(0h18), remapindex_28) when _T_4190 : connect remapVecData[28], Queue10_UInt8_24.io.deq.bits connect remapVecValids[28], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[28] node _T_4191 = eq(UInt<5>(0h19), remapindex_28) when _T_4191 : connect remapVecData[28], Queue10_UInt8_25.io.deq.bits connect remapVecValids[28], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[28] node _T_4192 = eq(UInt<5>(0h1a), remapindex_28) when _T_4192 : connect remapVecData[28], Queue10_UInt8_26.io.deq.bits connect remapVecValids[28], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[28] node _T_4193 = eq(UInt<5>(0h1b), remapindex_28) when _T_4193 : connect remapVecData[28], Queue10_UInt8_27.io.deq.bits connect remapVecValids[28], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[28] node _T_4194 = eq(UInt<5>(0h1c), remapindex_28) when _T_4194 : connect remapVecData[28], Queue10_UInt8_28.io.deq.bits connect remapVecValids[28], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[28] node _T_4195 = eq(UInt<5>(0h1d), remapindex_28) when _T_4195 : connect remapVecData[28], Queue10_UInt8_29.io.deq.bits connect remapVecValids[28], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[28] node _T_4196 = eq(UInt<5>(0h1e), remapindex_28) when _T_4196 : connect remapVecData[28], Queue10_UInt8_30.io.deq.bits connect remapVecValids[28], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[28] node _T_4197 = eq(UInt<5>(0h1f), remapindex_28) when _T_4197 : connect remapVecData[28], Queue10_UInt8_31.io.deq.bits connect remapVecValids[28], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[28] node _remapindex_T_29 = add(UInt<5>(0h1d), read_start_index) node remapindex_29 = rem(_remapindex_T_29, UInt<6>(0h20)) node _T_4198 = eq(UInt<1>(0h0), remapindex_29) when _T_4198 : connect remapVecData[29], Queue10_UInt8.io.deq.bits connect remapVecValids[29], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[29] node _T_4199 = eq(UInt<1>(0h1), remapindex_29) when _T_4199 : connect remapVecData[29], Queue10_UInt8_1.io.deq.bits connect remapVecValids[29], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[29] node _T_4200 = eq(UInt<2>(0h2), remapindex_29) when _T_4200 : connect remapVecData[29], Queue10_UInt8_2.io.deq.bits connect remapVecValids[29], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[29] node _T_4201 = eq(UInt<2>(0h3), remapindex_29) when _T_4201 : connect remapVecData[29], Queue10_UInt8_3.io.deq.bits connect remapVecValids[29], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[29] node _T_4202 = eq(UInt<3>(0h4), remapindex_29) when _T_4202 : connect remapVecData[29], Queue10_UInt8_4.io.deq.bits connect remapVecValids[29], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[29] node _T_4203 = eq(UInt<3>(0h5), remapindex_29) when _T_4203 : connect remapVecData[29], Queue10_UInt8_5.io.deq.bits connect remapVecValids[29], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[29] node _T_4204 = eq(UInt<3>(0h6), remapindex_29) when _T_4204 : connect remapVecData[29], Queue10_UInt8_6.io.deq.bits connect remapVecValids[29], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[29] node _T_4205 = eq(UInt<3>(0h7), remapindex_29) when _T_4205 : connect remapVecData[29], Queue10_UInt8_7.io.deq.bits connect remapVecValids[29], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[29] node _T_4206 = eq(UInt<4>(0h8), remapindex_29) when _T_4206 : connect remapVecData[29], Queue10_UInt8_8.io.deq.bits connect remapVecValids[29], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[29] node _T_4207 = eq(UInt<4>(0h9), remapindex_29) when _T_4207 : connect remapVecData[29], Queue10_UInt8_9.io.deq.bits connect remapVecValids[29], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[29] node _T_4208 = eq(UInt<4>(0ha), remapindex_29) when _T_4208 : connect remapVecData[29], Queue10_UInt8_10.io.deq.bits connect remapVecValids[29], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[29] node _T_4209 = eq(UInt<4>(0hb), remapindex_29) when _T_4209 : connect remapVecData[29], Queue10_UInt8_11.io.deq.bits connect remapVecValids[29], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[29] node _T_4210 = eq(UInt<4>(0hc), remapindex_29) when _T_4210 : connect remapVecData[29], Queue10_UInt8_12.io.deq.bits connect remapVecValids[29], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[29] node _T_4211 = eq(UInt<4>(0hd), remapindex_29) when _T_4211 : connect remapVecData[29], Queue10_UInt8_13.io.deq.bits connect remapVecValids[29], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[29] node _T_4212 = eq(UInt<4>(0he), remapindex_29) when _T_4212 : connect remapVecData[29], Queue10_UInt8_14.io.deq.bits connect remapVecValids[29], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[29] node _T_4213 = eq(UInt<4>(0hf), remapindex_29) when _T_4213 : connect remapVecData[29], Queue10_UInt8_15.io.deq.bits connect remapVecValids[29], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[29] node _T_4214 = eq(UInt<5>(0h10), remapindex_29) when _T_4214 : connect remapVecData[29], Queue10_UInt8_16.io.deq.bits connect remapVecValids[29], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[29] node _T_4215 = eq(UInt<5>(0h11), remapindex_29) when _T_4215 : connect remapVecData[29], Queue10_UInt8_17.io.deq.bits connect remapVecValids[29], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[29] node _T_4216 = eq(UInt<5>(0h12), remapindex_29) when _T_4216 : connect remapVecData[29], Queue10_UInt8_18.io.deq.bits connect remapVecValids[29], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[29] node _T_4217 = eq(UInt<5>(0h13), remapindex_29) when _T_4217 : connect remapVecData[29], Queue10_UInt8_19.io.deq.bits connect remapVecValids[29], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[29] node _T_4218 = eq(UInt<5>(0h14), remapindex_29) when _T_4218 : connect remapVecData[29], Queue10_UInt8_20.io.deq.bits connect remapVecValids[29], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[29] node _T_4219 = eq(UInt<5>(0h15), remapindex_29) when _T_4219 : connect remapVecData[29], Queue10_UInt8_21.io.deq.bits connect remapVecValids[29], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[29] node _T_4220 = eq(UInt<5>(0h16), remapindex_29) when _T_4220 : connect remapVecData[29], Queue10_UInt8_22.io.deq.bits connect remapVecValids[29], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[29] node _T_4221 = eq(UInt<5>(0h17), remapindex_29) when _T_4221 : connect remapVecData[29], Queue10_UInt8_23.io.deq.bits connect remapVecValids[29], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[29] node _T_4222 = eq(UInt<5>(0h18), remapindex_29) when _T_4222 : connect remapVecData[29], Queue10_UInt8_24.io.deq.bits connect remapVecValids[29], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[29] node _T_4223 = eq(UInt<5>(0h19), remapindex_29) when _T_4223 : connect remapVecData[29], Queue10_UInt8_25.io.deq.bits connect remapVecValids[29], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[29] node _T_4224 = eq(UInt<5>(0h1a), remapindex_29) when _T_4224 : connect remapVecData[29], Queue10_UInt8_26.io.deq.bits connect remapVecValids[29], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[29] node _T_4225 = eq(UInt<5>(0h1b), remapindex_29) when _T_4225 : connect remapVecData[29], Queue10_UInt8_27.io.deq.bits connect remapVecValids[29], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[29] node _T_4226 = eq(UInt<5>(0h1c), remapindex_29) when _T_4226 : connect remapVecData[29], Queue10_UInt8_28.io.deq.bits connect remapVecValids[29], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[29] node _T_4227 = eq(UInt<5>(0h1d), remapindex_29) when _T_4227 : connect remapVecData[29], Queue10_UInt8_29.io.deq.bits connect remapVecValids[29], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[29] node _T_4228 = eq(UInt<5>(0h1e), remapindex_29) when _T_4228 : connect remapVecData[29], Queue10_UInt8_30.io.deq.bits connect remapVecValids[29], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[29] node _T_4229 = eq(UInt<5>(0h1f), remapindex_29) when _T_4229 : connect remapVecData[29], Queue10_UInt8_31.io.deq.bits connect remapVecValids[29], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[29] node _remapindex_T_30 = add(UInt<5>(0h1e), read_start_index) node remapindex_30 = rem(_remapindex_T_30, UInt<6>(0h20)) node _T_4230 = eq(UInt<1>(0h0), remapindex_30) when _T_4230 : connect remapVecData[30], Queue10_UInt8.io.deq.bits connect remapVecValids[30], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[30] node _T_4231 = eq(UInt<1>(0h1), remapindex_30) when _T_4231 : connect remapVecData[30], Queue10_UInt8_1.io.deq.bits connect remapVecValids[30], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[30] node _T_4232 = eq(UInt<2>(0h2), remapindex_30) when _T_4232 : connect remapVecData[30], Queue10_UInt8_2.io.deq.bits connect remapVecValids[30], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[30] node _T_4233 = eq(UInt<2>(0h3), remapindex_30) when _T_4233 : connect remapVecData[30], Queue10_UInt8_3.io.deq.bits connect remapVecValids[30], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[30] node _T_4234 = eq(UInt<3>(0h4), remapindex_30) when _T_4234 : connect remapVecData[30], Queue10_UInt8_4.io.deq.bits connect remapVecValids[30], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[30] node _T_4235 = eq(UInt<3>(0h5), remapindex_30) when _T_4235 : connect remapVecData[30], Queue10_UInt8_5.io.deq.bits connect remapVecValids[30], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[30] node _T_4236 = eq(UInt<3>(0h6), remapindex_30) when _T_4236 : connect remapVecData[30], Queue10_UInt8_6.io.deq.bits connect remapVecValids[30], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[30] node _T_4237 = eq(UInt<3>(0h7), remapindex_30) when _T_4237 : connect remapVecData[30], Queue10_UInt8_7.io.deq.bits connect remapVecValids[30], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[30] node _T_4238 = eq(UInt<4>(0h8), remapindex_30) when _T_4238 : connect remapVecData[30], Queue10_UInt8_8.io.deq.bits connect remapVecValids[30], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[30] node _T_4239 = eq(UInt<4>(0h9), remapindex_30) when _T_4239 : connect remapVecData[30], Queue10_UInt8_9.io.deq.bits connect remapVecValids[30], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[30] node _T_4240 = eq(UInt<4>(0ha), remapindex_30) when _T_4240 : connect remapVecData[30], Queue10_UInt8_10.io.deq.bits connect remapVecValids[30], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[30] node _T_4241 = eq(UInt<4>(0hb), remapindex_30) when _T_4241 : connect remapVecData[30], Queue10_UInt8_11.io.deq.bits connect remapVecValids[30], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[30] node _T_4242 = eq(UInt<4>(0hc), remapindex_30) when _T_4242 : connect remapVecData[30], Queue10_UInt8_12.io.deq.bits connect remapVecValids[30], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[30] node _T_4243 = eq(UInt<4>(0hd), remapindex_30) when _T_4243 : connect remapVecData[30], Queue10_UInt8_13.io.deq.bits connect remapVecValids[30], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[30] node _T_4244 = eq(UInt<4>(0he), remapindex_30) when _T_4244 : connect remapVecData[30], Queue10_UInt8_14.io.deq.bits connect remapVecValids[30], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[30] node _T_4245 = eq(UInt<4>(0hf), remapindex_30) when _T_4245 : connect remapVecData[30], Queue10_UInt8_15.io.deq.bits connect remapVecValids[30], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[30] node _T_4246 = eq(UInt<5>(0h10), remapindex_30) when _T_4246 : connect remapVecData[30], Queue10_UInt8_16.io.deq.bits connect remapVecValids[30], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[30] node _T_4247 = eq(UInt<5>(0h11), remapindex_30) when _T_4247 : connect remapVecData[30], Queue10_UInt8_17.io.deq.bits connect remapVecValids[30], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[30] node _T_4248 = eq(UInt<5>(0h12), remapindex_30) when _T_4248 : connect remapVecData[30], Queue10_UInt8_18.io.deq.bits connect remapVecValids[30], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[30] node _T_4249 = eq(UInt<5>(0h13), remapindex_30) when _T_4249 : connect remapVecData[30], Queue10_UInt8_19.io.deq.bits connect remapVecValids[30], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[30] node _T_4250 = eq(UInt<5>(0h14), remapindex_30) when _T_4250 : connect remapVecData[30], Queue10_UInt8_20.io.deq.bits connect remapVecValids[30], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[30] node _T_4251 = eq(UInt<5>(0h15), remapindex_30) when _T_4251 : connect remapVecData[30], Queue10_UInt8_21.io.deq.bits connect remapVecValids[30], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[30] node _T_4252 = eq(UInt<5>(0h16), remapindex_30) when _T_4252 : connect remapVecData[30], Queue10_UInt8_22.io.deq.bits connect remapVecValids[30], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[30] node _T_4253 = eq(UInt<5>(0h17), remapindex_30) when _T_4253 : connect remapVecData[30], Queue10_UInt8_23.io.deq.bits connect remapVecValids[30], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[30] node _T_4254 = eq(UInt<5>(0h18), remapindex_30) when _T_4254 : connect remapVecData[30], Queue10_UInt8_24.io.deq.bits connect remapVecValids[30], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[30] node _T_4255 = eq(UInt<5>(0h19), remapindex_30) when _T_4255 : connect remapVecData[30], Queue10_UInt8_25.io.deq.bits connect remapVecValids[30], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[30] node _T_4256 = eq(UInt<5>(0h1a), remapindex_30) when _T_4256 : connect remapVecData[30], Queue10_UInt8_26.io.deq.bits connect remapVecValids[30], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[30] node _T_4257 = eq(UInt<5>(0h1b), remapindex_30) when _T_4257 : connect remapVecData[30], Queue10_UInt8_27.io.deq.bits connect remapVecValids[30], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[30] node _T_4258 = eq(UInt<5>(0h1c), remapindex_30) when _T_4258 : connect remapVecData[30], Queue10_UInt8_28.io.deq.bits connect remapVecValids[30], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[30] node _T_4259 = eq(UInt<5>(0h1d), remapindex_30) when _T_4259 : connect remapVecData[30], Queue10_UInt8_29.io.deq.bits connect remapVecValids[30], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[30] node _T_4260 = eq(UInt<5>(0h1e), remapindex_30) when _T_4260 : connect remapVecData[30], Queue10_UInt8_30.io.deq.bits connect remapVecValids[30], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[30] node _T_4261 = eq(UInt<5>(0h1f), remapindex_30) when _T_4261 : connect remapVecData[30], Queue10_UInt8_31.io.deq.bits connect remapVecValids[30], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[30] node _remapindex_T_31 = add(UInt<5>(0h1f), read_start_index) node remapindex_31 = rem(_remapindex_T_31, UInt<6>(0h20)) node _T_4262 = eq(UInt<1>(0h0), remapindex_31) when _T_4262 : connect remapVecData[31], Queue10_UInt8.io.deq.bits connect remapVecValids[31], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[31] node _T_4263 = eq(UInt<1>(0h1), remapindex_31) when _T_4263 : connect remapVecData[31], Queue10_UInt8_1.io.deq.bits connect remapVecValids[31], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[31] node _T_4264 = eq(UInt<2>(0h2), remapindex_31) when _T_4264 : connect remapVecData[31], Queue10_UInt8_2.io.deq.bits connect remapVecValids[31], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[31] node _T_4265 = eq(UInt<2>(0h3), remapindex_31) when _T_4265 : connect remapVecData[31], Queue10_UInt8_3.io.deq.bits connect remapVecValids[31], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[31] node _T_4266 = eq(UInt<3>(0h4), remapindex_31) when _T_4266 : connect remapVecData[31], Queue10_UInt8_4.io.deq.bits connect remapVecValids[31], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[31] node _T_4267 = eq(UInt<3>(0h5), remapindex_31) when _T_4267 : connect remapVecData[31], Queue10_UInt8_5.io.deq.bits connect remapVecValids[31], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[31] node _T_4268 = eq(UInt<3>(0h6), remapindex_31) when _T_4268 : connect remapVecData[31], Queue10_UInt8_6.io.deq.bits connect remapVecValids[31], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[31] node _T_4269 = eq(UInt<3>(0h7), remapindex_31) when _T_4269 : connect remapVecData[31], Queue10_UInt8_7.io.deq.bits connect remapVecValids[31], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[31] node _T_4270 = eq(UInt<4>(0h8), remapindex_31) when _T_4270 : connect remapVecData[31], Queue10_UInt8_8.io.deq.bits connect remapVecValids[31], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[31] node _T_4271 = eq(UInt<4>(0h9), remapindex_31) when _T_4271 : connect remapVecData[31], Queue10_UInt8_9.io.deq.bits connect remapVecValids[31], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[31] node _T_4272 = eq(UInt<4>(0ha), remapindex_31) when _T_4272 : connect remapVecData[31], Queue10_UInt8_10.io.deq.bits connect remapVecValids[31], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[31] node _T_4273 = eq(UInt<4>(0hb), remapindex_31) when _T_4273 : connect remapVecData[31], Queue10_UInt8_11.io.deq.bits connect remapVecValids[31], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[31] node _T_4274 = eq(UInt<4>(0hc), remapindex_31) when _T_4274 : connect remapVecData[31], Queue10_UInt8_12.io.deq.bits connect remapVecValids[31], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[31] node _T_4275 = eq(UInt<4>(0hd), remapindex_31) when _T_4275 : connect remapVecData[31], Queue10_UInt8_13.io.deq.bits connect remapVecValids[31], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[31] node _T_4276 = eq(UInt<4>(0he), remapindex_31) when _T_4276 : connect remapVecData[31], Queue10_UInt8_14.io.deq.bits connect remapVecValids[31], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[31] node _T_4277 = eq(UInt<4>(0hf), remapindex_31) when _T_4277 : connect remapVecData[31], Queue10_UInt8_15.io.deq.bits connect remapVecValids[31], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[31] node _T_4278 = eq(UInt<5>(0h10), remapindex_31) when _T_4278 : connect remapVecData[31], Queue10_UInt8_16.io.deq.bits connect remapVecValids[31], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[31] node _T_4279 = eq(UInt<5>(0h11), remapindex_31) when _T_4279 : connect remapVecData[31], Queue10_UInt8_17.io.deq.bits connect remapVecValids[31], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[31] node _T_4280 = eq(UInt<5>(0h12), remapindex_31) when _T_4280 : connect remapVecData[31], Queue10_UInt8_18.io.deq.bits connect remapVecValids[31], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[31] node _T_4281 = eq(UInt<5>(0h13), remapindex_31) when _T_4281 : connect remapVecData[31], Queue10_UInt8_19.io.deq.bits connect remapVecValids[31], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[31] node _T_4282 = eq(UInt<5>(0h14), remapindex_31) when _T_4282 : connect remapVecData[31], Queue10_UInt8_20.io.deq.bits connect remapVecValids[31], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[31] node _T_4283 = eq(UInt<5>(0h15), remapindex_31) when _T_4283 : connect remapVecData[31], Queue10_UInt8_21.io.deq.bits connect remapVecValids[31], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[31] node _T_4284 = eq(UInt<5>(0h16), remapindex_31) when _T_4284 : connect remapVecData[31], Queue10_UInt8_22.io.deq.bits connect remapVecValids[31], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[31] node _T_4285 = eq(UInt<5>(0h17), remapindex_31) when _T_4285 : connect remapVecData[31], Queue10_UInt8_23.io.deq.bits connect remapVecValids[31], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[31] node _T_4286 = eq(UInt<5>(0h18), remapindex_31) when _T_4286 : connect remapVecData[31], Queue10_UInt8_24.io.deq.bits connect remapVecValids[31], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[31] node _T_4287 = eq(UInt<5>(0h19), remapindex_31) when _T_4287 : connect remapVecData[31], Queue10_UInt8_25.io.deq.bits connect remapVecValids[31], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[31] node _T_4288 = eq(UInt<5>(0h1a), remapindex_31) when _T_4288 : connect remapVecData[31], Queue10_UInt8_26.io.deq.bits connect remapVecValids[31], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[31] node _T_4289 = eq(UInt<5>(0h1b), remapindex_31) when _T_4289 : connect remapVecData[31], Queue10_UInt8_27.io.deq.bits connect remapVecValids[31], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[31] node _T_4290 = eq(UInt<5>(0h1c), remapindex_31) when _T_4290 : connect remapVecData[31], Queue10_UInt8_28.io.deq.bits connect remapVecValids[31], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[31] node _T_4291 = eq(UInt<5>(0h1d), remapindex_31) when _T_4291 : connect remapVecData[31], Queue10_UInt8_29.io.deq.bits connect remapVecValids[31], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[31] node _T_4292 = eq(UInt<5>(0h1e), remapindex_31) when _T_4292 : connect remapVecData[31], Queue10_UInt8_30.io.deq.bits connect remapVecValids[31], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[31] node _T_4293 = eq(UInt<5>(0h1f), remapindex_31) when _T_4293 : connect remapVecData[31], Queue10_UInt8_31.io.deq.bits connect remapVecValids[31], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[31] node io_consumer_output_data_lo_lo_lo_lo = cat(remapVecData[1], remapVecData[0]) node io_consumer_output_data_lo_lo_lo_hi = cat(remapVecData[3], remapVecData[2]) node io_consumer_output_data_lo_lo_lo = cat(io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo) node io_consumer_output_data_lo_lo_hi_lo = cat(remapVecData[5], remapVecData[4]) node io_consumer_output_data_lo_lo_hi_hi = cat(remapVecData[7], remapVecData[6]) node io_consumer_output_data_lo_lo_hi = cat(io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo) node io_consumer_output_data_lo_lo = cat(io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo) node io_consumer_output_data_lo_hi_lo_lo = cat(remapVecData[9], remapVecData[8]) node io_consumer_output_data_lo_hi_lo_hi = cat(remapVecData[11], remapVecData[10]) node io_consumer_output_data_lo_hi_lo = cat(io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo) node io_consumer_output_data_lo_hi_hi_lo = cat(remapVecData[13], remapVecData[12]) node io_consumer_output_data_lo_hi_hi_hi = cat(remapVecData[15], remapVecData[14]) node io_consumer_output_data_lo_hi_hi = cat(io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo) node io_consumer_output_data_lo_hi = cat(io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo) node io_consumer_output_data_lo = cat(io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo) node io_consumer_output_data_hi_lo_lo_lo = cat(remapVecData[17], remapVecData[16]) node io_consumer_output_data_hi_lo_lo_hi = cat(remapVecData[19], remapVecData[18]) node io_consumer_output_data_hi_lo_lo = cat(io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo) node io_consumer_output_data_hi_lo_hi_lo = cat(remapVecData[21], remapVecData[20]) node io_consumer_output_data_hi_lo_hi_hi = cat(remapVecData[23], remapVecData[22]) node io_consumer_output_data_hi_lo_hi = cat(io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo) node io_consumer_output_data_hi_lo = cat(io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo) node io_consumer_output_data_hi_hi_lo_lo = cat(remapVecData[25], remapVecData[24]) node io_consumer_output_data_hi_hi_lo_hi = cat(remapVecData[27], remapVecData[26]) node io_consumer_output_data_hi_hi_lo = cat(io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo) node io_consumer_output_data_hi_hi_hi_lo = cat(remapVecData[29], remapVecData[28]) node io_consumer_output_data_hi_hi_hi_hi = cat(remapVecData[31], remapVecData[30]) node io_consumer_output_data_hi_hi_hi = cat(io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo) node io_consumer_output_data_hi_hi = cat(io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo) node io_consumer_output_data_hi = cat(io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo) node _io_consumer_output_data_T = cat(io_consumer_output_data_hi, io_consumer_output_data_lo) connect io.consumer.output_data, _io_consumer_output_data_T node _count_valids_T = add(remapVecValids[0], remapVecValids[1]) node _count_valids_T_1 = add(_count_valids_T, remapVecValids[2]) node _count_valids_T_2 = add(_count_valids_T_1, remapVecValids[3]) node _count_valids_T_3 = add(_count_valids_T_2, remapVecValids[4]) node _count_valids_T_4 = add(_count_valids_T_3, remapVecValids[5]) node _count_valids_T_5 = add(_count_valids_T_4, remapVecValids[6]) node _count_valids_T_6 = add(_count_valids_T_5, remapVecValids[7]) node _count_valids_T_7 = add(_count_valids_T_6, remapVecValids[8]) node _count_valids_T_8 = add(_count_valids_T_7, remapVecValids[9]) node _count_valids_T_9 = add(_count_valids_T_8, remapVecValids[10]) node _count_valids_T_10 = add(_count_valids_T_9, remapVecValids[11]) node _count_valids_T_11 = add(_count_valids_T_10, remapVecValids[12]) node _count_valids_T_12 = add(_count_valids_T_11, remapVecValids[13]) node _count_valids_T_13 = add(_count_valids_T_12, remapVecValids[14]) node _count_valids_T_14 = add(_count_valids_T_13, remapVecValids[15]) node _count_valids_T_15 = add(_count_valids_T_14, remapVecValids[16]) node _count_valids_T_16 = add(_count_valids_T_15, remapVecValids[17]) node _count_valids_T_17 = add(_count_valids_T_16, remapVecValids[18]) node _count_valids_T_18 = add(_count_valids_T_17, remapVecValids[19]) node _count_valids_T_19 = add(_count_valids_T_18, remapVecValids[20]) node _count_valids_T_20 = add(_count_valids_T_19, remapVecValids[21]) node _count_valids_T_21 = add(_count_valids_T_20, remapVecValids[22]) node _count_valids_T_22 = add(_count_valids_T_21, remapVecValids[23]) node _count_valids_T_23 = add(_count_valids_T_22, remapVecValids[24]) node _count_valids_T_24 = add(_count_valids_T_23, remapVecValids[25]) node _count_valids_T_25 = add(_count_valids_T_24, remapVecValids[26]) node _count_valids_T_26 = add(_count_valids_T_25, remapVecValids[27]) node _count_valids_T_27 = add(_count_valids_T_26, remapVecValids[28]) node _count_valids_T_28 = add(_count_valids_T_27, remapVecValids[29]) node _count_valids_T_29 = add(_count_valids_T_28, remapVecValids[30]) node count_valids = add(_count_valids_T_29, remapVecValids[31]) node enough_data = neq(count_valids, UInt<1>(0h0)) connect io.consumer.available_output_bytes, count_valids connect io.consumer.output_last_chunk, UInt<1>(0h0) node _T_4294 = and(io.consumer.output_ready, enough_data) when _T_4294 : regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1)) node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1) connect loginfo_cycles_33, _loginfo_cycles_T_67 node _T_4295 = asUInt(reset) node _T_4296 = eq(_T_4295, UInt<1>(0h0)) when _T_4296 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_66 node _T_4297 = asUInt(reset) node _T_4298 = eq(_T_4297, UInt<1>(0h0)) when _T_4298 : printf(clock, UInt<1>(0h1), "lrb READ: bytesread %d\n", io.consumer.user_consumed_bytes) : printf_67 regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1)) node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1) connect loginfo_cycles_34, _loginfo_cycles_T_69 node _T_4299 = asUInt(reset) node _T_4300 = eq(_T_4299, UInt<1>(0h0)) when _T_4300 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_68 node _T_4301 = asUInt(reset) node _T_4302 = eq(_T_4301, UInt<1>(0h0)) when _T_4302 : printf(clock, UInt<1>(0h1), "lrb read data: 0x%x\n", io.consumer.output_data) : printf_69 connect io.consumer.output_valid, enough_data node _remapVecReadys_0_T = lt(UInt<1>(0h0), io.consumer.user_consumed_bytes) node _remapVecReadys_0_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_0_T_2 = and(_remapVecReadys_0_T, _remapVecReadys_0_T_1) connect remapVecReadys[0], _remapVecReadys_0_T_2 node _remapVecReadys_1_T = lt(UInt<1>(0h1), io.consumer.user_consumed_bytes) node _remapVecReadys_1_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_1_T_2 = and(_remapVecReadys_1_T, _remapVecReadys_1_T_1) connect remapVecReadys[1], _remapVecReadys_1_T_2 node _remapVecReadys_2_T = lt(UInt<2>(0h2), io.consumer.user_consumed_bytes) node _remapVecReadys_2_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_2_T_2 = and(_remapVecReadys_2_T, _remapVecReadys_2_T_1) connect remapVecReadys[2], _remapVecReadys_2_T_2 node _remapVecReadys_3_T = lt(UInt<2>(0h3), io.consumer.user_consumed_bytes) node _remapVecReadys_3_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_3_T_2 = and(_remapVecReadys_3_T, _remapVecReadys_3_T_1) connect remapVecReadys[3], _remapVecReadys_3_T_2 node _remapVecReadys_4_T = lt(UInt<3>(0h4), io.consumer.user_consumed_bytes) node _remapVecReadys_4_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_4_T_2 = and(_remapVecReadys_4_T, _remapVecReadys_4_T_1) connect remapVecReadys[4], _remapVecReadys_4_T_2 node _remapVecReadys_5_T = lt(UInt<3>(0h5), io.consumer.user_consumed_bytes) node _remapVecReadys_5_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_5_T_2 = and(_remapVecReadys_5_T, _remapVecReadys_5_T_1) connect remapVecReadys[5], _remapVecReadys_5_T_2 node _remapVecReadys_6_T = lt(UInt<3>(0h6), io.consumer.user_consumed_bytes) node _remapVecReadys_6_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_6_T_2 = and(_remapVecReadys_6_T, _remapVecReadys_6_T_1) connect remapVecReadys[6], _remapVecReadys_6_T_2 node _remapVecReadys_7_T = lt(UInt<3>(0h7), io.consumer.user_consumed_bytes) node _remapVecReadys_7_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_7_T_2 = and(_remapVecReadys_7_T, _remapVecReadys_7_T_1) connect remapVecReadys[7], _remapVecReadys_7_T_2 node _remapVecReadys_8_T = lt(UInt<4>(0h8), io.consumer.user_consumed_bytes) node _remapVecReadys_8_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_8_T_2 = and(_remapVecReadys_8_T, _remapVecReadys_8_T_1) connect remapVecReadys[8], _remapVecReadys_8_T_2 node _remapVecReadys_9_T = lt(UInt<4>(0h9), io.consumer.user_consumed_bytes) node _remapVecReadys_9_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_9_T_2 = and(_remapVecReadys_9_T, _remapVecReadys_9_T_1) connect remapVecReadys[9], _remapVecReadys_9_T_2 node _remapVecReadys_10_T = lt(UInt<4>(0ha), io.consumer.user_consumed_bytes) node _remapVecReadys_10_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_10_T_2 = and(_remapVecReadys_10_T, _remapVecReadys_10_T_1) connect remapVecReadys[10], _remapVecReadys_10_T_2 node _remapVecReadys_11_T = lt(UInt<4>(0hb), io.consumer.user_consumed_bytes) node _remapVecReadys_11_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_11_T_2 = and(_remapVecReadys_11_T, _remapVecReadys_11_T_1) connect remapVecReadys[11], _remapVecReadys_11_T_2 node _remapVecReadys_12_T = lt(UInt<4>(0hc), io.consumer.user_consumed_bytes) node _remapVecReadys_12_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_12_T_2 = and(_remapVecReadys_12_T, _remapVecReadys_12_T_1) connect remapVecReadys[12], _remapVecReadys_12_T_2 node _remapVecReadys_13_T = lt(UInt<4>(0hd), io.consumer.user_consumed_bytes) node _remapVecReadys_13_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_13_T_2 = and(_remapVecReadys_13_T, _remapVecReadys_13_T_1) connect remapVecReadys[13], _remapVecReadys_13_T_2 node _remapVecReadys_14_T = lt(UInt<4>(0he), io.consumer.user_consumed_bytes) node _remapVecReadys_14_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_14_T_2 = and(_remapVecReadys_14_T, _remapVecReadys_14_T_1) connect remapVecReadys[14], _remapVecReadys_14_T_2 node _remapVecReadys_15_T = lt(UInt<4>(0hf), io.consumer.user_consumed_bytes) node _remapVecReadys_15_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_15_T_2 = and(_remapVecReadys_15_T, _remapVecReadys_15_T_1) connect remapVecReadys[15], _remapVecReadys_15_T_2 node _remapVecReadys_16_T = lt(UInt<5>(0h10), io.consumer.user_consumed_bytes) node _remapVecReadys_16_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_16_T_2 = and(_remapVecReadys_16_T, _remapVecReadys_16_T_1) connect remapVecReadys[16], _remapVecReadys_16_T_2 node _remapVecReadys_17_T = lt(UInt<5>(0h11), io.consumer.user_consumed_bytes) node _remapVecReadys_17_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_17_T_2 = and(_remapVecReadys_17_T, _remapVecReadys_17_T_1) connect remapVecReadys[17], _remapVecReadys_17_T_2 node _remapVecReadys_18_T = lt(UInt<5>(0h12), io.consumer.user_consumed_bytes) node _remapVecReadys_18_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_18_T_2 = and(_remapVecReadys_18_T, _remapVecReadys_18_T_1) connect remapVecReadys[18], _remapVecReadys_18_T_2 node _remapVecReadys_19_T = lt(UInt<5>(0h13), io.consumer.user_consumed_bytes) node _remapVecReadys_19_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_19_T_2 = and(_remapVecReadys_19_T, _remapVecReadys_19_T_1) connect remapVecReadys[19], _remapVecReadys_19_T_2 node _remapVecReadys_20_T = lt(UInt<5>(0h14), io.consumer.user_consumed_bytes) node _remapVecReadys_20_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_20_T_2 = and(_remapVecReadys_20_T, _remapVecReadys_20_T_1) connect remapVecReadys[20], _remapVecReadys_20_T_2 node _remapVecReadys_21_T = lt(UInt<5>(0h15), io.consumer.user_consumed_bytes) node _remapVecReadys_21_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_21_T_2 = and(_remapVecReadys_21_T, _remapVecReadys_21_T_1) connect remapVecReadys[21], _remapVecReadys_21_T_2 node _remapVecReadys_22_T = lt(UInt<5>(0h16), io.consumer.user_consumed_bytes) node _remapVecReadys_22_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_22_T_2 = and(_remapVecReadys_22_T, _remapVecReadys_22_T_1) connect remapVecReadys[22], _remapVecReadys_22_T_2 node _remapVecReadys_23_T = lt(UInt<5>(0h17), io.consumer.user_consumed_bytes) node _remapVecReadys_23_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_23_T_2 = and(_remapVecReadys_23_T, _remapVecReadys_23_T_1) connect remapVecReadys[23], _remapVecReadys_23_T_2 node _remapVecReadys_24_T = lt(UInt<5>(0h18), io.consumer.user_consumed_bytes) node _remapVecReadys_24_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_24_T_2 = and(_remapVecReadys_24_T, _remapVecReadys_24_T_1) connect remapVecReadys[24], _remapVecReadys_24_T_2 node _remapVecReadys_25_T = lt(UInt<5>(0h19), io.consumer.user_consumed_bytes) node _remapVecReadys_25_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_25_T_2 = and(_remapVecReadys_25_T, _remapVecReadys_25_T_1) connect remapVecReadys[25], _remapVecReadys_25_T_2 node _remapVecReadys_26_T = lt(UInt<5>(0h1a), io.consumer.user_consumed_bytes) node _remapVecReadys_26_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_26_T_2 = and(_remapVecReadys_26_T, _remapVecReadys_26_T_1) connect remapVecReadys[26], _remapVecReadys_26_T_2 node _remapVecReadys_27_T = lt(UInt<5>(0h1b), io.consumer.user_consumed_bytes) node _remapVecReadys_27_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_27_T_2 = and(_remapVecReadys_27_T, _remapVecReadys_27_T_1) connect remapVecReadys[27], _remapVecReadys_27_T_2 node _remapVecReadys_28_T = lt(UInt<5>(0h1c), io.consumer.user_consumed_bytes) node _remapVecReadys_28_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_28_T_2 = and(_remapVecReadys_28_T, _remapVecReadys_28_T_1) connect remapVecReadys[28], _remapVecReadys_28_T_2 node _remapVecReadys_29_T = lt(UInt<5>(0h1d), io.consumer.user_consumed_bytes) node _remapVecReadys_29_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_29_T_2 = and(_remapVecReadys_29_T, _remapVecReadys_29_T_1) connect remapVecReadys[29], _remapVecReadys_29_T_2 node _remapVecReadys_30_T = lt(UInt<5>(0h1e), io.consumer.user_consumed_bytes) node _remapVecReadys_30_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_30_T_2 = and(_remapVecReadys_30_T, _remapVecReadys_30_T_1) connect remapVecReadys[30], _remapVecReadys_30_T_2 node _remapVecReadys_31_T = lt(UInt<5>(0h1f), io.consumer.user_consumed_bytes) node _remapVecReadys_31_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_31_T_2 = and(_remapVecReadys_31_T, _remapVecReadys_31_T_1) connect remapVecReadys[31], _remapVecReadys_31_T_2 node _T_4303 = and(io.consumer.output_ready, enough_data) when _T_4303 : node _read_start_index_T = add(read_start_index, io.consumer.user_consumed_bytes) node _read_start_index_T_1 = rem(_read_start_index_T, UInt<6>(0h20)) connect read_start_index, _read_start_index_T_1
module ZstdCompressorLitRotBuf_3( // @[ZstdLitRotBuf.scala:152:7] input clock, // @[ZstdLitRotBuf.scala:152:7] input reset, // @[ZstdLitRotBuf.scala:152:7] output io_memwrites_in_ready, // @[ZstdLitRotBuf.scala:153:14] input io_memwrites_in_valid, // @[ZstdLitRotBuf.scala:153:14] input [255:0] io_memwrites_in_bits_data, // @[ZstdLitRotBuf.scala:153:14] input io_memwrites_in_bits_end_of_message, // @[ZstdLitRotBuf.scala:153:14] input [5:0] io_consumer_user_consumed_bytes, // @[ZstdLitRotBuf.scala:153:14] output [5:0] io_consumer_available_output_bytes, // @[ZstdLitRotBuf.scala:153:14] output io_consumer_output_valid, // @[ZstdLitRotBuf.scala:153:14] input io_consumer_output_ready, // @[ZstdLitRotBuf.scala:153:14] output [255:0] io_consumer_output_data // @[ZstdLitRotBuf.scala:153:14] ); wire _Queue10_UInt8_31_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_31_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_31_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_30_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_30_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_30_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_29_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_29_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_29_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_28_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_28_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_28_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_27_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_27_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_27_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_26_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_26_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_26_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_25_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_25_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_25_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_24_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_24_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_24_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_23_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_23_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_23_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_22_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_22_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_22_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_21_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_21_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_21_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_20_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_20_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_20_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_19_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_19_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_19_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_18_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_18_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_18_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_17_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_17_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_17_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_16_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_16_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_16_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_15_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_15_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_15_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_14_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_14_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_14_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_13_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_13_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_13_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_12_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_12_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_12_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_11_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_11_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_11_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_10_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_10_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_10_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_9_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_9_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_9_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_8_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_8_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_7_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_7_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_7_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_6_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_6_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_6_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_5_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_5_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_5_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_4_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_4_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_4_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_3_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_3_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_3_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_2_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_2_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_2_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_1_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_1_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_1_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _incoming_writes_Q_io_deq_valid; // @[ZstdLitRotBuf.scala:158:33] wire [255:0] _incoming_writes_Q_io_deq_bits_data; // @[ZstdLitRotBuf.scala:158:33] wire [5:0] _incoming_writes_Q_io_deq_bits_validbytes; // @[ZstdLitRotBuf.scala:158:33] wire _incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdLitRotBuf.scala:158:33] wire io_memwrites_in_valid_0 = io_memwrites_in_valid; // @[ZstdLitRotBuf.scala:152:7] wire [255:0] io_memwrites_in_bits_data_0 = io_memwrites_in_bits_data; // @[ZstdLitRotBuf.scala:152:7] wire io_memwrites_in_bits_end_of_message_0 = io_memwrites_in_bits_end_of_message; // @[ZstdLitRotBuf.scala:152:7] wire [5:0] io_consumer_user_consumed_bytes_0 = io_consumer_user_consumed_bytes; // @[ZstdLitRotBuf.scala:152:7] wire io_consumer_output_ready_0 = io_consumer_output_ready; // @[ZstdLitRotBuf.scala:152:7] wire [5:0] io_memwrites_in_bits_validbytes = 6'h1; // @[ZstdLitRotBuf.scala:152:7] wire io_consumer_output_last_chunk = 1'h0; // @[ZstdLitRotBuf.scala:152:7] wire enough_data; // @[ZstdLitRotBuf.scala:251:34] wire [255:0] _io_consumer_output_data_T; // @[ZstdLitRotBuf.scala:246:33] wire io_memwrites_in_ready_0; // @[ZstdLitRotBuf.scala:152:7] wire [5:0] io_consumer_available_output_bytes_0; // @[ZstdLitRotBuf.scala:152:7] wire io_consumer_output_valid_0; // @[ZstdLitRotBuf.scala:152:7] wire [255:0] io_consumer_output_data_0; // @[ZstdLitRotBuf.scala:152:7] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [5:0] write_start_index; // @[ZstdLitRotBuf.scala:172:34] wire [6:0] _idx_T = {1'h0, write_start_index}; // @[ZstdLitRotBuf.scala:172:34, :182:34] wire [6:0] _GEN = _idx_T % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx = _GEN[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_0 = _idx_T_1 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_1 = _GEN_0[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_1 = _idx_T_2 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_2 = _GEN_1[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_2 = _idx_T_3 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_3 = _GEN_2[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_3 = _idx_T_4 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_4 = _GEN_3[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_4 = _idx_T_5 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_5 = _GEN_4[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_5 = _idx_T_6 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_6 = _GEN_5[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_6 = _idx_T_7 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_7 = _GEN_6[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_7 = _idx_T_8 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_8 = _GEN_7[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_8 = _idx_T_9 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_9 = _GEN_8[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_9 = _idx_T_10 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_10 = _GEN_9[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_10 = _idx_T_11 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_11 = _GEN_10[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_11 = _idx_T_12 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_12 = _GEN_11[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_12 = _idx_T_13 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_13 = _GEN_12[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_13 = _idx_T_14 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_14 = _GEN_13[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_14 = _idx_T_15 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_15 = _GEN_14[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_15 = _idx_T_16 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_16 = _GEN_15[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_16 = _idx_T_17 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_17 = _GEN_16[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_17 = _idx_T_18 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_18 = _GEN_17[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_18 = _idx_T_19 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_19 = _GEN_18[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_19 = _idx_T_20 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_20 = _GEN_19[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_20 = _idx_T_21 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_21 = _GEN_20[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_21 = _idx_T_22 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_22 = _GEN_21[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_22 = _idx_T_23 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_23 = _GEN_22[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_23 = _idx_T_24 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_24 = _GEN_23[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_24 = _idx_T_25 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_25 = _GEN_24[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_25 = _idx_T_26 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_26 = _GEN_25[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_26 = _idx_T_27 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_27 = _GEN_26[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_27 = _idx_T_28 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_28 = _GEN_27[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_28 = _idx_T_29 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_29 = _GEN_28[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_29 = _idx_T_30 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_30 = _GEN_29[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_30 = _idx_T_31 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_31 = _GEN_30[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdLitRotBuf.scala:158:33, :182:34, :190:47] wire [6:0] _GEN_31 = wrap_len_index_wide % 7'h20; // @[ZstdLitRotBuf.scala:190:47, :191:48] wire [5:0] wrap_len_index_end = _GEN_31[5:0]; // @[ZstdLitRotBuf.scala:191:48] wire wrapped = |(wrap_len_index_wide[6:5]); // @[ZstdLitRotBuf.scala:190:47, :192:37] wire _all_queues_ready_T = _Queue10_UInt8_io_enq_ready & _Queue10_UInt8_1_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue10_UInt8_2_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue10_UInt8_3_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue10_UInt8_4_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue10_UInt8_5_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue10_UInt8_6_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue10_UInt8_7_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue10_UInt8_8_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue10_UInt8_9_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue10_UInt8_10_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue10_UInt8_11_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue10_UInt8_12_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue10_UInt8_13_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue10_UInt8_14_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue10_UInt8_15_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue10_UInt8_16_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue10_UInt8_17_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue10_UInt8_18_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue10_UInt8_19_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue10_UInt8_20_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue10_UInt8_21_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue10_UInt8_22_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue10_UInt8_23_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue10_UInt8_24_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue10_UInt8_25_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue10_UInt8_26_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue10_UInt8_27_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue10_UInt8_28_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue10_UInt8_29_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue10_UInt8_30_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire all_queues_ready = _all_queues_ready_T_29 & _Queue10_UInt8_31_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _T_3140 = _incoming_writes_Q_io_deq_valid & all_queues_ready; // @[Misc.scala:29:18] wire _GEN_32 = write_start_index == 6'h0; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T = _GEN_32; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_3; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_3 = _GEN_32; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_1 = |wrap_len_index_end; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_2 = _use_this_queue_T | _use_this_queue_T_1; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_4 = |wrap_len_index_end; // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_33 = write_start_index < 6'h2; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_6; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_6 = _GEN_33; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_9; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_9 = _GEN_33; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_7 = |(wrap_len_index_end[5:1]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_8 = _use_this_queue_T_6 | _use_this_queue_T_7; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_10 = |(wrap_len_index_end[5:1]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_34 = write_start_index < 6'h3; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_12; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_12 = _GEN_34; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_15; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_15 = _GEN_34; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_35 = wrap_len_index_end > 6'h2; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_13; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_13 = _GEN_35; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_16; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_16 = _GEN_35; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_14 = _use_this_queue_T_12 | _use_this_queue_T_13; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_36 = write_start_index < 6'h4; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_18; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_18 = _GEN_36; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_21; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_21 = _GEN_36; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_19 = |(wrap_len_index_end[5:2]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_20 = _use_this_queue_T_18 | _use_this_queue_T_19; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_22 = |(wrap_len_index_end[5:2]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_37 = write_start_index < 6'h5; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_24; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_24 = _GEN_37; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_27; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_27 = _GEN_37; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_38 = wrap_len_index_end > 6'h4; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_25; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_25 = _GEN_38; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_28; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_28 = _GEN_38; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_26 = _use_this_queue_T_24 | _use_this_queue_T_25; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_39 = write_start_index < 6'h6; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_30; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_30 = _GEN_39; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_33; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_33 = _GEN_39; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_40 = wrap_len_index_end > 6'h5; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_31; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_31 = _GEN_40; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_34; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_34 = _GEN_40; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_32 = _use_this_queue_T_30 | _use_this_queue_T_31; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_41 = write_start_index < 6'h7; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_36; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_36 = _GEN_41; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_39; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_39 = _GEN_41; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_42 = wrap_len_index_end > 6'h6; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_37; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_37 = _GEN_42; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_40; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_40 = _GEN_42; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_38 = _use_this_queue_T_36 | _use_this_queue_T_37; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_43 = write_start_index < 6'h8; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_42; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_42 = _GEN_43; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_45; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_45 = _GEN_43; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_43 = |(wrap_len_index_end[5:3]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_44 = _use_this_queue_T_42 | _use_this_queue_T_43; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_46 = |(wrap_len_index_end[5:3]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_44 = write_start_index < 6'h9; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_48; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_48 = _GEN_44; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_51; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_51 = _GEN_44; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_45 = wrap_len_index_end > 6'h8; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_49; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_49 = _GEN_45; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_52; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_52 = _GEN_45; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_50 = _use_this_queue_T_48 | _use_this_queue_T_49; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_46 = write_start_index < 6'hA; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_54; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_54 = _GEN_46; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_57; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_57 = _GEN_46; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_47 = wrap_len_index_end > 6'h9; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_55; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_55 = _GEN_47; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_58; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_58 = _GEN_47; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_56 = _use_this_queue_T_54 | _use_this_queue_T_55; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_48 = write_start_index < 6'hB; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_60; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_60 = _GEN_48; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_63; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_63 = _GEN_48; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_49 = wrap_len_index_end > 6'hA; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_61; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_61 = _GEN_49; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_64; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_64 = _GEN_49; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_62 = _use_this_queue_T_60 | _use_this_queue_T_61; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_50 = write_start_index < 6'hC; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_66; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_66 = _GEN_50; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_69; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_69 = _GEN_50; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_51 = wrap_len_index_end > 6'hB; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_67; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_67 = _GEN_51; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_70; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_70 = _GEN_51; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_68 = _use_this_queue_T_66 | _use_this_queue_T_67; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_52 = write_start_index < 6'hD; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_72; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_72 = _GEN_52; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_75; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_75 = _GEN_52; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_53 = wrap_len_index_end > 6'hC; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_73; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_73 = _GEN_53; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_76; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_76 = _GEN_53; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_74 = _use_this_queue_T_72 | _use_this_queue_T_73; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_54 = write_start_index < 6'hE; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_78; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_78 = _GEN_54; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_81; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_81 = _GEN_54; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_55 = wrap_len_index_end > 6'hD; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_79; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_79 = _GEN_55; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_82; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_82 = _GEN_55; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_80 = _use_this_queue_T_78 | _use_this_queue_T_79; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_56 = write_start_index < 6'hF; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_84; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_84 = _GEN_56; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_87; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_87 = _GEN_56; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_57 = wrap_len_index_end > 6'hE; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_85; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_85 = _GEN_57; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_88; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_88 = _GEN_57; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_86 = _use_this_queue_T_84 | _use_this_queue_T_85; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_58 = write_start_index < 6'h10; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_90; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_90 = _GEN_58; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_93; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_93 = _GEN_58; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_91 = |(wrap_len_index_end[5:4]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_92 = _use_this_queue_T_90 | _use_this_queue_T_91; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_94 = |(wrap_len_index_end[5:4]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_59 = write_start_index < 6'h11; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_96; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_96 = _GEN_59; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_99; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_99 = _GEN_59; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_60 = wrap_len_index_end > 6'h10; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_97; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_97 = _GEN_60; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_100; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_100 = _GEN_60; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_98 = _use_this_queue_T_96 | _use_this_queue_T_97; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_61 = write_start_index < 6'h12; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_102; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_102 = _GEN_61; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_105; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_105 = _GEN_61; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_62 = wrap_len_index_end > 6'h11; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_103; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_103 = _GEN_62; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_106; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_106 = _GEN_62; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_104 = _use_this_queue_T_102 | _use_this_queue_T_103; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_63 = write_start_index < 6'h13; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_108; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_108 = _GEN_63; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_111; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_111 = _GEN_63; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_64 = wrap_len_index_end > 6'h12; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_109; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_109 = _GEN_64; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_112; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_112 = _GEN_64; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_110 = _use_this_queue_T_108 | _use_this_queue_T_109; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_65 = write_start_index < 6'h14; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_114; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_114 = _GEN_65; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_117; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_117 = _GEN_65; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_66 = wrap_len_index_end > 6'h13; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_115; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_115 = _GEN_66; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_118; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_118 = _GEN_66; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_116 = _use_this_queue_T_114 | _use_this_queue_T_115; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_67 = write_start_index < 6'h15; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_120; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_120 = _GEN_67; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_123; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_123 = _GEN_67; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_68 = wrap_len_index_end > 6'h14; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_121; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_121 = _GEN_68; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_124; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_124 = _GEN_68; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_122 = _use_this_queue_T_120 | _use_this_queue_T_121; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_69 = write_start_index < 6'h16; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_126; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_126 = _GEN_69; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_129; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_129 = _GEN_69; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_70 = wrap_len_index_end > 6'h15; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_127; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_127 = _GEN_70; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_130; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_130 = _GEN_70; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_128 = _use_this_queue_T_126 | _use_this_queue_T_127; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_71 = write_start_index < 6'h17; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_132; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_132 = _GEN_71; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_135; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_135 = _GEN_71; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_72 = wrap_len_index_end > 6'h16; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_133; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_133 = _GEN_72; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_136; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_136 = _GEN_72; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_134 = _use_this_queue_T_132 | _use_this_queue_T_133; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_73 = write_start_index < 6'h18; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_138; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_138 = _GEN_73; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_141; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_141 = _GEN_73; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_74 = wrap_len_index_end > 6'h17; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_139; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_139 = _GEN_74; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_142; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_142 = _GEN_74; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_140 = _use_this_queue_T_138 | _use_this_queue_T_139; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_75 = write_start_index < 6'h19; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_144; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_144 = _GEN_75; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_147; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_147 = _GEN_75; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_76 = wrap_len_index_end > 6'h18; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_145; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_145 = _GEN_76; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_148; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_148 = _GEN_76; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_146 = _use_this_queue_T_144 | _use_this_queue_T_145; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_77 = write_start_index < 6'h1A; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_150; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_150 = _GEN_77; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_153; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_153 = _GEN_77; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_78 = wrap_len_index_end > 6'h19; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_151; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_151 = _GEN_78; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_154; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_154 = _GEN_78; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_152 = _use_this_queue_T_150 | _use_this_queue_T_151; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_79 = write_start_index < 6'h1B; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_156; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_156 = _GEN_79; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_159; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_159 = _GEN_79; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_80 = wrap_len_index_end > 6'h1A; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_157; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_157 = _GEN_80; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_160; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_160 = _GEN_80; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_158 = _use_this_queue_T_156 | _use_this_queue_T_157; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_81 = write_start_index < 6'h1C; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_162; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_162 = _GEN_81; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_165; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_165 = _GEN_81; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_82 = wrap_len_index_end > 6'h1B; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_163; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_163 = _GEN_82; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_166; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_166 = _GEN_82; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_164 = _use_this_queue_T_162 | _use_this_queue_T_163; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_83 = write_start_index < 6'h1D; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_168; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_168 = _GEN_83; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_171; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_171 = _GEN_83; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_84 = wrap_len_index_end > 6'h1C; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_169; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_169 = _GEN_84; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_172; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_172 = _GEN_84; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_170 = _use_this_queue_T_168 | _use_this_queue_T_169; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_85 = write_start_index < 6'h1E; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_174; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_174 = _GEN_85; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_177; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_177 = _GEN_85; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_86 = wrap_len_index_end > 6'h1D; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_175; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_175 = _GEN_86; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_178; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_178 = _GEN_86; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_176 = _use_this_queue_T_174 | _use_this_queue_T_175; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_87 = write_start_index < 6'h1F; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_180; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_180 = _GEN_87; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_183; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_183 = _GEN_87; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_88 = wrap_len_index_end > 6'h1E; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_181; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_181 = _GEN_88; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_184; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_184 = _GEN_88; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_182 = _use_this_queue_T_180 | _use_this_queue_T_181; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_188 = _use_this_queue_T_186 | _use_this_queue_T_187; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[ZstdLitRotBuf.scala:172:34, :210:41, :211:41] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [5:0] read_start_index; // @[ZstdLitRotBuf.scala:222:33] wire [7:0] remapVecData_0; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_1; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_2; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_3; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_4; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_5; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_6; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_7; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_8; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_9; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_10; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_11; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_12; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_13; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_14; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_15; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_16; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_17; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_18; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_19; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_20; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_21; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_22; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_23; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_24; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_25; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_26; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_27; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_28; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_29; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_30; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_31; // @[ZstdLitRotBuf.scala:225:26] wire remapVecValids_0; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_1; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_2; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_3; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_4; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_5; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_6; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_7; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_8; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_9; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_10; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_11; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_12; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_13; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_14; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_15; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_16; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_17; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_18; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_19; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_20; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_21; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_22; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_23; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_24; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_25; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_26; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_27; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_28; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_29; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_30; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_31; // @[ZstdLitRotBuf.scala:226:28] wire _remapVecReadys_0_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_1_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_2_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_3_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_4_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_5_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_6_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_7_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_8_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_9_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_10_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_11_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_12_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_13_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_14_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_15_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_16_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_17_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_18_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_19_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_20_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_21_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_22_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_23_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_24_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_25_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_26_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_27_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_28_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_29_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_30_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_31_T_2; // @[ZstdLitRotBuf.scala:270:78] wire remapVecReadys_0; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_1; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_2; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_3; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_4; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_5; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_6; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_7; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_8; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_9; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_10; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_11; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_12; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_13; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_14; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_15; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_16; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_17; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_18; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_19; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_20; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_21; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_22; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_23; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_24; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_25; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_26; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_27; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_28; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_29; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_30; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_31; // @[ZstdLitRotBuf.scala:227:28] wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[ZstdLitRotBuf.scala:222:33, :237:33] wire [6:0] _GEN_89 = _remapindex_T % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex = _GEN_89[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3270 = remapindex == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3271 = remapindex == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3272 = remapindex == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3273 = remapindex == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3274 = remapindex == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3275 = remapindex == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3276 = remapindex == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3277 = remapindex == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3278 = remapindex == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3279 = remapindex == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3280 = remapindex == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3281 = remapindex == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3282 = remapindex == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3283 = remapindex == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3284 = remapindex == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3285 = remapindex == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3286 = remapindex == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3287 = remapindex == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3288 = remapindex == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3289 = remapindex == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3290 = remapindex == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3291 = remapindex == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3292 = remapindex == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3293 = remapindex == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3294 = remapindex == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3295 = remapindex == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3296 = remapindex == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3297 = remapindex == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3298 = remapindex == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3299 = remapindex == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3300 = remapindex == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3301 = remapindex == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_0 = _T_3301 ? _Queue10_UInt8_31_io_deq_bits : _T_3300 ? _Queue10_UInt8_30_io_deq_bits : _T_3299 ? _Queue10_UInt8_29_io_deq_bits : _T_3298 ? _Queue10_UInt8_28_io_deq_bits : _T_3297 ? _Queue10_UInt8_27_io_deq_bits : _T_3296 ? _Queue10_UInt8_26_io_deq_bits : _T_3295 ? _Queue10_UInt8_25_io_deq_bits : _T_3294 ? _Queue10_UInt8_24_io_deq_bits : _T_3293 ? _Queue10_UInt8_23_io_deq_bits : _T_3292 ? _Queue10_UInt8_22_io_deq_bits : _T_3291 ? _Queue10_UInt8_21_io_deq_bits : _T_3290 ? _Queue10_UInt8_20_io_deq_bits : _T_3289 ? _Queue10_UInt8_19_io_deq_bits : _T_3288 ? _Queue10_UInt8_18_io_deq_bits : _T_3287 ? _Queue10_UInt8_17_io_deq_bits : _T_3286 ? _Queue10_UInt8_16_io_deq_bits : _T_3285 ? _Queue10_UInt8_15_io_deq_bits : _T_3284 ? _Queue10_UInt8_14_io_deq_bits : _T_3283 ? _Queue10_UInt8_13_io_deq_bits : _T_3282 ? _Queue10_UInt8_12_io_deq_bits : _T_3281 ? _Queue10_UInt8_11_io_deq_bits : _T_3280 ? _Queue10_UInt8_10_io_deq_bits : _T_3279 ? _Queue10_UInt8_9_io_deq_bits : _T_3278 ? _Queue10_UInt8_8_io_deq_bits : _T_3277 ? _Queue10_UInt8_7_io_deq_bits : _T_3276 ? _Queue10_UInt8_6_io_deq_bits : _T_3275 ? _Queue10_UInt8_5_io_deq_bits : _T_3274 ? _Queue10_UInt8_4_io_deq_bits : _T_3273 ? _Queue10_UInt8_3_io_deq_bits : _T_3272 ? _Queue10_UInt8_2_io_deq_bits : _T_3271 ? _Queue10_UInt8_1_io_deq_bits : _T_3270 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_0 = _T_3301 ? _Queue10_UInt8_31_io_deq_valid : _T_3300 ? _Queue10_UInt8_30_io_deq_valid : _T_3299 ? _Queue10_UInt8_29_io_deq_valid : _T_3298 ? _Queue10_UInt8_28_io_deq_valid : _T_3297 ? _Queue10_UInt8_27_io_deq_valid : _T_3296 ? _Queue10_UInt8_26_io_deq_valid : _T_3295 ? _Queue10_UInt8_25_io_deq_valid : _T_3294 ? _Queue10_UInt8_24_io_deq_valid : _T_3293 ? _Queue10_UInt8_23_io_deq_valid : _T_3292 ? _Queue10_UInt8_22_io_deq_valid : _T_3291 ? _Queue10_UInt8_21_io_deq_valid : _T_3290 ? _Queue10_UInt8_20_io_deq_valid : _T_3289 ? _Queue10_UInt8_19_io_deq_valid : _T_3288 ? _Queue10_UInt8_18_io_deq_valid : _T_3287 ? _Queue10_UInt8_17_io_deq_valid : _T_3286 ? _Queue10_UInt8_16_io_deq_valid : _T_3285 ? _Queue10_UInt8_15_io_deq_valid : _T_3284 ? _Queue10_UInt8_14_io_deq_valid : _T_3283 ? _Queue10_UInt8_13_io_deq_valid : _T_3282 ? _Queue10_UInt8_12_io_deq_valid : _T_3281 ? _Queue10_UInt8_11_io_deq_valid : _T_3280 ? _Queue10_UInt8_10_io_deq_valid : _T_3279 ? _Queue10_UInt8_9_io_deq_valid : _T_3278 ? _Queue10_UInt8_8_io_deq_valid : _T_3277 ? _Queue10_UInt8_7_io_deq_valid : _T_3276 ? _Queue10_UInt8_6_io_deq_valid : _T_3275 ? _Queue10_UInt8_5_io_deq_valid : _T_3274 ? _Queue10_UInt8_4_io_deq_valid : _T_3273 ? _Queue10_UInt8_3_io_deq_valid : _T_3272 ? _Queue10_UInt8_2_io_deq_valid : _T_3271 ? _Queue10_UInt8_1_io_deq_valid : _T_3270 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_90 = _remapindex_T_1 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_1 = _GEN_90[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3302 = remapindex_1 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3303 = remapindex_1 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3304 = remapindex_1 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3305 = remapindex_1 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3306 = remapindex_1 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3307 = remapindex_1 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3308 = remapindex_1 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3309 = remapindex_1 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3310 = remapindex_1 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3311 = remapindex_1 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3312 = remapindex_1 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3313 = remapindex_1 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3314 = remapindex_1 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3315 = remapindex_1 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3316 = remapindex_1 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3317 = remapindex_1 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3318 = remapindex_1 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3319 = remapindex_1 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3320 = remapindex_1 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3321 = remapindex_1 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3322 = remapindex_1 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3323 = remapindex_1 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3324 = remapindex_1 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3325 = remapindex_1 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3326 = remapindex_1 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3327 = remapindex_1 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3328 = remapindex_1 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3329 = remapindex_1 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3330 = remapindex_1 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3331 = remapindex_1 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3332 = remapindex_1 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3333 = remapindex_1 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_1 = _T_3333 ? _Queue10_UInt8_31_io_deq_bits : _T_3332 ? _Queue10_UInt8_30_io_deq_bits : _T_3331 ? _Queue10_UInt8_29_io_deq_bits : _T_3330 ? _Queue10_UInt8_28_io_deq_bits : _T_3329 ? _Queue10_UInt8_27_io_deq_bits : _T_3328 ? _Queue10_UInt8_26_io_deq_bits : _T_3327 ? _Queue10_UInt8_25_io_deq_bits : _T_3326 ? _Queue10_UInt8_24_io_deq_bits : _T_3325 ? _Queue10_UInt8_23_io_deq_bits : _T_3324 ? _Queue10_UInt8_22_io_deq_bits : _T_3323 ? _Queue10_UInt8_21_io_deq_bits : _T_3322 ? _Queue10_UInt8_20_io_deq_bits : _T_3321 ? _Queue10_UInt8_19_io_deq_bits : _T_3320 ? _Queue10_UInt8_18_io_deq_bits : _T_3319 ? _Queue10_UInt8_17_io_deq_bits : _T_3318 ? _Queue10_UInt8_16_io_deq_bits : _T_3317 ? _Queue10_UInt8_15_io_deq_bits : _T_3316 ? _Queue10_UInt8_14_io_deq_bits : _T_3315 ? _Queue10_UInt8_13_io_deq_bits : _T_3314 ? _Queue10_UInt8_12_io_deq_bits : _T_3313 ? _Queue10_UInt8_11_io_deq_bits : _T_3312 ? _Queue10_UInt8_10_io_deq_bits : _T_3311 ? _Queue10_UInt8_9_io_deq_bits : _T_3310 ? _Queue10_UInt8_8_io_deq_bits : _T_3309 ? _Queue10_UInt8_7_io_deq_bits : _T_3308 ? _Queue10_UInt8_6_io_deq_bits : _T_3307 ? _Queue10_UInt8_5_io_deq_bits : _T_3306 ? _Queue10_UInt8_4_io_deq_bits : _T_3305 ? _Queue10_UInt8_3_io_deq_bits : _T_3304 ? _Queue10_UInt8_2_io_deq_bits : _T_3303 ? _Queue10_UInt8_1_io_deq_bits : _T_3302 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_1 = _T_3333 ? _Queue10_UInt8_31_io_deq_valid : _T_3332 ? _Queue10_UInt8_30_io_deq_valid : _T_3331 ? _Queue10_UInt8_29_io_deq_valid : _T_3330 ? _Queue10_UInt8_28_io_deq_valid : _T_3329 ? _Queue10_UInt8_27_io_deq_valid : _T_3328 ? _Queue10_UInt8_26_io_deq_valid : _T_3327 ? _Queue10_UInt8_25_io_deq_valid : _T_3326 ? _Queue10_UInt8_24_io_deq_valid : _T_3325 ? _Queue10_UInt8_23_io_deq_valid : _T_3324 ? _Queue10_UInt8_22_io_deq_valid : _T_3323 ? _Queue10_UInt8_21_io_deq_valid : _T_3322 ? _Queue10_UInt8_20_io_deq_valid : _T_3321 ? _Queue10_UInt8_19_io_deq_valid : _T_3320 ? _Queue10_UInt8_18_io_deq_valid : _T_3319 ? _Queue10_UInt8_17_io_deq_valid : _T_3318 ? _Queue10_UInt8_16_io_deq_valid : _T_3317 ? _Queue10_UInt8_15_io_deq_valid : _T_3316 ? _Queue10_UInt8_14_io_deq_valid : _T_3315 ? _Queue10_UInt8_13_io_deq_valid : _T_3314 ? _Queue10_UInt8_12_io_deq_valid : _T_3313 ? _Queue10_UInt8_11_io_deq_valid : _T_3312 ? _Queue10_UInt8_10_io_deq_valid : _T_3311 ? _Queue10_UInt8_9_io_deq_valid : _T_3310 ? _Queue10_UInt8_8_io_deq_valid : _T_3309 ? _Queue10_UInt8_7_io_deq_valid : _T_3308 ? _Queue10_UInt8_6_io_deq_valid : _T_3307 ? _Queue10_UInt8_5_io_deq_valid : _T_3306 ? _Queue10_UInt8_4_io_deq_valid : _T_3305 ? _Queue10_UInt8_3_io_deq_valid : _T_3304 ? _Queue10_UInt8_2_io_deq_valid : _T_3303 ? _Queue10_UInt8_1_io_deq_valid : _T_3302 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_91 = _remapindex_T_2 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_2 = _GEN_91[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3334 = remapindex_2 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3335 = remapindex_2 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3336 = remapindex_2 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3337 = remapindex_2 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3338 = remapindex_2 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3339 = remapindex_2 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3340 = remapindex_2 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3341 = remapindex_2 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3342 = remapindex_2 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3343 = remapindex_2 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3344 = remapindex_2 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3345 = remapindex_2 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3346 = remapindex_2 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3347 = remapindex_2 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3348 = remapindex_2 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3349 = remapindex_2 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3350 = remapindex_2 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3351 = remapindex_2 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3352 = remapindex_2 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3353 = remapindex_2 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3354 = remapindex_2 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3355 = remapindex_2 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3356 = remapindex_2 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3357 = remapindex_2 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3358 = remapindex_2 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3359 = remapindex_2 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3360 = remapindex_2 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3361 = remapindex_2 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3362 = remapindex_2 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3363 = remapindex_2 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3364 = remapindex_2 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3365 = remapindex_2 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_2 = _T_3365 ? _Queue10_UInt8_31_io_deq_bits : _T_3364 ? _Queue10_UInt8_30_io_deq_bits : _T_3363 ? _Queue10_UInt8_29_io_deq_bits : _T_3362 ? _Queue10_UInt8_28_io_deq_bits : _T_3361 ? _Queue10_UInt8_27_io_deq_bits : _T_3360 ? _Queue10_UInt8_26_io_deq_bits : _T_3359 ? _Queue10_UInt8_25_io_deq_bits : _T_3358 ? _Queue10_UInt8_24_io_deq_bits : _T_3357 ? _Queue10_UInt8_23_io_deq_bits : _T_3356 ? _Queue10_UInt8_22_io_deq_bits : _T_3355 ? _Queue10_UInt8_21_io_deq_bits : _T_3354 ? _Queue10_UInt8_20_io_deq_bits : _T_3353 ? _Queue10_UInt8_19_io_deq_bits : _T_3352 ? _Queue10_UInt8_18_io_deq_bits : _T_3351 ? _Queue10_UInt8_17_io_deq_bits : _T_3350 ? _Queue10_UInt8_16_io_deq_bits : _T_3349 ? _Queue10_UInt8_15_io_deq_bits : _T_3348 ? _Queue10_UInt8_14_io_deq_bits : _T_3347 ? _Queue10_UInt8_13_io_deq_bits : _T_3346 ? _Queue10_UInt8_12_io_deq_bits : _T_3345 ? _Queue10_UInt8_11_io_deq_bits : _T_3344 ? _Queue10_UInt8_10_io_deq_bits : _T_3343 ? _Queue10_UInt8_9_io_deq_bits : _T_3342 ? _Queue10_UInt8_8_io_deq_bits : _T_3341 ? _Queue10_UInt8_7_io_deq_bits : _T_3340 ? _Queue10_UInt8_6_io_deq_bits : _T_3339 ? _Queue10_UInt8_5_io_deq_bits : _T_3338 ? _Queue10_UInt8_4_io_deq_bits : _T_3337 ? _Queue10_UInt8_3_io_deq_bits : _T_3336 ? _Queue10_UInt8_2_io_deq_bits : _T_3335 ? _Queue10_UInt8_1_io_deq_bits : _T_3334 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_2 = _T_3365 ? _Queue10_UInt8_31_io_deq_valid : _T_3364 ? _Queue10_UInt8_30_io_deq_valid : _T_3363 ? _Queue10_UInt8_29_io_deq_valid : _T_3362 ? _Queue10_UInt8_28_io_deq_valid : _T_3361 ? _Queue10_UInt8_27_io_deq_valid : _T_3360 ? _Queue10_UInt8_26_io_deq_valid : _T_3359 ? _Queue10_UInt8_25_io_deq_valid : _T_3358 ? _Queue10_UInt8_24_io_deq_valid : _T_3357 ? _Queue10_UInt8_23_io_deq_valid : _T_3356 ? _Queue10_UInt8_22_io_deq_valid : _T_3355 ? _Queue10_UInt8_21_io_deq_valid : _T_3354 ? _Queue10_UInt8_20_io_deq_valid : _T_3353 ? _Queue10_UInt8_19_io_deq_valid : _T_3352 ? _Queue10_UInt8_18_io_deq_valid : _T_3351 ? _Queue10_UInt8_17_io_deq_valid : _T_3350 ? _Queue10_UInt8_16_io_deq_valid : _T_3349 ? _Queue10_UInt8_15_io_deq_valid : _T_3348 ? _Queue10_UInt8_14_io_deq_valid : _T_3347 ? _Queue10_UInt8_13_io_deq_valid : _T_3346 ? _Queue10_UInt8_12_io_deq_valid : _T_3345 ? _Queue10_UInt8_11_io_deq_valid : _T_3344 ? _Queue10_UInt8_10_io_deq_valid : _T_3343 ? _Queue10_UInt8_9_io_deq_valid : _T_3342 ? _Queue10_UInt8_8_io_deq_valid : _T_3341 ? _Queue10_UInt8_7_io_deq_valid : _T_3340 ? _Queue10_UInt8_6_io_deq_valid : _T_3339 ? _Queue10_UInt8_5_io_deq_valid : _T_3338 ? _Queue10_UInt8_4_io_deq_valid : _T_3337 ? _Queue10_UInt8_3_io_deq_valid : _T_3336 ? _Queue10_UInt8_2_io_deq_valid : _T_3335 ? _Queue10_UInt8_1_io_deq_valid : _T_3334 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_92 = _remapindex_T_3 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_3 = _GEN_92[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3366 = remapindex_3 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3367 = remapindex_3 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3368 = remapindex_3 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3369 = remapindex_3 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3370 = remapindex_3 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3371 = remapindex_3 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3372 = remapindex_3 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3373 = remapindex_3 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3374 = remapindex_3 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3375 = remapindex_3 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3376 = remapindex_3 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3377 = remapindex_3 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3378 = remapindex_3 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3379 = remapindex_3 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3380 = remapindex_3 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3381 = remapindex_3 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3382 = remapindex_3 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3383 = remapindex_3 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3384 = remapindex_3 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3385 = remapindex_3 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3386 = remapindex_3 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3387 = remapindex_3 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3388 = remapindex_3 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3389 = remapindex_3 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3390 = remapindex_3 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3391 = remapindex_3 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3392 = remapindex_3 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3393 = remapindex_3 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3394 = remapindex_3 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3395 = remapindex_3 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3396 = remapindex_3 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3397 = remapindex_3 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_3 = _T_3397 ? _Queue10_UInt8_31_io_deq_bits : _T_3396 ? _Queue10_UInt8_30_io_deq_bits : _T_3395 ? _Queue10_UInt8_29_io_deq_bits : _T_3394 ? _Queue10_UInt8_28_io_deq_bits : _T_3393 ? _Queue10_UInt8_27_io_deq_bits : _T_3392 ? _Queue10_UInt8_26_io_deq_bits : _T_3391 ? _Queue10_UInt8_25_io_deq_bits : _T_3390 ? _Queue10_UInt8_24_io_deq_bits : _T_3389 ? _Queue10_UInt8_23_io_deq_bits : _T_3388 ? _Queue10_UInt8_22_io_deq_bits : _T_3387 ? _Queue10_UInt8_21_io_deq_bits : _T_3386 ? _Queue10_UInt8_20_io_deq_bits : _T_3385 ? _Queue10_UInt8_19_io_deq_bits : _T_3384 ? _Queue10_UInt8_18_io_deq_bits : _T_3383 ? _Queue10_UInt8_17_io_deq_bits : _T_3382 ? _Queue10_UInt8_16_io_deq_bits : _T_3381 ? _Queue10_UInt8_15_io_deq_bits : _T_3380 ? _Queue10_UInt8_14_io_deq_bits : _T_3379 ? _Queue10_UInt8_13_io_deq_bits : _T_3378 ? _Queue10_UInt8_12_io_deq_bits : _T_3377 ? _Queue10_UInt8_11_io_deq_bits : _T_3376 ? _Queue10_UInt8_10_io_deq_bits : _T_3375 ? _Queue10_UInt8_9_io_deq_bits : _T_3374 ? _Queue10_UInt8_8_io_deq_bits : _T_3373 ? _Queue10_UInt8_7_io_deq_bits : _T_3372 ? _Queue10_UInt8_6_io_deq_bits : _T_3371 ? _Queue10_UInt8_5_io_deq_bits : _T_3370 ? _Queue10_UInt8_4_io_deq_bits : _T_3369 ? _Queue10_UInt8_3_io_deq_bits : _T_3368 ? _Queue10_UInt8_2_io_deq_bits : _T_3367 ? _Queue10_UInt8_1_io_deq_bits : _T_3366 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_3 = _T_3397 ? _Queue10_UInt8_31_io_deq_valid : _T_3396 ? _Queue10_UInt8_30_io_deq_valid : _T_3395 ? _Queue10_UInt8_29_io_deq_valid : _T_3394 ? _Queue10_UInt8_28_io_deq_valid : _T_3393 ? _Queue10_UInt8_27_io_deq_valid : _T_3392 ? _Queue10_UInt8_26_io_deq_valid : _T_3391 ? _Queue10_UInt8_25_io_deq_valid : _T_3390 ? _Queue10_UInt8_24_io_deq_valid : _T_3389 ? _Queue10_UInt8_23_io_deq_valid : _T_3388 ? _Queue10_UInt8_22_io_deq_valid : _T_3387 ? _Queue10_UInt8_21_io_deq_valid : _T_3386 ? _Queue10_UInt8_20_io_deq_valid : _T_3385 ? _Queue10_UInt8_19_io_deq_valid : _T_3384 ? _Queue10_UInt8_18_io_deq_valid : _T_3383 ? _Queue10_UInt8_17_io_deq_valid : _T_3382 ? _Queue10_UInt8_16_io_deq_valid : _T_3381 ? _Queue10_UInt8_15_io_deq_valid : _T_3380 ? _Queue10_UInt8_14_io_deq_valid : _T_3379 ? _Queue10_UInt8_13_io_deq_valid : _T_3378 ? _Queue10_UInt8_12_io_deq_valid : _T_3377 ? _Queue10_UInt8_11_io_deq_valid : _T_3376 ? _Queue10_UInt8_10_io_deq_valid : _T_3375 ? _Queue10_UInt8_9_io_deq_valid : _T_3374 ? _Queue10_UInt8_8_io_deq_valid : _T_3373 ? _Queue10_UInt8_7_io_deq_valid : _T_3372 ? _Queue10_UInt8_6_io_deq_valid : _T_3371 ? _Queue10_UInt8_5_io_deq_valid : _T_3370 ? _Queue10_UInt8_4_io_deq_valid : _T_3369 ? _Queue10_UInt8_3_io_deq_valid : _T_3368 ? _Queue10_UInt8_2_io_deq_valid : _T_3367 ? _Queue10_UInt8_1_io_deq_valid : _T_3366 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_93 = _remapindex_T_4 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_4 = _GEN_93[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3398 = remapindex_4 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3399 = remapindex_4 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3400 = remapindex_4 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3401 = remapindex_4 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3402 = remapindex_4 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3403 = remapindex_4 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3404 = remapindex_4 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3405 = remapindex_4 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3406 = remapindex_4 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3407 = remapindex_4 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3408 = remapindex_4 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3409 = remapindex_4 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3410 = remapindex_4 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3411 = remapindex_4 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3412 = remapindex_4 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3413 = remapindex_4 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3414 = remapindex_4 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3415 = remapindex_4 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3416 = remapindex_4 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3417 = remapindex_4 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3418 = remapindex_4 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3419 = remapindex_4 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3420 = remapindex_4 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3421 = remapindex_4 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3422 = remapindex_4 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3423 = remapindex_4 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3424 = remapindex_4 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3425 = remapindex_4 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3426 = remapindex_4 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3427 = remapindex_4 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3428 = remapindex_4 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3429 = remapindex_4 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_4 = _T_3429 ? _Queue10_UInt8_31_io_deq_bits : _T_3428 ? _Queue10_UInt8_30_io_deq_bits : _T_3427 ? _Queue10_UInt8_29_io_deq_bits : _T_3426 ? _Queue10_UInt8_28_io_deq_bits : _T_3425 ? _Queue10_UInt8_27_io_deq_bits : _T_3424 ? _Queue10_UInt8_26_io_deq_bits : _T_3423 ? _Queue10_UInt8_25_io_deq_bits : _T_3422 ? _Queue10_UInt8_24_io_deq_bits : _T_3421 ? _Queue10_UInt8_23_io_deq_bits : _T_3420 ? _Queue10_UInt8_22_io_deq_bits : _T_3419 ? _Queue10_UInt8_21_io_deq_bits : _T_3418 ? _Queue10_UInt8_20_io_deq_bits : _T_3417 ? _Queue10_UInt8_19_io_deq_bits : _T_3416 ? _Queue10_UInt8_18_io_deq_bits : _T_3415 ? _Queue10_UInt8_17_io_deq_bits : _T_3414 ? _Queue10_UInt8_16_io_deq_bits : _T_3413 ? _Queue10_UInt8_15_io_deq_bits : _T_3412 ? _Queue10_UInt8_14_io_deq_bits : _T_3411 ? _Queue10_UInt8_13_io_deq_bits : _T_3410 ? _Queue10_UInt8_12_io_deq_bits : _T_3409 ? _Queue10_UInt8_11_io_deq_bits : _T_3408 ? _Queue10_UInt8_10_io_deq_bits : _T_3407 ? _Queue10_UInt8_9_io_deq_bits : _T_3406 ? _Queue10_UInt8_8_io_deq_bits : _T_3405 ? _Queue10_UInt8_7_io_deq_bits : _T_3404 ? _Queue10_UInt8_6_io_deq_bits : _T_3403 ? _Queue10_UInt8_5_io_deq_bits : _T_3402 ? _Queue10_UInt8_4_io_deq_bits : _T_3401 ? _Queue10_UInt8_3_io_deq_bits : _T_3400 ? _Queue10_UInt8_2_io_deq_bits : _T_3399 ? _Queue10_UInt8_1_io_deq_bits : _T_3398 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_4 = _T_3429 ? _Queue10_UInt8_31_io_deq_valid : _T_3428 ? _Queue10_UInt8_30_io_deq_valid : _T_3427 ? _Queue10_UInt8_29_io_deq_valid : _T_3426 ? _Queue10_UInt8_28_io_deq_valid : _T_3425 ? _Queue10_UInt8_27_io_deq_valid : _T_3424 ? _Queue10_UInt8_26_io_deq_valid : _T_3423 ? _Queue10_UInt8_25_io_deq_valid : _T_3422 ? _Queue10_UInt8_24_io_deq_valid : _T_3421 ? _Queue10_UInt8_23_io_deq_valid : _T_3420 ? _Queue10_UInt8_22_io_deq_valid : _T_3419 ? _Queue10_UInt8_21_io_deq_valid : _T_3418 ? _Queue10_UInt8_20_io_deq_valid : _T_3417 ? _Queue10_UInt8_19_io_deq_valid : _T_3416 ? _Queue10_UInt8_18_io_deq_valid : _T_3415 ? _Queue10_UInt8_17_io_deq_valid : _T_3414 ? _Queue10_UInt8_16_io_deq_valid : _T_3413 ? _Queue10_UInt8_15_io_deq_valid : _T_3412 ? _Queue10_UInt8_14_io_deq_valid : _T_3411 ? _Queue10_UInt8_13_io_deq_valid : _T_3410 ? _Queue10_UInt8_12_io_deq_valid : _T_3409 ? _Queue10_UInt8_11_io_deq_valid : _T_3408 ? _Queue10_UInt8_10_io_deq_valid : _T_3407 ? _Queue10_UInt8_9_io_deq_valid : _T_3406 ? _Queue10_UInt8_8_io_deq_valid : _T_3405 ? _Queue10_UInt8_7_io_deq_valid : _T_3404 ? _Queue10_UInt8_6_io_deq_valid : _T_3403 ? _Queue10_UInt8_5_io_deq_valid : _T_3402 ? _Queue10_UInt8_4_io_deq_valid : _T_3401 ? _Queue10_UInt8_3_io_deq_valid : _T_3400 ? _Queue10_UInt8_2_io_deq_valid : _T_3399 ? _Queue10_UInt8_1_io_deq_valid : _T_3398 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_94 = _remapindex_T_5 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_5 = _GEN_94[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3430 = remapindex_5 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3431 = remapindex_5 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3432 = remapindex_5 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3433 = remapindex_5 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3434 = remapindex_5 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3435 = remapindex_5 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3436 = remapindex_5 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3437 = remapindex_5 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3438 = remapindex_5 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3439 = remapindex_5 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3440 = remapindex_5 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3441 = remapindex_5 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3442 = remapindex_5 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3443 = remapindex_5 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3444 = remapindex_5 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3445 = remapindex_5 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3446 = remapindex_5 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3447 = remapindex_5 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3448 = remapindex_5 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3449 = remapindex_5 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3450 = remapindex_5 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3451 = remapindex_5 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3452 = remapindex_5 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3453 = remapindex_5 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3454 = remapindex_5 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3455 = remapindex_5 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3456 = remapindex_5 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3457 = remapindex_5 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3458 = remapindex_5 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3459 = remapindex_5 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3460 = remapindex_5 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3461 = remapindex_5 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_5 = _T_3461 ? _Queue10_UInt8_31_io_deq_bits : _T_3460 ? _Queue10_UInt8_30_io_deq_bits : _T_3459 ? _Queue10_UInt8_29_io_deq_bits : _T_3458 ? _Queue10_UInt8_28_io_deq_bits : _T_3457 ? _Queue10_UInt8_27_io_deq_bits : _T_3456 ? _Queue10_UInt8_26_io_deq_bits : _T_3455 ? _Queue10_UInt8_25_io_deq_bits : _T_3454 ? _Queue10_UInt8_24_io_deq_bits : _T_3453 ? _Queue10_UInt8_23_io_deq_bits : _T_3452 ? _Queue10_UInt8_22_io_deq_bits : _T_3451 ? _Queue10_UInt8_21_io_deq_bits : _T_3450 ? _Queue10_UInt8_20_io_deq_bits : _T_3449 ? _Queue10_UInt8_19_io_deq_bits : _T_3448 ? _Queue10_UInt8_18_io_deq_bits : _T_3447 ? _Queue10_UInt8_17_io_deq_bits : _T_3446 ? _Queue10_UInt8_16_io_deq_bits : _T_3445 ? _Queue10_UInt8_15_io_deq_bits : _T_3444 ? _Queue10_UInt8_14_io_deq_bits : _T_3443 ? _Queue10_UInt8_13_io_deq_bits : _T_3442 ? _Queue10_UInt8_12_io_deq_bits : _T_3441 ? _Queue10_UInt8_11_io_deq_bits : _T_3440 ? _Queue10_UInt8_10_io_deq_bits : _T_3439 ? _Queue10_UInt8_9_io_deq_bits : _T_3438 ? _Queue10_UInt8_8_io_deq_bits : _T_3437 ? _Queue10_UInt8_7_io_deq_bits : _T_3436 ? _Queue10_UInt8_6_io_deq_bits : _T_3435 ? _Queue10_UInt8_5_io_deq_bits : _T_3434 ? _Queue10_UInt8_4_io_deq_bits : _T_3433 ? _Queue10_UInt8_3_io_deq_bits : _T_3432 ? _Queue10_UInt8_2_io_deq_bits : _T_3431 ? _Queue10_UInt8_1_io_deq_bits : _T_3430 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_5 = _T_3461 ? _Queue10_UInt8_31_io_deq_valid : _T_3460 ? _Queue10_UInt8_30_io_deq_valid : _T_3459 ? _Queue10_UInt8_29_io_deq_valid : _T_3458 ? _Queue10_UInt8_28_io_deq_valid : _T_3457 ? _Queue10_UInt8_27_io_deq_valid : _T_3456 ? _Queue10_UInt8_26_io_deq_valid : _T_3455 ? _Queue10_UInt8_25_io_deq_valid : _T_3454 ? _Queue10_UInt8_24_io_deq_valid : _T_3453 ? _Queue10_UInt8_23_io_deq_valid : _T_3452 ? _Queue10_UInt8_22_io_deq_valid : _T_3451 ? _Queue10_UInt8_21_io_deq_valid : _T_3450 ? _Queue10_UInt8_20_io_deq_valid : _T_3449 ? _Queue10_UInt8_19_io_deq_valid : _T_3448 ? _Queue10_UInt8_18_io_deq_valid : _T_3447 ? _Queue10_UInt8_17_io_deq_valid : _T_3446 ? _Queue10_UInt8_16_io_deq_valid : _T_3445 ? _Queue10_UInt8_15_io_deq_valid : _T_3444 ? _Queue10_UInt8_14_io_deq_valid : _T_3443 ? _Queue10_UInt8_13_io_deq_valid : _T_3442 ? _Queue10_UInt8_12_io_deq_valid : _T_3441 ? _Queue10_UInt8_11_io_deq_valid : _T_3440 ? _Queue10_UInt8_10_io_deq_valid : _T_3439 ? _Queue10_UInt8_9_io_deq_valid : _T_3438 ? _Queue10_UInt8_8_io_deq_valid : _T_3437 ? _Queue10_UInt8_7_io_deq_valid : _T_3436 ? _Queue10_UInt8_6_io_deq_valid : _T_3435 ? _Queue10_UInt8_5_io_deq_valid : _T_3434 ? _Queue10_UInt8_4_io_deq_valid : _T_3433 ? _Queue10_UInt8_3_io_deq_valid : _T_3432 ? _Queue10_UInt8_2_io_deq_valid : _T_3431 ? _Queue10_UInt8_1_io_deq_valid : _T_3430 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_95 = _remapindex_T_6 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_6 = _GEN_95[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3462 = remapindex_6 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3463 = remapindex_6 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3464 = remapindex_6 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3465 = remapindex_6 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3466 = remapindex_6 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3467 = remapindex_6 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3468 = remapindex_6 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3469 = remapindex_6 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3470 = remapindex_6 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3471 = remapindex_6 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3472 = remapindex_6 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3473 = remapindex_6 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3474 = remapindex_6 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3475 = remapindex_6 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3476 = remapindex_6 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3477 = remapindex_6 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3478 = remapindex_6 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3479 = remapindex_6 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3480 = remapindex_6 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3481 = remapindex_6 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3482 = remapindex_6 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3483 = remapindex_6 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3484 = remapindex_6 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3485 = remapindex_6 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3486 = remapindex_6 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3487 = remapindex_6 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3488 = remapindex_6 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3489 = remapindex_6 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3490 = remapindex_6 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3491 = remapindex_6 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3492 = remapindex_6 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3493 = remapindex_6 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_6 = _T_3493 ? _Queue10_UInt8_31_io_deq_bits : _T_3492 ? _Queue10_UInt8_30_io_deq_bits : _T_3491 ? _Queue10_UInt8_29_io_deq_bits : _T_3490 ? _Queue10_UInt8_28_io_deq_bits : _T_3489 ? _Queue10_UInt8_27_io_deq_bits : _T_3488 ? _Queue10_UInt8_26_io_deq_bits : _T_3487 ? _Queue10_UInt8_25_io_deq_bits : _T_3486 ? _Queue10_UInt8_24_io_deq_bits : _T_3485 ? _Queue10_UInt8_23_io_deq_bits : _T_3484 ? _Queue10_UInt8_22_io_deq_bits : _T_3483 ? _Queue10_UInt8_21_io_deq_bits : _T_3482 ? _Queue10_UInt8_20_io_deq_bits : _T_3481 ? _Queue10_UInt8_19_io_deq_bits : _T_3480 ? _Queue10_UInt8_18_io_deq_bits : _T_3479 ? _Queue10_UInt8_17_io_deq_bits : _T_3478 ? _Queue10_UInt8_16_io_deq_bits : _T_3477 ? _Queue10_UInt8_15_io_deq_bits : _T_3476 ? _Queue10_UInt8_14_io_deq_bits : _T_3475 ? _Queue10_UInt8_13_io_deq_bits : _T_3474 ? _Queue10_UInt8_12_io_deq_bits : _T_3473 ? _Queue10_UInt8_11_io_deq_bits : _T_3472 ? _Queue10_UInt8_10_io_deq_bits : _T_3471 ? _Queue10_UInt8_9_io_deq_bits : _T_3470 ? _Queue10_UInt8_8_io_deq_bits : _T_3469 ? _Queue10_UInt8_7_io_deq_bits : _T_3468 ? _Queue10_UInt8_6_io_deq_bits : _T_3467 ? _Queue10_UInt8_5_io_deq_bits : _T_3466 ? _Queue10_UInt8_4_io_deq_bits : _T_3465 ? _Queue10_UInt8_3_io_deq_bits : _T_3464 ? _Queue10_UInt8_2_io_deq_bits : _T_3463 ? _Queue10_UInt8_1_io_deq_bits : _T_3462 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_6 = _T_3493 ? _Queue10_UInt8_31_io_deq_valid : _T_3492 ? _Queue10_UInt8_30_io_deq_valid : _T_3491 ? _Queue10_UInt8_29_io_deq_valid : _T_3490 ? _Queue10_UInt8_28_io_deq_valid : _T_3489 ? _Queue10_UInt8_27_io_deq_valid : _T_3488 ? _Queue10_UInt8_26_io_deq_valid : _T_3487 ? _Queue10_UInt8_25_io_deq_valid : _T_3486 ? _Queue10_UInt8_24_io_deq_valid : _T_3485 ? _Queue10_UInt8_23_io_deq_valid : _T_3484 ? _Queue10_UInt8_22_io_deq_valid : _T_3483 ? _Queue10_UInt8_21_io_deq_valid : _T_3482 ? _Queue10_UInt8_20_io_deq_valid : _T_3481 ? _Queue10_UInt8_19_io_deq_valid : _T_3480 ? _Queue10_UInt8_18_io_deq_valid : _T_3479 ? _Queue10_UInt8_17_io_deq_valid : _T_3478 ? _Queue10_UInt8_16_io_deq_valid : _T_3477 ? _Queue10_UInt8_15_io_deq_valid : _T_3476 ? _Queue10_UInt8_14_io_deq_valid : _T_3475 ? _Queue10_UInt8_13_io_deq_valid : _T_3474 ? _Queue10_UInt8_12_io_deq_valid : _T_3473 ? _Queue10_UInt8_11_io_deq_valid : _T_3472 ? _Queue10_UInt8_10_io_deq_valid : _T_3471 ? _Queue10_UInt8_9_io_deq_valid : _T_3470 ? _Queue10_UInt8_8_io_deq_valid : _T_3469 ? _Queue10_UInt8_7_io_deq_valid : _T_3468 ? _Queue10_UInt8_6_io_deq_valid : _T_3467 ? _Queue10_UInt8_5_io_deq_valid : _T_3466 ? _Queue10_UInt8_4_io_deq_valid : _T_3465 ? _Queue10_UInt8_3_io_deq_valid : _T_3464 ? _Queue10_UInt8_2_io_deq_valid : _T_3463 ? _Queue10_UInt8_1_io_deq_valid : _T_3462 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_96 = _remapindex_T_7 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_7 = _GEN_96[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3494 = remapindex_7 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3495 = remapindex_7 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3496 = remapindex_7 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3497 = remapindex_7 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3498 = remapindex_7 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3499 = remapindex_7 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3500 = remapindex_7 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3501 = remapindex_7 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3502 = remapindex_7 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3503 = remapindex_7 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3504 = remapindex_7 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3505 = remapindex_7 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3506 = remapindex_7 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3507 = remapindex_7 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3508 = remapindex_7 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3509 = remapindex_7 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3510 = remapindex_7 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3511 = remapindex_7 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3512 = remapindex_7 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3513 = remapindex_7 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3514 = remapindex_7 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3515 = remapindex_7 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3516 = remapindex_7 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3517 = remapindex_7 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3518 = remapindex_7 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3519 = remapindex_7 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3520 = remapindex_7 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3521 = remapindex_7 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3522 = remapindex_7 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3523 = remapindex_7 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3524 = remapindex_7 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3525 = remapindex_7 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_7 = _T_3525 ? _Queue10_UInt8_31_io_deq_bits : _T_3524 ? _Queue10_UInt8_30_io_deq_bits : _T_3523 ? _Queue10_UInt8_29_io_deq_bits : _T_3522 ? _Queue10_UInt8_28_io_deq_bits : _T_3521 ? _Queue10_UInt8_27_io_deq_bits : _T_3520 ? _Queue10_UInt8_26_io_deq_bits : _T_3519 ? _Queue10_UInt8_25_io_deq_bits : _T_3518 ? _Queue10_UInt8_24_io_deq_bits : _T_3517 ? _Queue10_UInt8_23_io_deq_bits : _T_3516 ? _Queue10_UInt8_22_io_deq_bits : _T_3515 ? _Queue10_UInt8_21_io_deq_bits : _T_3514 ? _Queue10_UInt8_20_io_deq_bits : _T_3513 ? _Queue10_UInt8_19_io_deq_bits : _T_3512 ? _Queue10_UInt8_18_io_deq_bits : _T_3511 ? _Queue10_UInt8_17_io_deq_bits : _T_3510 ? _Queue10_UInt8_16_io_deq_bits : _T_3509 ? _Queue10_UInt8_15_io_deq_bits : _T_3508 ? _Queue10_UInt8_14_io_deq_bits : _T_3507 ? _Queue10_UInt8_13_io_deq_bits : _T_3506 ? _Queue10_UInt8_12_io_deq_bits : _T_3505 ? _Queue10_UInt8_11_io_deq_bits : _T_3504 ? _Queue10_UInt8_10_io_deq_bits : _T_3503 ? _Queue10_UInt8_9_io_deq_bits : _T_3502 ? _Queue10_UInt8_8_io_deq_bits : _T_3501 ? _Queue10_UInt8_7_io_deq_bits : _T_3500 ? _Queue10_UInt8_6_io_deq_bits : _T_3499 ? _Queue10_UInt8_5_io_deq_bits : _T_3498 ? _Queue10_UInt8_4_io_deq_bits : _T_3497 ? _Queue10_UInt8_3_io_deq_bits : _T_3496 ? _Queue10_UInt8_2_io_deq_bits : _T_3495 ? _Queue10_UInt8_1_io_deq_bits : _T_3494 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_7 = _T_3525 ? _Queue10_UInt8_31_io_deq_valid : _T_3524 ? _Queue10_UInt8_30_io_deq_valid : _T_3523 ? _Queue10_UInt8_29_io_deq_valid : _T_3522 ? _Queue10_UInt8_28_io_deq_valid : _T_3521 ? _Queue10_UInt8_27_io_deq_valid : _T_3520 ? _Queue10_UInt8_26_io_deq_valid : _T_3519 ? _Queue10_UInt8_25_io_deq_valid : _T_3518 ? _Queue10_UInt8_24_io_deq_valid : _T_3517 ? _Queue10_UInt8_23_io_deq_valid : _T_3516 ? _Queue10_UInt8_22_io_deq_valid : _T_3515 ? _Queue10_UInt8_21_io_deq_valid : _T_3514 ? _Queue10_UInt8_20_io_deq_valid : _T_3513 ? _Queue10_UInt8_19_io_deq_valid : _T_3512 ? _Queue10_UInt8_18_io_deq_valid : _T_3511 ? _Queue10_UInt8_17_io_deq_valid : _T_3510 ? _Queue10_UInt8_16_io_deq_valid : _T_3509 ? _Queue10_UInt8_15_io_deq_valid : _T_3508 ? _Queue10_UInt8_14_io_deq_valid : _T_3507 ? _Queue10_UInt8_13_io_deq_valid : _T_3506 ? _Queue10_UInt8_12_io_deq_valid : _T_3505 ? _Queue10_UInt8_11_io_deq_valid : _T_3504 ? _Queue10_UInt8_10_io_deq_valid : _T_3503 ? _Queue10_UInt8_9_io_deq_valid : _T_3502 ? _Queue10_UInt8_8_io_deq_valid : _T_3501 ? _Queue10_UInt8_7_io_deq_valid : _T_3500 ? _Queue10_UInt8_6_io_deq_valid : _T_3499 ? _Queue10_UInt8_5_io_deq_valid : _T_3498 ? _Queue10_UInt8_4_io_deq_valid : _T_3497 ? _Queue10_UInt8_3_io_deq_valid : _T_3496 ? _Queue10_UInt8_2_io_deq_valid : _T_3495 ? _Queue10_UInt8_1_io_deq_valid : _T_3494 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_97 = _remapindex_T_8 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_8 = _GEN_97[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3526 = remapindex_8 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3527 = remapindex_8 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3528 = remapindex_8 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3529 = remapindex_8 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3530 = remapindex_8 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3531 = remapindex_8 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3532 = remapindex_8 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3533 = remapindex_8 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3534 = remapindex_8 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3535 = remapindex_8 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3536 = remapindex_8 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3537 = remapindex_8 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3538 = remapindex_8 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3539 = remapindex_8 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3540 = remapindex_8 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3541 = remapindex_8 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3542 = remapindex_8 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3543 = remapindex_8 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3544 = remapindex_8 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3545 = remapindex_8 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3546 = remapindex_8 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3547 = remapindex_8 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3548 = remapindex_8 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3549 = remapindex_8 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3550 = remapindex_8 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3551 = remapindex_8 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3552 = remapindex_8 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3553 = remapindex_8 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3554 = remapindex_8 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3555 = remapindex_8 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3556 = remapindex_8 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3557 = remapindex_8 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_8 = _T_3557 ? _Queue10_UInt8_31_io_deq_bits : _T_3556 ? _Queue10_UInt8_30_io_deq_bits : _T_3555 ? _Queue10_UInt8_29_io_deq_bits : _T_3554 ? _Queue10_UInt8_28_io_deq_bits : _T_3553 ? _Queue10_UInt8_27_io_deq_bits : _T_3552 ? _Queue10_UInt8_26_io_deq_bits : _T_3551 ? _Queue10_UInt8_25_io_deq_bits : _T_3550 ? _Queue10_UInt8_24_io_deq_bits : _T_3549 ? _Queue10_UInt8_23_io_deq_bits : _T_3548 ? _Queue10_UInt8_22_io_deq_bits : _T_3547 ? _Queue10_UInt8_21_io_deq_bits : _T_3546 ? _Queue10_UInt8_20_io_deq_bits : _T_3545 ? _Queue10_UInt8_19_io_deq_bits : _T_3544 ? _Queue10_UInt8_18_io_deq_bits : _T_3543 ? _Queue10_UInt8_17_io_deq_bits : _T_3542 ? _Queue10_UInt8_16_io_deq_bits : _T_3541 ? _Queue10_UInt8_15_io_deq_bits : _T_3540 ? _Queue10_UInt8_14_io_deq_bits : _T_3539 ? _Queue10_UInt8_13_io_deq_bits : _T_3538 ? _Queue10_UInt8_12_io_deq_bits : _T_3537 ? _Queue10_UInt8_11_io_deq_bits : _T_3536 ? _Queue10_UInt8_10_io_deq_bits : _T_3535 ? _Queue10_UInt8_9_io_deq_bits : _T_3534 ? _Queue10_UInt8_8_io_deq_bits : _T_3533 ? _Queue10_UInt8_7_io_deq_bits : _T_3532 ? _Queue10_UInt8_6_io_deq_bits : _T_3531 ? _Queue10_UInt8_5_io_deq_bits : _T_3530 ? _Queue10_UInt8_4_io_deq_bits : _T_3529 ? _Queue10_UInt8_3_io_deq_bits : _T_3528 ? _Queue10_UInt8_2_io_deq_bits : _T_3527 ? _Queue10_UInt8_1_io_deq_bits : _T_3526 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_8 = _T_3557 ? _Queue10_UInt8_31_io_deq_valid : _T_3556 ? _Queue10_UInt8_30_io_deq_valid : _T_3555 ? _Queue10_UInt8_29_io_deq_valid : _T_3554 ? _Queue10_UInt8_28_io_deq_valid : _T_3553 ? _Queue10_UInt8_27_io_deq_valid : _T_3552 ? _Queue10_UInt8_26_io_deq_valid : _T_3551 ? _Queue10_UInt8_25_io_deq_valid : _T_3550 ? _Queue10_UInt8_24_io_deq_valid : _T_3549 ? _Queue10_UInt8_23_io_deq_valid : _T_3548 ? _Queue10_UInt8_22_io_deq_valid : _T_3547 ? _Queue10_UInt8_21_io_deq_valid : _T_3546 ? _Queue10_UInt8_20_io_deq_valid : _T_3545 ? _Queue10_UInt8_19_io_deq_valid : _T_3544 ? _Queue10_UInt8_18_io_deq_valid : _T_3543 ? _Queue10_UInt8_17_io_deq_valid : _T_3542 ? _Queue10_UInt8_16_io_deq_valid : _T_3541 ? _Queue10_UInt8_15_io_deq_valid : _T_3540 ? _Queue10_UInt8_14_io_deq_valid : _T_3539 ? _Queue10_UInt8_13_io_deq_valid : _T_3538 ? _Queue10_UInt8_12_io_deq_valid : _T_3537 ? _Queue10_UInt8_11_io_deq_valid : _T_3536 ? _Queue10_UInt8_10_io_deq_valid : _T_3535 ? _Queue10_UInt8_9_io_deq_valid : _T_3534 ? _Queue10_UInt8_8_io_deq_valid : _T_3533 ? _Queue10_UInt8_7_io_deq_valid : _T_3532 ? _Queue10_UInt8_6_io_deq_valid : _T_3531 ? _Queue10_UInt8_5_io_deq_valid : _T_3530 ? _Queue10_UInt8_4_io_deq_valid : _T_3529 ? _Queue10_UInt8_3_io_deq_valid : _T_3528 ? _Queue10_UInt8_2_io_deq_valid : _T_3527 ? _Queue10_UInt8_1_io_deq_valid : _T_3526 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_98 = _remapindex_T_9 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_9 = _GEN_98[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3558 = remapindex_9 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3559 = remapindex_9 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3560 = remapindex_9 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3561 = remapindex_9 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3562 = remapindex_9 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3563 = remapindex_9 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3564 = remapindex_9 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3565 = remapindex_9 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3566 = remapindex_9 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3567 = remapindex_9 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3568 = remapindex_9 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3569 = remapindex_9 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3570 = remapindex_9 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3571 = remapindex_9 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3572 = remapindex_9 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3573 = remapindex_9 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3574 = remapindex_9 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3575 = remapindex_9 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3576 = remapindex_9 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3577 = remapindex_9 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3578 = remapindex_9 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3579 = remapindex_9 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3580 = remapindex_9 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3581 = remapindex_9 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3582 = remapindex_9 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3583 = remapindex_9 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3584 = remapindex_9 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3585 = remapindex_9 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3586 = remapindex_9 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3587 = remapindex_9 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3588 = remapindex_9 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3589 = remapindex_9 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_9 = _T_3589 ? _Queue10_UInt8_31_io_deq_bits : _T_3588 ? _Queue10_UInt8_30_io_deq_bits : _T_3587 ? _Queue10_UInt8_29_io_deq_bits : _T_3586 ? _Queue10_UInt8_28_io_deq_bits : _T_3585 ? _Queue10_UInt8_27_io_deq_bits : _T_3584 ? _Queue10_UInt8_26_io_deq_bits : _T_3583 ? _Queue10_UInt8_25_io_deq_bits : _T_3582 ? _Queue10_UInt8_24_io_deq_bits : _T_3581 ? _Queue10_UInt8_23_io_deq_bits : _T_3580 ? _Queue10_UInt8_22_io_deq_bits : _T_3579 ? _Queue10_UInt8_21_io_deq_bits : _T_3578 ? _Queue10_UInt8_20_io_deq_bits : _T_3577 ? _Queue10_UInt8_19_io_deq_bits : _T_3576 ? _Queue10_UInt8_18_io_deq_bits : _T_3575 ? _Queue10_UInt8_17_io_deq_bits : _T_3574 ? _Queue10_UInt8_16_io_deq_bits : _T_3573 ? _Queue10_UInt8_15_io_deq_bits : _T_3572 ? _Queue10_UInt8_14_io_deq_bits : _T_3571 ? _Queue10_UInt8_13_io_deq_bits : _T_3570 ? _Queue10_UInt8_12_io_deq_bits : _T_3569 ? _Queue10_UInt8_11_io_deq_bits : _T_3568 ? _Queue10_UInt8_10_io_deq_bits : _T_3567 ? _Queue10_UInt8_9_io_deq_bits : _T_3566 ? _Queue10_UInt8_8_io_deq_bits : _T_3565 ? _Queue10_UInt8_7_io_deq_bits : _T_3564 ? _Queue10_UInt8_6_io_deq_bits : _T_3563 ? _Queue10_UInt8_5_io_deq_bits : _T_3562 ? _Queue10_UInt8_4_io_deq_bits : _T_3561 ? _Queue10_UInt8_3_io_deq_bits : _T_3560 ? _Queue10_UInt8_2_io_deq_bits : _T_3559 ? _Queue10_UInt8_1_io_deq_bits : _T_3558 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_9 = _T_3589 ? _Queue10_UInt8_31_io_deq_valid : _T_3588 ? _Queue10_UInt8_30_io_deq_valid : _T_3587 ? _Queue10_UInt8_29_io_deq_valid : _T_3586 ? _Queue10_UInt8_28_io_deq_valid : _T_3585 ? _Queue10_UInt8_27_io_deq_valid : _T_3584 ? _Queue10_UInt8_26_io_deq_valid : _T_3583 ? _Queue10_UInt8_25_io_deq_valid : _T_3582 ? _Queue10_UInt8_24_io_deq_valid : _T_3581 ? _Queue10_UInt8_23_io_deq_valid : _T_3580 ? _Queue10_UInt8_22_io_deq_valid : _T_3579 ? _Queue10_UInt8_21_io_deq_valid : _T_3578 ? _Queue10_UInt8_20_io_deq_valid : _T_3577 ? _Queue10_UInt8_19_io_deq_valid : _T_3576 ? _Queue10_UInt8_18_io_deq_valid : _T_3575 ? _Queue10_UInt8_17_io_deq_valid : _T_3574 ? _Queue10_UInt8_16_io_deq_valid : _T_3573 ? _Queue10_UInt8_15_io_deq_valid : _T_3572 ? _Queue10_UInt8_14_io_deq_valid : _T_3571 ? _Queue10_UInt8_13_io_deq_valid : _T_3570 ? _Queue10_UInt8_12_io_deq_valid : _T_3569 ? _Queue10_UInt8_11_io_deq_valid : _T_3568 ? _Queue10_UInt8_10_io_deq_valid : _T_3567 ? _Queue10_UInt8_9_io_deq_valid : _T_3566 ? _Queue10_UInt8_8_io_deq_valid : _T_3565 ? _Queue10_UInt8_7_io_deq_valid : _T_3564 ? _Queue10_UInt8_6_io_deq_valid : _T_3563 ? _Queue10_UInt8_5_io_deq_valid : _T_3562 ? _Queue10_UInt8_4_io_deq_valid : _T_3561 ? _Queue10_UInt8_3_io_deq_valid : _T_3560 ? _Queue10_UInt8_2_io_deq_valid : _T_3559 ? _Queue10_UInt8_1_io_deq_valid : _T_3558 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_99 = _remapindex_T_10 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_10 = _GEN_99[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3590 = remapindex_10 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3591 = remapindex_10 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3592 = remapindex_10 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3593 = remapindex_10 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3594 = remapindex_10 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3595 = remapindex_10 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3596 = remapindex_10 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3597 = remapindex_10 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3598 = remapindex_10 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3599 = remapindex_10 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3600 = remapindex_10 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3601 = remapindex_10 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3602 = remapindex_10 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3603 = remapindex_10 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3604 = remapindex_10 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3605 = remapindex_10 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3606 = remapindex_10 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3607 = remapindex_10 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3608 = remapindex_10 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3609 = remapindex_10 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3610 = remapindex_10 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3611 = remapindex_10 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3612 = remapindex_10 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3613 = remapindex_10 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3614 = remapindex_10 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3615 = remapindex_10 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3616 = remapindex_10 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3617 = remapindex_10 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3618 = remapindex_10 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3619 = remapindex_10 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3620 = remapindex_10 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3621 = remapindex_10 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_10 = _T_3621 ? _Queue10_UInt8_31_io_deq_bits : _T_3620 ? _Queue10_UInt8_30_io_deq_bits : _T_3619 ? _Queue10_UInt8_29_io_deq_bits : _T_3618 ? _Queue10_UInt8_28_io_deq_bits : _T_3617 ? _Queue10_UInt8_27_io_deq_bits : _T_3616 ? _Queue10_UInt8_26_io_deq_bits : _T_3615 ? _Queue10_UInt8_25_io_deq_bits : _T_3614 ? _Queue10_UInt8_24_io_deq_bits : _T_3613 ? _Queue10_UInt8_23_io_deq_bits : _T_3612 ? _Queue10_UInt8_22_io_deq_bits : _T_3611 ? _Queue10_UInt8_21_io_deq_bits : _T_3610 ? _Queue10_UInt8_20_io_deq_bits : _T_3609 ? _Queue10_UInt8_19_io_deq_bits : _T_3608 ? _Queue10_UInt8_18_io_deq_bits : _T_3607 ? _Queue10_UInt8_17_io_deq_bits : _T_3606 ? _Queue10_UInt8_16_io_deq_bits : _T_3605 ? _Queue10_UInt8_15_io_deq_bits : _T_3604 ? _Queue10_UInt8_14_io_deq_bits : _T_3603 ? _Queue10_UInt8_13_io_deq_bits : _T_3602 ? _Queue10_UInt8_12_io_deq_bits : _T_3601 ? _Queue10_UInt8_11_io_deq_bits : _T_3600 ? _Queue10_UInt8_10_io_deq_bits : _T_3599 ? _Queue10_UInt8_9_io_deq_bits : _T_3598 ? _Queue10_UInt8_8_io_deq_bits : _T_3597 ? _Queue10_UInt8_7_io_deq_bits : _T_3596 ? _Queue10_UInt8_6_io_deq_bits : _T_3595 ? _Queue10_UInt8_5_io_deq_bits : _T_3594 ? _Queue10_UInt8_4_io_deq_bits : _T_3593 ? _Queue10_UInt8_3_io_deq_bits : _T_3592 ? _Queue10_UInt8_2_io_deq_bits : _T_3591 ? _Queue10_UInt8_1_io_deq_bits : _T_3590 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_10 = _T_3621 ? _Queue10_UInt8_31_io_deq_valid : _T_3620 ? _Queue10_UInt8_30_io_deq_valid : _T_3619 ? _Queue10_UInt8_29_io_deq_valid : _T_3618 ? _Queue10_UInt8_28_io_deq_valid : _T_3617 ? _Queue10_UInt8_27_io_deq_valid : _T_3616 ? _Queue10_UInt8_26_io_deq_valid : _T_3615 ? _Queue10_UInt8_25_io_deq_valid : _T_3614 ? _Queue10_UInt8_24_io_deq_valid : _T_3613 ? _Queue10_UInt8_23_io_deq_valid : _T_3612 ? _Queue10_UInt8_22_io_deq_valid : _T_3611 ? _Queue10_UInt8_21_io_deq_valid : _T_3610 ? _Queue10_UInt8_20_io_deq_valid : _T_3609 ? _Queue10_UInt8_19_io_deq_valid : _T_3608 ? _Queue10_UInt8_18_io_deq_valid : _T_3607 ? _Queue10_UInt8_17_io_deq_valid : _T_3606 ? _Queue10_UInt8_16_io_deq_valid : _T_3605 ? _Queue10_UInt8_15_io_deq_valid : _T_3604 ? _Queue10_UInt8_14_io_deq_valid : _T_3603 ? _Queue10_UInt8_13_io_deq_valid : _T_3602 ? _Queue10_UInt8_12_io_deq_valid : _T_3601 ? _Queue10_UInt8_11_io_deq_valid : _T_3600 ? _Queue10_UInt8_10_io_deq_valid : _T_3599 ? _Queue10_UInt8_9_io_deq_valid : _T_3598 ? _Queue10_UInt8_8_io_deq_valid : _T_3597 ? _Queue10_UInt8_7_io_deq_valid : _T_3596 ? _Queue10_UInt8_6_io_deq_valid : _T_3595 ? _Queue10_UInt8_5_io_deq_valid : _T_3594 ? _Queue10_UInt8_4_io_deq_valid : _T_3593 ? _Queue10_UInt8_3_io_deq_valid : _T_3592 ? _Queue10_UInt8_2_io_deq_valid : _T_3591 ? _Queue10_UInt8_1_io_deq_valid : _T_3590 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_100 = _remapindex_T_11 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_11 = _GEN_100[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3622 = remapindex_11 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3623 = remapindex_11 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3624 = remapindex_11 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3625 = remapindex_11 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3626 = remapindex_11 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3627 = remapindex_11 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3628 = remapindex_11 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3629 = remapindex_11 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3630 = remapindex_11 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3631 = remapindex_11 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3632 = remapindex_11 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3633 = remapindex_11 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3634 = remapindex_11 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3635 = remapindex_11 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3636 = remapindex_11 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3637 = remapindex_11 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3638 = remapindex_11 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3639 = remapindex_11 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3640 = remapindex_11 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3641 = remapindex_11 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3642 = remapindex_11 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3643 = remapindex_11 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3644 = remapindex_11 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3645 = remapindex_11 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3646 = remapindex_11 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3647 = remapindex_11 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3648 = remapindex_11 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3649 = remapindex_11 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3650 = remapindex_11 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3651 = remapindex_11 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3652 = remapindex_11 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3653 = remapindex_11 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_11 = _T_3653 ? _Queue10_UInt8_31_io_deq_bits : _T_3652 ? _Queue10_UInt8_30_io_deq_bits : _T_3651 ? _Queue10_UInt8_29_io_deq_bits : _T_3650 ? _Queue10_UInt8_28_io_deq_bits : _T_3649 ? _Queue10_UInt8_27_io_deq_bits : _T_3648 ? _Queue10_UInt8_26_io_deq_bits : _T_3647 ? _Queue10_UInt8_25_io_deq_bits : _T_3646 ? _Queue10_UInt8_24_io_deq_bits : _T_3645 ? _Queue10_UInt8_23_io_deq_bits : _T_3644 ? _Queue10_UInt8_22_io_deq_bits : _T_3643 ? _Queue10_UInt8_21_io_deq_bits : _T_3642 ? _Queue10_UInt8_20_io_deq_bits : _T_3641 ? _Queue10_UInt8_19_io_deq_bits : _T_3640 ? _Queue10_UInt8_18_io_deq_bits : _T_3639 ? _Queue10_UInt8_17_io_deq_bits : _T_3638 ? _Queue10_UInt8_16_io_deq_bits : _T_3637 ? _Queue10_UInt8_15_io_deq_bits : _T_3636 ? _Queue10_UInt8_14_io_deq_bits : _T_3635 ? _Queue10_UInt8_13_io_deq_bits : _T_3634 ? _Queue10_UInt8_12_io_deq_bits : _T_3633 ? _Queue10_UInt8_11_io_deq_bits : _T_3632 ? _Queue10_UInt8_10_io_deq_bits : _T_3631 ? _Queue10_UInt8_9_io_deq_bits : _T_3630 ? _Queue10_UInt8_8_io_deq_bits : _T_3629 ? _Queue10_UInt8_7_io_deq_bits : _T_3628 ? _Queue10_UInt8_6_io_deq_bits : _T_3627 ? _Queue10_UInt8_5_io_deq_bits : _T_3626 ? _Queue10_UInt8_4_io_deq_bits : _T_3625 ? _Queue10_UInt8_3_io_deq_bits : _T_3624 ? _Queue10_UInt8_2_io_deq_bits : _T_3623 ? _Queue10_UInt8_1_io_deq_bits : _T_3622 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_11 = _T_3653 ? _Queue10_UInt8_31_io_deq_valid : _T_3652 ? _Queue10_UInt8_30_io_deq_valid : _T_3651 ? _Queue10_UInt8_29_io_deq_valid : _T_3650 ? _Queue10_UInt8_28_io_deq_valid : _T_3649 ? _Queue10_UInt8_27_io_deq_valid : _T_3648 ? _Queue10_UInt8_26_io_deq_valid : _T_3647 ? _Queue10_UInt8_25_io_deq_valid : _T_3646 ? _Queue10_UInt8_24_io_deq_valid : _T_3645 ? _Queue10_UInt8_23_io_deq_valid : _T_3644 ? _Queue10_UInt8_22_io_deq_valid : _T_3643 ? _Queue10_UInt8_21_io_deq_valid : _T_3642 ? _Queue10_UInt8_20_io_deq_valid : _T_3641 ? _Queue10_UInt8_19_io_deq_valid : _T_3640 ? _Queue10_UInt8_18_io_deq_valid : _T_3639 ? _Queue10_UInt8_17_io_deq_valid : _T_3638 ? _Queue10_UInt8_16_io_deq_valid : _T_3637 ? _Queue10_UInt8_15_io_deq_valid : _T_3636 ? _Queue10_UInt8_14_io_deq_valid : _T_3635 ? _Queue10_UInt8_13_io_deq_valid : _T_3634 ? _Queue10_UInt8_12_io_deq_valid : _T_3633 ? _Queue10_UInt8_11_io_deq_valid : _T_3632 ? _Queue10_UInt8_10_io_deq_valid : _T_3631 ? _Queue10_UInt8_9_io_deq_valid : _T_3630 ? _Queue10_UInt8_8_io_deq_valid : _T_3629 ? _Queue10_UInt8_7_io_deq_valid : _T_3628 ? _Queue10_UInt8_6_io_deq_valid : _T_3627 ? _Queue10_UInt8_5_io_deq_valid : _T_3626 ? _Queue10_UInt8_4_io_deq_valid : _T_3625 ? _Queue10_UInt8_3_io_deq_valid : _T_3624 ? _Queue10_UInt8_2_io_deq_valid : _T_3623 ? _Queue10_UInt8_1_io_deq_valid : _T_3622 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_101 = _remapindex_T_12 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_12 = _GEN_101[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3654 = remapindex_12 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3655 = remapindex_12 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3656 = remapindex_12 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3657 = remapindex_12 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3658 = remapindex_12 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3659 = remapindex_12 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3660 = remapindex_12 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3661 = remapindex_12 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3662 = remapindex_12 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3663 = remapindex_12 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3664 = remapindex_12 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3665 = remapindex_12 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3666 = remapindex_12 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3667 = remapindex_12 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3668 = remapindex_12 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3669 = remapindex_12 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3670 = remapindex_12 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3671 = remapindex_12 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3672 = remapindex_12 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3673 = remapindex_12 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3674 = remapindex_12 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3675 = remapindex_12 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3676 = remapindex_12 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3677 = remapindex_12 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3678 = remapindex_12 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3679 = remapindex_12 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3680 = remapindex_12 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3681 = remapindex_12 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3682 = remapindex_12 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3683 = remapindex_12 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3684 = remapindex_12 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3685 = remapindex_12 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_12 = _T_3685 ? _Queue10_UInt8_31_io_deq_bits : _T_3684 ? _Queue10_UInt8_30_io_deq_bits : _T_3683 ? _Queue10_UInt8_29_io_deq_bits : _T_3682 ? _Queue10_UInt8_28_io_deq_bits : _T_3681 ? _Queue10_UInt8_27_io_deq_bits : _T_3680 ? _Queue10_UInt8_26_io_deq_bits : _T_3679 ? _Queue10_UInt8_25_io_deq_bits : _T_3678 ? _Queue10_UInt8_24_io_deq_bits : _T_3677 ? _Queue10_UInt8_23_io_deq_bits : _T_3676 ? _Queue10_UInt8_22_io_deq_bits : _T_3675 ? _Queue10_UInt8_21_io_deq_bits : _T_3674 ? _Queue10_UInt8_20_io_deq_bits : _T_3673 ? _Queue10_UInt8_19_io_deq_bits : _T_3672 ? _Queue10_UInt8_18_io_deq_bits : _T_3671 ? _Queue10_UInt8_17_io_deq_bits : _T_3670 ? _Queue10_UInt8_16_io_deq_bits : _T_3669 ? _Queue10_UInt8_15_io_deq_bits : _T_3668 ? _Queue10_UInt8_14_io_deq_bits : _T_3667 ? _Queue10_UInt8_13_io_deq_bits : _T_3666 ? _Queue10_UInt8_12_io_deq_bits : _T_3665 ? _Queue10_UInt8_11_io_deq_bits : _T_3664 ? _Queue10_UInt8_10_io_deq_bits : _T_3663 ? _Queue10_UInt8_9_io_deq_bits : _T_3662 ? _Queue10_UInt8_8_io_deq_bits : _T_3661 ? _Queue10_UInt8_7_io_deq_bits : _T_3660 ? _Queue10_UInt8_6_io_deq_bits : _T_3659 ? _Queue10_UInt8_5_io_deq_bits : _T_3658 ? _Queue10_UInt8_4_io_deq_bits : _T_3657 ? _Queue10_UInt8_3_io_deq_bits : _T_3656 ? _Queue10_UInt8_2_io_deq_bits : _T_3655 ? _Queue10_UInt8_1_io_deq_bits : _T_3654 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_12 = _T_3685 ? _Queue10_UInt8_31_io_deq_valid : _T_3684 ? _Queue10_UInt8_30_io_deq_valid : _T_3683 ? _Queue10_UInt8_29_io_deq_valid : _T_3682 ? _Queue10_UInt8_28_io_deq_valid : _T_3681 ? _Queue10_UInt8_27_io_deq_valid : _T_3680 ? _Queue10_UInt8_26_io_deq_valid : _T_3679 ? _Queue10_UInt8_25_io_deq_valid : _T_3678 ? _Queue10_UInt8_24_io_deq_valid : _T_3677 ? _Queue10_UInt8_23_io_deq_valid : _T_3676 ? _Queue10_UInt8_22_io_deq_valid : _T_3675 ? _Queue10_UInt8_21_io_deq_valid : _T_3674 ? _Queue10_UInt8_20_io_deq_valid : _T_3673 ? _Queue10_UInt8_19_io_deq_valid : _T_3672 ? _Queue10_UInt8_18_io_deq_valid : _T_3671 ? _Queue10_UInt8_17_io_deq_valid : _T_3670 ? _Queue10_UInt8_16_io_deq_valid : _T_3669 ? _Queue10_UInt8_15_io_deq_valid : _T_3668 ? _Queue10_UInt8_14_io_deq_valid : _T_3667 ? _Queue10_UInt8_13_io_deq_valid : _T_3666 ? _Queue10_UInt8_12_io_deq_valid : _T_3665 ? _Queue10_UInt8_11_io_deq_valid : _T_3664 ? _Queue10_UInt8_10_io_deq_valid : _T_3663 ? _Queue10_UInt8_9_io_deq_valid : _T_3662 ? _Queue10_UInt8_8_io_deq_valid : _T_3661 ? _Queue10_UInt8_7_io_deq_valid : _T_3660 ? _Queue10_UInt8_6_io_deq_valid : _T_3659 ? _Queue10_UInt8_5_io_deq_valid : _T_3658 ? _Queue10_UInt8_4_io_deq_valid : _T_3657 ? _Queue10_UInt8_3_io_deq_valid : _T_3656 ? _Queue10_UInt8_2_io_deq_valid : _T_3655 ? _Queue10_UInt8_1_io_deq_valid : _T_3654 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_102 = _remapindex_T_13 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_13 = _GEN_102[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3686 = remapindex_13 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3687 = remapindex_13 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3688 = remapindex_13 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3689 = remapindex_13 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3690 = remapindex_13 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3691 = remapindex_13 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3692 = remapindex_13 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3693 = remapindex_13 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3694 = remapindex_13 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3695 = remapindex_13 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3696 = remapindex_13 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3697 = remapindex_13 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3698 = remapindex_13 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3699 = remapindex_13 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3700 = remapindex_13 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3701 = remapindex_13 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3702 = remapindex_13 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3703 = remapindex_13 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3704 = remapindex_13 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3705 = remapindex_13 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3706 = remapindex_13 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3707 = remapindex_13 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3708 = remapindex_13 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3709 = remapindex_13 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3710 = remapindex_13 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3711 = remapindex_13 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3712 = remapindex_13 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3713 = remapindex_13 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3714 = remapindex_13 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3715 = remapindex_13 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3716 = remapindex_13 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3717 = remapindex_13 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_13 = _T_3717 ? _Queue10_UInt8_31_io_deq_bits : _T_3716 ? _Queue10_UInt8_30_io_deq_bits : _T_3715 ? _Queue10_UInt8_29_io_deq_bits : _T_3714 ? _Queue10_UInt8_28_io_deq_bits : _T_3713 ? _Queue10_UInt8_27_io_deq_bits : _T_3712 ? _Queue10_UInt8_26_io_deq_bits : _T_3711 ? _Queue10_UInt8_25_io_deq_bits : _T_3710 ? _Queue10_UInt8_24_io_deq_bits : _T_3709 ? _Queue10_UInt8_23_io_deq_bits : _T_3708 ? _Queue10_UInt8_22_io_deq_bits : _T_3707 ? _Queue10_UInt8_21_io_deq_bits : _T_3706 ? _Queue10_UInt8_20_io_deq_bits : _T_3705 ? _Queue10_UInt8_19_io_deq_bits : _T_3704 ? _Queue10_UInt8_18_io_deq_bits : _T_3703 ? _Queue10_UInt8_17_io_deq_bits : _T_3702 ? _Queue10_UInt8_16_io_deq_bits : _T_3701 ? _Queue10_UInt8_15_io_deq_bits : _T_3700 ? _Queue10_UInt8_14_io_deq_bits : _T_3699 ? _Queue10_UInt8_13_io_deq_bits : _T_3698 ? _Queue10_UInt8_12_io_deq_bits : _T_3697 ? _Queue10_UInt8_11_io_deq_bits : _T_3696 ? _Queue10_UInt8_10_io_deq_bits : _T_3695 ? _Queue10_UInt8_9_io_deq_bits : _T_3694 ? _Queue10_UInt8_8_io_deq_bits : _T_3693 ? _Queue10_UInt8_7_io_deq_bits : _T_3692 ? _Queue10_UInt8_6_io_deq_bits : _T_3691 ? _Queue10_UInt8_5_io_deq_bits : _T_3690 ? _Queue10_UInt8_4_io_deq_bits : _T_3689 ? _Queue10_UInt8_3_io_deq_bits : _T_3688 ? _Queue10_UInt8_2_io_deq_bits : _T_3687 ? _Queue10_UInt8_1_io_deq_bits : _T_3686 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_13 = _T_3717 ? _Queue10_UInt8_31_io_deq_valid : _T_3716 ? _Queue10_UInt8_30_io_deq_valid : _T_3715 ? _Queue10_UInt8_29_io_deq_valid : _T_3714 ? _Queue10_UInt8_28_io_deq_valid : _T_3713 ? _Queue10_UInt8_27_io_deq_valid : _T_3712 ? _Queue10_UInt8_26_io_deq_valid : _T_3711 ? _Queue10_UInt8_25_io_deq_valid : _T_3710 ? _Queue10_UInt8_24_io_deq_valid : _T_3709 ? _Queue10_UInt8_23_io_deq_valid : _T_3708 ? _Queue10_UInt8_22_io_deq_valid : _T_3707 ? _Queue10_UInt8_21_io_deq_valid : _T_3706 ? _Queue10_UInt8_20_io_deq_valid : _T_3705 ? _Queue10_UInt8_19_io_deq_valid : _T_3704 ? _Queue10_UInt8_18_io_deq_valid : _T_3703 ? _Queue10_UInt8_17_io_deq_valid : _T_3702 ? _Queue10_UInt8_16_io_deq_valid : _T_3701 ? _Queue10_UInt8_15_io_deq_valid : _T_3700 ? _Queue10_UInt8_14_io_deq_valid : _T_3699 ? _Queue10_UInt8_13_io_deq_valid : _T_3698 ? _Queue10_UInt8_12_io_deq_valid : _T_3697 ? _Queue10_UInt8_11_io_deq_valid : _T_3696 ? _Queue10_UInt8_10_io_deq_valid : _T_3695 ? _Queue10_UInt8_9_io_deq_valid : _T_3694 ? _Queue10_UInt8_8_io_deq_valid : _T_3693 ? _Queue10_UInt8_7_io_deq_valid : _T_3692 ? _Queue10_UInt8_6_io_deq_valid : _T_3691 ? _Queue10_UInt8_5_io_deq_valid : _T_3690 ? _Queue10_UInt8_4_io_deq_valid : _T_3689 ? _Queue10_UInt8_3_io_deq_valid : _T_3688 ? _Queue10_UInt8_2_io_deq_valid : _T_3687 ? _Queue10_UInt8_1_io_deq_valid : _T_3686 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_103 = _remapindex_T_14 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_14 = _GEN_103[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3718 = remapindex_14 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3719 = remapindex_14 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3720 = remapindex_14 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3721 = remapindex_14 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3722 = remapindex_14 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3723 = remapindex_14 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3724 = remapindex_14 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3725 = remapindex_14 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3726 = remapindex_14 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3727 = remapindex_14 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3728 = remapindex_14 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3729 = remapindex_14 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3730 = remapindex_14 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3731 = remapindex_14 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3732 = remapindex_14 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3733 = remapindex_14 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3734 = remapindex_14 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3735 = remapindex_14 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3736 = remapindex_14 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3737 = remapindex_14 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3738 = remapindex_14 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3739 = remapindex_14 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3740 = remapindex_14 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3741 = remapindex_14 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3742 = remapindex_14 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3743 = remapindex_14 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3744 = remapindex_14 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3745 = remapindex_14 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3746 = remapindex_14 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3747 = remapindex_14 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3748 = remapindex_14 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3749 = remapindex_14 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_14 = _T_3749 ? _Queue10_UInt8_31_io_deq_bits : _T_3748 ? _Queue10_UInt8_30_io_deq_bits : _T_3747 ? _Queue10_UInt8_29_io_deq_bits : _T_3746 ? _Queue10_UInt8_28_io_deq_bits : _T_3745 ? _Queue10_UInt8_27_io_deq_bits : _T_3744 ? _Queue10_UInt8_26_io_deq_bits : _T_3743 ? _Queue10_UInt8_25_io_deq_bits : _T_3742 ? _Queue10_UInt8_24_io_deq_bits : _T_3741 ? _Queue10_UInt8_23_io_deq_bits : _T_3740 ? _Queue10_UInt8_22_io_deq_bits : _T_3739 ? _Queue10_UInt8_21_io_deq_bits : _T_3738 ? _Queue10_UInt8_20_io_deq_bits : _T_3737 ? _Queue10_UInt8_19_io_deq_bits : _T_3736 ? _Queue10_UInt8_18_io_deq_bits : _T_3735 ? _Queue10_UInt8_17_io_deq_bits : _T_3734 ? _Queue10_UInt8_16_io_deq_bits : _T_3733 ? _Queue10_UInt8_15_io_deq_bits : _T_3732 ? _Queue10_UInt8_14_io_deq_bits : _T_3731 ? _Queue10_UInt8_13_io_deq_bits : _T_3730 ? _Queue10_UInt8_12_io_deq_bits : _T_3729 ? _Queue10_UInt8_11_io_deq_bits : _T_3728 ? _Queue10_UInt8_10_io_deq_bits : _T_3727 ? _Queue10_UInt8_9_io_deq_bits : _T_3726 ? _Queue10_UInt8_8_io_deq_bits : _T_3725 ? _Queue10_UInt8_7_io_deq_bits : _T_3724 ? _Queue10_UInt8_6_io_deq_bits : _T_3723 ? _Queue10_UInt8_5_io_deq_bits : _T_3722 ? _Queue10_UInt8_4_io_deq_bits : _T_3721 ? _Queue10_UInt8_3_io_deq_bits : _T_3720 ? _Queue10_UInt8_2_io_deq_bits : _T_3719 ? _Queue10_UInt8_1_io_deq_bits : _T_3718 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_14 = _T_3749 ? _Queue10_UInt8_31_io_deq_valid : _T_3748 ? _Queue10_UInt8_30_io_deq_valid : _T_3747 ? _Queue10_UInt8_29_io_deq_valid : _T_3746 ? _Queue10_UInt8_28_io_deq_valid : _T_3745 ? _Queue10_UInt8_27_io_deq_valid : _T_3744 ? _Queue10_UInt8_26_io_deq_valid : _T_3743 ? _Queue10_UInt8_25_io_deq_valid : _T_3742 ? _Queue10_UInt8_24_io_deq_valid : _T_3741 ? _Queue10_UInt8_23_io_deq_valid : _T_3740 ? _Queue10_UInt8_22_io_deq_valid : _T_3739 ? _Queue10_UInt8_21_io_deq_valid : _T_3738 ? _Queue10_UInt8_20_io_deq_valid : _T_3737 ? _Queue10_UInt8_19_io_deq_valid : _T_3736 ? _Queue10_UInt8_18_io_deq_valid : _T_3735 ? _Queue10_UInt8_17_io_deq_valid : _T_3734 ? _Queue10_UInt8_16_io_deq_valid : _T_3733 ? _Queue10_UInt8_15_io_deq_valid : _T_3732 ? _Queue10_UInt8_14_io_deq_valid : _T_3731 ? _Queue10_UInt8_13_io_deq_valid : _T_3730 ? _Queue10_UInt8_12_io_deq_valid : _T_3729 ? _Queue10_UInt8_11_io_deq_valid : _T_3728 ? _Queue10_UInt8_10_io_deq_valid : _T_3727 ? _Queue10_UInt8_9_io_deq_valid : _T_3726 ? _Queue10_UInt8_8_io_deq_valid : _T_3725 ? _Queue10_UInt8_7_io_deq_valid : _T_3724 ? _Queue10_UInt8_6_io_deq_valid : _T_3723 ? _Queue10_UInt8_5_io_deq_valid : _T_3722 ? _Queue10_UInt8_4_io_deq_valid : _T_3721 ? _Queue10_UInt8_3_io_deq_valid : _T_3720 ? _Queue10_UInt8_2_io_deq_valid : _T_3719 ? _Queue10_UInt8_1_io_deq_valid : _T_3718 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_104 = _remapindex_T_15 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_15 = _GEN_104[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3750 = remapindex_15 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3751 = remapindex_15 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3752 = remapindex_15 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3753 = remapindex_15 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3754 = remapindex_15 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3755 = remapindex_15 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3756 = remapindex_15 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3757 = remapindex_15 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3758 = remapindex_15 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3759 = remapindex_15 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3760 = remapindex_15 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3761 = remapindex_15 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3762 = remapindex_15 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3763 = remapindex_15 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3764 = remapindex_15 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3765 = remapindex_15 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3766 = remapindex_15 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3767 = remapindex_15 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3768 = remapindex_15 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3769 = remapindex_15 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3770 = remapindex_15 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3771 = remapindex_15 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3772 = remapindex_15 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3773 = remapindex_15 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3774 = remapindex_15 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3775 = remapindex_15 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3776 = remapindex_15 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3777 = remapindex_15 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3778 = remapindex_15 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3779 = remapindex_15 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3780 = remapindex_15 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3781 = remapindex_15 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_15 = _T_3781 ? _Queue10_UInt8_31_io_deq_bits : _T_3780 ? _Queue10_UInt8_30_io_deq_bits : _T_3779 ? _Queue10_UInt8_29_io_deq_bits : _T_3778 ? _Queue10_UInt8_28_io_deq_bits : _T_3777 ? _Queue10_UInt8_27_io_deq_bits : _T_3776 ? _Queue10_UInt8_26_io_deq_bits : _T_3775 ? _Queue10_UInt8_25_io_deq_bits : _T_3774 ? _Queue10_UInt8_24_io_deq_bits : _T_3773 ? _Queue10_UInt8_23_io_deq_bits : _T_3772 ? _Queue10_UInt8_22_io_deq_bits : _T_3771 ? _Queue10_UInt8_21_io_deq_bits : _T_3770 ? _Queue10_UInt8_20_io_deq_bits : _T_3769 ? _Queue10_UInt8_19_io_deq_bits : _T_3768 ? _Queue10_UInt8_18_io_deq_bits : _T_3767 ? _Queue10_UInt8_17_io_deq_bits : _T_3766 ? _Queue10_UInt8_16_io_deq_bits : _T_3765 ? _Queue10_UInt8_15_io_deq_bits : _T_3764 ? _Queue10_UInt8_14_io_deq_bits : _T_3763 ? _Queue10_UInt8_13_io_deq_bits : _T_3762 ? _Queue10_UInt8_12_io_deq_bits : _T_3761 ? _Queue10_UInt8_11_io_deq_bits : _T_3760 ? _Queue10_UInt8_10_io_deq_bits : _T_3759 ? _Queue10_UInt8_9_io_deq_bits : _T_3758 ? _Queue10_UInt8_8_io_deq_bits : _T_3757 ? _Queue10_UInt8_7_io_deq_bits : _T_3756 ? _Queue10_UInt8_6_io_deq_bits : _T_3755 ? _Queue10_UInt8_5_io_deq_bits : _T_3754 ? _Queue10_UInt8_4_io_deq_bits : _T_3753 ? _Queue10_UInt8_3_io_deq_bits : _T_3752 ? _Queue10_UInt8_2_io_deq_bits : _T_3751 ? _Queue10_UInt8_1_io_deq_bits : _T_3750 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_15 = _T_3781 ? _Queue10_UInt8_31_io_deq_valid : _T_3780 ? _Queue10_UInt8_30_io_deq_valid : _T_3779 ? _Queue10_UInt8_29_io_deq_valid : _T_3778 ? _Queue10_UInt8_28_io_deq_valid : _T_3777 ? _Queue10_UInt8_27_io_deq_valid : _T_3776 ? _Queue10_UInt8_26_io_deq_valid : _T_3775 ? _Queue10_UInt8_25_io_deq_valid : _T_3774 ? _Queue10_UInt8_24_io_deq_valid : _T_3773 ? _Queue10_UInt8_23_io_deq_valid : _T_3772 ? _Queue10_UInt8_22_io_deq_valid : _T_3771 ? _Queue10_UInt8_21_io_deq_valid : _T_3770 ? _Queue10_UInt8_20_io_deq_valid : _T_3769 ? _Queue10_UInt8_19_io_deq_valid : _T_3768 ? _Queue10_UInt8_18_io_deq_valid : _T_3767 ? _Queue10_UInt8_17_io_deq_valid : _T_3766 ? _Queue10_UInt8_16_io_deq_valid : _T_3765 ? _Queue10_UInt8_15_io_deq_valid : _T_3764 ? _Queue10_UInt8_14_io_deq_valid : _T_3763 ? _Queue10_UInt8_13_io_deq_valid : _T_3762 ? _Queue10_UInt8_12_io_deq_valid : _T_3761 ? _Queue10_UInt8_11_io_deq_valid : _T_3760 ? _Queue10_UInt8_10_io_deq_valid : _T_3759 ? _Queue10_UInt8_9_io_deq_valid : _T_3758 ? _Queue10_UInt8_8_io_deq_valid : _T_3757 ? _Queue10_UInt8_7_io_deq_valid : _T_3756 ? _Queue10_UInt8_6_io_deq_valid : _T_3755 ? _Queue10_UInt8_5_io_deq_valid : _T_3754 ? _Queue10_UInt8_4_io_deq_valid : _T_3753 ? _Queue10_UInt8_3_io_deq_valid : _T_3752 ? _Queue10_UInt8_2_io_deq_valid : _T_3751 ? _Queue10_UInt8_1_io_deq_valid : _T_3750 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_105 = _remapindex_T_16 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_16 = _GEN_105[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3782 = remapindex_16 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3783 = remapindex_16 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3784 = remapindex_16 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3785 = remapindex_16 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3786 = remapindex_16 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3787 = remapindex_16 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3788 = remapindex_16 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3789 = remapindex_16 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3790 = remapindex_16 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3791 = remapindex_16 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3792 = remapindex_16 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3793 = remapindex_16 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3794 = remapindex_16 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3795 = remapindex_16 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3796 = remapindex_16 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3797 = remapindex_16 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3798 = remapindex_16 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3799 = remapindex_16 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3800 = remapindex_16 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3801 = remapindex_16 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3802 = remapindex_16 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3803 = remapindex_16 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3804 = remapindex_16 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3805 = remapindex_16 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3806 = remapindex_16 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3807 = remapindex_16 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3808 = remapindex_16 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3809 = remapindex_16 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3810 = remapindex_16 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3811 = remapindex_16 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3812 = remapindex_16 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3813 = remapindex_16 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_16 = _T_3813 ? _Queue10_UInt8_31_io_deq_bits : _T_3812 ? _Queue10_UInt8_30_io_deq_bits : _T_3811 ? _Queue10_UInt8_29_io_deq_bits : _T_3810 ? _Queue10_UInt8_28_io_deq_bits : _T_3809 ? _Queue10_UInt8_27_io_deq_bits : _T_3808 ? _Queue10_UInt8_26_io_deq_bits : _T_3807 ? _Queue10_UInt8_25_io_deq_bits : _T_3806 ? _Queue10_UInt8_24_io_deq_bits : _T_3805 ? _Queue10_UInt8_23_io_deq_bits : _T_3804 ? _Queue10_UInt8_22_io_deq_bits : _T_3803 ? _Queue10_UInt8_21_io_deq_bits : _T_3802 ? _Queue10_UInt8_20_io_deq_bits : _T_3801 ? _Queue10_UInt8_19_io_deq_bits : _T_3800 ? _Queue10_UInt8_18_io_deq_bits : _T_3799 ? _Queue10_UInt8_17_io_deq_bits : _T_3798 ? _Queue10_UInt8_16_io_deq_bits : _T_3797 ? _Queue10_UInt8_15_io_deq_bits : _T_3796 ? _Queue10_UInt8_14_io_deq_bits : _T_3795 ? _Queue10_UInt8_13_io_deq_bits : _T_3794 ? _Queue10_UInt8_12_io_deq_bits : _T_3793 ? _Queue10_UInt8_11_io_deq_bits : _T_3792 ? _Queue10_UInt8_10_io_deq_bits : _T_3791 ? _Queue10_UInt8_9_io_deq_bits : _T_3790 ? _Queue10_UInt8_8_io_deq_bits : _T_3789 ? _Queue10_UInt8_7_io_deq_bits : _T_3788 ? _Queue10_UInt8_6_io_deq_bits : _T_3787 ? _Queue10_UInt8_5_io_deq_bits : _T_3786 ? _Queue10_UInt8_4_io_deq_bits : _T_3785 ? _Queue10_UInt8_3_io_deq_bits : _T_3784 ? _Queue10_UInt8_2_io_deq_bits : _T_3783 ? _Queue10_UInt8_1_io_deq_bits : _T_3782 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_16 = _T_3813 ? _Queue10_UInt8_31_io_deq_valid : _T_3812 ? _Queue10_UInt8_30_io_deq_valid : _T_3811 ? _Queue10_UInt8_29_io_deq_valid : _T_3810 ? _Queue10_UInt8_28_io_deq_valid : _T_3809 ? _Queue10_UInt8_27_io_deq_valid : _T_3808 ? _Queue10_UInt8_26_io_deq_valid : _T_3807 ? _Queue10_UInt8_25_io_deq_valid : _T_3806 ? _Queue10_UInt8_24_io_deq_valid : _T_3805 ? _Queue10_UInt8_23_io_deq_valid : _T_3804 ? _Queue10_UInt8_22_io_deq_valid : _T_3803 ? _Queue10_UInt8_21_io_deq_valid : _T_3802 ? _Queue10_UInt8_20_io_deq_valid : _T_3801 ? _Queue10_UInt8_19_io_deq_valid : _T_3800 ? _Queue10_UInt8_18_io_deq_valid : _T_3799 ? _Queue10_UInt8_17_io_deq_valid : _T_3798 ? _Queue10_UInt8_16_io_deq_valid : _T_3797 ? _Queue10_UInt8_15_io_deq_valid : _T_3796 ? _Queue10_UInt8_14_io_deq_valid : _T_3795 ? _Queue10_UInt8_13_io_deq_valid : _T_3794 ? _Queue10_UInt8_12_io_deq_valid : _T_3793 ? _Queue10_UInt8_11_io_deq_valid : _T_3792 ? _Queue10_UInt8_10_io_deq_valid : _T_3791 ? _Queue10_UInt8_9_io_deq_valid : _T_3790 ? _Queue10_UInt8_8_io_deq_valid : _T_3789 ? _Queue10_UInt8_7_io_deq_valid : _T_3788 ? _Queue10_UInt8_6_io_deq_valid : _T_3787 ? _Queue10_UInt8_5_io_deq_valid : _T_3786 ? _Queue10_UInt8_4_io_deq_valid : _T_3785 ? _Queue10_UInt8_3_io_deq_valid : _T_3784 ? _Queue10_UInt8_2_io_deq_valid : _T_3783 ? _Queue10_UInt8_1_io_deq_valid : _T_3782 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_106 = _remapindex_T_17 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_17 = _GEN_106[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3814 = remapindex_17 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3815 = remapindex_17 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3816 = remapindex_17 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3817 = remapindex_17 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3818 = remapindex_17 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3819 = remapindex_17 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3820 = remapindex_17 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3821 = remapindex_17 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3822 = remapindex_17 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3823 = remapindex_17 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3824 = remapindex_17 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3825 = remapindex_17 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3826 = remapindex_17 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3827 = remapindex_17 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3828 = remapindex_17 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3829 = remapindex_17 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3830 = remapindex_17 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3831 = remapindex_17 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3832 = remapindex_17 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3833 = remapindex_17 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3834 = remapindex_17 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3835 = remapindex_17 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3836 = remapindex_17 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3837 = remapindex_17 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3838 = remapindex_17 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3839 = remapindex_17 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3840 = remapindex_17 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3841 = remapindex_17 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3842 = remapindex_17 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3843 = remapindex_17 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3844 = remapindex_17 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3845 = remapindex_17 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_17 = _T_3845 ? _Queue10_UInt8_31_io_deq_bits : _T_3844 ? _Queue10_UInt8_30_io_deq_bits : _T_3843 ? _Queue10_UInt8_29_io_deq_bits : _T_3842 ? _Queue10_UInt8_28_io_deq_bits : _T_3841 ? _Queue10_UInt8_27_io_deq_bits : _T_3840 ? _Queue10_UInt8_26_io_deq_bits : _T_3839 ? _Queue10_UInt8_25_io_deq_bits : _T_3838 ? _Queue10_UInt8_24_io_deq_bits : _T_3837 ? _Queue10_UInt8_23_io_deq_bits : _T_3836 ? _Queue10_UInt8_22_io_deq_bits : _T_3835 ? _Queue10_UInt8_21_io_deq_bits : _T_3834 ? _Queue10_UInt8_20_io_deq_bits : _T_3833 ? _Queue10_UInt8_19_io_deq_bits : _T_3832 ? _Queue10_UInt8_18_io_deq_bits : _T_3831 ? _Queue10_UInt8_17_io_deq_bits : _T_3830 ? _Queue10_UInt8_16_io_deq_bits : _T_3829 ? _Queue10_UInt8_15_io_deq_bits : _T_3828 ? _Queue10_UInt8_14_io_deq_bits : _T_3827 ? _Queue10_UInt8_13_io_deq_bits : _T_3826 ? _Queue10_UInt8_12_io_deq_bits : _T_3825 ? _Queue10_UInt8_11_io_deq_bits : _T_3824 ? _Queue10_UInt8_10_io_deq_bits : _T_3823 ? _Queue10_UInt8_9_io_deq_bits : _T_3822 ? _Queue10_UInt8_8_io_deq_bits : _T_3821 ? _Queue10_UInt8_7_io_deq_bits : _T_3820 ? _Queue10_UInt8_6_io_deq_bits : _T_3819 ? _Queue10_UInt8_5_io_deq_bits : _T_3818 ? _Queue10_UInt8_4_io_deq_bits : _T_3817 ? _Queue10_UInt8_3_io_deq_bits : _T_3816 ? _Queue10_UInt8_2_io_deq_bits : _T_3815 ? _Queue10_UInt8_1_io_deq_bits : _T_3814 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_17 = _T_3845 ? _Queue10_UInt8_31_io_deq_valid : _T_3844 ? _Queue10_UInt8_30_io_deq_valid : _T_3843 ? _Queue10_UInt8_29_io_deq_valid : _T_3842 ? _Queue10_UInt8_28_io_deq_valid : _T_3841 ? _Queue10_UInt8_27_io_deq_valid : _T_3840 ? _Queue10_UInt8_26_io_deq_valid : _T_3839 ? _Queue10_UInt8_25_io_deq_valid : _T_3838 ? _Queue10_UInt8_24_io_deq_valid : _T_3837 ? _Queue10_UInt8_23_io_deq_valid : _T_3836 ? _Queue10_UInt8_22_io_deq_valid : _T_3835 ? _Queue10_UInt8_21_io_deq_valid : _T_3834 ? _Queue10_UInt8_20_io_deq_valid : _T_3833 ? _Queue10_UInt8_19_io_deq_valid : _T_3832 ? _Queue10_UInt8_18_io_deq_valid : _T_3831 ? _Queue10_UInt8_17_io_deq_valid : _T_3830 ? _Queue10_UInt8_16_io_deq_valid : _T_3829 ? _Queue10_UInt8_15_io_deq_valid : _T_3828 ? _Queue10_UInt8_14_io_deq_valid : _T_3827 ? _Queue10_UInt8_13_io_deq_valid : _T_3826 ? _Queue10_UInt8_12_io_deq_valid : _T_3825 ? _Queue10_UInt8_11_io_deq_valid : _T_3824 ? _Queue10_UInt8_10_io_deq_valid : _T_3823 ? _Queue10_UInt8_9_io_deq_valid : _T_3822 ? _Queue10_UInt8_8_io_deq_valid : _T_3821 ? _Queue10_UInt8_7_io_deq_valid : _T_3820 ? _Queue10_UInt8_6_io_deq_valid : _T_3819 ? _Queue10_UInt8_5_io_deq_valid : _T_3818 ? _Queue10_UInt8_4_io_deq_valid : _T_3817 ? _Queue10_UInt8_3_io_deq_valid : _T_3816 ? _Queue10_UInt8_2_io_deq_valid : _T_3815 ? _Queue10_UInt8_1_io_deq_valid : _T_3814 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_107 = _remapindex_T_18 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_18 = _GEN_107[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3846 = remapindex_18 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3847 = remapindex_18 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3848 = remapindex_18 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3849 = remapindex_18 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3850 = remapindex_18 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3851 = remapindex_18 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3852 = remapindex_18 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3853 = remapindex_18 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3854 = remapindex_18 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3855 = remapindex_18 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3856 = remapindex_18 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3857 = remapindex_18 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3858 = remapindex_18 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3859 = remapindex_18 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3860 = remapindex_18 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3861 = remapindex_18 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3862 = remapindex_18 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3863 = remapindex_18 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3864 = remapindex_18 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3865 = remapindex_18 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3866 = remapindex_18 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3867 = remapindex_18 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3868 = remapindex_18 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3869 = remapindex_18 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3870 = remapindex_18 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3871 = remapindex_18 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3872 = remapindex_18 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3873 = remapindex_18 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3874 = remapindex_18 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3875 = remapindex_18 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3876 = remapindex_18 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3877 = remapindex_18 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_18 = _T_3877 ? _Queue10_UInt8_31_io_deq_bits : _T_3876 ? _Queue10_UInt8_30_io_deq_bits : _T_3875 ? _Queue10_UInt8_29_io_deq_bits : _T_3874 ? _Queue10_UInt8_28_io_deq_bits : _T_3873 ? _Queue10_UInt8_27_io_deq_bits : _T_3872 ? _Queue10_UInt8_26_io_deq_bits : _T_3871 ? _Queue10_UInt8_25_io_deq_bits : _T_3870 ? _Queue10_UInt8_24_io_deq_bits : _T_3869 ? _Queue10_UInt8_23_io_deq_bits : _T_3868 ? _Queue10_UInt8_22_io_deq_bits : _T_3867 ? _Queue10_UInt8_21_io_deq_bits : _T_3866 ? _Queue10_UInt8_20_io_deq_bits : _T_3865 ? _Queue10_UInt8_19_io_deq_bits : _T_3864 ? _Queue10_UInt8_18_io_deq_bits : _T_3863 ? _Queue10_UInt8_17_io_deq_bits : _T_3862 ? _Queue10_UInt8_16_io_deq_bits : _T_3861 ? _Queue10_UInt8_15_io_deq_bits : _T_3860 ? _Queue10_UInt8_14_io_deq_bits : _T_3859 ? _Queue10_UInt8_13_io_deq_bits : _T_3858 ? _Queue10_UInt8_12_io_deq_bits : _T_3857 ? _Queue10_UInt8_11_io_deq_bits : _T_3856 ? _Queue10_UInt8_10_io_deq_bits : _T_3855 ? _Queue10_UInt8_9_io_deq_bits : _T_3854 ? _Queue10_UInt8_8_io_deq_bits : _T_3853 ? _Queue10_UInt8_7_io_deq_bits : _T_3852 ? _Queue10_UInt8_6_io_deq_bits : _T_3851 ? _Queue10_UInt8_5_io_deq_bits : _T_3850 ? _Queue10_UInt8_4_io_deq_bits : _T_3849 ? _Queue10_UInt8_3_io_deq_bits : _T_3848 ? _Queue10_UInt8_2_io_deq_bits : _T_3847 ? _Queue10_UInt8_1_io_deq_bits : _T_3846 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_18 = _T_3877 ? _Queue10_UInt8_31_io_deq_valid : _T_3876 ? _Queue10_UInt8_30_io_deq_valid : _T_3875 ? _Queue10_UInt8_29_io_deq_valid : _T_3874 ? _Queue10_UInt8_28_io_deq_valid : _T_3873 ? _Queue10_UInt8_27_io_deq_valid : _T_3872 ? _Queue10_UInt8_26_io_deq_valid : _T_3871 ? _Queue10_UInt8_25_io_deq_valid : _T_3870 ? _Queue10_UInt8_24_io_deq_valid : _T_3869 ? _Queue10_UInt8_23_io_deq_valid : _T_3868 ? _Queue10_UInt8_22_io_deq_valid : _T_3867 ? _Queue10_UInt8_21_io_deq_valid : _T_3866 ? _Queue10_UInt8_20_io_deq_valid : _T_3865 ? _Queue10_UInt8_19_io_deq_valid : _T_3864 ? _Queue10_UInt8_18_io_deq_valid : _T_3863 ? _Queue10_UInt8_17_io_deq_valid : _T_3862 ? _Queue10_UInt8_16_io_deq_valid : _T_3861 ? _Queue10_UInt8_15_io_deq_valid : _T_3860 ? _Queue10_UInt8_14_io_deq_valid : _T_3859 ? _Queue10_UInt8_13_io_deq_valid : _T_3858 ? _Queue10_UInt8_12_io_deq_valid : _T_3857 ? _Queue10_UInt8_11_io_deq_valid : _T_3856 ? _Queue10_UInt8_10_io_deq_valid : _T_3855 ? _Queue10_UInt8_9_io_deq_valid : _T_3854 ? _Queue10_UInt8_8_io_deq_valid : _T_3853 ? _Queue10_UInt8_7_io_deq_valid : _T_3852 ? _Queue10_UInt8_6_io_deq_valid : _T_3851 ? _Queue10_UInt8_5_io_deq_valid : _T_3850 ? _Queue10_UInt8_4_io_deq_valid : _T_3849 ? _Queue10_UInt8_3_io_deq_valid : _T_3848 ? _Queue10_UInt8_2_io_deq_valid : _T_3847 ? _Queue10_UInt8_1_io_deq_valid : _T_3846 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_108 = _remapindex_T_19 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_19 = _GEN_108[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3878 = remapindex_19 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3879 = remapindex_19 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3880 = remapindex_19 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3881 = remapindex_19 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3882 = remapindex_19 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3883 = remapindex_19 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3884 = remapindex_19 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3885 = remapindex_19 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3886 = remapindex_19 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3887 = remapindex_19 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3888 = remapindex_19 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3889 = remapindex_19 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3890 = remapindex_19 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3891 = remapindex_19 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3892 = remapindex_19 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3893 = remapindex_19 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3894 = remapindex_19 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3895 = remapindex_19 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3896 = remapindex_19 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3897 = remapindex_19 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3898 = remapindex_19 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3899 = remapindex_19 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3900 = remapindex_19 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3901 = remapindex_19 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3902 = remapindex_19 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3903 = remapindex_19 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3904 = remapindex_19 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3905 = remapindex_19 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3906 = remapindex_19 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3907 = remapindex_19 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3908 = remapindex_19 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3909 = remapindex_19 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_19 = _T_3909 ? _Queue10_UInt8_31_io_deq_bits : _T_3908 ? _Queue10_UInt8_30_io_deq_bits : _T_3907 ? _Queue10_UInt8_29_io_deq_bits : _T_3906 ? _Queue10_UInt8_28_io_deq_bits : _T_3905 ? _Queue10_UInt8_27_io_deq_bits : _T_3904 ? _Queue10_UInt8_26_io_deq_bits : _T_3903 ? _Queue10_UInt8_25_io_deq_bits : _T_3902 ? _Queue10_UInt8_24_io_deq_bits : _T_3901 ? _Queue10_UInt8_23_io_deq_bits : _T_3900 ? _Queue10_UInt8_22_io_deq_bits : _T_3899 ? _Queue10_UInt8_21_io_deq_bits : _T_3898 ? _Queue10_UInt8_20_io_deq_bits : _T_3897 ? _Queue10_UInt8_19_io_deq_bits : _T_3896 ? _Queue10_UInt8_18_io_deq_bits : _T_3895 ? _Queue10_UInt8_17_io_deq_bits : _T_3894 ? _Queue10_UInt8_16_io_deq_bits : _T_3893 ? _Queue10_UInt8_15_io_deq_bits : _T_3892 ? _Queue10_UInt8_14_io_deq_bits : _T_3891 ? _Queue10_UInt8_13_io_deq_bits : _T_3890 ? _Queue10_UInt8_12_io_deq_bits : _T_3889 ? _Queue10_UInt8_11_io_deq_bits : _T_3888 ? _Queue10_UInt8_10_io_deq_bits : _T_3887 ? _Queue10_UInt8_9_io_deq_bits : _T_3886 ? _Queue10_UInt8_8_io_deq_bits : _T_3885 ? _Queue10_UInt8_7_io_deq_bits : _T_3884 ? _Queue10_UInt8_6_io_deq_bits : _T_3883 ? _Queue10_UInt8_5_io_deq_bits : _T_3882 ? _Queue10_UInt8_4_io_deq_bits : _T_3881 ? _Queue10_UInt8_3_io_deq_bits : _T_3880 ? _Queue10_UInt8_2_io_deq_bits : _T_3879 ? _Queue10_UInt8_1_io_deq_bits : _T_3878 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_19 = _T_3909 ? _Queue10_UInt8_31_io_deq_valid : _T_3908 ? _Queue10_UInt8_30_io_deq_valid : _T_3907 ? _Queue10_UInt8_29_io_deq_valid : _T_3906 ? _Queue10_UInt8_28_io_deq_valid : _T_3905 ? _Queue10_UInt8_27_io_deq_valid : _T_3904 ? _Queue10_UInt8_26_io_deq_valid : _T_3903 ? _Queue10_UInt8_25_io_deq_valid : _T_3902 ? _Queue10_UInt8_24_io_deq_valid : _T_3901 ? _Queue10_UInt8_23_io_deq_valid : _T_3900 ? _Queue10_UInt8_22_io_deq_valid : _T_3899 ? _Queue10_UInt8_21_io_deq_valid : _T_3898 ? _Queue10_UInt8_20_io_deq_valid : _T_3897 ? _Queue10_UInt8_19_io_deq_valid : _T_3896 ? _Queue10_UInt8_18_io_deq_valid : _T_3895 ? _Queue10_UInt8_17_io_deq_valid : _T_3894 ? _Queue10_UInt8_16_io_deq_valid : _T_3893 ? _Queue10_UInt8_15_io_deq_valid : _T_3892 ? _Queue10_UInt8_14_io_deq_valid : _T_3891 ? _Queue10_UInt8_13_io_deq_valid : _T_3890 ? _Queue10_UInt8_12_io_deq_valid : _T_3889 ? _Queue10_UInt8_11_io_deq_valid : _T_3888 ? _Queue10_UInt8_10_io_deq_valid : _T_3887 ? _Queue10_UInt8_9_io_deq_valid : _T_3886 ? _Queue10_UInt8_8_io_deq_valid : _T_3885 ? _Queue10_UInt8_7_io_deq_valid : _T_3884 ? _Queue10_UInt8_6_io_deq_valid : _T_3883 ? _Queue10_UInt8_5_io_deq_valid : _T_3882 ? _Queue10_UInt8_4_io_deq_valid : _T_3881 ? _Queue10_UInt8_3_io_deq_valid : _T_3880 ? _Queue10_UInt8_2_io_deq_valid : _T_3879 ? _Queue10_UInt8_1_io_deq_valid : _T_3878 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_109 = _remapindex_T_20 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_20 = _GEN_109[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3910 = remapindex_20 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3911 = remapindex_20 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3912 = remapindex_20 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3913 = remapindex_20 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3914 = remapindex_20 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3915 = remapindex_20 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3916 = remapindex_20 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3917 = remapindex_20 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3918 = remapindex_20 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3919 = remapindex_20 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3920 = remapindex_20 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3921 = remapindex_20 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3922 = remapindex_20 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3923 = remapindex_20 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3924 = remapindex_20 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3925 = remapindex_20 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3926 = remapindex_20 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3927 = remapindex_20 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3928 = remapindex_20 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3929 = remapindex_20 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3930 = remapindex_20 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3931 = remapindex_20 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3932 = remapindex_20 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3933 = remapindex_20 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3934 = remapindex_20 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3935 = remapindex_20 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3936 = remapindex_20 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3937 = remapindex_20 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3938 = remapindex_20 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3939 = remapindex_20 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3940 = remapindex_20 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3941 = remapindex_20 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_20 = _T_3941 ? _Queue10_UInt8_31_io_deq_bits : _T_3940 ? _Queue10_UInt8_30_io_deq_bits : _T_3939 ? _Queue10_UInt8_29_io_deq_bits : _T_3938 ? _Queue10_UInt8_28_io_deq_bits : _T_3937 ? _Queue10_UInt8_27_io_deq_bits : _T_3936 ? _Queue10_UInt8_26_io_deq_bits : _T_3935 ? _Queue10_UInt8_25_io_deq_bits : _T_3934 ? _Queue10_UInt8_24_io_deq_bits : _T_3933 ? _Queue10_UInt8_23_io_deq_bits : _T_3932 ? _Queue10_UInt8_22_io_deq_bits : _T_3931 ? _Queue10_UInt8_21_io_deq_bits : _T_3930 ? _Queue10_UInt8_20_io_deq_bits : _T_3929 ? _Queue10_UInt8_19_io_deq_bits : _T_3928 ? _Queue10_UInt8_18_io_deq_bits : _T_3927 ? _Queue10_UInt8_17_io_deq_bits : _T_3926 ? _Queue10_UInt8_16_io_deq_bits : _T_3925 ? _Queue10_UInt8_15_io_deq_bits : _T_3924 ? _Queue10_UInt8_14_io_deq_bits : _T_3923 ? _Queue10_UInt8_13_io_deq_bits : _T_3922 ? _Queue10_UInt8_12_io_deq_bits : _T_3921 ? _Queue10_UInt8_11_io_deq_bits : _T_3920 ? _Queue10_UInt8_10_io_deq_bits : _T_3919 ? _Queue10_UInt8_9_io_deq_bits : _T_3918 ? _Queue10_UInt8_8_io_deq_bits : _T_3917 ? _Queue10_UInt8_7_io_deq_bits : _T_3916 ? _Queue10_UInt8_6_io_deq_bits : _T_3915 ? _Queue10_UInt8_5_io_deq_bits : _T_3914 ? _Queue10_UInt8_4_io_deq_bits : _T_3913 ? _Queue10_UInt8_3_io_deq_bits : _T_3912 ? _Queue10_UInt8_2_io_deq_bits : _T_3911 ? _Queue10_UInt8_1_io_deq_bits : _T_3910 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_20 = _T_3941 ? _Queue10_UInt8_31_io_deq_valid : _T_3940 ? _Queue10_UInt8_30_io_deq_valid : _T_3939 ? _Queue10_UInt8_29_io_deq_valid : _T_3938 ? _Queue10_UInt8_28_io_deq_valid : _T_3937 ? _Queue10_UInt8_27_io_deq_valid : _T_3936 ? _Queue10_UInt8_26_io_deq_valid : _T_3935 ? _Queue10_UInt8_25_io_deq_valid : _T_3934 ? _Queue10_UInt8_24_io_deq_valid : _T_3933 ? _Queue10_UInt8_23_io_deq_valid : _T_3932 ? _Queue10_UInt8_22_io_deq_valid : _T_3931 ? _Queue10_UInt8_21_io_deq_valid : _T_3930 ? _Queue10_UInt8_20_io_deq_valid : _T_3929 ? _Queue10_UInt8_19_io_deq_valid : _T_3928 ? _Queue10_UInt8_18_io_deq_valid : _T_3927 ? _Queue10_UInt8_17_io_deq_valid : _T_3926 ? _Queue10_UInt8_16_io_deq_valid : _T_3925 ? _Queue10_UInt8_15_io_deq_valid : _T_3924 ? _Queue10_UInt8_14_io_deq_valid : _T_3923 ? _Queue10_UInt8_13_io_deq_valid : _T_3922 ? _Queue10_UInt8_12_io_deq_valid : _T_3921 ? _Queue10_UInt8_11_io_deq_valid : _T_3920 ? _Queue10_UInt8_10_io_deq_valid : _T_3919 ? _Queue10_UInt8_9_io_deq_valid : _T_3918 ? _Queue10_UInt8_8_io_deq_valid : _T_3917 ? _Queue10_UInt8_7_io_deq_valid : _T_3916 ? _Queue10_UInt8_6_io_deq_valid : _T_3915 ? _Queue10_UInt8_5_io_deq_valid : _T_3914 ? _Queue10_UInt8_4_io_deq_valid : _T_3913 ? _Queue10_UInt8_3_io_deq_valid : _T_3912 ? _Queue10_UInt8_2_io_deq_valid : _T_3911 ? _Queue10_UInt8_1_io_deq_valid : _T_3910 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_110 = _remapindex_T_21 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_21 = _GEN_110[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3942 = remapindex_21 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3943 = remapindex_21 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3944 = remapindex_21 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3945 = remapindex_21 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3946 = remapindex_21 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3947 = remapindex_21 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3948 = remapindex_21 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3949 = remapindex_21 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3950 = remapindex_21 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3951 = remapindex_21 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3952 = remapindex_21 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3953 = remapindex_21 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3954 = remapindex_21 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3955 = remapindex_21 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3956 = remapindex_21 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3957 = remapindex_21 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3958 = remapindex_21 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3959 = remapindex_21 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3960 = remapindex_21 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3961 = remapindex_21 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3962 = remapindex_21 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3963 = remapindex_21 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3964 = remapindex_21 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3965 = remapindex_21 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3966 = remapindex_21 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3967 = remapindex_21 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3968 = remapindex_21 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3969 = remapindex_21 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3970 = remapindex_21 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3971 = remapindex_21 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3972 = remapindex_21 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3973 = remapindex_21 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_21 = _T_3973 ? _Queue10_UInt8_31_io_deq_bits : _T_3972 ? _Queue10_UInt8_30_io_deq_bits : _T_3971 ? _Queue10_UInt8_29_io_deq_bits : _T_3970 ? _Queue10_UInt8_28_io_deq_bits : _T_3969 ? _Queue10_UInt8_27_io_deq_bits : _T_3968 ? _Queue10_UInt8_26_io_deq_bits : _T_3967 ? _Queue10_UInt8_25_io_deq_bits : _T_3966 ? _Queue10_UInt8_24_io_deq_bits : _T_3965 ? _Queue10_UInt8_23_io_deq_bits : _T_3964 ? _Queue10_UInt8_22_io_deq_bits : _T_3963 ? _Queue10_UInt8_21_io_deq_bits : _T_3962 ? _Queue10_UInt8_20_io_deq_bits : _T_3961 ? _Queue10_UInt8_19_io_deq_bits : _T_3960 ? _Queue10_UInt8_18_io_deq_bits : _T_3959 ? _Queue10_UInt8_17_io_deq_bits : _T_3958 ? _Queue10_UInt8_16_io_deq_bits : _T_3957 ? _Queue10_UInt8_15_io_deq_bits : _T_3956 ? _Queue10_UInt8_14_io_deq_bits : _T_3955 ? _Queue10_UInt8_13_io_deq_bits : _T_3954 ? _Queue10_UInt8_12_io_deq_bits : _T_3953 ? _Queue10_UInt8_11_io_deq_bits : _T_3952 ? _Queue10_UInt8_10_io_deq_bits : _T_3951 ? _Queue10_UInt8_9_io_deq_bits : _T_3950 ? _Queue10_UInt8_8_io_deq_bits : _T_3949 ? _Queue10_UInt8_7_io_deq_bits : _T_3948 ? _Queue10_UInt8_6_io_deq_bits : _T_3947 ? _Queue10_UInt8_5_io_deq_bits : _T_3946 ? _Queue10_UInt8_4_io_deq_bits : _T_3945 ? _Queue10_UInt8_3_io_deq_bits : _T_3944 ? _Queue10_UInt8_2_io_deq_bits : _T_3943 ? _Queue10_UInt8_1_io_deq_bits : _T_3942 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_21 = _T_3973 ? _Queue10_UInt8_31_io_deq_valid : _T_3972 ? _Queue10_UInt8_30_io_deq_valid : _T_3971 ? _Queue10_UInt8_29_io_deq_valid : _T_3970 ? _Queue10_UInt8_28_io_deq_valid : _T_3969 ? _Queue10_UInt8_27_io_deq_valid : _T_3968 ? _Queue10_UInt8_26_io_deq_valid : _T_3967 ? _Queue10_UInt8_25_io_deq_valid : _T_3966 ? _Queue10_UInt8_24_io_deq_valid : _T_3965 ? _Queue10_UInt8_23_io_deq_valid : _T_3964 ? _Queue10_UInt8_22_io_deq_valid : _T_3963 ? _Queue10_UInt8_21_io_deq_valid : _T_3962 ? _Queue10_UInt8_20_io_deq_valid : _T_3961 ? _Queue10_UInt8_19_io_deq_valid : _T_3960 ? _Queue10_UInt8_18_io_deq_valid : _T_3959 ? _Queue10_UInt8_17_io_deq_valid : _T_3958 ? _Queue10_UInt8_16_io_deq_valid : _T_3957 ? _Queue10_UInt8_15_io_deq_valid : _T_3956 ? _Queue10_UInt8_14_io_deq_valid : _T_3955 ? _Queue10_UInt8_13_io_deq_valid : _T_3954 ? _Queue10_UInt8_12_io_deq_valid : _T_3953 ? _Queue10_UInt8_11_io_deq_valid : _T_3952 ? _Queue10_UInt8_10_io_deq_valid : _T_3951 ? _Queue10_UInt8_9_io_deq_valid : _T_3950 ? _Queue10_UInt8_8_io_deq_valid : _T_3949 ? _Queue10_UInt8_7_io_deq_valid : _T_3948 ? _Queue10_UInt8_6_io_deq_valid : _T_3947 ? _Queue10_UInt8_5_io_deq_valid : _T_3946 ? _Queue10_UInt8_4_io_deq_valid : _T_3945 ? _Queue10_UInt8_3_io_deq_valid : _T_3944 ? _Queue10_UInt8_2_io_deq_valid : _T_3943 ? _Queue10_UInt8_1_io_deq_valid : _T_3942 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_111 = _remapindex_T_22 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_22 = _GEN_111[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3974 = remapindex_22 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3975 = remapindex_22 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3976 = remapindex_22 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3977 = remapindex_22 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3978 = remapindex_22 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3979 = remapindex_22 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3980 = remapindex_22 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3981 = remapindex_22 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3982 = remapindex_22 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3983 = remapindex_22 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3984 = remapindex_22 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3985 = remapindex_22 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3986 = remapindex_22 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3987 = remapindex_22 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3988 = remapindex_22 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3989 = remapindex_22 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3990 = remapindex_22 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3991 = remapindex_22 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3992 = remapindex_22 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3993 = remapindex_22 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3994 = remapindex_22 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3995 = remapindex_22 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3996 = remapindex_22 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3997 = remapindex_22 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3998 = remapindex_22 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3999 = remapindex_22 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4000 = remapindex_22 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4001 = remapindex_22 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4002 = remapindex_22 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4003 = remapindex_22 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4004 = remapindex_22 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4005 = remapindex_22 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_22 = _T_4005 ? _Queue10_UInt8_31_io_deq_bits : _T_4004 ? _Queue10_UInt8_30_io_deq_bits : _T_4003 ? _Queue10_UInt8_29_io_deq_bits : _T_4002 ? _Queue10_UInt8_28_io_deq_bits : _T_4001 ? _Queue10_UInt8_27_io_deq_bits : _T_4000 ? _Queue10_UInt8_26_io_deq_bits : _T_3999 ? _Queue10_UInt8_25_io_deq_bits : _T_3998 ? _Queue10_UInt8_24_io_deq_bits : _T_3997 ? _Queue10_UInt8_23_io_deq_bits : _T_3996 ? _Queue10_UInt8_22_io_deq_bits : _T_3995 ? _Queue10_UInt8_21_io_deq_bits : _T_3994 ? _Queue10_UInt8_20_io_deq_bits : _T_3993 ? _Queue10_UInt8_19_io_deq_bits : _T_3992 ? _Queue10_UInt8_18_io_deq_bits : _T_3991 ? _Queue10_UInt8_17_io_deq_bits : _T_3990 ? _Queue10_UInt8_16_io_deq_bits : _T_3989 ? _Queue10_UInt8_15_io_deq_bits : _T_3988 ? _Queue10_UInt8_14_io_deq_bits : _T_3987 ? _Queue10_UInt8_13_io_deq_bits : _T_3986 ? _Queue10_UInt8_12_io_deq_bits : _T_3985 ? _Queue10_UInt8_11_io_deq_bits : _T_3984 ? _Queue10_UInt8_10_io_deq_bits : _T_3983 ? _Queue10_UInt8_9_io_deq_bits : _T_3982 ? _Queue10_UInt8_8_io_deq_bits : _T_3981 ? _Queue10_UInt8_7_io_deq_bits : _T_3980 ? _Queue10_UInt8_6_io_deq_bits : _T_3979 ? _Queue10_UInt8_5_io_deq_bits : _T_3978 ? _Queue10_UInt8_4_io_deq_bits : _T_3977 ? _Queue10_UInt8_3_io_deq_bits : _T_3976 ? _Queue10_UInt8_2_io_deq_bits : _T_3975 ? _Queue10_UInt8_1_io_deq_bits : _T_3974 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_22 = _T_4005 ? _Queue10_UInt8_31_io_deq_valid : _T_4004 ? _Queue10_UInt8_30_io_deq_valid : _T_4003 ? _Queue10_UInt8_29_io_deq_valid : _T_4002 ? _Queue10_UInt8_28_io_deq_valid : _T_4001 ? _Queue10_UInt8_27_io_deq_valid : _T_4000 ? _Queue10_UInt8_26_io_deq_valid : _T_3999 ? _Queue10_UInt8_25_io_deq_valid : _T_3998 ? _Queue10_UInt8_24_io_deq_valid : _T_3997 ? _Queue10_UInt8_23_io_deq_valid : _T_3996 ? _Queue10_UInt8_22_io_deq_valid : _T_3995 ? _Queue10_UInt8_21_io_deq_valid : _T_3994 ? _Queue10_UInt8_20_io_deq_valid : _T_3993 ? _Queue10_UInt8_19_io_deq_valid : _T_3992 ? _Queue10_UInt8_18_io_deq_valid : _T_3991 ? _Queue10_UInt8_17_io_deq_valid : _T_3990 ? _Queue10_UInt8_16_io_deq_valid : _T_3989 ? _Queue10_UInt8_15_io_deq_valid : _T_3988 ? _Queue10_UInt8_14_io_deq_valid : _T_3987 ? _Queue10_UInt8_13_io_deq_valid : _T_3986 ? _Queue10_UInt8_12_io_deq_valid : _T_3985 ? _Queue10_UInt8_11_io_deq_valid : _T_3984 ? _Queue10_UInt8_10_io_deq_valid : _T_3983 ? _Queue10_UInt8_9_io_deq_valid : _T_3982 ? _Queue10_UInt8_8_io_deq_valid : _T_3981 ? _Queue10_UInt8_7_io_deq_valid : _T_3980 ? _Queue10_UInt8_6_io_deq_valid : _T_3979 ? _Queue10_UInt8_5_io_deq_valid : _T_3978 ? _Queue10_UInt8_4_io_deq_valid : _T_3977 ? _Queue10_UInt8_3_io_deq_valid : _T_3976 ? _Queue10_UInt8_2_io_deq_valid : _T_3975 ? _Queue10_UInt8_1_io_deq_valid : _T_3974 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_112 = _remapindex_T_23 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_23 = _GEN_112[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4006 = remapindex_23 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4007 = remapindex_23 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4008 = remapindex_23 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4009 = remapindex_23 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4010 = remapindex_23 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4011 = remapindex_23 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4012 = remapindex_23 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4013 = remapindex_23 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4014 = remapindex_23 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4015 = remapindex_23 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4016 = remapindex_23 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4017 = remapindex_23 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4018 = remapindex_23 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4019 = remapindex_23 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4020 = remapindex_23 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4021 = remapindex_23 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4022 = remapindex_23 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4023 = remapindex_23 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4024 = remapindex_23 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4025 = remapindex_23 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4026 = remapindex_23 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4027 = remapindex_23 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4028 = remapindex_23 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4029 = remapindex_23 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4030 = remapindex_23 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4031 = remapindex_23 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4032 = remapindex_23 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4033 = remapindex_23 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4034 = remapindex_23 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4035 = remapindex_23 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4036 = remapindex_23 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4037 = remapindex_23 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_23 = _T_4037 ? _Queue10_UInt8_31_io_deq_bits : _T_4036 ? _Queue10_UInt8_30_io_deq_bits : _T_4035 ? _Queue10_UInt8_29_io_deq_bits : _T_4034 ? _Queue10_UInt8_28_io_deq_bits : _T_4033 ? _Queue10_UInt8_27_io_deq_bits : _T_4032 ? _Queue10_UInt8_26_io_deq_bits : _T_4031 ? _Queue10_UInt8_25_io_deq_bits : _T_4030 ? _Queue10_UInt8_24_io_deq_bits : _T_4029 ? _Queue10_UInt8_23_io_deq_bits : _T_4028 ? _Queue10_UInt8_22_io_deq_bits : _T_4027 ? _Queue10_UInt8_21_io_deq_bits : _T_4026 ? _Queue10_UInt8_20_io_deq_bits : _T_4025 ? _Queue10_UInt8_19_io_deq_bits : _T_4024 ? _Queue10_UInt8_18_io_deq_bits : _T_4023 ? _Queue10_UInt8_17_io_deq_bits : _T_4022 ? _Queue10_UInt8_16_io_deq_bits : _T_4021 ? _Queue10_UInt8_15_io_deq_bits : _T_4020 ? _Queue10_UInt8_14_io_deq_bits : _T_4019 ? _Queue10_UInt8_13_io_deq_bits : _T_4018 ? _Queue10_UInt8_12_io_deq_bits : _T_4017 ? _Queue10_UInt8_11_io_deq_bits : _T_4016 ? _Queue10_UInt8_10_io_deq_bits : _T_4015 ? _Queue10_UInt8_9_io_deq_bits : _T_4014 ? _Queue10_UInt8_8_io_deq_bits : _T_4013 ? _Queue10_UInt8_7_io_deq_bits : _T_4012 ? _Queue10_UInt8_6_io_deq_bits : _T_4011 ? _Queue10_UInt8_5_io_deq_bits : _T_4010 ? _Queue10_UInt8_4_io_deq_bits : _T_4009 ? _Queue10_UInt8_3_io_deq_bits : _T_4008 ? _Queue10_UInt8_2_io_deq_bits : _T_4007 ? _Queue10_UInt8_1_io_deq_bits : _T_4006 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_23 = _T_4037 ? _Queue10_UInt8_31_io_deq_valid : _T_4036 ? _Queue10_UInt8_30_io_deq_valid : _T_4035 ? _Queue10_UInt8_29_io_deq_valid : _T_4034 ? _Queue10_UInt8_28_io_deq_valid : _T_4033 ? _Queue10_UInt8_27_io_deq_valid : _T_4032 ? _Queue10_UInt8_26_io_deq_valid : _T_4031 ? _Queue10_UInt8_25_io_deq_valid : _T_4030 ? _Queue10_UInt8_24_io_deq_valid : _T_4029 ? _Queue10_UInt8_23_io_deq_valid : _T_4028 ? _Queue10_UInt8_22_io_deq_valid : _T_4027 ? _Queue10_UInt8_21_io_deq_valid : _T_4026 ? _Queue10_UInt8_20_io_deq_valid : _T_4025 ? _Queue10_UInt8_19_io_deq_valid : _T_4024 ? _Queue10_UInt8_18_io_deq_valid : _T_4023 ? _Queue10_UInt8_17_io_deq_valid : _T_4022 ? _Queue10_UInt8_16_io_deq_valid : _T_4021 ? _Queue10_UInt8_15_io_deq_valid : _T_4020 ? _Queue10_UInt8_14_io_deq_valid : _T_4019 ? _Queue10_UInt8_13_io_deq_valid : _T_4018 ? _Queue10_UInt8_12_io_deq_valid : _T_4017 ? _Queue10_UInt8_11_io_deq_valid : _T_4016 ? _Queue10_UInt8_10_io_deq_valid : _T_4015 ? _Queue10_UInt8_9_io_deq_valid : _T_4014 ? _Queue10_UInt8_8_io_deq_valid : _T_4013 ? _Queue10_UInt8_7_io_deq_valid : _T_4012 ? _Queue10_UInt8_6_io_deq_valid : _T_4011 ? _Queue10_UInt8_5_io_deq_valid : _T_4010 ? _Queue10_UInt8_4_io_deq_valid : _T_4009 ? _Queue10_UInt8_3_io_deq_valid : _T_4008 ? _Queue10_UInt8_2_io_deq_valid : _T_4007 ? _Queue10_UInt8_1_io_deq_valid : _T_4006 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_113 = _remapindex_T_24 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_24 = _GEN_113[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4038 = remapindex_24 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4039 = remapindex_24 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4040 = remapindex_24 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4041 = remapindex_24 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4042 = remapindex_24 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4043 = remapindex_24 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4044 = remapindex_24 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4045 = remapindex_24 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4046 = remapindex_24 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4047 = remapindex_24 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4048 = remapindex_24 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4049 = remapindex_24 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4050 = remapindex_24 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4051 = remapindex_24 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4052 = remapindex_24 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4053 = remapindex_24 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4054 = remapindex_24 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4055 = remapindex_24 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4056 = remapindex_24 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4057 = remapindex_24 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4058 = remapindex_24 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4059 = remapindex_24 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4060 = remapindex_24 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4061 = remapindex_24 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4062 = remapindex_24 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4063 = remapindex_24 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4064 = remapindex_24 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4065 = remapindex_24 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4066 = remapindex_24 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4067 = remapindex_24 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4068 = remapindex_24 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4069 = remapindex_24 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_24 = _T_4069 ? _Queue10_UInt8_31_io_deq_bits : _T_4068 ? _Queue10_UInt8_30_io_deq_bits : _T_4067 ? _Queue10_UInt8_29_io_deq_bits : _T_4066 ? _Queue10_UInt8_28_io_deq_bits : _T_4065 ? _Queue10_UInt8_27_io_deq_bits : _T_4064 ? _Queue10_UInt8_26_io_deq_bits : _T_4063 ? _Queue10_UInt8_25_io_deq_bits : _T_4062 ? _Queue10_UInt8_24_io_deq_bits : _T_4061 ? _Queue10_UInt8_23_io_deq_bits : _T_4060 ? _Queue10_UInt8_22_io_deq_bits : _T_4059 ? _Queue10_UInt8_21_io_deq_bits : _T_4058 ? _Queue10_UInt8_20_io_deq_bits : _T_4057 ? _Queue10_UInt8_19_io_deq_bits : _T_4056 ? _Queue10_UInt8_18_io_deq_bits : _T_4055 ? _Queue10_UInt8_17_io_deq_bits : _T_4054 ? _Queue10_UInt8_16_io_deq_bits : _T_4053 ? _Queue10_UInt8_15_io_deq_bits : _T_4052 ? _Queue10_UInt8_14_io_deq_bits : _T_4051 ? _Queue10_UInt8_13_io_deq_bits : _T_4050 ? _Queue10_UInt8_12_io_deq_bits : _T_4049 ? _Queue10_UInt8_11_io_deq_bits : _T_4048 ? _Queue10_UInt8_10_io_deq_bits : _T_4047 ? _Queue10_UInt8_9_io_deq_bits : _T_4046 ? _Queue10_UInt8_8_io_deq_bits : _T_4045 ? _Queue10_UInt8_7_io_deq_bits : _T_4044 ? _Queue10_UInt8_6_io_deq_bits : _T_4043 ? _Queue10_UInt8_5_io_deq_bits : _T_4042 ? _Queue10_UInt8_4_io_deq_bits : _T_4041 ? _Queue10_UInt8_3_io_deq_bits : _T_4040 ? _Queue10_UInt8_2_io_deq_bits : _T_4039 ? _Queue10_UInt8_1_io_deq_bits : _T_4038 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_24 = _T_4069 ? _Queue10_UInt8_31_io_deq_valid : _T_4068 ? _Queue10_UInt8_30_io_deq_valid : _T_4067 ? _Queue10_UInt8_29_io_deq_valid : _T_4066 ? _Queue10_UInt8_28_io_deq_valid : _T_4065 ? _Queue10_UInt8_27_io_deq_valid : _T_4064 ? _Queue10_UInt8_26_io_deq_valid : _T_4063 ? _Queue10_UInt8_25_io_deq_valid : _T_4062 ? _Queue10_UInt8_24_io_deq_valid : _T_4061 ? _Queue10_UInt8_23_io_deq_valid : _T_4060 ? _Queue10_UInt8_22_io_deq_valid : _T_4059 ? _Queue10_UInt8_21_io_deq_valid : _T_4058 ? _Queue10_UInt8_20_io_deq_valid : _T_4057 ? _Queue10_UInt8_19_io_deq_valid : _T_4056 ? _Queue10_UInt8_18_io_deq_valid : _T_4055 ? _Queue10_UInt8_17_io_deq_valid : _T_4054 ? _Queue10_UInt8_16_io_deq_valid : _T_4053 ? _Queue10_UInt8_15_io_deq_valid : _T_4052 ? _Queue10_UInt8_14_io_deq_valid : _T_4051 ? _Queue10_UInt8_13_io_deq_valid : _T_4050 ? _Queue10_UInt8_12_io_deq_valid : _T_4049 ? _Queue10_UInt8_11_io_deq_valid : _T_4048 ? _Queue10_UInt8_10_io_deq_valid : _T_4047 ? _Queue10_UInt8_9_io_deq_valid : _T_4046 ? _Queue10_UInt8_8_io_deq_valid : _T_4045 ? _Queue10_UInt8_7_io_deq_valid : _T_4044 ? _Queue10_UInt8_6_io_deq_valid : _T_4043 ? _Queue10_UInt8_5_io_deq_valid : _T_4042 ? _Queue10_UInt8_4_io_deq_valid : _T_4041 ? _Queue10_UInt8_3_io_deq_valid : _T_4040 ? _Queue10_UInt8_2_io_deq_valid : _T_4039 ? _Queue10_UInt8_1_io_deq_valid : _T_4038 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_114 = _remapindex_T_25 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_25 = _GEN_114[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4070 = remapindex_25 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4071 = remapindex_25 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4072 = remapindex_25 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4073 = remapindex_25 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4074 = remapindex_25 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4075 = remapindex_25 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4076 = remapindex_25 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4077 = remapindex_25 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4078 = remapindex_25 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4079 = remapindex_25 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4080 = remapindex_25 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4081 = remapindex_25 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4082 = remapindex_25 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4083 = remapindex_25 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4084 = remapindex_25 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4085 = remapindex_25 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4086 = remapindex_25 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4087 = remapindex_25 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4088 = remapindex_25 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4089 = remapindex_25 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4090 = remapindex_25 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4091 = remapindex_25 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4092 = remapindex_25 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4093 = remapindex_25 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4094 = remapindex_25 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4095 = remapindex_25 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4096 = remapindex_25 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4097 = remapindex_25 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4098 = remapindex_25 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4099 = remapindex_25 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4100 = remapindex_25 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4101 = remapindex_25 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_25 = _T_4101 ? _Queue10_UInt8_31_io_deq_bits : _T_4100 ? _Queue10_UInt8_30_io_deq_bits : _T_4099 ? _Queue10_UInt8_29_io_deq_bits : _T_4098 ? _Queue10_UInt8_28_io_deq_bits : _T_4097 ? _Queue10_UInt8_27_io_deq_bits : _T_4096 ? _Queue10_UInt8_26_io_deq_bits : _T_4095 ? _Queue10_UInt8_25_io_deq_bits : _T_4094 ? _Queue10_UInt8_24_io_deq_bits : _T_4093 ? _Queue10_UInt8_23_io_deq_bits : _T_4092 ? _Queue10_UInt8_22_io_deq_bits : _T_4091 ? _Queue10_UInt8_21_io_deq_bits : _T_4090 ? _Queue10_UInt8_20_io_deq_bits : _T_4089 ? _Queue10_UInt8_19_io_deq_bits : _T_4088 ? _Queue10_UInt8_18_io_deq_bits : _T_4087 ? _Queue10_UInt8_17_io_deq_bits : _T_4086 ? _Queue10_UInt8_16_io_deq_bits : _T_4085 ? _Queue10_UInt8_15_io_deq_bits : _T_4084 ? _Queue10_UInt8_14_io_deq_bits : _T_4083 ? _Queue10_UInt8_13_io_deq_bits : _T_4082 ? _Queue10_UInt8_12_io_deq_bits : _T_4081 ? _Queue10_UInt8_11_io_deq_bits : _T_4080 ? _Queue10_UInt8_10_io_deq_bits : _T_4079 ? _Queue10_UInt8_9_io_deq_bits : _T_4078 ? _Queue10_UInt8_8_io_deq_bits : _T_4077 ? _Queue10_UInt8_7_io_deq_bits : _T_4076 ? _Queue10_UInt8_6_io_deq_bits : _T_4075 ? _Queue10_UInt8_5_io_deq_bits : _T_4074 ? _Queue10_UInt8_4_io_deq_bits : _T_4073 ? _Queue10_UInt8_3_io_deq_bits : _T_4072 ? _Queue10_UInt8_2_io_deq_bits : _T_4071 ? _Queue10_UInt8_1_io_deq_bits : _T_4070 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_25 = _T_4101 ? _Queue10_UInt8_31_io_deq_valid : _T_4100 ? _Queue10_UInt8_30_io_deq_valid : _T_4099 ? _Queue10_UInt8_29_io_deq_valid : _T_4098 ? _Queue10_UInt8_28_io_deq_valid : _T_4097 ? _Queue10_UInt8_27_io_deq_valid : _T_4096 ? _Queue10_UInt8_26_io_deq_valid : _T_4095 ? _Queue10_UInt8_25_io_deq_valid : _T_4094 ? _Queue10_UInt8_24_io_deq_valid : _T_4093 ? _Queue10_UInt8_23_io_deq_valid : _T_4092 ? _Queue10_UInt8_22_io_deq_valid : _T_4091 ? _Queue10_UInt8_21_io_deq_valid : _T_4090 ? _Queue10_UInt8_20_io_deq_valid : _T_4089 ? _Queue10_UInt8_19_io_deq_valid : _T_4088 ? _Queue10_UInt8_18_io_deq_valid : _T_4087 ? _Queue10_UInt8_17_io_deq_valid : _T_4086 ? _Queue10_UInt8_16_io_deq_valid : _T_4085 ? _Queue10_UInt8_15_io_deq_valid : _T_4084 ? _Queue10_UInt8_14_io_deq_valid : _T_4083 ? _Queue10_UInt8_13_io_deq_valid : _T_4082 ? _Queue10_UInt8_12_io_deq_valid : _T_4081 ? _Queue10_UInt8_11_io_deq_valid : _T_4080 ? _Queue10_UInt8_10_io_deq_valid : _T_4079 ? _Queue10_UInt8_9_io_deq_valid : _T_4078 ? _Queue10_UInt8_8_io_deq_valid : _T_4077 ? _Queue10_UInt8_7_io_deq_valid : _T_4076 ? _Queue10_UInt8_6_io_deq_valid : _T_4075 ? _Queue10_UInt8_5_io_deq_valid : _T_4074 ? _Queue10_UInt8_4_io_deq_valid : _T_4073 ? _Queue10_UInt8_3_io_deq_valid : _T_4072 ? _Queue10_UInt8_2_io_deq_valid : _T_4071 ? _Queue10_UInt8_1_io_deq_valid : _T_4070 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_115 = _remapindex_T_26 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_26 = _GEN_115[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4102 = remapindex_26 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4103 = remapindex_26 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4104 = remapindex_26 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4105 = remapindex_26 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4106 = remapindex_26 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4107 = remapindex_26 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4108 = remapindex_26 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4109 = remapindex_26 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4110 = remapindex_26 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4111 = remapindex_26 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4112 = remapindex_26 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4113 = remapindex_26 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4114 = remapindex_26 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4115 = remapindex_26 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4116 = remapindex_26 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4117 = remapindex_26 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4118 = remapindex_26 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4119 = remapindex_26 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4120 = remapindex_26 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4121 = remapindex_26 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4122 = remapindex_26 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4123 = remapindex_26 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4124 = remapindex_26 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4125 = remapindex_26 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4126 = remapindex_26 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4127 = remapindex_26 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4128 = remapindex_26 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4129 = remapindex_26 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4130 = remapindex_26 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4131 = remapindex_26 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4132 = remapindex_26 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4133 = remapindex_26 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_26 = _T_4133 ? _Queue10_UInt8_31_io_deq_bits : _T_4132 ? _Queue10_UInt8_30_io_deq_bits : _T_4131 ? _Queue10_UInt8_29_io_deq_bits : _T_4130 ? _Queue10_UInt8_28_io_deq_bits : _T_4129 ? _Queue10_UInt8_27_io_deq_bits : _T_4128 ? _Queue10_UInt8_26_io_deq_bits : _T_4127 ? _Queue10_UInt8_25_io_deq_bits : _T_4126 ? _Queue10_UInt8_24_io_deq_bits : _T_4125 ? _Queue10_UInt8_23_io_deq_bits : _T_4124 ? _Queue10_UInt8_22_io_deq_bits : _T_4123 ? _Queue10_UInt8_21_io_deq_bits : _T_4122 ? _Queue10_UInt8_20_io_deq_bits : _T_4121 ? _Queue10_UInt8_19_io_deq_bits : _T_4120 ? _Queue10_UInt8_18_io_deq_bits : _T_4119 ? _Queue10_UInt8_17_io_deq_bits : _T_4118 ? _Queue10_UInt8_16_io_deq_bits : _T_4117 ? _Queue10_UInt8_15_io_deq_bits : _T_4116 ? _Queue10_UInt8_14_io_deq_bits : _T_4115 ? _Queue10_UInt8_13_io_deq_bits : _T_4114 ? _Queue10_UInt8_12_io_deq_bits : _T_4113 ? _Queue10_UInt8_11_io_deq_bits : _T_4112 ? _Queue10_UInt8_10_io_deq_bits : _T_4111 ? _Queue10_UInt8_9_io_deq_bits : _T_4110 ? _Queue10_UInt8_8_io_deq_bits : _T_4109 ? _Queue10_UInt8_7_io_deq_bits : _T_4108 ? _Queue10_UInt8_6_io_deq_bits : _T_4107 ? _Queue10_UInt8_5_io_deq_bits : _T_4106 ? _Queue10_UInt8_4_io_deq_bits : _T_4105 ? _Queue10_UInt8_3_io_deq_bits : _T_4104 ? _Queue10_UInt8_2_io_deq_bits : _T_4103 ? _Queue10_UInt8_1_io_deq_bits : _T_4102 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_26 = _T_4133 ? _Queue10_UInt8_31_io_deq_valid : _T_4132 ? _Queue10_UInt8_30_io_deq_valid : _T_4131 ? _Queue10_UInt8_29_io_deq_valid : _T_4130 ? _Queue10_UInt8_28_io_deq_valid : _T_4129 ? _Queue10_UInt8_27_io_deq_valid : _T_4128 ? _Queue10_UInt8_26_io_deq_valid : _T_4127 ? _Queue10_UInt8_25_io_deq_valid : _T_4126 ? _Queue10_UInt8_24_io_deq_valid : _T_4125 ? _Queue10_UInt8_23_io_deq_valid : _T_4124 ? _Queue10_UInt8_22_io_deq_valid : _T_4123 ? _Queue10_UInt8_21_io_deq_valid : _T_4122 ? _Queue10_UInt8_20_io_deq_valid : _T_4121 ? _Queue10_UInt8_19_io_deq_valid : _T_4120 ? _Queue10_UInt8_18_io_deq_valid : _T_4119 ? _Queue10_UInt8_17_io_deq_valid : _T_4118 ? _Queue10_UInt8_16_io_deq_valid : _T_4117 ? _Queue10_UInt8_15_io_deq_valid : _T_4116 ? _Queue10_UInt8_14_io_deq_valid : _T_4115 ? _Queue10_UInt8_13_io_deq_valid : _T_4114 ? _Queue10_UInt8_12_io_deq_valid : _T_4113 ? _Queue10_UInt8_11_io_deq_valid : _T_4112 ? _Queue10_UInt8_10_io_deq_valid : _T_4111 ? _Queue10_UInt8_9_io_deq_valid : _T_4110 ? _Queue10_UInt8_8_io_deq_valid : _T_4109 ? _Queue10_UInt8_7_io_deq_valid : _T_4108 ? _Queue10_UInt8_6_io_deq_valid : _T_4107 ? _Queue10_UInt8_5_io_deq_valid : _T_4106 ? _Queue10_UInt8_4_io_deq_valid : _T_4105 ? _Queue10_UInt8_3_io_deq_valid : _T_4104 ? _Queue10_UInt8_2_io_deq_valid : _T_4103 ? _Queue10_UInt8_1_io_deq_valid : _T_4102 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_116 = _remapindex_T_27 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_27 = _GEN_116[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4134 = remapindex_27 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4135 = remapindex_27 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4136 = remapindex_27 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4137 = remapindex_27 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4138 = remapindex_27 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4139 = remapindex_27 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4140 = remapindex_27 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4141 = remapindex_27 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4142 = remapindex_27 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4143 = remapindex_27 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4144 = remapindex_27 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4145 = remapindex_27 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4146 = remapindex_27 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4147 = remapindex_27 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4148 = remapindex_27 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4149 = remapindex_27 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4150 = remapindex_27 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4151 = remapindex_27 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4152 = remapindex_27 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4153 = remapindex_27 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4154 = remapindex_27 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4155 = remapindex_27 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4156 = remapindex_27 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4157 = remapindex_27 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4158 = remapindex_27 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4159 = remapindex_27 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4160 = remapindex_27 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4161 = remapindex_27 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4162 = remapindex_27 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4163 = remapindex_27 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4164 = remapindex_27 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4165 = remapindex_27 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_27 = _T_4165 ? _Queue10_UInt8_31_io_deq_bits : _T_4164 ? _Queue10_UInt8_30_io_deq_bits : _T_4163 ? _Queue10_UInt8_29_io_deq_bits : _T_4162 ? _Queue10_UInt8_28_io_deq_bits : _T_4161 ? _Queue10_UInt8_27_io_deq_bits : _T_4160 ? _Queue10_UInt8_26_io_deq_bits : _T_4159 ? _Queue10_UInt8_25_io_deq_bits : _T_4158 ? _Queue10_UInt8_24_io_deq_bits : _T_4157 ? _Queue10_UInt8_23_io_deq_bits : _T_4156 ? _Queue10_UInt8_22_io_deq_bits : _T_4155 ? _Queue10_UInt8_21_io_deq_bits : _T_4154 ? _Queue10_UInt8_20_io_deq_bits : _T_4153 ? _Queue10_UInt8_19_io_deq_bits : _T_4152 ? _Queue10_UInt8_18_io_deq_bits : _T_4151 ? _Queue10_UInt8_17_io_deq_bits : _T_4150 ? _Queue10_UInt8_16_io_deq_bits : _T_4149 ? _Queue10_UInt8_15_io_deq_bits : _T_4148 ? _Queue10_UInt8_14_io_deq_bits : _T_4147 ? _Queue10_UInt8_13_io_deq_bits : _T_4146 ? _Queue10_UInt8_12_io_deq_bits : _T_4145 ? _Queue10_UInt8_11_io_deq_bits : _T_4144 ? _Queue10_UInt8_10_io_deq_bits : _T_4143 ? _Queue10_UInt8_9_io_deq_bits : _T_4142 ? _Queue10_UInt8_8_io_deq_bits : _T_4141 ? _Queue10_UInt8_7_io_deq_bits : _T_4140 ? _Queue10_UInt8_6_io_deq_bits : _T_4139 ? _Queue10_UInt8_5_io_deq_bits : _T_4138 ? _Queue10_UInt8_4_io_deq_bits : _T_4137 ? _Queue10_UInt8_3_io_deq_bits : _T_4136 ? _Queue10_UInt8_2_io_deq_bits : _T_4135 ? _Queue10_UInt8_1_io_deq_bits : _T_4134 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_27 = _T_4165 ? _Queue10_UInt8_31_io_deq_valid : _T_4164 ? _Queue10_UInt8_30_io_deq_valid : _T_4163 ? _Queue10_UInt8_29_io_deq_valid : _T_4162 ? _Queue10_UInt8_28_io_deq_valid : _T_4161 ? _Queue10_UInt8_27_io_deq_valid : _T_4160 ? _Queue10_UInt8_26_io_deq_valid : _T_4159 ? _Queue10_UInt8_25_io_deq_valid : _T_4158 ? _Queue10_UInt8_24_io_deq_valid : _T_4157 ? _Queue10_UInt8_23_io_deq_valid : _T_4156 ? _Queue10_UInt8_22_io_deq_valid : _T_4155 ? _Queue10_UInt8_21_io_deq_valid : _T_4154 ? _Queue10_UInt8_20_io_deq_valid : _T_4153 ? _Queue10_UInt8_19_io_deq_valid : _T_4152 ? _Queue10_UInt8_18_io_deq_valid : _T_4151 ? _Queue10_UInt8_17_io_deq_valid : _T_4150 ? _Queue10_UInt8_16_io_deq_valid : _T_4149 ? _Queue10_UInt8_15_io_deq_valid : _T_4148 ? _Queue10_UInt8_14_io_deq_valid : _T_4147 ? _Queue10_UInt8_13_io_deq_valid : _T_4146 ? _Queue10_UInt8_12_io_deq_valid : _T_4145 ? _Queue10_UInt8_11_io_deq_valid : _T_4144 ? _Queue10_UInt8_10_io_deq_valid : _T_4143 ? _Queue10_UInt8_9_io_deq_valid : _T_4142 ? _Queue10_UInt8_8_io_deq_valid : _T_4141 ? _Queue10_UInt8_7_io_deq_valid : _T_4140 ? _Queue10_UInt8_6_io_deq_valid : _T_4139 ? _Queue10_UInt8_5_io_deq_valid : _T_4138 ? _Queue10_UInt8_4_io_deq_valid : _T_4137 ? _Queue10_UInt8_3_io_deq_valid : _T_4136 ? _Queue10_UInt8_2_io_deq_valid : _T_4135 ? _Queue10_UInt8_1_io_deq_valid : _T_4134 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_117 = _remapindex_T_28 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_28 = _GEN_117[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4166 = remapindex_28 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4167 = remapindex_28 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4168 = remapindex_28 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4169 = remapindex_28 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4170 = remapindex_28 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4171 = remapindex_28 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4172 = remapindex_28 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4173 = remapindex_28 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4174 = remapindex_28 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4175 = remapindex_28 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4176 = remapindex_28 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4177 = remapindex_28 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4178 = remapindex_28 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4179 = remapindex_28 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4180 = remapindex_28 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4181 = remapindex_28 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4182 = remapindex_28 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4183 = remapindex_28 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4184 = remapindex_28 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4185 = remapindex_28 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4186 = remapindex_28 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4187 = remapindex_28 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4188 = remapindex_28 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4189 = remapindex_28 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4190 = remapindex_28 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4191 = remapindex_28 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4192 = remapindex_28 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4193 = remapindex_28 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4194 = remapindex_28 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4195 = remapindex_28 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4196 = remapindex_28 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4197 = remapindex_28 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_28 = _T_4197 ? _Queue10_UInt8_31_io_deq_bits : _T_4196 ? _Queue10_UInt8_30_io_deq_bits : _T_4195 ? _Queue10_UInt8_29_io_deq_bits : _T_4194 ? _Queue10_UInt8_28_io_deq_bits : _T_4193 ? _Queue10_UInt8_27_io_deq_bits : _T_4192 ? _Queue10_UInt8_26_io_deq_bits : _T_4191 ? _Queue10_UInt8_25_io_deq_bits : _T_4190 ? _Queue10_UInt8_24_io_deq_bits : _T_4189 ? _Queue10_UInt8_23_io_deq_bits : _T_4188 ? _Queue10_UInt8_22_io_deq_bits : _T_4187 ? _Queue10_UInt8_21_io_deq_bits : _T_4186 ? _Queue10_UInt8_20_io_deq_bits : _T_4185 ? _Queue10_UInt8_19_io_deq_bits : _T_4184 ? _Queue10_UInt8_18_io_deq_bits : _T_4183 ? _Queue10_UInt8_17_io_deq_bits : _T_4182 ? _Queue10_UInt8_16_io_deq_bits : _T_4181 ? _Queue10_UInt8_15_io_deq_bits : _T_4180 ? _Queue10_UInt8_14_io_deq_bits : _T_4179 ? _Queue10_UInt8_13_io_deq_bits : _T_4178 ? _Queue10_UInt8_12_io_deq_bits : _T_4177 ? _Queue10_UInt8_11_io_deq_bits : _T_4176 ? _Queue10_UInt8_10_io_deq_bits : _T_4175 ? _Queue10_UInt8_9_io_deq_bits : _T_4174 ? _Queue10_UInt8_8_io_deq_bits : _T_4173 ? _Queue10_UInt8_7_io_deq_bits : _T_4172 ? _Queue10_UInt8_6_io_deq_bits : _T_4171 ? _Queue10_UInt8_5_io_deq_bits : _T_4170 ? _Queue10_UInt8_4_io_deq_bits : _T_4169 ? _Queue10_UInt8_3_io_deq_bits : _T_4168 ? _Queue10_UInt8_2_io_deq_bits : _T_4167 ? _Queue10_UInt8_1_io_deq_bits : _T_4166 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_28 = _T_4197 ? _Queue10_UInt8_31_io_deq_valid : _T_4196 ? _Queue10_UInt8_30_io_deq_valid : _T_4195 ? _Queue10_UInt8_29_io_deq_valid : _T_4194 ? _Queue10_UInt8_28_io_deq_valid : _T_4193 ? _Queue10_UInt8_27_io_deq_valid : _T_4192 ? _Queue10_UInt8_26_io_deq_valid : _T_4191 ? _Queue10_UInt8_25_io_deq_valid : _T_4190 ? _Queue10_UInt8_24_io_deq_valid : _T_4189 ? _Queue10_UInt8_23_io_deq_valid : _T_4188 ? _Queue10_UInt8_22_io_deq_valid : _T_4187 ? _Queue10_UInt8_21_io_deq_valid : _T_4186 ? _Queue10_UInt8_20_io_deq_valid : _T_4185 ? _Queue10_UInt8_19_io_deq_valid : _T_4184 ? _Queue10_UInt8_18_io_deq_valid : _T_4183 ? _Queue10_UInt8_17_io_deq_valid : _T_4182 ? _Queue10_UInt8_16_io_deq_valid : _T_4181 ? _Queue10_UInt8_15_io_deq_valid : _T_4180 ? _Queue10_UInt8_14_io_deq_valid : _T_4179 ? _Queue10_UInt8_13_io_deq_valid : _T_4178 ? _Queue10_UInt8_12_io_deq_valid : _T_4177 ? _Queue10_UInt8_11_io_deq_valid : _T_4176 ? _Queue10_UInt8_10_io_deq_valid : _T_4175 ? _Queue10_UInt8_9_io_deq_valid : _T_4174 ? _Queue10_UInt8_8_io_deq_valid : _T_4173 ? _Queue10_UInt8_7_io_deq_valid : _T_4172 ? _Queue10_UInt8_6_io_deq_valid : _T_4171 ? _Queue10_UInt8_5_io_deq_valid : _T_4170 ? _Queue10_UInt8_4_io_deq_valid : _T_4169 ? _Queue10_UInt8_3_io_deq_valid : _T_4168 ? _Queue10_UInt8_2_io_deq_valid : _T_4167 ? _Queue10_UInt8_1_io_deq_valid : _T_4166 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_118 = _remapindex_T_29 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_29 = _GEN_118[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4198 = remapindex_29 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4199 = remapindex_29 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4200 = remapindex_29 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4201 = remapindex_29 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4202 = remapindex_29 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4203 = remapindex_29 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4204 = remapindex_29 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4205 = remapindex_29 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4206 = remapindex_29 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4207 = remapindex_29 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4208 = remapindex_29 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4209 = remapindex_29 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4210 = remapindex_29 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4211 = remapindex_29 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4212 = remapindex_29 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4213 = remapindex_29 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4214 = remapindex_29 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4215 = remapindex_29 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4216 = remapindex_29 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4217 = remapindex_29 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4218 = remapindex_29 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4219 = remapindex_29 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4220 = remapindex_29 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4221 = remapindex_29 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4222 = remapindex_29 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4223 = remapindex_29 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4224 = remapindex_29 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4225 = remapindex_29 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4226 = remapindex_29 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4227 = remapindex_29 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4228 = remapindex_29 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4229 = remapindex_29 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_29 = _T_4229 ? _Queue10_UInt8_31_io_deq_bits : _T_4228 ? _Queue10_UInt8_30_io_deq_bits : _T_4227 ? _Queue10_UInt8_29_io_deq_bits : _T_4226 ? _Queue10_UInt8_28_io_deq_bits : _T_4225 ? _Queue10_UInt8_27_io_deq_bits : _T_4224 ? _Queue10_UInt8_26_io_deq_bits : _T_4223 ? _Queue10_UInt8_25_io_deq_bits : _T_4222 ? _Queue10_UInt8_24_io_deq_bits : _T_4221 ? _Queue10_UInt8_23_io_deq_bits : _T_4220 ? _Queue10_UInt8_22_io_deq_bits : _T_4219 ? _Queue10_UInt8_21_io_deq_bits : _T_4218 ? _Queue10_UInt8_20_io_deq_bits : _T_4217 ? _Queue10_UInt8_19_io_deq_bits : _T_4216 ? _Queue10_UInt8_18_io_deq_bits : _T_4215 ? _Queue10_UInt8_17_io_deq_bits : _T_4214 ? _Queue10_UInt8_16_io_deq_bits : _T_4213 ? _Queue10_UInt8_15_io_deq_bits : _T_4212 ? _Queue10_UInt8_14_io_deq_bits : _T_4211 ? _Queue10_UInt8_13_io_deq_bits : _T_4210 ? _Queue10_UInt8_12_io_deq_bits : _T_4209 ? _Queue10_UInt8_11_io_deq_bits : _T_4208 ? _Queue10_UInt8_10_io_deq_bits : _T_4207 ? _Queue10_UInt8_9_io_deq_bits : _T_4206 ? _Queue10_UInt8_8_io_deq_bits : _T_4205 ? _Queue10_UInt8_7_io_deq_bits : _T_4204 ? _Queue10_UInt8_6_io_deq_bits : _T_4203 ? _Queue10_UInt8_5_io_deq_bits : _T_4202 ? _Queue10_UInt8_4_io_deq_bits : _T_4201 ? _Queue10_UInt8_3_io_deq_bits : _T_4200 ? _Queue10_UInt8_2_io_deq_bits : _T_4199 ? _Queue10_UInt8_1_io_deq_bits : _T_4198 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_29 = _T_4229 ? _Queue10_UInt8_31_io_deq_valid : _T_4228 ? _Queue10_UInt8_30_io_deq_valid : _T_4227 ? _Queue10_UInt8_29_io_deq_valid : _T_4226 ? _Queue10_UInt8_28_io_deq_valid : _T_4225 ? _Queue10_UInt8_27_io_deq_valid : _T_4224 ? _Queue10_UInt8_26_io_deq_valid : _T_4223 ? _Queue10_UInt8_25_io_deq_valid : _T_4222 ? _Queue10_UInt8_24_io_deq_valid : _T_4221 ? _Queue10_UInt8_23_io_deq_valid : _T_4220 ? _Queue10_UInt8_22_io_deq_valid : _T_4219 ? _Queue10_UInt8_21_io_deq_valid : _T_4218 ? _Queue10_UInt8_20_io_deq_valid : _T_4217 ? _Queue10_UInt8_19_io_deq_valid : _T_4216 ? _Queue10_UInt8_18_io_deq_valid : _T_4215 ? _Queue10_UInt8_17_io_deq_valid : _T_4214 ? _Queue10_UInt8_16_io_deq_valid : _T_4213 ? _Queue10_UInt8_15_io_deq_valid : _T_4212 ? _Queue10_UInt8_14_io_deq_valid : _T_4211 ? _Queue10_UInt8_13_io_deq_valid : _T_4210 ? _Queue10_UInt8_12_io_deq_valid : _T_4209 ? _Queue10_UInt8_11_io_deq_valid : _T_4208 ? _Queue10_UInt8_10_io_deq_valid : _T_4207 ? _Queue10_UInt8_9_io_deq_valid : _T_4206 ? _Queue10_UInt8_8_io_deq_valid : _T_4205 ? _Queue10_UInt8_7_io_deq_valid : _T_4204 ? _Queue10_UInt8_6_io_deq_valid : _T_4203 ? _Queue10_UInt8_5_io_deq_valid : _T_4202 ? _Queue10_UInt8_4_io_deq_valid : _T_4201 ? _Queue10_UInt8_3_io_deq_valid : _T_4200 ? _Queue10_UInt8_2_io_deq_valid : _T_4199 ? _Queue10_UInt8_1_io_deq_valid : _T_4198 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_119 = _remapindex_T_30 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_30 = _GEN_119[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4230 = remapindex_30 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4231 = remapindex_30 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4232 = remapindex_30 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4233 = remapindex_30 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4234 = remapindex_30 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4235 = remapindex_30 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4236 = remapindex_30 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4237 = remapindex_30 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4238 = remapindex_30 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4239 = remapindex_30 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4240 = remapindex_30 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4241 = remapindex_30 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4242 = remapindex_30 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4243 = remapindex_30 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4244 = remapindex_30 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4245 = remapindex_30 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4246 = remapindex_30 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4247 = remapindex_30 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4248 = remapindex_30 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4249 = remapindex_30 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4250 = remapindex_30 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4251 = remapindex_30 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4252 = remapindex_30 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4253 = remapindex_30 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4254 = remapindex_30 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4255 = remapindex_30 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4256 = remapindex_30 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4257 = remapindex_30 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4258 = remapindex_30 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4259 = remapindex_30 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4260 = remapindex_30 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4261 = remapindex_30 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_30 = _T_4261 ? _Queue10_UInt8_31_io_deq_bits : _T_4260 ? _Queue10_UInt8_30_io_deq_bits : _T_4259 ? _Queue10_UInt8_29_io_deq_bits : _T_4258 ? _Queue10_UInt8_28_io_deq_bits : _T_4257 ? _Queue10_UInt8_27_io_deq_bits : _T_4256 ? _Queue10_UInt8_26_io_deq_bits : _T_4255 ? _Queue10_UInt8_25_io_deq_bits : _T_4254 ? _Queue10_UInt8_24_io_deq_bits : _T_4253 ? _Queue10_UInt8_23_io_deq_bits : _T_4252 ? _Queue10_UInt8_22_io_deq_bits : _T_4251 ? _Queue10_UInt8_21_io_deq_bits : _T_4250 ? _Queue10_UInt8_20_io_deq_bits : _T_4249 ? _Queue10_UInt8_19_io_deq_bits : _T_4248 ? _Queue10_UInt8_18_io_deq_bits : _T_4247 ? _Queue10_UInt8_17_io_deq_bits : _T_4246 ? _Queue10_UInt8_16_io_deq_bits : _T_4245 ? _Queue10_UInt8_15_io_deq_bits : _T_4244 ? _Queue10_UInt8_14_io_deq_bits : _T_4243 ? _Queue10_UInt8_13_io_deq_bits : _T_4242 ? _Queue10_UInt8_12_io_deq_bits : _T_4241 ? _Queue10_UInt8_11_io_deq_bits : _T_4240 ? _Queue10_UInt8_10_io_deq_bits : _T_4239 ? _Queue10_UInt8_9_io_deq_bits : _T_4238 ? _Queue10_UInt8_8_io_deq_bits : _T_4237 ? _Queue10_UInt8_7_io_deq_bits : _T_4236 ? _Queue10_UInt8_6_io_deq_bits : _T_4235 ? _Queue10_UInt8_5_io_deq_bits : _T_4234 ? _Queue10_UInt8_4_io_deq_bits : _T_4233 ? _Queue10_UInt8_3_io_deq_bits : _T_4232 ? _Queue10_UInt8_2_io_deq_bits : _T_4231 ? _Queue10_UInt8_1_io_deq_bits : _T_4230 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_30 = _T_4261 ? _Queue10_UInt8_31_io_deq_valid : _T_4260 ? _Queue10_UInt8_30_io_deq_valid : _T_4259 ? _Queue10_UInt8_29_io_deq_valid : _T_4258 ? _Queue10_UInt8_28_io_deq_valid : _T_4257 ? _Queue10_UInt8_27_io_deq_valid : _T_4256 ? _Queue10_UInt8_26_io_deq_valid : _T_4255 ? _Queue10_UInt8_25_io_deq_valid : _T_4254 ? _Queue10_UInt8_24_io_deq_valid : _T_4253 ? _Queue10_UInt8_23_io_deq_valid : _T_4252 ? _Queue10_UInt8_22_io_deq_valid : _T_4251 ? _Queue10_UInt8_21_io_deq_valid : _T_4250 ? _Queue10_UInt8_20_io_deq_valid : _T_4249 ? _Queue10_UInt8_19_io_deq_valid : _T_4248 ? _Queue10_UInt8_18_io_deq_valid : _T_4247 ? _Queue10_UInt8_17_io_deq_valid : _T_4246 ? _Queue10_UInt8_16_io_deq_valid : _T_4245 ? _Queue10_UInt8_15_io_deq_valid : _T_4244 ? _Queue10_UInt8_14_io_deq_valid : _T_4243 ? _Queue10_UInt8_13_io_deq_valid : _T_4242 ? _Queue10_UInt8_12_io_deq_valid : _T_4241 ? _Queue10_UInt8_11_io_deq_valid : _T_4240 ? _Queue10_UInt8_10_io_deq_valid : _T_4239 ? _Queue10_UInt8_9_io_deq_valid : _T_4238 ? _Queue10_UInt8_8_io_deq_valid : _T_4237 ? _Queue10_UInt8_7_io_deq_valid : _T_4236 ? _Queue10_UInt8_6_io_deq_valid : _T_4235 ? _Queue10_UInt8_5_io_deq_valid : _T_4234 ? _Queue10_UInt8_4_io_deq_valid : _T_4233 ? _Queue10_UInt8_3_io_deq_valid : _T_4232 ? _Queue10_UInt8_2_io_deq_valid : _T_4231 ? _Queue10_UInt8_1_io_deq_valid : _T_4230 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_120 = _remapindex_T_31 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_31 = _GEN_120[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4262 = remapindex_31 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4263 = remapindex_31 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4264 = remapindex_31 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4265 = remapindex_31 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4266 = remapindex_31 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4267 = remapindex_31 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4268 = remapindex_31 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4269 = remapindex_31 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4270 = remapindex_31 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4271 = remapindex_31 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4272 = remapindex_31 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4273 = remapindex_31 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4274 = remapindex_31 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4275 = remapindex_31 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4276 = remapindex_31 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4277 = remapindex_31 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4278 = remapindex_31 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4279 = remapindex_31 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4280 = remapindex_31 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4281 = remapindex_31 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4282 = remapindex_31 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4283 = remapindex_31 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4284 = remapindex_31 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4285 = remapindex_31 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4286 = remapindex_31 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4287 = remapindex_31 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4288 = remapindex_31 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4289 = remapindex_31 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4290 = remapindex_31 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4291 = remapindex_31 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4292 = remapindex_31 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4293 = remapindex_31 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_31 = _T_4293 ? _Queue10_UInt8_31_io_deq_bits : _T_4292 ? _Queue10_UInt8_30_io_deq_bits : _T_4291 ? _Queue10_UInt8_29_io_deq_bits : _T_4290 ? _Queue10_UInt8_28_io_deq_bits : _T_4289 ? _Queue10_UInt8_27_io_deq_bits : _T_4288 ? _Queue10_UInt8_26_io_deq_bits : _T_4287 ? _Queue10_UInt8_25_io_deq_bits : _T_4286 ? _Queue10_UInt8_24_io_deq_bits : _T_4285 ? _Queue10_UInt8_23_io_deq_bits : _T_4284 ? _Queue10_UInt8_22_io_deq_bits : _T_4283 ? _Queue10_UInt8_21_io_deq_bits : _T_4282 ? _Queue10_UInt8_20_io_deq_bits : _T_4281 ? _Queue10_UInt8_19_io_deq_bits : _T_4280 ? _Queue10_UInt8_18_io_deq_bits : _T_4279 ? _Queue10_UInt8_17_io_deq_bits : _T_4278 ? _Queue10_UInt8_16_io_deq_bits : _T_4277 ? _Queue10_UInt8_15_io_deq_bits : _T_4276 ? _Queue10_UInt8_14_io_deq_bits : _T_4275 ? _Queue10_UInt8_13_io_deq_bits : _T_4274 ? _Queue10_UInt8_12_io_deq_bits : _T_4273 ? _Queue10_UInt8_11_io_deq_bits : _T_4272 ? _Queue10_UInt8_10_io_deq_bits : _T_4271 ? _Queue10_UInt8_9_io_deq_bits : _T_4270 ? _Queue10_UInt8_8_io_deq_bits : _T_4269 ? _Queue10_UInt8_7_io_deq_bits : _T_4268 ? _Queue10_UInt8_6_io_deq_bits : _T_4267 ? _Queue10_UInt8_5_io_deq_bits : _T_4266 ? _Queue10_UInt8_4_io_deq_bits : _T_4265 ? _Queue10_UInt8_3_io_deq_bits : _T_4264 ? _Queue10_UInt8_2_io_deq_bits : _T_4263 ? _Queue10_UInt8_1_io_deq_bits : _T_4262 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_31 = _T_4293 ? _Queue10_UInt8_31_io_deq_valid : _T_4292 ? _Queue10_UInt8_30_io_deq_valid : _T_4291 ? _Queue10_UInt8_29_io_deq_valid : _T_4290 ? _Queue10_UInt8_28_io_deq_valid : _T_4289 ? _Queue10_UInt8_27_io_deq_valid : _T_4288 ? _Queue10_UInt8_26_io_deq_valid : _T_4287 ? _Queue10_UInt8_25_io_deq_valid : _T_4286 ? _Queue10_UInt8_24_io_deq_valid : _T_4285 ? _Queue10_UInt8_23_io_deq_valid : _T_4284 ? _Queue10_UInt8_22_io_deq_valid : _T_4283 ? _Queue10_UInt8_21_io_deq_valid : _T_4282 ? _Queue10_UInt8_20_io_deq_valid : _T_4281 ? _Queue10_UInt8_19_io_deq_valid : _T_4280 ? _Queue10_UInt8_18_io_deq_valid : _T_4279 ? _Queue10_UInt8_17_io_deq_valid : _T_4278 ? _Queue10_UInt8_16_io_deq_valid : _T_4277 ? _Queue10_UInt8_15_io_deq_valid : _T_4276 ? _Queue10_UInt8_14_io_deq_valid : _T_4275 ? _Queue10_UInt8_13_io_deq_valid : _T_4274 ? _Queue10_UInt8_12_io_deq_valid : _T_4273 ? _Queue10_UInt8_11_io_deq_valid : _T_4272 ? _Queue10_UInt8_10_io_deq_valid : _T_4271 ? _Queue10_UInt8_9_io_deq_valid : _T_4270 ? _Queue10_UInt8_8_io_deq_valid : _T_4269 ? _Queue10_UInt8_7_io_deq_valid : _T_4268 ? _Queue10_UInt8_6_io_deq_valid : _T_4267 ? _Queue10_UInt8_5_io_deq_valid : _T_4266 ? _Queue10_UInt8_4_io_deq_valid : _T_4265 ? _Queue10_UInt8_3_io_deq_valid : _T_4264 ? _Queue10_UInt8_2_io_deq_valid : _T_4263 ? _Queue10_UInt8_1_io_deq_valid : _T_4262 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [15:0] io_consumer_output_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_lo_lo = {io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_lo_hi = {io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_lo_lo = {io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_hi_lo = {io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_hi_hi = {io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_lo_hi = {io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [127:0] io_consumer_output_data_lo = {io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_lo_lo = {io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_lo_hi = {io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_hi_lo = {io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_hi_lo = {io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_hi_hi = {io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_hi_hi = {io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [127:0] io_consumer_output_data_hi = {io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] assign _io_consumer_output_data_T = {io_consumer_output_data_hi, io_consumer_output_data_lo}; // @[ZstdLitRotBuf.scala:246:33] assign io_consumer_output_data_0 = _io_consumer_output_data_T; // @[ZstdLitRotBuf.scala:152:7, :246:33] wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[ZstdLitRotBuf.scala:185:{75,91}, :226:28, :249:60] wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[ZstdLitRotBuf.scala:185:{75,91}, :226:28, :249:60] wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[ZstdLitRotBuf.scala:226:28, :249:60] assign enough_data = |count_valids; // @[ZstdLitRotBuf.scala:249:60, :251:34] assign io_consumer_output_valid_0 = enough_data; // @[ZstdLitRotBuf.scala:152:7, :251:34] assign io_consumer_available_output_bytes_0 = count_valids[5:0]; // @[ZstdLitRotBuf.scala:152:7, :249:60, :253:38] wire _T_4303 = io_consumer_output_ready_0 & enough_data; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_4303; // @[Misc.scala:29:18] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module RocketTile : input clock : Clock input reset : Reset output auto : { buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, wfi_out : UInt<1>[1], cease_out : UInt<1>[1], halt_out : UInt<1>[1], flip int_local_in_3 : UInt<1>[1], flip int_local_in_2 : UInt<1>[1], flip int_local_in_1 : UInt<1>[2], flip int_local_in_0 : UInt<1>[1], trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip reset_vector_in : UInt<32>, flip hartid_in : UInt<3>} inst tlMasterXbar of TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c connect tlMasterXbar.clock, clock connect tlMasterXbar.reset, reset inst tlSlaveXbar of TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u connect tlSlaveXbar.clock, clock connect tlSlaveXbar.reset, reset inst intXbar of IntXbar_i4_o1 inst broadcast of BundleBridgeNexus_UInt3 inst broadcast_1 of BundleBridgeNexus_UInt32 inst nexus of BundleBridgeNexus_NoOutput_8 inst nexus_1 of BundleBridgeNexus_TraceAux inst broadcast_2 of BundleBridgeNexus_NoOutput_9 inst widget of TLWidthWidget8_13 connect widget.clock, clock connect widget.reset, reset inst dcache of DCache connect dcache.clock, clock connect dcache.reset, reset inst frontend of Frontend connect frontend.clock, clock connect frontend.reset, reset inst widget_1 of TLWidthWidget8_14 connect widget_1.clock, clock connect widget_1.reset, reset inst fragmenter of TLFragmenter connect fragmenter.clock, clock connect fragmenter.reset, reset inst widget_2 of TLWidthWidget8_15 connect widget_2.clock, clock connect widget_2.reset, reset inst buffer of TLBuffer_a32d64s2k3z4c connect buffer.clock, clock connect buffer.reset, reset inst buffer_1 of TLBuffer_2 connect buffer_1.clock, clock connect buffer_1.reset, reset wire tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate tlOtherMastersNodeOut.e.bits.sink invalidate tlOtherMastersNodeOut.e.valid invalidate tlOtherMastersNodeOut.e.ready invalidate tlOtherMastersNodeOut.d.bits.corrupt invalidate tlOtherMastersNodeOut.d.bits.data invalidate tlOtherMastersNodeOut.d.bits.denied invalidate tlOtherMastersNodeOut.d.bits.sink invalidate tlOtherMastersNodeOut.d.bits.source invalidate tlOtherMastersNodeOut.d.bits.size invalidate tlOtherMastersNodeOut.d.bits.param invalidate tlOtherMastersNodeOut.d.bits.opcode invalidate tlOtherMastersNodeOut.d.valid invalidate tlOtherMastersNodeOut.d.ready invalidate tlOtherMastersNodeOut.c.bits.corrupt invalidate tlOtherMastersNodeOut.c.bits.data invalidate tlOtherMastersNodeOut.c.bits.address invalidate tlOtherMastersNodeOut.c.bits.source invalidate tlOtherMastersNodeOut.c.bits.size invalidate tlOtherMastersNodeOut.c.bits.param invalidate tlOtherMastersNodeOut.c.bits.opcode invalidate tlOtherMastersNodeOut.c.valid invalidate tlOtherMastersNodeOut.c.ready invalidate tlOtherMastersNodeOut.b.bits.corrupt invalidate tlOtherMastersNodeOut.b.bits.data invalidate tlOtherMastersNodeOut.b.bits.mask invalidate tlOtherMastersNodeOut.b.bits.address invalidate tlOtherMastersNodeOut.b.bits.source invalidate tlOtherMastersNodeOut.b.bits.size invalidate tlOtherMastersNodeOut.b.bits.param invalidate tlOtherMastersNodeOut.b.bits.opcode invalidate tlOtherMastersNodeOut.b.valid invalidate tlOtherMastersNodeOut.b.ready invalidate tlOtherMastersNodeOut.a.bits.corrupt invalidate tlOtherMastersNodeOut.a.bits.data invalidate tlOtherMastersNodeOut.a.bits.mask invalidate tlOtherMastersNodeOut.a.bits.address invalidate tlOtherMastersNodeOut.a.bits.source invalidate tlOtherMastersNodeOut.a.bits.size invalidate tlOtherMastersNodeOut.a.bits.param invalidate tlOtherMastersNodeOut.a.bits.opcode invalidate tlOtherMastersNodeOut.a.valid invalidate tlOtherMastersNodeOut.a.ready wire tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate tlOtherMastersNodeIn.e.bits.sink invalidate tlOtherMastersNodeIn.e.valid invalidate tlOtherMastersNodeIn.e.ready invalidate tlOtherMastersNodeIn.d.bits.corrupt invalidate tlOtherMastersNodeIn.d.bits.data invalidate tlOtherMastersNodeIn.d.bits.denied invalidate tlOtherMastersNodeIn.d.bits.sink invalidate tlOtherMastersNodeIn.d.bits.source invalidate tlOtherMastersNodeIn.d.bits.size invalidate tlOtherMastersNodeIn.d.bits.param invalidate tlOtherMastersNodeIn.d.bits.opcode invalidate tlOtherMastersNodeIn.d.valid invalidate tlOtherMastersNodeIn.d.ready invalidate tlOtherMastersNodeIn.c.bits.corrupt invalidate tlOtherMastersNodeIn.c.bits.data invalidate tlOtherMastersNodeIn.c.bits.address invalidate tlOtherMastersNodeIn.c.bits.source invalidate tlOtherMastersNodeIn.c.bits.size invalidate tlOtherMastersNodeIn.c.bits.param invalidate tlOtherMastersNodeIn.c.bits.opcode invalidate tlOtherMastersNodeIn.c.valid invalidate tlOtherMastersNodeIn.c.ready invalidate tlOtherMastersNodeIn.b.bits.corrupt invalidate tlOtherMastersNodeIn.b.bits.data invalidate tlOtherMastersNodeIn.b.bits.mask invalidate tlOtherMastersNodeIn.b.bits.address invalidate tlOtherMastersNodeIn.b.bits.source invalidate tlOtherMastersNodeIn.b.bits.size invalidate tlOtherMastersNodeIn.b.bits.param invalidate tlOtherMastersNodeIn.b.bits.opcode invalidate tlOtherMastersNodeIn.b.valid invalidate tlOtherMastersNodeIn.b.ready invalidate tlOtherMastersNodeIn.a.bits.corrupt invalidate tlOtherMastersNodeIn.a.bits.data invalidate tlOtherMastersNodeIn.a.bits.mask invalidate tlOtherMastersNodeIn.a.bits.address invalidate tlOtherMastersNodeIn.a.bits.source invalidate tlOtherMastersNodeIn.a.bits.size invalidate tlOtherMastersNodeIn.a.bits.param invalidate tlOtherMastersNodeIn.a.bits.opcode invalidate tlOtherMastersNodeIn.a.valid invalidate tlOtherMastersNodeIn.a.ready connect tlOtherMastersNodeOut, tlOtherMastersNodeIn wire hartIdSinkNodeIn : UInt<3> invalidate hartIdSinkNodeIn wire hartidOut : UInt<3> invalidate hartidOut wire hartidIn : UInt<3> invalidate hartidIn connect hartidOut, hartidIn wire resetVectorSinkNodeIn : UInt<32> invalidate resetVectorSinkNodeIn wire reset_vectorOut : UInt<32> invalidate reset_vectorOut wire reset_vectorIn : UInt<32> invalidate reset_vectorIn connect reset_vectorOut, reset_vectorIn wire traceSourceNodeOut : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceSourceNodeOut.time invalidate traceSourceNodeOut.insns[0].tval invalidate traceSourceNodeOut.insns[0].cause invalidate traceSourceNodeOut.insns[0].interrupt invalidate traceSourceNodeOut.insns[0].exception invalidate traceSourceNodeOut.insns[0].priv invalidate traceSourceNodeOut.insns[0].insn invalidate traceSourceNodeOut.insns[0].iaddr invalidate traceSourceNodeOut.insns[0].valid wire traceCoreSourceNodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreSourceNodeOut.cause invalidate traceCoreSourceNodeOut.tval invalidate traceCoreSourceNodeOut.priv invalidate traceCoreSourceNodeOut.group[0].ilastsize invalidate traceCoreSourceNodeOut.group[0].itype invalidate traceCoreSourceNodeOut.group[0].iaddr invalidate traceCoreSourceNodeOut.group[0].iretire wire bundleIn_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>} connect bundleIn_x_sourceOpt.stall, UInt<1>(0h0) connect bundleIn_x_sourceOpt.enable, UInt<1>(0h0) wire traceAuxSinkNodeIn : { enable : UInt<1>, stall : UInt<1>} invalidate traceAuxSinkNodeIn.stall invalidate traceAuxSinkNodeIn.enable wire bpwatchSourceNodeOut : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1] invalidate bpwatchSourceNodeOut[0].action invalidate bpwatchSourceNodeOut[0].ivalid[0] invalidate bpwatchSourceNodeOut[0].wvalid[0] invalidate bpwatchSourceNodeOut[0].rvalid[0] invalidate bpwatchSourceNodeOut[0].valid[0] wire int_localOut : UInt<1>[1] invalidate int_localOut[0] wire x1_int_localOut : UInt<1>[2] invalidate x1_int_localOut[0] invalidate x1_int_localOut[1] wire x1_int_localOut_1 : UInt<1>[1] invalidate x1_int_localOut_1[0] wire x1_int_localOut_2 : UInt<1>[1] invalidate x1_int_localOut_2[0] wire int_localIn : UInt<1>[1] invalidate int_localIn[0] wire x1_int_localIn : UInt<1>[2] invalidate x1_int_localIn[0] invalidate x1_int_localIn[1] wire x1_int_localIn_1 : UInt<1>[1] invalidate x1_int_localIn_1[0] wire x1_int_localIn_2 : UInt<1>[1] invalidate x1_int_localIn_2[0] connect int_localOut, int_localIn connect x1_int_localOut, x1_int_localIn connect x1_int_localOut_1, x1_int_localIn_1 connect x1_int_localOut_2, x1_int_localIn_2 wire intSinkNodeIn : UInt<1>[5] invalidate intSinkNodeIn[0] invalidate intSinkNodeIn[1] invalidate intSinkNodeIn[2] invalidate intSinkNodeIn[3] invalidate intSinkNodeIn[4] wire haltNodeOut : UInt<1>[1] invalidate haltNodeOut[0] wire ceaseNodeOut : UInt<1>[1] invalidate ceaseNodeOut[0] wire wfiNodeOut : UInt<1>[1] invalidate wfiNodeOut[0] connect buffer.auto.in, tlOtherMastersNodeOut connect tlOtherMastersNodeIn.e.bits, tlMasterXbar.auto.anon_out.e.bits connect tlOtherMastersNodeIn.e.valid, tlMasterXbar.auto.anon_out.e.valid connect tlMasterXbar.auto.anon_out.e.ready, tlOtherMastersNodeIn.e.ready connect tlMasterXbar.auto.anon_out.d, tlOtherMastersNodeIn.d connect tlOtherMastersNodeIn.c.bits, tlMasterXbar.auto.anon_out.c.bits connect tlOtherMastersNodeIn.c.valid, tlMasterXbar.auto.anon_out.c.valid connect tlMasterXbar.auto.anon_out.c.ready, tlOtherMastersNodeIn.c.ready connect tlMasterXbar.auto.anon_out.b, tlOtherMastersNodeIn.b connect tlOtherMastersNodeIn.a.bits, tlMasterXbar.auto.anon_out.a.bits connect tlOtherMastersNodeIn.a.valid, tlMasterXbar.auto.anon_out.a.valid connect tlMasterXbar.auto.anon_out.a.ready, tlOtherMastersNodeIn.a.ready connect intSinkNodeIn, intXbar.auto.anon_out connect hartIdSinkNodeIn, broadcast.auto.out connect broadcast.auto.in, hartidOut connect resetVectorSinkNodeIn, broadcast_1.auto.out_0 connect frontend.auto.reset_vector_sink_in, broadcast_1.auto.out_1 connect broadcast_1.auto.in, reset_vectorOut connect traceAuxSinkNodeIn, nexus_1.auto.out connect broadcast_2.auto.in[0], bpwatchSourceNodeOut[0] connect intXbar.auto.anon_in_0[0], int_localOut[0] connect intXbar.auto.anon_in_1[0], x1_int_localOut[0] connect intXbar.auto.anon_in_1[1], x1_int_localOut[1] connect intXbar.auto.anon_in_2[0], x1_int_localOut_1[0] connect intXbar.auto.anon_in_3[0], x1_int_localOut_2[0] connect tlMasterXbar.auto.anon_in_0, widget.auto.anon_out connect widget.auto.anon_in, dcache.auto.out connect widget_1.auto.anon_in, frontend.auto.icache_master_out connect tlMasterXbar.auto.anon_in_1, widget_1.auto.anon_out connect hartidIn, auto.hartid_in connect reset_vectorIn, auto.reset_vector_in connect auto.trace_source_out, traceSourceNodeOut connect auto.trace_core_source_out, traceCoreSourceNodeOut connect int_localIn, auto.int_local_in_0 connect x1_int_localIn, auto.int_local_in_1 connect x1_int_localIn_1, auto.int_local_in_2 connect x1_int_localIn_2, auto.int_local_in_3 connect auto.halt_out, haltNodeOut connect auto.cease_out, ceaseNodeOut connect auto.wfi_out, wfiNodeOut connect auto.buffer_out.e.bits, buffer.auto.out.e.bits connect auto.buffer_out.e.valid, buffer.auto.out.e.valid connect buffer.auto.out.e.ready, auto.buffer_out.e.ready connect buffer.auto.out.d, auto.buffer_out.d connect auto.buffer_out.c.bits, buffer.auto.out.c.bits connect auto.buffer_out.c.valid, buffer.auto.out.c.valid connect buffer.auto.out.c.ready, auto.buffer_out.c.ready connect buffer.auto.out.b, auto.buffer_out.b connect auto.buffer_out.a.bits, buffer.auto.out.a.bits connect auto.buffer_out.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, auto.buffer_out.a.ready invalidate dcache.io.tlb_port.s2_kill invalidate dcache.io.tlb_port.s1_resp.cmd invalidate dcache.io.tlb_port.s1_resp.size invalidate dcache.io.tlb_port.s1_resp.prefetchable invalidate dcache.io.tlb_port.s1_resp.must_alloc invalidate dcache.io.tlb_port.s1_resp.cacheable invalidate dcache.io.tlb_port.s1_resp.ma.inst invalidate dcache.io.tlb_port.s1_resp.ma.st invalidate dcache.io.tlb_port.s1_resp.ma.ld invalidate dcache.io.tlb_port.s1_resp.ae.inst invalidate dcache.io.tlb_port.s1_resp.ae.st invalidate dcache.io.tlb_port.s1_resp.ae.ld invalidate dcache.io.tlb_port.s1_resp.gf.inst invalidate dcache.io.tlb_port.s1_resp.gf.st invalidate dcache.io.tlb_port.s1_resp.gf.ld invalidate dcache.io.tlb_port.s1_resp.pf.inst invalidate dcache.io.tlb_port.s1_resp.pf.st invalidate dcache.io.tlb_port.s1_resp.pf.ld invalidate dcache.io.tlb_port.s1_resp.gpa_is_pte invalidate dcache.io.tlb_port.s1_resp.gpa invalidate dcache.io.tlb_port.s1_resp.paddr invalidate dcache.io.tlb_port.s1_resp.miss invalidate dcache.io.tlb_port.req.bits.v invalidate dcache.io.tlb_port.req.bits.prv invalidate dcache.io.tlb_port.req.bits.cmd invalidate dcache.io.tlb_port.req.bits.size invalidate dcache.io.tlb_port.req.bits.passthrough invalidate dcache.io.tlb_port.req.bits.vaddr invalidate dcache.io.tlb_port.req.valid invalidate dcache.io.tlb_port.req.ready inst fpuOpt of FPU connect fpuOpt.clock, clock connect fpuOpt.reset, reset connect fpuOpt.io.cp_req.valid, UInt<1>(0h0) invalidate fpuOpt.io.cp_req.bits.in3 invalidate fpuOpt.io.cp_req.bits.in2 invalidate fpuOpt.io.cp_req.bits.in1 invalidate fpuOpt.io.cp_req.bits.fmt invalidate fpuOpt.io.cp_req.bits.typ invalidate fpuOpt.io.cp_req.bits.fmaCmd invalidate fpuOpt.io.cp_req.bits.rm invalidate fpuOpt.io.cp_req.bits.vec invalidate fpuOpt.io.cp_req.bits.wflags invalidate fpuOpt.io.cp_req.bits.sqrt invalidate fpuOpt.io.cp_req.bits.div invalidate fpuOpt.io.cp_req.bits.fma invalidate fpuOpt.io.cp_req.bits.fastpipe invalidate fpuOpt.io.cp_req.bits.toint invalidate fpuOpt.io.cp_req.bits.fromint invalidate fpuOpt.io.cp_req.bits.typeTagOut invalidate fpuOpt.io.cp_req.bits.typeTagIn invalidate fpuOpt.io.cp_req.bits.swap23 invalidate fpuOpt.io.cp_req.bits.swap12 invalidate fpuOpt.io.cp_req.bits.ren3 invalidate fpuOpt.io.cp_req.bits.ren2 invalidate fpuOpt.io.cp_req.bits.ren1 invalidate fpuOpt.io.cp_req.bits.wen invalidate fpuOpt.io.cp_req.bits.ldst connect fpuOpt.io.cp_resp.ready, UInt<1>(0h0) inst dcacheArb of HellaCacheArbiter connect dcacheArb.clock, clock connect dcacheArb.reset, reset connect dcache.io.cpu, dcacheArb.io.mem inst ptw of PTW connect ptw.clock, clock connect ptw.reset, reset invalidate ptw.io.mem.clock_enabled invalidate ptw.io.mem.keep_clock_enabled invalidate ptw.io.mem.perf.storeBufferEmptyAfterStore invalidate ptw.io.mem.perf.storeBufferEmptyAfterLoad invalidate ptw.io.mem.perf.canAcceptLoadThenLoad invalidate ptw.io.mem.perf.canAcceptStoreThenRMW invalidate ptw.io.mem.perf.canAcceptStoreThenLoad invalidate ptw.io.mem.perf.blocked invalidate ptw.io.mem.perf.tlbMiss invalidate ptw.io.mem.perf.grant invalidate ptw.io.mem.perf.release invalidate ptw.io.mem.perf.acquire invalidate ptw.io.mem.store_pending invalidate ptw.io.mem.ordered invalidate ptw.io.mem.s2_gpa_is_pte invalidate ptw.io.mem.s2_gpa invalidate ptw.io.mem.s2_xcpt.ae.st invalidate ptw.io.mem.s2_xcpt.ae.ld invalidate ptw.io.mem.s2_xcpt.gf.st invalidate ptw.io.mem.s2_xcpt.gf.ld invalidate ptw.io.mem.s2_xcpt.pf.st invalidate ptw.io.mem.s2_xcpt.pf.ld invalidate ptw.io.mem.s2_xcpt.ma.st invalidate ptw.io.mem.s2_xcpt.ma.ld invalidate ptw.io.mem.replay_next invalidate ptw.io.mem.resp.bits.store_data invalidate ptw.io.mem.resp.bits.data_raw invalidate ptw.io.mem.resp.bits.data_word_bypass invalidate ptw.io.mem.resp.bits.has_data invalidate ptw.io.mem.resp.bits.replay invalidate ptw.io.mem.resp.bits.mask invalidate ptw.io.mem.resp.bits.data invalidate ptw.io.mem.resp.bits.dv invalidate ptw.io.mem.resp.bits.dprv invalidate ptw.io.mem.resp.bits.signed invalidate ptw.io.mem.resp.bits.size invalidate ptw.io.mem.resp.bits.cmd invalidate ptw.io.mem.resp.bits.tag invalidate ptw.io.mem.resp.bits.addr invalidate ptw.io.mem.resp.valid invalidate ptw.io.mem.s2_paddr invalidate ptw.io.mem.s2_uncached invalidate ptw.io.mem.s2_kill invalidate ptw.io.mem.s2_nack_cause_raw invalidate ptw.io.mem.s2_nack invalidate ptw.io.mem.s1_data.mask invalidate ptw.io.mem.s1_data.data invalidate ptw.io.mem.s1_kill invalidate ptw.io.mem.req.bits.mask invalidate ptw.io.mem.req.bits.data invalidate ptw.io.mem.req.bits.no_xcpt invalidate ptw.io.mem.req.bits.no_alloc invalidate ptw.io.mem.req.bits.no_resp invalidate ptw.io.mem.req.bits.phys invalidate ptw.io.mem.req.bits.dv invalidate ptw.io.mem.req.bits.dprv invalidate ptw.io.mem.req.bits.signed invalidate ptw.io.mem.req.bits.size invalidate ptw.io.mem.req.bits.cmd invalidate ptw.io.mem.req.bits.tag invalidate ptw.io.mem.req.bits.addr invalidate ptw.io.mem.req.valid invalidate ptw.io.mem.req.ready inst core of Rocket connect core.clock, clock connect core.reset, reset invalidate core.io.reset_vector connect haltNodeOut[0], UInt<1>(0h0) connect ceaseNodeOut[0], UInt<1>(0h0) regreset wfiNodeOut_0_REG : UInt<1>, clock, reset, UInt<1>(0h0) connect wfiNodeOut_0_REG, core.io.wfi connect wfiNodeOut[0], wfiNodeOut_0_REG connect core.io.interrupts.debug, intSinkNodeIn[0] connect core.io.interrupts.msip, intSinkNodeIn[1] connect core.io.interrupts.mtip, intSinkNodeIn[2] connect core.io.interrupts.meip, intSinkNodeIn[3] connect core.io.interrupts.seip, intSinkNodeIn[4] connect traceSourceNodeOut, core.io.trace connect core.io.traceStall, traceAuxSinkNodeIn.stall connect bpwatchSourceNodeOut, core.io.bpwatch connect core.io.hartid, hartIdSinkNodeIn connect frontend.io.cpu, core.io.imem connect fpuOpt.io.keep_clock_enabled, core.io.fpu.keep_clock_enabled connect core.io.fpu.sboard_clra, fpuOpt.io.sboard_clra connect core.io.fpu.sboard_clr, fpuOpt.io.sboard_clr connect core.io.fpu.sboard_set, fpuOpt.io.sboard_set connect core.io.fpu.dec.vec, fpuOpt.io.dec.vec connect core.io.fpu.dec.wflags, fpuOpt.io.dec.wflags connect core.io.fpu.dec.sqrt, fpuOpt.io.dec.sqrt connect core.io.fpu.dec.div, fpuOpt.io.dec.div connect core.io.fpu.dec.fma, fpuOpt.io.dec.fma connect core.io.fpu.dec.fastpipe, fpuOpt.io.dec.fastpipe connect core.io.fpu.dec.toint, fpuOpt.io.dec.toint connect core.io.fpu.dec.fromint, fpuOpt.io.dec.fromint connect core.io.fpu.dec.typeTagOut, fpuOpt.io.dec.typeTagOut connect core.io.fpu.dec.typeTagIn, fpuOpt.io.dec.typeTagIn connect core.io.fpu.dec.swap23, fpuOpt.io.dec.swap23 connect core.io.fpu.dec.swap12, fpuOpt.io.dec.swap12 connect core.io.fpu.dec.ren3, fpuOpt.io.dec.ren3 connect core.io.fpu.dec.ren2, fpuOpt.io.dec.ren2 connect core.io.fpu.dec.ren1, fpuOpt.io.dec.ren1 connect core.io.fpu.dec.wen, fpuOpt.io.dec.wen connect core.io.fpu.dec.ldst, fpuOpt.io.dec.ldst connect fpuOpt.io.killm, core.io.fpu.killm connect fpuOpt.io.killx, core.io.fpu.killx connect core.io.fpu.illegal_rm, fpuOpt.io.illegal_rm connect core.io.fpu.nack_mem, fpuOpt.io.nack_mem connect core.io.fpu.fcsr_rdy, fpuOpt.io.fcsr_rdy connect fpuOpt.io.valid, core.io.fpu.valid connect fpuOpt.io.ll_resp_data, core.io.fpu.ll_resp_data connect fpuOpt.io.ll_resp_tag, core.io.fpu.ll_resp_tag connect fpuOpt.io.ll_resp_type, core.io.fpu.ll_resp_type connect fpuOpt.io.ll_resp_val, core.io.fpu.ll_resp_val connect core.io.fpu.toint_data, fpuOpt.io.toint_data connect core.io.fpu.store_data, fpuOpt.io.store_data connect fpuOpt.io.v_sew, core.io.fpu.v_sew connect core.io.fpu.fcsr_flags.bits, fpuOpt.io.fcsr_flags.bits connect core.io.fpu.fcsr_flags.valid, fpuOpt.io.fcsr_flags.valid connect fpuOpt.io.fcsr_rm, core.io.fpu.fcsr_rm connect fpuOpt.io.fromint_data, core.io.fpu.fromint_data connect fpuOpt.io.inst, core.io.fpu.inst connect fpuOpt.io.time, core.io.fpu.time connect fpuOpt.io.hartid, core.io.fpu.hartid connect core.io.ptw, ptw.io.dpath connect core.io.rocc.cmd.ready, UInt<1>(0h0) connect core.io.rocc.resp.valid, UInt<1>(0h0) invalidate core.io.rocc.resp.bits.data invalidate core.io.rocc.resp.bits.rd invalidate core.io.rocc.busy invalidate core.io.rocc.interrupt invalidate core.io.rocc.mem.clock_enabled invalidate core.io.rocc.mem.keep_clock_enabled invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterStore invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterLoad invalidate core.io.rocc.mem.perf.canAcceptLoadThenLoad invalidate core.io.rocc.mem.perf.canAcceptStoreThenRMW invalidate core.io.rocc.mem.perf.canAcceptStoreThenLoad invalidate core.io.rocc.mem.perf.blocked invalidate core.io.rocc.mem.perf.tlbMiss invalidate core.io.rocc.mem.perf.grant invalidate core.io.rocc.mem.perf.release invalidate core.io.rocc.mem.perf.acquire invalidate core.io.rocc.mem.store_pending invalidate core.io.rocc.mem.ordered invalidate core.io.rocc.mem.s2_gpa_is_pte invalidate core.io.rocc.mem.s2_gpa invalidate core.io.rocc.mem.s2_xcpt.ae.st invalidate core.io.rocc.mem.s2_xcpt.ae.ld invalidate core.io.rocc.mem.s2_xcpt.gf.st invalidate core.io.rocc.mem.s2_xcpt.gf.ld invalidate core.io.rocc.mem.s2_xcpt.pf.st invalidate core.io.rocc.mem.s2_xcpt.pf.ld invalidate core.io.rocc.mem.s2_xcpt.ma.st invalidate core.io.rocc.mem.s2_xcpt.ma.ld invalidate core.io.rocc.mem.replay_next invalidate core.io.rocc.mem.resp.bits.store_data invalidate core.io.rocc.mem.resp.bits.data_raw invalidate core.io.rocc.mem.resp.bits.data_word_bypass invalidate core.io.rocc.mem.resp.bits.has_data invalidate core.io.rocc.mem.resp.bits.replay invalidate core.io.rocc.mem.resp.bits.mask invalidate core.io.rocc.mem.resp.bits.data invalidate core.io.rocc.mem.resp.bits.dv invalidate core.io.rocc.mem.resp.bits.dprv invalidate core.io.rocc.mem.resp.bits.signed invalidate core.io.rocc.mem.resp.bits.size invalidate core.io.rocc.mem.resp.bits.cmd invalidate core.io.rocc.mem.resp.bits.tag invalidate core.io.rocc.mem.resp.bits.addr invalidate core.io.rocc.mem.resp.valid invalidate core.io.rocc.mem.s2_paddr invalidate core.io.rocc.mem.s2_uncached invalidate core.io.rocc.mem.s2_kill invalidate core.io.rocc.mem.s2_nack_cause_raw invalidate core.io.rocc.mem.s2_nack invalidate core.io.rocc.mem.s1_data.mask invalidate core.io.rocc.mem.s1_data.data invalidate core.io.rocc.mem.s1_kill invalidate core.io.rocc.mem.req.bits.mask invalidate core.io.rocc.mem.req.bits.data invalidate core.io.rocc.mem.req.bits.no_xcpt invalidate core.io.rocc.mem.req.bits.no_alloc invalidate core.io.rocc.mem.req.bits.no_resp invalidate core.io.rocc.mem.req.bits.phys invalidate core.io.rocc.mem.req.bits.dv invalidate core.io.rocc.mem.req.bits.dprv invalidate core.io.rocc.mem.req.bits.signed invalidate core.io.rocc.mem.req.bits.size invalidate core.io.rocc.mem.req.bits.cmd invalidate core.io.rocc.mem.req.bits.tag invalidate core.io.rocc.mem.req.bits.addr invalidate core.io.rocc.mem.req.valid invalidate core.io.rocc.mem.req.ready connect dcacheArb.io.requestor[0], ptw.io.mem connect dcacheArb.io.requestor[1], core.io.dmem connect ptw.io.requestor[0], dcache.io.ptw connect ptw.io.requestor[1], frontend.io.ptw
module RocketTile( // @[RocketTile.scala:141:7] input clock, // @[RocketTile.scala:141:7] input reset, // @[RocketTile.scala:141:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_wfi_out_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25] output [31:0] auto_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25] output [2:0] auto_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25] input [2:0] auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] broadcast_2_auto_in_0_action; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_valid_0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9] wire _core_io_imem_might_request; // @[RocketTile.scala:147:20] wire _core_io_imem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_imem_req_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_req_bits_speculative; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_imem_resp_ready; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_valid; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_taken; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_mask; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bridx; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_prediction_target; // @[RocketTile.scala:147:20] wire [4:0] _core_io_imem_btb_update_bits_prediction_entry; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_btb_update_bits_prediction_bht_history; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bht_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_pc; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_target; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_isValid; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_br_pc; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_valid; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_bht_update_bits_prediction_history; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_prediction_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_bht_update_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_branch; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_taken; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_mispredict; // @[RocketTile.scala:147:20] wire _core_io_imem_flush_icache; // @[RocketTile.scala:147:20] wire _core_io_imem_progress; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_dmem_req_bits_addr; // @[RocketTile.scala:147:20] wire [6:0] _core_io_dmem_req_bits_tag; // @[RocketTile.scala:147:20] wire [4:0] _core_io_dmem_req_bits_cmd; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_size; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_signed; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_dprv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_dv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_no_resp; // @[RocketTile.scala:147:20] wire _core_io_dmem_s1_kill; // @[RocketTile.scala:147:20] wire [63:0] _core_io_dmem_s1_data_data; // @[RocketTile.scala:147:20] wire _core_io_dmem_keep_clock_enabled; // @[RocketTile.scala:147:20] wire [3:0] _core_io_ptw_ptbr_mode; // @[RocketTile.scala:147:20] wire [43:0] _core_io_ptw_ptbr_ppn; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_ptw_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_status_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_v; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sd; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_mpp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spvp; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spv; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_gstatus_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_v; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sd; // @[RocketTile.scala:147:20] wire [22:0] _core_io_ptw_gstatus_zero2; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mbe; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sbe; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_sxl; // @[RocketTile.scala:147:20] wire [7:0] _core_io_ptw_gstatus_zero1; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_mpp; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_vs; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_ube; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_upie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_hie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_uie; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_0_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_0_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_1_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_1_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_2_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_2_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_3_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_3_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_4_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_4_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_5_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_5_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_6_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_6_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_7_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_7_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_value; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_hartid; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_time; // @[RocketTile.scala:147:20] wire [31:0] _core_io_fpu_inst; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_fromint_data; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_fcsr_rm; // @[RocketTile.scala:147:20] wire _core_io_fpu_ll_resp_val; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_ll_resp_type; // @[RocketTile.scala:147:20] wire [4:0] _core_io_fpu_ll_resp_tag; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_ll_resp_data; // @[RocketTile.scala:147:20] wire _core_io_fpu_valid; // @[RocketTile.scala:147:20] wire _core_io_fpu_killx; // @[RocketTile.scala:147:20] wire _core_io_fpu_killm; // @[RocketTile.scala:147:20] wire _core_io_fpu_keep_clock_enabled; // @[RocketTile.scala:147:20] wire _core_io_wfi; // @[RocketTile.scala:147:20] wire _ptw_io_requestor_0_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sd; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sd; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_0_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_0_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sd; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sd; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_1_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_1_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_mem_req_valid; // @[PTW.scala:802:19] wire [39:0] _ptw_io_mem_req_bits_addr; // @[PTW.scala:802:19] wire _ptw_io_mem_req_bits_dv; // @[PTW.scala:802:19] wire _ptw_io_mem_s1_kill; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_miss; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_hit; // @[PTW.scala:802:19] wire _ptw_io_dpath_clock_enabled; // @[PTW.scala:802:19] wire _dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_0_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_0_resp_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_requestor_0_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_0_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_0_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_0_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_1_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_1_resp_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_1_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_1_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_dv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_phys; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_no_resp; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_s1_kill; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_keep_clock_enabled; // @[HellaCache.scala:292:25] wire _fpuOpt_io_fcsr_flags_valid; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_fcsr_flags_bits; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_store_data; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_toint_data; // @[RocketTile.scala:242:62] wire _fpuOpt_io_fcsr_rdy; // @[RocketTile.scala:242:62] wire _fpuOpt_io_nack_mem; // @[RocketTile.scala:242:62] wire _fpuOpt_io_illegal_rm; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ldst; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wen; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren1; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren2; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren3; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap12; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap23; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagIn; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagOut; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fromint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_toint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fastpipe; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fma; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_div; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_sqrt; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wflags; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_vec; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_set; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_clr; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_sboard_clra; // @[RocketTile.scala:242:62] wire _frontend_io_cpu_resp_valid; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_cfiType; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_taken; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bridx; // @[Frontend.scala:393:28] wire [38:0] _frontend_io_cpu_resp_bits_btb_target; // @[Frontend.scala:393:28] wire [4:0] _frontend_io_cpu_resp_bits_btb_entry; // @[Frontend.scala:393:28] wire [7:0] _frontend_io_cpu_resp_bits_btb_bht_history; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bht_value; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_resp_bits_pc; // @[Frontend.scala:393:28] wire [31:0] _frontend_io_cpu_resp_bits_data; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_pf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_gf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_replay; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_valid; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_gpa_bits; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_is_pte; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_npc; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_acquire; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_tlbMiss; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_valid; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_valid; // @[Frontend.scala:393:28] wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[Frontend.scala:393:28] wire _dcache_io_cpu_req_ready; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack_cause_raw; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_uncached; // @[HellaCache.scala:278:43] wire [31:0] _dcache_io_cpu_s2_paddr; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_valid; // @[HellaCache.scala:278:43] wire [39:0] _dcache_io_cpu_resp_bits_addr; // @[HellaCache.scala:278:43] wire [6:0] _dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala:278:43] wire [4:0] _dcache_io_cpu_resp_bits_cmd; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_size; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_signed; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_dprv; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_dv; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data; // @[HellaCache.scala:278:43] wire [7:0] _dcache_io_cpu_resp_bits_mask; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_store_data; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_replay_next; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala:278:43] wire [39:0] _dcache_io_cpu_s2_gpa; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_ordered; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_store_pending; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_acquire; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_release; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_grant; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_tlbMiss; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_blocked; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_valid; // @[HellaCache.scala:278:43] wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[HellaCache.scala:278:43] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[RocketTile.scala:141:7] wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[RocketTile.scala:141:7] wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[RocketTile.scala:141:7] wire [2:0] auto_hartid_in_0 = auto_hartid_in; // @[RocketTile.scala:141:7] wire auto_buffer_out_a_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_cease_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_halt_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[RocketTile.scala:141:7] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire broadcast_2_auto_in_0_rvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_wvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_ivalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_2_nodeIn_0_rvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_wvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_ivalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire buffer_auto_in_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17] wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17] wire bpwatchSourceNodeOut_0_rvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_wvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_ivalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_in_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_out_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonOut_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonIn_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonIn_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [31:0] auto_reset_vector_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorIn = 32'h10000; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire buffer_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_b_valid = auto_buffer_out_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_b_bits_opcode = auto_buffer_out_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_b_bits_param = auto_buffer_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_b_bits_size = auto_buffer_out_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_b_bits_source = auto_buffer_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_b_bits_address = auto_buffer_out_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_b_bits_mask = auto_buffer_out_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_b_bits_data = auto_buffer_out_b_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_b_bits_corrupt = auto_buffer_out_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_ready = auto_buffer_out_c_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_ready = auto_buffer_out_e_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] wire wfiNodeOut_0; // @[MixedNode.scala:542:17] wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[RocketTile.scala:141:7] wire int_localIn_0 = auto_int_local_in_0_0_0; // @[RocketTile.scala:141:7] wire traceSourceNodeOut_insns_0_valid; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_0_insn; // @[MixedNode.scala:542:17] wire [2:0] traceSourceNodeOut_insns_0_priv; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_exception; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_insns_0_cause; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_tval; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17] wire [2:0] hartidIn = auto_hartid_in_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_c_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_c_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_c_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_c_bits_address_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_c_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_e_bits_sink_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_e_valid_0; // @[RocketTile.scala:141:7] wire auto_wfi_out_0_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] wire [2:0] auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] wire [2:0] hartidOut; // @[MixedNode.scala:542:17] wire [2:0] broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17] wire [2:0] broadcast_nodeOut; // @[MixedNode.scala:542:17] wire [2:0] broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9] wire [2:0] hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17] assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] wire broadcast_2_nodeIn_0_valid_0 = broadcast_2_auto_in_0_valid_0; // @[MixedNode.scala:551:17] wire [2:0] bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire [2:0] broadcast_2_nodeIn_0_action = broadcast_2_auto_in_0_action; // @[MixedNode.scala:551:17] wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9] assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_b_ready = buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_b_valid = buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_b_bits_opcode = buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_b_bits_param = buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_b_bits_size = buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_b_bits_source = buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] tlOtherMastersNodeOut_b_bits_address = buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] tlOtherMastersNodeOut_b_bits_mask = buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] tlOtherMastersNodeOut_b_bits_data = buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_c_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_b_bits_corrupt = buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_c_ready = buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_c_valid = buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_opcode = buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_param = buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_c_bits_size = buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_c_bits_source = buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_c_bits_address = buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_c_bits_data = buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_param = buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] tlOtherMastersNodeOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_e_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_e_ready = buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_e_valid = buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_e_bits_sink = buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_valid_0 = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_opcode_0 = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_param_0 = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_size_0 = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_source_0 = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_address_0 = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_mask_0 = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_data_0 = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_b_ready_0 = buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_valid = buffer_auto_out_b_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_b_bits_opcode = buffer_auto_out_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_b_bits_param = buffer_auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_b_bits_size = buffer_auto_out_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_b_bits_source = buffer_auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_b_bits_address = buffer_auto_out_b_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_b_bits_mask = buffer_auto_out_b_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_b_bits_data = buffer_auto_out_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_bits_corrupt = buffer_auto_out_b_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_ready = buffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_valid_0 = buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_opcode_0 = buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_param_0 = buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_size_0 = buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_source_0 = buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_address_0 = buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_data_0 = buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_d_ready_0 = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_denied = buffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_ready = buffer_auto_out_e_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_valid_0 = buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_bits_sink_0 = buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_b_ready = buffer_nodeOut_b_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_b_valid = buffer_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_opcode = buffer_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_param = buffer_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_size = buffer_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_source = buffer_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_address = buffer_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_mask = buffer_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_data = buffer_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_corrupt = buffer_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_c_ready = buffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_c_valid = buffer_nodeOut_c_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_opcode = buffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_param = buffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_size = buffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_source = buffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_address = buffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_data = buffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_e_ready = buffer_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_e_valid = buffer_nodeOut_e_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_e_bits_sink = buffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_b_ready = buffer_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_b_valid = buffer_nodeIn_b_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_opcode = buffer_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_param = buffer_nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_size = buffer_nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_source = buffer_nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_address = buffer_nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_mask = buffer_nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_data = buffer_nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_corrupt = buffer_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_c_ready = buffer_nodeIn_c_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_c_valid = buffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_opcode = buffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_param = buffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_size = buffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_source = buffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_address = buffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_data = buffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_e_ready = buffer_nodeIn_e_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_e_valid = buffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_e_bits_sink = buffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_valid = tlOtherMastersNodeOut_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_b_ready = tlOtherMastersNodeOut_b_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_b_valid = tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_b_bits_opcode = tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_b_bits_param = tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_b_bits_size = tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_b_bits_source = tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlOtherMastersNodeIn_b_bits_address = tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] tlOtherMastersNodeIn_b_bits_mask = tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlOtherMastersNodeIn_b_bits_data = tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_b_bits_corrupt = tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_ready = tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_valid = tlOtherMastersNodeOut_c_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_opcode = tlOtherMastersNodeOut_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_param = tlOtherMastersNodeOut_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_size = tlOtherMastersNodeOut_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_source = tlOtherMastersNodeOut_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_address = tlOtherMastersNodeOut_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_data = tlOtherMastersNodeOut_c_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_d_ready = tlOtherMastersNodeOut_d_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_e_ready = tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_valid = tlOtherMastersNodeOut_e_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_bits_sink = tlOtherMastersNodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_ready = tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_valid = tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_opcode = tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_param = tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_size = tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_source = tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_address = tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_data = tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_valid = tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_bits_sink = tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17] assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17] assign auto_trace_source_out_insns_0_valid_0 = traceSourceNodeOut_insns_0_valid; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr_0 = traceSourceNodeOut_insns_0_iaddr; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn_0 = traceSourceNodeOut_insns_0_insn; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv_0 = traceSourceNodeOut_insns_0_priv; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception_0 = traceSourceNodeOut_insns_0_exception; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt_0 = traceSourceNodeOut_insns_0_interrupt; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause_0 = traceSourceNodeOut_insns_0_cause; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval_0 = traceSourceNodeOut_insns_0_tval; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[RocketTile.scala:141:7] assign broadcast_2_auto_in_0_valid_0 = bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] assign broadcast_2_auto_in_0_action = bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1; // @[MixedNode.scala:542:17] wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17] assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17] wire intSinkNodeIn_0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_1; // @[MixedNode.scala:551:17] wire intSinkNodeIn_2; // @[MixedNode.scala:551:17] wire intSinkNodeIn_3; // @[MixedNode.scala:551:17] wire intSinkNodeIn_4; // @[MixedNode.scala:551:17] assign auto_wfi_out_0_0 = wfiNodeOut_0; // @[RocketTile.scala:141:7] reg wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] assign wfiNodeOut_0 = wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] always @(posedge clock) begin // @[RocketTile.scala:141:7] if (reset) // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= 1'h0; // @[Interrupts.scala:131:36] else // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= _core_io_wfi; // @[RocketTile.scala:147:20] always @(posedge) TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c tlMasterXbar ( // @[HierarchicalElement.scala:55:42] .clock (clock), .reset (reset), .auto_anon_in_1_a_ready (widget_1_auto_anon_out_a_ready), .auto_anon_in_1_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_1_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_1_d_valid (widget_1_auto_anon_out_d_valid), .auto_anon_in_1_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode), .auto_anon_in_1_d_bits_param (widget_1_auto_anon_out_d_bits_param), .auto_anon_in_1_d_bits_size (widget_1_auto_anon_out_d_bits_size), .auto_anon_in_1_d_bits_sink (widget_1_auto_anon_out_d_bits_sink), .auto_anon_in_1_d_bits_denied (widget_1_auto_anon_out_d_bits_denied), .auto_anon_in_1_d_bits_data (widget_1_auto_anon_out_d_bits_data), .auto_anon_in_1_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_a_ready (widget_auto_anon_out_a_ready), .auto_anon_in_0_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_ready (widget_auto_anon_out_b_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_valid (widget_auto_anon_out_b_valid), .auto_anon_in_0_b_bits_opcode (widget_auto_anon_out_b_bits_opcode), .auto_anon_in_0_b_bits_param (widget_auto_anon_out_b_bits_param), .auto_anon_in_0_b_bits_size (widget_auto_anon_out_b_bits_size), .auto_anon_in_0_b_bits_source (widget_auto_anon_out_b_bits_source), .auto_anon_in_0_b_bits_address (widget_auto_anon_out_b_bits_address), .auto_anon_in_0_b_bits_mask (widget_auto_anon_out_b_bits_mask), .auto_anon_in_0_b_bits_data (widget_auto_anon_out_b_bits_data), .auto_anon_in_0_b_bits_corrupt (widget_auto_anon_out_b_bits_corrupt), .auto_anon_in_0_c_ready (widget_auto_anon_out_c_ready), .auto_anon_in_0_c_valid (widget_auto_anon_out_c_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_opcode (widget_auto_anon_out_c_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_param (widget_auto_anon_out_c_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_size (widget_auto_anon_out_c_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_source (widget_auto_anon_out_c_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_address (widget_auto_anon_out_c_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_data (widget_auto_anon_out_c_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_valid (widget_auto_anon_out_d_valid), .auto_anon_in_0_d_bits_opcode (widget_auto_anon_out_d_bits_opcode), .auto_anon_in_0_d_bits_param (widget_auto_anon_out_d_bits_param), .auto_anon_in_0_d_bits_size (widget_auto_anon_out_d_bits_size), .auto_anon_in_0_d_bits_source (widget_auto_anon_out_d_bits_source), .auto_anon_in_0_d_bits_sink (widget_auto_anon_out_d_bits_sink), .auto_anon_in_0_d_bits_denied (widget_auto_anon_out_d_bits_denied), .auto_anon_in_0_d_bits_data (widget_auto_anon_out_d_bits_data), .auto_anon_in_0_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_e_ready (widget_auto_anon_out_e_ready), .auto_anon_in_0_e_valid (widget_auto_anon_out_e_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_e_bits_sink (widget_auto_anon_out_e_bits_sink), // @[WidthWidget.scala:27:9] .auto_anon_out_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_anon_out_a_valid (tlOtherMastersNodeIn_a_valid), .auto_anon_out_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode), .auto_anon_out_a_bits_param (tlOtherMastersNodeIn_a_bits_param), .auto_anon_out_a_bits_size (tlOtherMastersNodeIn_a_bits_size), .auto_anon_out_a_bits_source (tlOtherMastersNodeIn_a_bits_source), .auto_anon_out_a_bits_address (tlOtherMastersNodeIn_a_bits_address), .auto_anon_out_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask), .auto_anon_out_a_bits_data (tlOtherMastersNodeIn_a_bits_data), .auto_anon_out_b_ready (tlOtherMastersNodeIn_b_ready), .auto_anon_out_b_valid (tlOtherMastersNodeIn_b_valid), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_opcode (tlOtherMastersNodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_param (tlOtherMastersNodeIn_b_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_size (tlOtherMastersNodeIn_b_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_source (tlOtherMastersNodeIn_b_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_address (tlOtherMastersNodeIn_b_bits_address), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_mask (tlOtherMastersNodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_data (tlOtherMastersNodeIn_b_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_corrupt (tlOtherMastersNodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_c_ready (tlOtherMastersNodeIn_c_ready), // @[MixedNode.scala:551:17] .auto_anon_out_c_valid (tlOtherMastersNodeIn_c_valid), .auto_anon_out_c_bits_opcode (tlOtherMastersNodeIn_c_bits_opcode), .auto_anon_out_c_bits_param (tlOtherMastersNodeIn_c_bits_param), .auto_anon_out_c_bits_size (tlOtherMastersNodeIn_c_bits_size), .auto_anon_out_c_bits_source (tlOtherMastersNodeIn_c_bits_source), .auto_anon_out_c_bits_address (tlOtherMastersNodeIn_c_bits_address), .auto_anon_out_c_bits_data (tlOtherMastersNodeIn_c_bits_data), .auto_anon_out_d_ready (tlOtherMastersNodeIn_d_ready), .auto_anon_out_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_e_ready (tlOtherMastersNodeIn_e_ready), // @[MixedNode.scala:551:17] .auto_anon_out_e_valid (tlOtherMastersNodeIn_e_valid), .auto_anon_out_e_bits_sink (tlOtherMastersNodeIn_e_bits_sink) ); // @[HierarchicalElement.scala:55:42] TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u tlSlaveXbar ( // @[HierarchicalElement.scala:56:41] .clock (clock), .reset (reset) ); // @[HierarchicalElement.scala:56:41] IntXbar_i4_o1 intXbar ( // @[HierarchicalElement.scala:57:37] .auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17] .auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17] .auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_out_0 (intSinkNodeIn_0), .auto_anon_out_1 (intSinkNodeIn_1), .auto_anon_out_2 (intSinkNodeIn_2), .auto_anon_out_3 (intSinkNodeIn_3), .auto_anon_out_4 (intSinkNodeIn_4) ); // @[HierarchicalElement.scala:57:37] DCache dcache ( // @[HellaCache.scala:278:43] .clock (clock), .reset (reset), .auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_out_a_valid (widget_auto_anon_in_a_valid), .auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (widget_auto_anon_in_a_bits_param), .auto_out_a_bits_size (widget_auto_anon_in_a_bits_size), .auto_out_a_bits_source (widget_auto_anon_in_a_bits_source), .auto_out_a_bits_address (widget_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (widget_auto_anon_in_a_bits_data), .auto_out_b_ready (widget_auto_anon_in_b_ready), .auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9] .auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9] .auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9] .auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9] .auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9] .auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9] .auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9] .auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9] .auto_out_c_valid (widget_auto_anon_in_c_valid), .auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode), .auto_out_c_bits_param (widget_auto_anon_in_c_bits_param), .auto_out_c_bits_size (widget_auto_anon_in_c_bits_size), .auto_out_c_bits_source (widget_auto_anon_in_c_bits_source), .auto_out_c_bits_address (widget_auto_anon_in_c_bits_address), .auto_out_c_bits_data (widget_auto_anon_in_c_bits_data), .auto_out_d_ready (widget_auto_anon_in_d_ready), .auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9] .auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9] .auto_out_e_valid (widget_auto_anon_in_e_valid), .auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink), .io_cpu_req_ready (_dcache_io_cpu_req_ready), .io_cpu_req_valid (_dcacheArb_io_mem_req_valid), // @[HellaCache.scala:292:25] .io_cpu_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), // @[HellaCache.scala:292:25] .io_cpu_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), // @[HellaCache.scala:292:25] .io_cpu_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), // @[HellaCache.scala:292:25] .io_cpu_req_bits_size (_dcacheArb_io_mem_req_bits_size), // @[HellaCache.scala:292:25] .io_cpu_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), // @[HellaCache.scala:292:25] .io_cpu_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), // @[HellaCache.scala:292:25] .io_cpu_s1_kill (_dcacheArb_io_mem_s1_kill), // @[HellaCache.scala:292:25] .io_cpu_s1_data_data (_dcacheArb_io_mem_s1_data_data), // @[HellaCache.scala:292:25] .io_cpu_s1_data_mask (8'h0), // @[RocketTile.scala:147:20] .io_cpu_s2_nack (_dcache_io_cpu_s2_nack), .io_cpu_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), .io_cpu_s2_uncached (_dcache_io_cpu_s2_uncached), .io_cpu_s2_paddr (_dcache_io_cpu_s2_paddr), .io_cpu_resp_valid (_dcache_io_cpu_resp_valid), .io_cpu_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), .io_cpu_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), .io_cpu_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), .io_cpu_resp_bits_size (_dcache_io_cpu_resp_bits_size), .io_cpu_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), .io_cpu_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), .io_cpu_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), .io_cpu_resp_bits_data (_dcache_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), .io_cpu_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), .io_cpu_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), .io_cpu_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), .io_cpu_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), .io_cpu_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), .io_cpu_replay_next (_dcache_io_cpu_replay_next), .io_cpu_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), .io_cpu_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), .io_cpu_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), .io_cpu_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), .io_cpu_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), .io_cpu_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), .io_cpu_s2_gpa (_dcache_io_cpu_s2_gpa), .io_cpu_ordered (_dcache_io_cpu_ordered), .io_cpu_store_pending (_dcache_io_cpu_store_pending), .io_cpu_perf_acquire (_dcache_io_cpu_perf_acquire), .io_cpu_perf_release (_dcache_io_cpu_perf_release), .io_cpu_perf_grant (_dcache_io_cpu_perf_grant), .io_cpu_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), .io_cpu_perf_blocked (_dcache_io_cpu_perf_blocked), .io_cpu_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), .io_cpu_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), .io_cpu_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), .io_cpu_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), .io_cpu_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), .io_cpu_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled), // @[HellaCache.scala:292:25] .io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_dcache_io_ptw_req_valid), .io_ptw_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_0_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[PTW.scala:802:19] .io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_0_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_sd (_ptw_io_requestor_0_gstatus_sd), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[HellaCache.scala:278:43] Frontend frontend ( // @[Frontend.scala:393:28] .clock (clock), .reset (reset), .auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid), .auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address), .auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .io_cpu_might_request (_core_io_imem_might_request), // @[RocketTile.scala:147:20] .io_cpu_req_valid (_core_io_imem_req_valid), // @[RocketTile.scala:147:20] .io_cpu_req_bits_pc (_core_io_imem_req_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_req_bits_speculative (_core_io_imem_req_bits_speculative), // @[RocketTile.scala:147:20] .io_cpu_sfence_valid (_core_io_imem_sfence_valid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_addr (_core_io_imem_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_asid (_core_io_imem_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hv (_core_io_imem_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hg (_core_io_imem_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_cpu_resp_ready (_core_io_imem_resp_ready), // @[RocketTile.scala:147:20] .io_cpu_resp_valid (_frontend_io_cpu_resp_valid), .io_cpu_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), .io_cpu_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), .io_cpu_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), .io_cpu_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), .io_cpu_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), .io_cpu_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), .io_cpu_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), .io_cpu_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), .io_cpu_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), .io_cpu_resp_bits_data (_frontend_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), .io_cpu_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), .io_cpu_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), .io_cpu_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), .io_cpu_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), .io_cpu_gpa_valid (_frontend_io_cpu_gpa_valid), .io_cpu_gpa_bits (_frontend_io_cpu_gpa_bits), .io_cpu_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), .io_cpu_btb_update_valid (_core_io_imem_btb_update_valid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_target (_core_io_imem_btb_update_bits_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), // @[RocketTile.scala:147:20] .io_cpu_bht_update_valid (_core_io_imem_bht_update_valid), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), // @[RocketTile.scala:147:20] .io_cpu_flush_icache (_core_io_imem_flush_icache), // @[RocketTile.scala:147:20] .io_cpu_npc (_frontend_io_cpu_npc), .io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire), .io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), .io_cpu_progress (_core_io_imem_progress), // @[RocketTile.scala:147:20] .io_ptw_req_ready (_ptw_io_requestor_1_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_frontend_io_ptw_req_valid), .io_ptw_req_bits_valid (_frontend_io_ptw_req_bits_valid), .io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_1_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_1_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_1_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_1_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_1_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_1_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_1_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_1_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_1_status_v), // @[PTW.scala:802:19] .io_ptw_status_sd (_ptw_io_requestor_1_status_sd), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_1_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_1_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_1_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_1_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_1_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_1_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_1_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_1_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_1_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_1_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_1_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_1_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_1_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_1_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_1_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_1_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_sd (_ptw_io_requestor_1_gstatus_sd), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[Frontend.scala:393:28] TLFragmenter fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset) ); // @[Fragmenter.scala:345:34] FPU fpuOpt ( // @[RocketTile.scala:242:62] .clock (clock), .reset (reset), .io_hartid (_core_io_fpu_hartid), // @[RocketTile.scala:147:20] .io_time (_core_io_fpu_time), // @[RocketTile.scala:147:20] .io_inst (_core_io_fpu_inst), // @[RocketTile.scala:147:20] .io_fromint_data (_core_io_fpu_fromint_data), // @[RocketTile.scala:147:20] .io_fcsr_rm (_core_io_fpu_fcsr_rm), // @[RocketTile.scala:147:20] .io_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), .io_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), .io_store_data (_fpuOpt_io_store_data), .io_toint_data (_fpuOpt_io_toint_data), .io_ll_resp_val (_core_io_fpu_ll_resp_val), // @[RocketTile.scala:147:20] .io_ll_resp_type (_core_io_fpu_ll_resp_type), // @[RocketTile.scala:147:20] .io_ll_resp_tag (_core_io_fpu_ll_resp_tag), // @[RocketTile.scala:147:20] .io_ll_resp_data (_core_io_fpu_ll_resp_data), // @[RocketTile.scala:147:20] .io_valid (_core_io_fpu_valid), // @[RocketTile.scala:147:20] .io_fcsr_rdy (_fpuOpt_io_fcsr_rdy), .io_nack_mem (_fpuOpt_io_nack_mem), .io_illegal_rm (_fpuOpt_io_illegal_rm), .io_killx (_core_io_fpu_killx), // @[RocketTile.scala:147:20] .io_killm (_core_io_fpu_killm), // @[RocketTile.scala:147:20] .io_dec_ldst (_fpuOpt_io_dec_ldst), .io_dec_wen (_fpuOpt_io_dec_wen), .io_dec_ren1 (_fpuOpt_io_dec_ren1), .io_dec_ren2 (_fpuOpt_io_dec_ren2), .io_dec_ren3 (_fpuOpt_io_dec_ren3), .io_dec_swap12 (_fpuOpt_io_dec_swap12), .io_dec_swap23 (_fpuOpt_io_dec_swap23), .io_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), .io_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), .io_dec_fromint (_fpuOpt_io_dec_fromint), .io_dec_toint (_fpuOpt_io_dec_toint), .io_dec_fastpipe (_fpuOpt_io_dec_fastpipe), .io_dec_fma (_fpuOpt_io_dec_fma), .io_dec_div (_fpuOpt_io_dec_div), .io_dec_sqrt (_fpuOpt_io_dec_sqrt), .io_dec_wflags (_fpuOpt_io_dec_wflags), .io_dec_vec (_fpuOpt_io_dec_vec), .io_sboard_set (_fpuOpt_io_sboard_set), .io_sboard_clr (_fpuOpt_io_sboard_clr), .io_sboard_clra (_fpuOpt_io_sboard_clra), .io_keep_clock_enabled (_core_io_fpu_keep_clock_enabled) // @[RocketTile.scala:147:20] ); // @[RocketTile.scala:242:62] HellaCacheArbiter dcacheArb ( // @[HellaCache.scala:292:25] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_dcacheArb_io_requestor_0_req_ready), .io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[PTW.scala:802:19] .io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[PTW.scala:802:19] .io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[PTW.scala:802:19] .io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[PTW.scala:802:19] .io_requestor_0_s2_nack (_dcacheArb_io_requestor_0_s2_nack), .io_requestor_0_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), .io_requestor_0_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), .io_requestor_0_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), .io_requestor_0_resp_valid (_dcacheArb_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), .io_requestor_0_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), .io_requestor_0_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), .io_requestor_0_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), .io_requestor_0_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), .io_requestor_0_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), .io_requestor_0_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), .io_requestor_0_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), .io_requestor_0_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), .io_requestor_0_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), .io_requestor_0_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), .io_requestor_0_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), .io_requestor_0_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), .io_requestor_0_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), .io_requestor_0_replay_next (_dcacheArb_io_requestor_0_replay_next), .io_requestor_0_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), .io_requestor_0_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), .io_requestor_0_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), .io_requestor_0_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), .io_requestor_0_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), .io_requestor_0_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), .io_requestor_0_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), .io_requestor_0_ordered (_dcacheArb_io_requestor_0_ordered), .io_requestor_0_store_pending (_dcacheArb_io_requestor_0_store_pending), .io_requestor_0_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), .io_requestor_0_perf_release (_dcacheArb_io_requestor_0_perf_release), .io_requestor_0_perf_grant (_dcacheArb_io_requestor_0_perf_grant), .io_requestor_0_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), .io_requestor_0_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), .io_requestor_0_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), .io_requestor_0_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), .io_requestor_0_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), .io_requestor_0_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), .io_requestor_0_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), .io_requestor_1_req_ready (_dcacheArb_io_requestor_1_req_ready), .io_requestor_1_req_valid (_core_io_dmem_req_valid), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_addr (_core_io_dmem_req_bits_addr), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_tag (_core_io_dmem_req_bits_tag), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_cmd (_core_io_dmem_req_bits_cmd), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_size (_core_io_dmem_req_bits_size), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_signed (_core_io_dmem_req_bits_signed), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_dprv (_core_io_dmem_req_bits_dprv), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_dv (_core_io_dmem_req_bits_dv), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), // @[RocketTile.scala:147:20] .io_requestor_1_s1_kill (_core_io_dmem_s1_kill), // @[RocketTile.scala:147:20] .io_requestor_1_s1_data_data (_core_io_dmem_s1_data_data), // @[RocketTile.scala:147:20] .io_requestor_1_s2_nack (_dcacheArb_io_requestor_1_s2_nack), .io_requestor_1_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), .io_requestor_1_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), .io_requestor_1_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), .io_requestor_1_resp_valid (_dcacheArb_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), .io_requestor_1_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), .io_requestor_1_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), .io_requestor_1_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), .io_requestor_1_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), .io_requestor_1_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), .io_requestor_1_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), .io_requestor_1_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), .io_requestor_1_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), .io_requestor_1_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), .io_requestor_1_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), .io_requestor_1_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), .io_requestor_1_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), .io_requestor_1_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), .io_requestor_1_replay_next (_dcacheArb_io_requestor_1_replay_next), .io_requestor_1_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), .io_requestor_1_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), .io_requestor_1_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), .io_requestor_1_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), .io_requestor_1_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), .io_requestor_1_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), .io_requestor_1_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), .io_requestor_1_ordered (_dcacheArb_io_requestor_1_ordered), .io_requestor_1_store_pending (_dcacheArb_io_requestor_1_store_pending), .io_requestor_1_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), .io_requestor_1_perf_release (_dcacheArb_io_requestor_1_perf_release), .io_requestor_1_perf_grant (_dcacheArb_io_requestor_1_perf_grant), .io_requestor_1_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), .io_requestor_1_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), .io_requestor_1_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), .io_requestor_1_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), .io_requestor_1_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), .io_requestor_1_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), .io_requestor_1_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore), .io_requestor_1_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), // @[RocketTile.scala:147:20] .io_mem_req_ready (_dcache_io_cpu_req_ready), // @[HellaCache.scala:278:43] .io_mem_req_valid (_dcacheArb_io_mem_req_valid), .io_mem_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), .io_mem_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), .io_mem_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), .io_mem_req_bits_size (_dcacheArb_io_mem_req_bits_size), .io_mem_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), .io_mem_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), .io_mem_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), .io_mem_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), .io_mem_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), .io_mem_s1_kill (_dcacheArb_io_mem_s1_kill), .io_mem_s1_data_data (_dcacheArb_io_mem_s1_data_data), .io_mem_s2_nack (_dcache_io_cpu_s2_nack), // @[HellaCache.scala:278:43] .io_mem_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), // @[HellaCache.scala:278:43] .io_mem_s2_uncached (_dcache_io_cpu_s2_uncached), // @[HellaCache.scala:278:43] .io_mem_s2_paddr (_dcache_io_cpu_s2_paddr), // @[HellaCache.scala:278:43] .io_mem_resp_valid (_dcache_io_cpu_resp_valid), // @[HellaCache.scala:278:43] .io_mem_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), // @[HellaCache.scala:278:43] .io_mem_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), // @[HellaCache.scala:278:43] .io_mem_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), // @[HellaCache.scala:278:43] .io_mem_resp_bits_size (_dcache_io_cpu_resp_bits_size), // @[HellaCache.scala:278:43] .io_mem_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data (_dcache_io_cpu_resp_bits_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), // @[HellaCache.scala:278:43] .io_mem_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), // @[HellaCache.scala:278:43] .io_mem_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), // @[HellaCache.scala:278:43] .io_mem_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), // @[HellaCache.scala:278:43] .io_mem_replay_next (_dcache_io_cpu_replay_next), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), // @[HellaCache.scala:278:43] .io_mem_s2_gpa (_dcache_io_cpu_s2_gpa), // @[HellaCache.scala:278:43] .io_mem_ordered (_dcache_io_cpu_ordered), // @[HellaCache.scala:278:43] .io_mem_store_pending (_dcache_io_cpu_store_pending), // @[HellaCache.scala:278:43] .io_mem_perf_acquire (_dcache_io_cpu_perf_acquire), // @[HellaCache.scala:278:43] .io_mem_perf_release (_dcache_io_cpu_perf_release), // @[HellaCache.scala:278:43] .io_mem_perf_grant (_dcache_io_cpu_perf_grant), // @[HellaCache.scala:278:43] .io_mem_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), // @[HellaCache.scala:278:43] .io_mem_perf_blocked (_dcache_io_cpu_perf_blocked), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:278:43] .io_mem_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:278:43] .io_mem_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:278:43] .io_mem_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled) ); // @[HellaCache.scala:292:25] PTW ptw ( // @[PTW.scala:802:19] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready), .io_requestor_0_req_valid (_dcache_io_ptw_req_valid), // @[HellaCache.scala:278:43] .io_requestor_0_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), // @[HellaCache.scala:278:43] .io_requestor_0_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), // @[HellaCache.scala:278:43] .io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), .io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), .io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), .io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), .io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), .io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), .io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), .io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), .io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), .io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), .io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), .io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), .io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), .io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), .io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), .io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), .io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), .io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), .io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), .io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), .io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), .io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), .io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), .io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), .io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), .io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug), .io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease), .io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi), .io_requestor_0_status_isa (_ptw_io_requestor_0_status_isa), .io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv), .io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv), .io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv), .io_requestor_0_status_v (_ptw_io_requestor_0_status_v), .io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd), .io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv), .io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva), .io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr), .io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw), .io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm), .io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr), .io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum), .io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv), .io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs), .io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp), .io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp), .io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie), .io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie), .io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie), .io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie), .io_requestor_0_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), .io_requestor_0_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), .io_requestor_0_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), .io_requestor_0_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), .io_requestor_0_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), .io_requestor_0_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), .io_requestor_0_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), .io_requestor_0_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), .io_requestor_0_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), .io_requestor_0_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), .io_requestor_0_gstatus_v (_ptw_io_requestor_0_gstatus_v), .io_requestor_0_gstatus_sd (_ptw_io_requestor_0_gstatus_sd), .io_requestor_0_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), .io_requestor_0_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), .io_requestor_0_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), .io_requestor_0_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), .io_requestor_0_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), .io_requestor_0_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), .io_requestor_0_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), .io_requestor_0_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), .io_requestor_0_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), .io_requestor_0_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), .io_requestor_0_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), .io_requestor_0_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), .io_requestor_0_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), .io_requestor_0_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), .io_requestor_0_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), .io_requestor_0_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), .io_requestor_0_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), .io_requestor_0_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), .io_requestor_0_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), .io_requestor_0_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), .io_requestor_0_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), .io_requestor_0_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), .io_requestor_0_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), .io_requestor_0_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), .io_requestor_0_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), .io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), .io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), .io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), .io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), .io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), .io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), .io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), .io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), .io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), .io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), .io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), .io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), .io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), .io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), .io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), .io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), .io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), .io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), .io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), .io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), .io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), .io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), .io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), .io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), .io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), .io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), .io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), .io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), .io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), .io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), .io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), .io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), .io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), .io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), .io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), .io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), .io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), .io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), .io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), .io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), .io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), .io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), .io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), .io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), .io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), .io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), .io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), .io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), .io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), .io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), .io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), .io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), .io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), .io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), .io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), .io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), .io_requestor_0_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), .io_requestor_0_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), .io_requestor_0_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), .io_requestor_0_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), .io_requestor_0_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), .io_requestor_0_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), .io_requestor_0_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), .io_requestor_0_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), .io_requestor_0_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), .io_requestor_0_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), .io_requestor_0_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), .io_requestor_0_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), .io_requestor_0_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), .io_requestor_0_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), .io_requestor_0_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), .io_requestor_0_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value), .io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready), .io_requestor_1_req_valid (_frontend_io_ptw_req_valid), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_valid (_frontend_io_ptw_req_bits_valid), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[Frontend.scala:393:28] .io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), .io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), .io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), .io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), .io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), .io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), .io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), .io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), .io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), .io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), .io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), .io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), .io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), .io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), .io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), .io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), .io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), .io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), .io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), .io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), .io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), .io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), .io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), .io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), .io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), .io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug), .io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease), .io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi), .io_requestor_1_status_isa (_ptw_io_requestor_1_status_isa), .io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv), .io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv), .io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv), .io_requestor_1_status_v (_ptw_io_requestor_1_status_v), .io_requestor_1_status_sd (_ptw_io_requestor_1_status_sd), .io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv), .io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva), .io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr), .io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw), .io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm), .io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr), .io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum), .io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv), .io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs), .io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp), .io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp), .io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie), .io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie), .io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie), .io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie), .io_requestor_1_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), .io_requestor_1_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), .io_requestor_1_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), .io_requestor_1_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), .io_requestor_1_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), .io_requestor_1_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), .io_requestor_1_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), .io_requestor_1_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), .io_requestor_1_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), .io_requestor_1_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), .io_requestor_1_gstatus_v (_ptw_io_requestor_1_gstatus_v), .io_requestor_1_gstatus_sd (_ptw_io_requestor_1_gstatus_sd), .io_requestor_1_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), .io_requestor_1_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), .io_requestor_1_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), .io_requestor_1_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), .io_requestor_1_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), .io_requestor_1_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), .io_requestor_1_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), .io_requestor_1_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), .io_requestor_1_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), .io_requestor_1_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), .io_requestor_1_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), .io_requestor_1_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), .io_requestor_1_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), .io_requestor_1_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), .io_requestor_1_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), .io_requestor_1_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), .io_requestor_1_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), .io_requestor_1_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), .io_requestor_1_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), .io_requestor_1_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), .io_requestor_1_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), .io_requestor_1_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), .io_requestor_1_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), .io_requestor_1_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), .io_requestor_1_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), .io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), .io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), .io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), .io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), .io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), .io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), .io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), .io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), .io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), .io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), .io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), .io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), .io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), .io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), .io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), .io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), .io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), .io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), .io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), .io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), .io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), .io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), .io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), .io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), .io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), .io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), .io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), .io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), .io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), .io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), .io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), .io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), .io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), .io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), .io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), .io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), .io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), .io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), .io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), .io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), .io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), .io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), .io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), .io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), .io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), .io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), .io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), .io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), .io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), .io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), .io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), .io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), .io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), .io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), .io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), .io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), .io_requestor_1_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), .io_requestor_1_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), .io_requestor_1_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), .io_requestor_1_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), .io_requestor_1_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), .io_requestor_1_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), .io_requestor_1_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), .io_requestor_1_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), .io_requestor_1_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), .io_requestor_1_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), .io_requestor_1_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), .io_requestor_1_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), .io_requestor_1_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), .io_requestor_1_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), .io_requestor_1_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), .io_requestor_1_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value), .io_mem_req_ready (_dcacheArb_io_requestor_0_req_ready), // @[HellaCache.scala:292:25] .io_mem_req_valid (_ptw_io_mem_req_valid), .io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr), .io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv), .io_mem_s1_kill (_ptw_io_mem_s1_kill), .io_mem_s2_nack (_dcacheArb_io_requestor_0_s2_nack), // @[HellaCache.scala:292:25] .io_mem_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_mem_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), // @[HellaCache.scala:292:25] .io_mem_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), // @[HellaCache.scala:292:25] .io_mem_resp_valid (_dcacheArb_io_requestor_0_resp_valid), // @[HellaCache.scala:292:25] .io_mem_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), // @[HellaCache.scala:292:25] .io_mem_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), // @[HellaCache.scala:292:25] .io_mem_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_mem_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), // @[HellaCache.scala:292:25] .io_mem_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), // @[HellaCache.scala:292:25] .io_mem_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), // @[HellaCache.scala:292:25] .io_mem_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_mem_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_mem_replay_next (_dcacheArb_io_requestor_0_replay_next), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_mem_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), // @[HellaCache.scala:292:25] .io_mem_ordered (_dcacheArb_io_requestor_0_ordered), // @[HellaCache.scala:292:25] .io_mem_store_pending (_dcacheArb_io_requestor_0_store_pending), // @[HellaCache.scala:292:25] .io_mem_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), // @[HellaCache.scala:292:25] .io_mem_perf_release (_dcacheArb_io_requestor_0_perf_release), // @[HellaCache.scala:292:25] .io_mem_perf_grant (_dcacheArb_io_requestor_0_perf_grant), // @[HellaCache.scala:292:25] .io_mem_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_mem_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_mem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_mem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25] .io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[RocketTile.scala:147:20] .io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[RocketTile.scala:147:20] .io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_dpath_status_debug (_core_io_ptw_status_debug), // @[RocketTile.scala:147:20] .io_dpath_status_cease (_core_io_ptw_status_cease), // @[RocketTile.scala:147:20] .io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[RocketTile.scala:147:20] .io_dpath_status_isa (_core_io_ptw_status_isa), // @[RocketTile.scala:147:20] .io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[RocketTile.scala:147:20] .io_dpath_status_dv (_core_io_ptw_status_dv), // @[RocketTile.scala:147:20] .io_dpath_status_prv (_core_io_ptw_status_prv), // @[RocketTile.scala:147:20] .io_dpath_status_v (_core_io_ptw_status_v), // @[RocketTile.scala:147:20] .io_dpath_status_sd (_core_io_ptw_status_sd), // @[RocketTile.scala:147:20] .io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[RocketTile.scala:147:20] .io_dpath_status_gva (_core_io_ptw_status_gva), // @[RocketTile.scala:147:20] .io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[RocketTile.scala:147:20] .io_dpath_status_tw (_core_io_ptw_status_tw), // @[RocketTile.scala:147:20] .io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[RocketTile.scala:147:20] .io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[RocketTile.scala:147:20] .io_dpath_status_sum (_core_io_ptw_status_sum), // @[RocketTile.scala:147:20] .io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[RocketTile.scala:147:20] .io_dpath_status_fs (_core_io_ptw_status_fs), // @[RocketTile.scala:147:20] .io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[RocketTile.scala:147:20] .io_dpath_status_spp (_core_io_ptw_status_spp), // @[RocketTile.scala:147:20] .io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[RocketTile.scala:147:20] .io_dpath_status_spie (_core_io_ptw_status_spie), // @[RocketTile.scala:147:20] .io_dpath_status_mie (_core_io_ptw_status_mie), // @[RocketTile.scala:147:20] .io_dpath_status_sie (_core_io_ptw_status_sie), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spvp (_core_io_ptw_hstatus_spvp), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spv (_core_io_ptw_hstatus_spv), // @[RocketTile.scala:147:20] .io_dpath_hstatus_gva (_core_io_ptw_hstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_debug (_core_io_ptw_gstatus_debug), // @[RocketTile.scala:147:20] .io_dpath_gstatus_cease (_core_io_ptw_gstatus_cease), // @[RocketTile.scala:147:20] .io_dpath_gstatus_wfi (_core_io_ptw_gstatus_wfi), // @[RocketTile.scala:147:20] .io_dpath_gstatus_isa (_core_io_ptw_gstatus_isa), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dprv (_core_io_ptw_gstatus_dprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dv (_core_io_ptw_gstatus_dv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_prv (_core_io_ptw_gstatus_prv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_v (_core_io_ptw_gstatus_v), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sd (_core_io_ptw_gstatus_sd), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero2 (_core_io_ptw_gstatus_zero2), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpv (_core_io_ptw_gstatus_mpv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_gva (_core_io_ptw_gstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mbe (_core_io_ptw_gstatus_mbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sbe (_core_io_ptw_gstatus_sbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sxl (_core_io_ptw_gstatus_sxl), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero1 (_core_io_ptw_gstatus_zero1), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tsr (_core_io_ptw_gstatus_tsr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tw (_core_io_ptw_gstatus_tw), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tvm (_core_io_ptw_gstatus_tvm), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mxr (_core_io_ptw_gstatus_mxr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sum (_core_io_ptw_gstatus_sum), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mprv (_core_io_ptw_gstatus_mprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_fs (_core_io_ptw_gstatus_fs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpp (_core_io_ptw_gstatus_mpp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_vs (_core_io_ptw_gstatus_vs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spp (_core_io_ptw_gstatus_spp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpie (_core_io_ptw_gstatus_mpie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_ube (_core_io_ptw_gstatus_ube), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spie (_core_io_ptw_gstatus_spie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_upie (_core_io_ptw_gstatus_upie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mie (_core_io_ptw_gstatus_mie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_hie (_core_io_ptw_gstatus_hie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sie (_core_io_ptw_gstatus_sie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_uie (_core_io_ptw_gstatus_uie), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[RocketTile.scala:147:20] .io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), .io_dpath_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), .io_dpath_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), // @[RocketTile.scala:147:20] .io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled) ); // @[PTW.scala:802:19] Rocket core ( // @[RocketTile.scala:147:20] .clock (clock), .reset (reset), .io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17] .io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17] .io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17] .io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17] .io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17] .io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17] .io_imem_might_request (_core_io_imem_might_request), .io_imem_req_valid (_core_io_imem_req_valid), .io_imem_req_bits_pc (_core_io_imem_req_bits_pc), .io_imem_req_bits_speculative (_core_io_imem_req_bits_speculative), .io_imem_sfence_valid (_core_io_imem_sfence_valid), .io_imem_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), .io_imem_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), .io_imem_sfence_bits_addr (_core_io_imem_sfence_bits_addr), .io_imem_sfence_bits_asid (_core_io_imem_sfence_bits_asid), .io_imem_sfence_bits_hv (_core_io_imem_sfence_bits_hv), .io_imem_sfence_bits_hg (_core_io_imem_sfence_bits_hg), .io_imem_resp_ready (_core_io_imem_resp_ready), .io_imem_resp_valid (_frontend_io_cpu_resp_valid), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), // @[Frontend.scala:393:28] .io_imem_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), // @[Frontend.scala:393:28] .io_imem_resp_bits_data (_frontend_io_cpu_resp_bits_data), // @[Frontend.scala:393:28] .io_imem_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), // @[Frontend.scala:393:28] .io_imem_gpa_valid (_frontend_io_cpu_gpa_valid), // @[Frontend.scala:393:28] .io_imem_gpa_bits (_frontend_io_cpu_gpa_bits), // @[Frontend.scala:393:28] .io_imem_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), // @[Frontend.scala:393:28] .io_imem_btb_update_valid (_core_io_imem_btb_update_valid), .io_imem_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), .io_imem_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), .io_imem_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), .io_imem_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), .io_imem_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), .io_imem_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), .io_imem_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), .io_imem_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), .io_imem_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), .io_imem_btb_update_bits_target (_core_io_imem_btb_update_bits_target), .io_imem_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), .io_imem_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), .io_imem_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), .io_imem_bht_update_valid (_core_io_imem_bht_update_valid), .io_imem_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), .io_imem_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), .io_imem_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), .io_imem_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), .io_imem_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), .io_imem_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), .io_imem_flush_icache (_core_io_imem_flush_icache), .io_imem_npc (_frontend_io_cpu_npc), // @[Frontend.scala:393:28] .io_imem_perf_acquire (_frontend_io_cpu_perf_acquire), // @[Frontend.scala:393:28] .io_imem_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[Frontend.scala:393:28] .io_imem_progress (_core_io_imem_progress), .io_dmem_req_ready (_dcacheArb_io_requestor_1_req_ready), // @[HellaCache.scala:292:25] .io_dmem_req_valid (_core_io_dmem_req_valid), .io_dmem_req_bits_addr (_core_io_dmem_req_bits_addr), .io_dmem_req_bits_tag (_core_io_dmem_req_bits_tag), .io_dmem_req_bits_cmd (_core_io_dmem_req_bits_cmd), .io_dmem_req_bits_size (_core_io_dmem_req_bits_size), .io_dmem_req_bits_signed (_core_io_dmem_req_bits_signed), .io_dmem_req_bits_dprv (_core_io_dmem_req_bits_dprv), .io_dmem_req_bits_dv (_core_io_dmem_req_bits_dv), .io_dmem_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), .io_dmem_s1_kill (_core_io_dmem_s1_kill), .io_dmem_s1_data_data (_core_io_dmem_s1_data_data), .io_dmem_s2_nack (_dcacheArb_io_requestor_1_s2_nack), // @[HellaCache.scala:292:25] .io_dmem_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_dmem_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), // @[HellaCache.scala:292:25] .io_dmem_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), // @[HellaCache.scala:292:25] .io_dmem_resp_valid (_dcacheArb_io_requestor_1_resp_valid), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_dmem_replay_next (_dcacheArb_io_requestor_1_replay_next), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_dmem_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), // @[HellaCache.scala:292:25] .io_dmem_ordered (_dcacheArb_io_requestor_1_ordered), // @[HellaCache.scala:292:25] .io_dmem_store_pending (_dcacheArb_io_requestor_1_store_pending), // @[HellaCache.scala:292:25] .io_dmem_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), // @[HellaCache.scala:292:25] .io_dmem_perf_release (_dcacheArb_io_requestor_1_perf_release), // @[HellaCache.scala:292:25] .io_dmem_perf_grant (_dcacheArb_io_requestor_1_perf_grant), // @[HellaCache.scala:292:25] .io_dmem_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_dmem_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25] .io_dmem_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), .io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode), .io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn), .io_ptw_sfence_valid (_core_io_ptw_sfence_valid), .io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), .io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), .io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), .io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), .io_ptw_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), .io_ptw_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), .io_ptw_status_debug (_core_io_ptw_status_debug), .io_ptw_status_cease (_core_io_ptw_status_cease), .io_ptw_status_wfi (_core_io_ptw_status_wfi), .io_ptw_status_isa (_core_io_ptw_status_isa), .io_ptw_status_dprv (_core_io_ptw_status_dprv), .io_ptw_status_dv (_core_io_ptw_status_dv), .io_ptw_status_prv (_core_io_ptw_status_prv), .io_ptw_status_v (_core_io_ptw_status_v), .io_ptw_status_sd (_core_io_ptw_status_sd), .io_ptw_status_mpv (_core_io_ptw_status_mpv), .io_ptw_status_gva (_core_io_ptw_status_gva), .io_ptw_status_tsr (_core_io_ptw_status_tsr), .io_ptw_status_tw (_core_io_ptw_status_tw), .io_ptw_status_tvm (_core_io_ptw_status_tvm), .io_ptw_status_mxr (_core_io_ptw_status_mxr), .io_ptw_status_sum (_core_io_ptw_status_sum), .io_ptw_status_mprv (_core_io_ptw_status_mprv), .io_ptw_status_fs (_core_io_ptw_status_fs), .io_ptw_status_mpp (_core_io_ptw_status_mpp), .io_ptw_status_spp (_core_io_ptw_status_spp), .io_ptw_status_mpie (_core_io_ptw_status_mpie), .io_ptw_status_spie (_core_io_ptw_status_spie), .io_ptw_status_mie (_core_io_ptw_status_mie), .io_ptw_status_sie (_core_io_ptw_status_sie), .io_ptw_hstatus_spvp (_core_io_ptw_hstatus_spvp), .io_ptw_hstatus_spv (_core_io_ptw_hstatus_spv), .io_ptw_hstatus_gva (_core_io_ptw_hstatus_gva), .io_ptw_gstatus_debug (_core_io_ptw_gstatus_debug), .io_ptw_gstatus_cease (_core_io_ptw_gstatus_cease), .io_ptw_gstatus_wfi (_core_io_ptw_gstatus_wfi), .io_ptw_gstatus_isa (_core_io_ptw_gstatus_isa), .io_ptw_gstatus_dprv (_core_io_ptw_gstatus_dprv), .io_ptw_gstatus_dv (_core_io_ptw_gstatus_dv), .io_ptw_gstatus_prv (_core_io_ptw_gstatus_prv), .io_ptw_gstatus_v (_core_io_ptw_gstatus_v), .io_ptw_gstatus_sd (_core_io_ptw_gstatus_sd), .io_ptw_gstatus_zero2 (_core_io_ptw_gstatus_zero2), .io_ptw_gstatus_mpv (_core_io_ptw_gstatus_mpv), .io_ptw_gstatus_gva (_core_io_ptw_gstatus_gva), .io_ptw_gstatus_mbe (_core_io_ptw_gstatus_mbe), .io_ptw_gstatus_sbe (_core_io_ptw_gstatus_sbe), .io_ptw_gstatus_sxl (_core_io_ptw_gstatus_sxl), .io_ptw_gstatus_zero1 (_core_io_ptw_gstatus_zero1), .io_ptw_gstatus_tsr (_core_io_ptw_gstatus_tsr), .io_ptw_gstatus_tw (_core_io_ptw_gstatus_tw), .io_ptw_gstatus_tvm (_core_io_ptw_gstatus_tvm), .io_ptw_gstatus_mxr (_core_io_ptw_gstatus_mxr), .io_ptw_gstatus_sum (_core_io_ptw_gstatus_sum), .io_ptw_gstatus_mprv (_core_io_ptw_gstatus_mprv), .io_ptw_gstatus_fs (_core_io_ptw_gstatus_fs), .io_ptw_gstatus_mpp (_core_io_ptw_gstatus_mpp), .io_ptw_gstatus_vs (_core_io_ptw_gstatus_vs), .io_ptw_gstatus_spp (_core_io_ptw_gstatus_spp), .io_ptw_gstatus_mpie (_core_io_ptw_gstatus_mpie), .io_ptw_gstatus_ube (_core_io_ptw_gstatus_ube), .io_ptw_gstatus_spie (_core_io_ptw_gstatus_spie), .io_ptw_gstatus_upie (_core_io_ptw_gstatus_upie), .io_ptw_gstatus_mie (_core_io_ptw_gstatus_mie), .io_ptw_gstatus_hie (_core_io_ptw_gstatus_hie), .io_ptw_gstatus_sie (_core_io_ptw_gstatus_sie), .io_ptw_gstatus_uie (_core_io_ptw_gstatus_uie), .io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask), .io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[PTW.scala:802:19] .io_ptw_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), .io_ptw_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), .io_ptw_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), .io_ptw_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), .io_ptw_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), .io_ptw_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), .io_ptw_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), .io_ptw_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), .io_ptw_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), .io_ptw_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), .io_ptw_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), .io_ptw_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), .io_ptw_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), .io_ptw_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), .io_ptw_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), .io_ptw_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), .io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[PTW.scala:802:19] .io_fpu_hartid (_core_io_fpu_hartid), .io_fpu_time (_core_io_fpu_time), .io_fpu_inst (_core_io_fpu_inst), .io_fpu_fromint_data (_core_io_fpu_fromint_data), .io_fpu_fcsr_rm (_core_io_fpu_fcsr_rm), .io_fpu_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), // @[RocketTile.scala:242:62] .io_fpu_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), // @[RocketTile.scala:242:62] .io_fpu_store_data (_fpuOpt_io_store_data), // @[RocketTile.scala:242:62] .io_fpu_toint_data (_fpuOpt_io_toint_data), // @[RocketTile.scala:242:62] .io_fpu_ll_resp_val (_core_io_fpu_ll_resp_val), .io_fpu_ll_resp_type (_core_io_fpu_ll_resp_type), .io_fpu_ll_resp_tag (_core_io_fpu_ll_resp_tag), .io_fpu_ll_resp_data (_core_io_fpu_ll_resp_data), .io_fpu_valid (_core_io_fpu_valid), .io_fpu_fcsr_rdy (_fpuOpt_io_fcsr_rdy), // @[RocketTile.scala:242:62] .io_fpu_nack_mem (_fpuOpt_io_nack_mem), // @[RocketTile.scala:242:62] .io_fpu_illegal_rm (_fpuOpt_io_illegal_rm), // @[RocketTile.scala:242:62] .io_fpu_killx (_core_io_fpu_killx), .io_fpu_killm (_core_io_fpu_killm), .io_fpu_dec_ldst (_fpuOpt_io_dec_ldst), // @[RocketTile.scala:242:62] .io_fpu_dec_wen (_fpuOpt_io_dec_wen), // @[RocketTile.scala:242:62] .io_fpu_dec_ren1 (_fpuOpt_io_dec_ren1), // @[RocketTile.scala:242:62] .io_fpu_dec_ren2 (_fpuOpt_io_dec_ren2), // @[RocketTile.scala:242:62] .io_fpu_dec_ren3 (_fpuOpt_io_dec_ren3), // @[RocketTile.scala:242:62] .io_fpu_dec_swap12 (_fpuOpt_io_dec_swap12), // @[RocketTile.scala:242:62] .io_fpu_dec_swap23 (_fpuOpt_io_dec_swap23), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), // @[RocketTile.scala:242:62] .io_fpu_dec_fromint (_fpuOpt_io_dec_fromint), // @[RocketTile.scala:242:62] .io_fpu_dec_toint (_fpuOpt_io_dec_toint), // @[RocketTile.scala:242:62] .io_fpu_dec_fastpipe (_fpuOpt_io_dec_fastpipe), // @[RocketTile.scala:242:62] .io_fpu_dec_fma (_fpuOpt_io_dec_fma), // @[RocketTile.scala:242:62] .io_fpu_dec_div (_fpuOpt_io_dec_div), // @[RocketTile.scala:242:62] .io_fpu_dec_sqrt (_fpuOpt_io_dec_sqrt), // @[RocketTile.scala:242:62] .io_fpu_dec_wflags (_fpuOpt_io_dec_wflags), // @[RocketTile.scala:242:62] .io_fpu_dec_vec (_fpuOpt_io_dec_vec), // @[RocketTile.scala:242:62] .io_fpu_sboard_set (_fpuOpt_io_sboard_set), // @[RocketTile.scala:242:62] .io_fpu_sboard_clr (_fpuOpt_io_sboard_clr), // @[RocketTile.scala:242:62] .io_fpu_sboard_clra (_fpuOpt_io_sboard_clra), // @[RocketTile.scala:242:62] .io_fpu_keep_clock_enabled (_core_io_fpu_keep_clock_enabled), .io_trace_insns_0_valid (traceSourceNodeOut_insns_0_valid), .io_trace_insns_0_iaddr (traceSourceNodeOut_insns_0_iaddr), .io_trace_insns_0_insn (traceSourceNodeOut_insns_0_insn), .io_trace_insns_0_priv (traceSourceNodeOut_insns_0_priv), .io_trace_insns_0_exception (traceSourceNodeOut_insns_0_exception), .io_trace_insns_0_interrupt (traceSourceNodeOut_insns_0_interrupt), .io_trace_insns_0_cause (traceSourceNodeOut_insns_0_cause), .io_trace_insns_0_tval (traceSourceNodeOut_insns_0_tval), .io_trace_time (traceSourceNodeOut_time), .io_bpwatch_0_valid_0 (bpwatchSourceNodeOut_0_valid_0), .io_bpwatch_0_action (bpwatchSourceNodeOut_0_action), .io_wfi (_core_io_wfi) ); // @[RocketTile.scala:147:20] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[RocketTile.scala:141:7] assign auto_wfi_out_0 = auto_wfi_out_0_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_valid = auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr = auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn = auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv = auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception = auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt = auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause = auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval = auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_8 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_8 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_8( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_8 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_96 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_96( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_2 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_4 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_2 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<4>(0hd), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _T_2 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _T_3 = eq(UInt<4>(0h9), io.in.bits.egress_id) node _T_4 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _T_5 = or(_T, _T_1) node _T_6 = or(_T_5, _T_2) node _T_7 = or(_T_6, _T_3) node _T_8 = or(_T_7, _T_4) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = and(io.in.valid, _T_9) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_11, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h2) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<4>(0h9), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0hb), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0h8), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<4>(0hc), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<4>(0h9), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<1>(0h1)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] node _T_15 = and(io.in.ready, io.in.valid) node _T_16 = and(_T_15, io.in.bits.head) node _T_17 = and(_T_16, at_dest) when _T_17 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) node _T_18 = eq(UInt<2>(0h2), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_19 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_20 = and(route_q.io.enq.valid, _T_19) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_5 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_2 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] node _T_25 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_26 = and(vcalloc_q.io.enq.valid, _T_25) node _T_27 = eq(_T_26, UInt<1>(0h0)) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node c_lo = cat(c_lo_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _c_T = cat(c_hi, c_lo) node _c_T_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_lo_hi_1 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node c_lo_1 = cat(c_lo_hi_1, io.out_credit_available.`0`[0]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node c_hi_1 = cat(c_hi_hi_1, io.out_credit_available.`0`[3]) node _c_T_2 = cat(c_hi_1, c_lo_1) node _c_T_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_channel_oh_0 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 5, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_10 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1
module IngressUnit_2( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'hB; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = io_in_bits_egress_id == 5'h9; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 4'hA : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hB : 4'h0) | {_route_buffer_io_enq_bits_flow_egress_node_id_T_13, 3'h0} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 4'hC : 4'h0); // @[Mux.scala:30:73] wire [1:0] route_buffer_io_enq_bits_flow_egress_node_id = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_13}; // @[IngressUnit.scala:30:72, :45:50] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 == 4'h1; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 != 4'h1; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module BoomIOMSHR : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, mem_access : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_ack : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}, clock reg grant_word : UInt<64>, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T wire size : UInt<2> connect size, req.uop.mem_size node _get_legal_T = leq(UInt<1>(0h0), req.uop.mem_size) node _get_legal_T_1 = leq(req.uop.mem_size, UInt<4>(0hc)) node _get_legal_T_2 = and(_get_legal_T, _get_legal_T_1) node _get_legal_T_3 = or(UInt<1>(0h0), _get_legal_T_2) node _get_legal_T_4 = xor(req.addr, UInt<14>(0h3000)) node _get_legal_T_5 = cvt(_get_legal_T_4) node _get_legal_T_6 = and(_get_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _get_legal_T_7 = asSInt(_get_legal_T_6) node _get_legal_T_8 = eq(_get_legal_T_7, asSInt(UInt<1>(0h0))) node _get_legal_T_9 = and(_get_legal_T_3, _get_legal_T_8) node _get_legal_T_10 = leq(UInt<1>(0h0), req.uop.mem_size) node _get_legal_T_11 = leq(req.uop.mem_size, UInt<3>(0h6)) node _get_legal_T_12 = and(_get_legal_T_10, _get_legal_T_11) node _get_legal_T_13 = or(UInt<1>(0h0), _get_legal_T_12) node _get_legal_T_14 = xor(req.addr, UInt<1>(0h0)) node _get_legal_T_15 = cvt(_get_legal_T_14) node _get_legal_T_16 = and(_get_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _get_legal_T_17 = asSInt(_get_legal_T_16) node _get_legal_T_18 = eq(_get_legal_T_17, asSInt(UInt<1>(0h0))) node _get_legal_T_19 = xor(req.addr, UInt<17>(0h10000)) node _get_legal_T_20 = cvt(_get_legal_T_19) node _get_legal_T_21 = and(_get_legal_T_20, asSInt(UInt<33>(0h98013000))) node _get_legal_T_22 = asSInt(_get_legal_T_21) node _get_legal_T_23 = eq(_get_legal_T_22, asSInt(UInt<1>(0h0))) node _get_legal_T_24 = xor(req.addr, UInt<17>(0h10000)) node _get_legal_T_25 = cvt(_get_legal_T_24) node _get_legal_T_26 = and(_get_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _get_legal_T_27 = asSInt(_get_legal_T_26) node _get_legal_T_28 = eq(_get_legal_T_27, asSInt(UInt<1>(0h0))) node _get_legal_T_29 = xor(req.addr, UInt<26>(0h2000000)) node _get_legal_T_30 = cvt(_get_legal_T_29) node _get_legal_T_31 = and(_get_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _get_legal_T_32 = asSInt(_get_legal_T_31) node _get_legal_T_33 = eq(_get_legal_T_32, asSInt(UInt<1>(0h0))) node _get_legal_T_34 = xor(req.addr, UInt<28>(0h8000000)) node _get_legal_T_35 = cvt(_get_legal_T_34) node _get_legal_T_36 = and(_get_legal_T_35, asSInt(UInt<33>(0h98000000))) node _get_legal_T_37 = asSInt(_get_legal_T_36) node _get_legal_T_38 = eq(_get_legal_T_37, asSInt(UInt<1>(0h0))) node _get_legal_T_39 = xor(req.addr, UInt<28>(0h8000000)) node _get_legal_T_40 = cvt(_get_legal_T_39) node _get_legal_T_41 = and(_get_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _get_legal_T_42 = asSInt(_get_legal_T_41) node _get_legal_T_43 = eq(_get_legal_T_42, asSInt(UInt<1>(0h0))) node _get_legal_T_44 = xor(req.addr, UInt<29>(0h10000000)) node _get_legal_T_45 = cvt(_get_legal_T_44) node _get_legal_T_46 = and(_get_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _get_legal_T_47 = asSInt(_get_legal_T_46) node _get_legal_T_48 = eq(_get_legal_T_47, asSInt(UInt<1>(0h0))) node _get_legal_T_49 = xor(req.addr, UInt<32>(0h80000000)) node _get_legal_T_50 = cvt(_get_legal_T_49) node _get_legal_T_51 = and(_get_legal_T_50, asSInt(UInt<33>(0h90000000))) node _get_legal_T_52 = asSInt(_get_legal_T_51) node _get_legal_T_53 = eq(_get_legal_T_52, asSInt(UInt<1>(0h0))) node _get_legal_T_54 = or(_get_legal_T_18, _get_legal_T_23) node _get_legal_T_55 = or(_get_legal_T_54, _get_legal_T_28) node _get_legal_T_56 = or(_get_legal_T_55, _get_legal_T_33) node _get_legal_T_57 = or(_get_legal_T_56, _get_legal_T_38) node _get_legal_T_58 = or(_get_legal_T_57, _get_legal_T_43) node _get_legal_T_59 = or(_get_legal_T_58, _get_legal_T_48) node _get_legal_T_60 = or(_get_legal_T_59, _get_legal_T_53) node _get_legal_T_61 = and(_get_legal_T_13, _get_legal_T_60) node _get_legal_T_62 = or(UInt<1>(0h0), _get_legal_T_9) node get_legal = or(_get_legal_T_62, _get_legal_T_61) wire get : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect get.opcode, UInt<3>(0h4) connect get.param, UInt<1>(0h0) connect get.size, req.uop.mem_size connect get.source, UInt<2>(0h3) connect get.address, req.addr node _get_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<3>(0h0)) node get_a_mask_sizeOH_shiftAmount = bits(_get_a_mask_sizeOH_T, 1, 0) node _get_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_a_mask_sizeOH_shiftAmount) node _get_a_mask_sizeOH_T_2 = bits(_get_a_mask_sizeOH_T_1, 2, 0) node get_a_mask_sizeOH = or(_get_a_mask_sizeOH_T_2, UInt<1>(0h1)) node get_a_mask_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<2>(0h3)) node get_a_mask_sub_sub_size = bits(get_a_mask_sizeOH, 2, 2) node get_a_mask_sub_sub_bit = bits(req.addr, 2, 2) node get_a_mask_sub_sub_nbit = eq(get_a_mask_sub_sub_bit, UInt<1>(0h0)) node get_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_nbit) node _get_a_mask_sub_sub_acc_T = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_0_2) node get_a_mask_sub_sub_0_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T) node get_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_bit) node _get_a_mask_sub_sub_acc_T_1 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_1_2) node get_a_mask_sub_sub_1_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T_1) node get_a_mask_sub_size = bits(get_a_mask_sizeOH, 1, 1) node get_a_mask_sub_bit = bits(req.addr, 1, 1) node get_a_mask_sub_nbit = eq(get_a_mask_sub_bit, UInt<1>(0h0)) node get_a_mask_sub_0_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T = and(get_a_mask_sub_size, get_a_mask_sub_0_2) node get_a_mask_sub_0_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T) node get_a_mask_sub_1_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_bit) node _get_a_mask_sub_acc_T_1 = and(get_a_mask_sub_size, get_a_mask_sub_1_2) node get_a_mask_sub_1_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T_1) node get_a_mask_sub_2_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T_2 = and(get_a_mask_sub_size, get_a_mask_sub_2_2) node get_a_mask_sub_2_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_2) node get_a_mask_sub_3_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_bit) node _get_a_mask_sub_acc_T_3 = and(get_a_mask_sub_size, get_a_mask_sub_3_2) node get_a_mask_sub_3_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_3) node get_a_mask_size = bits(get_a_mask_sizeOH, 0, 0) node get_a_mask_bit = bits(req.addr, 0, 0) node get_a_mask_nbit = eq(get_a_mask_bit, UInt<1>(0h0)) node get_a_mask_eq = and(get_a_mask_sub_0_2, get_a_mask_nbit) node _get_a_mask_acc_T = and(get_a_mask_size, get_a_mask_eq) node get_a_mask_acc = or(get_a_mask_sub_0_1, _get_a_mask_acc_T) node get_a_mask_eq_1 = and(get_a_mask_sub_0_2, get_a_mask_bit) node _get_a_mask_acc_T_1 = and(get_a_mask_size, get_a_mask_eq_1) node get_a_mask_acc_1 = or(get_a_mask_sub_0_1, _get_a_mask_acc_T_1) node get_a_mask_eq_2 = and(get_a_mask_sub_1_2, get_a_mask_nbit) node _get_a_mask_acc_T_2 = and(get_a_mask_size, get_a_mask_eq_2) node get_a_mask_acc_2 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_2) node get_a_mask_eq_3 = and(get_a_mask_sub_1_2, get_a_mask_bit) node _get_a_mask_acc_T_3 = and(get_a_mask_size, get_a_mask_eq_3) node get_a_mask_acc_3 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_3) node get_a_mask_eq_4 = and(get_a_mask_sub_2_2, get_a_mask_nbit) node _get_a_mask_acc_T_4 = and(get_a_mask_size, get_a_mask_eq_4) node get_a_mask_acc_4 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_4) node get_a_mask_eq_5 = and(get_a_mask_sub_2_2, get_a_mask_bit) node _get_a_mask_acc_T_5 = and(get_a_mask_size, get_a_mask_eq_5) node get_a_mask_acc_5 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_5) node get_a_mask_eq_6 = and(get_a_mask_sub_3_2, get_a_mask_nbit) node _get_a_mask_acc_T_6 = and(get_a_mask_size, get_a_mask_eq_6) node get_a_mask_acc_6 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_6) node get_a_mask_eq_7 = and(get_a_mask_sub_3_2, get_a_mask_bit) node _get_a_mask_acc_T_7 = and(get_a_mask_size, get_a_mask_eq_7) node get_a_mask_acc_7 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_7) node get_a_mask_lo_lo = cat(get_a_mask_acc_1, get_a_mask_acc) node get_a_mask_lo_hi = cat(get_a_mask_acc_3, get_a_mask_acc_2) node get_a_mask_lo = cat(get_a_mask_lo_hi, get_a_mask_lo_lo) node get_a_mask_hi_lo = cat(get_a_mask_acc_5, get_a_mask_acc_4) node get_a_mask_hi_hi = cat(get_a_mask_acc_7, get_a_mask_acc_6) node get_a_mask_hi = cat(get_a_mask_hi_hi, get_a_mask_hi_lo) node _get_a_mask_T = cat(get_a_mask_hi, get_a_mask_lo) connect get.mask, _get_a_mask_T invalidate get.data connect get.corrupt, UInt<1>(0h0) node _put_legal_T = leq(UInt<1>(0h0), req.uop.mem_size) node _put_legal_T_1 = leq(req.uop.mem_size, UInt<4>(0hc)) node _put_legal_T_2 = and(_put_legal_T, _put_legal_T_1) node _put_legal_T_3 = or(UInt<1>(0h0), _put_legal_T_2) node _put_legal_T_4 = xor(req.addr, UInt<14>(0h3000)) node _put_legal_T_5 = cvt(_put_legal_T_4) node _put_legal_T_6 = and(_put_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _put_legal_T_7 = asSInt(_put_legal_T_6) node _put_legal_T_8 = eq(_put_legal_T_7, asSInt(UInt<1>(0h0))) node _put_legal_T_9 = and(_put_legal_T_3, _put_legal_T_8) node _put_legal_T_10 = leq(UInt<1>(0h0), req.uop.mem_size) node _put_legal_T_11 = leq(req.uop.mem_size, UInt<3>(0h6)) node _put_legal_T_12 = and(_put_legal_T_10, _put_legal_T_11) node _put_legal_T_13 = or(UInt<1>(0h0), _put_legal_T_12) node _put_legal_T_14 = xor(req.addr, UInt<1>(0h0)) node _put_legal_T_15 = cvt(_put_legal_T_14) node _put_legal_T_16 = and(_put_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _put_legal_T_17 = asSInt(_put_legal_T_16) node _put_legal_T_18 = eq(_put_legal_T_17, asSInt(UInt<1>(0h0))) node _put_legal_T_19 = xor(req.addr, UInt<21>(0h100000)) node _put_legal_T_20 = cvt(_put_legal_T_19) node _put_legal_T_21 = and(_put_legal_T_20, asSInt(UInt<33>(0h9a103000))) node _put_legal_T_22 = asSInt(_put_legal_T_21) node _put_legal_T_23 = eq(_put_legal_T_22, asSInt(UInt<1>(0h0))) node _put_legal_T_24 = xor(req.addr, UInt<26>(0h2000000)) node _put_legal_T_25 = cvt(_put_legal_T_24) node _put_legal_T_26 = and(_put_legal_T_25, asSInt(UInt<33>(0h9a110000))) node _put_legal_T_27 = asSInt(_put_legal_T_26) node _put_legal_T_28 = eq(_put_legal_T_27, asSInt(UInt<1>(0h0))) node _put_legal_T_29 = xor(req.addr, UInt<26>(0h2010000)) node _put_legal_T_30 = cvt(_put_legal_T_29) node _put_legal_T_31 = and(_put_legal_T_30, asSInt(UInt<33>(0h9a113000))) node _put_legal_T_32 = asSInt(_put_legal_T_31) node _put_legal_T_33 = eq(_put_legal_T_32, asSInt(UInt<1>(0h0))) node _put_legal_T_34 = xor(req.addr, UInt<28>(0h8000000)) node _put_legal_T_35 = cvt(_put_legal_T_34) node _put_legal_T_36 = and(_put_legal_T_35, asSInt(UInt<33>(0h98000000))) node _put_legal_T_37 = asSInt(_put_legal_T_36) node _put_legal_T_38 = eq(_put_legal_T_37, asSInt(UInt<1>(0h0))) node _put_legal_T_39 = xor(req.addr, UInt<28>(0h8000000)) node _put_legal_T_40 = cvt(_put_legal_T_39) node _put_legal_T_41 = and(_put_legal_T_40, asSInt(UInt<33>(0h9a110000))) node _put_legal_T_42 = asSInt(_put_legal_T_41) node _put_legal_T_43 = eq(_put_legal_T_42, asSInt(UInt<1>(0h0))) node _put_legal_T_44 = xor(req.addr, UInt<29>(0h10000000)) node _put_legal_T_45 = cvt(_put_legal_T_44) node _put_legal_T_46 = and(_put_legal_T_45, asSInt(UInt<33>(0h9a113000))) node _put_legal_T_47 = asSInt(_put_legal_T_46) node _put_legal_T_48 = eq(_put_legal_T_47, asSInt(UInt<1>(0h0))) node _put_legal_T_49 = xor(req.addr, UInt<32>(0h80000000)) node _put_legal_T_50 = cvt(_put_legal_T_49) node _put_legal_T_51 = and(_put_legal_T_50, asSInt(UInt<33>(0h90000000))) node _put_legal_T_52 = asSInt(_put_legal_T_51) node _put_legal_T_53 = eq(_put_legal_T_52, asSInt(UInt<1>(0h0))) node _put_legal_T_54 = or(_put_legal_T_18, _put_legal_T_23) node _put_legal_T_55 = or(_put_legal_T_54, _put_legal_T_28) node _put_legal_T_56 = or(_put_legal_T_55, _put_legal_T_33) node _put_legal_T_57 = or(_put_legal_T_56, _put_legal_T_38) node _put_legal_T_58 = or(_put_legal_T_57, _put_legal_T_43) node _put_legal_T_59 = or(_put_legal_T_58, _put_legal_T_48) node _put_legal_T_60 = or(_put_legal_T_59, _put_legal_T_53) node _put_legal_T_61 = and(_put_legal_T_13, _put_legal_T_60) node _put_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) node _put_legal_T_63 = xor(req.addr, UInt<17>(0h10000)) node _put_legal_T_64 = cvt(_put_legal_T_63) node _put_legal_T_65 = and(_put_legal_T_64, asSInt(UInt<33>(0h9a110000))) node _put_legal_T_66 = asSInt(_put_legal_T_65) node _put_legal_T_67 = eq(_put_legal_T_66, asSInt(UInt<1>(0h0))) node _put_legal_T_68 = and(_put_legal_T_62, _put_legal_T_67) node _put_legal_T_69 = or(UInt<1>(0h0), _put_legal_T_9) node _put_legal_T_70 = or(_put_legal_T_69, _put_legal_T_61) node put_legal = or(_put_legal_T_70, _put_legal_T_68) wire put : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect put.opcode, UInt<1>(0h0) connect put.param, UInt<1>(0h0) connect put.size, req.uop.mem_size connect put.source, UInt<2>(0h3) connect put.address, req.addr node _put_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<3>(0h0)) node put_a_mask_sizeOH_shiftAmount = bits(_put_a_mask_sizeOH_T, 1, 0) node _put_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), put_a_mask_sizeOH_shiftAmount) node _put_a_mask_sizeOH_T_2 = bits(_put_a_mask_sizeOH_T_1, 2, 0) node put_a_mask_sizeOH = or(_put_a_mask_sizeOH_T_2, UInt<1>(0h1)) node put_a_mask_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<2>(0h3)) node put_a_mask_sub_sub_size = bits(put_a_mask_sizeOH, 2, 2) node put_a_mask_sub_sub_bit = bits(req.addr, 2, 2) node put_a_mask_sub_sub_nbit = eq(put_a_mask_sub_sub_bit, UInt<1>(0h0)) node put_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_nbit) node _put_a_mask_sub_sub_acc_T = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_0_2) node put_a_mask_sub_sub_0_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T) node put_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_bit) node _put_a_mask_sub_sub_acc_T_1 = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_1_2) node put_a_mask_sub_sub_1_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T_1) node put_a_mask_sub_size = bits(put_a_mask_sizeOH, 1, 1) node put_a_mask_sub_bit = bits(req.addr, 1, 1) node put_a_mask_sub_nbit = eq(put_a_mask_sub_bit, UInt<1>(0h0)) node put_a_mask_sub_0_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_nbit) node _put_a_mask_sub_acc_T = and(put_a_mask_sub_size, put_a_mask_sub_0_2) node put_a_mask_sub_0_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T) node put_a_mask_sub_1_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_bit) node _put_a_mask_sub_acc_T_1 = and(put_a_mask_sub_size, put_a_mask_sub_1_2) node put_a_mask_sub_1_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T_1) node put_a_mask_sub_2_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_nbit) node _put_a_mask_sub_acc_T_2 = and(put_a_mask_sub_size, put_a_mask_sub_2_2) node put_a_mask_sub_2_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_2) node put_a_mask_sub_3_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_bit) node _put_a_mask_sub_acc_T_3 = and(put_a_mask_sub_size, put_a_mask_sub_3_2) node put_a_mask_sub_3_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_3) node put_a_mask_size = bits(put_a_mask_sizeOH, 0, 0) node put_a_mask_bit = bits(req.addr, 0, 0) node put_a_mask_nbit = eq(put_a_mask_bit, UInt<1>(0h0)) node put_a_mask_eq = and(put_a_mask_sub_0_2, put_a_mask_nbit) node _put_a_mask_acc_T = and(put_a_mask_size, put_a_mask_eq) node put_a_mask_acc = or(put_a_mask_sub_0_1, _put_a_mask_acc_T) node put_a_mask_eq_1 = and(put_a_mask_sub_0_2, put_a_mask_bit) node _put_a_mask_acc_T_1 = and(put_a_mask_size, put_a_mask_eq_1) node put_a_mask_acc_1 = or(put_a_mask_sub_0_1, _put_a_mask_acc_T_1) node put_a_mask_eq_2 = and(put_a_mask_sub_1_2, put_a_mask_nbit) node _put_a_mask_acc_T_2 = and(put_a_mask_size, put_a_mask_eq_2) node put_a_mask_acc_2 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_2) node put_a_mask_eq_3 = and(put_a_mask_sub_1_2, put_a_mask_bit) node _put_a_mask_acc_T_3 = and(put_a_mask_size, put_a_mask_eq_3) node put_a_mask_acc_3 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_3) node put_a_mask_eq_4 = and(put_a_mask_sub_2_2, put_a_mask_nbit) node _put_a_mask_acc_T_4 = and(put_a_mask_size, put_a_mask_eq_4) node put_a_mask_acc_4 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_4) node put_a_mask_eq_5 = and(put_a_mask_sub_2_2, put_a_mask_bit) node _put_a_mask_acc_T_5 = and(put_a_mask_size, put_a_mask_eq_5) node put_a_mask_acc_5 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_5) node put_a_mask_eq_6 = and(put_a_mask_sub_3_2, put_a_mask_nbit) node _put_a_mask_acc_T_6 = and(put_a_mask_size, put_a_mask_eq_6) node put_a_mask_acc_6 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_6) node put_a_mask_eq_7 = and(put_a_mask_sub_3_2, put_a_mask_bit) node _put_a_mask_acc_T_7 = and(put_a_mask_size, put_a_mask_eq_7) node put_a_mask_acc_7 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_7) node put_a_mask_lo_lo = cat(put_a_mask_acc_1, put_a_mask_acc) node put_a_mask_lo_hi = cat(put_a_mask_acc_3, put_a_mask_acc_2) node put_a_mask_lo = cat(put_a_mask_lo_hi, put_a_mask_lo_lo) node put_a_mask_hi_lo = cat(put_a_mask_acc_5, put_a_mask_acc_4) node put_a_mask_hi_hi = cat(put_a_mask_acc_7, put_a_mask_acc_6) node put_a_mask_hi = cat(put_a_mask_hi_hi, put_a_mask_hi_lo) node _put_a_mask_T = cat(put_a_mask_hi, put_a_mask_lo) connect put.mask, _put_a_mask_T connect put.data, req.data connect put.corrupt, UInt<1>(0h0) wire _atomics_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect _atomics_WIRE.corrupt, UInt<1>(0h0) connect _atomics_WIRE.data, UInt<64>(0h0) connect _atomics_WIRE.mask, UInt<8>(0h0) connect _atomics_WIRE.address, UInt<32>(0h0) connect _atomics_WIRE.source, UInt<2>(0h0) connect _atomics_WIRE.size, UInt<4>(0h0) connect _atomics_WIRE.param, UInt<3>(0h0) connect _atomics_WIRE.opcode, UInt<3>(0h0) node _atomics_legal_T = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_1 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_2 = and(_atomics_legal_T, _atomics_legal_T_1) node _atomics_legal_T_3 = or(UInt<1>(0h0), _atomics_legal_T_2) node _atomics_legal_T_4 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_5 = cvt(_atomics_legal_T_4) node _atomics_legal_T_6 = and(_atomics_legal_T_5, asSInt(UInt<33>(0h98110000))) node _atomics_legal_T_7 = asSInt(_atomics_legal_T_6) node _atomics_legal_T_8 = eq(_atomics_legal_T_7, asSInt(UInt<1>(0h0))) node _atomics_legal_T_9 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_10 = cvt(_atomics_legal_T_9) node _atomics_legal_T_11 = and(_atomics_legal_T_10, asSInt(UInt<33>(0h9a101000))) node _atomics_legal_T_12 = asSInt(_atomics_legal_T_11) node _atomics_legal_T_13 = eq(_atomics_legal_T_12, asSInt(UInt<1>(0h0))) node _atomics_legal_T_14 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_15 = cvt(_atomics_legal_T_14) node _atomics_legal_T_16 = and(_atomics_legal_T_15, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_17 = asSInt(_atomics_legal_T_16) node _atomics_legal_T_18 = eq(_atomics_legal_T_17, asSInt(UInt<1>(0h0))) node _atomics_legal_T_19 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_20 = cvt(_atomics_legal_T_19) node _atomics_legal_T_21 = and(_atomics_legal_T_20, asSInt(UInt<33>(0h98000000))) node _atomics_legal_T_22 = asSInt(_atomics_legal_T_21) node _atomics_legal_T_23 = eq(_atomics_legal_T_22, asSInt(UInt<1>(0h0))) node _atomics_legal_T_24 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_25 = cvt(_atomics_legal_T_24) node _atomics_legal_T_26 = and(_atomics_legal_T_25, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_27 = asSInt(_atomics_legal_T_26) node _atomics_legal_T_28 = eq(_atomics_legal_T_27, asSInt(UInt<1>(0h0))) node _atomics_legal_T_29 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_30 = cvt(_atomics_legal_T_29) node _atomics_legal_T_31 = and(_atomics_legal_T_30, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_32 = asSInt(_atomics_legal_T_31) node _atomics_legal_T_33 = eq(_atomics_legal_T_32, asSInt(UInt<1>(0h0))) node _atomics_legal_T_34 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_35 = cvt(_atomics_legal_T_34) node _atomics_legal_T_36 = and(_atomics_legal_T_35, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_37 = asSInt(_atomics_legal_T_36) node _atomics_legal_T_38 = eq(_atomics_legal_T_37, asSInt(UInt<1>(0h0))) node _atomics_legal_T_39 = or(_atomics_legal_T_8, _atomics_legal_T_13) node _atomics_legal_T_40 = or(_atomics_legal_T_39, _atomics_legal_T_18) node _atomics_legal_T_41 = or(_atomics_legal_T_40, _atomics_legal_T_23) node _atomics_legal_T_42 = or(_atomics_legal_T_41, _atomics_legal_T_28) node _atomics_legal_T_43 = or(_atomics_legal_T_42, _atomics_legal_T_33) node _atomics_legal_T_44 = or(_atomics_legal_T_43, _atomics_legal_T_38) node _atomics_legal_T_45 = and(_atomics_legal_T_3, _atomics_legal_T_44) node _atomics_legal_T_46 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_47 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_48 = cvt(_atomics_legal_T_47) node _atomics_legal_T_49 = and(_atomics_legal_T_48, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_50 = asSInt(_atomics_legal_T_49) node _atomics_legal_T_51 = eq(_atomics_legal_T_50, asSInt(UInt<1>(0h0))) node _atomics_legal_T_52 = and(_atomics_legal_T_46, _atomics_legal_T_51) node _atomics_legal_T_53 = or(UInt<1>(0h0), _atomics_legal_T_45) node atomics_legal = or(_atomics_legal_T_53, _atomics_legal_T_52) wire atomics_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect atomics_a.opcode, UInt<2>(0h3) connect atomics_a.param, UInt<3>(0h3) connect atomics_a.size, req.uop.mem_size connect atomics_a.source, UInt<2>(0h3) connect atomics_a.address, req.addr node _atomics_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<3>(0h0)) node atomics_a_mask_sizeOH_shiftAmount = bits(_atomics_a_mask_sizeOH_T, 1, 0) node _atomics_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount) node _atomics_a_mask_sizeOH_T_2 = bits(_atomics_a_mask_sizeOH_T_1, 2, 0) node atomics_a_mask_sizeOH = or(_atomics_a_mask_sizeOH_T_2, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<2>(0h3)) node atomics_a_mask_sub_sub_size = bits(atomics_a_mask_sizeOH, 2, 2) node atomics_a_mask_sub_sub_bit = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit = eq(atomics_a_mask_sub_sub_bit, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit) node _atomics_a_mask_sub_sub_acc_T = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_0_2) node atomics_a_mask_sub_sub_0_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T) node atomics_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit) node _atomics_a_mask_sub_sub_acc_T_1 = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_1_2) node atomics_a_mask_sub_sub_1_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T_1) node atomics_a_mask_sub_size = bits(atomics_a_mask_sizeOH, 1, 1) node atomics_a_mask_sub_bit = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit = eq(atomics_a_mask_sub_bit, UInt<1>(0h0)) node atomics_a_mask_sub_0_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_nbit) node _atomics_a_mask_sub_acc_T = and(atomics_a_mask_sub_size, atomics_a_mask_sub_0_2) node atomics_a_mask_sub_0_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T) node atomics_a_mask_sub_1_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_bit) node _atomics_a_mask_sub_acc_T_1 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_1_2) node atomics_a_mask_sub_1_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T_1) node atomics_a_mask_sub_2_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_nbit) node _atomics_a_mask_sub_acc_T_2 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_2_2) node atomics_a_mask_sub_2_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_2) node atomics_a_mask_sub_3_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_bit) node _atomics_a_mask_sub_acc_T_3 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_3_2) node atomics_a_mask_sub_3_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_3) node atomics_a_mask_size = bits(atomics_a_mask_sizeOH, 0, 0) node atomics_a_mask_bit = bits(req.addr, 0, 0) node atomics_a_mask_nbit = eq(atomics_a_mask_bit, UInt<1>(0h0)) node atomics_a_mask_eq = and(atomics_a_mask_sub_0_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T = and(atomics_a_mask_size, atomics_a_mask_eq) node atomics_a_mask_acc = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T) node atomics_a_mask_eq_1 = and(atomics_a_mask_sub_0_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_1 = and(atomics_a_mask_size, atomics_a_mask_eq_1) node atomics_a_mask_acc_1 = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T_1) node atomics_a_mask_eq_2 = and(atomics_a_mask_sub_1_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_2 = and(atomics_a_mask_size, atomics_a_mask_eq_2) node atomics_a_mask_acc_2 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_2) node atomics_a_mask_eq_3 = and(atomics_a_mask_sub_1_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_3 = and(atomics_a_mask_size, atomics_a_mask_eq_3) node atomics_a_mask_acc_3 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_3) node atomics_a_mask_eq_4 = and(atomics_a_mask_sub_2_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_4 = and(atomics_a_mask_size, atomics_a_mask_eq_4) node atomics_a_mask_acc_4 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_4) node atomics_a_mask_eq_5 = and(atomics_a_mask_sub_2_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_5 = and(atomics_a_mask_size, atomics_a_mask_eq_5) node atomics_a_mask_acc_5 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_5) node atomics_a_mask_eq_6 = and(atomics_a_mask_sub_3_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_6 = and(atomics_a_mask_size, atomics_a_mask_eq_6) node atomics_a_mask_acc_6 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_6) node atomics_a_mask_eq_7 = and(atomics_a_mask_sub_3_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_7 = and(atomics_a_mask_size, atomics_a_mask_eq_7) node atomics_a_mask_acc_7 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_7) node atomics_a_mask_lo_lo = cat(atomics_a_mask_acc_1, atomics_a_mask_acc) node atomics_a_mask_lo_hi = cat(atomics_a_mask_acc_3, atomics_a_mask_acc_2) node atomics_a_mask_lo = cat(atomics_a_mask_lo_hi, atomics_a_mask_lo_lo) node atomics_a_mask_hi_lo = cat(atomics_a_mask_acc_5, atomics_a_mask_acc_4) node atomics_a_mask_hi_hi = cat(atomics_a_mask_acc_7, atomics_a_mask_acc_6) node atomics_a_mask_hi = cat(atomics_a_mask_hi_hi, atomics_a_mask_hi_lo) node _atomics_a_mask_T = cat(atomics_a_mask_hi, atomics_a_mask_lo) connect atomics_a.mask, _atomics_a_mask_T connect atomics_a.data, req.data connect atomics_a.corrupt, UInt<1>(0h0) node _atomics_legal_T_54 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_55 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_56 = and(_atomics_legal_T_54, _atomics_legal_T_55) node _atomics_legal_T_57 = or(UInt<1>(0h0), _atomics_legal_T_56) node _atomics_legal_T_58 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_59 = cvt(_atomics_legal_T_58) node _atomics_legal_T_60 = and(_atomics_legal_T_59, asSInt(UInt<33>(0h98110000))) node _atomics_legal_T_61 = asSInt(_atomics_legal_T_60) node _atomics_legal_T_62 = eq(_atomics_legal_T_61, asSInt(UInt<1>(0h0))) node _atomics_legal_T_63 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_64 = cvt(_atomics_legal_T_63) node _atomics_legal_T_65 = and(_atomics_legal_T_64, asSInt(UInt<33>(0h9a101000))) node _atomics_legal_T_66 = asSInt(_atomics_legal_T_65) node _atomics_legal_T_67 = eq(_atomics_legal_T_66, asSInt(UInt<1>(0h0))) node _atomics_legal_T_68 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_69 = cvt(_atomics_legal_T_68) node _atomics_legal_T_70 = and(_atomics_legal_T_69, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_71 = asSInt(_atomics_legal_T_70) node _atomics_legal_T_72 = eq(_atomics_legal_T_71, asSInt(UInt<1>(0h0))) node _atomics_legal_T_73 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_74 = cvt(_atomics_legal_T_73) node _atomics_legal_T_75 = and(_atomics_legal_T_74, asSInt(UInt<33>(0h98000000))) node _atomics_legal_T_76 = asSInt(_atomics_legal_T_75) node _atomics_legal_T_77 = eq(_atomics_legal_T_76, asSInt(UInt<1>(0h0))) node _atomics_legal_T_78 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_79 = cvt(_atomics_legal_T_78) node _atomics_legal_T_80 = and(_atomics_legal_T_79, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_81 = asSInt(_atomics_legal_T_80) node _atomics_legal_T_82 = eq(_atomics_legal_T_81, asSInt(UInt<1>(0h0))) node _atomics_legal_T_83 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_84 = cvt(_atomics_legal_T_83) node _atomics_legal_T_85 = and(_atomics_legal_T_84, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_86 = asSInt(_atomics_legal_T_85) node _atomics_legal_T_87 = eq(_atomics_legal_T_86, asSInt(UInt<1>(0h0))) node _atomics_legal_T_88 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_89 = cvt(_atomics_legal_T_88) node _atomics_legal_T_90 = and(_atomics_legal_T_89, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_91 = asSInt(_atomics_legal_T_90) node _atomics_legal_T_92 = eq(_atomics_legal_T_91, asSInt(UInt<1>(0h0))) node _atomics_legal_T_93 = or(_atomics_legal_T_62, _atomics_legal_T_67) node _atomics_legal_T_94 = or(_atomics_legal_T_93, _atomics_legal_T_72) node _atomics_legal_T_95 = or(_atomics_legal_T_94, _atomics_legal_T_77) node _atomics_legal_T_96 = or(_atomics_legal_T_95, _atomics_legal_T_82) node _atomics_legal_T_97 = or(_atomics_legal_T_96, _atomics_legal_T_87) node _atomics_legal_T_98 = or(_atomics_legal_T_97, _atomics_legal_T_92) node _atomics_legal_T_99 = and(_atomics_legal_T_57, _atomics_legal_T_98) node _atomics_legal_T_100 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_101 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_102 = cvt(_atomics_legal_T_101) node _atomics_legal_T_103 = and(_atomics_legal_T_102, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_104 = asSInt(_atomics_legal_T_103) node _atomics_legal_T_105 = eq(_atomics_legal_T_104, asSInt(UInt<1>(0h0))) node _atomics_legal_T_106 = and(_atomics_legal_T_100, _atomics_legal_T_105) node _atomics_legal_T_107 = or(UInt<1>(0h0), _atomics_legal_T_99) node atomics_legal_1 = or(_atomics_legal_T_107, _atomics_legal_T_106) wire atomics_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect atomics_a_1.opcode, UInt<2>(0h3) connect atomics_a_1.param, UInt<3>(0h0) connect atomics_a_1.size, req.uop.mem_size connect atomics_a_1.source, UInt<2>(0h3) connect atomics_a_1.address, req.addr node _atomics_a_mask_sizeOH_T_3 = or(req.uop.mem_size, UInt<3>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_1 = bits(_atomics_a_mask_sizeOH_T_3, 1, 0) node _atomics_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_1) node _atomics_a_mask_sizeOH_T_5 = bits(_atomics_a_mask_sizeOH_T_4, 2, 0) node atomics_a_mask_sizeOH_1 = or(_atomics_a_mask_sizeOH_T_5, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_0_1_1 = geq(req.uop.mem_size, UInt<2>(0h3)) node atomics_a_mask_sub_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 2, 2) node atomics_a_mask_sub_sub_bit_1 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_1 = eq(atomics_a_mask_sub_sub_bit_1, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_1) node _atomics_a_mask_sub_sub_acc_T_2 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_0_2_1) node atomics_a_mask_sub_sub_0_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_2) node atomics_a_mask_sub_sub_1_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_1) node _atomics_a_mask_sub_sub_acc_T_3 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_1_2_1) node atomics_a_mask_sub_sub_1_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_3) node atomics_a_mask_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 1, 1) node atomics_a_mask_sub_bit_1 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_1 = eq(atomics_a_mask_sub_bit_1, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_nbit_1) node _atomics_a_mask_sub_acc_T_4 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_0_2_1) node atomics_a_mask_sub_0_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_4) node atomics_a_mask_sub_1_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_bit_1) node _atomics_a_mask_sub_acc_T_5 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_1_2_1) node atomics_a_mask_sub_1_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_5) node atomics_a_mask_sub_2_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_nbit_1) node _atomics_a_mask_sub_acc_T_6 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_2_2_1) node atomics_a_mask_sub_2_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_6) node atomics_a_mask_sub_3_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_bit_1) node _atomics_a_mask_sub_acc_T_7 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_3_2_1) node atomics_a_mask_sub_3_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_7) node atomics_a_mask_size_1 = bits(atomics_a_mask_sizeOH_1, 0, 0) node atomics_a_mask_bit_1 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_1 = eq(atomics_a_mask_bit_1, UInt<1>(0h0)) node atomics_a_mask_eq_8 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_8 = and(atomics_a_mask_size_1, atomics_a_mask_eq_8) node atomics_a_mask_acc_8 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_8) node atomics_a_mask_eq_9 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_9 = and(atomics_a_mask_size_1, atomics_a_mask_eq_9) node atomics_a_mask_acc_9 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_9) node atomics_a_mask_eq_10 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_10 = and(atomics_a_mask_size_1, atomics_a_mask_eq_10) node atomics_a_mask_acc_10 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_10) node atomics_a_mask_eq_11 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_11 = and(atomics_a_mask_size_1, atomics_a_mask_eq_11) node atomics_a_mask_acc_11 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_11) node atomics_a_mask_eq_12 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_12 = and(atomics_a_mask_size_1, atomics_a_mask_eq_12) node atomics_a_mask_acc_12 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_12) node atomics_a_mask_eq_13 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_13 = and(atomics_a_mask_size_1, atomics_a_mask_eq_13) node atomics_a_mask_acc_13 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_13) node atomics_a_mask_eq_14 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_14 = and(atomics_a_mask_size_1, atomics_a_mask_eq_14) node atomics_a_mask_acc_14 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_14) node atomics_a_mask_eq_15 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_15 = and(atomics_a_mask_size_1, atomics_a_mask_eq_15) node atomics_a_mask_acc_15 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_15) node atomics_a_mask_lo_lo_1 = cat(atomics_a_mask_acc_9, atomics_a_mask_acc_8) node atomics_a_mask_lo_hi_1 = cat(atomics_a_mask_acc_11, atomics_a_mask_acc_10) node atomics_a_mask_lo_1 = cat(atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1) node atomics_a_mask_hi_lo_1 = cat(atomics_a_mask_acc_13, atomics_a_mask_acc_12) node atomics_a_mask_hi_hi_1 = cat(atomics_a_mask_acc_15, atomics_a_mask_acc_14) node atomics_a_mask_hi_1 = cat(atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1) node _atomics_a_mask_T_1 = cat(atomics_a_mask_hi_1, atomics_a_mask_lo_1) connect atomics_a_1.mask, _atomics_a_mask_T_1 connect atomics_a_1.data, req.data connect atomics_a_1.corrupt, UInt<1>(0h0) node _atomics_legal_T_108 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_109 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_110 = and(_atomics_legal_T_108, _atomics_legal_T_109) node _atomics_legal_T_111 = or(UInt<1>(0h0), _atomics_legal_T_110) node _atomics_legal_T_112 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_113 = cvt(_atomics_legal_T_112) node _atomics_legal_T_114 = and(_atomics_legal_T_113, asSInt(UInt<33>(0h98110000))) node _atomics_legal_T_115 = asSInt(_atomics_legal_T_114) node _atomics_legal_T_116 = eq(_atomics_legal_T_115, asSInt(UInt<1>(0h0))) node _atomics_legal_T_117 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_118 = cvt(_atomics_legal_T_117) node _atomics_legal_T_119 = and(_atomics_legal_T_118, asSInt(UInt<33>(0h9a101000))) node _atomics_legal_T_120 = asSInt(_atomics_legal_T_119) node _atomics_legal_T_121 = eq(_atomics_legal_T_120, asSInt(UInt<1>(0h0))) node _atomics_legal_T_122 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_123 = cvt(_atomics_legal_T_122) node _atomics_legal_T_124 = and(_atomics_legal_T_123, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_125 = asSInt(_atomics_legal_T_124) node _atomics_legal_T_126 = eq(_atomics_legal_T_125, asSInt(UInt<1>(0h0))) node _atomics_legal_T_127 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_128 = cvt(_atomics_legal_T_127) node _atomics_legal_T_129 = and(_atomics_legal_T_128, asSInt(UInt<33>(0h98000000))) node _atomics_legal_T_130 = asSInt(_atomics_legal_T_129) node _atomics_legal_T_131 = eq(_atomics_legal_T_130, asSInt(UInt<1>(0h0))) node _atomics_legal_T_132 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_133 = cvt(_atomics_legal_T_132) node _atomics_legal_T_134 = and(_atomics_legal_T_133, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_135 = asSInt(_atomics_legal_T_134) node _atomics_legal_T_136 = eq(_atomics_legal_T_135, asSInt(UInt<1>(0h0))) node _atomics_legal_T_137 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_138 = cvt(_atomics_legal_T_137) node _atomics_legal_T_139 = and(_atomics_legal_T_138, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_140 = asSInt(_atomics_legal_T_139) node _atomics_legal_T_141 = eq(_atomics_legal_T_140, asSInt(UInt<1>(0h0))) node _atomics_legal_T_142 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_143 = cvt(_atomics_legal_T_142) node _atomics_legal_T_144 = and(_atomics_legal_T_143, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_145 = asSInt(_atomics_legal_T_144) node _atomics_legal_T_146 = eq(_atomics_legal_T_145, asSInt(UInt<1>(0h0))) node _atomics_legal_T_147 = or(_atomics_legal_T_116, _atomics_legal_T_121) node _atomics_legal_T_148 = or(_atomics_legal_T_147, _atomics_legal_T_126) node _atomics_legal_T_149 = or(_atomics_legal_T_148, _atomics_legal_T_131) node _atomics_legal_T_150 = or(_atomics_legal_T_149, _atomics_legal_T_136) node _atomics_legal_T_151 = or(_atomics_legal_T_150, _atomics_legal_T_141) node _atomics_legal_T_152 = or(_atomics_legal_T_151, _atomics_legal_T_146) node _atomics_legal_T_153 = and(_atomics_legal_T_111, _atomics_legal_T_152) node _atomics_legal_T_154 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_155 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_156 = cvt(_atomics_legal_T_155) node _atomics_legal_T_157 = and(_atomics_legal_T_156, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_158 = asSInt(_atomics_legal_T_157) node _atomics_legal_T_159 = eq(_atomics_legal_T_158, asSInt(UInt<1>(0h0))) node _atomics_legal_T_160 = and(_atomics_legal_T_154, _atomics_legal_T_159) node _atomics_legal_T_161 = or(UInt<1>(0h0), _atomics_legal_T_153) node atomics_legal_2 = or(_atomics_legal_T_161, _atomics_legal_T_160) wire atomics_a_2 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect atomics_a_2.opcode, UInt<2>(0h3) connect atomics_a_2.param, UInt<3>(0h1) connect atomics_a_2.size, req.uop.mem_size connect atomics_a_2.source, UInt<2>(0h3) connect atomics_a_2.address, req.addr node _atomics_a_mask_sizeOH_T_6 = or(req.uop.mem_size, UInt<3>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_2 = bits(_atomics_a_mask_sizeOH_T_6, 1, 0) node _atomics_a_mask_sizeOH_T_7 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_2) node _atomics_a_mask_sizeOH_T_8 = bits(_atomics_a_mask_sizeOH_T_7, 2, 0) node atomics_a_mask_sizeOH_2 = or(_atomics_a_mask_sizeOH_T_8, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_0_1_2 = geq(req.uop.mem_size, UInt<2>(0h3)) node atomics_a_mask_sub_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 2, 2) node atomics_a_mask_sub_sub_bit_2 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_2 = eq(atomics_a_mask_sub_sub_bit_2, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_2) node _atomics_a_mask_sub_sub_acc_T_4 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_0_2_2) node atomics_a_mask_sub_sub_0_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_4) node atomics_a_mask_sub_sub_1_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_2) node _atomics_a_mask_sub_sub_acc_T_5 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_1_2_2) node atomics_a_mask_sub_sub_1_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_5) node atomics_a_mask_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 1, 1) node atomics_a_mask_sub_bit_2 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_2 = eq(atomics_a_mask_sub_bit_2, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_nbit_2) node _atomics_a_mask_sub_acc_T_8 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_0_2_2) node atomics_a_mask_sub_0_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_8) node atomics_a_mask_sub_1_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_bit_2) node _atomics_a_mask_sub_acc_T_9 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_1_2_2) node atomics_a_mask_sub_1_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_9) node atomics_a_mask_sub_2_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_nbit_2) node _atomics_a_mask_sub_acc_T_10 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_2_2_2) node atomics_a_mask_sub_2_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_10) node atomics_a_mask_sub_3_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_bit_2) node _atomics_a_mask_sub_acc_T_11 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_3_2_2) node atomics_a_mask_sub_3_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_11) node atomics_a_mask_size_2 = bits(atomics_a_mask_sizeOH_2, 0, 0) node atomics_a_mask_bit_2 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_2 = eq(atomics_a_mask_bit_2, UInt<1>(0h0)) node atomics_a_mask_eq_16 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_16 = and(atomics_a_mask_size_2, atomics_a_mask_eq_16) node atomics_a_mask_acc_16 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_16) node atomics_a_mask_eq_17 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_17 = and(atomics_a_mask_size_2, atomics_a_mask_eq_17) node atomics_a_mask_acc_17 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_17) node atomics_a_mask_eq_18 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_18 = and(atomics_a_mask_size_2, atomics_a_mask_eq_18) node atomics_a_mask_acc_18 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_18) node atomics_a_mask_eq_19 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_19 = and(atomics_a_mask_size_2, atomics_a_mask_eq_19) node atomics_a_mask_acc_19 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_19) node atomics_a_mask_eq_20 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_20 = and(atomics_a_mask_size_2, atomics_a_mask_eq_20) node atomics_a_mask_acc_20 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_20) node atomics_a_mask_eq_21 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_21 = and(atomics_a_mask_size_2, atomics_a_mask_eq_21) node atomics_a_mask_acc_21 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_21) node atomics_a_mask_eq_22 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_22 = and(atomics_a_mask_size_2, atomics_a_mask_eq_22) node atomics_a_mask_acc_22 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_22) node atomics_a_mask_eq_23 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_23 = and(atomics_a_mask_size_2, atomics_a_mask_eq_23) node atomics_a_mask_acc_23 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_23) node atomics_a_mask_lo_lo_2 = cat(atomics_a_mask_acc_17, atomics_a_mask_acc_16) node atomics_a_mask_lo_hi_2 = cat(atomics_a_mask_acc_19, atomics_a_mask_acc_18) node atomics_a_mask_lo_2 = cat(atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2) node atomics_a_mask_hi_lo_2 = cat(atomics_a_mask_acc_21, atomics_a_mask_acc_20) node atomics_a_mask_hi_hi_2 = cat(atomics_a_mask_acc_23, atomics_a_mask_acc_22) node atomics_a_mask_hi_2 = cat(atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2) node _atomics_a_mask_T_2 = cat(atomics_a_mask_hi_2, atomics_a_mask_lo_2) connect atomics_a_2.mask, _atomics_a_mask_T_2 connect atomics_a_2.data, req.data connect atomics_a_2.corrupt, UInt<1>(0h0) node _atomics_legal_T_162 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_163 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_164 = and(_atomics_legal_T_162, _atomics_legal_T_163) node _atomics_legal_T_165 = or(UInt<1>(0h0), _atomics_legal_T_164) node _atomics_legal_T_166 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_167 = cvt(_atomics_legal_T_166) node _atomics_legal_T_168 = and(_atomics_legal_T_167, asSInt(UInt<33>(0h98110000))) node _atomics_legal_T_169 = asSInt(_atomics_legal_T_168) node _atomics_legal_T_170 = eq(_atomics_legal_T_169, asSInt(UInt<1>(0h0))) node _atomics_legal_T_171 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_172 = cvt(_atomics_legal_T_171) node _atomics_legal_T_173 = and(_atomics_legal_T_172, asSInt(UInt<33>(0h9a101000))) node _atomics_legal_T_174 = asSInt(_atomics_legal_T_173) node _atomics_legal_T_175 = eq(_atomics_legal_T_174, asSInt(UInt<1>(0h0))) node _atomics_legal_T_176 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_177 = cvt(_atomics_legal_T_176) node _atomics_legal_T_178 = and(_atomics_legal_T_177, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_179 = asSInt(_atomics_legal_T_178) node _atomics_legal_T_180 = eq(_atomics_legal_T_179, asSInt(UInt<1>(0h0))) node _atomics_legal_T_181 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_182 = cvt(_atomics_legal_T_181) node _atomics_legal_T_183 = and(_atomics_legal_T_182, asSInt(UInt<33>(0h98000000))) node _atomics_legal_T_184 = asSInt(_atomics_legal_T_183) node _atomics_legal_T_185 = eq(_atomics_legal_T_184, asSInt(UInt<1>(0h0))) node _atomics_legal_T_186 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_187 = cvt(_atomics_legal_T_186) node _atomics_legal_T_188 = and(_atomics_legal_T_187, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_189 = asSInt(_atomics_legal_T_188) node _atomics_legal_T_190 = eq(_atomics_legal_T_189, asSInt(UInt<1>(0h0))) node _atomics_legal_T_191 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_192 = cvt(_atomics_legal_T_191) node _atomics_legal_T_193 = and(_atomics_legal_T_192, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_194 = asSInt(_atomics_legal_T_193) node _atomics_legal_T_195 = eq(_atomics_legal_T_194, asSInt(UInt<1>(0h0))) node _atomics_legal_T_196 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_197 = cvt(_atomics_legal_T_196) node _atomics_legal_T_198 = and(_atomics_legal_T_197, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_199 = asSInt(_atomics_legal_T_198) node _atomics_legal_T_200 = eq(_atomics_legal_T_199, asSInt(UInt<1>(0h0))) node _atomics_legal_T_201 = or(_atomics_legal_T_170, _atomics_legal_T_175) node _atomics_legal_T_202 = or(_atomics_legal_T_201, _atomics_legal_T_180) node _atomics_legal_T_203 = or(_atomics_legal_T_202, _atomics_legal_T_185) node _atomics_legal_T_204 = or(_atomics_legal_T_203, _atomics_legal_T_190) node _atomics_legal_T_205 = or(_atomics_legal_T_204, _atomics_legal_T_195) node _atomics_legal_T_206 = or(_atomics_legal_T_205, _atomics_legal_T_200) node _atomics_legal_T_207 = and(_atomics_legal_T_165, _atomics_legal_T_206) node _atomics_legal_T_208 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_209 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_210 = cvt(_atomics_legal_T_209) node _atomics_legal_T_211 = and(_atomics_legal_T_210, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_212 = asSInt(_atomics_legal_T_211) node _atomics_legal_T_213 = eq(_atomics_legal_T_212, asSInt(UInt<1>(0h0))) node _atomics_legal_T_214 = and(_atomics_legal_T_208, _atomics_legal_T_213) node _atomics_legal_T_215 = or(UInt<1>(0h0), _atomics_legal_T_207) node atomics_legal_3 = or(_atomics_legal_T_215, _atomics_legal_T_214) wire atomics_a_3 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect atomics_a_3.opcode, UInt<2>(0h3) connect atomics_a_3.param, UInt<3>(0h2) connect atomics_a_3.size, req.uop.mem_size connect atomics_a_3.source, UInt<2>(0h3) connect atomics_a_3.address, req.addr node _atomics_a_mask_sizeOH_T_9 = or(req.uop.mem_size, UInt<3>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_3 = bits(_atomics_a_mask_sizeOH_T_9, 1, 0) node _atomics_a_mask_sizeOH_T_10 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_3) node _atomics_a_mask_sizeOH_T_11 = bits(_atomics_a_mask_sizeOH_T_10, 2, 0) node atomics_a_mask_sizeOH_3 = or(_atomics_a_mask_sizeOH_T_11, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_0_1_3 = geq(req.uop.mem_size, UInt<2>(0h3)) node atomics_a_mask_sub_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 2, 2) node atomics_a_mask_sub_sub_bit_3 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_3 = eq(atomics_a_mask_sub_sub_bit_3, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_3) node _atomics_a_mask_sub_sub_acc_T_6 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_0_2_3) node atomics_a_mask_sub_sub_0_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_6) node atomics_a_mask_sub_sub_1_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_3) node _atomics_a_mask_sub_sub_acc_T_7 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_1_2_3) node atomics_a_mask_sub_sub_1_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_7) node atomics_a_mask_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 1, 1) node atomics_a_mask_sub_bit_3 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_3 = eq(atomics_a_mask_sub_bit_3, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_nbit_3) node _atomics_a_mask_sub_acc_T_12 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_0_2_3) node atomics_a_mask_sub_0_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_12) node atomics_a_mask_sub_1_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_bit_3) node _atomics_a_mask_sub_acc_T_13 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_1_2_3) node atomics_a_mask_sub_1_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_13) node atomics_a_mask_sub_2_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_nbit_3) node _atomics_a_mask_sub_acc_T_14 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_2_2_3) node atomics_a_mask_sub_2_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_14) node atomics_a_mask_sub_3_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_bit_3) node _atomics_a_mask_sub_acc_T_15 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_3_2_3) node atomics_a_mask_sub_3_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_15) node atomics_a_mask_size_3 = bits(atomics_a_mask_sizeOH_3, 0, 0) node atomics_a_mask_bit_3 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_3 = eq(atomics_a_mask_bit_3, UInt<1>(0h0)) node atomics_a_mask_eq_24 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_24 = and(atomics_a_mask_size_3, atomics_a_mask_eq_24) node atomics_a_mask_acc_24 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_24) node atomics_a_mask_eq_25 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_25 = and(atomics_a_mask_size_3, atomics_a_mask_eq_25) node atomics_a_mask_acc_25 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_25) node atomics_a_mask_eq_26 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_26 = and(atomics_a_mask_size_3, atomics_a_mask_eq_26) node atomics_a_mask_acc_26 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_26) node atomics_a_mask_eq_27 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_27 = and(atomics_a_mask_size_3, atomics_a_mask_eq_27) node atomics_a_mask_acc_27 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_27) node atomics_a_mask_eq_28 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_28 = and(atomics_a_mask_size_3, atomics_a_mask_eq_28) node atomics_a_mask_acc_28 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_28) node atomics_a_mask_eq_29 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_29 = and(atomics_a_mask_size_3, atomics_a_mask_eq_29) node atomics_a_mask_acc_29 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_29) node atomics_a_mask_eq_30 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_30 = and(atomics_a_mask_size_3, atomics_a_mask_eq_30) node atomics_a_mask_acc_30 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_30) node atomics_a_mask_eq_31 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_31 = and(atomics_a_mask_size_3, atomics_a_mask_eq_31) node atomics_a_mask_acc_31 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_31) node atomics_a_mask_lo_lo_3 = cat(atomics_a_mask_acc_25, atomics_a_mask_acc_24) node atomics_a_mask_lo_hi_3 = cat(atomics_a_mask_acc_27, atomics_a_mask_acc_26) node atomics_a_mask_lo_3 = cat(atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3) node atomics_a_mask_hi_lo_3 = cat(atomics_a_mask_acc_29, atomics_a_mask_acc_28) node atomics_a_mask_hi_hi_3 = cat(atomics_a_mask_acc_31, atomics_a_mask_acc_30) node atomics_a_mask_hi_3 = cat(atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3) node _atomics_a_mask_T_3 = cat(atomics_a_mask_hi_3, atomics_a_mask_lo_3) connect atomics_a_3.mask, _atomics_a_mask_T_3 connect atomics_a_3.data, req.data connect atomics_a_3.corrupt, UInt<1>(0h0) node _atomics_legal_T_216 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_217 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_218 = and(_atomics_legal_T_216, _atomics_legal_T_217) node _atomics_legal_T_219 = or(UInt<1>(0h0), _atomics_legal_T_218) node _atomics_legal_T_220 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_221 = cvt(_atomics_legal_T_220) node _atomics_legal_T_222 = and(_atomics_legal_T_221, asSInt(UInt<33>(0h98110000))) node _atomics_legal_T_223 = asSInt(_atomics_legal_T_222) node _atomics_legal_T_224 = eq(_atomics_legal_T_223, asSInt(UInt<1>(0h0))) node _atomics_legal_T_225 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_226 = cvt(_atomics_legal_T_225) node _atomics_legal_T_227 = and(_atomics_legal_T_226, asSInt(UInt<33>(0h9a101000))) node _atomics_legal_T_228 = asSInt(_atomics_legal_T_227) node _atomics_legal_T_229 = eq(_atomics_legal_T_228, asSInt(UInt<1>(0h0))) node _atomics_legal_T_230 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_231 = cvt(_atomics_legal_T_230) node _atomics_legal_T_232 = and(_atomics_legal_T_231, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_233 = asSInt(_atomics_legal_T_232) node _atomics_legal_T_234 = eq(_atomics_legal_T_233, asSInt(UInt<1>(0h0))) node _atomics_legal_T_235 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_236 = cvt(_atomics_legal_T_235) node _atomics_legal_T_237 = and(_atomics_legal_T_236, asSInt(UInt<33>(0h98000000))) node _atomics_legal_T_238 = asSInt(_atomics_legal_T_237) node _atomics_legal_T_239 = eq(_atomics_legal_T_238, asSInt(UInt<1>(0h0))) node _atomics_legal_T_240 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_241 = cvt(_atomics_legal_T_240) node _atomics_legal_T_242 = and(_atomics_legal_T_241, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_243 = asSInt(_atomics_legal_T_242) node _atomics_legal_T_244 = eq(_atomics_legal_T_243, asSInt(UInt<1>(0h0))) node _atomics_legal_T_245 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_246 = cvt(_atomics_legal_T_245) node _atomics_legal_T_247 = and(_atomics_legal_T_246, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_248 = asSInt(_atomics_legal_T_247) node _atomics_legal_T_249 = eq(_atomics_legal_T_248, asSInt(UInt<1>(0h0))) node _atomics_legal_T_250 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_251 = cvt(_atomics_legal_T_250) node _atomics_legal_T_252 = and(_atomics_legal_T_251, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_253 = asSInt(_atomics_legal_T_252) node _atomics_legal_T_254 = eq(_atomics_legal_T_253, asSInt(UInt<1>(0h0))) node _atomics_legal_T_255 = or(_atomics_legal_T_224, _atomics_legal_T_229) node _atomics_legal_T_256 = or(_atomics_legal_T_255, _atomics_legal_T_234) node _atomics_legal_T_257 = or(_atomics_legal_T_256, _atomics_legal_T_239) node _atomics_legal_T_258 = or(_atomics_legal_T_257, _atomics_legal_T_244) node _atomics_legal_T_259 = or(_atomics_legal_T_258, _atomics_legal_T_249) node _atomics_legal_T_260 = or(_atomics_legal_T_259, _atomics_legal_T_254) node _atomics_legal_T_261 = and(_atomics_legal_T_219, _atomics_legal_T_260) node _atomics_legal_T_262 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_263 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_264 = cvt(_atomics_legal_T_263) node _atomics_legal_T_265 = and(_atomics_legal_T_264, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_266 = asSInt(_atomics_legal_T_265) node _atomics_legal_T_267 = eq(_atomics_legal_T_266, asSInt(UInt<1>(0h0))) node _atomics_legal_T_268 = and(_atomics_legal_T_262, _atomics_legal_T_267) node _atomics_legal_T_269 = or(UInt<1>(0h0), _atomics_legal_T_261) node atomics_legal_4 = or(_atomics_legal_T_269, _atomics_legal_T_268) wire atomics_a_4 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect atomics_a_4.opcode, UInt<2>(0h2) connect atomics_a_4.param, UInt<3>(0h4) connect atomics_a_4.size, req.uop.mem_size connect atomics_a_4.source, UInt<2>(0h3) connect atomics_a_4.address, req.addr node _atomics_a_mask_sizeOH_T_12 = or(req.uop.mem_size, UInt<3>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_4 = bits(_atomics_a_mask_sizeOH_T_12, 1, 0) node _atomics_a_mask_sizeOH_T_13 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_4) node _atomics_a_mask_sizeOH_T_14 = bits(_atomics_a_mask_sizeOH_T_13, 2, 0) node atomics_a_mask_sizeOH_4 = or(_atomics_a_mask_sizeOH_T_14, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_0_1_4 = geq(req.uop.mem_size, UInt<2>(0h3)) node atomics_a_mask_sub_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 2, 2) node atomics_a_mask_sub_sub_bit_4 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_4 = eq(atomics_a_mask_sub_sub_bit_4, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_4) node _atomics_a_mask_sub_sub_acc_T_8 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_0_2_4) node atomics_a_mask_sub_sub_0_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_8) node atomics_a_mask_sub_sub_1_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_4) node _atomics_a_mask_sub_sub_acc_T_9 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_1_2_4) node atomics_a_mask_sub_sub_1_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_9) node atomics_a_mask_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 1, 1) node atomics_a_mask_sub_bit_4 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_4 = eq(atomics_a_mask_sub_bit_4, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_nbit_4) node _atomics_a_mask_sub_acc_T_16 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_0_2_4) node atomics_a_mask_sub_0_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_16) node atomics_a_mask_sub_1_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_bit_4) node _atomics_a_mask_sub_acc_T_17 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_1_2_4) node atomics_a_mask_sub_1_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_17) node atomics_a_mask_sub_2_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_nbit_4) node _atomics_a_mask_sub_acc_T_18 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_2_2_4) node atomics_a_mask_sub_2_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_18) node atomics_a_mask_sub_3_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_bit_4) node _atomics_a_mask_sub_acc_T_19 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_3_2_4) node atomics_a_mask_sub_3_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_19) node atomics_a_mask_size_4 = bits(atomics_a_mask_sizeOH_4, 0, 0) node atomics_a_mask_bit_4 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_4 = eq(atomics_a_mask_bit_4, UInt<1>(0h0)) node atomics_a_mask_eq_32 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_32 = and(atomics_a_mask_size_4, atomics_a_mask_eq_32) node atomics_a_mask_acc_32 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_32) node atomics_a_mask_eq_33 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_33 = and(atomics_a_mask_size_4, atomics_a_mask_eq_33) node atomics_a_mask_acc_33 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_33) node atomics_a_mask_eq_34 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_34 = and(atomics_a_mask_size_4, atomics_a_mask_eq_34) node atomics_a_mask_acc_34 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_34) node atomics_a_mask_eq_35 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_35 = and(atomics_a_mask_size_4, atomics_a_mask_eq_35) node atomics_a_mask_acc_35 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_35) node atomics_a_mask_eq_36 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_36 = and(atomics_a_mask_size_4, atomics_a_mask_eq_36) node atomics_a_mask_acc_36 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_36) node atomics_a_mask_eq_37 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_37 = and(atomics_a_mask_size_4, atomics_a_mask_eq_37) node atomics_a_mask_acc_37 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_37) node atomics_a_mask_eq_38 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_38 = and(atomics_a_mask_size_4, atomics_a_mask_eq_38) node atomics_a_mask_acc_38 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_38) node atomics_a_mask_eq_39 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_39 = and(atomics_a_mask_size_4, atomics_a_mask_eq_39) node atomics_a_mask_acc_39 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_39) node atomics_a_mask_lo_lo_4 = cat(atomics_a_mask_acc_33, atomics_a_mask_acc_32) node atomics_a_mask_lo_hi_4 = cat(atomics_a_mask_acc_35, atomics_a_mask_acc_34) node atomics_a_mask_lo_4 = cat(atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4) node atomics_a_mask_hi_lo_4 = cat(atomics_a_mask_acc_37, atomics_a_mask_acc_36) node atomics_a_mask_hi_hi_4 = cat(atomics_a_mask_acc_39, atomics_a_mask_acc_38) node atomics_a_mask_hi_4 = cat(atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4) node _atomics_a_mask_T_4 = cat(atomics_a_mask_hi_4, atomics_a_mask_lo_4) connect atomics_a_4.mask, _atomics_a_mask_T_4 connect atomics_a_4.data, req.data connect atomics_a_4.corrupt, UInt<1>(0h0) node _atomics_legal_T_270 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_271 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_272 = and(_atomics_legal_T_270, _atomics_legal_T_271) node _atomics_legal_T_273 = or(UInt<1>(0h0), _atomics_legal_T_272) node _atomics_legal_T_274 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_275 = cvt(_atomics_legal_T_274) node _atomics_legal_T_276 = and(_atomics_legal_T_275, asSInt(UInt<33>(0h98110000))) node _atomics_legal_T_277 = asSInt(_atomics_legal_T_276) node _atomics_legal_T_278 = eq(_atomics_legal_T_277, asSInt(UInt<1>(0h0))) node _atomics_legal_T_279 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_280 = cvt(_atomics_legal_T_279) node _atomics_legal_T_281 = and(_atomics_legal_T_280, asSInt(UInt<33>(0h9a101000))) node _atomics_legal_T_282 = asSInt(_atomics_legal_T_281) node _atomics_legal_T_283 = eq(_atomics_legal_T_282, asSInt(UInt<1>(0h0))) node _atomics_legal_T_284 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_285 = cvt(_atomics_legal_T_284) node _atomics_legal_T_286 = and(_atomics_legal_T_285, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_287 = asSInt(_atomics_legal_T_286) node _atomics_legal_T_288 = eq(_atomics_legal_T_287, asSInt(UInt<1>(0h0))) node _atomics_legal_T_289 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_290 = cvt(_atomics_legal_T_289) node _atomics_legal_T_291 = and(_atomics_legal_T_290, asSInt(UInt<33>(0h98000000))) node _atomics_legal_T_292 = asSInt(_atomics_legal_T_291) node _atomics_legal_T_293 = eq(_atomics_legal_T_292, asSInt(UInt<1>(0h0))) node _atomics_legal_T_294 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_295 = cvt(_atomics_legal_T_294) node _atomics_legal_T_296 = and(_atomics_legal_T_295, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_297 = asSInt(_atomics_legal_T_296) node _atomics_legal_T_298 = eq(_atomics_legal_T_297, asSInt(UInt<1>(0h0))) node _atomics_legal_T_299 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_300 = cvt(_atomics_legal_T_299) node _atomics_legal_T_301 = and(_atomics_legal_T_300, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_302 = asSInt(_atomics_legal_T_301) node _atomics_legal_T_303 = eq(_atomics_legal_T_302, asSInt(UInt<1>(0h0))) node _atomics_legal_T_304 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_305 = cvt(_atomics_legal_T_304) node _atomics_legal_T_306 = and(_atomics_legal_T_305, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_307 = asSInt(_atomics_legal_T_306) node _atomics_legal_T_308 = eq(_atomics_legal_T_307, asSInt(UInt<1>(0h0))) node _atomics_legal_T_309 = or(_atomics_legal_T_278, _atomics_legal_T_283) node _atomics_legal_T_310 = or(_atomics_legal_T_309, _atomics_legal_T_288) node _atomics_legal_T_311 = or(_atomics_legal_T_310, _atomics_legal_T_293) node _atomics_legal_T_312 = or(_atomics_legal_T_311, _atomics_legal_T_298) node _atomics_legal_T_313 = or(_atomics_legal_T_312, _atomics_legal_T_303) node _atomics_legal_T_314 = or(_atomics_legal_T_313, _atomics_legal_T_308) node _atomics_legal_T_315 = and(_atomics_legal_T_273, _atomics_legal_T_314) node _atomics_legal_T_316 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_317 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_318 = cvt(_atomics_legal_T_317) node _atomics_legal_T_319 = and(_atomics_legal_T_318, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_320 = asSInt(_atomics_legal_T_319) node _atomics_legal_T_321 = eq(_atomics_legal_T_320, asSInt(UInt<1>(0h0))) node _atomics_legal_T_322 = and(_atomics_legal_T_316, _atomics_legal_T_321) node _atomics_legal_T_323 = or(UInt<1>(0h0), _atomics_legal_T_315) node atomics_legal_5 = or(_atomics_legal_T_323, _atomics_legal_T_322) wire atomics_a_5 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect atomics_a_5.opcode, UInt<2>(0h2) connect atomics_a_5.param, UInt<3>(0h0) connect atomics_a_5.size, req.uop.mem_size connect atomics_a_5.source, UInt<2>(0h3) connect atomics_a_5.address, req.addr node _atomics_a_mask_sizeOH_T_15 = or(req.uop.mem_size, UInt<3>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_5 = bits(_atomics_a_mask_sizeOH_T_15, 1, 0) node _atomics_a_mask_sizeOH_T_16 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_5) node _atomics_a_mask_sizeOH_T_17 = bits(_atomics_a_mask_sizeOH_T_16, 2, 0) node atomics_a_mask_sizeOH_5 = or(_atomics_a_mask_sizeOH_T_17, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_0_1_5 = geq(req.uop.mem_size, UInt<2>(0h3)) node atomics_a_mask_sub_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 2, 2) node atomics_a_mask_sub_sub_bit_5 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_5 = eq(atomics_a_mask_sub_sub_bit_5, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_5) node _atomics_a_mask_sub_sub_acc_T_10 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_0_2_5) node atomics_a_mask_sub_sub_0_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_10) node atomics_a_mask_sub_sub_1_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_5) node _atomics_a_mask_sub_sub_acc_T_11 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_1_2_5) node atomics_a_mask_sub_sub_1_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_11) node atomics_a_mask_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 1, 1) node atomics_a_mask_sub_bit_5 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_5 = eq(atomics_a_mask_sub_bit_5, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_nbit_5) node _atomics_a_mask_sub_acc_T_20 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_0_2_5) node atomics_a_mask_sub_0_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_20) node atomics_a_mask_sub_1_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_bit_5) node _atomics_a_mask_sub_acc_T_21 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_1_2_5) node atomics_a_mask_sub_1_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_21) node atomics_a_mask_sub_2_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_nbit_5) node _atomics_a_mask_sub_acc_T_22 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_2_2_5) node atomics_a_mask_sub_2_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_22) node atomics_a_mask_sub_3_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_bit_5) node _atomics_a_mask_sub_acc_T_23 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_3_2_5) node atomics_a_mask_sub_3_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_23) node atomics_a_mask_size_5 = bits(atomics_a_mask_sizeOH_5, 0, 0) node atomics_a_mask_bit_5 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_5 = eq(atomics_a_mask_bit_5, UInt<1>(0h0)) node atomics_a_mask_eq_40 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_40 = and(atomics_a_mask_size_5, atomics_a_mask_eq_40) node atomics_a_mask_acc_40 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_40) node atomics_a_mask_eq_41 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_41 = and(atomics_a_mask_size_5, atomics_a_mask_eq_41) node atomics_a_mask_acc_41 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_41) node atomics_a_mask_eq_42 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_42 = and(atomics_a_mask_size_5, atomics_a_mask_eq_42) node atomics_a_mask_acc_42 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_42) node atomics_a_mask_eq_43 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_43 = and(atomics_a_mask_size_5, atomics_a_mask_eq_43) node atomics_a_mask_acc_43 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_43) node atomics_a_mask_eq_44 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_44 = and(atomics_a_mask_size_5, atomics_a_mask_eq_44) node atomics_a_mask_acc_44 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_44) node atomics_a_mask_eq_45 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_45 = and(atomics_a_mask_size_5, atomics_a_mask_eq_45) node atomics_a_mask_acc_45 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_45) node atomics_a_mask_eq_46 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_46 = and(atomics_a_mask_size_5, atomics_a_mask_eq_46) node atomics_a_mask_acc_46 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_46) node atomics_a_mask_eq_47 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_47 = and(atomics_a_mask_size_5, atomics_a_mask_eq_47) node atomics_a_mask_acc_47 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_47) node atomics_a_mask_lo_lo_5 = cat(atomics_a_mask_acc_41, atomics_a_mask_acc_40) node atomics_a_mask_lo_hi_5 = cat(atomics_a_mask_acc_43, atomics_a_mask_acc_42) node atomics_a_mask_lo_5 = cat(atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5) node atomics_a_mask_hi_lo_5 = cat(atomics_a_mask_acc_45, atomics_a_mask_acc_44) node atomics_a_mask_hi_hi_5 = cat(atomics_a_mask_acc_47, atomics_a_mask_acc_46) node atomics_a_mask_hi_5 = cat(atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5) node _atomics_a_mask_T_5 = cat(atomics_a_mask_hi_5, atomics_a_mask_lo_5) connect atomics_a_5.mask, _atomics_a_mask_T_5 connect atomics_a_5.data, req.data connect atomics_a_5.corrupt, UInt<1>(0h0) node _atomics_legal_T_324 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_325 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_326 = and(_atomics_legal_T_324, _atomics_legal_T_325) node _atomics_legal_T_327 = or(UInt<1>(0h0), _atomics_legal_T_326) node _atomics_legal_T_328 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_329 = cvt(_atomics_legal_T_328) node _atomics_legal_T_330 = and(_atomics_legal_T_329, asSInt(UInt<33>(0h98110000))) node _atomics_legal_T_331 = asSInt(_atomics_legal_T_330) node _atomics_legal_T_332 = eq(_atomics_legal_T_331, asSInt(UInt<1>(0h0))) node _atomics_legal_T_333 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_334 = cvt(_atomics_legal_T_333) node _atomics_legal_T_335 = and(_atomics_legal_T_334, asSInt(UInt<33>(0h9a101000))) node _atomics_legal_T_336 = asSInt(_atomics_legal_T_335) node _atomics_legal_T_337 = eq(_atomics_legal_T_336, asSInt(UInt<1>(0h0))) node _atomics_legal_T_338 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_339 = cvt(_atomics_legal_T_338) node _atomics_legal_T_340 = and(_atomics_legal_T_339, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_341 = asSInt(_atomics_legal_T_340) node _atomics_legal_T_342 = eq(_atomics_legal_T_341, asSInt(UInt<1>(0h0))) node _atomics_legal_T_343 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_344 = cvt(_atomics_legal_T_343) node _atomics_legal_T_345 = and(_atomics_legal_T_344, asSInt(UInt<33>(0h98000000))) node _atomics_legal_T_346 = asSInt(_atomics_legal_T_345) node _atomics_legal_T_347 = eq(_atomics_legal_T_346, asSInt(UInt<1>(0h0))) node _atomics_legal_T_348 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_349 = cvt(_atomics_legal_T_348) node _atomics_legal_T_350 = and(_atomics_legal_T_349, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_351 = asSInt(_atomics_legal_T_350) node _atomics_legal_T_352 = eq(_atomics_legal_T_351, asSInt(UInt<1>(0h0))) node _atomics_legal_T_353 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_354 = cvt(_atomics_legal_T_353) node _atomics_legal_T_355 = and(_atomics_legal_T_354, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_356 = asSInt(_atomics_legal_T_355) node _atomics_legal_T_357 = eq(_atomics_legal_T_356, asSInt(UInt<1>(0h0))) node _atomics_legal_T_358 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_359 = cvt(_atomics_legal_T_358) node _atomics_legal_T_360 = and(_atomics_legal_T_359, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_361 = asSInt(_atomics_legal_T_360) node _atomics_legal_T_362 = eq(_atomics_legal_T_361, asSInt(UInt<1>(0h0))) node _atomics_legal_T_363 = or(_atomics_legal_T_332, _atomics_legal_T_337) node _atomics_legal_T_364 = or(_atomics_legal_T_363, _atomics_legal_T_342) node _atomics_legal_T_365 = or(_atomics_legal_T_364, _atomics_legal_T_347) node _atomics_legal_T_366 = or(_atomics_legal_T_365, _atomics_legal_T_352) node _atomics_legal_T_367 = or(_atomics_legal_T_366, _atomics_legal_T_357) node _atomics_legal_T_368 = or(_atomics_legal_T_367, _atomics_legal_T_362) node _atomics_legal_T_369 = and(_atomics_legal_T_327, _atomics_legal_T_368) node _atomics_legal_T_370 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_371 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_372 = cvt(_atomics_legal_T_371) node _atomics_legal_T_373 = and(_atomics_legal_T_372, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_374 = asSInt(_atomics_legal_T_373) node _atomics_legal_T_375 = eq(_atomics_legal_T_374, asSInt(UInt<1>(0h0))) node _atomics_legal_T_376 = and(_atomics_legal_T_370, _atomics_legal_T_375) node _atomics_legal_T_377 = or(UInt<1>(0h0), _atomics_legal_T_369) node atomics_legal_6 = or(_atomics_legal_T_377, _atomics_legal_T_376) wire atomics_a_6 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect atomics_a_6.opcode, UInt<2>(0h2) connect atomics_a_6.param, UInt<3>(0h1) connect atomics_a_6.size, req.uop.mem_size connect atomics_a_6.source, UInt<2>(0h3) connect atomics_a_6.address, req.addr node _atomics_a_mask_sizeOH_T_18 = or(req.uop.mem_size, UInt<3>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_6 = bits(_atomics_a_mask_sizeOH_T_18, 1, 0) node _atomics_a_mask_sizeOH_T_19 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_6) node _atomics_a_mask_sizeOH_T_20 = bits(_atomics_a_mask_sizeOH_T_19, 2, 0) node atomics_a_mask_sizeOH_6 = or(_atomics_a_mask_sizeOH_T_20, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_0_1_6 = geq(req.uop.mem_size, UInt<2>(0h3)) node atomics_a_mask_sub_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 2, 2) node atomics_a_mask_sub_sub_bit_6 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_6 = eq(atomics_a_mask_sub_sub_bit_6, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_6) node _atomics_a_mask_sub_sub_acc_T_12 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_0_2_6) node atomics_a_mask_sub_sub_0_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_12) node atomics_a_mask_sub_sub_1_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_6) node _atomics_a_mask_sub_sub_acc_T_13 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_1_2_6) node atomics_a_mask_sub_sub_1_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_13) node atomics_a_mask_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 1, 1) node atomics_a_mask_sub_bit_6 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_6 = eq(atomics_a_mask_sub_bit_6, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_nbit_6) node _atomics_a_mask_sub_acc_T_24 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_0_2_6) node atomics_a_mask_sub_0_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_24) node atomics_a_mask_sub_1_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_bit_6) node _atomics_a_mask_sub_acc_T_25 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_1_2_6) node atomics_a_mask_sub_1_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_25) node atomics_a_mask_sub_2_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_nbit_6) node _atomics_a_mask_sub_acc_T_26 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_2_2_6) node atomics_a_mask_sub_2_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_26) node atomics_a_mask_sub_3_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_bit_6) node _atomics_a_mask_sub_acc_T_27 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_3_2_6) node atomics_a_mask_sub_3_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_27) node atomics_a_mask_size_6 = bits(atomics_a_mask_sizeOH_6, 0, 0) node atomics_a_mask_bit_6 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_6 = eq(atomics_a_mask_bit_6, UInt<1>(0h0)) node atomics_a_mask_eq_48 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_48 = and(atomics_a_mask_size_6, atomics_a_mask_eq_48) node atomics_a_mask_acc_48 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_48) node atomics_a_mask_eq_49 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_49 = and(atomics_a_mask_size_6, atomics_a_mask_eq_49) node atomics_a_mask_acc_49 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_49) node atomics_a_mask_eq_50 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_50 = and(atomics_a_mask_size_6, atomics_a_mask_eq_50) node atomics_a_mask_acc_50 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_50) node atomics_a_mask_eq_51 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_51 = and(atomics_a_mask_size_6, atomics_a_mask_eq_51) node atomics_a_mask_acc_51 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_51) node atomics_a_mask_eq_52 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_52 = and(atomics_a_mask_size_6, atomics_a_mask_eq_52) node atomics_a_mask_acc_52 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_52) node atomics_a_mask_eq_53 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_53 = and(atomics_a_mask_size_6, atomics_a_mask_eq_53) node atomics_a_mask_acc_53 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_53) node atomics_a_mask_eq_54 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_54 = and(atomics_a_mask_size_6, atomics_a_mask_eq_54) node atomics_a_mask_acc_54 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_54) node atomics_a_mask_eq_55 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_55 = and(atomics_a_mask_size_6, atomics_a_mask_eq_55) node atomics_a_mask_acc_55 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_55) node atomics_a_mask_lo_lo_6 = cat(atomics_a_mask_acc_49, atomics_a_mask_acc_48) node atomics_a_mask_lo_hi_6 = cat(atomics_a_mask_acc_51, atomics_a_mask_acc_50) node atomics_a_mask_lo_6 = cat(atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6) node atomics_a_mask_hi_lo_6 = cat(atomics_a_mask_acc_53, atomics_a_mask_acc_52) node atomics_a_mask_hi_hi_6 = cat(atomics_a_mask_acc_55, atomics_a_mask_acc_54) node atomics_a_mask_hi_6 = cat(atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6) node _atomics_a_mask_T_6 = cat(atomics_a_mask_hi_6, atomics_a_mask_lo_6) connect atomics_a_6.mask, _atomics_a_mask_T_6 connect atomics_a_6.data, req.data connect atomics_a_6.corrupt, UInt<1>(0h0) node _atomics_legal_T_378 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_379 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_380 = and(_atomics_legal_T_378, _atomics_legal_T_379) node _atomics_legal_T_381 = or(UInt<1>(0h0), _atomics_legal_T_380) node _atomics_legal_T_382 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_383 = cvt(_atomics_legal_T_382) node _atomics_legal_T_384 = and(_atomics_legal_T_383, asSInt(UInt<33>(0h98110000))) node _atomics_legal_T_385 = asSInt(_atomics_legal_T_384) node _atomics_legal_T_386 = eq(_atomics_legal_T_385, asSInt(UInt<1>(0h0))) node _atomics_legal_T_387 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_388 = cvt(_atomics_legal_T_387) node _atomics_legal_T_389 = and(_atomics_legal_T_388, asSInt(UInt<33>(0h9a101000))) node _atomics_legal_T_390 = asSInt(_atomics_legal_T_389) node _atomics_legal_T_391 = eq(_atomics_legal_T_390, asSInt(UInt<1>(0h0))) node _atomics_legal_T_392 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_393 = cvt(_atomics_legal_T_392) node _atomics_legal_T_394 = and(_atomics_legal_T_393, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_395 = asSInt(_atomics_legal_T_394) node _atomics_legal_T_396 = eq(_atomics_legal_T_395, asSInt(UInt<1>(0h0))) node _atomics_legal_T_397 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_398 = cvt(_atomics_legal_T_397) node _atomics_legal_T_399 = and(_atomics_legal_T_398, asSInt(UInt<33>(0h98000000))) node _atomics_legal_T_400 = asSInt(_atomics_legal_T_399) node _atomics_legal_T_401 = eq(_atomics_legal_T_400, asSInt(UInt<1>(0h0))) node _atomics_legal_T_402 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_403 = cvt(_atomics_legal_T_402) node _atomics_legal_T_404 = and(_atomics_legal_T_403, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_405 = asSInt(_atomics_legal_T_404) node _atomics_legal_T_406 = eq(_atomics_legal_T_405, asSInt(UInt<1>(0h0))) node _atomics_legal_T_407 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_408 = cvt(_atomics_legal_T_407) node _atomics_legal_T_409 = and(_atomics_legal_T_408, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_410 = asSInt(_atomics_legal_T_409) node _atomics_legal_T_411 = eq(_atomics_legal_T_410, asSInt(UInt<1>(0h0))) node _atomics_legal_T_412 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_413 = cvt(_atomics_legal_T_412) node _atomics_legal_T_414 = and(_atomics_legal_T_413, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_415 = asSInt(_atomics_legal_T_414) node _atomics_legal_T_416 = eq(_atomics_legal_T_415, asSInt(UInt<1>(0h0))) node _atomics_legal_T_417 = or(_atomics_legal_T_386, _atomics_legal_T_391) node _atomics_legal_T_418 = or(_atomics_legal_T_417, _atomics_legal_T_396) node _atomics_legal_T_419 = or(_atomics_legal_T_418, _atomics_legal_T_401) node _atomics_legal_T_420 = or(_atomics_legal_T_419, _atomics_legal_T_406) node _atomics_legal_T_421 = or(_atomics_legal_T_420, _atomics_legal_T_411) node _atomics_legal_T_422 = or(_atomics_legal_T_421, _atomics_legal_T_416) node _atomics_legal_T_423 = and(_atomics_legal_T_381, _atomics_legal_T_422) node _atomics_legal_T_424 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_425 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_426 = cvt(_atomics_legal_T_425) node _atomics_legal_T_427 = and(_atomics_legal_T_426, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_428 = asSInt(_atomics_legal_T_427) node _atomics_legal_T_429 = eq(_atomics_legal_T_428, asSInt(UInt<1>(0h0))) node _atomics_legal_T_430 = and(_atomics_legal_T_424, _atomics_legal_T_429) node _atomics_legal_T_431 = or(UInt<1>(0h0), _atomics_legal_T_423) node atomics_legal_7 = or(_atomics_legal_T_431, _atomics_legal_T_430) wire atomics_a_7 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect atomics_a_7.opcode, UInt<2>(0h2) connect atomics_a_7.param, UInt<3>(0h2) connect atomics_a_7.size, req.uop.mem_size connect atomics_a_7.source, UInt<2>(0h3) connect atomics_a_7.address, req.addr node _atomics_a_mask_sizeOH_T_21 = or(req.uop.mem_size, UInt<3>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_7 = bits(_atomics_a_mask_sizeOH_T_21, 1, 0) node _atomics_a_mask_sizeOH_T_22 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_7) node _atomics_a_mask_sizeOH_T_23 = bits(_atomics_a_mask_sizeOH_T_22, 2, 0) node atomics_a_mask_sizeOH_7 = or(_atomics_a_mask_sizeOH_T_23, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_0_1_7 = geq(req.uop.mem_size, UInt<2>(0h3)) node atomics_a_mask_sub_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 2, 2) node atomics_a_mask_sub_sub_bit_7 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_7 = eq(atomics_a_mask_sub_sub_bit_7, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_7) node _atomics_a_mask_sub_sub_acc_T_14 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_0_2_7) node atomics_a_mask_sub_sub_0_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_14) node atomics_a_mask_sub_sub_1_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_7) node _atomics_a_mask_sub_sub_acc_T_15 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_1_2_7) node atomics_a_mask_sub_sub_1_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_15) node atomics_a_mask_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 1, 1) node atomics_a_mask_sub_bit_7 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_7 = eq(atomics_a_mask_sub_bit_7, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_nbit_7) node _atomics_a_mask_sub_acc_T_28 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_0_2_7) node atomics_a_mask_sub_0_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_28) node atomics_a_mask_sub_1_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_bit_7) node _atomics_a_mask_sub_acc_T_29 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_1_2_7) node atomics_a_mask_sub_1_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_29) node atomics_a_mask_sub_2_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_nbit_7) node _atomics_a_mask_sub_acc_T_30 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_2_2_7) node atomics_a_mask_sub_2_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_30) node atomics_a_mask_sub_3_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_bit_7) node _atomics_a_mask_sub_acc_T_31 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_3_2_7) node atomics_a_mask_sub_3_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_31) node atomics_a_mask_size_7 = bits(atomics_a_mask_sizeOH_7, 0, 0) node atomics_a_mask_bit_7 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_7 = eq(atomics_a_mask_bit_7, UInt<1>(0h0)) node atomics_a_mask_eq_56 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_56 = and(atomics_a_mask_size_7, atomics_a_mask_eq_56) node atomics_a_mask_acc_56 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_56) node atomics_a_mask_eq_57 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_57 = and(atomics_a_mask_size_7, atomics_a_mask_eq_57) node atomics_a_mask_acc_57 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_57) node atomics_a_mask_eq_58 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_58 = and(atomics_a_mask_size_7, atomics_a_mask_eq_58) node atomics_a_mask_acc_58 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_58) node atomics_a_mask_eq_59 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_59 = and(atomics_a_mask_size_7, atomics_a_mask_eq_59) node atomics_a_mask_acc_59 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_59) node atomics_a_mask_eq_60 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_60 = and(atomics_a_mask_size_7, atomics_a_mask_eq_60) node atomics_a_mask_acc_60 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_60) node atomics_a_mask_eq_61 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_61 = and(atomics_a_mask_size_7, atomics_a_mask_eq_61) node atomics_a_mask_acc_61 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_61) node atomics_a_mask_eq_62 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_62 = and(atomics_a_mask_size_7, atomics_a_mask_eq_62) node atomics_a_mask_acc_62 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_62) node atomics_a_mask_eq_63 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_63 = and(atomics_a_mask_size_7, atomics_a_mask_eq_63) node atomics_a_mask_acc_63 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_63) node atomics_a_mask_lo_lo_7 = cat(atomics_a_mask_acc_57, atomics_a_mask_acc_56) node atomics_a_mask_lo_hi_7 = cat(atomics_a_mask_acc_59, atomics_a_mask_acc_58) node atomics_a_mask_lo_7 = cat(atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7) node atomics_a_mask_hi_lo_7 = cat(atomics_a_mask_acc_61, atomics_a_mask_acc_60) node atomics_a_mask_hi_hi_7 = cat(atomics_a_mask_acc_63, atomics_a_mask_acc_62) node atomics_a_mask_hi_7 = cat(atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7) node _atomics_a_mask_T_7 = cat(atomics_a_mask_hi_7, atomics_a_mask_lo_7) connect atomics_a_7.mask, _atomics_a_mask_T_7 connect atomics_a_7.data, req.data connect atomics_a_7.corrupt, UInt<1>(0h0) node _atomics_legal_T_432 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_433 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_434 = and(_atomics_legal_T_432, _atomics_legal_T_433) node _atomics_legal_T_435 = or(UInt<1>(0h0), _atomics_legal_T_434) node _atomics_legal_T_436 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_437 = cvt(_atomics_legal_T_436) node _atomics_legal_T_438 = and(_atomics_legal_T_437, asSInt(UInt<33>(0h98110000))) node _atomics_legal_T_439 = asSInt(_atomics_legal_T_438) node _atomics_legal_T_440 = eq(_atomics_legal_T_439, asSInt(UInt<1>(0h0))) node _atomics_legal_T_441 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_442 = cvt(_atomics_legal_T_441) node _atomics_legal_T_443 = and(_atomics_legal_T_442, asSInt(UInt<33>(0h9a101000))) node _atomics_legal_T_444 = asSInt(_atomics_legal_T_443) node _atomics_legal_T_445 = eq(_atomics_legal_T_444, asSInt(UInt<1>(0h0))) node _atomics_legal_T_446 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_447 = cvt(_atomics_legal_T_446) node _atomics_legal_T_448 = and(_atomics_legal_T_447, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_449 = asSInt(_atomics_legal_T_448) node _atomics_legal_T_450 = eq(_atomics_legal_T_449, asSInt(UInt<1>(0h0))) node _atomics_legal_T_451 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_452 = cvt(_atomics_legal_T_451) node _atomics_legal_T_453 = and(_atomics_legal_T_452, asSInt(UInt<33>(0h98000000))) node _atomics_legal_T_454 = asSInt(_atomics_legal_T_453) node _atomics_legal_T_455 = eq(_atomics_legal_T_454, asSInt(UInt<1>(0h0))) node _atomics_legal_T_456 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_457 = cvt(_atomics_legal_T_456) node _atomics_legal_T_458 = and(_atomics_legal_T_457, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_459 = asSInt(_atomics_legal_T_458) node _atomics_legal_T_460 = eq(_atomics_legal_T_459, asSInt(UInt<1>(0h0))) node _atomics_legal_T_461 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_462 = cvt(_atomics_legal_T_461) node _atomics_legal_T_463 = and(_atomics_legal_T_462, asSInt(UInt<33>(0h9a111000))) node _atomics_legal_T_464 = asSInt(_atomics_legal_T_463) node _atomics_legal_T_465 = eq(_atomics_legal_T_464, asSInt(UInt<1>(0h0))) node _atomics_legal_T_466 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_467 = cvt(_atomics_legal_T_466) node _atomics_legal_T_468 = and(_atomics_legal_T_467, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_469 = asSInt(_atomics_legal_T_468) node _atomics_legal_T_470 = eq(_atomics_legal_T_469, asSInt(UInt<1>(0h0))) node _atomics_legal_T_471 = or(_atomics_legal_T_440, _atomics_legal_T_445) node _atomics_legal_T_472 = or(_atomics_legal_T_471, _atomics_legal_T_450) node _atomics_legal_T_473 = or(_atomics_legal_T_472, _atomics_legal_T_455) node _atomics_legal_T_474 = or(_atomics_legal_T_473, _atomics_legal_T_460) node _atomics_legal_T_475 = or(_atomics_legal_T_474, _atomics_legal_T_465) node _atomics_legal_T_476 = or(_atomics_legal_T_475, _atomics_legal_T_470) node _atomics_legal_T_477 = and(_atomics_legal_T_435, _atomics_legal_T_476) node _atomics_legal_T_478 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_479 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_480 = cvt(_atomics_legal_T_479) node _atomics_legal_T_481 = and(_atomics_legal_T_480, asSInt(UInt<33>(0h9a110000))) node _atomics_legal_T_482 = asSInt(_atomics_legal_T_481) node _atomics_legal_T_483 = eq(_atomics_legal_T_482, asSInt(UInt<1>(0h0))) node _atomics_legal_T_484 = and(_atomics_legal_T_478, _atomics_legal_T_483) node _atomics_legal_T_485 = or(UInt<1>(0h0), _atomics_legal_T_477) node atomics_legal_8 = or(_atomics_legal_T_485, _atomics_legal_T_484) wire atomics_a_8 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect atomics_a_8.opcode, UInt<2>(0h2) connect atomics_a_8.param, UInt<3>(0h3) connect atomics_a_8.size, req.uop.mem_size connect atomics_a_8.source, UInt<2>(0h3) connect atomics_a_8.address, req.addr node _atomics_a_mask_sizeOH_T_24 = or(req.uop.mem_size, UInt<3>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_8 = bits(_atomics_a_mask_sizeOH_T_24, 1, 0) node _atomics_a_mask_sizeOH_T_25 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_8) node _atomics_a_mask_sizeOH_T_26 = bits(_atomics_a_mask_sizeOH_T_25, 2, 0) node atomics_a_mask_sizeOH_8 = or(_atomics_a_mask_sizeOH_T_26, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_0_1_8 = geq(req.uop.mem_size, UInt<2>(0h3)) node atomics_a_mask_sub_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 2, 2) node atomics_a_mask_sub_sub_bit_8 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_8 = eq(atomics_a_mask_sub_sub_bit_8, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_8) node _atomics_a_mask_sub_sub_acc_T_16 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_0_2_8) node atomics_a_mask_sub_sub_0_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_16) node atomics_a_mask_sub_sub_1_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_8) node _atomics_a_mask_sub_sub_acc_T_17 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_1_2_8) node atomics_a_mask_sub_sub_1_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_17) node atomics_a_mask_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 1, 1) node atomics_a_mask_sub_bit_8 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_8 = eq(atomics_a_mask_sub_bit_8, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_nbit_8) node _atomics_a_mask_sub_acc_T_32 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_0_2_8) node atomics_a_mask_sub_0_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_32) node atomics_a_mask_sub_1_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_bit_8) node _atomics_a_mask_sub_acc_T_33 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_1_2_8) node atomics_a_mask_sub_1_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_33) node atomics_a_mask_sub_2_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_nbit_8) node _atomics_a_mask_sub_acc_T_34 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_2_2_8) node atomics_a_mask_sub_2_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_34) node atomics_a_mask_sub_3_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_bit_8) node _atomics_a_mask_sub_acc_T_35 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_3_2_8) node atomics_a_mask_sub_3_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_35) node atomics_a_mask_size_8 = bits(atomics_a_mask_sizeOH_8, 0, 0) node atomics_a_mask_bit_8 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_8 = eq(atomics_a_mask_bit_8, UInt<1>(0h0)) node atomics_a_mask_eq_64 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_64 = and(atomics_a_mask_size_8, atomics_a_mask_eq_64) node atomics_a_mask_acc_64 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_64) node atomics_a_mask_eq_65 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_65 = and(atomics_a_mask_size_8, atomics_a_mask_eq_65) node atomics_a_mask_acc_65 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_65) node atomics_a_mask_eq_66 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_66 = and(atomics_a_mask_size_8, atomics_a_mask_eq_66) node atomics_a_mask_acc_66 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_66) node atomics_a_mask_eq_67 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_67 = and(atomics_a_mask_size_8, atomics_a_mask_eq_67) node atomics_a_mask_acc_67 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_67) node atomics_a_mask_eq_68 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_68 = and(atomics_a_mask_size_8, atomics_a_mask_eq_68) node atomics_a_mask_acc_68 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_68) node atomics_a_mask_eq_69 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_69 = and(atomics_a_mask_size_8, atomics_a_mask_eq_69) node atomics_a_mask_acc_69 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_69) node atomics_a_mask_eq_70 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_70 = and(atomics_a_mask_size_8, atomics_a_mask_eq_70) node atomics_a_mask_acc_70 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_70) node atomics_a_mask_eq_71 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_71 = and(atomics_a_mask_size_8, atomics_a_mask_eq_71) node atomics_a_mask_acc_71 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_71) node atomics_a_mask_lo_lo_8 = cat(atomics_a_mask_acc_65, atomics_a_mask_acc_64) node atomics_a_mask_lo_hi_8 = cat(atomics_a_mask_acc_67, atomics_a_mask_acc_66) node atomics_a_mask_lo_8 = cat(atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8) node atomics_a_mask_hi_lo_8 = cat(atomics_a_mask_acc_69, atomics_a_mask_acc_68) node atomics_a_mask_hi_hi_8 = cat(atomics_a_mask_acc_71, atomics_a_mask_acc_70) node atomics_a_mask_hi_8 = cat(atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8) node _atomics_a_mask_T_8 = cat(atomics_a_mask_hi_8, atomics_a_mask_lo_8) connect atomics_a_8.mask, _atomics_a_mask_T_8 connect atomics_a_8.data, req.data connect atomics_a_8.corrupt, UInt<1>(0h0) node _atomics_T = eq(UInt<3>(0h4), req.uop.mem_cmd) node _atomics_T_1 = mux(_atomics_T, atomics_a, _atomics_WIRE) node _atomics_T_2 = eq(UInt<4>(0h9), req.uop.mem_cmd) node _atomics_T_3 = mux(_atomics_T_2, atomics_a_1, _atomics_T_1) node _atomics_T_4 = eq(UInt<4>(0ha), req.uop.mem_cmd) node _atomics_T_5 = mux(_atomics_T_4, atomics_a_2, _atomics_T_3) node _atomics_T_6 = eq(UInt<4>(0hb), req.uop.mem_cmd) node _atomics_T_7 = mux(_atomics_T_6, atomics_a_3, _atomics_T_5) node _atomics_T_8 = eq(UInt<4>(0h8), req.uop.mem_cmd) node _atomics_T_9 = mux(_atomics_T_8, atomics_a_4, _atomics_T_7) node _atomics_T_10 = eq(UInt<4>(0hc), req.uop.mem_cmd) node _atomics_T_11 = mux(_atomics_T_10, atomics_a_5, _atomics_T_9) node _atomics_T_12 = eq(UInt<4>(0hd), req.uop.mem_cmd) node _atomics_T_13 = mux(_atomics_T_12, atomics_a_6, _atomics_T_11) node _atomics_T_14 = eq(UInt<4>(0he), req.uop.mem_cmd) node _atomics_T_15 = mux(_atomics_T_14, atomics_a_7, _atomics_T_13) node _atomics_T_16 = eq(UInt<4>(0hf), req.uop.mem_cmd) node atomics = mux(_atomics_T_16, atomics_a_8, _atomics_T_15) node _T = eq(state, UInt<2>(0h0)) node _T_1 = neq(req.uop.mem_cmd, UInt<3>(0h7)) node _T_2 = or(_T, _T_1) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:454 assert(state === s_idle || req.uop.mem_cmd =/= M_XSC)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_mem_access_valid_T = eq(state, UInt<2>(0h1)) connect io.mem_access.valid, _io_mem_access_valid_T node _io_mem_access_bits_T = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _io_mem_access_bits_T_1 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _io_mem_access_bits_T_2 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _io_mem_access_bits_T_3 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _io_mem_access_bits_T_4 = or(_io_mem_access_bits_T, _io_mem_access_bits_T_1) node _io_mem_access_bits_T_5 = or(_io_mem_access_bits_T_4, _io_mem_access_bits_T_2) node _io_mem_access_bits_T_6 = or(_io_mem_access_bits_T_5, _io_mem_access_bits_T_3) node _io_mem_access_bits_T_7 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _io_mem_access_bits_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _io_mem_access_bits_T_9 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _io_mem_access_bits_T_10 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _io_mem_access_bits_T_11 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _io_mem_access_bits_T_12 = or(_io_mem_access_bits_T_7, _io_mem_access_bits_T_8) node _io_mem_access_bits_T_13 = or(_io_mem_access_bits_T_12, _io_mem_access_bits_T_9) node _io_mem_access_bits_T_14 = or(_io_mem_access_bits_T_13, _io_mem_access_bits_T_10) node _io_mem_access_bits_T_15 = or(_io_mem_access_bits_T_14, _io_mem_access_bits_T_11) node _io_mem_access_bits_T_16 = or(_io_mem_access_bits_T_6, _io_mem_access_bits_T_15) node _io_mem_access_bits_T_17 = eq(req.uop.mem_cmd, UInt<1>(0h0)) node _io_mem_access_bits_T_18 = eq(req.uop.mem_cmd, UInt<5>(0h10)) node _io_mem_access_bits_T_19 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _io_mem_access_bits_T_20 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _io_mem_access_bits_T_21 = or(_io_mem_access_bits_T_17, _io_mem_access_bits_T_18) node _io_mem_access_bits_T_22 = or(_io_mem_access_bits_T_21, _io_mem_access_bits_T_19) node _io_mem_access_bits_T_23 = or(_io_mem_access_bits_T_22, _io_mem_access_bits_T_20) node _io_mem_access_bits_T_24 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _io_mem_access_bits_T_25 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _io_mem_access_bits_T_26 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _io_mem_access_bits_T_27 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _io_mem_access_bits_T_28 = or(_io_mem_access_bits_T_24, _io_mem_access_bits_T_25) node _io_mem_access_bits_T_29 = or(_io_mem_access_bits_T_28, _io_mem_access_bits_T_26) node _io_mem_access_bits_T_30 = or(_io_mem_access_bits_T_29, _io_mem_access_bits_T_27) node _io_mem_access_bits_T_31 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _io_mem_access_bits_T_32 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _io_mem_access_bits_T_33 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _io_mem_access_bits_T_34 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _io_mem_access_bits_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _io_mem_access_bits_T_36 = or(_io_mem_access_bits_T_31, _io_mem_access_bits_T_32) node _io_mem_access_bits_T_37 = or(_io_mem_access_bits_T_36, _io_mem_access_bits_T_33) node _io_mem_access_bits_T_38 = or(_io_mem_access_bits_T_37, _io_mem_access_bits_T_34) node _io_mem_access_bits_T_39 = or(_io_mem_access_bits_T_38, _io_mem_access_bits_T_35) node _io_mem_access_bits_T_40 = or(_io_mem_access_bits_T_30, _io_mem_access_bits_T_39) node _io_mem_access_bits_T_41 = or(_io_mem_access_bits_T_23, _io_mem_access_bits_T_40) node _io_mem_access_bits_T_42 = mux(_io_mem_access_bits_T_41, get, put) node _io_mem_access_bits_T_43 = mux(_io_mem_access_bits_T_16, atomics, _io_mem_access_bits_T_42) connect io.mem_access.bits, _io_mem_access_bits_T_43 node _send_resp_T = eq(req.uop.mem_cmd, UInt<1>(0h0)) node _send_resp_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h10)) node _send_resp_T_2 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _send_resp_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _send_resp_T_4 = or(_send_resp_T, _send_resp_T_1) node _send_resp_T_5 = or(_send_resp_T_4, _send_resp_T_2) node _send_resp_T_6 = or(_send_resp_T_5, _send_resp_T_3) node _send_resp_T_7 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _send_resp_T_8 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _send_resp_T_9 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _send_resp_T_10 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _send_resp_T_11 = or(_send_resp_T_7, _send_resp_T_8) node _send_resp_T_12 = or(_send_resp_T_11, _send_resp_T_9) node _send_resp_T_13 = or(_send_resp_T_12, _send_resp_T_10) node _send_resp_T_14 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _send_resp_T_15 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _send_resp_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _send_resp_T_17 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _send_resp_T_18 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _send_resp_T_19 = or(_send_resp_T_14, _send_resp_T_15) node _send_resp_T_20 = or(_send_resp_T_19, _send_resp_T_16) node _send_resp_T_21 = or(_send_resp_T_20, _send_resp_T_17) node _send_resp_T_22 = or(_send_resp_T_21, _send_resp_T_18) node _send_resp_T_23 = or(_send_resp_T_13, _send_resp_T_22) node send_resp = or(_send_resp_T_6, _send_resp_T_23) node _io_resp_valid_T = eq(state, UInt<2>(0h3)) node _io_resp_valid_T_1 = and(_io_resp_valid_T, send_resp) connect io.resp.valid, _io_resp_valid_T_1 connect io.resp.bits.is_hella, req.is_hella connect io.resp.bits.uop, req.uop node _io_resp_bits_data_shifted_T = bits(req.addr, 2, 2) node _io_resp_bits_data_shifted_T_1 = bits(grant_word, 63, 32) node _io_resp_bits_data_shifted_T_2 = bits(grant_word, 31, 0) node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2) node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted) node _io_resp_bits_data_T = eq(size, UInt<2>(0h2)) node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero) node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31) node _io_resp_bits_data_T_3 = and(req.uop.mem_signed, _io_resp_bits_data_T_2) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_resp_bits_data_T_5 = bits(grant_word, 63, 32) node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5) node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed) node _io_resp_bits_data_shifted_T_3 = bits(req.addr, 1, 1) node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16) node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0) node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5) node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1) node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1)) node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1) node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15) node _io_resp_bits_data_T_11 = and(req.uop.mem_signed, _io_resp_bits_data_T_10) node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16) node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13) node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1) node _io_resp_bits_data_shifted_T_6 = bits(req.addr, 0, 0) node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8) node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0) node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8) node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2) node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0)) node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2) node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7) node _io_resp_bits_data_T_19 = and(req.uop.mem_signed, _io_resp_bits_data_T_18) node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8) node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21) node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2) connect io.resp.bits.data, _io_resp_bits_data_T_23 node _T_6 = and(io.req.ready, io.req.valid) when _T_6 : connect req, io.req.bits connect state, UInt<2>(0h1) node _T_7 = and(io.mem_access.ready, io.mem_access.valid) when _T_7 : connect state, UInt<2>(0h2) node _T_8 = eq(state, UInt<2>(0h2)) node _T_9 = and(_T_8, io.mem_ack.valid) when _T_9 : connect state, UInt<2>(0h3) node _T_10 = eq(req.uop.mem_cmd, UInt<1>(0h0)) node _T_11 = eq(req.uop.mem_cmd, UInt<5>(0h10)) node _T_12 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _T_13 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _T_14 = or(_T_10, _T_11) node _T_15 = or(_T_14, _T_12) node _T_16 = or(_T_15, _T_13) node _T_17 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _T_18 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _T_19 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _T_20 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _T_21 = or(_T_17, _T_18) node _T_22 = or(_T_21, _T_19) node _T_23 = or(_T_22, _T_20) node _T_24 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _T_25 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _T_26 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _T_27 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _T_28 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _T_29 = or(_T_24, _T_25) node _T_30 = or(_T_29, _T_26) node _T_31 = or(_T_30, _T_27) node _T_32 = or(_T_31, _T_28) node _T_33 = or(_T_23, _T_32) node _T_34 = or(_T_16, _T_33) when _T_34 : node grant_word_shift = cat(UInt<1>(0h0), UInt<6>(0h0)) node _grant_word_T = dshr(io.mem_ack.bits.data, grant_word_shift) node _grant_word_T_1 = bits(_grant_word_T, 63, 0) connect grant_word, _grant_word_T_1 node _T_35 = eq(state, UInt<2>(0h3)) when _T_35 : node _T_36 = eq(send_resp, UInt<1>(0h0)) node _T_37 = and(io.resp.ready, io.resp.valid) node _T_38 = or(_T_36, _T_37) when _T_38 : connect state, UInt<2>(0h0)
module BoomIOMSHR( // @[mshrs.scala:402:7] input clock, // @[mshrs.scala:402:7] input reset, // @[mshrs.scala:402:7] output io_req_ready, // @[mshrs.scala:405:14] input io_req_valid, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_uopc, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_inst, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_debug_inst, // @[mshrs.scala:405:14] input io_req_bits_uop_is_rvc, // @[mshrs.scala:405:14] input [39:0] io_req_bits_uop_debug_pc, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_iq_type, // @[mshrs.scala:405:14] input [9:0] io_req_bits_uop_fu_code, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_iw_state, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_is_br, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jalr, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jal, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sfb, // @[mshrs.scala:405:14] input [7:0] io_req_bits_uop_br_mask, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_br_tag, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ftq_idx, // @[mshrs.scala:405:14] input io_req_bits_uop_edge_inst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_pc_lob, // @[mshrs.scala:405:14] input io_req_bits_uop_taken, // @[mshrs.scala:405:14] input [19:0] io_req_bits_uop_imm_packed, // @[mshrs.scala:405:14] input [11:0] io_req_bits_uop_csr_addr, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_rob_idx, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ldq_idx, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_stq_idx, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_rxq_idx, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_pdst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_prs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_prs2, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_prs3, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ppred, // @[mshrs.scala:405:14] input io_req_bits_uop_prs1_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs2_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs3_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_ppred_busy, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_stale_pdst, // @[mshrs.scala:405:14] input io_req_bits_uop_exception, // @[mshrs.scala:405:14] input [63:0] io_req_bits_uop_exc_cause, // @[mshrs.scala:405:14] input io_req_bits_uop_bypassable, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_mem_cmd, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_mem_size, // @[mshrs.scala:405:14] input io_req_bits_uop_mem_signed, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fence, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fencei, // @[mshrs.scala:405:14] input io_req_bits_uop_is_amo, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_ldq, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_stq, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] input io_req_bits_uop_is_unique, // @[mshrs.scala:405:14] input io_req_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_ldst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs2, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs3, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_val, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_dst_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] input io_req_bits_uop_frs3_en, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_val, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_single, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] input [39:0] io_req_bits_addr, // @[mshrs.scala:405:14] input [63:0] io_req_bits_data, // @[mshrs.scala:405:14] input io_req_bits_is_hella, // @[mshrs.scala:405:14] input io_resp_ready, // @[mshrs.scala:405:14] output io_resp_valid, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:405:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:405:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:405:14] output [7:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:405:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:405:14] output io_resp_bits_uop_taken, // @[mshrs.scala:405:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:405:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_pdst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_prs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_prs2, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_prs3, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:405:14] output io_resp_bits_uop_exception, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:405:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:405:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:405:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:405:14] output io_resp_bits_is_hella, // @[mshrs.scala:405:14] input io_mem_access_ready, // @[mshrs.scala:405:14] output io_mem_access_valid, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_opcode, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_param, // @[mshrs.scala:405:14] output [3:0] io_mem_access_bits_size, // @[mshrs.scala:405:14] output [1:0] io_mem_access_bits_source, // @[mshrs.scala:405:14] output [31:0] io_mem_access_bits_address, // @[mshrs.scala:405:14] output [7:0] io_mem_access_bits_mask, // @[mshrs.scala:405:14] output [63:0] io_mem_access_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_valid, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_opcode, // @[mshrs.scala:405:14] input [1:0] io_mem_ack_bits_param, // @[mshrs.scala:405:14] input [3:0] io_mem_ack_bits_size, // @[mshrs.scala:405:14] input [1:0] io_mem_ack_bits_source, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_sink, // @[mshrs.scala:405:14] input io_mem_ack_bits_denied, // @[mshrs.scala:405:14] input [63:0] io_mem_ack_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_bits_corrupt // @[mshrs.scala:405:14] ); wire io_req_valid_0 = io_req_valid; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[mshrs.scala:402:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[mshrs.scala:402:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[mshrs.scala:402:7] wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[mshrs.scala:402:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[mshrs.scala:402:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[mshrs.scala:402:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[mshrs.scala:402:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[mshrs.scala:402:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[mshrs.scala:402:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[mshrs.scala:402:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[mshrs.scala:402:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[mshrs.scala:402:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[mshrs.scala:402:7] wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[mshrs.scala:402:7] wire io_req_bits_is_hella_0 = io_req_bits_is_hella; // @[mshrs.scala:402:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:402:7] wire io_mem_access_ready_0 = io_mem_access_ready; // @[mshrs.scala:402:7] wire io_mem_ack_valid_0 = io_mem_ack_valid; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_opcode_0 = io_mem_ack_bits_opcode; // @[mshrs.scala:402:7] wire [1:0] io_mem_ack_bits_param_0 = io_mem_ack_bits_param; // @[mshrs.scala:402:7] wire [3:0] io_mem_ack_bits_size_0 = io_mem_ack_bits_size; // @[mshrs.scala:402:7] wire [1:0] io_mem_ack_bits_source_0 = io_mem_ack_bits_source; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_sink_0 = io_mem_ack_bits_sink; // @[mshrs.scala:402:7] wire io_mem_ack_bits_denied_0 = io_mem_ack_bits_denied; // @[mshrs.scala:402:7] wire [63:0] io_mem_ack_bits_data_0 = io_mem_ack_bits_data; // @[mshrs.scala:402:7] wire io_mem_ack_bits_corrupt_0 = io_mem_ack_bits_corrupt; // @[mshrs.scala:402:7] wire io_mem_access_bits_corrupt = 1'h0; // @[mshrs.scala:402:7] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire _put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire _atomics_WIRE_corrupt = 1'h0; // @[mshrs.scala:439:46] wire _atomics_legal_T_46 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_52 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_100 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_106 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_154 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_160 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_208 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_214 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_262 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_268 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_316 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_322 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_370 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_376 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_424 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_430 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_478 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_484 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_T_1_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_3_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_5_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_7_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_9_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_11_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_13_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_15_corrupt = 1'h0; // @[mshrs.scala:439:75] wire atomics_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_42_corrupt = 1'h0; // @[mshrs.scala:457:66] wire _io_mem_access_bits_T_43_corrupt = 1'h0; // @[mshrs.scala:457:29] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire [6:0] grant_word_shift = 7'h0; // @[mshrs.scala:417:20] wire [1:0] get_source = 2'h3; // @[Edges.scala:460:17] wire [1:0] put_source = 2'h3; // @[Edges.scala:480:17] wire [1:0] atomics_a_source = 2'h3; // @[Edges.scala:534:17] wire [1:0] atomics_a_1_source = 2'h3; // @[Edges.scala:534:17] wire [1:0] atomics_a_2_source = 2'h3; // @[Edges.scala:534:17] wire [1:0] atomics_a_3_source = 2'h3; // @[Edges.scala:534:17] wire [1:0] atomics_a_4_source = 2'h3; // @[Edges.scala:517:17] wire [1:0] atomics_a_5_source = 2'h3; // @[Edges.scala:517:17] wire [1:0] atomics_a_6_source = 2'h3; // @[Edges.scala:517:17] wire [1:0] atomics_a_7_source = 2'h3; // @[Edges.scala:517:17] wire [1:0] atomics_a_8_source = 2'h3; // @[Edges.scala:517:17] wire [1:0] _io_mem_access_bits_T_42_source = 2'h3; // @[mshrs.scala:457:66] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[mshrs.scala:439:46] wire [2:0] _atomics_WIRE_param = 3'h0; // @[mshrs.scala:439:46] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_param = 3'h0; // @[mshrs.scala:457:66] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_54 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_55 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_56 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_57 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_108 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_109 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_110 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_111 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_163 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_164 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_165 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_216 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_217 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_270 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_271 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_272 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_273 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_324 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_325 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_326 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_327 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_378 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_379 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_380 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_381 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_432 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_433 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_434 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_435 = 1'h1; // @[Parameters.scala:684:29] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17] wire [63:0] _atomics_WIRE_data = 64'h0; // @[mshrs.scala:439:46] wire [7:0] _atomics_WIRE_mask = 8'h0; // @[mshrs.scala:439:46] wire [31:0] _atomics_WIRE_address = 32'h0; // @[mshrs.scala:439:46] wire [1:0] _atomics_WIRE_source = 2'h0; // @[mshrs.scala:439:46] wire [3:0] _atomics_WIRE_size = 4'h0; // @[mshrs.scala:439:46] wire _io_req_ready_T; // @[mshrs.scala:427:25] wire _io_resp_valid_T_1; // @[mshrs.scala:461:43] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_mem_access_valid_T; // @[mshrs.scala:456:32] wire [2:0] _io_mem_access_bits_T_43_opcode; // @[mshrs.scala:457:29] wire [2:0] _io_mem_access_bits_T_43_param; // @[mshrs.scala:457:29] wire [3:0] _io_mem_access_bits_T_43_size; // @[mshrs.scala:457:29] wire [1:0] _io_mem_access_bits_T_43_source; // @[mshrs.scala:457:29] wire [31:0] _io_mem_access_bits_T_43_address; // @[mshrs.scala:457:29] wire [7:0] _io_mem_access_bits_T_43_mask; // @[mshrs.scala:457:29] wire [63:0] _io_mem_access_bits_T_43_data; // @[mshrs.scala:457:29] wire [63:0] _grant_word_T = io_mem_ack_bits_data_0; // @[mshrs.scala:402:7, :418:10] wire io_req_ready_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:402:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:402:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:402:7] wire [7:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:402:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:402:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:402:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:402:7] wire io_resp_valid_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_opcode_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_param_0; // @[mshrs.scala:402:7] wire [3:0] io_mem_access_bits_size_0; // @[mshrs.scala:402:7] wire [1:0] io_mem_access_bits_source_0; // @[mshrs.scala:402:7] wire [31:0] io_mem_access_bits_address_0; // @[mshrs.scala:402:7] wire [7:0] io_mem_access_bits_mask_0; // @[mshrs.scala:402:7] wire [63:0] io_mem_access_bits_data_0; // @[mshrs.scala:402:7] wire io_mem_access_valid_0; // @[mshrs.scala:402:7] reg [6:0] req_uop_uopc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uopc_0 = req_uop_uopc; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_inst_0 = req_uop_inst; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_inst_0 = req_uop_debug_inst; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_rvc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_rvc_0 = req_uop_is_rvc; // @[mshrs.scala:402:7, :421:16] reg [39:0] req_uop_debug_pc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_pc_0 = req_uop_debug_pc; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_iq_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iq_type_0 = req_uop_iq_type; // @[mshrs.scala:402:7, :421:16] reg [9:0] req_uop_fu_code; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fu_code_0 = req_uop_fu_code; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_br_type_0 = req_uop_ctrl_br_type; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op1_sel_0 = req_uop_ctrl_op1_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op2_sel_0 = req_uop_ctrl_op2_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_imm_sel_0 = req_uop_ctrl_imm_sel; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op_fcn_0 = req_uop_ctrl_op_fcn; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_fcn_dw_0 = req_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_csr_cmd_0 = req_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_load; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_load_0 = req_uop_ctrl_is_load; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_sta; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_sta_0 = req_uop_ctrl_is_sta; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_std; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_std_0 = req_uop_ctrl_is_std; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_iw_state; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_state_0 = req_uop_iw_state; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p1_poisoned_0 = req_uop_iw_p1_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p2_poisoned_0 = req_uop_iw_p2_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_br; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_br_0 = req_uop_is_br; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jalr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jalr_0 = req_uop_is_jalr; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jal; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jal_0 = req_uop_is_jal; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sfb; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sfb_0 = req_uop_is_sfb; // @[mshrs.scala:402:7, :421:16] reg [7:0] req_uop_br_mask; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_mask_0 = req_uop_br_mask; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_br_tag; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_tag_0 = req_uop_br_tag; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ftq_idx_0 = req_uop_ftq_idx; // @[mshrs.scala:402:7, :421:16] reg req_uop_edge_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_edge_inst_0 = req_uop_edge_inst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pc_lob_0 = req_uop_pc_lob; // @[mshrs.scala:402:7, :421:16] reg req_uop_taken; // @[mshrs.scala:421:16] assign io_resp_bits_uop_taken_0 = req_uop_taken; // @[mshrs.scala:402:7, :421:16] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_imm_packed_0 = req_uop_imm_packed; // @[mshrs.scala:402:7, :421:16] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_csr_addr_0 = req_uop_csr_addr; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_rob_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rob_idx_0 = req_uop_rob_idx; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ldq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldq_idx_0 = req_uop_ldq_idx; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_stq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stq_idx_0 = req_uop_stq_idx; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rxq_idx_0 = req_uop_rxq_idx; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pdst_0 = req_uop_pdst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_prs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_0 = req_uop_prs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_prs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_0 = req_uop_prs2; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_prs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_0 = req_uop_prs3; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ppred; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_0 = req_uop_ppred; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs1_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_busy_0 = req_uop_prs1_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs2_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_busy_0 = req_uop_prs2_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs3_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_busy_0 = req_uop_prs3_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_ppred_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_busy_0 = req_uop_ppred_busy; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_stale_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stale_pdst_0 = req_uop_stale_pdst; // @[mshrs.scala:402:7, :421:16] reg req_uop_exception; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exception_0 = req_uop_exception; // @[mshrs.scala:402:7, :421:16] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exc_cause_0 = req_uop_exc_cause; // @[mshrs.scala:402:7, :421:16] reg req_uop_bypassable; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bypassable_0 = req_uop_bypassable; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_cmd_0 = req_uop_mem_cmd; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_mem_size; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_size_0 = req_uop_mem_size; // @[mshrs.scala:402:7, :421:16] wire [1:0] size = req_uop_mem_size; // @[AMOALU.scala:11:18] reg req_uop_mem_signed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_signed_0 = req_uop_mem_signed; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fence; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fence_0 = req_uop_is_fence; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fencei; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fencei_0 = req_uop_is_fencei; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_amo; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_amo_0 = req_uop_is_amo; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_ldq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_ldq_0 = req_uop_uses_ldq; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_stq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_stq_0 = req_uop_uses_stq; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sys_pc2epc_0 = req_uop_is_sys_pc2epc; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_unique; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_unique_0 = req_uop_is_unique; // @[mshrs.scala:402:7, :421:16] reg req_uop_flush_on_commit; // @[mshrs.scala:421:16] assign io_resp_bits_uop_flush_on_commit_0 = req_uop_flush_on_commit; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_is_rs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_is_rs1_0 = req_uop_ldst_is_rs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_ldst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_0 = req_uop_ldst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_0 = req_uop_lrs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_0 = req_uop_lrs2; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs3_0 = req_uop_lrs3; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_val_0 = req_uop_ldst_val; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_dst_rtype_0 = req_uop_dst_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_rtype_0 = req_uop_lrs1_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_rtype_0 = req_uop_lrs2_rtype; // @[mshrs.scala:402:7, :421:16] reg req_uop_frs3_en; // @[mshrs.scala:421:16] assign io_resp_bits_uop_frs3_en_0 = req_uop_frs3_en; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_val_0 = req_uop_fp_val; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_single; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_single_0 = req_uop_fp_single; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_pf_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_pf_if_0 = req_uop_xcpt_pf_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ae_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ae_if_0 = req_uop_xcpt_ae_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ma_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ma_if_0 = req_uop_xcpt_ma_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_debug_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_debug_if_0 = req_uop_bp_debug_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_xcpt_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_xcpt_if_0 = req_uop_bp_xcpt_if; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_fsrc_0 = req_uop_debug_fsrc; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_tsrc_0 = req_uop_debug_tsrc; // @[mshrs.scala:402:7, :421:16] reg [39:0] req_addr; // @[mshrs.scala:421:16] wire [39:0] _get_legal_T_14 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_14 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_4 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_58 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_112 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_166 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_220 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_274 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_328 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_382 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_436 = req_addr; // @[Parameters.scala:137:31] reg [63:0] req_data; // @[mshrs.scala:421:16] wire [63:0] put_data = req_data; // @[Edges.scala:480:17] wire [63:0] atomics_a_data = req_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_1_data = req_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_2_data = req_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_3_data = req_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_4_data = req_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_5_data = req_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_6_data = req_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_7_data = req_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_8_data = req_data; // @[Edges.scala:517:17] reg req_is_hella; // @[mshrs.scala:421:16] assign io_resp_bits_is_hella_0 = req_is_hella; // @[mshrs.scala:402:7, :421:16] reg [63:0] grant_word; // @[mshrs.scala:422:23] reg [1:0] state; // @[mshrs.scala:426:22] assign _io_req_ready_T = state == 2'h0; // @[mshrs.scala:426:22, :427:25] assign io_req_ready_0 = _io_req_ready_T; // @[mshrs.scala:402:7, :427:25] wire [39:0] _GEN = {req_addr[39:14], req_addr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_62 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_0 = {req_addr[39:17], req_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_63; // @[Parameters.scala:137:31] assign _put_legal_T_63 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_47; // @[Parameters.scala:137:31] assign _atomics_legal_T_47 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_101; // @[Parameters.scala:137:31] assign _atomics_legal_T_101 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_155; // @[Parameters.scala:137:31] assign _atomics_legal_T_155 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_209; // @[Parameters.scala:137:31] assign _atomics_legal_T_209 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_263; // @[Parameters.scala:137:31] assign _atomics_legal_T_263 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_317; // @[Parameters.scala:137:31] assign _atomics_legal_T_317 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_371; // @[Parameters.scala:137:31] assign _atomics_legal_T_371 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_425; // @[Parameters.scala:137:31] assign _atomics_legal_T_425 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_479; // @[Parameters.scala:137:31] assign _atomics_legal_T_479 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {req_addr[39:26], req_addr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {req_addr[39:28], req_addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31] assign _put_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31] assign _atomics_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31] assign _atomics_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31] assign _atomics_legal_T_73 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31] assign _atomics_legal_T_78 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31] assign _atomics_legal_T_127 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31] assign _atomics_legal_T_132 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_181; // @[Parameters.scala:137:31] assign _atomics_legal_T_181 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31] assign _atomics_legal_T_186 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_235; // @[Parameters.scala:137:31] assign _atomics_legal_T_235 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_240; // @[Parameters.scala:137:31] assign _atomics_legal_T_240 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_289; // @[Parameters.scala:137:31] assign _atomics_legal_T_289 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_294; // @[Parameters.scala:137:31] assign _atomics_legal_T_294 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_343; // @[Parameters.scala:137:31] assign _atomics_legal_T_343 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_348; // @[Parameters.scala:137:31] assign _atomics_legal_T_348 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_397; // @[Parameters.scala:137:31] assign _atomics_legal_T_397 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_402; // @[Parameters.scala:137:31] assign _atomics_legal_T_402 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_451; // @[Parameters.scala:137:31] assign _atomics_legal_T_451 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_456; // @[Parameters.scala:137:31] assign _atomics_legal_T_456 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {req_addr[39:29], req_addr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31] assign _get_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31] assign _put_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_29; // @[Parameters.scala:137:31] assign _atomics_legal_T_29 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31] assign _atomics_legal_T_137 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31] assign _atomics_legal_T_191 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31] assign _atomics_legal_T_245 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_299; // @[Parameters.scala:137:31] assign _atomics_legal_T_299 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_353; // @[Parameters.scala:137:31] assign _atomics_legal_T_353 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_407; // @[Parameters.scala:137:31] assign _atomics_legal_T_407 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_461; // @[Parameters.scala:137:31] assign _atomics_legal_T_461 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46] wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] get_address = req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] atomics_a_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [39:0] _GEN_4 = {req_addr[39:32], req_addr[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31] assign _get_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31] assign _put_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_34; // @[Parameters.scala:137:31] assign _atomics_legal_T_34 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_88; // @[Parameters.scala:137:31] assign _atomics_legal_T_88 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31] assign _atomics_legal_T_142 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31] assign _atomics_legal_T_196 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31] assign _atomics_legal_T_250 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31] assign _atomics_legal_T_304 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_358; // @[Parameters.scala:137:31] assign _atomics_legal_T_358 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_412; // @[Parameters.scala:137:31] assign _atomics_legal_T_412 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_466; // @[Parameters.scala:137:31] assign _atomics_legal_T_466 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46] wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_54 = _get_legal_T_18 | _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_55 = _get_legal_T_54 | _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_56 = _get_legal_T_55 | _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_57 = _get_legal_T_56 | _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_58 = _get_legal_T_57 | _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_59 = _get_legal_T_58 | _get_legal_T_48; // @[Parameters.scala:685:42] wire _get_legal_T_60 = _get_legal_T_59 | _get_legal_T_53; // @[Parameters.scala:685:42] wire _get_legal_T_61 = _get_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_62 | _get_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [7:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_5 = {2'h0, req_uop_mem_size}; // @[Edges.scala:463:15] assign get_size = _GEN_5; // @[Edges.scala:460:17, :463:15] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_5; // @[Edges.scala:463:15, :480:17] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [2:0] _GEN_6 = {1'h0, req_uop_mem_size}; // @[Misc.scala:202:34] wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_6; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_6; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = req_addr[2]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T = req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = req_addr[1]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_3 = req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = req_addr[0]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_6 = req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 | _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_69 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_7 = {req_addr[39:21], req_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_63; // @[Parameters.scala:137:31] assign _atomics_legal_T_63 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_117; // @[Parameters.scala:137:31] assign _atomics_legal_T_117 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_171; // @[Parameters.scala:137:31] assign _atomics_legal_T_171 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_225; // @[Parameters.scala:137:31] assign _atomics_legal_T_225 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_279; // @[Parameters.scala:137:31] assign _atomics_legal_T_279 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_333; // @[Parameters.scala:137:31] assign _atomics_legal_T_333 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_387; // @[Parameters.scala:137:31] assign _atomics_legal_T_387 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_441; // @[Parameters.scala:137:31] assign _atomics_legal_T_441 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_8 = {req_addr[39:26], req_addr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31] assign _atomics_legal_T_68 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_122; // @[Parameters.scala:137:31] assign _atomics_legal_T_122 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_176; // @[Parameters.scala:137:31] assign _atomics_legal_T_176 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_230; // @[Parameters.scala:137:31] assign _atomics_legal_T_230 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_284; // @[Parameters.scala:137:31] assign _atomics_legal_T_284 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_338; // @[Parameters.scala:137:31] assign _atomics_legal_T_338 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_392; // @[Parameters.scala:137:31] assign _atomics_legal_T_392 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_446; // @[Parameters.scala:137:31] assign _atomics_legal_T_446 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46] wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46] wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46] wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_54 = _put_legal_T_18 | _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_55 = _put_legal_T_54 | _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_56 = _put_legal_T_55 | _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_57 = _put_legal_T_56 | _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_58 = _put_legal_T_57 | _put_legal_T_43; // @[Parameters.scala:685:42] wire _put_legal_T_59 = _put_legal_T_58 | _put_legal_T_48; // @[Parameters.scala:685:42] wire _put_legal_T_60 = _put_legal_T_59 | _put_legal_T_53; // @[Parameters.scala:685:42] wire _put_legal_T_61 = _put_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _put_legal_T_64 = {1'h0, _put_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_65 = _put_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_66 = _put_legal_T_65; // @[Parameters.scala:137:46] wire _put_legal_T_67 = _put_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_70 = _put_legal_T_69 | _put_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_70; // @[Parameters.scala:686:26] wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [7:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 | _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 | _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46] wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46] wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_30 = {1'h0, _atomics_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_31 = _atomics_legal_T_30 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_32 = _atomics_legal_T_31; // @[Parameters.scala:137:46] wire _atomics_legal_T_33 = _atomics_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_36 = _atomics_legal_T_35 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36; // @[Parameters.scala:137:46] wire _atomics_legal_T_38 = _atomics_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_39 = _atomics_legal_T_8 | _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_40 = _atomics_legal_T_39 | _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_41 = _atomics_legal_T_40 | _atomics_legal_T_23; // @[Parameters.scala:685:42] wire _atomics_legal_T_42 = _atomics_legal_T_41 | _atomics_legal_T_28; // @[Parameters.scala:685:42] wire _atomics_legal_T_43 = _atomics_legal_T_42 | _atomics_legal_T_33; // @[Parameters.scala:685:42] wire _atomics_legal_T_44 = _atomics_legal_T_43 | _atomics_legal_T_38; // @[Parameters.scala:685:42] wire _atomics_legal_T_45 = _atomics_legal_T_44; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_53 = _atomics_legal_T_45; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_48 = {1'h0, _atomics_legal_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_49 = _atomics_legal_T_48 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_50 = _atomics_legal_T_49; // @[Parameters.scala:137:46] wire _atomics_legal_T_51 = _atomics_legal_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal = _atomics_legal_T_53; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_59 = {1'h0, _atomics_legal_T_58}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_60 = _atomics_legal_T_59 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_61 = _atomics_legal_T_60; // @[Parameters.scala:137:46] wire _atomics_legal_T_62 = _atomics_legal_T_61 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46] wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46] wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46] wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46] wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_89 = {1'h0, _atomics_legal_T_88}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_90 = _atomics_legal_T_89 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_91 = _atomics_legal_T_90; // @[Parameters.scala:137:46] wire _atomics_legal_T_92 = _atomics_legal_T_91 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_93 = _atomics_legal_T_62 | _atomics_legal_T_67; // @[Parameters.scala:685:42] wire _atomics_legal_T_94 = _atomics_legal_T_93 | _atomics_legal_T_72; // @[Parameters.scala:685:42] wire _atomics_legal_T_95 = _atomics_legal_T_94 | _atomics_legal_T_77; // @[Parameters.scala:685:42] wire _atomics_legal_T_96 = _atomics_legal_T_95 | _atomics_legal_T_82; // @[Parameters.scala:685:42] wire _atomics_legal_T_97 = _atomics_legal_T_96 | _atomics_legal_T_87; // @[Parameters.scala:685:42] wire _atomics_legal_T_98 = _atomics_legal_T_97 | _atomics_legal_T_92; // @[Parameters.scala:685:42] wire _atomics_legal_T_99 = _atomics_legal_T_98; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_107 = _atomics_legal_T_99; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_102 = {1'h0, _atomics_legal_T_101}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_103 = _atomics_legal_T_102 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_104 = _atomics_legal_T_103; // @[Parameters.scala:137:46] wire _atomics_legal_T_105 = _atomics_legal_T_104 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_1 = _atomics_legal_T_107; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_1 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_113 = {1'h0, _atomics_legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_114 = _atomics_legal_T_113 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:137:46] wire _atomics_legal_T_116 = _atomics_legal_T_115 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_118 = {1'h0, _atomics_legal_T_117}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_119 = _atomics_legal_T_118 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_120 = _atomics_legal_T_119; // @[Parameters.scala:137:46] wire _atomics_legal_T_121 = _atomics_legal_T_120 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46] wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46] wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46] wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46] wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46] wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_147 = _atomics_legal_T_116 | _atomics_legal_T_121; // @[Parameters.scala:685:42] wire _atomics_legal_T_148 = _atomics_legal_T_147 | _atomics_legal_T_126; // @[Parameters.scala:685:42] wire _atomics_legal_T_149 = _atomics_legal_T_148 | _atomics_legal_T_131; // @[Parameters.scala:685:42] wire _atomics_legal_T_150 = _atomics_legal_T_149 | _atomics_legal_T_136; // @[Parameters.scala:685:42] wire _atomics_legal_T_151 = _atomics_legal_T_150 | _atomics_legal_T_141; // @[Parameters.scala:685:42] wire _atomics_legal_T_152 = _atomics_legal_T_151 | _atomics_legal_T_146; // @[Parameters.scala:685:42] wire _atomics_legal_T_153 = _atomics_legal_T_152; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_161 = _atomics_legal_T_153; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_156 = {1'h0, _atomics_legal_T_155}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_157 = _atomics_legal_T_156 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_158 = _atomics_legal_T_157; // @[Parameters.scala:137:46] wire _atomics_legal_T_159 = _atomics_legal_T_158 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_2 = _atomics_legal_T_161; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_2 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_167 = {1'h0, _atomics_legal_T_166}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_168 = _atomics_legal_T_167 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_169 = _atomics_legal_T_168; // @[Parameters.scala:137:46] wire _atomics_legal_T_170 = _atomics_legal_T_169 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_172 = {1'h0, _atomics_legal_T_171}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_173 = _atomics_legal_T_172 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:137:46] wire _atomics_legal_T_175 = _atomics_legal_T_174 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_177 = {1'h0, _atomics_legal_T_176}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_178 = _atomics_legal_T_177 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_179 = _atomics_legal_T_178; // @[Parameters.scala:137:46] wire _atomics_legal_T_180 = _atomics_legal_T_179 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46] wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46] wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46] wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46] wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_201 = _atomics_legal_T_170 | _atomics_legal_T_175; // @[Parameters.scala:685:42] wire _atomics_legal_T_202 = _atomics_legal_T_201 | _atomics_legal_T_180; // @[Parameters.scala:685:42] wire _atomics_legal_T_203 = _atomics_legal_T_202 | _atomics_legal_T_185; // @[Parameters.scala:685:42] wire _atomics_legal_T_204 = _atomics_legal_T_203 | _atomics_legal_T_190; // @[Parameters.scala:685:42] wire _atomics_legal_T_205 = _atomics_legal_T_204 | _atomics_legal_T_195; // @[Parameters.scala:685:42] wire _atomics_legal_T_206 = _atomics_legal_T_205 | _atomics_legal_T_200; // @[Parameters.scala:685:42] wire _atomics_legal_T_207 = _atomics_legal_T_206; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_215 = _atomics_legal_T_207; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_210 = {1'h0, _atomics_legal_T_209}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_211 = _atomics_legal_T_210 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_212 = _atomics_legal_T_211; // @[Parameters.scala:137:46] wire _atomics_legal_T_213 = _atomics_legal_T_212 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_3 = _atomics_legal_T_215; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_3 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_221 = {1'h0, _atomics_legal_T_220}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_222 = _atomics_legal_T_221 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_223 = _atomics_legal_T_222; // @[Parameters.scala:137:46] wire _atomics_legal_T_224 = _atomics_legal_T_223 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_226 = {1'h0, _atomics_legal_T_225}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_227 = _atomics_legal_T_226 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_228 = _atomics_legal_T_227; // @[Parameters.scala:137:46] wire _atomics_legal_T_229 = _atomics_legal_T_228 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_231 = {1'h0, _atomics_legal_T_230}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_232 = _atomics_legal_T_231 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:137:46] wire _atomics_legal_T_234 = _atomics_legal_T_233 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_236 = {1'h0, _atomics_legal_T_235}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_237 = _atomics_legal_T_236 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_238 = _atomics_legal_T_237; // @[Parameters.scala:137:46] wire _atomics_legal_T_239 = _atomics_legal_T_238 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46] wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46] wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46] wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_255 = _atomics_legal_T_224 | _atomics_legal_T_229; // @[Parameters.scala:685:42] wire _atomics_legal_T_256 = _atomics_legal_T_255 | _atomics_legal_T_234; // @[Parameters.scala:685:42] wire _atomics_legal_T_257 = _atomics_legal_T_256 | _atomics_legal_T_239; // @[Parameters.scala:685:42] wire _atomics_legal_T_258 = _atomics_legal_T_257 | _atomics_legal_T_244; // @[Parameters.scala:685:42] wire _atomics_legal_T_259 = _atomics_legal_T_258 | _atomics_legal_T_249; // @[Parameters.scala:685:42] wire _atomics_legal_T_260 = _atomics_legal_T_259 | _atomics_legal_T_254; // @[Parameters.scala:685:42] wire _atomics_legal_T_261 = _atomics_legal_T_260; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_269 = _atomics_legal_T_261; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_264 = {1'h0, _atomics_legal_T_263}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_265 = _atomics_legal_T_264 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_266 = _atomics_legal_T_265; // @[Parameters.scala:137:46] wire _atomics_legal_T_267 = _atomics_legal_T_266 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_4 = _atomics_legal_T_269; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_4 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_275 = {1'h0, _atomics_legal_T_274}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_276 = _atomics_legal_T_275 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_277 = _atomics_legal_T_276; // @[Parameters.scala:137:46] wire _atomics_legal_T_278 = _atomics_legal_T_277 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_280 = {1'h0, _atomics_legal_T_279}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_281 = _atomics_legal_T_280 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_282 = _atomics_legal_T_281; // @[Parameters.scala:137:46] wire _atomics_legal_T_283 = _atomics_legal_T_282 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_285 = {1'h0, _atomics_legal_T_284}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_286 = _atomics_legal_T_285 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_287 = _atomics_legal_T_286; // @[Parameters.scala:137:46] wire _atomics_legal_T_288 = _atomics_legal_T_287 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_290 = {1'h0, _atomics_legal_T_289}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_291 = _atomics_legal_T_290 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:137:46] wire _atomics_legal_T_293 = _atomics_legal_T_292 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_295 = {1'h0, _atomics_legal_T_294}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_296 = _atomics_legal_T_295 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_297 = _atomics_legal_T_296; // @[Parameters.scala:137:46] wire _atomics_legal_T_298 = _atomics_legal_T_297 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46] wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46] wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_309 = _atomics_legal_T_278 | _atomics_legal_T_283; // @[Parameters.scala:685:42] wire _atomics_legal_T_310 = _atomics_legal_T_309 | _atomics_legal_T_288; // @[Parameters.scala:685:42] wire _atomics_legal_T_311 = _atomics_legal_T_310 | _atomics_legal_T_293; // @[Parameters.scala:685:42] wire _atomics_legal_T_312 = _atomics_legal_T_311 | _atomics_legal_T_298; // @[Parameters.scala:685:42] wire _atomics_legal_T_313 = _atomics_legal_T_312 | _atomics_legal_T_303; // @[Parameters.scala:685:42] wire _atomics_legal_T_314 = _atomics_legal_T_313 | _atomics_legal_T_308; // @[Parameters.scala:685:42] wire _atomics_legal_T_315 = _atomics_legal_T_314; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_323 = _atomics_legal_T_315; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_318 = {1'h0, _atomics_legal_T_317}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_319 = _atomics_legal_T_318 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_320 = _atomics_legal_T_319; // @[Parameters.scala:137:46] wire _atomics_legal_T_321 = _atomics_legal_T_320 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_5 = _atomics_legal_T_323; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_5 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_329 = {1'h0, _atomics_legal_T_328}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_330 = _atomics_legal_T_329 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_331 = _atomics_legal_T_330; // @[Parameters.scala:137:46] wire _atomics_legal_T_332 = _atomics_legal_T_331 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_334 = {1'h0, _atomics_legal_T_333}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_335 = _atomics_legal_T_334 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_336 = _atomics_legal_T_335; // @[Parameters.scala:137:46] wire _atomics_legal_T_337 = _atomics_legal_T_336 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_339 = {1'h0, _atomics_legal_T_338}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_340 = _atomics_legal_T_339 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_341 = _atomics_legal_T_340; // @[Parameters.scala:137:46] wire _atomics_legal_T_342 = _atomics_legal_T_341 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_344 = {1'h0, _atomics_legal_T_343}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_345 = _atomics_legal_T_344 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_346 = _atomics_legal_T_345; // @[Parameters.scala:137:46] wire _atomics_legal_T_347 = _atomics_legal_T_346 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_349 = {1'h0, _atomics_legal_T_348}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_350 = _atomics_legal_T_349 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:137:46] wire _atomics_legal_T_352 = _atomics_legal_T_351 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_354 = {1'h0, _atomics_legal_T_353}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_355 = _atomics_legal_T_354 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_356 = _atomics_legal_T_355; // @[Parameters.scala:137:46] wire _atomics_legal_T_357 = _atomics_legal_T_356 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46] wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_363 = _atomics_legal_T_332 | _atomics_legal_T_337; // @[Parameters.scala:685:42] wire _atomics_legal_T_364 = _atomics_legal_T_363 | _atomics_legal_T_342; // @[Parameters.scala:685:42] wire _atomics_legal_T_365 = _atomics_legal_T_364 | _atomics_legal_T_347; // @[Parameters.scala:685:42] wire _atomics_legal_T_366 = _atomics_legal_T_365 | _atomics_legal_T_352; // @[Parameters.scala:685:42] wire _atomics_legal_T_367 = _atomics_legal_T_366 | _atomics_legal_T_357; // @[Parameters.scala:685:42] wire _atomics_legal_T_368 = _atomics_legal_T_367 | _atomics_legal_T_362; // @[Parameters.scala:685:42] wire _atomics_legal_T_369 = _atomics_legal_T_368; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_377 = _atomics_legal_T_369; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_372 = {1'h0, _atomics_legal_T_371}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_373 = _atomics_legal_T_372 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_374 = _atomics_legal_T_373; // @[Parameters.scala:137:46] wire _atomics_legal_T_375 = _atomics_legal_T_374 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_6 = _atomics_legal_T_377; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_6 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_383 = {1'h0, _atomics_legal_T_382}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_384 = _atomics_legal_T_383 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_385 = _atomics_legal_T_384; // @[Parameters.scala:137:46] wire _atomics_legal_T_386 = _atomics_legal_T_385 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_388 = {1'h0, _atomics_legal_T_387}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_389 = _atomics_legal_T_388 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_390 = _atomics_legal_T_389; // @[Parameters.scala:137:46] wire _atomics_legal_T_391 = _atomics_legal_T_390 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_393 = {1'h0, _atomics_legal_T_392}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_394 = _atomics_legal_T_393 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_395 = _atomics_legal_T_394; // @[Parameters.scala:137:46] wire _atomics_legal_T_396 = _atomics_legal_T_395 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_398 = {1'h0, _atomics_legal_T_397}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_399 = _atomics_legal_T_398 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_400 = _atomics_legal_T_399; // @[Parameters.scala:137:46] wire _atomics_legal_T_401 = _atomics_legal_T_400 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_403 = {1'h0, _atomics_legal_T_402}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_404 = _atomics_legal_T_403 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_405 = _atomics_legal_T_404; // @[Parameters.scala:137:46] wire _atomics_legal_T_406 = _atomics_legal_T_405 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_408 = {1'h0, _atomics_legal_T_407}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_409 = _atomics_legal_T_408 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:137:46] wire _atomics_legal_T_411 = _atomics_legal_T_410 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_413 = {1'h0, _atomics_legal_T_412}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_414 = _atomics_legal_T_413 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_415 = _atomics_legal_T_414; // @[Parameters.scala:137:46] wire _atomics_legal_T_416 = _atomics_legal_T_415 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_417 = _atomics_legal_T_386 | _atomics_legal_T_391; // @[Parameters.scala:685:42] wire _atomics_legal_T_418 = _atomics_legal_T_417 | _atomics_legal_T_396; // @[Parameters.scala:685:42] wire _atomics_legal_T_419 = _atomics_legal_T_418 | _atomics_legal_T_401; // @[Parameters.scala:685:42] wire _atomics_legal_T_420 = _atomics_legal_T_419 | _atomics_legal_T_406; // @[Parameters.scala:685:42] wire _atomics_legal_T_421 = _atomics_legal_T_420 | _atomics_legal_T_411; // @[Parameters.scala:685:42] wire _atomics_legal_T_422 = _atomics_legal_T_421 | _atomics_legal_T_416; // @[Parameters.scala:685:42] wire _atomics_legal_T_423 = _atomics_legal_T_422; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_431 = _atomics_legal_T_423; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_426 = {1'h0, _atomics_legal_T_425}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_427 = _atomics_legal_T_426 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_428 = _atomics_legal_T_427; // @[Parameters.scala:137:46] wire _atomics_legal_T_429 = _atomics_legal_T_428 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_7 = _atomics_legal_T_431; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_7 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_437 = {1'h0, _atomics_legal_T_436}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_438 = _atomics_legal_T_437 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438; // @[Parameters.scala:137:46] wire _atomics_legal_T_440 = _atomics_legal_T_439 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_442 = {1'h0, _atomics_legal_T_441}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_443 = _atomics_legal_T_442 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_444 = _atomics_legal_T_443; // @[Parameters.scala:137:46] wire _atomics_legal_T_445 = _atomics_legal_T_444 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_447 = {1'h0, _atomics_legal_T_446}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_448 = _atomics_legal_T_447 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_449 = _atomics_legal_T_448; // @[Parameters.scala:137:46] wire _atomics_legal_T_450 = _atomics_legal_T_449 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_452 = {1'h0, _atomics_legal_T_451}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_453 = _atomics_legal_T_452 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_454 = _atomics_legal_T_453; // @[Parameters.scala:137:46] wire _atomics_legal_T_455 = _atomics_legal_T_454 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_457 = {1'h0, _atomics_legal_T_456}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_458 = _atomics_legal_T_457 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_459 = _atomics_legal_T_458; // @[Parameters.scala:137:46] wire _atomics_legal_T_460 = _atomics_legal_T_459 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_462 = {1'h0, _atomics_legal_T_461}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_463 = _atomics_legal_T_462 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_464 = _atomics_legal_T_463; // @[Parameters.scala:137:46] wire _atomics_legal_T_465 = _atomics_legal_T_464 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_467 = {1'h0, _atomics_legal_T_466}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_468 = _atomics_legal_T_467 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:137:46] wire _atomics_legal_T_470 = _atomics_legal_T_469 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_471 = _atomics_legal_T_440 | _atomics_legal_T_445; // @[Parameters.scala:685:42] wire _atomics_legal_T_472 = _atomics_legal_T_471 | _atomics_legal_T_450; // @[Parameters.scala:685:42] wire _atomics_legal_T_473 = _atomics_legal_T_472 | _atomics_legal_T_455; // @[Parameters.scala:685:42] wire _atomics_legal_T_474 = _atomics_legal_T_473 | _atomics_legal_T_460; // @[Parameters.scala:685:42] wire _atomics_legal_T_475 = _atomics_legal_T_474 | _atomics_legal_T_465; // @[Parameters.scala:685:42] wire _atomics_legal_T_476 = _atomics_legal_T_475 | _atomics_legal_T_470; // @[Parameters.scala:685:42] wire _atomics_legal_T_477 = _atomics_legal_T_476; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_485 = _atomics_legal_T_477; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_480 = {1'h0, _atomics_legal_T_479}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_481 = _atomics_legal_T_480 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_482 = _atomics_legal_T_481; // @[Parameters.scala:137:46] wire _atomics_legal_T_483 = _atomics_legal_T_482 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_8 = _atomics_legal_T_485; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_8 = &req_uop_mem_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire _T_17 = req_uop_mem_cmd == 5'h4; // @[mshrs.scala:421:16, :439:75] wire _atomics_T; // @[mshrs.scala:439:75] assign _atomics_T = _T_17; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T; // @[package.scala:16:47] assign _io_mem_access_bits_T = _T_17; // @[package.scala:16:47] wire _io_mem_access_bits_T_24; // @[package.scala:16:47] assign _io_mem_access_bits_T_24 = _T_17; // @[package.scala:16:47] wire _send_resp_T_7; // @[package.scala:16:47] assign _send_resp_T_7 = _T_17; // @[package.scala:16:47] wire [2:0] _GEN_9 = _atomics_T ? 3'h3 : 3'h0; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_opcode; // @[mshrs.scala:439:75] assign _atomics_T_1_opcode = _GEN_9; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_param; // @[mshrs.scala:439:75] assign _atomics_T_1_param = _GEN_9; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire [1:0] _atomics_T_1_source = {2{_atomics_T}}; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[Edges.scala:534:17] wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[Edges.scala:534:17] wire _T_18 = req_uop_mem_cmd == 5'h9; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_2; // @[mshrs.scala:439:75] assign _atomics_T_2 = _T_18; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_1; // @[package.scala:16:47] assign _io_mem_access_bits_T_1 = _T_18; // @[package.scala:16:47] wire _io_mem_access_bits_T_25; // @[package.scala:16:47] assign _io_mem_access_bits_T_25 = _T_18; // @[package.scala:16:47] wire _send_resp_T_8; // @[package.scala:16:47] assign _send_resp_T_8 = _T_18; // @[package.scala:16:47] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire [1:0] _atomics_T_3_source = _atomics_T_2 ? 2'h3 : _atomics_T_1_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire _T_19 = req_uop_mem_cmd == 5'hA; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_4; // @[mshrs.scala:439:75] assign _atomics_T_4 = _T_19; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_2; // @[package.scala:16:47] assign _io_mem_access_bits_T_2 = _T_19; // @[package.scala:16:47] wire _io_mem_access_bits_T_26; // @[package.scala:16:47] assign _io_mem_access_bits_T_26 = _T_19; // @[package.scala:16:47] wire _send_resp_T_9; // @[package.scala:16:47] assign _send_resp_T_9 = _T_19; // @[package.scala:16:47] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire [1:0] _atomics_T_5_source = _atomics_T_4 ? 2'h3 : _atomics_T_3_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire _T_20 = req_uop_mem_cmd == 5'hB; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_6; // @[mshrs.scala:439:75] assign _atomics_T_6 = _T_20; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_3; // @[package.scala:16:47] assign _io_mem_access_bits_T_3 = _T_20; // @[package.scala:16:47] wire _io_mem_access_bits_T_27; // @[package.scala:16:47] assign _io_mem_access_bits_T_27 = _T_20; // @[package.scala:16:47] wire _send_resp_T_10; // @[package.scala:16:47] assign _send_resp_T_10 = _T_20; // @[package.scala:16:47] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire [1:0] _atomics_T_7_source = _atomics_T_6 ? 2'h3 : _atomics_T_5_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire _T_24 = req_uop_mem_cmd == 5'h8; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_8; // @[mshrs.scala:439:75] assign _atomics_T_8 = _T_24; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_7; // @[package.scala:16:47] assign _io_mem_access_bits_T_7 = _T_24; // @[package.scala:16:47] wire _io_mem_access_bits_T_31; // @[package.scala:16:47] assign _io_mem_access_bits_T_31 = _T_24; // @[package.scala:16:47] wire _send_resp_T_14; // @[package.scala:16:47] assign _send_resp_T_14 = _T_24; // @[package.scala:16:47] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire [1:0] _atomics_T_9_source = _atomics_T_8 ? 2'h3 : _atomics_T_7_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire _T_25 = req_uop_mem_cmd == 5'hC; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_10; // @[mshrs.scala:439:75] assign _atomics_T_10 = _T_25; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_8; // @[package.scala:16:47] assign _io_mem_access_bits_T_8 = _T_25; // @[package.scala:16:47] wire _io_mem_access_bits_T_32; // @[package.scala:16:47] assign _io_mem_access_bits_T_32 = _T_25; // @[package.scala:16:47] wire _send_resp_T_15; // @[package.scala:16:47] assign _send_resp_T_15 = _T_25; // @[package.scala:16:47] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire [1:0] _atomics_T_11_source = _atomics_T_10 ? 2'h3 : _atomics_T_9_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire _T_26 = req_uop_mem_cmd == 5'hD; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_12; // @[mshrs.scala:439:75] assign _atomics_T_12 = _T_26; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_9; // @[package.scala:16:47] assign _io_mem_access_bits_T_9 = _T_26; // @[package.scala:16:47] wire _io_mem_access_bits_T_33; // @[package.scala:16:47] assign _io_mem_access_bits_T_33 = _T_26; // @[package.scala:16:47] wire _send_resp_T_16; // @[package.scala:16:47] assign _send_resp_T_16 = _T_26; // @[package.scala:16:47] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire [1:0] _atomics_T_13_source = _atomics_T_12 ? 2'h3 : _atomics_T_11_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire _T_27 = req_uop_mem_cmd == 5'hE; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_14; // @[mshrs.scala:439:75] assign _atomics_T_14 = _T_27; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_10; // @[package.scala:16:47] assign _io_mem_access_bits_T_10 = _T_27; // @[package.scala:16:47] wire _io_mem_access_bits_T_34; // @[package.scala:16:47] assign _io_mem_access_bits_T_34 = _T_27; // @[package.scala:16:47] wire _send_resp_T_17; // @[package.scala:16:47] assign _send_resp_T_17 = _T_27; // @[package.scala:16:47] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire [1:0] _atomics_T_15_source = _atomics_T_14 ? 2'h3 : _atomics_T_13_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire _T_28 = req_uop_mem_cmd == 5'hF; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_16; // @[mshrs.scala:439:75] assign _atomics_T_16 = _T_28; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_11; // @[package.scala:16:47] assign _io_mem_access_bits_T_11 = _T_28; // @[package.scala:16:47] wire _io_mem_access_bits_T_35; // @[package.scala:16:47] assign _io_mem_access_bits_T_35 = _T_28; // @[package.scala:16:47] wire _send_resp_T_18; // @[package.scala:16:47] assign _send_resp_T_18 = _T_28; // @[package.scala:16:47] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[mshrs.scala:439:75] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[mshrs.scala:439:75] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire [1:0] atomics_source = _atomics_T_16 ? 2'h3 : _atomics_T_15_source; // @[mshrs.scala:439:75] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_15 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_15 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_15 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_27 connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags
module MulAddRecFN_e8_s24_15( // @[MulAddRecFN.scala:300:7] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = 48'h0; // @[MulAddRecFN.scala:327:45] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_a = 33'h115800000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [48:0] mulAddResult = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_15 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_15 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_27 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_25 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_25( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCacheBankScheduler : input clock : Clock input reset : Reset output io : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip ways : UInt<8>[8], flip divs : UInt<11>[8], flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { address : UInt<32>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}}} inst sourceA of SourceA connect sourceA.clock, clock connect sourceA.reset, reset inst sourceB of SourceB connect sourceB.clock, clock connect sourceB.reset, reset inst sourceC of SourceC connect sourceC.clock, clock connect sourceC.reset, reset inst sourceD of SourceD connect sourceD.clock, clock connect sourceD.reset, reset inst sourceE of SourceE connect sourceE.clock, clock connect sourceE.reset, reset inst sourceX of SourceX connect sourceX.clock, clock connect sourceX.reset, reset connect io.out.a.bits, sourceA.io.a.bits connect io.out.a.valid, sourceA.io.a.valid connect sourceA.io.a.ready, io.out.a.ready connect io.out.c.bits, sourceC.io.c.bits connect io.out.c.valid, sourceC.io.c.valid connect sourceC.io.c.ready, io.out.c.ready connect io.out.e.bits, sourceE.io.e.bits connect io.out.e.valid, sourceE.io.e.valid connect sourceE.io.e.ready, io.out.e.ready connect io.in.b.bits, sourceB.io.b.bits connect io.in.b.valid, sourceB.io.b.valid connect sourceB.io.b.ready, io.in.b.ready connect io.in.d.bits, sourceD.io.d.bits connect io.in.d.valid, sourceD.io.d.valid connect sourceD.io.d.ready, io.in.d.ready connect io.resp.bits, sourceX.io.x.bits connect io.resp.valid, sourceX.io.x.valid connect sourceX.io.x.ready, io.resp.ready inst sinkA of SinkA connect sinkA.clock, clock connect sinkA.reset, reset inst sinkC of SinkC connect sinkC.clock, clock connect sinkC.reset, reset inst sinkD of SinkD connect sinkD.clock, clock connect sinkD.reset, reset inst sinkE of SinkE connect sinkE.clock, clock connect sinkE.reset, reset inst sinkX of SinkX connect sinkX.clock, clock connect sinkX.reset, reset connect sinkA.io.a, io.in.a connect sinkC.io.c, io.in.c connect sinkE.io.e, io.in.e connect sinkD.io.d, io.out.d connect sinkX.io.x, io.req connect io.out.b.ready, UInt<1>(0h1) inst directory of Directory connect directory.clock, clock connect directory.reset, reset inst bankedStore of BankedStore connect bankedStore.clock, clock connect bankedStore.reset, reset inst requests of ListBuffer_QueuedRequest_q21_e33 connect requests.clock, clock connect requests.reset, reset inst mshrs_0 of MSHR connect mshrs_0.clock, clock connect mshrs_0.reset, reset inst mshrs_1 of MSHR_1 connect mshrs_1.clock, clock connect mshrs_1.reset, reset inst mshrs_2 of MSHR_2 connect mshrs_2.clock, clock connect mshrs_2.reset, reset inst mshrs_3 of MSHR_3 connect mshrs_3.clock, clock connect mshrs_3.reset, reset inst mshrs_4 of MSHR_4 connect mshrs_4.clock, clock connect mshrs_4.reset, reset inst mshrs_5 of MSHR_5 connect mshrs_5.clock, clock connect mshrs_5.reset, reset inst mshrs_6 of MSHR_6 connect mshrs_6.clock, clock connect mshrs_6.reset, reset wire nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>} node _mshrs_0_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_0.io.status.bits.set) node _mshrs_0_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_0_io_sinkc_valid_T) connect mshrs_0.io.sinkc.valid, _mshrs_0_io_sinkc_valid_T_1 node _mshrs_0_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h0)) node _mshrs_0_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_0_io_sinkd_valid_T) connect mshrs_0.io.sinkd.valid, _mshrs_0_io_sinkd_valid_T_1 node _mshrs_0_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h0)) node _mshrs_0_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_0_io_sinke_valid_T) connect mshrs_0.io.sinke.valid, _mshrs_0_io_sinke_valid_T_1 connect mshrs_0.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_0.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_0.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_0.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_0.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_0.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_0.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_0.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_0.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_0.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_0.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_0.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_0.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_0.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_0.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_0.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_0.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_0.io.nestedwb.tag, nestedwb.tag connect mshrs_0.io.nestedwb.set, nestedwb.set node _mshrs_1_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_1.io.status.bits.set) node _mshrs_1_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_1_io_sinkc_valid_T) connect mshrs_1.io.sinkc.valid, _mshrs_1_io_sinkc_valid_T_1 node _mshrs_1_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h1)) node _mshrs_1_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_1_io_sinkd_valid_T) connect mshrs_1.io.sinkd.valid, _mshrs_1_io_sinkd_valid_T_1 node _mshrs_1_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h1)) node _mshrs_1_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_1_io_sinke_valid_T) connect mshrs_1.io.sinke.valid, _mshrs_1_io_sinke_valid_T_1 connect mshrs_1.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_1.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_1.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_1.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_1.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_1.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_1.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_1.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_1.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_1.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_1.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_1.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_1.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_1.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_1.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_1.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_1.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_1.io.nestedwb.tag, nestedwb.tag connect mshrs_1.io.nestedwb.set, nestedwb.set node _mshrs_2_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_2.io.status.bits.set) node _mshrs_2_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_2_io_sinkc_valid_T) connect mshrs_2.io.sinkc.valid, _mshrs_2_io_sinkc_valid_T_1 node _mshrs_2_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h2)) node _mshrs_2_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_2_io_sinkd_valid_T) connect mshrs_2.io.sinkd.valid, _mshrs_2_io_sinkd_valid_T_1 node _mshrs_2_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h2)) node _mshrs_2_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_2_io_sinke_valid_T) connect mshrs_2.io.sinke.valid, _mshrs_2_io_sinke_valid_T_1 connect mshrs_2.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_2.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_2.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_2.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_2.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_2.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_2.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_2.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_2.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_2.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_2.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_2.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_2.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_2.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_2.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_2.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_2.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_2.io.nestedwb.tag, nestedwb.tag connect mshrs_2.io.nestedwb.set, nestedwb.set node _mshrs_3_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_3.io.status.bits.set) node _mshrs_3_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_3_io_sinkc_valid_T) connect mshrs_3.io.sinkc.valid, _mshrs_3_io_sinkc_valid_T_1 node _mshrs_3_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h3)) node _mshrs_3_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_3_io_sinkd_valid_T) connect mshrs_3.io.sinkd.valid, _mshrs_3_io_sinkd_valid_T_1 node _mshrs_3_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h3)) node _mshrs_3_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_3_io_sinke_valid_T) connect mshrs_3.io.sinke.valid, _mshrs_3_io_sinke_valid_T_1 connect mshrs_3.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_3.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_3.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_3.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_3.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_3.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_3.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_3.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_3.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_3.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_3.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_3.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_3.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_3.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_3.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_3.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_3.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_3.io.nestedwb.tag, nestedwb.tag connect mshrs_3.io.nestedwb.set, nestedwb.set node _mshrs_4_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_4.io.status.bits.set) node _mshrs_4_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_4_io_sinkc_valid_T) connect mshrs_4.io.sinkc.valid, _mshrs_4_io_sinkc_valid_T_1 node _mshrs_4_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h4)) node _mshrs_4_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_4_io_sinkd_valid_T) connect mshrs_4.io.sinkd.valid, _mshrs_4_io_sinkd_valid_T_1 node _mshrs_4_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h4)) node _mshrs_4_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_4_io_sinke_valid_T) connect mshrs_4.io.sinke.valid, _mshrs_4_io_sinke_valid_T_1 connect mshrs_4.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_4.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_4.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_4.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_4.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_4.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_4.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_4.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_4.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_4.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_4.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_4.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_4.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_4.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_4.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_4.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_4.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_4.io.nestedwb.tag, nestedwb.tag connect mshrs_4.io.nestedwb.set, nestedwb.set node _mshrs_5_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_5.io.status.bits.set) node _mshrs_5_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_5_io_sinkc_valid_T) connect mshrs_5.io.sinkc.valid, _mshrs_5_io_sinkc_valid_T_1 node _mshrs_5_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h5)) node _mshrs_5_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_5_io_sinkd_valid_T) connect mshrs_5.io.sinkd.valid, _mshrs_5_io_sinkd_valid_T_1 node _mshrs_5_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h5)) node _mshrs_5_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_5_io_sinke_valid_T) connect mshrs_5.io.sinke.valid, _mshrs_5_io_sinke_valid_T_1 connect mshrs_5.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_5.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_5.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_5.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_5.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_5.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_5.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_5.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_5.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_5.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_5.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_5.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_5.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_5.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_5.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_5.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_5.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_5.io.nestedwb.tag, nestedwb.tag connect mshrs_5.io.nestedwb.set, nestedwb.set node _mshrs_6_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_6.io.status.bits.set) node _mshrs_6_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_6_io_sinkc_valid_T) connect mshrs_6.io.sinkc.valid, _mshrs_6_io_sinkc_valid_T_1 node _mshrs_6_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h6)) node _mshrs_6_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_6_io_sinkd_valid_T) connect mshrs_6.io.sinkd.valid, _mshrs_6_io_sinkd_valid_T_1 node _mshrs_6_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h6)) node _mshrs_6_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_6_io_sinke_valid_T) connect mshrs_6.io.sinke.valid, _mshrs_6_io_sinke_valid_T_1 connect mshrs_6.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_6.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_6.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_6.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_6.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_6.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_6.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_6.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_6.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_6.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_6.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_6.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_6.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_6.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_6.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_6.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_6.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_6.io.nestedwb.tag, nestedwb.tag connect mshrs_6.io.nestedwb.set, nestedwb.set node _mshr_stall_abc_T = eq(mshrs_0.io.status.bits.set, mshrs_5.io.status.bits.set) node _mshr_stall_abc_T_1 = and(mshrs_5.io.status.valid, _mshr_stall_abc_T) node _mshr_stall_abc_T_2 = eq(mshrs_0.io.status.bits.set, mshrs_6.io.status.bits.set) node _mshr_stall_abc_T_3 = and(mshrs_6.io.status.valid, _mshr_stall_abc_T_2) node mshr_stall_abc_0 = or(_mshr_stall_abc_T_1, _mshr_stall_abc_T_3) node _mshr_stall_abc_T_4 = eq(mshrs_1.io.status.bits.set, mshrs_5.io.status.bits.set) node _mshr_stall_abc_T_5 = and(mshrs_5.io.status.valid, _mshr_stall_abc_T_4) node _mshr_stall_abc_T_6 = eq(mshrs_1.io.status.bits.set, mshrs_6.io.status.bits.set) node _mshr_stall_abc_T_7 = and(mshrs_6.io.status.valid, _mshr_stall_abc_T_6) node mshr_stall_abc_1 = or(_mshr_stall_abc_T_5, _mshr_stall_abc_T_7) node _mshr_stall_abc_T_8 = eq(mshrs_2.io.status.bits.set, mshrs_5.io.status.bits.set) node _mshr_stall_abc_T_9 = and(mshrs_5.io.status.valid, _mshr_stall_abc_T_8) node _mshr_stall_abc_T_10 = eq(mshrs_2.io.status.bits.set, mshrs_6.io.status.bits.set) node _mshr_stall_abc_T_11 = and(mshrs_6.io.status.valid, _mshr_stall_abc_T_10) node mshr_stall_abc_2 = or(_mshr_stall_abc_T_9, _mshr_stall_abc_T_11) node _mshr_stall_abc_T_12 = eq(mshrs_3.io.status.bits.set, mshrs_5.io.status.bits.set) node _mshr_stall_abc_T_13 = and(mshrs_5.io.status.valid, _mshr_stall_abc_T_12) node _mshr_stall_abc_T_14 = eq(mshrs_3.io.status.bits.set, mshrs_6.io.status.bits.set) node _mshr_stall_abc_T_15 = and(mshrs_6.io.status.valid, _mshr_stall_abc_T_14) node mshr_stall_abc_3 = or(_mshr_stall_abc_T_13, _mshr_stall_abc_T_15) node _mshr_stall_abc_T_16 = eq(mshrs_4.io.status.bits.set, mshrs_5.io.status.bits.set) node _mshr_stall_abc_T_17 = and(mshrs_5.io.status.valid, _mshr_stall_abc_T_16) node _mshr_stall_abc_T_18 = eq(mshrs_4.io.status.bits.set, mshrs_6.io.status.bits.set) node _mshr_stall_abc_T_19 = and(mshrs_6.io.status.valid, _mshr_stall_abc_T_18) node mshr_stall_abc_4 = or(_mshr_stall_abc_T_17, _mshr_stall_abc_T_19) node _mshr_stall_bc_T = eq(mshrs_5.io.status.bits.set, mshrs_6.io.status.bits.set) node mshr_stall_bc = and(mshrs_6.io.status.valid, _mshr_stall_bc_T) node stall_abc_0 = and(mshr_stall_abc_0, mshrs_0.io.status.valid) node stall_abc_1 = and(mshr_stall_abc_1, mshrs_1.io.status.valid) node stall_abc_2 = and(mshr_stall_abc_2, mshrs_2.io.status.valid) node stall_abc_3 = and(mshr_stall_abc_3, mshrs_3.io.status.valid) node stall_abc_4 = and(mshr_stall_abc_4, mshrs_4.io.status.valid) node _T = or(stall_abc_0, stall_abc_1) node _T_1 = or(_T, stall_abc_2) node _T_2 = or(_T_1, stall_abc_3) node _T_3 = or(_T_2, stall_abc_4) node _mshr_request_T = eq(mshr_stall_abc_0, UInt<1>(0h0)) node _mshr_request_T_1 = and(mshrs_0.io.schedule.valid, _mshr_request_T) node _mshr_request_T_2 = eq(mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_3 = or(sourceA.io.req.ready, _mshr_request_T_2) node _mshr_request_T_4 = and(_mshr_request_T_1, _mshr_request_T_3) node _mshr_request_T_5 = eq(mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_6 = or(sourceB.io.req.ready, _mshr_request_T_5) node _mshr_request_T_7 = and(_mshr_request_T_4, _mshr_request_T_6) node _mshr_request_T_8 = eq(mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_9 = or(sourceC.io.req.ready, _mshr_request_T_8) node _mshr_request_T_10 = and(_mshr_request_T_7, _mshr_request_T_9) node _mshr_request_T_11 = eq(mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_12 = or(sourceD.io.req.ready, _mshr_request_T_11) node _mshr_request_T_13 = and(_mshr_request_T_10, _mshr_request_T_12) node _mshr_request_T_14 = eq(mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_15 = or(sourceE.io.req.ready, _mshr_request_T_14) node _mshr_request_T_16 = and(_mshr_request_T_13, _mshr_request_T_15) node _mshr_request_T_17 = eq(mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_18 = or(sourceX.io.req.ready, _mshr_request_T_17) node _mshr_request_T_19 = and(_mshr_request_T_16, _mshr_request_T_18) node _mshr_request_T_20 = eq(mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_21 = or(directory.io.write.ready, _mshr_request_T_20) node _mshr_request_T_22 = and(_mshr_request_T_19, _mshr_request_T_21) node _mshr_request_T_23 = eq(mshr_stall_abc_1, UInt<1>(0h0)) node _mshr_request_T_24 = and(mshrs_1.io.schedule.valid, _mshr_request_T_23) node _mshr_request_T_25 = eq(mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_26 = or(sourceA.io.req.ready, _mshr_request_T_25) node _mshr_request_T_27 = and(_mshr_request_T_24, _mshr_request_T_26) node _mshr_request_T_28 = eq(mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_29 = or(sourceB.io.req.ready, _mshr_request_T_28) node _mshr_request_T_30 = and(_mshr_request_T_27, _mshr_request_T_29) node _mshr_request_T_31 = eq(mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_32 = or(sourceC.io.req.ready, _mshr_request_T_31) node _mshr_request_T_33 = and(_mshr_request_T_30, _mshr_request_T_32) node _mshr_request_T_34 = eq(mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_35 = or(sourceD.io.req.ready, _mshr_request_T_34) node _mshr_request_T_36 = and(_mshr_request_T_33, _mshr_request_T_35) node _mshr_request_T_37 = eq(mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_38 = or(sourceE.io.req.ready, _mshr_request_T_37) node _mshr_request_T_39 = and(_mshr_request_T_36, _mshr_request_T_38) node _mshr_request_T_40 = eq(mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_41 = or(sourceX.io.req.ready, _mshr_request_T_40) node _mshr_request_T_42 = and(_mshr_request_T_39, _mshr_request_T_41) node _mshr_request_T_43 = eq(mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_44 = or(directory.io.write.ready, _mshr_request_T_43) node _mshr_request_T_45 = and(_mshr_request_T_42, _mshr_request_T_44) node _mshr_request_T_46 = eq(mshr_stall_abc_2, UInt<1>(0h0)) node _mshr_request_T_47 = and(mshrs_2.io.schedule.valid, _mshr_request_T_46) node _mshr_request_T_48 = eq(mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_49 = or(sourceA.io.req.ready, _mshr_request_T_48) node _mshr_request_T_50 = and(_mshr_request_T_47, _mshr_request_T_49) node _mshr_request_T_51 = eq(mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_52 = or(sourceB.io.req.ready, _mshr_request_T_51) node _mshr_request_T_53 = and(_mshr_request_T_50, _mshr_request_T_52) node _mshr_request_T_54 = eq(mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_55 = or(sourceC.io.req.ready, _mshr_request_T_54) node _mshr_request_T_56 = and(_mshr_request_T_53, _mshr_request_T_55) node _mshr_request_T_57 = eq(mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_58 = or(sourceD.io.req.ready, _mshr_request_T_57) node _mshr_request_T_59 = and(_mshr_request_T_56, _mshr_request_T_58) node _mshr_request_T_60 = eq(mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_61 = or(sourceE.io.req.ready, _mshr_request_T_60) node _mshr_request_T_62 = and(_mshr_request_T_59, _mshr_request_T_61) node _mshr_request_T_63 = eq(mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_64 = or(sourceX.io.req.ready, _mshr_request_T_63) node _mshr_request_T_65 = and(_mshr_request_T_62, _mshr_request_T_64) node _mshr_request_T_66 = eq(mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_67 = or(directory.io.write.ready, _mshr_request_T_66) node _mshr_request_T_68 = and(_mshr_request_T_65, _mshr_request_T_67) node _mshr_request_T_69 = eq(mshr_stall_abc_3, UInt<1>(0h0)) node _mshr_request_T_70 = and(mshrs_3.io.schedule.valid, _mshr_request_T_69) node _mshr_request_T_71 = eq(mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_72 = or(sourceA.io.req.ready, _mshr_request_T_71) node _mshr_request_T_73 = and(_mshr_request_T_70, _mshr_request_T_72) node _mshr_request_T_74 = eq(mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_75 = or(sourceB.io.req.ready, _mshr_request_T_74) node _mshr_request_T_76 = and(_mshr_request_T_73, _mshr_request_T_75) node _mshr_request_T_77 = eq(mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_78 = or(sourceC.io.req.ready, _mshr_request_T_77) node _mshr_request_T_79 = and(_mshr_request_T_76, _mshr_request_T_78) node _mshr_request_T_80 = eq(mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_81 = or(sourceD.io.req.ready, _mshr_request_T_80) node _mshr_request_T_82 = and(_mshr_request_T_79, _mshr_request_T_81) node _mshr_request_T_83 = eq(mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_84 = or(sourceE.io.req.ready, _mshr_request_T_83) node _mshr_request_T_85 = and(_mshr_request_T_82, _mshr_request_T_84) node _mshr_request_T_86 = eq(mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_87 = or(sourceX.io.req.ready, _mshr_request_T_86) node _mshr_request_T_88 = and(_mshr_request_T_85, _mshr_request_T_87) node _mshr_request_T_89 = eq(mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_90 = or(directory.io.write.ready, _mshr_request_T_89) node _mshr_request_T_91 = and(_mshr_request_T_88, _mshr_request_T_90) node _mshr_request_T_92 = eq(mshr_stall_abc_4, UInt<1>(0h0)) node _mshr_request_T_93 = and(mshrs_4.io.schedule.valid, _mshr_request_T_92) node _mshr_request_T_94 = eq(mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_95 = or(sourceA.io.req.ready, _mshr_request_T_94) node _mshr_request_T_96 = and(_mshr_request_T_93, _mshr_request_T_95) node _mshr_request_T_97 = eq(mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_98 = or(sourceB.io.req.ready, _mshr_request_T_97) node _mshr_request_T_99 = and(_mshr_request_T_96, _mshr_request_T_98) node _mshr_request_T_100 = eq(mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_101 = or(sourceC.io.req.ready, _mshr_request_T_100) node _mshr_request_T_102 = and(_mshr_request_T_99, _mshr_request_T_101) node _mshr_request_T_103 = eq(mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_104 = or(sourceD.io.req.ready, _mshr_request_T_103) node _mshr_request_T_105 = and(_mshr_request_T_102, _mshr_request_T_104) node _mshr_request_T_106 = eq(mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_107 = or(sourceE.io.req.ready, _mshr_request_T_106) node _mshr_request_T_108 = and(_mshr_request_T_105, _mshr_request_T_107) node _mshr_request_T_109 = eq(mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_110 = or(sourceX.io.req.ready, _mshr_request_T_109) node _mshr_request_T_111 = and(_mshr_request_T_108, _mshr_request_T_110) node _mshr_request_T_112 = eq(mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_113 = or(directory.io.write.ready, _mshr_request_T_112) node _mshr_request_T_114 = and(_mshr_request_T_111, _mshr_request_T_113) node _mshr_request_T_115 = eq(mshr_stall_bc, UInt<1>(0h0)) node _mshr_request_T_116 = and(mshrs_5.io.schedule.valid, _mshr_request_T_115) node _mshr_request_T_117 = eq(mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_118 = or(sourceA.io.req.ready, _mshr_request_T_117) node _mshr_request_T_119 = and(_mshr_request_T_116, _mshr_request_T_118) node _mshr_request_T_120 = eq(mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_121 = or(sourceB.io.req.ready, _mshr_request_T_120) node _mshr_request_T_122 = and(_mshr_request_T_119, _mshr_request_T_121) node _mshr_request_T_123 = eq(mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_124 = or(sourceC.io.req.ready, _mshr_request_T_123) node _mshr_request_T_125 = and(_mshr_request_T_122, _mshr_request_T_124) node _mshr_request_T_126 = eq(mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_127 = or(sourceD.io.req.ready, _mshr_request_T_126) node _mshr_request_T_128 = and(_mshr_request_T_125, _mshr_request_T_127) node _mshr_request_T_129 = eq(mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_130 = or(sourceE.io.req.ready, _mshr_request_T_129) node _mshr_request_T_131 = and(_mshr_request_T_128, _mshr_request_T_130) node _mshr_request_T_132 = eq(mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_133 = or(sourceX.io.req.ready, _mshr_request_T_132) node _mshr_request_T_134 = and(_mshr_request_T_131, _mshr_request_T_133) node _mshr_request_T_135 = eq(mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_136 = or(directory.io.write.ready, _mshr_request_T_135) node _mshr_request_T_137 = and(_mshr_request_T_134, _mshr_request_T_136) node _mshr_request_T_138 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _mshr_request_T_139 = and(mshrs_6.io.schedule.valid, _mshr_request_T_138) node _mshr_request_T_140 = eq(mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_141 = or(sourceA.io.req.ready, _mshr_request_T_140) node _mshr_request_T_142 = and(_mshr_request_T_139, _mshr_request_T_141) node _mshr_request_T_143 = eq(mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_144 = or(sourceB.io.req.ready, _mshr_request_T_143) node _mshr_request_T_145 = and(_mshr_request_T_142, _mshr_request_T_144) node _mshr_request_T_146 = eq(mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_147 = or(sourceC.io.req.ready, _mshr_request_T_146) node _mshr_request_T_148 = and(_mshr_request_T_145, _mshr_request_T_147) node _mshr_request_T_149 = eq(mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_150 = or(sourceD.io.req.ready, _mshr_request_T_149) node _mshr_request_T_151 = and(_mshr_request_T_148, _mshr_request_T_150) node _mshr_request_T_152 = eq(mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_153 = or(sourceE.io.req.ready, _mshr_request_T_152) node _mshr_request_T_154 = and(_mshr_request_T_151, _mshr_request_T_153) node _mshr_request_T_155 = eq(mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_156 = or(sourceX.io.req.ready, _mshr_request_T_155) node _mshr_request_T_157 = and(_mshr_request_T_154, _mshr_request_T_156) node _mshr_request_T_158 = eq(mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_159 = or(directory.io.write.ready, _mshr_request_T_158) node _mshr_request_T_160 = and(_mshr_request_T_157, _mshr_request_T_159) node mshr_request_lo_hi = cat(_mshr_request_T_68, _mshr_request_T_45) node mshr_request_lo = cat(mshr_request_lo_hi, _mshr_request_T_22) node mshr_request_hi_lo = cat(_mshr_request_T_114, _mshr_request_T_91) node mshr_request_hi_hi = cat(_mshr_request_T_160, _mshr_request_T_137) node mshr_request_hi = cat(mshr_request_hi_hi, mshr_request_hi_lo) node mshr_request = cat(mshr_request_hi, mshr_request_lo) regreset robin_filter : UInt<7>, clock, reset, UInt<7>(0h0) node _robin_request_T = and(mshr_request, robin_filter) node robin_request = cat(mshr_request, _robin_request_T) node _mshr_selectOH2_T = shl(robin_request, 1) node _mshr_selectOH2_T_1 = bits(_mshr_selectOH2_T, 13, 0) node _mshr_selectOH2_T_2 = or(robin_request, _mshr_selectOH2_T_1) node _mshr_selectOH2_T_3 = shl(_mshr_selectOH2_T_2, 2) node _mshr_selectOH2_T_4 = bits(_mshr_selectOH2_T_3, 13, 0) node _mshr_selectOH2_T_5 = or(_mshr_selectOH2_T_2, _mshr_selectOH2_T_4) node _mshr_selectOH2_T_6 = shl(_mshr_selectOH2_T_5, 4) node _mshr_selectOH2_T_7 = bits(_mshr_selectOH2_T_6, 13, 0) node _mshr_selectOH2_T_8 = or(_mshr_selectOH2_T_5, _mshr_selectOH2_T_7) node _mshr_selectOH2_T_9 = shl(_mshr_selectOH2_T_8, 8) node _mshr_selectOH2_T_10 = bits(_mshr_selectOH2_T_9, 13, 0) node _mshr_selectOH2_T_11 = or(_mshr_selectOH2_T_8, _mshr_selectOH2_T_10) node _mshr_selectOH2_T_12 = bits(_mshr_selectOH2_T_11, 13, 0) node _mshr_selectOH2_T_13 = shl(_mshr_selectOH2_T_12, 1) node _mshr_selectOH2_T_14 = not(_mshr_selectOH2_T_13) node mshr_selectOH2 = and(_mshr_selectOH2_T_14, robin_request) node _mshr_selectOH_T = bits(mshr_selectOH2, 13, 7) node _mshr_selectOH_T_1 = bits(mshr_selectOH2, 6, 0) node mshr_selectOH = or(_mshr_selectOH_T, _mshr_selectOH_T_1) node mshr_select_hi = bits(mshr_selectOH, 6, 4) node mshr_select_lo = bits(mshr_selectOH, 3, 0) node _mshr_select_T = orr(mshr_select_hi) node _mshr_select_T_1 = or(mshr_select_hi, mshr_select_lo) node mshr_select_hi_1 = bits(_mshr_select_T_1, 3, 2) node mshr_select_lo_1 = bits(_mshr_select_T_1, 1, 0) node _mshr_select_T_2 = orr(mshr_select_hi_1) node _mshr_select_T_3 = or(mshr_select_hi_1, mshr_select_lo_1) node _mshr_select_T_4 = bits(_mshr_select_T_3, 1, 1) node _mshr_select_T_5 = cat(_mshr_select_T_2, _mshr_select_T_4) node mshr_select = cat(_mshr_select_T, _mshr_select_T_5) node _schedule_T = bits(mshr_selectOH, 0, 0) node _schedule_T_1 = bits(mshr_selectOH, 1, 1) node _schedule_T_2 = bits(mshr_selectOH, 2, 2) node _schedule_T_3 = bits(mshr_selectOH, 3, 3) node _schedule_T_4 = bits(mshr_selectOH, 4, 4) node _schedule_T_5 = bits(mshr_selectOH, 5, 5) node _schedule_T_6 = bits(mshr_selectOH, 6, 6) wire schedule : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>} node _schedule_T_7 = mux(_schedule_T, mshrs_0.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_8 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_9 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_10 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_11 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_12 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_13 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_14 = or(_schedule_T_7, _schedule_T_8) node _schedule_T_15 = or(_schedule_T_14, _schedule_T_9) node _schedule_T_16 = or(_schedule_T_15, _schedule_T_10) node _schedule_T_17 = or(_schedule_T_16, _schedule_T_11) node _schedule_T_18 = or(_schedule_T_17, _schedule_T_12) node _schedule_T_19 = or(_schedule_T_18, _schedule_T_13) wire _schedule_WIRE : UInt<1> connect _schedule_WIRE, _schedule_T_19 connect schedule.reload, _schedule_WIRE wire _schedule_WIRE_1 : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}} wire _schedule_WIRE_2 : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}} wire _schedule_WIRE_3 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} node _schedule_T_20 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_21 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_22 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_23 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_24 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_25 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_26 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_27 = or(_schedule_T_20, _schedule_T_21) node _schedule_T_28 = or(_schedule_T_27, _schedule_T_22) node _schedule_T_29 = or(_schedule_T_28, _schedule_T_23) node _schedule_T_30 = or(_schedule_T_29, _schedule_T_24) node _schedule_T_31 = or(_schedule_T_30, _schedule_T_25) node _schedule_T_32 = or(_schedule_T_31, _schedule_T_26) wire _schedule_WIRE_4 : UInt<13> connect _schedule_WIRE_4, _schedule_T_32 connect _schedule_WIRE_3.tag, _schedule_WIRE_4 node _schedule_T_33 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_34 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_35 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_36 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_37 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_38 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_39 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_40 = or(_schedule_T_33, _schedule_T_34) node _schedule_T_41 = or(_schedule_T_40, _schedule_T_35) node _schedule_T_42 = or(_schedule_T_41, _schedule_T_36) node _schedule_T_43 = or(_schedule_T_42, _schedule_T_37) node _schedule_T_44 = or(_schedule_T_43, _schedule_T_38) node _schedule_T_45 = or(_schedule_T_44, _schedule_T_39) wire _schedule_WIRE_5 : UInt<1> connect _schedule_WIRE_5, _schedule_T_45 connect _schedule_WIRE_3.clients, _schedule_WIRE_5 node _schedule_T_46 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_47 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_48 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_49 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_50 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_51 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_52 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_53 = or(_schedule_T_46, _schedule_T_47) node _schedule_T_54 = or(_schedule_T_53, _schedule_T_48) node _schedule_T_55 = or(_schedule_T_54, _schedule_T_49) node _schedule_T_56 = or(_schedule_T_55, _schedule_T_50) node _schedule_T_57 = or(_schedule_T_56, _schedule_T_51) node _schedule_T_58 = or(_schedule_T_57, _schedule_T_52) wire _schedule_WIRE_6 : UInt<2> connect _schedule_WIRE_6, _schedule_T_58 connect _schedule_WIRE_3.state, _schedule_WIRE_6 node _schedule_T_59 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_60 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_61 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_62 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_63 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_64 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_65 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_66 = or(_schedule_T_59, _schedule_T_60) node _schedule_T_67 = or(_schedule_T_66, _schedule_T_61) node _schedule_T_68 = or(_schedule_T_67, _schedule_T_62) node _schedule_T_69 = or(_schedule_T_68, _schedule_T_63) node _schedule_T_70 = or(_schedule_T_69, _schedule_T_64) node _schedule_T_71 = or(_schedule_T_70, _schedule_T_65) wire _schedule_WIRE_7 : UInt<1> connect _schedule_WIRE_7, _schedule_T_71 connect _schedule_WIRE_3.dirty, _schedule_WIRE_7 connect _schedule_WIRE_2.data, _schedule_WIRE_3 node _schedule_T_72 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_73 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_74 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_75 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_76 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_77 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_78 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_79 = or(_schedule_T_72, _schedule_T_73) node _schedule_T_80 = or(_schedule_T_79, _schedule_T_74) node _schedule_T_81 = or(_schedule_T_80, _schedule_T_75) node _schedule_T_82 = or(_schedule_T_81, _schedule_T_76) node _schedule_T_83 = or(_schedule_T_82, _schedule_T_77) node _schedule_T_84 = or(_schedule_T_83, _schedule_T_78) wire _schedule_WIRE_8 : UInt<3> connect _schedule_WIRE_8, _schedule_T_84 connect _schedule_WIRE_2.way, _schedule_WIRE_8 node _schedule_T_85 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_86 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_87 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_88 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_89 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_90 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_91 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_92 = or(_schedule_T_85, _schedule_T_86) node _schedule_T_93 = or(_schedule_T_92, _schedule_T_87) node _schedule_T_94 = or(_schedule_T_93, _schedule_T_88) node _schedule_T_95 = or(_schedule_T_94, _schedule_T_89) node _schedule_T_96 = or(_schedule_T_95, _schedule_T_90) node _schedule_T_97 = or(_schedule_T_96, _schedule_T_91) wire _schedule_WIRE_9 : UInt<10> connect _schedule_WIRE_9, _schedule_T_97 connect _schedule_WIRE_2.set, _schedule_WIRE_9 connect _schedule_WIRE_1.bits, _schedule_WIRE_2 node _schedule_T_98 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_99 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_100 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_101 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_102 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_103 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_104 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_105 = or(_schedule_T_98, _schedule_T_99) node _schedule_T_106 = or(_schedule_T_105, _schedule_T_100) node _schedule_T_107 = or(_schedule_T_106, _schedule_T_101) node _schedule_T_108 = or(_schedule_T_107, _schedule_T_102) node _schedule_T_109 = or(_schedule_T_108, _schedule_T_103) node _schedule_T_110 = or(_schedule_T_109, _schedule_T_104) wire _schedule_WIRE_10 : UInt<1> connect _schedule_WIRE_10, _schedule_T_110 connect _schedule_WIRE_1.valid, _schedule_WIRE_10 connect schedule.dir, _schedule_WIRE_1 wire _schedule_WIRE_11 : { valid : UInt<1>, bits : { fail : UInt<1>}} wire _schedule_WIRE_12 : { fail : UInt<1>} node _schedule_T_111 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_112 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_113 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_114 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_115 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_116 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_117 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_118 = or(_schedule_T_111, _schedule_T_112) node _schedule_T_119 = or(_schedule_T_118, _schedule_T_113) node _schedule_T_120 = or(_schedule_T_119, _schedule_T_114) node _schedule_T_121 = or(_schedule_T_120, _schedule_T_115) node _schedule_T_122 = or(_schedule_T_121, _schedule_T_116) node _schedule_T_123 = or(_schedule_T_122, _schedule_T_117) wire _schedule_WIRE_13 : UInt<1> connect _schedule_WIRE_13, _schedule_T_123 connect _schedule_WIRE_12.fail, _schedule_WIRE_13 connect _schedule_WIRE_11.bits, _schedule_WIRE_12 node _schedule_T_124 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_125 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_126 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_127 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_128 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_129 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_130 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_131 = or(_schedule_T_124, _schedule_T_125) node _schedule_T_132 = or(_schedule_T_131, _schedule_T_126) node _schedule_T_133 = or(_schedule_T_132, _schedule_T_127) node _schedule_T_134 = or(_schedule_T_133, _schedule_T_128) node _schedule_T_135 = or(_schedule_T_134, _schedule_T_129) node _schedule_T_136 = or(_schedule_T_135, _schedule_T_130) wire _schedule_WIRE_14 : UInt<1> connect _schedule_WIRE_14, _schedule_T_136 connect _schedule_WIRE_11.valid, _schedule_WIRE_14 connect schedule.x, _schedule_WIRE_11 wire _schedule_WIRE_15 : { valid : UInt<1>, bits : { sink : UInt<3>}} wire _schedule_WIRE_16 : { sink : UInt<3>} node _schedule_T_137 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_138 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_139 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_140 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_141 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_142 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_143 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_144 = or(_schedule_T_137, _schedule_T_138) node _schedule_T_145 = or(_schedule_T_144, _schedule_T_139) node _schedule_T_146 = or(_schedule_T_145, _schedule_T_140) node _schedule_T_147 = or(_schedule_T_146, _schedule_T_141) node _schedule_T_148 = or(_schedule_T_147, _schedule_T_142) node _schedule_T_149 = or(_schedule_T_148, _schedule_T_143) wire _schedule_WIRE_17 : UInt<3> connect _schedule_WIRE_17, _schedule_T_149 connect _schedule_WIRE_16.sink, _schedule_WIRE_17 connect _schedule_WIRE_15.bits, _schedule_WIRE_16 node _schedule_T_150 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_151 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_152 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_153 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_154 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_155 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_156 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_157 = or(_schedule_T_150, _schedule_T_151) node _schedule_T_158 = or(_schedule_T_157, _schedule_T_152) node _schedule_T_159 = or(_schedule_T_158, _schedule_T_153) node _schedule_T_160 = or(_schedule_T_159, _schedule_T_154) node _schedule_T_161 = or(_schedule_T_160, _schedule_T_155) node _schedule_T_162 = or(_schedule_T_161, _schedule_T_156) wire _schedule_WIRE_18 : UInt<1> connect _schedule_WIRE_18, _schedule_T_162 connect _schedule_WIRE_15.valid, _schedule_WIRE_18 connect schedule.e, _schedule_WIRE_15 wire _schedule_WIRE_19 : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}} wire _schedule_WIRE_20 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>} node _schedule_T_163 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_164 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_165 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_166 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_167 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_168 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_169 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_170 = or(_schedule_T_163, _schedule_T_164) node _schedule_T_171 = or(_schedule_T_170, _schedule_T_165) node _schedule_T_172 = or(_schedule_T_171, _schedule_T_166) node _schedule_T_173 = or(_schedule_T_172, _schedule_T_167) node _schedule_T_174 = or(_schedule_T_173, _schedule_T_168) node _schedule_T_175 = or(_schedule_T_174, _schedule_T_169) wire _schedule_WIRE_21 : UInt<1> connect _schedule_WIRE_21, _schedule_T_175 connect _schedule_WIRE_20.bad, _schedule_WIRE_21 node _schedule_T_176 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_177 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_178 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_179 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_180 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_181 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_182 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_183 = or(_schedule_T_176, _schedule_T_177) node _schedule_T_184 = or(_schedule_T_183, _schedule_T_178) node _schedule_T_185 = or(_schedule_T_184, _schedule_T_179) node _schedule_T_186 = or(_schedule_T_185, _schedule_T_180) node _schedule_T_187 = or(_schedule_T_186, _schedule_T_181) node _schedule_T_188 = or(_schedule_T_187, _schedule_T_182) wire _schedule_WIRE_22 : UInt<3> connect _schedule_WIRE_22, _schedule_T_188 connect _schedule_WIRE_20.way, _schedule_WIRE_22 node _schedule_T_189 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_190 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_191 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_192 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_193 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_194 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_195 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_196 = or(_schedule_T_189, _schedule_T_190) node _schedule_T_197 = or(_schedule_T_196, _schedule_T_191) node _schedule_T_198 = or(_schedule_T_197, _schedule_T_192) node _schedule_T_199 = or(_schedule_T_198, _schedule_T_193) node _schedule_T_200 = or(_schedule_T_199, _schedule_T_194) node _schedule_T_201 = or(_schedule_T_200, _schedule_T_195) wire _schedule_WIRE_23 : UInt<3> connect _schedule_WIRE_23, _schedule_T_201 connect _schedule_WIRE_20.sink, _schedule_WIRE_23 node _schedule_T_202 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_203 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_204 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_205 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_206 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_207 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_208 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_209 = or(_schedule_T_202, _schedule_T_203) node _schedule_T_210 = or(_schedule_T_209, _schedule_T_204) node _schedule_T_211 = or(_schedule_T_210, _schedule_T_205) node _schedule_T_212 = or(_schedule_T_211, _schedule_T_206) node _schedule_T_213 = or(_schedule_T_212, _schedule_T_207) node _schedule_T_214 = or(_schedule_T_213, _schedule_T_208) wire _schedule_WIRE_24 : UInt<10> connect _schedule_WIRE_24, _schedule_T_214 connect _schedule_WIRE_20.set, _schedule_WIRE_24 node _schedule_T_215 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_216 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_217 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_218 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_219 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_220 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_221 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_222 = or(_schedule_T_215, _schedule_T_216) node _schedule_T_223 = or(_schedule_T_222, _schedule_T_217) node _schedule_T_224 = or(_schedule_T_223, _schedule_T_218) node _schedule_T_225 = or(_schedule_T_224, _schedule_T_219) node _schedule_T_226 = or(_schedule_T_225, _schedule_T_220) node _schedule_T_227 = or(_schedule_T_226, _schedule_T_221) wire _schedule_WIRE_25 : UInt<6> connect _schedule_WIRE_25, _schedule_T_227 connect _schedule_WIRE_20.put, _schedule_WIRE_25 node _schedule_T_228 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_229 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_230 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_231 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_232 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_233 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_234 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_235 = or(_schedule_T_228, _schedule_T_229) node _schedule_T_236 = or(_schedule_T_235, _schedule_T_230) node _schedule_T_237 = or(_schedule_T_236, _schedule_T_231) node _schedule_T_238 = or(_schedule_T_237, _schedule_T_232) node _schedule_T_239 = or(_schedule_T_238, _schedule_T_233) node _schedule_T_240 = or(_schedule_T_239, _schedule_T_234) wire _schedule_WIRE_26 : UInt<6> connect _schedule_WIRE_26, _schedule_T_240 connect _schedule_WIRE_20.offset, _schedule_WIRE_26 node _schedule_T_241 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_242 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_243 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_244 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_245 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_246 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_247 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_248 = or(_schedule_T_241, _schedule_T_242) node _schedule_T_249 = or(_schedule_T_248, _schedule_T_243) node _schedule_T_250 = or(_schedule_T_249, _schedule_T_244) node _schedule_T_251 = or(_schedule_T_250, _schedule_T_245) node _schedule_T_252 = or(_schedule_T_251, _schedule_T_246) node _schedule_T_253 = or(_schedule_T_252, _schedule_T_247) wire _schedule_WIRE_27 : UInt<13> connect _schedule_WIRE_27, _schedule_T_253 connect _schedule_WIRE_20.tag, _schedule_WIRE_27 node _schedule_T_254 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_255 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_256 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_257 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_258 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_259 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_260 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_261 = or(_schedule_T_254, _schedule_T_255) node _schedule_T_262 = or(_schedule_T_261, _schedule_T_256) node _schedule_T_263 = or(_schedule_T_262, _schedule_T_257) node _schedule_T_264 = or(_schedule_T_263, _schedule_T_258) node _schedule_T_265 = or(_schedule_T_264, _schedule_T_259) node _schedule_T_266 = or(_schedule_T_265, _schedule_T_260) wire _schedule_WIRE_28 : UInt<6> connect _schedule_WIRE_28, _schedule_T_266 connect _schedule_WIRE_20.source, _schedule_WIRE_28 node _schedule_T_267 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_268 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_269 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_270 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_271 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_272 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_273 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_274 = or(_schedule_T_267, _schedule_T_268) node _schedule_T_275 = or(_schedule_T_274, _schedule_T_269) node _schedule_T_276 = or(_schedule_T_275, _schedule_T_270) node _schedule_T_277 = or(_schedule_T_276, _schedule_T_271) node _schedule_T_278 = or(_schedule_T_277, _schedule_T_272) node _schedule_T_279 = or(_schedule_T_278, _schedule_T_273) wire _schedule_WIRE_29 : UInt<3> connect _schedule_WIRE_29, _schedule_T_279 connect _schedule_WIRE_20.size, _schedule_WIRE_29 node _schedule_T_280 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_281 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_282 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_283 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_284 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_285 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_286 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_287 = or(_schedule_T_280, _schedule_T_281) node _schedule_T_288 = or(_schedule_T_287, _schedule_T_282) node _schedule_T_289 = or(_schedule_T_288, _schedule_T_283) node _schedule_T_290 = or(_schedule_T_289, _schedule_T_284) node _schedule_T_291 = or(_schedule_T_290, _schedule_T_285) node _schedule_T_292 = or(_schedule_T_291, _schedule_T_286) wire _schedule_WIRE_30 : UInt<3> connect _schedule_WIRE_30, _schedule_T_292 connect _schedule_WIRE_20.param, _schedule_WIRE_30 node _schedule_T_293 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_294 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_295 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_296 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_297 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_298 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_299 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_300 = or(_schedule_T_293, _schedule_T_294) node _schedule_T_301 = or(_schedule_T_300, _schedule_T_295) node _schedule_T_302 = or(_schedule_T_301, _schedule_T_296) node _schedule_T_303 = or(_schedule_T_302, _schedule_T_297) node _schedule_T_304 = or(_schedule_T_303, _schedule_T_298) node _schedule_T_305 = or(_schedule_T_304, _schedule_T_299) wire _schedule_WIRE_31 : UInt<3> connect _schedule_WIRE_31, _schedule_T_305 connect _schedule_WIRE_20.opcode, _schedule_WIRE_31 node _schedule_T_306 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_307 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_308 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_309 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_310 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_311 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_312 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_313 = or(_schedule_T_306, _schedule_T_307) node _schedule_T_314 = or(_schedule_T_313, _schedule_T_308) node _schedule_T_315 = or(_schedule_T_314, _schedule_T_309) node _schedule_T_316 = or(_schedule_T_315, _schedule_T_310) node _schedule_T_317 = or(_schedule_T_316, _schedule_T_311) node _schedule_T_318 = or(_schedule_T_317, _schedule_T_312) wire _schedule_WIRE_32 : UInt<1> connect _schedule_WIRE_32, _schedule_T_318 connect _schedule_WIRE_20.control, _schedule_WIRE_32 wire _schedule_WIRE_33 : UInt<1>[3] node _schedule_T_319 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_320 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_321 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_322 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_323 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_324 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_325 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_326 = or(_schedule_T_319, _schedule_T_320) node _schedule_T_327 = or(_schedule_T_326, _schedule_T_321) node _schedule_T_328 = or(_schedule_T_327, _schedule_T_322) node _schedule_T_329 = or(_schedule_T_328, _schedule_T_323) node _schedule_T_330 = or(_schedule_T_329, _schedule_T_324) node _schedule_T_331 = or(_schedule_T_330, _schedule_T_325) wire _schedule_WIRE_34 : UInt<1> connect _schedule_WIRE_34, _schedule_T_331 connect _schedule_WIRE_33[0], _schedule_WIRE_34 node _schedule_T_332 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_333 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_334 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_335 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_336 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_337 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_338 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_339 = or(_schedule_T_332, _schedule_T_333) node _schedule_T_340 = or(_schedule_T_339, _schedule_T_334) node _schedule_T_341 = or(_schedule_T_340, _schedule_T_335) node _schedule_T_342 = or(_schedule_T_341, _schedule_T_336) node _schedule_T_343 = or(_schedule_T_342, _schedule_T_337) node _schedule_T_344 = or(_schedule_T_343, _schedule_T_338) wire _schedule_WIRE_35 : UInt<1> connect _schedule_WIRE_35, _schedule_T_344 connect _schedule_WIRE_33[1], _schedule_WIRE_35 node _schedule_T_345 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_346 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_347 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_348 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_349 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_350 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_351 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_352 = or(_schedule_T_345, _schedule_T_346) node _schedule_T_353 = or(_schedule_T_352, _schedule_T_347) node _schedule_T_354 = or(_schedule_T_353, _schedule_T_348) node _schedule_T_355 = or(_schedule_T_354, _schedule_T_349) node _schedule_T_356 = or(_schedule_T_355, _schedule_T_350) node _schedule_T_357 = or(_schedule_T_356, _schedule_T_351) wire _schedule_WIRE_36 : UInt<1> connect _schedule_WIRE_36, _schedule_T_357 connect _schedule_WIRE_33[2], _schedule_WIRE_36 connect _schedule_WIRE_20.prio, _schedule_WIRE_33 connect _schedule_WIRE_19.bits, _schedule_WIRE_20 node _schedule_T_358 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_359 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_360 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_361 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_362 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_363 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_364 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_365 = or(_schedule_T_358, _schedule_T_359) node _schedule_T_366 = or(_schedule_T_365, _schedule_T_360) node _schedule_T_367 = or(_schedule_T_366, _schedule_T_361) node _schedule_T_368 = or(_schedule_T_367, _schedule_T_362) node _schedule_T_369 = or(_schedule_T_368, _schedule_T_363) node _schedule_T_370 = or(_schedule_T_369, _schedule_T_364) wire _schedule_WIRE_37 : UInt<1> connect _schedule_WIRE_37, _schedule_T_370 connect _schedule_WIRE_19.valid, _schedule_WIRE_37 connect schedule.d, _schedule_WIRE_19 wire _schedule_WIRE_38 : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}} wire _schedule_WIRE_39 : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>} node _schedule_T_371 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_372 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_373 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_374 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_375 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_376 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_377 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_378 = or(_schedule_T_371, _schedule_T_372) node _schedule_T_379 = or(_schedule_T_378, _schedule_T_373) node _schedule_T_380 = or(_schedule_T_379, _schedule_T_374) node _schedule_T_381 = or(_schedule_T_380, _schedule_T_375) node _schedule_T_382 = or(_schedule_T_381, _schedule_T_376) node _schedule_T_383 = or(_schedule_T_382, _schedule_T_377) wire _schedule_WIRE_40 : UInt<1> connect _schedule_WIRE_40, _schedule_T_383 connect _schedule_WIRE_39.dirty, _schedule_WIRE_40 node _schedule_T_384 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_385 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_386 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_387 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_388 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_389 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_390 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_391 = or(_schedule_T_384, _schedule_T_385) node _schedule_T_392 = or(_schedule_T_391, _schedule_T_386) node _schedule_T_393 = or(_schedule_T_392, _schedule_T_387) node _schedule_T_394 = or(_schedule_T_393, _schedule_T_388) node _schedule_T_395 = or(_schedule_T_394, _schedule_T_389) node _schedule_T_396 = or(_schedule_T_395, _schedule_T_390) wire _schedule_WIRE_41 : UInt<3> connect _schedule_WIRE_41, _schedule_T_396 connect _schedule_WIRE_39.way, _schedule_WIRE_41 node _schedule_T_397 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_398 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_399 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_400 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_401 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_402 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_403 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_404 = or(_schedule_T_397, _schedule_T_398) node _schedule_T_405 = or(_schedule_T_404, _schedule_T_399) node _schedule_T_406 = or(_schedule_T_405, _schedule_T_400) node _schedule_T_407 = or(_schedule_T_406, _schedule_T_401) node _schedule_T_408 = or(_schedule_T_407, _schedule_T_402) node _schedule_T_409 = or(_schedule_T_408, _schedule_T_403) wire _schedule_WIRE_42 : UInt<10> connect _schedule_WIRE_42, _schedule_T_409 connect _schedule_WIRE_39.set, _schedule_WIRE_42 node _schedule_T_410 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_411 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_412 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_413 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_414 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_415 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_416 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_417 = or(_schedule_T_410, _schedule_T_411) node _schedule_T_418 = or(_schedule_T_417, _schedule_T_412) node _schedule_T_419 = or(_schedule_T_418, _schedule_T_413) node _schedule_T_420 = or(_schedule_T_419, _schedule_T_414) node _schedule_T_421 = or(_schedule_T_420, _schedule_T_415) node _schedule_T_422 = or(_schedule_T_421, _schedule_T_416) wire _schedule_WIRE_43 : UInt<13> connect _schedule_WIRE_43, _schedule_T_422 connect _schedule_WIRE_39.tag, _schedule_WIRE_43 node _schedule_T_423 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_424 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_425 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_426 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_427 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_428 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_429 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_430 = or(_schedule_T_423, _schedule_T_424) node _schedule_T_431 = or(_schedule_T_430, _schedule_T_425) node _schedule_T_432 = or(_schedule_T_431, _schedule_T_426) node _schedule_T_433 = or(_schedule_T_432, _schedule_T_427) node _schedule_T_434 = or(_schedule_T_433, _schedule_T_428) node _schedule_T_435 = or(_schedule_T_434, _schedule_T_429) wire _schedule_WIRE_44 : UInt<3> connect _schedule_WIRE_44, _schedule_T_435 connect _schedule_WIRE_39.source, _schedule_WIRE_44 node _schedule_T_436 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_437 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_438 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_439 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_440 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_441 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_442 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_443 = or(_schedule_T_436, _schedule_T_437) node _schedule_T_444 = or(_schedule_T_443, _schedule_T_438) node _schedule_T_445 = or(_schedule_T_444, _schedule_T_439) node _schedule_T_446 = or(_schedule_T_445, _schedule_T_440) node _schedule_T_447 = or(_schedule_T_446, _schedule_T_441) node _schedule_T_448 = or(_schedule_T_447, _schedule_T_442) wire _schedule_WIRE_45 : UInt<3> connect _schedule_WIRE_45, _schedule_T_448 connect _schedule_WIRE_39.param, _schedule_WIRE_45 node _schedule_T_449 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_450 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_451 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_452 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_453 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_454 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_455 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_456 = or(_schedule_T_449, _schedule_T_450) node _schedule_T_457 = or(_schedule_T_456, _schedule_T_451) node _schedule_T_458 = or(_schedule_T_457, _schedule_T_452) node _schedule_T_459 = or(_schedule_T_458, _schedule_T_453) node _schedule_T_460 = or(_schedule_T_459, _schedule_T_454) node _schedule_T_461 = or(_schedule_T_460, _schedule_T_455) wire _schedule_WIRE_46 : UInt<3> connect _schedule_WIRE_46, _schedule_T_461 connect _schedule_WIRE_39.opcode, _schedule_WIRE_46 connect _schedule_WIRE_38.bits, _schedule_WIRE_39 node _schedule_T_462 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_463 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_464 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_465 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_466 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_467 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_468 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_469 = or(_schedule_T_462, _schedule_T_463) node _schedule_T_470 = or(_schedule_T_469, _schedule_T_464) node _schedule_T_471 = or(_schedule_T_470, _schedule_T_465) node _schedule_T_472 = or(_schedule_T_471, _schedule_T_466) node _schedule_T_473 = or(_schedule_T_472, _schedule_T_467) node _schedule_T_474 = or(_schedule_T_473, _schedule_T_468) wire _schedule_WIRE_47 : UInt<1> connect _schedule_WIRE_47, _schedule_T_474 connect _schedule_WIRE_38.valid, _schedule_WIRE_47 connect schedule.c, _schedule_WIRE_38 wire _schedule_WIRE_48 : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}} wire _schedule_WIRE_49 : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>} node _schedule_T_475 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_476 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_477 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_478 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_479 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_480 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_481 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_482 = or(_schedule_T_475, _schedule_T_476) node _schedule_T_483 = or(_schedule_T_482, _schedule_T_477) node _schedule_T_484 = or(_schedule_T_483, _schedule_T_478) node _schedule_T_485 = or(_schedule_T_484, _schedule_T_479) node _schedule_T_486 = or(_schedule_T_485, _schedule_T_480) node _schedule_T_487 = or(_schedule_T_486, _schedule_T_481) wire _schedule_WIRE_50 : UInt<1> connect _schedule_WIRE_50, _schedule_T_487 connect _schedule_WIRE_49.clients, _schedule_WIRE_50 node _schedule_T_488 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_489 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_490 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_491 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_492 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_493 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_494 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_495 = or(_schedule_T_488, _schedule_T_489) node _schedule_T_496 = or(_schedule_T_495, _schedule_T_490) node _schedule_T_497 = or(_schedule_T_496, _schedule_T_491) node _schedule_T_498 = or(_schedule_T_497, _schedule_T_492) node _schedule_T_499 = or(_schedule_T_498, _schedule_T_493) node _schedule_T_500 = or(_schedule_T_499, _schedule_T_494) wire _schedule_WIRE_51 : UInt<10> connect _schedule_WIRE_51, _schedule_T_500 connect _schedule_WIRE_49.set, _schedule_WIRE_51 node _schedule_T_501 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_502 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_503 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_504 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_505 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_506 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_507 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_508 = or(_schedule_T_501, _schedule_T_502) node _schedule_T_509 = or(_schedule_T_508, _schedule_T_503) node _schedule_T_510 = or(_schedule_T_509, _schedule_T_504) node _schedule_T_511 = or(_schedule_T_510, _schedule_T_505) node _schedule_T_512 = or(_schedule_T_511, _schedule_T_506) node _schedule_T_513 = or(_schedule_T_512, _schedule_T_507) wire _schedule_WIRE_52 : UInt<13> connect _schedule_WIRE_52, _schedule_T_513 connect _schedule_WIRE_49.tag, _schedule_WIRE_52 node _schedule_T_514 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_515 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_516 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_517 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_518 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_519 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_520 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_521 = or(_schedule_T_514, _schedule_T_515) node _schedule_T_522 = or(_schedule_T_521, _schedule_T_516) node _schedule_T_523 = or(_schedule_T_522, _schedule_T_517) node _schedule_T_524 = or(_schedule_T_523, _schedule_T_518) node _schedule_T_525 = or(_schedule_T_524, _schedule_T_519) node _schedule_T_526 = or(_schedule_T_525, _schedule_T_520) wire _schedule_WIRE_53 : UInt<3> connect _schedule_WIRE_53, _schedule_T_526 connect _schedule_WIRE_49.param, _schedule_WIRE_53 connect _schedule_WIRE_48.bits, _schedule_WIRE_49 node _schedule_T_527 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_528 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_529 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_530 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_531 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_532 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_533 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_534 = or(_schedule_T_527, _schedule_T_528) node _schedule_T_535 = or(_schedule_T_534, _schedule_T_529) node _schedule_T_536 = or(_schedule_T_535, _schedule_T_530) node _schedule_T_537 = or(_schedule_T_536, _schedule_T_531) node _schedule_T_538 = or(_schedule_T_537, _schedule_T_532) node _schedule_T_539 = or(_schedule_T_538, _schedule_T_533) wire _schedule_WIRE_54 : UInt<1> connect _schedule_WIRE_54, _schedule_T_539 connect _schedule_WIRE_48.valid, _schedule_WIRE_54 connect schedule.b, _schedule_WIRE_48 wire _schedule_WIRE_55 : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}} wire _schedule_WIRE_56 : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>} node _schedule_T_540 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_541 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_542 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_543 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_544 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_545 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_546 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_547 = or(_schedule_T_540, _schedule_T_541) node _schedule_T_548 = or(_schedule_T_547, _schedule_T_542) node _schedule_T_549 = or(_schedule_T_548, _schedule_T_543) node _schedule_T_550 = or(_schedule_T_549, _schedule_T_544) node _schedule_T_551 = or(_schedule_T_550, _schedule_T_545) node _schedule_T_552 = or(_schedule_T_551, _schedule_T_546) wire _schedule_WIRE_57 : UInt<1> connect _schedule_WIRE_57, _schedule_T_552 connect _schedule_WIRE_56.block, _schedule_WIRE_57 node _schedule_T_553 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_554 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_555 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_556 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_557 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_558 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_559 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_560 = or(_schedule_T_553, _schedule_T_554) node _schedule_T_561 = or(_schedule_T_560, _schedule_T_555) node _schedule_T_562 = or(_schedule_T_561, _schedule_T_556) node _schedule_T_563 = or(_schedule_T_562, _schedule_T_557) node _schedule_T_564 = or(_schedule_T_563, _schedule_T_558) node _schedule_T_565 = or(_schedule_T_564, _schedule_T_559) wire _schedule_WIRE_58 : UInt<3> connect _schedule_WIRE_58, _schedule_T_565 connect _schedule_WIRE_56.source, _schedule_WIRE_58 node _schedule_T_566 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_567 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_568 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_569 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_570 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_571 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_572 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_573 = or(_schedule_T_566, _schedule_T_567) node _schedule_T_574 = or(_schedule_T_573, _schedule_T_568) node _schedule_T_575 = or(_schedule_T_574, _schedule_T_569) node _schedule_T_576 = or(_schedule_T_575, _schedule_T_570) node _schedule_T_577 = or(_schedule_T_576, _schedule_T_571) node _schedule_T_578 = or(_schedule_T_577, _schedule_T_572) wire _schedule_WIRE_59 : UInt<3> connect _schedule_WIRE_59, _schedule_T_578 connect _schedule_WIRE_56.param, _schedule_WIRE_59 node _schedule_T_579 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_580 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_581 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_582 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_583 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_584 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_585 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_586 = or(_schedule_T_579, _schedule_T_580) node _schedule_T_587 = or(_schedule_T_586, _schedule_T_581) node _schedule_T_588 = or(_schedule_T_587, _schedule_T_582) node _schedule_T_589 = or(_schedule_T_588, _schedule_T_583) node _schedule_T_590 = or(_schedule_T_589, _schedule_T_584) node _schedule_T_591 = or(_schedule_T_590, _schedule_T_585) wire _schedule_WIRE_60 : UInt<10> connect _schedule_WIRE_60, _schedule_T_591 connect _schedule_WIRE_56.set, _schedule_WIRE_60 node _schedule_T_592 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_593 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_594 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_595 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_596 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_597 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_598 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_599 = or(_schedule_T_592, _schedule_T_593) node _schedule_T_600 = or(_schedule_T_599, _schedule_T_594) node _schedule_T_601 = or(_schedule_T_600, _schedule_T_595) node _schedule_T_602 = or(_schedule_T_601, _schedule_T_596) node _schedule_T_603 = or(_schedule_T_602, _schedule_T_597) node _schedule_T_604 = or(_schedule_T_603, _schedule_T_598) wire _schedule_WIRE_61 : UInt<13> connect _schedule_WIRE_61, _schedule_T_604 connect _schedule_WIRE_56.tag, _schedule_WIRE_61 connect _schedule_WIRE_55.bits, _schedule_WIRE_56 node _schedule_T_605 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_606 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_607 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_608 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_609 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_610 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_611 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_612 = or(_schedule_T_605, _schedule_T_606) node _schedule_T_613 = or(_schedule_T_612, _schedule_T_607) node _schedule_T_614 = or(_schedule_T_613, _schedule_T_608) node _schedule_T_615 = or(_schedule_T_614, _schedule_T_609) node _schedule_T_616 = or(_schedule_T_615, _schedule_T_610) node _schedule_T_617 = or(_schedule_T_616, _schedule_T_611) wire _schedule_WIRE_62 : UInt<1> connect _schedule_WIRE_62, _schedule_T_617 connect _schedule_WIRE_55.valid, _schedule_WIRE_62 connect schedule.a, _schedule_WIRE_55 node _scheduleTag_T = bits(mshr_selectOH, 0, 0) node _scheduleTag_T_1 = bits(mshr_selectOH, 1, 1) node _scheduleTag_T_2 = bits(mshr_selectOH, 2, 2) node _scheduleTag_T_3 = bits(mshr_selectOH, 3, 3) node _scheduleTag_T_4 = bits(mshr_selectOH, 4, 4) node _scheduleTag_T_5 = bits(mshr_selectOH, 5, 5) node _scheduleTag_T_6 = bits(mshr_selectOH, 6, 6) node _scheduleTag_T_7 = mux(_scheduleTag_T, mshrs_0.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_8 = mux(_scheduleTag_T_1, mshrs_1.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_9 = mux(_scheduleTag_T_2, mshrs_2.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_10 = mux(_scheduleTag_T_3, mshrs_3.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_11 = mux(_scheduleTag_T_4, mshrs_4.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_12 = mux(_scheduleTag_T_5, mshrs_5.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_13 = mux(_scheduleTag_T_6, mshrs_6.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_14 = or(_scheduleTag_T_7, _scheduleTag_T_8) node _scheduleTag_T_15 = or(_scheduleTag_T_14, _scheduleTag_T_9) node _scheduleTag_T_16 = or(_scheduleTag_T_15, _scheduleTag_T_10) node _scheduleTag_T_17 = or(_scheduleTag_T_16, _scheduleTag_T_11) node _scheduleTag_T_18 = or(_scheduleTag_T_17, _scheduleTag_T_12) node _scheduleTag_T_19 = or(_scheduleTag_T_18, _scheduleTag_T_13) wire scheduleTag : UInt<13> connect scheduleTag, _scheduleTag_T_19 node _scheduleSet_T = bits(mshr_selectOH, 0, 0) node _scheduleSet_T_1 = bits(mshr_selectOH, 1, 1) node _scheduleSet_T_2 = bits(mshr_selectOH, 2, 2) node _scheduleSet_T_3 = bits(mshr_selectOH, 3, 3) node _scheduleSet_T_4 = bits(mshr_selectOH, 4, 4) node _scheduleSet_T_5 = bits(mshr_selectOH, 5, 5) node _scheduleSet_T_6 = bits(mshr_selectOH, 6, 6) node _scheduleSet_T_7 = mux(_scheduleSet_T, mshrs_0.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_8 = mux(_scheduleSet_T_1, mshrs_1.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_9 = mux(_scheduleSet_T_2, mshrs_2.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_10 = mux(_scheduleSet_T_3, mshrs_3.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_11 = mux(_scheduleSet_T_4, mshrs_4.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_12 = mux(_scheduleSet_T_5, mshrs_5.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_13 = mux(_scheduleSet_T_6, mshrs_6.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_14 = or(_scheduleSet_T_7, _scheduleSet_T_8) node _scheduleSet_T_15 = or(_scheduleSet_T_14, _scheduleSet_T_9) node _scheduleSet_T_16 = or(_scheduleSet_T_15, _scheduleSet_T_10) node _scheduleSet_T_17 = or(_scheduleSet_T_16, _scheduleSet_T_11) node _scheduleSet_T_18 = or(_scheduleSet_T_17, _scheduleSet_T_12) node _scheduleSet_T_19 = or(_scheduleSet_T_18, _scheduleSet_T_13) wire scheduleSet : UInt<10> connect scheduleSet, _scheduleSet_T_19 node _T_4 = orr(mshr_request) when _T_4 : node _robin_filter_T = shr(mshr_selectOH, 1) node _robin_filter_T_1 = or(mshr_selectOH, _robin_filter_T) node _robin_filter_T_2 = shr(_robin_filter_T_1, 2) node _robin_filter_T_3 = or(_robin_filter_T_1, _robin_filter_T_2) node _robin_filter_T_4 = shr(_robin_filter_T_3, 4) node _robin_filter_T_5 = or(_robin_filter_T_3, _robin_filter_T_4) node _robin_filter_T_6 = bits(_robin_filter_T_5, 6, 0) node _robin_filter_T_7 = not(_robin_filter_T_6) connect robin_filter, _robin_filter_T_7 connect schedule.a.bits.source, mshr_select node _schedule_c_bits_source_T = bits(schedule.c.bits.opcode, 1, 1) node _schedule_c_bits_source_T_1 = mux(_schedule_c_bits_source_T, mshr_select, UInt<1>(0h0)) connect schedule.c.bits.source, _schedule_c_bits_source_T_1 connect schedule.d.bits.sink, mshr_select connect sourceA.io.req.valid, schedule.a.valid connect sourceB.io.req.valid, schedule.b.valid connect sourceC.io.req.valid, schedule.c.valid connect sourceD.io.req.valid, schedule.d.valid connect sourceE.io.req.valid, schedule.e.valid connect sourceX.io.req.valid, schedule.x.valid connect sourceA.io.req.bits.block, schedule.a.bits.block connect sourceA.io.req.bits.source, schedule.a.bits.source connect sourceA.io.req.bits.param, schedule.a.bits.param connect sourceA.io.req.bits.set, schedule.a.bits.set connect sourceA.io.req.bits.tag, schedule.a.bits.tag connect sourceB.io.req.bits.clients, schedule.b.bits.clients connect sourceB.io.req.bits.set, schedule.b.bits.set connect sourceB.io.req.bits.tag, schedule.b.bits.tag connect sourceB.io.req.bits.param, schedule.b.bits.param connect sourceC.io.req.bits.dirty, schedule.c.bits.dirty connect sourceC.io.req.bits.way, schedule.c.bits.way connect sourceC.io.req.bits.set, schedule.c.bits.set connect sourceC.io.req.bits.tag, schedule.c.bits.tag connect sourceC.io.req.bits.source, schedule.c.bits.source connect sourceC.io.req.bits.param, schedule.c.bits.param connect sourceC.io.req.bits.opcode, schedule.c.bits.opcode connect sourceD.io.req.bits.bad, schedule.d.bits.bad connect sourceD.io.req.bits.way, schedule.d.bits.way connect sourceD.io.req.bits.sink, schedule.d.bits.sink connect sourceD.io.req.bits.set, schedule.d.bits.set connect sourceD.io.req.bits.put, schedule.d.bits.put connect sourceD.io.req.bits.offset, schedule.d.bits.offset connect sourceD.io.req.bits.tag, schedule.d.bits.tag connect sourceD.io.req.bits.source, schedule.d.bits.source connect sourceD.io.req.bits.size, schedule.d.bits.size connect sourceD.io.req.bits.param, schedule.d.bits.param connect sourceD.io.req.bits.opcode, schedule.d.bits.opcode connect sourceD.io.req.bits.control, schedule.d.bits.control connect sourceD.io.req.bits.prio[0], schedule.d.bits.prio[0] connect sourceD.io.req.bits.prio[1], schedule.d.bits.prio[1] connect sourceD.io.req.bits.prio[2], schedule.d.bits.prio[2] connect sourceE.io.req.bits.sink, schedule.e.bits.sink connect sourceX.io.req.bits.fail, schedule.x.bits.fail connect directory.io.write.valid, schedule.dir.valid connect directory.io.write.bits.data.tag, schedule.dir.bits.data.tag connect directory.io.write.bits.data.clients, schedule.dir.bits.data.clients connect directory.io.write.bits.data.state, schedule.dir.bits.data.state connect directory.io.write.bits.data.dirty, schedule.dir.bits.data.dirty connect directory.io.write.bits.way, schedule.dir.bits.way connect directory.io.write.bits.set, schedule.dir.bits.set node select_c = bits(mshr_selectOH, 6, 6) node select_bc = bits(mshr_selectOH, 5, 5) node _nestedwb_set_T = mux(select_c, mshrs_6.io.status.bits.set, mshrs_5.io.status.bits.set) connect nestedwb.set, _nestedwb_set_T node _nestedwb_tag_T = mux(select_c, mshrs_6.io.status.bits.tag, mshrs_5.io.status.bits.tag) connect nestedwb.tag, _nestedwb_tag_T node _nestedwb_b_toN_T = and(select_bc, mshrs_5.io.schedule.bits.dir.valid) node _nestedwb_b_toN_T_1 = eq(mshrs_5.io.schedule.bits.dir.bits.data.state, UInt<2>(0h0)) node _nestedwb_b_toN_T_2 = and(_nestedwb_b_toN_T, _nestedwb_b_toN_T_1) connect nestedwb.b_toN, _nestedwb_b_toN_T_2 node _nestedwb_b_toB_T = and(select_bc, mshrs_5.io.schedule.bits.dir.valid) node _nestedwb_b_toB_T_1 = eq(mshrs_5.io.schedule.bits.dir.bits.data.state, UInt<2>(0h1)) node _nestedwb_b_toB_T_2 = and(_nestedwb_b_toB_T, _nestedwb_b_toB_T_1) connect nestedwb.b_toB, _nestedwb_b_toB_T_2 node _nestedwb_b_clr_dirty_T = and(select_bc, mshrs_5.io.schedule.bits.dir.valid) connect nestedwb.b_clr_dirty, _nestedwb_b_clr_dirty_T node _nestedwb_c_set_dirty_T = and(select_c, mshrs_6.io.schedule.bits.dir.valid) node _nestedwb_c_set_dirty_T_1 = and(_nestedwb_c_set_dirty_T, mshrs_6.io.schedule.bits.dir.bits.data.dirty) connect nestedwb.c_set_dirty, _nestedwb_c_set_dirty_T_1 wire request : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}} node _request_valid_T = or(sinkA.io.req.valid, sinkX.io.req.valid) node _request_valid_T_1 = or(_request_valid_T, sinkC.io.req.valid) node _request_valid_T_2 = and(directory.io.ready, _request_valid_T_1) connect request.valid, _request_valid_T_2 node _request_bits_T = mux(sinkX.io.req.valid, sinkX.io.req.bits, sinkA.io.req.bits) node _request_bits_T_1 = mux(sinkC.io.req.valid, sinkC.io.req.bits, _request_bits_T) connect request.bits, _request_bits_T_1 node _sinkC_io_req_ready_T = and(directory.io.ready, request.ready) connect sinkC.io.req.ready, _sinkC_io_req_ready_T node _sinkX_io_req_ready_T = and(directory.io.ready, request.ready) node _sinkX_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0)) node _sinkX_io_req_ready_T_2 = and(_sinkX_io_req_ready_T, _sinkX_io_req_ready_T_1) connect sinkX.io.req.ready, _sinkX_io_req_ready_T_2 node _sinkA_io_req_ready_T = and(directory.io.ready, request.ready) node _sinkA_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0)) node _sinkA_io_req_ready_T_2 = and(_sinkA_io_req_ready_T, _sinkA_io_req_ready_T_1) node _sinkA_io_req_ready_T_3 = eq(sinkX.io.req.valid, UInt<1>(0h0)) node _sinkA_io_req_ready_T_4 = and(_sinkA_io_req_ready_T_2, _sinkA_io_req_ready_T_3) connect sinkA.io.req.ready, _sinkA_io_req_ready_T_4 node _setMatches_T = eq(mshrs_0.io.status.bits.set, request.bits.set) node _setMatches_T_1 = and(mshrs_0.io.status.valid, _setMatches_T) node _setMatches_T_2 = eq(mshrs_1.io.status.bits.set, request.bits.set) node _setMatches_T_3 = and(mshrs_1.io.status.valid, _setMatches_T_2) node _setMatches_T_4 = eq(mshrs_2.io.status.bits.set, request.bits.set) node _setMatches_T_5 = and(mshrs_2.io.status.valid, _setMatches_T_4) node _setMatches_T_6 = eq(mshrs_3.io.status.bits.set, request.bits.set) node _setMatches_T_7 = and(mshrs_3.io.status.valid, _setMatches_T_6) node _setMatches_T_8 = eq(mshrs_4.io.status.bits.set, request.bits.set) node _setMatches_T_9 = and(mshrs_4.io.status.valid, _setMatches_T_8) node _setMatches_T_10 = eq(mshrs_5.io.status.bits.set, request.bits.set) node _setMatches_T_11 = and(mshrs_5.io.status.valid, _setMatches_T_10) node _setMatches_T_12 = eq(mshrs_6.io.status.bits.set, request.bits.set) node _setMatches_T_13 = and(mshrs_6.io.status.valid, _setMatches_T_12) node setMatches_lo_hi = cat(_setMatches_T_5, _setMatches_T_3) node setMatches_lo = cat(setMatches_lo_hi, _setMatches_T_1) node setMatches_hi_lo = cat(_setMatches_T_9, _setMatches_T_7) node setMatches_hi_hi = cat(_setMatches_T_13, _setMatches_T_11) node setMatches_hi = cat(setMatches_hi_hi, setMatches_hi_lo) node setMatches = cat(setMatches_hi, setMatches_lo) node _alloc_T = orr(setMatches) node alloc = eq(_alloc_T, UInt<1>(0h0)) node _blockB_T = bits(setMatches, 0, 0) node _blockB_T_1 = bits(setMatches, 1, 1) node _blockB_T_2 = bits(setMatches, 2, 2) node _blockB_T_3 = bits(setMatches, 3, 3) node _blockB_T_4 = bits(setMatches, 4, 4) node _blockB_T_5 = bits(setMatches, 5, 5) node _blockB_T_6 = bits(setMatches, 6, 6) node _blockB_T_7 = mux(_blockB_T, mshrs_0.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_8 = mux(_blockB_T_1, mshrs_1.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_9 = mux(_blockB_T_2, mshrs_2.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_10 = mux(_blockB_T_3, mshrs_3.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_11 = mux(_blockB_T_4, mshrs_4.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_12 = mux(_blockB_T_5, mshrs_5.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_13 = mux(_blockB_T_6, mshrs_6.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_14 = or(_blockB_T_7, _blockB_T_8) node _blockB_T_15 = or(_blockB_T_14, _blockB_T_9) node _blockB_T_16 = or(_blockB_T_15, _blockB_T_10) node _blockB_T_17 = or(_blockB_T_16, _blockB_T_11) node _blockB_T_18 = or(_blockB_T_17, _blockB_T_12) node _blockB_T_19 = or(_blockB_T_18, _blockB_T_13) wire _blockB_WIRE : UInt<1> connect _blockB_WIRE, _blockB_T_19 node blockB = and(_blockB_WIRE, request.bits.prio[1]) node _blockC_T = bits(setMatches, 0, 0) node _blockC_T_1 = bits(setMatches, 1, 1) node _blockC_T_2 = bits(setMatches, 2, 2) node _blockC_T_3 = bits(setMatches, 3, 3) node _blockC_T_4 = bits(setMatches, 4, 4) node _blockC_T_5 = bits(setMatches, 5, 5) node _blockC_T_6 = bits(setMatches, 6, 6) node _blockC_T_7 = mux(_blockC_T, mshrs_0.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_8 = mux(_blockC_T_1, mshrs_1.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_9 = mux(_blockC_T_2, mshrs_2.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_10 = mux(_blockC_T_3, mshrs_3.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_11 = mux(_blockC_T_4, mshrs_4.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_12 = mux(_blockC_T_5, mshrs_5.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_13 = mux(_blockC_T_6, mshrs_6.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_14 = or(_blockC_T_7, _blockC_T_8) node _blockC_T_15 = or(_blockC_T_14, _blockC_T_9) node _blockC_T_16 = or(_blockC_T_15, _blockC_T_10) node _blockC_T_17 = or(_blockC_T_16, _blockC_T_11) node _blockC_T_18 = or(_blockC_T_17, _blockC_T_12) node _blockC_T_19 = or(_blockC_T_18, _blockC_T_13) wire _blockC_WIRE : UInt<1> connect _blockC_WIRE, _blockC_T_19 node blockC = and(_blockC_WIRE, request.bits.prio[2]) node _nestB_T = bits(setMatches, 0, 0) node _nestB_T_1 = bits(setMatches, 1, 1) node _nestB_T_2 = bits(setMatches, 2, 2) node _nestB_T_3 = bits(setMatches, 3, 3) node _nestB_T_4 = bits(setMatches, 4, 4) node _nestB_T_5 = bits(setMatches, 5, 5) node _nestB_T_6 = bits(setMatches, 6, 6) node _nestB_T_7 = mux(_nestB_T, mshrs_0.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_8 = mux(_nestB_T_1, mshrs_1.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_9 = mux(_nestB_T_2, mshrs_2.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_10 = mux(_nestB_T_3, mshrs_3.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_11 = mux(_nestB_T_4, mshrs_4.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_12 = mux(_nestB_T_5, mshrs_5.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_13 = mux(_nestB_T_6, mshrs_6.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_14 = or(_nestB_T_7, _nestB_T_8) node _nestB_T_15 = or(_nestB_T_14, _nestB_T_9) node _nestB_T_16 = or(_nestB_T_15, _nestB_T_10) node _nestB_T_17 = or(_nestB_T_16, _nestB_T_11) node _nestB_T_18 = or(_nestB_T_17, _nestB_T_12) node _nestB_T_19 = or(_nestB_T_18, _nestB_T_13) wire _nestB_WIRE : UInt<1> connect _nestB_WIRE, _nestB_T_19 node nestB = and(_nestB_WIRE, request.bits.prio[1]) node _nestC_T = bits(setMatches, 0, 0) node _nestC_T_1 = bits(setMatches, 1, 1) node _nestC_T_2 = bits(setMatches, 2, 2) node _nestC_T_3 = bits(setMatches, 3, 3) node _nestC_T_4 = bits(setMatches, 4, 4) node _nestC_T_5 = bits(setMatches, 5, 5) node _nestC_T_6 = bits(setMatches, 6, 6) node _nestC_T_7 = mux(_nestC_T, mshrs_0.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_8 = mux(_nestC_T_1, mshrs_1.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_9 = mux(_nestC_T_2, mshrs_2.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_10 = mux(_nestC_T_3, mshrs_3.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_11 = mux(_nestC_T_4, mshrs_4.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_12 = mux(_nestC_T_5, mshrs_5.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_13 = mux(_nestC_T_6, mshrs_6.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_14 = or(_nestC_T_7, _nestC_T_8) node _nestC_T_15 = or(_nestC_T_14, _nestC_T_9) node _nestC_T_16 = or(_nestC_T_15, _nestC_T_10) node _nestC_T_17 = or(_nestC_T_16, _nestC_T_11) node _nestC_T_18 = or(_nestC_T_17, _nestC_T_12) node _nestC_T_19 = or(_nestC_T_18, _nestC_T_13) wire _nestC_WIRE : UInt<1> connect _nestC_WIRE, _nestC_T_19 node nestC = and(_nestC_WIRE, request.bits.prio[2]) node _prioFilter_T = eq(request.bits.prio[0], UInt<1>(0h0)) node _prioFilter_T_1 = not(UInt<5>(0h0)) node prioFilter_hi = cat(request.bits.prio[2], _prioFilter_T) node prioFilter = cat(prioFilter_hi, _prioFilter_T_1) node lowerMatches = and(setMatches, prioFilter) node _queue_T = orr(lowerMatches) node _queue_T_1 = eq(nestB, UInt<1>(0h0)) node _queue_T_2 = and(_queue_T, _queue_T_1) node _queue_T_3 = eq(nestC, UInt<1>(0h0)) node _queue_T_4 = and(_queue_T_2, _queue_T_3) node _queue_T_5 = eq(blockB, UInt<1>(0h0)) node _queue_T_6 = and(_queue_T_4, _queue_T_5) node _queue_T_7 = eq(blockC, UInt<1>(0h0)) node queue = and(_queue_T_6, _queue_T_7) node _T_5 = and(request.valid, blockC) node _T_6 = and(request.valid, nestC) node _T_7 = and(request.valid, queue) node _lowerMatches1_T = bits(lowerMatches, 6, 6) node _lowerMatches1_T_1 = shl(UInt<1>(0h1), 6) node _lowerMatches1_T_2 = bits(lowerMatches, 5, 5) node _lowerMatches1_T_3 = shl(UInt<1>(0h1), 5) node _lowerMatches1_T_4 = mux(_lowerMatches1_T_2, _lowerMatches1_T_3, lowerMatches) node lowerMatches1 = mux(_lowerMatches1_T, _lowerMatches1_T_1, _lowerMatches1_T_4) node selected_requests_hi = cat(mshr_selectOH, mshr_selectOH) node _selected_requests_T = cat(selected_requests_hi, mshr_selectOH) node selected_requests = and(_selected_requests_T, requests.io.valid) node _a_pop_T = bits(selected_requests, 6, 0) node a_pop = orr(_a_pop_T) node _b_pop_T = bits(selected_requests, 13, 7) node b_pop = orr(_b_pop_T) node _c_pop_T = bits(selected_requests, 20, 14) node c_pop = orr(_c_pop_T) node _bypassMatches_T = and(mshr_selectOH, lowerMatches1) node _bypassMatches_T_1 = orr(_bypassMatches_T) node _bypassMatches_T_2 = or(c_pop, request.bits.prio[2]) node _bypassMatches_T_3 = eq(c_pop, UInt<1>(0h0)) node _bypassMatches_T_4 = or(b_pop, request.bits.prio[1]) node _bypassMatches_T_5 = eq(b_pop, UInt<1>(0h0)) node _bypassMatches_T_6 = eq(a_pop, UInt<1>(0h0)) node _bypassMatches_T_7 = mux(_bypassMatches_T_4, _bypassMatches_T_5, _bypassMatches_T_6) node _bypassMatches_T_8 = mux(_bypassMatches_T_2, _bypassMatches_T_3, _bypassMatches_T_7) node bypassMatches = and(_bypassMatches_T_1, _bypassMatches_T_8) node _may_pop_T = or(a_pop, b_pop) node may_pop = or(_may_pop_T, c_pop) node _bypass_T = and(request.valid, queue) node bypass = and(_bypass_T, bypassMatches) node _will_reload_T = or(may_pop, bypass) node will_reload = and(schedule.reload, _will_reload_T) node _will_pop_T = and(schedule.reload, may_pop) node _will_pop_T_1 = eq(bypass, UInt<1>(0h0)) node will_pop = and(_will_pop_T, _will_pop_T_1) node _T_8 = orr(mshr_selectOH) node _T_9 = and(_T_8, bypass) node _T_10 = orr(mshr_selectOH) node _T_11 = and(_T_10, will_reload) node _T_12 = orr(mshr_selectOH) node _T_13 = and(_T_12, will_pop) node sel = bits(mshr_selectOH, 0, 0) connect mshrs_0.io.schedule.ready, sel node a_pop_1 = bits(requests.io.valid, 0, 0) node b_pop_1 = bits(requests.io.valid, 7, 7) node c_pop_1 = bits(requests.io.valid, 14, 14) node _bypassMatches_T_9 = bits(lowerMatches1, 0, 0) node _bypassMatches_T_10 = or(c_pop_1, request.bits.prio[2]) node _bypassMatches_T_11 = eq(c_pop_1, UInt<1>(0h0)) node _bypassMatches_T_12 = or(b_pop_1, request.bits.prio[1]) node _bypassMatches_T_13 = eq(b_pop_1, UInt<1>(0h0)) node _bypassMatches_T_14 = eq(a_pop_1, UInt<1>(0h0)) node _bypassMatches_T_15 = mux(_bypassMatches_T_12, _bypassMatches_T_13, _bypassMatches_T_14) node _bypassMatches_T_16 = mux(_bypassMatches_T_10, _bypassMatches_T_11, _bypassMatches_T_15) node bypassMatches_1 = and(_bypassMatches_T_9, _bypassMatches_T_16) node _may_pop_T_1 = or(a_pop_1, b_pop_1) node may_pop_1 = or(_may_pop_T_1, c_pop_1) node _bypass_T_1 = and(request.valid, queue) node bypass_1 = and(_bypass_T_1, bypassMatches_1) node _will_reload_T_1 = or(may_pop_1, bypass_1) node will_reload_1 = and(mshrs_0.io.schedule.bits.reload, _will_reload_T_1) wire _view__WIRE : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE.put, request.bits.put connect _view__WIRE.offset, request.bits.offset connect _view__WIRE.tag, request.bits.tag connect _view__WIRE.source, request.bits.source connect _view__WIRE.size, request.bits.size connect _view__WIRE.param, request.bits.param connect _view__WIRE.opcode, request.bits.opcode connect _view__WIRE.control, request.bits.control connect _view__WIRE.prio, request.bits.prio node _view__T = mux(bypass_1, _view__WIRE, requests.io.data) connect mshrs_0.io.allocate.bits.put, _view__T.put connect mshrs_0.io.allocate.bits.offset, _view__T.offset connect mshrs_0.io.allocate.bits.tag, _view__T.tag connect mshrs_0.io.allocate.bits.source, _view__T.source connect mshrs_0.io.allocate.bits.size, _view__T.size connect mshrs_0.io.allocate.bits.param, _view__T.param connect mshrs_0.io.allocate.bits.opcode, _view__T.opcode connect mshrs_0.io.allocate.bits.control, _view__T.control connect mshrs_0.io.allocate.bits.prio[0], _view__T.prio[0] connect mshrs_0.io.allocate.bits.prio[1], _view__T.prio[1] connect mshrs_0.io.allocate.bits.prio[2], _view__T.prio[2] connect mshrs_0.io.allocate.bits.set, mshrs_0.io.status.bits.set node _mshrs_0_io_allocate_bits_repeat_T = eq(mshrs_0.io.allocate.bits.tag, mshrs_0.io.status.bits.tag) connect mshrs_0.io.allocate.bits.repeat, _mshrs_0_io_allocate_bits_repeat_T node _mshrs_0_io_allocate_valid_T = and(sel, will_reload_1) connect mshrs_0.io.allocate.valid, _mshrs_0_io_allocate_valid_T node sel_1 = bits(mshr_selectOH, 1, 1) connect mshrs_1.io.schedule.ready, sel_1 node a_pop_2 = bits(requests.io.valid, 1, 1) node b_pop_2 = bits(requests.io.valid, 8, 8) node c_pop_2 = bits(requests.io.valid, 15, 15) node _bypassMatches_T_17 = bits(lowerMatches1, 1, 1) node _bypassMatches_T_18 = or(c_pop_2, request.bits.prio[2]) node _bypassMatches_T_19 = eq(c_pop_2, UInt<1>(0h0)) node _bypassMatches_T_20 = or(b_pop_2, request.bits.prio[1]) node _bypassMatches_T_21 = eq(b_pop_2, UInt<1>(0h0)) node _bypassMatches_T_22 = eq(a_pop_2, UInt<1>(0h0)) node _bypassMatches_T_23 = mux(_bypassMatches_T_20, _bypassMatches_T_21, _bypassMatches_T_22) node _bypassMatches_T_24 = mux(_bypassMatches_T_18, _bypassMatches_T_19, _bypassMatches_T_23) node bypassMatches_2 = and(_bypassMatches_T_17, _bypassMatches_T_24) node _may_pop_T_2 = or(a_pop_2, b_pop_2) node may_pop_2 = or(_may_pop_T_2, c_pop_2) node _bypass_T_2 = and(request.valid, queue) node bypass_2 = and(_bypass_T_2, bypassMatches_2) node _will_reload_T_2 = or(may_pop_2, bypass_2) node will_reload_2 = and(mshrs_1.io.schedule.bits.reload, _will_reload_T_2) wire _view__WIRE_1 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_1.put, request.bits.put connect _view__WIRE_1.offset, request.bits.offset connect _view__WIRE_1.tag, request.bits.tag connect _view__WIRE_1.source, request.bits.source connect _view__WIRE_1.size, request.bits.size connect _view__WIRE_1.param, request.bits.param connect _view__WIRE_1.opcode, request.bits.opcode connect _view__WIRE_1.control, request.bits.control connect _view__WIRE_1.prio, request.bits.prio node _view__T_1 = mux(bypass_2, _view__WIRE_1, requests.io.data) connect mshrs_1.io.allocate.bits.put, _view__T_1.put connect mshrs_1.io.allocate.bits.offset, _view__T_1.offset connect mshrs_1.io.allocate.bits.tag, _view__T_1.tag connect mshrs_1.io.allocate.bits.source, _view__T_1.source connect mshrs_1.io.allocate.bits.size, _view__T_1.size connect mshrs_1.io.allocate.bits.param, _view__T_1.param connect mshrs_1.io.allocate.bits.opcode, _view__T_1.opcode connect mshrs_1.io.allocate.bits.control, _view__T_1.control connect mshrs_1.io.allocate.bits.prio[0], _view__T_1.prio[0] connect mshrs_1.io.allocate.bits.prio[1], _view__T_1.prio[1] connect mshrs_1.io.allocate.bits.prio[2], _view__T_1.prio[2] connect mshrs_1.io.allocate.bits.set, mshrs_1.io.status.bits.set node _mshrs_1_io_allocate_bits_repeat_T = eq(mshrs_1.io.allocate.bits.tag, mshrs_1.io.status.bits.tag) connect mshrs_1.io.allocate.bits.repeat, _mshrs_1_io_allocate_bits_repeat_T node _mshrs_1_io_allocate_valid_T = and(sel_1, will_reload_2) connect mshrs_1.io.allocate.valid, _mshrs_1_io_allocate_valid_T node sel_2 = bits(mshr_selectOH, 2, 2) connect mshrs_2.io.schedule.ready, sel_2 node a_pop_3 = bits(requests.io.valid, 2, 2) node b_pop_3 = bits(requests.io.valid, 9, 9) node c_pop_3 = bits(requests.io.valid, 16, 16) node _bypassMatches_T_25 = bits(lowerMatches1, 2, 2) node _bypassMatches_T_26 = or(c_pop_3, request.bits.prio[2]) node _bypassMatches_T_27 = eq(c_pop_3, UInt<1>(0h0)) node _bypassMatches_T_28 = or(b_pop_3, request.bits.prio[1]) node _bypassMatches_T_29 = eq(b_pop_3, UInt<1>(0h0)) node _bypassMatches_T_30 = eq(a_pop_3, UInt<1>(0h0)) node _bypassMatches_T_31 = mux(_bypassMatches_T_28, _bypassMatches_T_29, _bypassMatches_T_30) node _bypassMatches_T_32 = mux(_bypassMatches_T_26, _bypassMatches_T_27, _bypassMatches_T_31) node bypassMatches_3 = and(_bypassMatches_T_25, _bypassMatches_T_32) node _may_pop_T_3 = or(a_pop_3, b_pop_3) node may_pop_3 = or(_may_pop_T_3, c_pop_3) node _bypass_T_3 = and(request.valid, queue) node bypass_3 = and(_bypass_T_3, bypassMatches_3) node _will_reload_T_3 = or(may_pop_3, bypass_3) node will_reload_3 = and(mshrs_2.io.schedule.bits.reload, _will_reload_T_3) wire _view__WIRE_2 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_2.put, request.bits.put connect _view__WIRE_2.offset, request.bits.offset connect _view__WIRE_2.tag, request.bits.tag connect _view__WIRE_2.source, request.bits.source connect _view__WIRE_2.size, request.bits.size connect _view__WIRE_2.param, request.bits.param connect _view__WIRE_2.opcode, request.bits.opcode connect _view__WIRE_2.control, request.bits.control connect _view__WIRE_2.prio, request.bits.prio node _view__T_2 = mux(bypass_3, _view__WIRE_2, requests.io.data) connect mshrs_2.io.allocate.bits.put, _view__T_2.put connect mshrs_2.io.allocate.bits.offset, _view__T_2.offset connect mshrs_2.io.allocate.bits.tag, _view__T_2.tag connect mshrs_2.io.allocate.bits.source, _view__T_2.source connect mshrs_2.io.allocate.bits.size, _view__T_2.size connect mshrs_2.io.allocate.bits.param, _view__T_2.param connect mshrs_2.io.allocate.bits.opcode, _view__T_2.opcode connect mshrs_2.io.allocate.bits.control, _view__T_2.control connect mshrs_2.io.allocate.bits.prio[0], _view__T_2.prio[0] connect mshrs_2.io.allocate.bits.prio[1], _view__T_2.prio[1] connect mshrs_2.io.allocate.bits.prio[2], _view__T_2.prio[2] connect mshrs_2.io.allocate.bits.set, mshrs_2.io.status.bits.set node _mshrs_2_io_allocate_bits_repeat_T = eq(mshrs_2.io.allocate.bits.tag, mshrs_2.io.status.bits.tag) connect mshrs_2.io.allocate.bits.repeat, _mshrs_2_io_allocate_bits_repeat_T node _mshrs_2_io_allocate_valid_T = and(sel_2, will_reload_3) connect mshrs_2.io.allocate.valid, _mshrs_2_io_allocate_valid_T node sel_3 = bits(mshr_selectOH, 3, 3) connect mshrs_3.io.schedule.ready, sel_3 node a_pop_4 = bits(requests.io.valid, 3, 3) node b_pop_4 = bits(requests.io.valid, 10, 10) node c_pop_4 = bits(requests.io.valid, 17, 17) node _bypassMatches_T_33 = bits(lowerMatches1, 3, 3) node _bypassMatches_T_34 = or(c_pop_4, request.bits.prio[2]) node _bypassMatches_T_35 = eq(c_pop_4, UInt<1>(0h0)) node _bypassMatches_T_36 = or(b_pop_4, request.bits.prio[1]) node _bypassMatches_T_37 = eq(b_pop_4, UInt<1>(0h0)) node _bypassMatches_T_38 = eq(a_pop_4, UInt<1>(0h0)) node _bypassMatches_T_39 = mux(_bypassMatches_T_36, _bypassMatches_T_37, _bypassMatches_T_38) node _bypassMatches_T_40 = mux(_bypassMatches_T_34, _bypassMatches_T_35, _bypassMatches_T_39) node bypassMatches_4 = and(_bypassMatches_T_33, _bypassMatches_T_40) node _may_pop_T_4 = or(a_pop_4, b_pop_4) node may_pop_4 = or(_may_pop_T_4, c_pop_4) node _bypass_T_4 = and(request.valid, queue) node bypass_4 = and(_bypass_T_4, bypassMatches_4) node _will_reload_T_4 = or(may_pop_4, bypass_4) node will_reload_4 = and(mshrs_3.io.schedule.bits.reload, _will_reload_T_4) wire _view__WIRE_3 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_3.put, request.bits.put connect _view__WIRE_3.offset, request.bits.offset connect _view__WIRE_3.tag, request.bits.tag connect _view__WIRE_3.source, request.bits.source connect _view__WIRE_3.size, request.bits.size connect _view__WIRE_3.param, request.bits.param connect _view__WIRE_3.opcode, request.bits.opcode connect _view__WIRE_3.control, request.bits.control connect _view__WIRE_3.prio, request.bits.prio node _view__T_3 = mux(bypass_4, _view__WIRE_3, requests.io.data) connect mshrs_3.io.allocate.bits.put, _view__T_3.put connect mshrs_3.io.allocate.bits.offset, _view__T_3.offset connect mshrs_3.io.allocate.bits.tag, _view__T_3.tag connect mshrs_3.io.allocate.bits.source, _view__T_3.source connect mshrs_3.io.allocate.bits.size, _view__T_3.size connect mshrs_3.io.allocate.bits.param, _view__T_3.param connect mshrs_3.io.allocate.bits.opcode, _view__T_3.opcode connect mshrs_3.io.allocate.bits.control, _view__T_3.control connect mshrs_3.io.allocate.bits.prio[0], _view__T_3.prio[0] connect mshrs_3.io.allocate.bits.prio[1], _view__T_3.prio[1] connect mshrs_3.io.allocate.bits.prio[2], _view__T_3.prio[2] connect mshrs_3.io.allocate.bits.set, mshrs_3.io.status.bits.set node _mshrs_3_io_allocate_bits_repeat_T = eq(mshrs_3.io.allocate.bits.tag, mshrs_3.io.status.bits.tag) connect mshrs_3.io.allocate.bits.repeat, _mshrs_3_io_allocate_bits_repeat_T node _mshrs_3_io_allocate_valid_T = and(sel_3, will_reload_4) connect mshrs_3.io.allocate.valid, _mshrs_3_io_allocate_valid_T node sel_4 = bits(mshr_selectOH, 4, 4) connect mshrs_4.io.schedule.ready, sel_4 node a_pop_5 = bits(requests.io.valid, 4, 4) node b_pop_5 = bits(requests.io.valid, 11, 11) node c_pop_5 = bits(requests.io.valid, 18, 18) node _bypassMatches_T_41 = bits(lowerMatches1, 4, 4) node _bypassMatches_T_42 = or(c_pop_5, request.bits.prio[2]) node _bypassMatches_T_43 = eq(c_pop_5, UInt<1>(0h0)) node _bypassMatches_T_44 = or(b_pop_5, request.bits.prio[1]) node _bypassMatches_T_45 = eq(b_pop_5, UInt<1>(0h0)) node _bypassMatches_T_46 = eq(a_pop_5, UInt<1>(0h0)) node _bypassMatches_T_47 = mux(_bypassMatches_T_44, _bypassMatches_T_45, _bypassMatches_T_46) node _bypassMatches_T_48 = mux(_bypassMatches_T_42, _bypassMatches_T_43, _bypassMatches_T_47) node bypassMatches_5 = and(_bypassMatches_T_41, _bypassMatches_T_48) node _may_pop_T_5 = or(a_pop_5, b_pop_5) node may_pop_5 = or(_may_pop_T_5, c_pop_5) node _bypass_T_5 = and(request.valid, queue) node bypass_5 = and(_bypass_T_5, bypassMatches_5) node _will_reload_T_5 = or(may_pop_5, bypass_5) node will_reload_5 = and(mshrs_4.io.schedule.bits.reload, _will_reload_T_5) wire _view__WIRE_4 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_4.put, request.bits.put connect _view__WIRE_4.offset, request.bits.offset connect _view__WIRE_4.tag, request.bits.tag connect _view__WIRE_4.source, request.bits.source connect _view__WIRE_4.size, request.bits.size connect _view__WIRE_4.param, request.bits.param connect _view__WIRE_4.opcode, request.bits.opcode connect _view__WIRE_4.control, request.bits.control connect _view__WIRE_4.prio, request.bits.prio node _view__T_4 = mux(bypass_5, _view__WIRE_4, requests.io.data) connect mshrs_4.io.allocate.bits.put, _view__T_4.put connect mshrs_4.io.allocate.bits.offset, _view__T_4.offset connect mshrs_4.io.allocate.bits.tag, _view__T_4.tag connect mshrs_4.io.allocate.bits.source, _view__T_4.source connect mshrs_4.io.allocate.bits.size, _view__T_4.size connect mshrs_4.io.allocate.bits.param, _view__T_4.param connect mshrs_4.io.allocate.bits.opcode, _view__T_4.opcode connect mshrs_4.io.allocate.bits.control, _view__T_4.control connect mshrs_4.io.allocate.bits.prio[0], _view__T_4.prio[0] connect mshrs_4.io.allocate.bits.prio[1], _view__T_4.prio[1] connect mshrs_4.io.allocate.bits.prio[2], _view__T_4.prio[2] connect mshrs_4.io.allocate.bits.set, mshrs_4.io.status.bits.set node _mshrs_4_io_allocate_bits_repeat_T = eq(mshrs_4.io.allocate.bits.tag, mshrs_4.io.status.bits.tag) connect mshrs_4.io.allocate.bits.repeat, _mshrs_4_io_allocate_bits_repeat_T node _mshrs_4_io_allocate_valid_T = and(sel_4, will_reload_5) connect mshrs_4.io.allocate.valid, _mshrs_4_io_allocate_valid_T node sel_5 = bits(mshr_selectOH, 5, 5) connect mshrs_5.io.schedule.ready, sel_5 node a_pop_6 = bits(requests.io.valid, 5, 5) node b_pop_6 = bits(requests.io.valid, 12, 12) node c_pop_6 = bits(requests.io.valid, 19, 19) node _bypassMatches_T_49 = bits(lowerMatches1, 5, 5) node _bypassMatches_T_50 = or(c_pop_6, request.bits.prio[2]) node _bypassMatches_T_51 = eq(c_pop_6, UInt<1>(0h0)) node _bypassMatches_T_52 = or(b_pop_6, request.bits.prio[1]) node _bypassMatches_T_53 = eq(b_pop_6, UInt<1>(0h0)) node _bypassMatches_T_54 = eq(a_pop_6, UInt<1>(0h0)) node _bypassMatches_T_55 = mux(_bypassMatches_T_52, _bypassMatches_T_53, _bypassMatches_T_54) node _bypassMatches_T_56 = mux(_bypassMatches_T_50, _bypassMatches_T_51, _bypassMatches_T_55) node bypassMatches_6 = and(_bypassMatches_T_49, _bypassMatches_T_56) node _may_pop_T_6 = or(a_pop_6, b_pop_6) node may_pop_6 = or(_may_pop_T_6, c_pop_6) node _bypass_T_6 = and(request.valid, queue) node bypass_6 = and(_bypass_T_6, bypassMatches_6) node _will_reload_T_6 = or(may_pop_6, bypass_6) node will_reload_6 = and(mshrs_5.io.schedule.bits.reload, _will_reload_T_6) wire _view__WIRE_5 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_5.put, request.bits.put connect _view__WIRE_5.offset, request.bits.offset connect _view__WIRE_5.tag, request.bits.tag connect _view__WIRE_5.source, request.bits.source connect _view__WIRE_5.size, request.bits.size connect _view__WIRE_5.param, request.bits.param connect _view__WIRE_5.opcode, request.bits.opcode connect _view__WIRE_5.control, request.bits.control connect _view__WIRE_5.prio, request.bits.prio node _view__T_5 = mux(bypass_6, _view__WIRE_5, requests.io.data) connect mshrs_5.io.allocate.bits.put, _view__T_5.put connect mshrs_5.io.allocate.bits.offset, _view__T_5.offset connect mshrs_5.io.allocate.bits.tag, _view__T_5.tag connect mshrs_5.io.allocate.bits.source, _view__T_5.source connect mshrs_5.io.allocate.bits.size, _view__T_5.size connect mshrs_5.io.allocate.bits.param, _view__T_5.param connect mshrs_5.io.allocate.bits.opcode, _view__T_5.opcode connect mshrs_5.io.allocate.bits.control, _view__T_5.control connect mshrs_5.io.allocate.bits.prio[0], _view__T_5.prio[0] connect mshrs_5.io.allocate.bits.prio[1], _view__T_5.prio[1] connect mshrs_5.io.allocate.bits.prio[2], _view__T_5.prio[2] connect mshrs_5.io.allocate.bits.set, mshrs_5.io.status.bits.set node _mshrs_5_io_allocate_bits_repeat_T = eq(mshrs_5.io.allocate.bits.tag, mshrs_5.io.status.bits.tag) connect mshrs_5.io.allocate.bits.repeat, _mshrs_5_io_allocate_bits_repeat_T node _mshrs_5_io_allocate_valid_T = and(sel_5, will_reload_6) connect mshrs_5.io.allocate.valid, _mshrs_5_io_allocate_valid_T node sel_6 = bits(mshr_selectOH, 6, 6) connect mshrs_6.io.schedule.ready, sel_6 node a_pop_7 = bits(requests.io.valid, 6, 6) node b_pop_7 = bits(requests.io.valid, 13, 13) node c_pop_7 = bits(requests.io.valid, 20, 20) node _bypassMatches_T_57 = bits(lowerMatches1, 6, 6) node _bypassMatches_T_58 = or(c_pop_7, request.bits.prio[2]) node _bypassMatches_T_59 = eq(c_pop_7, UInt<1>(0h0)) node _bypassMatches_T_60 = or(b_pop_7, request.bits.prio[1]) node _bypassMatches_T_61 = eq(b_pop_7, UInt<1>(0h0)) node _bypassMatches_T_62 = eq(a_pop_7, UInt<1>(0h0)) node _bypassMatches_T_63 = mux(_bypassMatches_T_60, _bypassMatches_T_61, _bypassMatches_T_62) node _bypassMatches_T_64 = mux(_bypassMatches_T_58, _bypassMatches_T_59, _bypassMatches_T_63) node bypassMatches_7 = and(_bypassMatches_T_57, _bypassMatches_T_64) node _may_pop_T_7 = or(a_pop_7, b_pop_7) node may_pop_7 = or(_may_pop_T_7, c_pop_7) node _bypass_T_7 = and(request.valid, queue) node bypass_7 = and(_bypass_T_7, bypassMatches_7) node _will_reload_T_7 = or(may_pop_7, bypass_7) node will_reload_7 = and(mshrs_6.io.schedule.bits.reload, _will_reload_T_7) wire _view__WIRE_6 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_6.put, request.bits.put connect _view__WIRE_6.offset, request.bits.offset connect _view__WIRE_6.tag, request.bits.tag connect _view__WIRE_6.source, request.bits.source connect _view__WIRE_6.size, request.bits.size connect _view__WIRE_6.param, request.bits.param connect _view__WIRE_6.opcode, request.bits.opcode connect _view__WIRE_6.control, request.bits.control connect _view__WIRE_6.prio, request.bits.prio node _view__T_6 = mux(bypass_7, _view__WIRE_6, requests.io.data) connect mshrs_6.io.allocate.bits.put, _view__T_6.put connect mshrs_6.io.allocate.bits.offset, _view__T_6.offset connect mshrs_6.io.allocate.bits.tag, _view__T_6.tag connect mshrs_6.io.allocate.bits.source, _view__T_6.source connect mshrs_6.io.allocate.bits.size, _view__T_6.size connect mshrs_6.io.allocate.bits.param, _view__T_6.param connect mshrs_6.io.allocate.bits.opcode, _view__T_6.opcode connect mshrs_6.io.allocate.bits.control, _view__T_6.control connect mshrs_6.io.allocate.bits.prio[0], _view__T_6.prio[0] connect mshrs_6.io.allocate.bits.prio[1], _view__T_6.prio[1] connect mshrs_6.io.allocate.bits.prio[2], _view__T_6.prio[2] connect mshrs_6.io.allocate.bits.set, mshrs_6.io.status.bits.set node _mshrs_6_io_allocate_bits_repeat_T = eq(mshrs_6.io.allocate.bits.tag, mshrs_6.io.status.bits.tag) connect mshrs_6.io.allocate.bits.repeat, _mshrs_6_io_allocate_bits_repeat_T node _mshrs_6_io_allocate_valid_T = and(sel_6, will_reload_7) connect mshrs_6.io.allocate.valid, _mshrs_6_io_allocate_valid_T node _prio_requests_T = not(requests.io.valid) node _prio_requests_T_1 = shr(requests.io.valid, 7) node _prio_requests_T_2 = or(_prio_requests_T, _prio_requests_T_1) node _prio_requests_T_3 = shr(requests.io.valid, 14) node _prio_requests_T_4 = or(_prio_requests_T_2, _prio_requests_T_3) node prio_requests = not(_prio_requests_T_4) node pop_index_hi = cat(mshr_selectOH, mshr_selectOH) node _pop_index_T = cat(pop_index_hi, mshr_selectOH) node _pop_index_T_1 = and(_pop_index_T, prio_requests) node pop_index_hi_1 = bits(_pop_index_T_1, 20, 16) node pop_index_lo = bits(_pop_index_T_1, 15, 0) node _pop_index_T_2 = orr(pop_index_hi_1) node _pop_index_T_3 = or(pop_index_hi_1, pop_index_lo) node pop_index_hi_2 = bits(_pop_index_T_3, 15, 8) node pop_index_lo_1 = bits(_pop_index_T_3, 7, 0) node _pop_index_T_4 = orr(pop_index_hi_2) node _pop_index_T_5 = or(pop_index_hi_2, pop_index_lo_1) node pop_index_hi_3 = bits(_pop_index_T_5, 7, 4) node pop_index_lo_2 = bits(_pop_index_T_5, 3, 0) node _pop_index_T_6 = orr(pop_index_hi_3) node _pop_index_T_7 = or(pop_index_hi_3, pop_index_lo_2) node pop_index_hi_4 = bits(_pop_index_T_7, 3, 2) node pop_index_lo_3 = bits(_pop_index_T_7, 1, 0) node _pop_index_T_8 = orr(pop_index_hi_4) node _pop_index_T_9 = or(pop_index_hi_4, pop_index_lo_3) node _pop_index_T_10 = bits(_pop_index_T_9, 1, 1) node _pop_index_T_11 = cat(_pop_index_T_8, _pop_index_T_10) node _pop_index_T_12 = cat(_pop_index_T_6, _pop_index_T_11) node _pop_index_T_13 = cat(_pop_index_T_4, _pop_index_T_12) node pop_index = cat(_pop_index_T_2, _pop_index_T_13) connect requests.io.pop.valid, will_pop connect requests.io.pop.bits, pop_index node lb_tag_mismatch = neq(scheduleTag, requests.io.data.tag) node _mshr_uses_directory_assuming_no_bypass_T = and(schedule.reload, may_pop) node mshr_uses_directory_assuming_no_bypass = and(_mshr_uses_directory_assuming_no_bypass_T, lb_tag_mismatch) node mshr_uses_directory_for_lb = and(will_pop, lb_tag_mismatch) node _mshr_uses_directory_T = mux(bypass, request.bits.tag, requests.io.data.tag) node _mshr_uses_directory_T_1 = neq(scheduleTag, _mshr_uses_directory_T) node mshr_uses_directory = and(will_reload, _mshr_uses_directory_T_1) node mshr_validOH_lo_hi = cat(mshrs_2.io.status.valid, mshrs_1.io.status.valid) node mshr_validOH_lo = cat(mshr_validOH_lo_hi, mshrs_0.io.status.valid) node mshr_validOH_hi_lo = cat(mshrs_4.io.status.valid, mshrs_3.io.status.valid) node mshr_validOH_hi_hi = cat(mshrs_6.io.status.valid, mshrs_5.io.status.valid) node mshr_validOH_hi = cat(mshr_validOH_hi_hi, mshr_validOH_hi_lo) node mshr_validOH = cat(mshr_validOH_hi, mshr_validOH_lo) node _mshr_free_T = not(mshr_validOH) node _mshr_free_T_1 = and(_mshr_free_T, prioFilter) node mshr_free = orr(_mshr_free_T_1) node bypassQueue = and(schedule.reload, bypassMatches) node _request_alloc_cases_T = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _request_alloc_cases_T_1 = and(alloc, _request_alloc_cases_T) node _request_alloc_cases_T_2 = and(_request_alloc_cases_T_1, mshr_free) node _request_alloc_cases_T_3 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _request_alloc_cases_T_4 = and(nestB, _request_alloc_cases_T_3) node _request_alloc_cases_T_5 = eq(mshrs_5.io.status.valid, UInt<1>(0h0)) node _request_alloc_cases_T_6 = and(_request_alloc_cases_T_4, _request_alloc_cases_T_5) node _request_alloc_cases_T_7 = eq(mshrs_6.io.status.valid, UInt<1>(0h0)) node _request_alloc_cases_T_8 = and(_request_alloc_cases_T_6, _request_alloc_cases_T_7) node _request_alloc_cases_T_9 = or(_request_alloc_cases_T_2, _request_alloc_cases_T_8) node _request_alloc_cases_T_10 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _request_alloc_cases_T_11 = and(nestC, _request_alloc_cases_T_10) node _request_alloc_cases_T_12 = eq(mshrs_6.io.status.valid, UInt<1>(0h0)) node _request_alloc_cases_T_13 = and(_request_alloc_cases_T_11, _request_alloc_cases_T_12) node request_alloc_cases = or(_request_alloc_cases_T_9, _request_alloc_cases_T_13) node _request_ready_T = or(bypassQueue, requests.io.push.ready) node _request_ready_T_1 = and(queue, _request_ready_T) node _request_ready_T_2 = or(request_alloc_cases, _request_ready_T_1) connect request.ready, _request_ready_T_2 node alloc_uses_directory = and(request.valid, request_alloc_cases) node _directory_io_read_valid_T = or(mshr_uses_directory, alloc_uses_directory) connect directory.io.read.valid, _directory_io_read_valid_T node _directory_io_read_bits_set_T = mux(mshr_uses_directory_for_lb, scheduleSet, request.bits.set) connect directory.io.read.bits.set, _directory_io_read_bits_set_T node _directory_io_read_bits_tag_T = mux(mshr_uses_directory_for_lb, requests.io.data.tag, request.bits.tag) connect directory.io.read.bits.tag, _directory_io_read_bits_tag_T node _requests_io_push_valid_T = and(request.valid, queue) node _requests_io_push_valid_T_1 = eq(bypassQueue, UInt<1>(0h0)) node _requests_io_push_valid_T_2 = and(_requests_io_push_valid_T, _requests_io_push_valid_T_1) connect requests.io.push.valid, _requests_io_push_valid_T_2 connect requests.io.push.bits.data.put, request.bits.put connect requests.io.push.bits.data.offset, request.bits.offset connect requests.io.push.bits.data.tag, request.bits.tag connect requests.io.push.bits.data.source, request.bits.source connect requests.io.push.bits.data.size, request.bits.size connect requests.io.push.bits.data.param, request.bits.param connect requests.io.push.bits.data.opcode, request.bits.opcode connect requests.io.push.bits.data.control, request.bits.control connect requests.io.push.bits.data.prio[0], request.bits.prio[0] connect requests.io.push.bits.data.prio[1], request.bits.prio[1] connect requests.io.push.bits.data.prio[2], request.bits.prio[2] node _requests_io_push_bits_index_T = shl(lowerMatches1, 0) node requests_io_push_bits_index_hi = bits(_requests_io_push_bits_index_T, 6, 4) node requests_io_push_bits_index_lo = bits(_requests_io_push_bits_index_T, 3, 0) node _requests_io_push_bits_index_T_1 = orr(requests_io_push_bits_index_hi) node _requests_io_push_bits_index_T_2 = or(requests_io_push_bits_index_hi, requests_io_push_bits_index_lo) node requests_io_push_bits_index_hi_1 = bits(_requests_io_push_bits_index_T_2, 3, 2) node requests_io_push_bits_index_lo_1 = bits(_requests_io_push_bits_index_T_2, 1, 0) node _requests_io_push_bits_index_T_3 = orr(requests_io_push_bits_index_hi_1) node _requests_io_push_bits_index_T_4 = or(requests_io_push_bits_index_hi_1, requests_io_push_bits_index_lo_1) node _requests_io_push_bits_index_T_5 = bits(_requests_io_push_bits_index_T_4, 1, 1) node _requests_io_push_bits_index_T_6 = cat(_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_5) node _requests_io_push_bits_index_T_7 = cat(_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_6) node _requests_io_push_bits_index_T_8 = shl(lowerMatches1, 7) node requests_io_push_bits_index_hi_2 = bits(_requests_io_push_bits_index_T_8, 13, 8) node requests_io_push_bits_index_lo_2 = bits(_requests_io_push_bits_index_T_8, 7, 0) node _requests_io_push_bits_index_T_9 = orr(requests_io_push_bits_index_hi_2) node _requests_io_push_bits_index_T_10 = or(requests_io_push_bits_index_hi_2, requests_io_push_bits_index_lo_2) node requests_io_push_bits_index_hi_3 = bits(_requests_io_push_bits_index_T_10, 7, 4) node requests_io_push_bits_index_lo_3 = bits(_requests_io_push_bits_index_T_10, 3, 0) node _requests_io_push_bits_index_T_11 = orr(requests_io_push_bits_index_hi_3) node _requests_io_push_bits_index_T_12 = or(requests_io_push_bits_index_hi_3, requests_io_push_bits_index_lo_3) node requests_io_push_bits_index_hi_4 = bits(_requests_io_push_bits_index_T_12, 3, 2) node requests_io_push_bits_index_lo_4 = bits(_requests_io_push_bits_index_T_12, 1, 0) node _requests_io_push_bits_index_T_13 = orr(requests_io_push_bits_index_hi_4) node _requests_io_push_bits_index_T_14 = or(requests_io_push_bits_index_hi_4, requests_io_push_bits_index_lo_4) node _requests_io_push_bits_index_T_15 = bits(_requests_io_push_bits_index_T_14, 1, 1) node _requests_io_push_bits_index_T_16 = cat(_requests_io_push_bits_index_T_13, _requests_io_push_bits_index_T_15) node _requests_io_push_bits_index_T_17 = cat(_requests_io_push_bits_index_T_11, _requests_io_push_bits_index_T_16) node _requests_io_push_bits_index_T_18 = cat(_requests_io_push_bits_index_T_9, _requests_io_push_bits_index_T_17) node _requests_io_push_bits_index_T_19 = shl(lowerMatches1, 14) node requests_io_push_bits_index_hi_5 = bits(_requests_io_push_bits_index_T_19, 20, 16) node requests_io_push_bits_index_lo_5 = bits(_requests_io_push_bits_index_T_19, 15, 0) node _requests_io_push_bits_index_T_20 = orr(requests_io_push_bits_index_hi_5) node _requests_io_push_bits_index_T_21 = or(requests_io_push_bits_index_hi_5, requests_io_push_bits_index_lo_5) node requests_io_push_bits_index_hi_6 = bits(_requests_io_push_bits_index_T_21, 15, 8) node requests_io_push_bits_index_lo_6 = bits(_requests_io_push_bits_index_T_21, 7, 0) node _requests_io_push_bits_index_T_22 = orr(requests_io_push_bits_index_hi_6) node _requests_io_push_bits_index_T_23 = or(requests_io_push_bits_index_hi_6, requests_io_push_bits_index_lo_6) node requests_io_push_bits_index_hi_7 = bits(_requests_io_push_bits_index_T_23, 7, 4) node requests_io_push_bits_index_lo_7 = bits(_requests_io_push_bits_index_T_23, 3, 0) node _requests_io_push_bits_index_T_24 = orr(requests_io_push_bits_index_hi_7) node _requests_io_push_bits_index_T_25 = or(requests_io_push_bits_index_hi_7, requests_io_push_bits_index_lo_7) node requests_io_push_bits_index_hi_8 = bits(_requests_io_push_bits_index_T_25, 3, 2) node requests_io_push_bits_index_lo_8 = bits(_requests_io_push_bits_index_T_25, 1, 0) node _requests_io_push_bits_index_T_26 = orr(requests_io_push_bits_index_hi_8) node _requests_io_push_bits_index_T_27 = or(requests_io_push_bits_index_hi_8, requests_io_push_bits_index_lo_8) node _requests_io_push_bits_index_T_28 = bits(_requests_io_push_bits_index_T_27, 1, 1) node _requests_io_push_bits_index_T_29 = cat(_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_28) node _requests_io_push_bits_index_T_30 = cat(_requests_io_push_bits_index_T_24, _requests_io_push_bits_index_T_29) node _requests_io_push_bits_index_T_31 = cat(_requests_io_push_bits_index_T_22, _requests_io_push_bits_index_T_30) node _requests_io_push_bits_index_T_32 = cat(_requests_io_push_bits_index_T_20, _requests_io_push_bits_index_T_31) node _requests_io_push_bits_index_T_33 = mux(request.bits.prio[0], _requests_io_push_bits_index_T_7, UInt<1>(0h0)) node _requests_io_push_bits_index_T_34 = mux(request.bits.prio[1], _requests_io_push_bits_index_T_18, UInt<1>(0h0)) node _requests_io_push_bits_index_T_35 = mux(request.bits.prio[2], _requests_io_push_bits_index_T_32, UInt<1>(0h0)) node _requests_io_push_bits_index_T_36 = or(_requests_io_push_bits_index_T_33, _requests_io_push_bits_index_T_34) node _requests_io_push_bits_index_T_37 = or(_requests_io_push_bits_index_T_36, _requests_io_push_bits_index_T_35) wire _requests_io_push_bits_index_WIRE : UInt<5> connect _requests_io_push_bits_index_WIRE, _requests_io_push_bits_index_T_37 connect requests.io.push.bits.index, _requests_io_push_bits_index_WIRE node _mshr_insertOH_T = not(mshr_validOH) node _mshr_insertOH_T_1 = shl(_mshr_insertOH_T, 1) node _mshr_insertOH_T_2 = bits(_mshr_insertOH_T_1, 6, 0) node _mshr_insertOH_T_3 = or(_mshr_insertOH_T, _mshr_insertOH_T_2) node _mshr_insertOH_T_4 = shl(_mshr_insertOH_T_3, 2) node _mshr_insertOH_T_5 = bits(_mshr_insertOH_T_4, 6, 0) node _mshr_insertOH_T_6 = or(_mshr_insertOH_T_3, _mshr_insertOH_T_5) node _mshr_insertOH_T_7 = shl(_mshr_insertOH_T_6, 4) node _mshr_insertOH_T_8 = bits(_mshr_insertOH_T_7, 6, 0) node _mshr_insertOH_T_9 = or(_mshr_insertOH_T_6, _mshr_insertOH_T_8) node _mshr_insertOH_T_10 = bits(_mshr_insertOH_T_9, 6, 0) node _mshr_insertOH_T_11 = shl(_mshr_insertOH_T_10, 1) node _mshr_insertOH_T_12 = not(_mshr_insertOH_T_11) node _mshr_insertOH_T_13 = not(mshr_validOH) node _mshr_insertOH_T_14 = and(_mshr_insertOH_T_12, _mshr_insertOH_T_13) node mshr_insertOH = and(_mshr_insertOH_T_14, prioFilter) node _T_14 = bits(mshr_insertOH, 0, 0) node _T_15 = bits(mshr_insertOH, 1, 1) node _T_16 = bits(mshr_insertOH, 2, 2) node _T_17 = bits(mshr_insertOH, 3, 3) node _T_18 = bits(mshr_insertOH, 4, 4) node _T_19 = bits(mshr_insertOH, 5, 5) node _T_20 = bits(mshr_insertOH, 6, 6) node _T_21 = bits(mshr_insertOH, 7, 7) node _T_22 = and(request.valid, alloc) node _T_23 = and(_T_22, _T_14) node _T_24 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_25 = and(_T_23, _T_24) when _T_25 : connect mshrs_0.io.allocate.valid, UInt<1>(0h1) connect mshrs_0.io.allocate.bits.set, request.bits.set connect mshrs_0.io.allocate.bits.put, request.bits.put connect mshrs_0.io.allocate.bits.offset, request.bits.offset connect mshrs_0.io.allocate.bits.tag, request.bits.tag connect mshrs_0.io.allocate.bits.source, request.bits.source connect mshrs_0.io.allocate.bits.size, request.bits.size connect mshrs_0.io.allocate.bits.param, request.bits.param connect mshrs_0.io.allocate.bits.opcode, request.bits.opcode connect mshrs_0.io.allocate.bits.control, request.bits.control connect mshrs_0.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_0.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_0.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_0.io.allocate.bits.repeat, UInt<1>(0h0) node _T_26 = and(request.valid, alloc) node _T_27 = and(_T_26, _T_15) node _T_28 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_29 = and(_T_27, _T_28) when _T_29 : connect mshrs_1.io.allocate.valid, UInt<1>(0h1) connect mshrs_1.io.allocate.bits.set, request.bits.set connect mshrs_1.io.allocate.bits.put, request.bits.put connect mshrs_1.io.allocate.bits.offset, request.bits.offset connect mshrs_1.io.allocate.bits.tag, request.bits.tag connect mshrs_1.io.allocate.bits.source, request.bits.source connect mshrs_1.io.allocate.bits.size, request.bits.size connect mshrs_1.io.allocate.bits.param, request.bits.param connect mshrs_1.io.allocate.bits.opcode, request.bits.opcode connect mshrs_1.io.allocate.bits.control, request.bits.control connect mshrs_1.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_1.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_1.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_1.io.allocate.bits.repeat, UInt<1>(0h0) node _T_30 = and(request.valid, alloc) node _T_31 = and(_T_30, _T_16) node _T_32 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) when _T_33 : connect mshrs_2.io.allocate.valid, UInt<1>(0h1) connect mshrs_2.io.allocate.bits.set, request.bits.set connect mshrs_2.io.allocate.bits.put, request.bits.put connect mshrs_2.io.allocate.bits.offset, request.bits.offset connect mshrs_2.io.allocate.bits.tag, request.bits.tag connect mshrs_2.io.allocate.bits.source, request.bits.source connect mshrs_2.io.allocate.bits.size, request.bits.size connect mshrs_2.io.allocate.bits.param, request.bits.param connect mshrs_2.io.allocate.bits.opcode, request.bits.opcode connect mshrs_2.io.allocate.bits.control, request.bits.control connect mshrs_2.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_2.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_2.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_2.io.allocate.bits.repeat, UInt<1>(0h0) node _T_34 = and(request.valid, alloc) node _T_35 = and(_T_34, _T_17) node _T_36 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) when _T_37 : connect mshrs_3.io.allocate.valid, UInt<1>(0h1) connect mshrs_3.io.allocate.bits.set, request.bits.set connect mshrs_3.io.allocate.bits.put, request.bits.put connect mshrs_3.io.allocate.bits.offset, request.bits.offset connect mshrs_3.io.allocate.bits.tag, request.bits.tag connect mshrs_3.io.allocate.bits.source, request.bits.source connect mshrs_3.io.allocate.bits.size, request.bits.size connect mshrs_3.io.allocate.bits.param, request.bits.param connect mshrs_3.io.allocate.bits.opcode, request.bits.opcode connect mshrs_3.io.allocate.bits.control, request.bits.control connect mshrs_3.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_3.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_3.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_3.io.allocate.bits.repeat, UInt<1>(0h0) node _T_38 = and(request.valid, alloc) node _T_39 = and(_T_38, _T_18) node _T_40 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_41 = and(_T_39, _T_40) when _T_41 : connect mshrs_4.io.allocate.valid, UInt<1>(0h1) connect mshrs_4.io.allocate.bits.set, request.bits.set connect mshrs_4.io.allocate.bits.put, request.bits.put connect mshrs_4.io.allocate.bits.offset, request.bits.offset connect mshrs_4.io.allocate.bits.tag, request.bits.tag connect mshrs_4.io.allocate.bits.source, request.bits.source connect mshrs_4.io.allocate.bits.size, request.bits.size connect mshrs_4.io.allocate.bits.param, request.bits.param connect mshrs_4.io.allocate.bits.opcode, request.bits.opcode connect mshrs_4.io.allocate.bits.control, request.bits.control connect mshrs_4.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_4.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_4.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_4.io.allocate.bits.repeat, UInt<1>(0h0) node _T_42 = and(request.valid, alloc) node _T_43 = and(_T_42, _T_19) node _T_44 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_45 = and(_T_43, _T_44) when _T_45 : connect mshrs_5.io.allocate.valid, UInt<1>(0h1) connect mshrs_5.io.allocate.bits.set, request.bits.set connect mshrs_5.io.allocate.bits.put, request.bits.put connect mshrs_5.io.allocate.bits.offset, request.bits.offset connect mshrs_5.io.allocate.bits.tag, request.bits.tag connect mshrs_5.io.allocate.bits.source, request.bits.source connect mshrs_5.io.allocate.bits.size, request.bits.size connect mshrs_5.io.allocate.bits.param, request.bits.param connect mshrs_5.io.allocate.bits.opcode, request.bits.opcode connect mshrs_5.io.allocate.bits.control, request.bits.control connect mshrs_5.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_5.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_5.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_5.io.allocate.bits.repeat, UInt<1>(0h0) node _T_46 = and(request.valid, alloc) node _T_47 = and(_T_46, _T_20) node _T_48 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_49 = and(_T_47, _T_48) when _T_49 : connect mshrs_6.io.allocate.valid, UInt<1>(0h1) connect mshrs_6.io.allocate.bits.set, request.bits.set connect mshrs_6.io.allocate.bits.put, request.bits.put connect mshrs_6.io.allocate.bits.offset, request.bits.offset connect mshrs_6.io.allocate.bits.tag, request.bits.tag connect mshrs_6.io.allocate.bits.source, request.bits.source connect mshrs_6.io.allocate.bits.size, request.bits.size connect mshrs_6.io.allocate.bits.param, request.bits.param connect mshrs_6.io.allocate.bits.opcode, request.bits.opcode connect mshrs_6.io.allocate.bits.control, request.bits.control connect mshrs_6.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_6.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_6.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_6.io.allocate.bits.repeat, UInt<1>(0h0) node _T_50 = and(request.valid, nestB) node _T_51 = eq(mshrs_5.io.status.valid, UInt<1>(0h0)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(mshrs_6.io.status.valid, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_56 = and(_T_54, _T_55) when _T_56 : connect mshrs_5.io.allocate.valid, UInt<1>(0h1) connect mshrs_5.io.allocate.bits.set, request.bits.set connect mshrs_5.io.allocate.bits.put, request.bits.put connect mshrs_5.io.allocate.bits.offset, request.bits.offset connect mshrs_5.io.allocate.bits.tag, request.bits.tag connect mshrs_5.io.allocate.bits.source, request.bits.source connect mshrs_5.io.allocate.bits.size, request.bits.size connect mshrs_5.io.allocate.bits.param, request.bits.param connect mshrs_5.io.allocate.bits.opcode, request.bits.opcode connect mshrs_5.io.allocate.bits.control, request.bits.control connect mshrs_5.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_5.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_5.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_5.io.allocate.bits.repeat, UInt<1>(0h0) node _T_57 = eq(request.bits.prio[0], UInt<1>(0h0)) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:291 assert (!request.bits.prio(0))\n") : printf assert(clock, _T_57, UInt<1>(0h1), "") : assert connect mshrs_5.io.allocate.bits.prio[0], UInt<1>(0h0) node _T_61 = and(request.valid, nestC) node _T_62 = eq(mshrs_6.io.status.valid, UInt<1>(0h0)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) when _T_65 : connect mshrs_6.io.allocate.valid, UInt<1>(0h1) connect mshrs_6.io.allocate.bits.set, request.bits.set connect mshrs_6.io.allocate.bits.put, request.bits.put connect mshrs_6.io.allocate.bits.offset, request.bits.offset connect mshrs_6.io.allocate.bits.tag, request.bits.tag connect mshrs_6.io.allocate.bits.source, request.bits.source connect mshrs_6.io.allocate.bits.size, request.bits.size connect mshrs_6.io.allocate.bits.param, request.bits.param connect mshrs_6.io.allocate.bits.opcode, request.bits.opcode connect mshrs_6.io.allocate.bits.control, request.bits.control connect mshrs_6.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_6.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_6.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_6.io.allocate.bits.repeat, UInt<1>(0h0) node _T_66 = eq(request.bits.prio[0], UInt<1>(0h0)) node _T_67 = asUInt(reset) node _T_68 = eq(_T_67, UInt<1>(0h0)) when _T_68 : node _T_69 = eq(_T_66, UInt<1>(0h0)) when _T_69 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:299 assert (!request.bits.prio(0))\n") : printf_1 assert(clock, _T_66, UInt<1>(0h1), "") : assert_1 node _T_70 = eq(request.bits.prio[1], UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:300 assert (!request.bits.prio(1))\n") : printf_2 assert(clock, _T_70, UInt<1>(0h1), "") : assert_2 connect mshrs_6.io.allocate.bits.prio[0], UInt<1>(0h0) connect mshrs_6.io.allocate.bits.prio[1], UInt<1>(0h0) node _dirTarget_T = mux(nestB, UInt<6>(0h20), UInt<7>(0h40)) node dirTarget = mux(alloc, mshr_insertOH, _dirTarget_T) node _directoryFanout_T = mux(alloc_uses_directory, dirTarget, UInt<1>(0h0)) node _directoryFanout_T_1 = mux(mshr_uses_directory, mshr_selectOH, _directoryFanout_T) reg directoryFanout : UInt, clock connect directoryFanout, _directoryFanout_T_1 node _mshrs_0_io_directory_valid_T = bits(directoryFanout, 0, 0) connect mshrs_0.io.directory.valid, _mshrs_0_io_directory_valid_T connect mshrs_0.io.directory.bits.way, directory.io.result.bits.way connect mshrs_0.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_0.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_0.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_0.io.directory.bits.state, directory.io.result.bits.state connect mshrs_0.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_1_io_directory_valid_T = bits(directoryFanout, 1, 1) connect mshrs_1.io.directory.valid, _mshrs_1_io_directory_valid_T connect mshrs_1.io.directory.bits.way, directory.io.result.bits.way connect mshrs_1.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_1.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_1.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_1.io.directory.bits.state, directory.io.result.bits.state connect mshrs_1.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_2_io_directory_valid_T = bits(directoryFanout, 2, 2) connect mshrs_2.io.directory.valid, _mshrs_2_io_directory_valid_T connect mshrs_2.io.directory.bits.way, directory.io.result.bits.way connect mshrs_2.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_2.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_2.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_2.io.directory.bits.state, directory.io.result.bits.state connect mshrs_2.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_3_io_directory_valid_T = bits(directoryFanout, 3, 3) connect mshrs_3.io.directory.valid, _mshrs_3_io_directory_valid_T connect mshrs_3.io.directory.bits.way, directory.io.result.bits.way connect mshrs_3.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_3.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_3.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_3.io.directory.bits.state, directory.io.result.bits.state connect mshrs_3.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_4_io_directory_valid_T = bits(directoryFanout, 4, 4) connect mshrs_4.io.directory.valid, _mshrs_4_io_directory_valid_T connect mshrs_4.io.directory.bits.way, directory.io.result.bits.way connect mshrs_4.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_4.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_4.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_4.io.directory.bits.state, directory.io.result.bits.state connect mshrs_4.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_5_io_directory_valid_T = bits(directoryFanout, 5, 5) connect mshrs_5.io.directory.valid, _mshrs_5_io_directory_valid_T connect mshrs_5.io.directory.bits.way, directory.io.result.bits.way connect mshrs_5.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_5.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_5.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_5.io.directory.bits.state, directory.io.result.bits.state connect mshrs_5.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_6_io_directory_valid_T = bits(directoryFanout, 6, 6) connect mshrs_6.io.directory.valid, _mshrs_6_io_directory_valid_T connect mshrs_6.io.directory.bits.way, directory.io.result.bits.way connect mshrs_6.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_6.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_6.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_6.io.directory.bits.state, directory.io.result.bits.state connect mshrs_6.io.directory.bits.dirty, directory.io.result.bits.dirty node _sinkC_io_way_T = eq(mshrs_5.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_1 = and(mshrs_5.io.status.valid, _sinkC_io_way_T) node _sinkC_io_way_T_2 = eq(mshrs_0.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_3 = and(mshrs_0.io.status.valid, _sinkC_io_way_T_2) node _sinkC_io_way_T_4 = eq(mshrs_1.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_5 = and(mshrs_1.io.status.valid, _sinkC_io_way_T_4) node _sinkC_io_way_T_6 = eq(mshrs_2.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_7 = and(mshrs_2.io.status.valid, _sinkC_io_way_T_6) node _sinkC_io_way_T_8 = eq(mshrs_3.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_9 = and(mshrs_3.io.status.valid, _sinkC_io_way_T_8) node _sinkC_io_way_T_10 = eq(mshrs_4.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_11 = and(mshrs_4.io.status.valid, _sinkC_io_way_T_10) node _sinkC_io_way_T_12 = mux(_sinkC_io_way_T_3, mshrs_0.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_13 = mux(_sinkC_io_way_T_5, mshrs_1.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_14 = mux(_sinkC_io_way_T_7, mshrs_2.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_15 = mux(_sinkC_io_way_T_9, mshrs_3.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_16 = mux(_sinkC_io_way_T_11, mshrs_4.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_17 = or(_sinkC_io_way_T_12, _sinkC_io_way_T_13) node _sinkC_io_way_T_18 = or(_sinkC_io_way_T_17, _sinkC_io_way_T_14) node _sinkC_io_way_T_19 = or(_sinkC_io_way_T_18, _sinkC_io_way_T_15) node _sinkC_io_way_T_20 = or(_sinkC_io_way_T_19, _sinkC_io_way_T_16) wire _sinkC_io_way_WIRE : UInt<3> connect _sinkC_io_way_WIRE, _sinkC_io_way_T_20 node _sinkC_io_way_T_21 = mux(_sinkC_io_way_T_1, mshrs_5.io.status.bits.way, _sinkC_io_way_WIRE) connect sinkC.io.way, _sinkC_io_way_T_21 wire _sinkD_io_way_WIRE : UInt<3>[7] connect _sinkD_io_way_WIRE[0], mshrs_0.io.status.bits.way connect _sinkD_io_way_WIRE[1], mshrs_1.io.status.bits.way connect _sinkD_io_way_WIRE[2], mshrs_2.io.status.bits.way connect _sinkD_io_way_WIRE[3], mshrs_3.io.status.bits.way connect _sinkD_io_way_WIRE[4], mshrs_4.io.status.bits.way connect _sinkD_io_way_WIRE[5], mshrs_5.io.status.bits.way connect _sinkD_io_way_WIRE[6], mshrs_6.io.status.bits.way connect sinkD.io.way, _sinkD_io_way_WIRE[sinkD.io.source] wire _sinkD_io_set_WIRE : UInt<10>[7] connect _sinkD_io_set_WIRE[0], mshrs_0.io.status.bits.set connect _sinkD_io_set_WIRE[1], mshrs_1.io.status.bits.set connect _sinkD_io_set_WIRE[2], mshrs_2.io.status.bits.set connect _sinkD_io_set_WIRE[3], mshrs_3.io.status.bits.set connect _sinkD_io_set_WIRE[4], mshrs_4.io.status.bits.set connect _sinkD_io_set_WIRE[5], mshrs_5.io.status.bits.set connect _sinkD_io_set_WIRE[6], mshrs_6.io.status.bits.set connect sinkD.io.set, _sinkD_io_set_WIRE[sinkD.io.source] connect sinkA.io.pb_pop, sourceD.io.pb_pop connect sourceD.io.pb_beat.corrupt, sinkA.io.pb_beat.corrupt connect sourceD.io.pb_beat.mask, sinkA.io.pb_beat.mask connect sourceD.io.pb_beat.data, sinkA.io.pb_beat.data connect sinkC.io.rel_pop, sourceD.io.rel_pop connect sourceD.io.rel_beat.corrupt, sinkC.io.rel_beat.corrupt connect sourceD.io.rel_beat.data, sinkC.io.rel_beat.data connect bankedStore.io.sinkC_adr, sinkC.io.bs_adr connect bankedStore.io.sinkC_dat.data, sinkC.io.bs_dat.data connect bankedStore.io.sinkD_adr, sinkD.io.bs_adr connect bankedStore.io.sinkD_dat.data, sinkD.io.bs_dat.data connect bankedStore.io.sourceC_adr, sourceC.io.bs_adr connect bankedStore.io.sourceD_radr, sourceD.io.bs_radr connect bankedStore.io.sourceD_wadr, sourceD.io.bs_wadr connect bankedStore.io.sourceD_wdat.data, sourceD.io.bs_wdat.data connect sourceC.io.bs_dat.data, bankedStore.io.sourceC_dat.data connect sourceD.io.bs_rdat.data, bankedStore.io.sourceD_rdat.data connect sourceD.io.evict_req.way, sourceC.io.evict_req.way connect sourceD.io.evict_req.set, sourceC.io.evict_req.set connect sourceD.io.grant_req.way, sinkD.io.grant_req.way connect sourceD.io.grant_req.set, sinkD.io.grant_req.set connect sourceC.io.evict_safe, sourceD.io.evict_safe connect sinkD.io.grant_safe, sourceD.io.grant_safe
module InclusiveCacheBankScheduler( // @[Scheduler.scala:27:7] input clock, // @[Scheduler.scala:27:7] input reset, // @[Scheduler.scala:27:7] output io_in_a_ready, // @[Scheduler.scala:29:14] input io_in_a_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_a_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_a_bits_address, // @[Scheduler.scala:29:14] input [7:0] io_in_a_bits_mask, // @[Scheduler.scala:29:14] input [63:0] io_in_a_bits_data, // @[Scheduler.scala:29:14] input io_in_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_b_ready, // @[Scheduler.scala:29:14] output io_in_b_valid, // @[Scheduler.scala:29:14] output [1:0] io_in_b_bits_param, // @[Scheduler.scala:29:14] output [31:0] io_in_b_bits_address, // @[Scheduler.scala:29:14] output io_in_c_ready, // @[Scheduler.scala:29:14] input io_in_c_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_c_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_c_bits_address, // @[Scheduler.scala:29:14] input [63:0] io_in_c_bits_data, // @[Scheduler.scala:29:14] input io_in_c_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_d_ready, // @[Scheduler.scala:29:14] output io_in_d_valid, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_opcode, // @[Scheduler.scala:29:14] output [1:0] io_in_d_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_size, // @[Scheduler.scala:29:14] output [5:0] io_in_d_bits_source, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_sink, // @[Scheduler.scala:29:14] output io_in_d_bits_denied, // @[Scheduler.scala:29:14] output [63:0] io_in_d_bits_data, // @[Scheduler.scala:29:14] output io_in_d_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_e_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_e_bits_sink, // @[Scheduler.scala:29:14] input io_out_a_ready, // @[Scheduler.scala:29:14] output io_out_a_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_size, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_a_bits_address, // @[Scheduler.scala:29:14] output [7:0] io_out_a_bits_mask, // @[Scheduler.scala:29:14] output [63:0] io_out_a_bits_data, // @[Scheduler.scala:29:14] output io_out_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_out_c_ready, // @[Scheduler.scala:29:14] output io_out_c_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_size, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_c_bits_address, // @[Scheduler.scala:29:14] output [63:0] io_out_c_bits_data, // @[Scheduler.scala:29:14] output io_out_c_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_d_ready, // @[Scheduler.scala:29:14] input io_out_d_valid, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_opcode, // @[Scheduler.scala:29:14] input [1:0] io_out_d_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_size, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_source, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_sink, // @[Scheduler.scala:29:14] input io_out_d_bits_denied, // @[Scheduler.scala:29:14] input [63:0] io_out_d_bits_data, // @[Scheduler.scala:29:14] input io_out_d_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_e_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_e_bits_sink, // @[Scheduler.scala:29:14] output io_req_ready, // @[Scheduler.scala:29:14] input io_req_valid, // @[Scheduler.scala:29:14] input [31:0] io_req_bits_address, // @[Scheduler.scala:29:14] output io_resp_valid // @[Scheduler.scala:29:14] ); wire [12:0] mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :295:103, :297:73] wire [12:0] mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :287:131, :289:74] wire [12:0] mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [12:0] mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [5:0] request_bits_put; // @[Scheduler.scala:163:21] wire [5:0] request_bits_offset; // @[Scheduler.scala:163:21] wire [12:0] request_bits_tag; // @[Scheduler.scala:163:21] wire [5:0] request_bits_source; // @[Scheduler.scala:163:21] wire [2:0] request_bits_size; // @[Scheduler.scala:163:21] wire [2:0] request_bits_param; // @[Scheduler.scala:163:21] wire [2:0] request_bits_opcode; // @[Scheduler.scala:163:21] wire request_bits_control; // @[Scheduler.scala:163:21] wire request_bits_prio_2; // @[Scheduler.scala:163:21] wire request_bits_prio_0; // @[Scheduler.scala:163:21] wire _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_status_bits_set; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [12:0] _mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _requests_io_push_ready; // @[Scheduler.scala:70:24] wire [20:0] _requests_io_valid; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_0; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_1; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_2; // @[Scheduler.scala:70:24] wire _requests_io_data_control; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_opcode; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_param; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_size; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_source; // @[Scheduler.scala:70:24] wire [12:0] _requests_io_data_tag; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_offset; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_put; // @[Scheduler.scala:70:24] wire _bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala:69:27] wire [63:0] _bankedStore_io_sourceC_dat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala:69:27] wire [63:0] _bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala:69:27] wire _directory_io_write_ready; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_dirty; // @[Scheduler.scala:68:25] wire [1:0] _directory_io_result_bits_state; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_clients; // @[Scheduler.scala:68:25] wire [12:0] _directory_io_result_bits_tag; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_hit; // @[Scheduler.scala:68:25] wire [2:0] _directory_io_result_bits_way; // @[Scheduler.scala:68:25] wire _directory_io_ready; // @[Scheduler.scala:68:25] wire _sinkX_io_req_valid; // @[Scheduler.scala:58:21] wire [12:0] _sinkX_io_req_bits_tag; // @[Scheduler.scala:58:21] wire [9:0] _sinkX_io_req_bits_set; // @[Scheduler.scala:58:21] wire _sinkE_io_resp_valid; // @[Scheduler.scala:57:21] wire [2:0] _sinkE_io_resp_bits_sink; // @[Scheduler.scala:57:21] wire _sinkD_io_resp_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_last; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_opcode; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_param; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_source; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_sink; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_denied; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_source; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_bs_adr_bits_way; // @[Scheduler.scala:56:21] wire [9:0] _sinkD_io_bs_adr_bits_set; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala:56:21] wire [63:0] _sinkD_io_bs_dat_data; // @[Scheduler.scala:56:21] wire [9:0] _sinkD_io_grant_req_set; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_grant_req_way; // @[Scheduler.scala:56:21] wire _sinkC_io_req_valid; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_opcode; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_param; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_size; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_source; // @[Scheduler.scala:55:21] wire [12:0] _sinkC_io_req_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_offset; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_put; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_req_bits_set; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_last; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_resp_bits_set; // @[Scheduler.scala:55:21] wire [12:0] _sinkC_io_resp_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_resp_bits_source; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_resp_bits_param; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_data; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_set; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_bs_adr_bits_way; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_bs_adr_bits_set; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala:55:21] wire [63:0] _sinkC_io_bs_dat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_pop_ready; // @[Scheduler.scala:55:21] wire [63:0] _sinkC_io_rel_beat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_beat_corrupt; // @[Scheduler.scala:55:21] wire _sinkA_io_req_valid; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21] wire [12:0] _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21] wire [9:0] _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_pop_ready; // @[Scheduler.scala:54:21] wire [63:0] _sinkA_io_pb_beat_data; // @[Scheduler.scala:54:21] wire [7:0] _sinkA_io_pb_beat_mask; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_beat_corrupt; // @[Scheduler.scala:54:21] wire _sourceX_io_req_ready; // @[Scheduler.scala:45:23] wire _sourceE_io_req_ready; // @[Scheduler.scala:44:23] wire _sourceD_io_req_ready; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_pb_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_rel_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_radr_valid; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_radr_bits_way; // @[Scheduler.scala:43:23] wire [9:0] _sourceD_io_bs_radr_bits_set; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_wadr_valid; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala:43:23] wire [9:0] _sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala:43:23] wire [63:0] _sourceD_io_bs_wdat_data; // @[Scheduler.scala:43:23] wire _sourceD_io_evict_safe; // @[Scheduler.scala:43:23] wire _sourceD_io_grant_safe; // @[Scheduler.scala:43:23] wire _sourceC_io_req_ready; // @[Scheduler.scala:42:23] wire _sourceC_io_bs_adr_valid; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_bs_adr_bits_way; // @[Scheduler.scala:42:23] wire [9:0] _sourceC_io_bs_adr_bits_set; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala:42:23] wire [9:0] _sourceC_io_evict_req_set; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_evict_req_way; // @[Scheduler.scala:42:23] wire _sourceB_io_req_ready; // @[Scheduler.scala:41:23] wire _sourceA_io_req_ready; // @[Scheduler.scala:40:23] wire io_in_a_valid_0 = io_in_a_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Scheduler.scala:27:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Scheduler.scala:27:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Scheduler.scala:27:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Scheduler.scala:27:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Scheduler.scala:27:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Scheduler.scala:27:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Scheduler.scala:27:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Scheduler.scala:27:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Scheduler.scala:27:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Scheduler.scala:27:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Scheduler.scala:27:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Scheduler.scala:27:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Scheduler.scala:27:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Scheduler.scala:27:7] wire io_out_a_ready_0 = io_out_a_ready; // @[Scheduler.scala:27:7] wire io_out_c_ready_0 = io_out_c_ready; // @[Scheduler.scala:27:7] wire io_out_d_valid_0 = io_out_d_valid; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_opcode_0 = io_out_d_bits_opcode; // @[Scheduler.scala:27:7] wire [1:0] io_out_d_bits_param_0 = io_out_d_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_size_0 = io_out_d_bits_size; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_source_0 = io_out_d_bits_source; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_sink_0 = io_out_d_bits_sink; // @[Scheduler.scala:27:7] wire io_out_d_bits_denied_0 = io_out_d_bits_denied; // @[Scheduler.scala:27:7] wire [63:0] io_out_d_bits_data_0 = io_out_d_bits_data; // @[Scheduler.scala:27:7] wire io_out_d_bits_corrupt_0 = io_out_d_bits_corrupt; // @[Scheduler.scala:27:7] wire io_req_valid_0 = io_req_valid; // @[Scheduler.scala:27:7] wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[Scheduler.scala:27:7] wire io_in_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7] wire io_out_b_valid = 1'h0; // @[Scheduler.scala:27:7] wire io_out_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7] wire io_resp_bits_fail = 1'h0; // @[Scheduler.scala:27:7] wire schedule_x_bits_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_11_bits_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_12_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_111 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_112 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_113 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_114 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_115 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_116 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_117 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_118 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_119 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_120 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_121 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_122 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_123 = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_324 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_325 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_338 = 1'h0; // @[Mux.scala:30:73] wire request_bits_prio_1 = 1'h0; // @[Scheduler.scala:163:21] wire _request_bits_T_prio_1 = 1'h0; // @[Scheduler.scala:166:22] wire _request_bits_T_prio_2 = 1'h0; // @[Scheduler.scala:166:22] wire _request_bits_T_1_prio_1 = 1'h0; // @[Scheduler.scala:165:22] wire blockB = 1'h0; // @[Scheduler.scala:175:70] wire nestB = 1'h0; // @[Scheduler.scala:179:70] wire _view__WIRE_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_1_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_2_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_3_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_4_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_5_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_6_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _request_alloc_cases_T_4 = 1'h0; // @[Scheduler.scala:259:13] wire _request_alloc_cases_T_6 = 1'h0; // @[Scheduler.scala:259:56] wire _request_alloc_cases_T_8 = 1'h0; // @[Scheduler.scala:259:84] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Scheduler.scala:27:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Scheduler.scala:27:7] wire [5:0] io_in_b_bits_source = 6'h20; // @[Scheduler.scala:27:7] wire [5:0] _lowerMatches1_T_3 = 6'h20; // @[Scheduler.scala:201:43] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Scheduler.scala:27:7] wire [63:0] io_in_b_bits_data = 64'h0; // @[Scheduler.scala:27:7] wire [63:0] io_out_b_bits_data = 64'h0; // @[Scheduler.scala:27:7] wire io_in_e_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_out_b_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_out_e_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_resp_ready = 1'h1; // @[Scheduler.scala:27:7] wire _mshr_request_T_138 = 1'h1; // @[Scheduler.scala:107:28] wire _request_bits_T_prio_0 = 1'h1; // @[Scheduler.scala:166:22] wire _queue_T_1 = 1'h1; // @[Scheduler.scala:185:35] wire _queue_T_5 = 1'h1; // @[Scheduler.scala:185:55] wire [2:0] io_out_b_bits_opcode = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] io_out_b_bits_size = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] io_out_b_bits_source = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] _schedule_WIRE_19_bits_sink = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_sink = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_189 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_190 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_191 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_192 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_193 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_194 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_195 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_196 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_197 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_198 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_199 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_200 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_201 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_23 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_423 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_424 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_425 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_426 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_427 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_428 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_429 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_430 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_431 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_432 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_433 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_434 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_435 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_44 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_55_bits_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_56_source = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_553 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_554 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_555 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_556 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_557 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_558 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_559 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_560 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_561 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_562 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_563 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_564 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_T_565 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_58 = 3'h0; // @[Mux.scala:30:73] wire [1:0] io_out_b_bits_param = 2'h0; // @[Scheduler.scala:27:7] wire [31:0] io_out_b_bits_address = 32'h0; // @[Scheduler.scala:27:7] wire [7:0] io_out_b_bits_mask = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_0 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_1 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_2 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_3 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_4 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_5 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_6 = 8'h0; // @[Scheduler.scala:27:7] wire [7:0] io_ways_7 = 8'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_0 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_1 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_2 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_3 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_4 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_5 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_6 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_7 = 11'h0; // @[Scheduler.scala:27:7] wire [6:0] _lowerMatches1_T_1 = 7'h40; // @[Scheduler.scala:200:43] wire [6:0] _dirTarget_T = 7'h40; // @[Scheduler.scala:306:48] wire [3:0] _requests_io_push_bits_index_T_34 = 4'h0; // @[Mux.scala:30:73] wire [4:0] _prioFilter_T_1 = 5'h1F; // @[Scheduler.scala:182:69] wire io_in_a_ready_0; // @[Scheduler.scala:27:7] wire [1:0] io_in_b_bits_param_0; // @[Scheduler.scala:27:7] wire [31:0] io_in_b_bits_address_0; // @[Scheduler.scala:27:7] wire io_in_b_valid_0; // @[Scheduler.scala:27:7] wire io_in_c_ready_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_opcode_0; // @[Scheduler.scala:27:7] wire [1:0] io_in_d_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_size_0; // @[Scheduler.scala:27:7] wire [5:0] io_in_d_bits_source_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_sink_0; // @[Scheduler.scala:27:7] wire io_in_d_bits_denied_0; // @[Scheduler.scala:27:7] wire [63:0] io_in_d_bits_data_0; // @[Scheduler.scala:27:7] wire io_in_d_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_in_d_valid_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_opcode_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_size_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_out_a_bits_address_0; // @[Scheduler.scala:27:7] wire [7:0] io_out_a_bits_mask_0; // @[Scheduler.scala:27:7] wire [63:0] io_out_a_bits_data_0; // @[Scheduler.scala:27:7] wire io_out_a_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_out_a_valid_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_opcode_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_size_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_out_c_bits_address_0; // @[Scheduler.scala:27:7] wire [63:0] io_out_c_bits_data_0; // @[Scheduler.scala:27:7] wire io_out_c_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_out_c_valid_0; // @[Scheduler.scala:27:7] wire io_out_d_ready_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_e_bits_sink_0; // @[Scheduler.scala:27:7] wire io_out_e_valid_0; // @[Scheduler.scala:27:7] wire io_req_ready_0; // @[Scheduler.scala:27:7] wire io_resp_valid_0; // @[Scheduler.scala:27:7] wire [9:0] _nestedwb_set_T; // @[Scheduler.scala:155:24] wire [12:0] _nestedwb_tag_T; // @[Scheduler.scala:156:24] wire _nestedwb_b_toN_T_2; // @[Scheduler.scala:157:75] wire _nestedwb_b_toB_T_2; // @[Scheduler.scala:158:75] wire _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:159:37] wire _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:160:75] wire [9:0] nestedwb_set; // @[Scheduler.scala:75:22] wire [12:0] nestedwb_tag; // @[Scheduler.scala:75:22] wire nestedwb_b_toN; // @[Scheduler.scala:75:22] wire nestedwb_b_toB; // @[Scheduler.scala:75:22] wire nestedwb_b_clr_dirty; // @[Scheduler.scala:75:22] wire nestedwb_c_set_dirty; // @[Scheduler.scala:75:22] wire _mshrs_0_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_0_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_0_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_0_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_0_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h0; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_0_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_0_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_0_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h0; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_0_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_0_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_1_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_1_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_1_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_1_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_1_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h1; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_1_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_1_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_1_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h1; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_1_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_1_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_2_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_2_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_2_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_2_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_2_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h2; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_2_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_2_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_2_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h2; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_2_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_2_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_3_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_3_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_3_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_3_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_3_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h3; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_3_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_3_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_3_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h3; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_3_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_3_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_4_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_4_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_4_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_4_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_4_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h4; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_4_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_4_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_4_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h4; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_4_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_4_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_5_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_5_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_5_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_5_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h5; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_5_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_5_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_5_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h5; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_5_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_5_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_6_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_6_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_6_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_6_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h6; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_6_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_6_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_6_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h6; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_6_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_6_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshr_stall_abc_T = _mshrs_0_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_1 = _mshrs_5_io_status_valid & _mshr_stall_abc_T; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_2 = _mshrs_0_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_3 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_2; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_0 = _mshr_stall_abc_T_1 | _mshr_stall_abc_T_3; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_4 = _mshrs_1_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_5 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_4; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_6 = _mshrs_1_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_7 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_6; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_1 = _mshr_stall_abc_T_5 | _mshr_stall_abc_T_7; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_8 = _mshrs_2_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_9 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_8; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_10 = _mshrs_2_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_11 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_10; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_2 = _mshr_stall_abc_T_9 | _mshr_stall_abc_T_11; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_12 = _mshrs_3_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_13 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_12; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_14 = _mshrs_3_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_15 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_14; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_3 = _mshr_stall_abc_T_13 | _mshr_stall_abc_T_15; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_16 = _mshrs_4_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_17 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_16; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_18 = _mshrs_4_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_19 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_18; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_4 = _mshr_stall_abc_T_17 | _mshr_stall_abc_T_19; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_bc_T = _mshrs_5_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :94:58] wire mshr_stall_bc = _mshrs_6_io_status_valid & _mshr_stall_bc_T; // @[Scheduler.scala:71:46, :94:{28,58}] wire stall_abc_0 = mshr_stall_abc_0 & _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_1 = mshr_stall_abc_1 & _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_2 = mshr_stall_abc_2 & _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_3 = mshr_stall_abc_3 & _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_4 = mshr_stall_abc_4 & _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire _mshr_request_T = ~mshr_stall_abc_0; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_1 = _mshrs_0_io_schedule_valid & _mshr_request_T; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_2 = ~_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_3 = _sourceA_io_req_ready | _mshr_request_T_2; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_4 = _mshr_request_T_1 & _mshr_request_T_3; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_5 = ~_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_6 = _sourceB_io_req_ready | _mshr_request_T_5; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_7 = _mshr_request_T_4 & _mshr_request_T_6; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_8 = ~_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_9 = _sourceC_io_req_ready | _mshr_request_T_8; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_10 = _mshr_request_T_7 & _mshr_request_T_9; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_11 = ~_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_12 = _sourceD_io_req_ready | _mshr_request_T_11; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_13 = _mshr_request_T_10 & _mshr_request_T_12; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_14 = ~_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_15 = _sourceE_io_req_ready | _mshr_request_T_14; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_16 = _mshr_request_T_13 & _mshr_request_T_15; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_17 = ~_mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_18 = _sourceX_io_req_ready | _mshr_request_T_17; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_19 = _mshr_request_T_16 & _mshr_request_T_18; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_20 = ~_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_21 = _directory_io_write_ready | _mshr_request_T_20; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_22 = _mshr_request_T_19 & _mshr_request_T_21; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_23 = ~mshr_stall_abc_1; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_24 = _mshrs_1_io_schedule_valid & _mshr_request_T_23; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_25 = ~_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_26 = _sourceA_io_req_ready | _mshr_request_T_25; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_27 = _mshr_request_T_24 & _mshr_request_T_26; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_28 = ~_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_29 = _sourceB_io_req_ready | _mshr_request_T_28; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_30 = _mshr_request_T_27 & _mshr_request_T_29; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_31 = ~_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_32 = _sourceC_io_req_ready | _mshr_request_T_31; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_33 = _mshr_request_T_30 & _mshr_request_T_32; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_34 = ~_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_35 = _sourceD_io_req_ready | _mshr_request_T_34; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_36 = _mshr_request_T_33 & _mshr_request_T_35; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_37 = ~_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_38 = _sourceE_io_req_ready | _mshr_request_T_37; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_39 = _mshr_request_T_36 & _mshr_request_T_38; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_40 = ~_mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_41 = _sourceX_io_req_ready | _mshr_request_T_40; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_42 = _mshr_request_T_39 & _mshr_request_T_41; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_43 = ~_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_44 = _directory_io_write_ready | _mshr_request_T_43; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_45 = _mshr_request_T_42 & _mshr_request_T_44; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_46 = ~mshr_stall_abc_2; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_47 = _mshrs_2_io_schedule_valid & _mshr_request_T_46; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_48 = ~_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_49 = _sourceA_io_req_ready | _mshr_request_T_48; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_50 = _mshr_request_T_47 & _mshr_request_T_49; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_51 = ~_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_52 = _sourceB_io_req_ready | _mshr_request_T_51; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_53 = _mshr_request_T_50 & _mshr_request_T_52; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_54 = ~_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_55 = _sourceC_io_req_ready | _mshr_request_T_54; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_56 = _mshr_request_T_53 & _mshr_request_T_55; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_57 = ~_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_58 = _sourceD_io_req_ready | _mshr_request_T_57; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_59 = _mshr_request_T_56 & _mshr_request_T_58; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_60 = ~_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_61 = _sourceE_io_req_ready | _mshr_request_T_60; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_62 = _mshr_request_T_59 & _mshr_request_T_61; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_63 = ~_mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_64 = _sourceX_io_req_ready | _mshr_request_T_63; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_65 = _mshr_request_T_62 & _mshr_request_T_64; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_66 = ~_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_67 = _directory_io_write_ready | _mshr_request_T_66; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_68 = _mshr_request_T_65 & _mshr_request_T_67; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_69 = ~mshr_stall_abc_3; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_70 = _mshrs_3_io_schedule_valid & _mshr_request_T_69; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_71 = ~_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_72 = _sourceA_io_req_ready | _mshr_request_T_71; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_73 = _mshr_request_T_70 & _mshr_request_T_72; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_74 = ~_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_75 = _sourceB_io_req_ready | _mshr_request_T_74; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_76 = _mshr_request_T_73 & _mshr_request_T_75; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_77 = ~_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_78 = _sourceC_io_req_ready | _mshr_request_T_77; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_79 = _mshr_request_T_76 & _mshr_request_T_78; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_80 = ~_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_81 = _sourceD_io_req_ready | _mshr_request_T_80; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_82 = _mshr_request_T_79 & _mshr_request_T_81; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_83 = ~_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_84 = _sourceE_io_req_ready | _mshr_request_T_83; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_85 = _mshr_request_T_82 & _mshr_request_T_84; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_86 = ~_mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_87 = _sourceX_io_req_ready | _mshr_request_T_86; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_88 = _mshr_request_T_85 & _mshr_request_T_87; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_89 = ~_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_90 = _directory_io_write_ready | _mshr_request_T_89; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_91 = _mshr_request_T_88 & _mshr_request_T_90; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_92 = ~mshr_stall_abc_4; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_93 = _mshrs_4_io_schedule_valid & _mshr_request_T_92; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_94 = ~_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_95 = _sourceA_io_req_ready | _mshr_request_T_94; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_96 = _mshr_request_T_93 & _mshr_request_T_95; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_97 = ~_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_98 = _sourceB_io_req_ready | _mshr_request_T_97; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_99 = _mshr_request_T_96 & _mshr_request_T_98; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_100 = ~_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_101 = _sourceC_io_req_ready | _mshr_request_T_100; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_102 = _mshr_request_T_99 & _mshr_request_T_101; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_103 = ~_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_104 = _sourceD_io_req_ready | _mshr_request_T_103; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_105 = _mshr_request_T_102 & _mshr_request_T_104; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_106 = ~_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_107 = _sourceE_io_req_ready | _mshr_request_T_106; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_108 = _mshr_request_T_105 & _mshr_request_T_107; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_109 = ~_mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_110 = _sourceX_io_req_ready | _mshr_request_T_109; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_111 = _mshr_request_T_108 & _mshr_request_T_110; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_112 = ~_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_113 = _directory_io_write_ready | _mshr_request_T_112; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_114 = _mshr_request_T_111 & _mshr_request_T_113; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_115 = ~mshr_stall_bc; // @[Scheduler.scala:94:28, :107:28] wire _mshr_request_T_116 = _mshrs_5_io_schedule_valid & _mshr_request_T_115; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_117 = ~_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_118 = _sourceA_io_req_ready | _mshr_request_T_117; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_119 = _mshr_request_T_116 & _mshr_request_T_118; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_120 = ~_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_121 = _sourceB_io_req_ready | _mshr_request_T_120; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_122 = _mshr_request_T_119 & _mshr_request_T_121; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_123 = ~_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_124 = _sourceC_io_req_ready | _mshr_request_T_123; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_125 = _mshr_request_T_122 & _mshr_request_T_124; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_126 = ~_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_127 = _sourceD_io_req_ready | _mshr_request_T_126; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_128 = _mshr_request_T_125 & _mshr_request_T_127; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_129 = ~_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_130 = _sourceE_io_req_ready | _mshr_request_T_129; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_131 = _mshr_request_T_128 & _mshr_request_T_130; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_132 = ~_mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_133 = _sourceX_io_req_ready | _mshr_request_T_132; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_134 = _mshr_request_T_131 & _mshr_request_T_133; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_135 = ~_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_136 = _directory_io_write_ready | _mshr_request_T_135; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_137 = _mshr_request_T_134 & _mshr_request_T_136; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_140 = ~_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_141 = _sourceA_io_req_ready | _mshr_request_T_140; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_139; // @[Scheduler.scala:107:25] wire _mshr_request_T_142 = _mshr_request_T_139 & _mshr_request_T_141; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_143 = ~_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_144 = _sourceB_io_req_ready | _mshr_request_T_143; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_145 = _mshr_request_T_142 & _mshr_request_T_144; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_146 = ~_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_147 = _sourceC_io_req_ready | _mshr_request_T_146; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_148 = _mshr_request_T_145 & _mshr_request_T_147; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_149 = ~_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_150 = _sourceD_io_req_ready | _mshr_request_T_149; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_151 = _mshr_request_T_148 & _mshr_request_T_150; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_152 = ~_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_153 = _sourceE_io_req_ready | _mshr_request_T_152; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_154 = _mshr_request_T_151 & _mshr_request_T_153; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_155 = ~_mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_156 = _sourceX_io_req_ready | _mshr_request_T_155; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_157 = _mshr_request_T_154 & _mshr_request_T_156; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_158 = ~_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_159 = _directory_io_write_ready | _mshr_request_T_158; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_160 = _mshr_request_T_157 & _mshr_request_T_159; // @[Scheduler.scala:112:61, :113:61, :114:33] wire [1:0] mshr_request_lo_hi = {_mshr_request_T_68, _mshr_request_T_45}; // @[Scheduler.scala:106:25, :113:61] wire [2:0] mshr_request_lo = {mshr_request_lo_hi, _mshr_request_T_22}; // @[Scheduler.scala:106:25, :113:61] wire [1:0] mshr_request_hi_lo = {_mshr_request_T_114, _mshr_request_T_91}; // @[Scheduler.scala:106:25, :113:61] wire [1:0] mshr_request_hi_hi = {_mshr_request_T_160, _mshr_request_T_137}; // @[Scheduler.scala:106:25, :113:61] wire [3:0] mshr_request_hi = {mshr_request_hi_hi, mshr_request_hi_lo}; // @[Scheduler.scala:106:25] wire [6:0] mshr_request = {mshr_request_hi, mshr_request_lo}; // @[Scheduler.scala:106:25] reg [6:0] robin_filter; // @[Scheduler.scala:118:29] wire [6:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala:106:25, :118:29, :119:54] wire [13:0] robin_request = {mshr_request, _robin_request_T}; // @[Scheduler.scala:106:25, :119:{26,54}] wire [14:0] _mshr_selectOH2_T = {robin_request, 1'h0}; // @[package.scala:253:48] wire [13:0] _mshr_selectOH2_T_1 = _mshr_selectOH2_T[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_2 = robin_request | _mshr_selectOH2_T_1; // @[package.scala:253:{43,53}] wire [15:0] _mshr_selectOH2_T_3 = {_mshr_selectOH2_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [13:0] _mshr_selectOH2_T_4 = _mshr_selectOH2_T_3[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_5 = _mshr_selectOH2_T_2 | _mshr_selectOH2_T_4; // @[package.scala:253:{43,53}] wire [17:0] _mshr_selectOH2_T_6 = {_mshr_selectOH2_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [13:0] _mshr_selectOH2_T_7 = _mshr_selectOH2_T_6[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_8 = _mshr_selectOH2_T_5 | _mshr_selectOH2_T_7; // @[package.scala:253:{43,53}] wire [21:0] _mshr_selectOH2_T_9 = {_mshr_selectOH2_T_8, 8'h0}; // @[package.scala:253:{43,48}] wire [13:0] _mshr_selectOH2_T_10 = _mshr_selectOH2_T_9[13:0]; // @[package.scala:253:{48,53}] wire [13:0] _mshr_selectOH2_T_11 = _mshr_selectOH2_T_8 | _mshr_selectOH2_T_10; // @[package.scala:253:{43,53}] wire [13:0] _mshr_selectOH2_T_12 = _mshr_selectOH2_T_11; // @[package.scala:253:43, :254:17] wire [14:0] _mshr_selectOH2_T_13 = {_mshr_selectOH2_T_12, 1'h0}; // @[package.scala:254:17] wire [14:0] _mshr_selectOH2_T_14 = ~_mshr_selectOH2_T_13; // @[Scheduler.scala:120:{24,48}] wire [14:0] mshr_selectOH2 = {1'h0, _mshr_selectOH2_T_14[13:0] & robin_request}; // @[Scheduler.scala:119:26, :120:{24,54}] wire [6:0] _mshr_selectOH_T = mshr_selectOH2[13:7]; // @[Scheduler.scala:120:54, :121:37] wire [6:0] _mshr_selectOH_T_1 = mshr_selectOH2[6:0]; // @[Scheduler.scala:120:54, :121:86] wire [6:0] mshr_selectOH = _mshr_selectOH_T | _mshr_selectOH_T_1; // @[Scheduler.scala:121:{37,70,86}] wire [2:0] mshr_select_hi = mshr_selectOH[6:4]; // @[OneHot.scala:30:18] wire [3:0] mshr_select_lo = mshr_selectOH[3:0]; // @[OneHot.scala:31:18] wire _mshr_select_T = |mshr_select_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _mshr_select_T_1 = {1'h0, mshr_select_hi} | mshr_select_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] mshr_select_hi_1 = _mshr_select_T_1[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] mshr_select_lo_1 = _mshr_select_T_1[1:0]; // @[OneHot.scala:31:18, :32:28] wire _mshr_select_T_2 = |mshr_select_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _mshr_select_T_3 = mshr_select_hi_1 | mshr_select_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _mshr_select_T_4 = _mshr_select_T_3[1]; // @[OneHot.scala:32:28] wire [1:0] _mshr_select_T_5 = {_mshr_select_T_2, _mshr_select_T_4}; // @[OneHot.scala:32:{10,14}] wire [2:0] mshr_select = {_mshr_select_T, _mshr_select_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] schedule_a_bits_source = mshr_select; // @[OneHot.scala:32:10] wire [2:0] schedule_d_bits_sink = mshr_select; // @[OneHot.scala:32:10] wire _schedule_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _scheduleTag_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _scheduleSet_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire sel = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _schedule_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _scheduleTag_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _scheduleSet_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire sel_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _schedule_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _scheduleTag_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _scheduleSet_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire sel_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _schedule_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _scheduleTag_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _scheduleSet_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire sel_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _schedule_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _scheduleTag_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _scheduleSet_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire sel_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _schedule_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _scheduleTag_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _scheduleSet_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire select_bc = mshr_selectOH[5]; // @[Mux.scala:32:36] wire sel_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _schedule_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _scheduleTag_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _scheduleSet_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire select_c = mshr_selectOH[6]; // @[Mux.scala:32:36] wire sel_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _schedule_WIRE_55_valid; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73] wire _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73] wire _schedule_WIRE_48_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73] wire _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73] wire _schedule_WIRE_38_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_c_bits_source_T_1; // @[Scheduler.scala:132:32] wire [12:0] _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73] wire _schedule_WIRE_19_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73] wire _schedule_WIRE_15_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73] wire _schedule_WIRE_11_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_1_valid; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73] wire _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73] wire _schedule_WIRE; // @[Mux.scala:30:73] wire [12:0] schedule_a_bits_tag; // @[Mux.scala:30:73] wire [9:0] schedule_a_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_a_bits_param; // @[Mux.scala:30:73] wire schedule_a_bits_block; // @[Mux.scala:30:73] wire schedule_a_valid; // @[Mux.scala:30:73] wire [2:0] schedule_b_bits_param; // @[Mux.scala:30:73] wire [12:0] schedule_b_bits_tag; // @[Mux.scala:30:73] wire [9:0] schedule_b_bits_set; // @[Mux.scala:30:73] wire schedule_b_bits_clients; // @[Mux.scala:30:73] wire schedule_b_valid; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_opcode; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_param; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_source; // @[Mux.scala:30:73] wire [12:0] schedule_c_bits_tag; // @[Mux.scala:30:73] wire [9:0] schedule_c_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_way; // @[Mux.scala:30:73] wire schedule_c_bits_dirty; // @[Mux.scala:30:73] wire schedule_c_valid; // @[Mux.scala:30:73] wire schedule_d_bits_prio_0; // @[Mux.scala:30:73] wire schedule_d_bits_prio_1; // @[Mux.scala:30:73] wire schedule_d_bits_prio_2; // @[Mux.scala:30:73] wire schedule_d_bits_control; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_opcode; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_param; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_size; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_source; // @[Mux.scala:30:73] wire [12:0] schedule_d_bits_tag; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_offset; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_put; // @[Mux.scala:30:73] wire [9:0] schedule_d_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_way; // @[Mux.scala:30:73] wire schedule_d_bits_bad; // @[Mux.scala:30:73] wire schedule_d_valid; // @[Mux.scala:30:73] wire [2:0] schedule_e_bits_sink; // @[Mux.scala:30:73] wire schedule_e_valid; // @[Mux.scala:30:73] wire schedule_x_valid; // @[Mux.scala:30:73] wire schedule_dir_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] schedule_dir_bits_data_state; // @[Mux.scala:30:73] wire schedule_dir_bits_data_clients; // @[Mux.scala:30:73] wire [12:0] schedule_dir_bits_data_tag; // @[Mux.scala:30:73] wire [9:0] schedule_dir_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_dir_bits_way; // @[Mux.scala:30:73] wire schedule_dir_valid; // @[Mux.scala:30:73] wire schedule_reload; // @[Mux.scala:30:73] wire _schedule_T_7 = _schedule_T & _mshrs_0_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_8 = _schedule_T_1 & _mshrs_1_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_9 = _schedule_T_2 & _mshrs_2_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_10 = _schedule_T_3 & _mshrs_3_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_11 = _schedule_T_4 & _mshrs_4_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_12 = _schedule_T_5 & _mshrs_5_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_13 = _schedule_T_6 & _mshrs_6_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_14 = _schedule_T_7 | _schedule_T_8; // @[Mux.scala:30:73] wire _schedule_T_15 = _schedule_T_14 | _schedule_T_9; // @[Mux.scala:30:73] wire _schedule_T_16 = _schedule_T_15 | _schedule_T_10; // @[Mux.scala:30:73] wire _schedule_T_17 = _schedule_T_16 | _schedule_T_11; // @[Mux.scala:30:73] wire _schedule_T_18 = _schedule_T_17 | _schedule_T_12; // @[Mux.scala:30:73] wire _schedule_T_19 = _schedule_T_18 | _schedule_T_13; // @[Mux.scala:30:73] assign _schedule_WIRE = _schedule_T_19; // @[Mux.scala:30:73] assign schedule_reload = _schedule_WIRE; // @[Mux.scala:30:73] wire _schedule_WIRE_10; // @[Mux.scala:30:73] assign schedule_dir_valid = _schedule_WIRE_1_valid; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_2_set; // @[Mux.scala:30:73] assign schedule_dir_bits_set = _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_2_way; // @[Mux.scala:30:73] assign schedule_dir_bits_way = _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73] assign schedule_dir_bits_data_dirty = _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_2_data_state; // @[Mux.scala:30:73] assign schedule_dir_bits_data_state = _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73] wire _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73] assign schedule_dir_bits_data_clients = _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73] assign schedule_dir_bits_data_tag = _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_9; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_set = _schedule_WIRE_2_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_8; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_way = _schedule_WIRE_2_way; // @[Mux.scala:30:73] wire _schedule_WIRE_3_dirty; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_dirty = _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_3_state; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_state = _schedule_WIRE_2_data_state; // @[Mux.scala:30:73] wire _schedule_WIRE_3_clients; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_clients = _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_3_tag; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_tag = _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73] wire _schedule_WIRE_7; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_dirty = _schedule_WIRE_3_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_6; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_state = _schedule_WIRE_3_state; // @[Mux.scala:30:73] wire _schedule_WIRE_5; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_clients = _schedule_WIRE_3_clients; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_4; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_tag = _schedule_WIRE_3_tag; // @[Mux.scala:30:73] wire [12:0] _schedule_T_20 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_21 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_22 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_23 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_24 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_25 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_26 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_27 = _schedule_T_20 | _schedule_T_21; // @[Mux.scala:30:73] wire [12:0] _schedule_T_28 = _schedule_T_27 | _schedule_T_22; // @[Mux.scala:30:73] wire [12:0] _schedule_T_29 = _schedule_T_28 | _schedule_T_23; // @[Mux.scala:30:73] wire [12:0] _schedule_T_30 = _schedule_T_29 | _schedule_T_24; // @[Mux.scala:30:73] wire [12:0] _schedule_T_31 = _schedule_T_30 | _schedule_T_25; // @[Mux.scala:30:73] wire [12:0] _schedule_T_32 = _schedule_T_31 | _schedule_T_26; // @[Mux.scala:30:73] assign _schedule_WIRE_4 = _schedule_T_32; // @[Mux.scala:30:73] assign _schedule_WIRE_3_tag = _schedule_WIRE_4; // @[Mux.scala:30:73] wire _schedule_T_33 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_34 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_35 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_36 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_37 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_38 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_39 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_40 = _schedule_T_33 | _schedule_T_34; // @[Mux.scala:30:73] wire _schedule_T_41 = _schedule_T_40 | _schedule_T_35; // @[Mux.scala:30:73] wire _schedule_T_42 = _schedule_T_41 | _schedule_T_36; // @[Mux.scala:30:73] wire _schedule_T_43 = _schedule_T_42 | _schedule_T_37; // @[Mux.scala:30:73] wire _schedule_T_44 = _schedule_T_43 | _schedule_T_38; // @[Mux.scala:30:73] wire _schedule_T_45 = _schedule_T_44 | _schedule_T_39; // @[Mux.scala:30:73] assign _schedule_WIRE_5 = _schedule_T_45; // @[Mux.scala:30:73] assign _schedule_WIRE_3_clients = _schedule_WIRE_5; // @[Mux.scala:30:73] wire [1:0] _schedule_T_46 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_47 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_48 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_49 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_50 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_51 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_52 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_53 = _schedule_T_46 | _schedule_T_47; // @[Mux.scala:30:73] wire [1:0] _schedule_T_54 = _schedule_T_53 | _schedule_T_48; // @[Mux.scala:30:73] wire [1:0] _schedule_T_55 = _schedule_T_54 | _schedule_T_49; // @[Mux.scala:30:73] wire [1:0] _schedule_T_56 = _schedule_T_55 | _schedule_T_50; // @[Mux.scala:30:73] wire [1:0] _schedule_T_57 = _schedule_T_56 | _schedule_T_51; // @[Mux.scala:30:73] wire [1:0] _schedule_T_58 = _schedule_T_57 | _schedule_T_52; // @[Mux.scala:30:73] assign _schedule_WIRE_6 = _schedule_T_58; // @[Mux.scala:30:73] assign _schedule_WIRE_3_state = _schedule_WIRE_6; // @[Mux.scala:30:73] wire _schedule_T_59 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_60 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_61 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_62 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_63 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_64 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_65 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_66 = _schedule_T_59 | _schedule_T_60; // @[Mux.scala:30:73] wire _schedule_T_67 = _schedule_T_66 | _schedule_T_61; // @[Mux.scala:30:73] wire _schedule_T_68 = _schedule_T_67 | _schedule_T_62; // @[Mux.scala:30:73] wire _schedule_T_69 = _schedule_T_68 | _schedule_T_63; // @[Mux.scala:30:73] wire _schedule_T_70 = _schedule_T_69 | _schedule_T_64; // @[Mux.scala:30:73] wire _schedule_T_71 = _schedule_T_70 | _schedule_T_65; // @[Mux.scala:30:73] assign _schedule_WIRE_7 = _schedule_T_71; // @[Mux.scala:30:73] assign _schedule_WIRE_3_dirty = _schedule_WIRE_7; // @[Mux.scala:30:73] wire [2:0] _schedule_T_72 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_73 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_74 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_75 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_76 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_77 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_78 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_79 = _schedule_T_72 | _schedule_T_73; // @[Mux.scala:30:73] wire [2:0] _schedule_T_80 = _schedule_T_79 | _schedule_T_74; // @[Mux.scala:30:73] wire [2:0] _schedule_T_81 = _schedule_T_80 | _schedule_T_75; // @[Mux.scala:30:73] wire [2:0] _schedule_T_82 = _schedule_T_81 | _schedule_T_76; // @[Mux.scala:30:73] wire [2:0] _schedule_T_83 = _schedule_T_82 | _schedule_T_77; // @[Mux.scala:30:73] wire [2:0] _schedule_T_84 = _schedule_T_83 | _schedule_T_78; // @[Mux.scala:30:73] assign _schedule_WIRE_8 = _schedule_T_84; // @[Mux.scala:30:73] assign _schedule_WIRE_2_way = _schedule_WIRE_8; // @[Mux.scala:30:73] wire [9:0] _schedule_T_85 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_86 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_87 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_88 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_89 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_90 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_91 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_92 = _schedule_T_85 | _schedule_T_86; // @[Mux.scala:30:73] wire [9:0] _schedule_T_93 = _schedule_T_92 | _schedule_T_87; // @[Mux.scala:30:73] wire [9:0] _schedule_T_94 = _schedule_T_93 | _schedule_T_88; // @[Mux.scala:30:73] wire [9:0] _schedule_T_95 = _schedule_T_94 | _schedule_T_89; // @[Mux.scala:30:73] wire [9:0] _schedule_T_96 = _schedule_T_95 | _schedule_T_90; // @[Mux.scala:30:73] wire [9:0] _schedule_T_97 = _schedule_T_96 | _schedule_T_91; // @[Mux.scala:30:73] assign _schedule_WIRE_9 = _schedule_T_97; // @[Mux.scala:30:73] assign _schedule_WIRE_2_set = _schedule_WIRE_9; // @[Mux.scala:30:73] wire _schedule_T_98 = _schedule_T & _mshrs_0_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_99 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_100 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_101 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_102 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_103 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_104 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_105 = _schedule_T_98 | _schedule_T_99; // @[Mux.scala:30:73] wire _schedule_T_106 = _schedule_T_105 | _schedule_T_100; // @[Mux.scala:30:73] wire _schedule_T_107 = _schedule_T_106 | _schedule_T_101; // @[Mux.scala:30:73] wire _schedule_T_108 = _schedule_T_107 | _schedule_T_102; // @[Mux.scala:30:73] wire _schedule_T_109 = _schedule_T_108 | _schedule_T_103; // @[Mux.scala:30:73] wire _schedule_T_110 = _schedule_T_109 | _schedule_T_104; // @[Mux.scala:30:73] assign _schedule_WIRE_10 = _schedule_T_110; // @[Mux.scala:30:73] assign _schedule_WIRE_1_valid = _schedule_WIRE_10; // @[Mux.scala:30:73] wire _schedule_WIRE_14; // @[Mux.scala:30:73] assign schedule_x_valid = _schedule_WIRE_11_valid; // @[Mux.scala:30:73] wire _schedule_T_124 = _schedule_T & _mshrs_0_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_125 = _schedule_T_1 & _mshrs_1_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_126 = _schedule_T_2 & _mshrs_2_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_127 = _schedule_T_3 & _mshrs_3_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_128 = _schedule_T_4 & _mshrs_4_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_129 = _schedule_T_5 & _mshrs_5_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_130 = _schedule_T_6 & _mshrs_6_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_131 = _schedule_T_124 | _schedule_T_125; // @[Mux.scala:30:73] wire _schedule_T_132 = _schedule_T_131 | _schedule_T_126; // @[Mux.scala:30:73] wire _schedule_T_133 = _schedule_T_132 | _schedule_T_127; // @[Mux.scala:30:73] wire _schedule_T_134 = _schedule_T_133 | _schedule_T_128; // @[Mux.scala:30:73] wire _schedule_T_135 = _schedule_T_134 | _schedule_T_129; // @[Mux.scala:30:73] wire _schedule_T_136 = _schedule_T_135 | _schedule_T_130; // @[Mux.scala:30:73] assign _schedule_WIRE_14 = _schedule_T_136; // @[Mux.scala:30:73] assign _schedule_WIRE_11_valid = _schedule_WIRE_14; // @[Mux.scala:30:73] wire _schedule_WIRE_18; // @[Mux.scala:30:73] assign schedule_e_valid = _schedule_WIRE_15_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_16_sink; // @[Mux.scala:30:73] assign schedule_e_bits_sink = _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_17; // @[Mux.scala:30:73] assign _schedule_WIRE_15_bits_sink = _schedule_WIRE_16_sink; // @[Mux.scala:30:73] wire [2:0] _schedule_T_137 = _schedule_T ? _mshrs_0_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_138 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_139 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_140 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_141 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_142 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_143 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_144 = _schedule_T_137 | _schedule_T_138; // @[Mux.scala:30:73] wire [2:0] _schedule_T_145 = _schedule_T_144 | _schedule_T_139; // @[Mux.scala:30:73] wire [2:0] _schedule_T_146 = _schedule_T_145 | _schedule_T_140; // @[Mux.scala:30:73] wire [2:0] _schedule_T_147 = _schedule_T_146 | _schedule_T_141; // @[Mux.scala:30:73] wire [2:0] _schedule_T_148 = _schedule_T_147 | _schedule_T_142; // @[Mux.scala:30:73] wire [2:0] _schedule_T_149 = _schedule_T_148 | _schedule_T_143; // @[Mux.scala:30:73] assign _schedule_WIRE_17 = _schedule_T_149; // @[Mux.scala:30:73] assign _schedule_WIRE_16_sink = _schedule_WIRE_17; // @[Mux.scala:30:73] wire _schedule_T_150 = _schedule_T & _mshrs_0_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_151 = _schedule_T_1 & _mshrs_1_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_152 = _schedule_T_2 & _mshrs_2_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_153 = _schedule_T_3 & _mshrs_3_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_154 = _schedule_T_4 & _mshrs_4_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_155 = _schedule_T_5 & _mshrs_5_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_156 = _schedule_T_6 & _mshrs_6_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_157 = _schedule_T_150 | _schedule_T_151; // @[Mux.scala:30:73] wire _schedule_T_158 = _schedule_T_157 | _schedule_T_152; // @[Mux.scala:30:73] wire _schedule_T_159 = _schedule_T_158 | _schedule_T_153; // @[Mux.scala:30:73] wire _schedule_T_160 = _schedule_T_159 | _schedule_T_154; // @[Mux.scala:30:73] wire _schedule_T_161 = _schedule_T_160 | _schedule_T_155; // @[Mux.scala:30:73] wire _schedule_T_162 = _schedule_T_161 | _schedule_T_156; // @[Mux.scala:30:73] assign _schedule_WIRE_18 = _schedule_T_162; // @[Mux.scala:30:73] assign _schedule_WIRE_15_valid = _schedule_WIRE_18; // @[Mux.scala:30:73] wire _schedule_WIRE_37; // @[Mux.scala:30:73] assign schedule_d_valid = _schedule_WIRE_19_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73] assign schedule_d_bits_prio_0 = _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73] assign schedule_d_bits_prio_1 = _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73] assign schedule_d_bits_prio_2 = _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_20_control; // @[Mux.scala:30:73] assign schedule_d_bits_control = _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_opcode; // @[Mux.scala:30:73] assign schedule_d_bits_opcode = _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_param; // @[Mux.scala:30:73] assign schedule_d_bits_param = _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_size; // @[Mux.scala:30:73] assign schedule_d_bits_size = _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_source; // @[Mux.scala:30:73] assign schedule_d_bits_source = _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_20_tag; // @[Mux.scala:30:73] assign schedule_d_bits_tag = _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_offset; // @[Mux.scala:30:73] assign schedule_d_bits_offset = _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_put; // @[Mux.scala:30:73] assign schedule_d_bits_put = _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_20_set; // @[Mux.scala:30:73] assign schedule_d_bits_set = _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_way; // @[Mux.scala:30:73] assign schedule_d_bits_way = _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_20_bad; // @[Mux.scala:30:73] assign schedule_d_bits_bad = _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73] wire _schedule_WIRE_33_0; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_0 = _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_33_1; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_1 = _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_33_2; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_2 = _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_32; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_control = _schedule_WIRE_20_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_31; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_opcode = _schedule_WIRE_20_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_30; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_param = _schedule_WIRE_20_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_29; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_size = _schedule_WIRE_20_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_28; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_source = _schedule_WIRE_20_source; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_27; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_tag = _schedule_WIRE_20_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_26; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_offset = _schedule_WIRE_20_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_25; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_put = _schedule_WIRE_20_put; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_24; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_set = _schedule_WIRE_20_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_22; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_way = _schedule_WIRE_20_way; // @[Mux.scala:30:73] wire _schedule_WIRE_21; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_bad = _schedule_WIRE_20_bad; // @[Mux.scala:30:73] wire _schedule_T_163 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_164 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_165 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_166 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_167 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_168 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_169 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_170 = _schedule_T_163 | _schedule_T_164; // @[Mux.scala:30:73] wire _schedule_T_171 = _schedule_T_170 | _schedule_T_165; // @[Mux.scala:30:73] wire _schedule_T_172 = _schedule_T_171 | _schedule_T_166; // @[Mux.scala:30:73] wire _schedule_T_173 = _schedule_T_172 | _schedule_T_167; // @[Mux.scala:30:73] wire _schedule_T_174 = _schedule_T_173 | _schedule_T_168; // @[Mux.scala:30:73] wire _schedule_T_175 = _schedule_T_174 | _schedule_T_169; // @[Mux.scala:30:73] assign _schedule_WIRE_21 = _schedule_T_175; // @[Mux.scala:30:73] assign _schedule_WIRE_20_bad = _schedule_WIRE_21; // @[Mux.scala:30:73] wire [2:0] _schedule_T_176 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_177 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_178 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_179 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_180 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_181 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_182 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_183 = _schedule_T_176 | _schedule_T_177; // @[Mux.scala:30:73] wire [2:0] _schedule_T_184 = _schedule_T_183 | _schedule_T_178; // @[Mux.scala:30:73] wire [2:0] _schedule_T_185 = _schedule_T_184 | _schedule_T_179; // @[Mux.scala:30:73] wire [2:0] _schedule_T_186 = _schedule_T_185 | _schedule_T_180; // @[Mux.scala:30:73] wire [2:0] _schedule_T_187 = _schedule_T_186 | _schedule_T_181; // @[Mux.scala:30:73] wire [2:0] _schedule_T_188 = _schedule_T_187 | _schedule_T_182; // @[Mux.scala:30:73] assign _schedule_WIRE_22 = _schedule_T_188; // @[Mux.scala:30:73] assign _schedule_WIRE_20_way = _schedule_WIRE_22; // @[Mux.scala:30:73] wire [9:0] _schedule_T_202 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_203 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_204 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_205 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_206 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_207 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_208 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_209 = _schedule_T_202 | _schedule_T_203; // @[Mux.scala:30:73] wire [9:0] _schedule_T_210 = _schedule_T_209 | _schedule_T_204; // @[Mux.scala:30:73] wire [9:0] _schedule_T_211 = _schedule_T_210 | _schedule_T_205; // @[Mux.scala:30:73] wire [9:0] _schedule_T_212 = _schedule_T_211 | _schedule_T_206; // @[Mux.scala:30:73] wire [9:0] _schedule_T_213 = _schedule_T_212 | _schedule_T_207; // @[Mux.scala:30:73] wire [9:0] _schedule_T_214 = _schedule_T_213 | _schedule_T_208; // @[Mux.scala:30:73] assign _schedule_WIRE_24 = _schedule_T_214; // @[Mux.scala:30:73] assign _schedule_WIRE_20_set = _schedule_WIRE_24; // @[Mux.scala:30:73] wire [5:0] _schedule_T_215 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_216 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_217 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_218 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_219 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_220 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_221 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_222 = _schedule_T_215 | _schedule_T_216; // @[Mux.scala:30:73] wire [5:0] _schedule_T_223 = _schedule_T_222 | _schedule_T_217; // @[Mux.scala:30:73] wire [5:0] _schedule_T_224 = _schedule_T_223 | _schedule_T_218; // @[Mux.scala:30:73] wire [5:0] _schedule_T_225 = _schedule_T_224 | _schedule_T_219; // @[Mux.scala:30:73] wire [5:0] _schedule_T_226 = _schedule_T_225 | _schedule_T_220; // @[Mux.scala:30:73] wire [5:0] _schedule_T_227 = _schedule_T_226 | _schedule_T_221; // @[Mux.scala:30:73] assign _schedule_WIRE_25 = _schedule_T_227; // @[Mux.scala:30:73] assign _schedule_WIRE_20_put = _schedule_WIRE_25; // @[Mux.scala:30:73] wire [5:0] _schedule_T_228 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_229 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_230 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_231 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_232 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_233 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_234 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_235 = _schedule_T_228 | _schedule_T_229; // @[Mux.scala:30:73] wire [5:0] _schedule_T_236 = _schedule_T_235 | _schedule_T_230; // @[Mux.scala:30:73] wire [5:0] _schedule_T_237 = _schedule_T_236 | _schedule_T_231; // @[Mux.scala:30:73] wire [5:0] _schedule_T_238 = _schedule_T_237 | _schedule_T_232; // @[Mux.scala:30:73] wire [5:0] _schedule_T_239 = _schedule_T_238 | _schedule_T_233; // @[Mux.scala:30:73] wire [5:0] _schedule_T_240 = _schedule_T_239 | _schedule_T_234; // @[Mux.scala:30:73] assign _schedule_WIRE_26 = _schedule_T_240; // @[Mux.scala:30:73] assign _schedule_WIRE_20_offset = _schedule_WIRE_26; // @[Mux.scala:30:73] wire [12:0] _schedule_T_241 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_242 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_243 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_244 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_245 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_246 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_247 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_248 = _schedule_T_241 | _schedule_T_242; // @[Mux.scala:30:73] wire [12:0] _schedule_T_249 = _schedule_T_248 | _schedule_T_243; // @[Mux.scala:30:73] wire [12:0] _schedule_T_250 = _schedule_T_249 | _schedule_T_244; // @[Mux.scala:30:73] wire [12:0] _schedule_T_251 = _schedule_T_250 | _schedule_T_245; // @[Mux.scala:30:73] wire [12:0] _schedule_T_252 = _schedule_T_251 | _schedule_T_246; // @[Mux.scala:30:73] wire [12:0] _schedule_T_253 = _schedule_T_252 | _schedule_T_247; // @[Mux.scala:30:73] assign _schedule_WIRE_27 = _schedule_T_253; // @[Mux.scala:30:73] assign _schedule_WIRE_20_tag = _schedule_WIRE_27; // @[Mux.scala:30:73] wire [5:0] _schedule_T_254 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_255 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_256 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_257 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_258 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_259 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_260 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_261 = _schedule_T_254 | _schedule_T_255; // @[Mux.scala:30:73] wire [5:0] _schedule_T_262 = _schedule_T_261 | _schedule_T_256; // @[Mux.scala:30:73] wire [5:0] _schedule_T_263 = _schedule_T_262 | _schedule_T_257; // @[Mux.scala:30:73] wire [5:0] _schedule_T_264 = _schedule_T_263 | _schedule_T_258; // @[Mux.scala:30:73] wire [5:0] _schedule_T_265 = _schedule_T_264 | _schedule_T_259; // @[Mux.scala:30:73] wire [5:0] _schedule_T_266 = _schedule_T_265 | _schedule_T_260; // @[Mux.scala:30:73] assign _schedule_WIRE_28 = _schedule_T_266; // @[Mux.scala:30:73] assign _schedule_WIRE_20_source = _schedule_WIRE_28; // @[Mux.scala:30:73] wire [2:0] _schedule_T_267 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_268 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_269 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_270 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_271 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_272 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_273 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_274 = _schedule_T_267 | _schedule_T_268; // @[Mux.scala:30:73] wire [2:0] _schedule_T_275 = _schedule_T_274 | _schedule_T_269; // @[Mux.scala:30:73] wire [2:0] _schedule_T_276 = _schedule_T_275 | _schedule_T_270; // @[Mux.scala:30:73] wire [2:0] _schedule_T_277 = _schedule_T_276 | _schedule_T_271; // @[Mux.scala:30:73] wire [2:0] _schedule_T_278 = _schedule_T_277 | _schedule_T_272; // @[Mux.scala:30:73] wire [2:0] _schedule_T_279 = _schedule_T_278 | _schedule_T_273; // @[Mux.scala:30:73] assign _schedule_WIRE_29 = _schedule_T_279; // @[Mux.scala:30:73] assign _schedule_WIRE_20_size = _schedule_WIRE_29; // @[Mux.scala:30:73] wire [2:0] _schedule_T_280 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_281 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_282 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_283 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_284 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_285 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_286 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_287 = _schedule_T_280 | _schedule_T_281; // @[Mux.scala:30:73] wire [2:0] _schedule_T_288 = _schedule_T_287 | _schedule_T_282; // @[Mux.scala:30:73] wire [2:0] _schedule_T_289 = _schedule_T_288 | _schedule_T_283; // @[Mux.scala:30:73] wire [2:0] _schedule_T_290 = _schedule_T_289 | _schedule_T_284; // @[Mux.scala:30:73] wire [2:0] _schedule_T_291 = _schedule_T_290 | _schedule_T_285; // @[Mux.scala:30:73] wire [2:0] _schedule_T_292 = _schedule_T_291 | _schedule_T_286; // @[Mux.scala:30:73] assign _schedule_WIRE_30 = _schedule_T_292; // @[Mux.scala:30:73] assign _schedule_WIRE_20_param = _schedule_WIRE_30; // @[Mux.scala:30:73] wire [2:0] _schedule_T_293 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_294 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_295 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_296 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_297 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_298 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_299 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_300 = _schedule_T_293 | _schedule_T_294; // @[Mux.scala:30:73] wire [2:0] _schedule_T_301 = _schedule_T_300 | _schedule_T_295; // @[Mux.scala:30:73] wire [2:0] _schedule_T_302 = _schedule_T_301 | _schedule_T_296; // @[Mux.scala:30:73] wire [2:0] _schedule_T_303 = _schedule_T_302 | _schedule_T_297; // @[Mux.scala:30:73] wire [2:0] _schedule_T_304 = _schedule_T_303 | _schedule_T_298; // @[Mux.scala:30:73] wire [2:0] _schedule_T_305 = _schedule_T_304 | _schedule_T_299; // @[Mux.scala:30:73] assign _schedule_WIRE_31 = _schedule_T_305; // @[Mux.scala:30:73] assign _schedule_WIRE_20_opcode = _schedule_WIRE_31; // @[Mux.scala:30:73] wire _schedule_T_306 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_307 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_308 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_309 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_310 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_311 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_312 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_313 = _schedule_T_306 | _schedule_T_307; // @[Mux.scala:30:73] wire _schedule_T_314 = _schedule_T_313 | _schedule_T_308; // @[Mux.scala:30:73] wire _schedule_T_315 = _schedule_T_314 | _schedule_T_309; // @[Mux.scala:30:73] wire _schedule_T_316 = _schedule_T_315 | _schedule_T_310; // @[Mux.scala:30:73] wire _schedule_T_317 = _schedule_T_316 | _schedule_T_311; // @[Mux.scala:30:73] wire _schedule_T_318 = _schedule_T_317 | _schedule_T_312; // @[Mux.scala:30:73] assign _schedule_WIRE_32 = _schedule_T_318; // @[Mux.scala:30:73] assign _schedule_WIRE_20_control = _schedule_WIRE_32; // @[Mux.scala:30:73] wire _schedule_WIRE_34; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_0 = _schedule_WIRE_33_0; // @[Mux.scala:30:73] wire _schedule_WIRE_35; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_1 = _schedule_WIRE_33_1; // @[Mux.scala:30:73] wire _schedule_WIRE_36; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_2 = _schedule_WIRE_33_2; // @[Mux.scala:30:73] wire _schedule_T_319 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_320 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_321 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_322 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_323 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_326 = _schedule_T_319 | _schedule_T_320; // @[Mux.scala:30:73] wire _schedule_T_327 = _schedule_T_326 | _schedule_T_321; // @[Mux.scala:30:73] wire _schedule_T_328 = _schedule_T_327 | _schedule_T_322; // @[Mux.scala:30:73] wire _schedule_T_329 = _schedule_T_328 | _schedule_T_323; // @[Mux.scala:30:73] wire _schedule_T_330 = _schedule_T_329; // @[Mux.scala:30:73] wire _schedule_T_331 = _schedule_T_330; // @[Mux.scala:30:73] assign _schedule_WIRE_34 = _schedule_T_331; // @[Mux.scala:30:73] assign _schedule_WIRE_33_0 = _schedule_WIRE_34; // @[Mux.scala:30:73] wire _schedule_T_332 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_333 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_334 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_335 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_336 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_337 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_339 = _schedule_T_332 | _schedule_T_333; // @[Mux.scala:30:73] wire _schedule_T_340 = _schedule_T_339 | _schedule_T_334; // @[Mux.scala:30:73] wire _schedule_T_341 = _schedule_T_340 | _schedule_T_335; // @[Mux.scala:30:73] wire _schedule_T_342 = _schedule_T_341 | _schedule_T_336; // @[Mux.scala:30:73] wire _schedule_T_343 = _schedule_T_342 | _schedule_T_337; // @[Mux.scala:30:73] wire _schedule_T_344 = _schedule_T_343; // @[Mux.scala:30:73] assign _schedule_WIRE_35 = _schedule_T_344; // @[Mux.scala:30:73] assign _schedule_WIRE_33_1 = _schedule_WIRE_35; // @[Mux.scala:30:73] wire _schedule_T_345 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_346 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_347 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_348 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_349 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_350 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_351 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_352 = _schedule_T_345 | _schedule_T_346; // @[Mux.scala:30:73] wire _schedule_T_353 = _schedule_T_352 | _schedule_T_347; // @[Mux.scala:30:73] wire _schedule_T_354 = _schedule_T_353 | _schedule_T_348; // @[Mux.scala:30:73] wire _schedule_T_355 = _schedule_T_354 | _schedule_T_349; // @[Mux.scala:30:73] wire _schedule_T_356 = _schedule_T_355 | _schedule_T_350; // @[Mux.scala:30:73] wire _schedule_T_357 = _schedule_T_356 | _schedule_T_351; // @[Mux.scala:30:73] assign _schedule_WIRE_36 = _schedule_T_357; // @[Mux.scala:30:73] assign _schedule_WIRE_33_2 = _schedule_WIRE_36; // @[Mux.scala:30:73] wire _schedule_T_358 = _schedule_T & _mshrs_0_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_359 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_360 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_361 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_362 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_363 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_364 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_365 = _schedule_T_358 | _schedule_T_359; // @[Mux.scala:30:73] wire _schedule_T_366 = _schedule_T_365 | _schedule_T_360; // @[Mux.scala:30:73] wire _schedule_T_367 = _schedule_T_366 | _schedule_T_361; // @[Mux.scala:30:73] wire _schedule_T_368 = _schedule_T_367 | _schedule_T_362; // @[Mux.scala:30:73] wire _schedule_T_369 = _schedule_T_368 | _schedule_T_363; // @[Mux.scala:30:73] wire _schedule_T_370 = _schedule_T_369 | _schedule_T_364; // @[Mux.scala:30:73] assign _schedule_WIRE_37 = _schedule_T_370; // @[Mux.scala:30:73] assign _schedule_WIRE_19_valid = _schedule_WIRE_37; // @[Mux.scala:30:73] wire _schedule_WIRE_47; // @[Mux.scala:30:73] assign schedule_c_valid = _schedule_WIRE_38_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_opcode; // @[Mux.scala:30:73] assign schedule_c_bits_opcode = _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_param; // @[Mux.scala:30:73] assign schedule_c_bits_param = _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_39_tag; // @[Mux.scala:30:73] assign schedule_c_bits_tag = _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_39_set; // @[Mux.scala:30:73] assign schedule_c_bits_set = _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_way; // @[Mux.scala:30:73] assign schedule_c_bits_way = _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_39_dirty; // @[Mux.scala:30:73] assign schedule_c_bits_dirty = _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_46; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_opcode = _schedule_WIRE_39_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_45; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_param = _schedule_WIRE_39_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_43; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_tag = _schedule_WIRE_39_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_42; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_set = _schedule_WIRE_39_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_41; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_way = _schedule_WIRE_39_way; // @[Mux.scala:30:73] wire _schedule_WIRE_40; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_dirty = _schedule_WIRE_39_dirty; // @[Mux.scala:30:73] wire _schedule_T_371 = _schedule_T & _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_372 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_373 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_374 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_375 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_376 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_377 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_378 = _schedule_T_371 | _schedule_T_372; // @[Mux.scala:30:73] wire _schedule_T_379 = _schedule_T_378 | _schedule_T_373; // @[Mux.scala:30:73] wire _schedule_T_380 = _schedule_T_379 | _schedule_T_374; // @[Mux.scala:30:73] wire _schedule_T_381 = _schedule_T_380 | _schedule_T_375; // @[Mux.scala:30:73] wire _schedule_T_382 = _schedule_T_381 | _schedule_T_376; // @[Mux.scala:30:73] wire _schedule_T_383 = _schedule_T_382 | _schedule_T_377; // @[Mux.scala:30:73] assign _schedule_WIRE_40 = _schedule_T_383; // @[Mux.scala:30:73] assign _schedule_WIRE_39_dirty = _schedule_WIRE_40; // @[Mux.scala:30:73] wire [2:0] _schedule_T_384 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_385 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_386 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_387 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_388 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_389 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_390 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_391 = _schedule_T_384 | _schedule_T_385; // @[Mux.scala:30:73] wire [2:0] _schedule_T_392 = _schedule_T_391 | _schedule_T_386; // @[Mux.scala:30:73] wire [2:0] _schedule_T_393 = _schedule_T_392 | _schedule_T_387; // @[Mux.scala:30:73] wire [2:0] _schedule_T_394 = _schedule_T_393 | _schedule_T_388; // @[Mux.scala:30:73] wire [2:0] _schedule_T_395 = _schedule_T_394 | _schedule_T_389; // @[Mux.scala:30:73] wire [2:0] _schedule_T_396 = _schedule_T_395 | _schedule_T_390; // @[Mux.scala:30:73] assign _schedule_WIRE_41 = _schedule_T_396; // @[Mux.scala:30:73] assign _schedule_WIRE_39_way = _schedule_WIRE_41; // @[Mux.scala:30:73] wire [9:0] _schedule_T_397 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_398 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_399 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_400 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_401 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_402 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_403 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_404 = _schedule_T_397 | _schedule_T_398; // @[Mux.scala:30:73] wire [9:0] _schedule_T_405 = _schedule_T_404 | _schedule_T_399; // @[Mux.scala:30:73] wire [9:0] _schedule_T_406 = _schedule_T_405 | _schedule_T_400; // @[Mux.scala:30:73] wire [9:0] _schedule_T_407 = _schedule_T_406 | _schedule_T_401; // @[Mux.scala:30:73] wire [9:0] _schedule_T_408 = _schedule_T_407 | _schedule_T_402; // @[Mux.scala:30:73] wire [9:0] _schedule_T_409 = _schedule_T_408 | _schedule_T_403; // @[Mux.scala:30:73] assign _schedule_WIRE_42 = _schedule_T_409; // @[Mux.scala:30:73] assign _schedule_WIRE_39_set = _schedule_WIRE_42; // @[Mux.scala:30:73] wire [12:0] _schedule_T_410 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_411 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_412 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_413 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_414 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_415 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_416 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_417 = _schedule_T_410 | _schedule_T_411; // @[Mux.scala:30:73] wire [12:0] _schedule_T_418 = _schedule_T_417 | _schedule_T_412; // @[Mux.scala:30:73] wire [12:0] _schedule_T_419 = _schedule_T_418 | _schedule_T_413; // @[Mux.scala:30:73] wire [12:0] _schedule_T_420 = _schedule_T_419 | _schedule_T_414; // @[Mux.scala:30:73] wire [12:0] _schedule_T_421 = _schedule_T_420 | _schedule_T_415; // @[Mux.scala:30:73] wire [12:0] _schedule_T_422 = _schedule_T_421 | _schedule_T_416; // @[Mux.scala:30:73] assign _schedule_WIRE_43 = _schedule_T_422; // @[Mux.scala:30:73] assign _schedule_WIRE_39_tag = _schedule_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _schedule_T_436 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_437 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_438 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_439 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_440 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_441 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_442 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_443 = _schedule_T_436 | _schedule_T_437; // @[Mux.scala:30:73] wire [2:0] _schedule_T_444 = _schedule_T_443 | _schedule_T_438; // @[Mux.scala:30:73] wire [2:0] _schedule_T_445 = _schedule_T_444 | _schedule_T_439; // @[Mux.scala:30:73] wire [2:0] _schedule_T_446 = _schedule_T_445 | _schedule_T_440; // @[Mux.scala:30:73] wire [2:0] _schedule_T_447 = _schedule_T_446 | _schedule_T_441; // @[Mux.scala:30:73] wire [2:0] _schedule_T_448 = _schedule_T_447 | _schedule_T_442; // @[Mux.scala:30:73] assign _schedule_WIRE_45 = _schedule_T_448; // @[Mux.scala:30:73] assign _schedule_WIRE_39_param = _schedule_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _schedule_T_449 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_450 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_451 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_452 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_453 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_454 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_455 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_456 = _schedule_T_449 | _schedule_T_450; // @[Mux.scala:30:73] wire [2:0] _schedule_T_457 = _schedule_T_456 | _schedule_T_451; // @[Mux.scala:30:73] wire [2:0] _schedule_T_458 = _schedule_T_457 | _schedule_T_452; // @[Mux.scala:30:73] wire [2:0] _schedule_T_459 = _schedule_T_458 | _schedule_T_453; // @[Mux.scala:30:73] wire [2:0] _schedule_T_460 = _schedule_T_459 | _schedule_T_454; // @[Mux.scala:30:73] wire [2:0] _schedule_T_461 = _schedule_T_460 | _schedule_T_455; // @[Mux.scala:30:73] assign _schedule_WIRE_46 = _schedule_T_461; // @[Mux.scala:30:73] assign _schedule_WIRE_39_opcode = _schedule_WIRE_46; // @[Mux.scala:30:73] wire _schedule_T_462 = _schedule_T & _mshrs_0_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_463 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_464 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_465 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_466 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_467 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_468 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_469 = _schedule_T_462 | _schedule_T_463; // @[Mux.scala:30:73] wire _schedule_T_470 = _schedule_T_469 | _schedule_T_464; // @[Mux.scala:30:73] wire _schedule_T_471 = _schedule_T_470 | _schedule_T_465; // @[Mux.scala:30:73] wire _schedule_T_472 = _schedule_T_471 | _schedule_T_466; // @[Mux.scala:30:73] wire _schedule_T_473 = _schedule_T_472 | _schedule_T_467; // @[Mux.scala:30:73] wire _schedule_T_474 = _schedule_T_473 | _schedule_T_468; // @[Mux.scala:30:73] assign _schedule_WIRE_47 = _schedule_T_474; // @[Mux.scala:30:73] assign _schedule_WIRE_38_valid = _schedule_WIRE_47; // @[Mux.scala:30:73] wire _schedule_WIRE_54; // @[Mux.scala:30:73] assign schedule_b_valid = _schedule_WIRE_48_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_49_param; // @[Mux.scala:30:73] assign schedule_b_bits_param = _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_49_tag; // @[Mux.scala:30:73] assign schedule_b_bits_tag = _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_49_set; // @[Mux.scala:30:73] assign schedule_b_bits_set = _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73] wire _schedule_WIRE_49_clients; // @[Mux.scala:30:73] assign schedule_b_bits_clients = _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_53; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_param = _schedule_WIRE_49_param; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_52; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_tag = _schedule_WIRE_49_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_51; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_set = _schedule_WIRE_49_set; // @[Mux.scala:30:73] wire _schedule_WIRE_50; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_clients = _schedule_WIRE_49_clients; // @[Mux.scala:30:73] wire _schedule_T_475 = _schedule_T & _mshrs_0_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_476 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_477 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_478 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_479 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_480 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_481 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_482 = _schedule_T_475 | _schedule_T_476; // @[Mux.scala:30:73] wire _schedule_T_483 = _schedule_T_482 | _schedule_T_477; // @[Mux.scala:30:73] wire _schedule_T_484 = _schedule_T_483 | _schedule_T_478; // @[Mux.scala:30:73] wire _schedule_T_485 = _schedule_T_484 | _schedule_T_479; // @[Mux.scala:30:73] wire _schedule_T_486 = _schedule_T_485 | _schedule_T_480; // @[Mux.scala:30:73] wire _schedule_T_487 = _schedule_T_486 | _schedule_T_481; // @[Mux.scala:30:73] assign _schedule_WIRE_50 = _schedule_T_487; // @[Mux.scala:30:73] assign _schedule_WIRE_49_clients = _schedule_WIRE_50; // @[Mux.scala:30:73] wire [9:0] _schedule_T_488 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_489 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_490 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_491 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_492 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_493 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_494 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_495 = _schedule_T_488 | _schedule_T_489; // @[Mux.scala:30:73] wire [9:0] _schedule_T_496 = _schedule_T_495 | _schedule_T_490; // @[Mux.scala:30:73] wire [9:0] _schedule_T_497 = _schedule_T_496 | _schedule_T_491; // @[Mux.scala:30:73] wire [9:0] _schedule_T_498 = _schedule_T_497 | _schedule_T_492; // @[Mux.scala:30:73] wire [9:0] _schedule_T_499 = _schedule_T_498 | _schedule_T_493; // @[Mux.scala:30:73] wire [9:0] _schedule_T_500 = _schedule_T_499 | _schedule_T_494; // @[Mux.scala:30:73] assign _schedule_WIRE_51 = _schedule_T_500; // @[Mux.scala:30:73] assign _schedule_WIRE_49_set = _schedule_WIRE_51; // @[Mux.scala:30:73] wire [12:0] _schedule_T_501 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_502 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_503 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_504 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_505 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_506 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_507 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_508 = _schedule_T_501 | _schedule_T_502; // @[Mux.scala:30:73] wire [12:0] _schedule_T_509 = _schedule_T_508 | _schedule_T_503; // @[Mux.scala:30:73] wire [12:0] _schedule_T_510 = _schedule_T_509 | _schedule_T_504; // @[Mux.scala:30:73] wire [12:0] _schedule_T_511 = _schedule_T_510 | _schedule_T_505; // @[Mux.scala:30:73] wire [12:0] _schedule_T_512 = _schedule_T_511 | _schedule_T_506; // @[Mux.scala:30:73] wire [12:0] _schedule_T_513 = _schedule_T_512 | _schedule_T_507; // @[Mux.scala:30:73] assign _schedule_WIRE_52 = _schedule_T_513; // @[Mux.scala:30:73] assign _schedule_WIRE_49_tag = _schedule_WIRE_52; // @[Mux.scala:30:73] wire [2:0] _schedule_T_514 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_515 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_516 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_517 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_518 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_519 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_520 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_521 = _schedule_T_514 | _schedule_T_515; // @[Mux.scala:30:73] wire [2:0] _schedule_T_522 = _schedule_T_521 | _schedule_T_516; // @[Mux.scala:30:73] wire [2:0] _schedule_T_523 = _schedule_T_522 | _schedule_T_517; // @[Mux.scala:30:73] wire [2:0] _schedule_T_524 = _schedule_T_523 | _schedule_T_518; // @[Mux.scala:30:73] wire [2:0] _schedule_T_525 = _schedule_T_524 | _schedule_T_519; // @[Mux.scala:30:73] wire [2:0] _schedule_T_526 = _schedule_T_525 | _schedule_T_520; // @[Mux.scala:30:73] assign _schedule_WIRE_53 = _schedule_T_526; // @[Mux.scala:30:73] assign _schedule_WIRE_49_param = _schedule_WIRE_53; // @[Mux.scala:30:73] wire _schedule_T_527 = _schedule_T & _mshrs_0_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_528 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_529 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_530 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_531 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_532 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_533 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_534 = _schedule_T_527 | _schedule_T_528; // @[Mux.scala:30:73] wire _schedule_T_535 = _schedule_T_534 | _schedule_T_529; // @[Mux.scala:30:73] wire _schedule_T_536 = _schedule_T_535 | _schedule_T_530; // @[Mux.scala:30:73] wire _schedule_T_537 = _schedule_T_536 | _schedule_T_531; // @[Mux.scala:30:73] wire _schedule_T_538 = _schedule_T_537 | _schedule_T_532; // @[Mux.scala:30:73] wire _schedule_T_539 = _schedule_T_538 | _schedule_T_533; // @[Mux.scala:30:73] assign _schedule_WIRE_54 = _schedule_T_539; // @[Mux.scala:30:73] assign _schedule_WIRE_48_valid = _schedule_WIRE_54; // @[Mux.scala:30:73] wire _schedule_WIRE_62; // @[Mux.scala:30:73] assign schedule_a_valid = _schedule_WIRE_55_valid; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_56_tag; // @[Mux.scala:30:73] assign schedule_a_bits_tag = _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_56_set; // @[Mux.scala:30:73] assign schedule_a_bits_set = _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_56_param; // @[Mux.scala:30:73] assign schedule_a_bits_param = _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73] wire _schedule_WIRE_56_block; // @[Mux.scala:30:73] assign schedule_a_bits_block = _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73] wire [12:0] _schedule_WIRE_61; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_tag = _schedule_WIRE_56_tag; // @[Mux.scala:30:73] wire [9:0] _schedule_WIRE_60; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_set = _schedule_WIRE_56_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_59; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_param = _schedule_WIRE_56_param; // @[Mux.scala:30:73] wire _schedule_WIRE_57; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_block = _schedule_WIRE_56_block; // @[Mux.scala:30:73] wire _schedule_T_540 = _schedule_T & _mshrs_0_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_541 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_542 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_543 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_544 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_545 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_546 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_547 = _schedule_T_540 | _schedule_T_541; // @[Mux.scala:30:73] wire _schedule_T_548 = _schedule_T_547 | _schedule_T_542; // @[Mux.scala:30:73] wire _schedule_T_549 = _schedule_T_548 | _schedule_T_543; // @[Mux.scala:30:73] wire _schedule_T_550 = _schedule_T_549 | _schedule_T_544; // @[Mux.scala:30:73] wire _schedule_T_551 = _schedule_T_550 | _schedule_T_545; // @[Mux.scala:30:73] wire _schedule_T_552 = _schedule_T_551 | _schedule_T_546; // @[Mux.scala:30:73] assign _schedule_WIRE_57 = _schedule_T_552; // @[Mux.scala:30:73] assign _schedule_WIRE_56_block = _schedule_WIRE_57; // @[Mux.scala:30:73] wire [2:0] _schedule_T_566 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_567 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_568 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_569 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_570 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_571 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_572 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_573 = _schedule_T_566 | _schedule_T_567; // @[Mux.scala:30:73] wire [2:0] _schedule_T_574 = _schedule_T_573 | _schedule_T_568; // @[Mux.scala:30:73] wire [2:0] _schedule_T_575 = _schedule_T_574 | _schedule_T_569; // @[Mux.scala:30:73] wire [2:0] _schedule_T_576 = _schedule_T_575 | _schedule_T_570; // @[Mux.scala:30:73] wire [2:0] _schedule_T_577 = _schedule_T_576 | _schedule_T_571; // @[Mux.scala:30:73] wire [2:0] _schedule_T_578 = _schedule_T_577 | _schedule_T_572; // @[Mux.scala:30:73] assign _schedule_WIRE_59 = _schedule_T_578; // @[Mux.scala:30:73] assign _schedule_WIRE_56_param = _schedule_WIRE_59; // @[Mux.scala:30:73] wire [9:0] _schedule_T_579 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_580 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_581 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_582 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_583 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_584 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_585 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _schedule_T_586 = _schedule_T_579 | _schedule_T_580; // @[Mux.scala:30:73] wire [9:0] _schedule_T_587 = _schedule_T_586 | _schedule_T_581; // @[Mux.scala:30:73] wire [9:0] _schedule_T_588 = _schedule_T_587 | _schedule_T_582; // @[Mux.scala:30:73] wire [9:0] _schedule_T_589 = _schedule_T_588 | _schedule_T_583; // @[Mux.scala:30:73] wire [9:0] _schedule_T_590 = _schedule_T_589 | _schedule_T_584; // @[Mux.scala:30:73] wire [9:0] _schedule_T_591 = _schedule_T_590 | _schedule_T_585; // @[Mux.scala:30:73] assign _schedule_WIRE_60 = _schedule_T_591; // @[Mux.scala:30:73] assign _schedule_WIRE_56_set = _schedule_WIRE_60; // @[Mux.scala:30:73] wire [12:0] _schedule_T_592 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_593 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_594 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_595 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_596 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_597 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_598 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _schedule_T_599 = _schedule_T_592 | _schedule_T_593; // @[Mux.scala:30:73] wire [12:0] _schedule_T_600 = _schedule_T_599 | _schedule_T_594; // @[Mux.scala:30:73] wire [12:0] _schedule_T_601 = _schedule_T_600 | _schedule_T_595; // @[Mux.scala:30:73] wire [12:0] _schedule_T_602 = _schedule_T_601 | _schedule_T_596; // @[Mux.scala:30:73] wire [12:0] _schedule_T_603 = _schedule_T_602 | _schedule_T_597; // @[Mux.scala:30:73] wire [12:0] _schedule_T_604 = _schedule_T_603 | _schedule_T_598; // @[Mux.scala:30:73] assign _schedule_WIRE_61 = _schedule_T_604; // @[Mux.scala:30:73] assign _schedule_WIRE_56_tag = _schedule_WIRE_61; // @[Mux.scala:30:73] wire _schedule_T_605 = _schedule_T & _mshrs_0_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_606 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_607 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_608 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_609 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_610 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_611 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_612 = _schedule_T_605 | _schedule_T_606; // @[Mux.scala:30:73] wire _schedule_T_613 = _schedule_T_612 | _schedule_T_607; // @[Mux.scala:30:73] wire _schedule_T_614 = _schedule_T_613 | _schedule_T_608; // @[Mux.scala:30:73] wire _schedule_T_615 = _schedule_T_614 | _schedule_T_609; // @[Mux.scala:30:73] wire _schedule_T_616 = _schedule_T_615 | _schedule_T_610; // @[Mux.scala:30:73] wire _schedule_T_617 = _schedule_T_616 | _schedule_T_611; // @[Mux.scala:30:73] assign _schedule_WIRE_62 = _schedule_T_617; // @[Mux.scala:30:73] assign _schedule_WIRE_55_valid = _schedule_WIRE_62; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_7 = _scheduleTag_T ? _mshrs_0_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_8 = _scheduleTag_T_1 ? _mshrs_1_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_9 = _scheduleTag_T_2 ? _mshrs_2_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_10 = _scheduleTag_T_3 ? _mshrs_3_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_11 = _scheduleTag_T_4 ? _mshrs_4_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_12 = _scheduleTag_T_5 ? _mshrs_5_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_13 = _scheduleTag_T_6 ? _mshrs_6_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _scheduleTag_T_14 = _scheduleTag_T_7 | _scheduleTag_T_8; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_15 = _scheduleTag_T_14 | _scheduleTag_T_9; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_16 = _scheduleTag_T_15 | _scheduleTag_T_10; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_17 = _scheduleTag_T_16 | _scheduleTag_T_11; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_18 = _scheduleTag_T_17 | _scheduleTag_T_12; // @[Mux.scala:30:73] wire [12:0] _scheduleTag_T_19 = _scheduleTag_T_18 | _scheduleTag_T_13; // @[Mux.scala:30:73] wire [12:0] scheduleTag = _scheduleTag_T_19; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_7 = _scheduleSet_T ? _mshrs_0_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_8 = _scheduleSet_T_1 ? _mshrs_1_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_9 = _scheduleSet_T_2 ? _mshrs_2_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_10 = _scheduleSet_T_3 ? _mshrs_3_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_11 = _scheduleSet_T_4 ? _mshrs_4_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_12 = _scheduleSet_T_5 ? _mshrs_5_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_13 = _scheduleSet_T_6 ? _mshrs_6_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36] wire [9:0] _scheduleSet_T_14 = _scheduleSet_T_7 | _scheduleSet_T_8; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_15 = _scheduleSet_T_14 | _scheduleSet_T_9; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_16 = _scheduleSet_T_15 | _scheduleSet_T_10; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_17 = _scheduleSet_T_16 | _scheduleSet_T_11; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_18 = _scheduleSet_T_17 | _scheduleSet_T_12; // @[Mux.scala:30:73] wire [9:0] _scheduleSet_T_19 = _scheduleSet_T_18 | _scheduleSet_T_13; // @[Mux.scala:30:73] wire [9:0] scheduleSet = _scheduleSet_T_19; // @[Mux.scala:30:73] wire [5:0] _robin_filter_T = mshr_selectOH[6:1]; // @[package.scala:262:48] wire [6:0] _robin_filter_T_1 = {mshr_selectOH[6], mshr_selectOH[5:0] | _robin_filter_T}; // @[Mux.scala:32:36] wire [4:0] _robin_filter_T_2 = _robin_filter_T_1[6:2]; // @[package.scala:262:{43,48}] wire [6:0] _robin_filter_T_3 = {_robin_filter_T_1[6:5], _robin_filter_T_1[4:0] | _robin_filter_T_2}; // @[package.scala:262:{43,48}] wire [2:0] _robin_filter_T_4 = _robin_filter_T_3[6:4]; // @[package.scala:262:{43,48}] wire [6:0] _robin_filter_T_5 = {_robin_filter_T_3[6:3], _robin_filter_T_3[2:0] | _robin_filter_T_4}; // @[package.scala:262:{43,48}] wire [6:0] _robin_filter_T_6 = _robin_filter_T_5; // @[package.scala:262:43, :263:17] wire [6:0] _robin_filter_T_7 = ~_robin_filter_T_6; // @[package.scala:263:17] wire _schedule_c_bits_source_T = schedule_c_bits_opcode[1]; // @[Mux.scala:30:73] assign _schedule_c_bits_source_T_1 = _schedule_c_bits_source_T ? mshr_select : 3'h0; // @[OneHot.scala:32:10] assign schedule_c_bits_source = _schedule_c_bits_source_T_1; // @[Mux.scala:30:73] assign _nestedwb_set_T = select_c ? _mshrs_6_io_status_bits_set : _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :153:32, :155:24] assign nestedwb_set = _nestedwb_set_T; // @[Scheduler.scala:75:22, :155:24] assign _nestedwb_tag_T = select_c ? _mshrs_6_io_status_bits_tag : _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :153:32, :156:24] assign nestedwb_tag = _nestedwb_tag_T; // @[Scheduler.scala:75:22, :156:24] wire _GEN = select_bc & _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :154:32, :157:37] wire _nestedwb_b_toN_T; // @[Scheduler.scala:157:37] assign _nestedwb_b_toN_T = _GEN; // @[Scheduler.scala:157:37] wire _nestedwb_b_toB_T; // @[Scheduler.scala:158:37] assign _nestedwb_b_toB_T = _GEN; // @[Scheduler.scala:157:37, :158:37] assign _nestedwb_b_clr_dirty_T = _GEN; // @[Scheduler.scala:157:37, :159:37] wire _nestedwb_b_toN_T_1 = _mshrs_5_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala:71:46, :157:123] assign _nestedwb_b_toN_T_2 = _nestedwb_b_toN_T & _nestedwb_b_toN_T_1; // @[Scheduler.scala:157:{37,75,123}] assign nestedwb_b_toN = _nestedwb_b_toN_T_2; // @[Scheduler.scala:75:22, :157:75] wire _nestedwb_b_toB_T_1 = _mshrs_5_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala:71:46, :158:123] assign _nestedwb_b_toB_T_2 = _nestedwb_b_toB_T & _nestedwb_b_toB_T_1; // @[Scheduler.scala:158:{37,75,123}] assign nestedwb_b_toB = _nestedwb_b_toB_T_2; // @[Scheduler.scala:75:22, :158:75] assign nestedwb_b_clr_dirty = _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:75:22, :159:37] wire _nestedwb_c_set_dirty_T = select_c & _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :153:32, :160:37] assign _nestedwb_c_set_dirty_T_1 = _nestedwb_c_set_dirty_T & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46, :160:{37,75}] assign nestedwb_c_set_dirty = _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:75:22, :160:75] wire _request_ready_T_2; // @[Scheduler.scala:261:40] wire _request_valid_T_2; // @[Scheduler.scala:164:39] wire _request_bits_T_1_prio_0; // @[Scheduler.scala:165:22] wire _view__WIRE_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _request_bits_T_1_prio_2; // @[Scheduler.scala:165:22] wire _request_bits_T_1_control; // @[Scheduler.scala:165:22] wire _view__WIRE_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_opcode; // @[Scheduler.scala:165:22] wire _view__WIRE_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_param; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_size; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_source; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _request_bits_T_1_tag; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_offset; // @[Scheduler.scala:165:22] wire [12:0] _view__WIRE_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_1_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_2_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_3_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_4_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_5_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [12:0] _view__WIRE_6_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_put; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [9:0] _request_bits_T_1_set; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [9:0] request_bits_set; // @[Scheduler.scala:163:21] wire request_ready; // @[Scheduler.scala:163:21] wire request_valid; // @[Scheduler.scala:163:21] wire _request_valid_T = _sinkA_io_req_valid | _sinkX_io_req_valid; // @[Scheduler.scala:54:21, :58:21, :164:62] wire _request_valid_T_1 = _request_valid_T | _sinkC_io_req_valid; // @[Scheduler.scala:55:21, :164:{62,84}] assign _request_valid_T_2 = _directory_io_ready & _request_valid_T_1; // @[Scheduler.scala:68:25, :164:{39,84}] assign request_valid = _request_valid_T_2; // @[Scheduler.scala:163:21, :164:39] wire [2:0] _request_bits_T_opcode = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [2:0] _request_bits_T_param = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [2:0] _request_bits_T_size = _sinkX_io_req_valid ? 3'h6 : _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_source = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [12:0] _request_bits_T_tag = _sinkX_io_req_valid ? _sinkX_io_req_bits_tag : _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_offset = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_put = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [9:0] _request_bits_T_set = _sinkX_io_req_valid ? _sinkX_io_req_bits_set : _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21, :58:21, :166:22] wire _request_bits_T_control; // @[Scheduler.scala:166:22] assign _request_bits_T_1_control = ~_sinkC_io_req_valid & _request_bits_T_control; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_opcode = _sinkC_io_req_valid ? _sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_param = _sinkC_io_req_valid ? _sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_size = _sinkC_io_req_valid ? _sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_source = _sinkC_io_req_valid ? _sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_tag = _sinkC_io_req_valid ? _sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_offset = _sinkC_io_req_valid ? _sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_put = _sinkC_io_req_valid ? _sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_set = _sinkC_io_req_valid ? _sinkC_io_req_bits_set : _request_bits_T_set; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_prio_0 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22] assign request_bits_prio_0 = _request_bits_T_1_prio_0; // @[Scheduler.scala:163:21, :165:22] assign request_bits_prio_2 = _request_bits_T_1_prio_2; // @[Scheduler.scala:163:21, :165:22] assign request_bits_control = _request_bits_T_1_control; // @[Scheduler.scala:163:21, :165:22] assign request_bits_opcode = _request_bits_T_1_opcode; // @[Scheduler.scala:163:21, :165:22] assign request_bits_param = _request_bits_T_1_param; // @[Scheduler.scala:163:21, :165:22] assign request_bits_size = _request_bits_T_1_size; // @[Scheduler.scala:163:21, :165:22] assign request_bits_source = _request_bits_T_1_source; // @[Scheduler.scala:163:21, :165:22] assign request_bits_tag = _request_bits_T_1_tag; // @[Scheduler.scala:163:21, :165:22] assign request_bits_offset = _request_bits_T_1_offset; // @[Scheduler.scala:163:21, :165:22] assign request_bits_put = _request_bits_T_1_put; // @[Scheduler.scala:163:21, :165:22] assign request_bits_set = _request_bits_T_1_set; // @[Scheduler.scala:163:21, :165:22] wire _GEN_0 = _directory_io_ready & request_ready; // @[Scheduler.scala:68:25, :163:21, :167:44] wire _sinkC_io_req_ready_T; // @[Scheduler.scala:167:44] assign _sinkC_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44] wire _sinkX_io_req_ready_T; // @[Scheduler.scala:168:44] assign _sinkX_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :168:44] wire _sinkA_io_req_ready_T; // @[Scheduler.scala:169:44] assign _sinkA_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :169:44] wire _sinkX_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :168:64] wire _sinkX_io_req_ready_T_2 = _sinkX_io_req_ready_T & _sinkX_io_req_ready_T_1; // @[Scheduler.scala:168:{44,61,64}] wire _sinkA_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :169:64] wire _sinkA_io_req_ready_T_2 = _sinkA_io_req_ready_T & _sinkA_io_req_ready_T_1; // @[Scheduler.scala:169:{44,61,64}] wire _sinkA_io_req_ready_T_3 = ~_sinkX_io_req_valid; // @[Scheduler.scala:58:21, :169:87] wire _sinkA_io_req_ready_T_4 = _sinkA_io_req_ready_T_2 & _sinkA_io_req_ready_T_3; // @[Scheduler.scala:169:{61,84,87}] wire _setMatches_T = _mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_1 = _mshrs_0_io_status_valid & _setMatches_T; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_2 = _mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_3 = _mshrs_1_io_status_valid & _setMatches_T_2; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_4 = _mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_5 = _mshrs_2_io_status_valid & _setMatches_T_4; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_6 = _mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_7 = _mshrs_3_io_status_valid & _setMatches_T_6; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_8 = _mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_9 = _mshrs_4_io_status_valid & _setMatches_T_8; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_10 = _mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_11 = _mshrs_5_io_status_valid & _setMatches_T_10; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_12 = _mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_13 = _mshrs_6_io_status_valid & _setMatches_T_12; // @[Scheduler.scala:71:46, :172:{59,83}] wire [1:0] setMatches_lo_hi = {_setMatches_T_5, _setMatches_T_3}; // @[Scheduler.scala:172:{23,59}] wire [2:0] setMatches_lo = {setMatches_lo_hi, _setMatches_T_1}; // @[Scheduler.scala:172:{23,59}] wire [1:0] setMatches_hi_lo = {_setMatches_T_9, _setMatches_T_7}; // @[Scheduler.scala:172:{23,59}] wire [1:0] setMatches_hi_hi = {_setMatches_T_13, _setMatches_T_11}; // @[Scheduler.scala:172:{23,59}] wire [3:0] setMatches_hi = {setMatches_hi_hi, setMatches_hi_lo}; // @[Scheduler.scala:172:23] wire [6:0] setMatches = {setMatches_hi, setMatches_lo}; // @[Scheduler.scala:172:23] wire _alloc_T = |setMatches; // @[Scheduler.scala:172:23, :173:27] wire alloc = ~_alloc_T; // @[Scheduler.scala:173:{15,27}] wire _blockB_T = setMatches[0]; // @[Mux.scala:32:36] wire _blockC_T = setMatches[0]; // @[Mux.scala:32:36] wire _nestB_T = setMatches[0]; // @[Mux.scala:32:36] wire _nestC_T = setMatches[0]; // @[Mux.scala:32:36] wire _blockB_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _blockC_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _nestB_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _nestC_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _blockB_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _blockC_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _nestB_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _nestC_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _blockB_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _blockC_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _nestB_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _nestC_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _blockB_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _blockC_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _nestB_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _nestC_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _blockB_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _blockC_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _nestB_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _nestC_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _blockB_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _blockC_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _nestB_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _nestC_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _blockB_T_7 = _blockB_T & _mshrs_0_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_8 = _blockB_T_1 & _mshrs_1_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_9 = _blockB_T_2 & _mshrs_2_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_10 = _blockB_T_3 & _mshrs_3_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_11 = _blockB_T_4 & _mshrs_4_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_12 = _blockB_T_5 & _mshrs_5_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_13 = _blockB_T_6 & _mshrs_6_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_14 = _blockB_T_7 | _blockB_T_8; // @[Mux.scala:30:73] wire _blockB_T_15 = _blockB_T_14 | _blockB_T_9; // @[Mux.scala:30:73] wire _blockB_T_16 = _blockB_T_15 | _blockB_T_10; // @[Mux.scala:30:73] wire _blockB_T_17 = _blockB_T_16 | _blockB_T_11; // @[Mux.scala:30:73] wire _blockB_T_18 = _blockB_T_17 | _blockB_T_12; // @[Mux.scala:30:73] wire _blockB_T_19 = _blockB_T_18 | _blockB_T_13; // @[Mux.scala:30:73] wire _blockB_WIRE = _blockB_T_19; // @[Mux.scala:30:73] wire _blockC_T_7 = _blockC_T & _mshrs_0_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_8 = _blockC_T_1 & _mshrs_1_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_9 = _blockC_T_2 & _mshrs_2_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_10 = _blockC_T_3 & _mshrs_3_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_11 = _blockC_T_4 & _mshrs_4_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_12 = _blockC_T_5 & _mshrs_5_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_13 = _blockC_T_6 & _mshrs_6_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_14 = _blockC_T_7 | _blockC_T_8; // @[Mux.scala:30:73] wire _blockC_T_15 = _blockC_T_14 | _blockC_T_9; // @[Mux.scala:30:73] wire _blockC_T_16 = _blockC_T_15 | _blockC_T_10; // @[Mux.scala:30:73] wire _blockC_T_17 = _blockC_T_16 | _blockC_T_11; // @[Mux.scala:30:73] wire _blockC_T_18 = _blockC_T_17 | _blockC_T_12; // @[Mux.scala:30:73] wire _blockC_T_19 = _blockC_T_18 | _blockC_T_13; // @[Mux.scala:30:73] wire _blockC_WIRE = _blockC_T_19; // @[Mux.scala:30:73] wire blockC = _blockC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73] wire _nestB_T_7 = _nestB_T & _mshrs_0_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_8 = _nestB_T_1 & _mshrs_1_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_9 = _nestB_T_2 & _mshrs_2_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_10 = _nestB_T_3 & _mshrs_3_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_11 = _nestB_T_4 & _mshrs_4_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_12 = _nestB_T_5 & _mshrs_5_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_13 = _nestB_T_6 & _mshrs_6_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_14 = _nestB_T_7 | _nestB_T_8; // @[Mux.scala:30:73] wire _nestB_T_15 = _nestB_T_14 | _nestB_T_9; // @[Mux.scala:30:73] wire _nestB_T_16 = _nestB_T_15 | _nestB_T_10; // @[Mux.scala:30:73] wire _nestB_T_17 = _nestB_T_16 | _nestB_T_11; // @[Mux.scala:30:73] wire _nestB_T_18 = _nestB_T_17 | _nestB_T_12; // @[Mux.scala:30:73] wire _nestB_T_19 = _nestB_T_18 | _nestB_T_13; // @[Mux.scala:30:73] wire _nestB_WIRE = _nestB_T_19; // @[Mux.scala:30:73] wire _nestC_T_7 = _nestC_T & _mshrs_0_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_8 = _nestC_T_1 & _mshrs_1_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_9 = _nestC_T_2 & _mshrs_2_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_10 = _nestC_T_3 & _mshrs_3_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_11 = _nestC_T_4 & _mshrs_4_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_12 = _nestC_T_5 & _mshrs_5_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_13 = _nestC_T_6 & _mshrs_6_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_14 = _nestC_T_7 | _nestC_T_8; // @[Mux.scala:30:73] wire _nestC_T_15 = _nestC_T_14 | _nestC_T_9; // @[Mux.scala:30:73] wire _nestC_T_16 = _nestC_T_15 | _nestC_T_10; // @[Mux.scala:30:73] wire _nestC_T_17 = _nestC_T_16 | _nestC_T_11; // @[Mux.scala:30:73] wire _nestC_T_18 = _nestC_T_17 | _nestC_T_12; // @[Mux.scala:30:73] wire _nestC_T_19 = _nestC_T_18 | _nestC_T_13; // @[Mux.scala:30:73] wire _nestC_WIRE = _nestC_T_19; // @[Mux.scala:30:73] wire nestC = _nestC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73] wire _prioFilter_T = ~request_bits_prio_0; // @[Scheduler.scala:163:21, :182:46] wire [1:0] prioFilter_hi = {request_bits_prio_2, _prioFilter_T}; // @[Scheduler.scala:163:21, :182:{23,46}] wire [6:0] prioFilter = {prioFilter_hi, 5'h1F}; // @[Scheduler.scala:182:23] wire [6:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala:172:23, :182:23, :183:33] wire _queue_T = |lowerMatches; // @[Scheduler.scala:183:33, :185:28] wire _queue_T_2 = _queue_T; // @[Scheduler.scala:185:{28,32}] wire _queue_T_3 = ~nestC; // @[Scheduler.scala:180:70, :185:45] wire _queue_T_4 = _queue_T_2 & _queue_T_3; // @[Scheduler.scala:185:{32,42,45}] wire _queue_T_6 = _queue_T_4; // @[Scheduler.scala:185:{42,52}] wire _queue_T_7 = ~blockC; // @[Scheduler.scala:176:70, :185:66] wire queue = _queue_T_6 & _queue_T_7; // @[Scheduler.scala:185:{52,63,66}] wire _T_7 = request_valid & queue; // @[Scheduler.scala:163:21, :185:63, :195:31] wire _bypass_T; // @[Scheduler.scala:213:30] assign _bypass_T = _T_7; // @[Scheduler.scala:195:31, :213:30] wire _bypass_T_1; // @[Scheduler.scala:231:32] assign _bypass_T_1 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_2; // @[Scheduler.scala:231:32] assign _bypass_T_2 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_3; // @[Scheduler.scala:231:32] assign _bypass_T_3 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_4; // @[Scheduler.scala:231:32] assign _bypass_T_4 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_5; // @[Scheduler.scala:231:32] assign _bypass_T_5 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_6; // @[Scheduler.scala:231:32] assign _bypass_T_6 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_7; // @[Scheduler.scala:231:32] assign _bypass_T_7 = _T_7; // @[Scheduler.scala:195:31, :231:32] wire _requests_io_push_valid_T; // @[Scheduler.scala:270:43] assign _requests_io_push_valid_T = _T_7; // @[Scheduler.scala:195:31, :270:43] wire _lowerMatches1_T = lowerMatches[6]; // @[Scheduler.scala:183:33, :200:21] wire _lowerMatches1_T_2 = lowerMatches[5]; // @[Scheduler.scala:183:33, :201:21] wire [6:0] _lowerMatches1_T_4 = _lowerMatches1_T_2 ? 7'h20 : lowerMatches; // @[Scheduler.scala:183:33, :201:{8,21}] wire [6:0] lowerMatches1 = _lowerMatches1_T ? 7'h40 : _lowerMatches1_T_4; // @[Scheduler.scala:200:{8,21}, :201:8] wire [6:0] _requests_io_push_bits_index_T = lowerMatches1; // @[Scheduler.scala:200:8, :274:30] wire [13:0] _GEN_1 = {2{mshr_selectOH}}; // @[Scheduler.scala:121:70, :206:30] wire [13:0] selected_requests_hi; // @[Scheduler.scala:206:30] assign selected_requests_hi = _GEN_1; // @[Scheduler.scala:206:30] wire [13:0] pop_index_hi; // @[Scheduler.scala:241:31] assign pop_index_hi = _GEN_1; // @[Scheduler.scala:206:30, :241:31] wire [20:0] _selected_requests_T = {selected_requests_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :206:30] wire [20:0] selected_requests = _selected_requests_T & _requests_io_valid; // @[Scheduler.scala:70:24, :206:{30,76}] wire [6:0] _a_pop_T = selected_requests[6:0]; // @[Scheduler.scala:206:76, :207:32] wire a_pop = |_a_pop_T; // @[Scheduler.scala:207:{32,79}] wire [6:0] _b_pop_T = selected_requests[13:7]; // @[Scheduler.scala:206:76, :208:32] wire b_pop = |_b_pop_T; // @[Scheduler.scala:208:{32,79}] wire _bypassMatches_T_4 = b_pop; // @[Scheduler.scala:208:79, :211:76] wire [6:0] _c_pop_T = selected_requests[20:14]; // @[Scheduler.scala:206:76, :209:32] wire c_pop = |_c_pop_T; // @[Scheduler.scala:209:{32,79}] wire [6:0] _bypassMatches_T = mshr_selectOH & lowerMatches1; // @[Scheduler.scala:121:70, :200:8, :210:38] wire _bypassMatches_T_1 = |_bypassMatches_T; // @[Scheduler.scala:210:{38,55}] wire _bypassMatches_T_2 = c_pop | request_bits_prio_2; // @[Scheduler.scala:163:21, :209:79, :211:33] wire _bypassMatches_T_3 = ~c_pop; // @[Scheduler.scala:209:79, :211:58] wire _bypassMatches_T_5 = ~b_pop; // @[Scheduler.scala:208:79, :211:101] wire _bypassMatches_T_6 = ~a_pop; // @[Scheduler.scala:207:79, :211:109] wire _bypassMatches_T_7 = _bypassMatches_T_4 ? _bypassMatches_T_5 : _bypassMatches_T_6; // @[Scheduler.scala:211:{69,76,101,109}] wire _bypassMatches_T_8 = _bypassMatches_T_2 ? _bypassMatches_T_3 : _bypassMatches_T_7; // @[Scheduler.scala:211:{26,33,58,69}] wire bypassMatches = _bypassMatches_T_1 & _bypassMatches_T_8; // @[Scheduler.scala:210:{55,59}, :211:26] wire _may_pop_T = a_pop | b_pop; // @[Scheduler.scala:207:79, :208:79, :212:23] wire may_pop = _may_pop_T | c_pop; // @[Scheduler.scala:209:79, :212:{23,32}] wire bypass = _bypass_T & bypassMatches; // @[Scheduler.scala:210:59, :213:{30,39}] wire _will_reload_T = may_pop | bypass; // @[Scheduler.scala:212:32, :213:39, :214:49] wire will_reload = schedule_reload & _will_reload_T; // @[Mux.scala:30:73] wire _GEN_2 = schedule_reload & may_pop; // @[Mux.scala:30:73] wire _will_pop_T; // @[Scheduler.scala:215:34] assign _will_pop_T = _GEN_2; // @[Scheduler.scala:215:34] wire _mshr_uses_directory_assuming_no_bypass_T; // @[Scheduler.scala:247:64] assign _mshr_uses_directory_assuming_no_bypass_T = _GEN_2; // @[Scheduler.scala:215:34, :247:64] wire _will_pop_T_1 = ~bypass; // @[Scheduler.scala:213:39, :215:48] wire will_pop = _will_pop_T & _will_pop_T_1; // @[Scheduler.scala:215:{34,45,48}] wire a_pop_1 = _requests_io_valid[0]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_1 = _requests_io_valid[7]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_12 = b_pop_1; // @[Scheduler.scala:226:34, :229:78] wire c_pop_1 = _requests_io_valid[14]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_9 = lowerMatches1[0]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_10 = c_pop_1 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_11 = ~c_pop_1; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_13 = ~b_pop_1; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_14 = ~a_pop_1; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_15 = _bypassMatches_T_12 ? _bypassMatches_T_13 : _bypassMatches_T_14; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_16 = _bypassMatches_T_10 ? _bypassMatches_T_11 : _bypassMatches_T_15; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_1 = _bypassMatches_T_9 & _bypassMatches_T_16; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_1 = a_pop_1 | b_pop_1; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_1 = _may_pop_T_1 | c_pop_1; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_1 = _bypass_T_1 & bypassMatches_1; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_1 = may_pop_1 | bypass_1; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_1 = _mshrs_0_io_schedule_bits_reload & _will_reload_T_1; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_prio_0 = bypass_1 ? _view__WIRE_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_prio_1 = ~bypass_1 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_prio_2 = bypass_1 ? _view__WIRE_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_control = bypass_1 ? _view__WIRE_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_opcode = bypass_1 ? _view__WIRE_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_param = bypass_1 ? _view__WIRE_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_size = bypass_1 ? _view__WIRE_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_source = bypass_1 ? _view__WIRE_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_tag = bypass_1 ? _view__WIRE_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_offset = bypass_1 ? _view__WIRE_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_put = bypass_1 ? _view__WIRE_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_0_io_allocate_bits_repeat_T = mshrs_0_io_allocate_bits_tag == _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_0_io_allocate_valid_T = sel & will_reload_1; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_2 = _requests_io_valid[1]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_2 = _requests_io_valid[8]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_20 = b_pop_2; // @[Scheduler.scala:226:34, :229:78] wire c_pop_2 = _requests_io_valid[15]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_17 = lowerMatches1[1]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_18 = c_pop_2 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_19 = ~c_pop_2; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_21 = ~b_pop_2; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_22 = ~a_pop_2; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_23 = _bypassMatches_T_20 ? _bypassMatches_T_21 : _bypassMatches_T_22; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_24 = _bypassMatches_T_18 ? _bypassMatches_T_19 : _bypassMatches_T_23; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_2 = _bypassMatches_T_17 & _bypassMatches_T_24; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_2 = a_pop_2 | b_pop_2; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_2 = _may_pop_T_2 | c_pop_2; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_2 = _bypass_T_2 & bypassMatches_2; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_2 = may_pop_2 | bypass_2; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_2 = _mshrs_1_io_schedule_bits_reload & _will_reload_T_2; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_1_prio_0 = bypass_2 ? _view__WIRE_1_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_1_prio_1 = ~bypass_2 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_1_prio_2 = bypass_2 ? _view__WIRE_1_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_1_control = bypass_2 ? _view__WIRE_1_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_opcode = bypass_2 ? _view__WIRE_1_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_param = bypass_2 ? _view__WIRE_1_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_size = bypass_2 ? _view__WIRE_1_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_source = bypass_2 ? _view__WIRE_1_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_1_tag = bypass_2 ? _view__WIRE_1_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_offset = bypass_2 ? _view__WIRE_1_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_put = bypass_2 ? _view__WIRE_1_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_1_io_allocate_bits_repeat_T = mshrs_1_io_allocate_bits_tag == _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_1_io_allocate_valid_T = sel_1 & will_reload_2; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_3 = _requests_io_valid[2]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_3 = _requests_io_valid[9]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_28 = b_pop_3; // @[Scheduler.scala:226:34, :229:78] wire c_pop_3 = _requests_io_valid[16]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_25 = lowerMatches1[2]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_26 = c_pop_3 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_27 = ~c_pop_3; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_29 = ~b_pop_3; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_30 = ~a_pop_3; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_31 = _bypassMatches_T_28 ? _bypassMatches_T_29 : _bypassMatches_T_30; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_32 = _bypassMatches_T_26 ? _bypassMatches_T_27 : _bypassMatches_T_31; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_3 = _bypassMatches_T_25 & _bypassMatches_T_32; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_3 = a_pop_3 | b_pop_3; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_3 = _may_pop_T_3 | c_pop_3; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_3 = _bypass_T_3 & bypassMatches_3; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_3 = may_pop_3 | bypass_3; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_3 = _mshrs_2_io_schedule_bits_reload & _will_reload_T_3; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_2_prio_0 = bypass_3 ? _view__WIRE_2_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_2_prio_1 = ~bypass_3 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_2_prio_2 = bypass_3 ? _view__WIRE_2_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_2_control = bypass_3 ? _view__WIRE_2_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_opcode = bypass_3 ? _view__WIRE_2_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_param = bypass_3 ? _view__WIRE_2_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_size = bypass_3 ? _view__WIRE_2_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_source = bypass_3 ? _view__WIRE_2_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_2_tag = bypass_3 ? _view__WIRE_2_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_offset = bypass_3 ? _view__WIRE_2_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_put = bypass_3 ? _view__WIRE_2_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_2_io_allocate_bits_repeat_T = mshrs_2_io_allocate_bits_tag == _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_2_io_allocate_valid_T = sel_2 & will_reload_3; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_4 = _requests_io_valid[3]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_4 = _requests_io_valid[10]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_36 = b_pop_4; // @[Scheduler.scala:226:34, :229:78] wire c_pop_4 = _requests_io_valid[17]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_33 = lowerMatches1[3]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_34 = c_pop_4 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_35 = ~c_pop_4; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_37 = ~b_pop_4; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_38 = ~a_pop_4; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_39 = _bypassMatches_T_36 ? _bypassMatches_T_37 : _bypassMatches_T_38; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_40 = _bypassMatches_T_34 ? _bypassMatches_T_35 : _bypassMatches_T_39; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_4 = _bypassMatches_T_33 & _bypassMatches_T_40; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_4 = a_pop_4 | b_pop_4; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_4 = _may_pop_T_4 | c_pop_4; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_4 = _bypass_T_4 & bypassMatches_4; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_4 = may_pop_4 | bypass_4; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_4 = _mshrs_3_io_schedule_bits_reload & _will_reload_T_4; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_3_prio_0 = bypass_4 ? _view__WIRE_3_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_3_prio_1 = ~bypass_4 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_3_prio_2 = bypass_4 ? _view__WIRE_3_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_3_control = bypass_4 ? _view__WIRE_3_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_opcode = bypass_4 ? _view__WIRE_3_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_param = bypass_4 ? _view__WIRE_3_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_size = bypass_4 ? _view__WIRE_3_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_source = bypass_4 ? _view__WIRE_3_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_3_tag = bypass_4 ? _view__WIRE_3_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_offset = bypass_4 ? _view__WIRE_3_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_put = bypass_4 ? _view__WIRE_3_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_3_io_allocate_bits_repeat_T = mshrs_3_io_allocate_bits_tag == _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_3_io_allocate_valid_T = sel_3 & will_reload_4; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_5 = _requests_io_valid[4]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_5 = _requests_io_valid[11]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_44 = b_pop_5; // @[Scheduler.scala:226:34, :229:78] wire c_pop_5 = _requests_io_valid[18]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_41 = lowerMatches1[4]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_42 = c_pop_5 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_43 = ~c_pop_5; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_45 = ~b_pop_5; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_46 = ~a_pop_5; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_47 = _bypassMatches_T_44 ? _bypassMatches_T_45 : _bypassMatches_T_46; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_48 = _bypassMatches_T_42 ? _bypassMatches_T_43 : _bypassMatches_T_47; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_5 = _bypassMatches_T_41 & _bypassMatches_T_48; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_5 = a_pop_5 | b_pop_5; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_5 = _may_pop_T_5 | c_pop_5; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_5 = _bypass_T_5 & bypassMatches_5; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_5 = may_pop_5 | bypass_5; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_5 = _mshrs_4_io_schedule_bits_reload & _will_reload_T_5; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_4_prio_0 = bypass_5 ? _view__WIRE_4_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_4_prio_1 = ~bypass_5 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_4_prio_2 = bypass_5 ? _view__WIRE_4_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_4_control = bypass_5 ? _view__WIRE_4_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_opcode = bypass_5 ? _view__WIRE_4_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_param = bypass_5 ? _view__WIRE_4_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_size = bypass_5 ? _view__WIRE_4_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_source = bypass_5 ? _view__WIRE_4_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_4_tag = bypass_5 ? _view__WIRE_4_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_offset = bypass_5 ? _view__WIRE_4_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_put = bypass_5 ? _view__WIRE_4_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_4_io_allocate_bits_repeat_T = mshrs_4_io_allocate_bits_tag == _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_4_io_allocate_valid_T = sel_4 & will_reload_5; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_6 = _requests_io_valid[5]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_6 = _requests_io_valid[12]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_52 = b_pop_6; // @[Scheduler.scala:226:34, :229:78] wire c_pop_6 = _requests_io_valid[19]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_49 = lowerMatches1[5]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_50 = c_pop_6 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_51 = ~c_pop_6; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_53 = ~b_pop_6; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_54 = ~a_pop_6; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_55 = _bypassMatches_T_52 ? _bypassMatches_T_53 : _bypassMatches_T_54; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_56 = _bypassMatches_T_50 ? _bypassMatches_T_51 : _bypassMatches_T_55; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_6 = _bypassMatches_T_49 & _bypassMatches_T_56; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_6 = a_pop_6 | b_pop_6; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_6 = _may_pop_T_6 | c_pop_6; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_6 = _bypass_T_6 & bypassMatches_6; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_6 = may_pop_6 | bypass_6; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_6 = _mshrs_5_io_schedule_bits_reload & _will_reload_T_6; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_5_prio_0 = bypass_6 ? _view__WIRE_5_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_5_prio_1 = ~bypass_6 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_5_prio_2 = bypass_6 ? _view__WIRE_5_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_5_control = bypass_6 ? _view__WIRE_5_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_opcode = bypass_6 ? _view__WIRE_5_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_param = bypass_6 ? _view__WIRE_5_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_size = bypass_6 ? _view__WIRE_5_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_source = bypass_6 ? _view__WIRE_5_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_5_tag = bypass_6 ? _view__WIRE_5_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_offset = bypass_6 ? _view__WIRE_5_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_put = bypass_6 ? _view__WIRE_5_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_5_io_allocate_bits_repeat_T = mshrs_5_io_allocate_bits_tag == _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :287:131, :289:74] wire _mshrs_5_io_allocate_valid_T = sel_5 & will_reload_6; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_7 = _requests_io_valid[6]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_7 = _requests_io_valid[13]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_60 = b_pop_7; // @[Scheduler.scala:226:34, :229:78] wire c_pop_7 = _requests_io_valid[20]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_57 = lowerMatches1[6]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_58 = c_pop_7 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_59 = ~c_pop_7; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_61 = ~b_pop_7; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_62 = ~a_pop_7; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_63 = _bypassMatches_T_60 ? _bypassMatches_T_61 : _bypassMatches_T_62; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_64 = _bypassMatches_T_58 ? _bypassMatches_T_59 : _bypassMatches_T_63; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_7 = _bypassMatches_T_57 & _bypassMatches_T_64; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_7 = a_pop_7 | b_pop_7; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_7 = _may_pop_T_7 | c_pop_7; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_7 = _bypass_T_7 & bypassMatches_7; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_7 = may_pop_7 | bypass_7; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_7 = _mshrs_6_io_schedule_bits_reload & _will_reload_T_7; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_6_prio_0 = bypass_7 ? _view__WIRE_6_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_6_prio_1 = ~bypass_7 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_6_prio_2 = bypass_7 ? _view__WIRE_6_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_6_control = bypass_7 ? _view__WIRE_6_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_opcode = bypass_7 ? _view__WIRE_6_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_param = bypass_7 ? _view__WIRE_6_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_size = bypass_7 ? _view__WIRE_6_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_source = bypass_7 ? _view__WIRE_6_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [12:0] _view__T_6_tag = bypass_7 ? _view__WIRE_6_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_offset = bypass_7 ? _view__WIRE_6_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_put = bypass_7 ? _view__WIRE_6_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_6_io_allocate_bits_repeat_T = mshrs_6_io_allocate_bits_tag == _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :295:103, :297:73] wire _mshrs_6_io_allocate_valid_T = sel_6 & will_reload_7; // @[Scheduler.scala:223:28, :232:49, :236:32] wire [20:0] _prio_requests_T = ~_requests_io_valid; // @[Scheduler.scala:70:24, :240:25] wire [13:0] _prio_requests_T_1 = _requests_io_valid[20:7]; // @[Scheduler.scala:70:24, :240:65] wire [20:0] _prio_requests_T_2 = {_prio_requests_T[20:14], _prio_requests_T[13:0] | _prio_requests_T_1}; // @[Scheduler.scala:240:{25,44,65}] wire [6:0] _prio_requests_T_3 = _requests_io_valid[20:14]; // @[Scheduler.scala:70:24, :240:103] wire [20:0] _prio_requests_T_4 = {_prio_requests_T_2[20:7], _prio_requests_T_2[6:0] | _prio_requests_T_3}; // @[Scheduler.scala:240:{44,82,103}] wire [20:0] prio_requests = ~_prio_requests_T_4; // @[Scheduler.scala:240:{23,82}] wire [20:0] _pop_index_T = {pop_index_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :241:31] wire [20:0] _pop_index_T_1 = _pop_index_T & prio_requests; // @[Scheduler.scala:240:23, :241:{31,77}] wire [4:0] pop_index_hi_1 = _pop_index_T_1[20:16]; // @[OneHot.scala:30:18] wire [15:0] pop_index_lo = _pop_index_T_1[15:0]; // @[OneHot.scala:31:18] wire _pop_index_T_2 = |pop_index_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _pop_index_T_3 = {11'h0, pop_index_hi_1} | pop_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] pop_index_hi_2 = _pop_index_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] pop_index_lo_1 = _pop_index_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_4 = |pop_index_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _pop_index_T_5 = pop_index_hi_2 | pop_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] pop_index_hi_3 = _pop_index_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] pop_index_lo_2 = _pop_index_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_6 = |pop_index_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _pop_index_T_7 = pop_index_hi_3 | pop_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] pop_index_hi_4 = _pop_index_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] pop_index_lo_3 = _pop_index_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_8 = |pop_index_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _pop_index_T_9 = pop_index_hi_4 | pop_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire _pop_index_T_10 = _pop_index_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _pop_index_T_11 = {_pop_index_T_8, _pop_index_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _pop_index_T_12 = {_pop_index_T_6, _pop_index_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _pop_index_T_13 = {_pop_index_T_4, _pop_index_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] pop_index = {_pop_index_T_2, _pop_index_T_13}; // @[OneHot.scala:32:{10,14}] wire lb_tag_mismatch = scheduleTag != _requests_io_data_tag; // @[Mux.scala:30:73] wire mshr_uses_directory_assuming_no_bypass = _mshr_uses_directory_assuming_no_bypass_T & lb_tag_mismatch; // @[Scheduler.scala:246:37, :247:{64,75}] wire mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala:215:45, :246:37, :248:45] wire [12:0] _mshr_uses_directory_T = bypass ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :163:21, :213:39, :249:63] wire _mshr_uses_directory_T_1 = scheduleTag != _mshr_uses_directory_T; // @[Mux.scala:30:73] wire mshr_uses_directory = will_reload & _mshr_uses_directory_T_1; // @[Scheduler.scala:214:37, :249:{41,56}] wire [1:0] mshr_validOH_lo_hi = {_mshrs_2_io_status_valid, _mshrs_1_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [2:0] mshr_validOH_lo = {mshr_validOH_lo_hi, _mshrs_0_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [1:0] mshr_validOH_hi_lo = {_mshrs_4_io_status_valid, _mshrs_3_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [1:0] mshr_validOH_hi_hi = {_mshrs_6_io_status_valid, _mshrs_5_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [3:0] mshr_validOH_hi = {mshr_validOH_hi_hi, mshr_validOH_hi_lo}; // @[Scheduler.scala:252:25] wire [6:0] mshr_validOH = {mshr_validOH_hi, mshr_validOH_lo}; // @[Scheduler.scala:252:25] wire [6:0] _mshr_free_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20] wire [6:0] _mshr_free_T_1 = _mshr_free_T & prioFilter; // @[Scheduler.scala:182:23, :253:{20,34}] wire mshr_free = |_mshr_free_T_1; // @[Scheduler.scala:253:{34,48}] wire bypassQueue = schedule_reload & bypassMatches; // @[Mux.scala:30:73] wire _request_alloc_cases_T = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16] wire _request_alloc_cases_T_1 = alloc & _request_alloc_cases_T; // @[Scheduler.scala:173:15, :258:{13,16}] wire _request_alloc_cases_T_2 = _request_alloc_cases_T_1 & mshr_free; // @[Scheduler.scala:253:48, :258:{13,56}] wire _request_alloc_cases_T_9 = _request_alloc_cases_T_2; // @[Scheduler.scala:258:{56,70}] wire _request_alloc_cases_T_3 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :259:16] wire _request_alloc_cases_T_5 = ~_mshrs_5_io_status_valid; // @[Scheduler.scala:71:46, :259:59] wire _request_alloc_cases_T_7 = ~_mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :259:87] wire _request_alloc_cases_T_10 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :260:16] wire _request_alloc_cases_T_11 = nestC & _request_alloc_cases_T_10; // @[Scheduler.scala:180:70, :260:{13,16}] wire _request_alloc_cases_T_12 = ~_mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :259:87, :260:59] wire _request_alloc_cases_T_13 = _request_alloc_cases_T_11 & _request_alloc_cases_T_12; // @[Scheduler.scala:260:{13,56,59}] wire request_alloc_cases = _request_alloc_cases_T_9 | _request_alloc_cases_T_13; // @[Scheduler.scala:258:70, :259:112, :260:56] wire _request_ready_T = bypassQueue | _requests_io_push_ready; // @[Scheduler.scala:70:24, :256:37, :261:66] wire _request_ready_T_1 = queue & _request_ready_T; // @[Scheduler.scala:185:63, :261:{50,66}] assign _request_ready_T_2 = request_alloc_cases | _request_ready_T_1; // @[Scheduler.scala:259:112, :261:{40,50}] assign request_ready = _request_ready_T_2; // @[Scheduler.scala:163:21, :261:40] wire alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala:163:21, :259:112, :262:44] wire _directory_io_read_valid_T = mshr_uses_directory | alloc_uses_directory; // @[Scheduler.scala:249:41, :262:44, :265:50] wire [9:0] _directory_io_read_bits_set_T = mshr_uses_directory_for_lb ? scheduleSet : request_bits_set; // @[Mux.scala:30:73] wire [12:0] _directory_io_read_bits_tag_T = mshr_uses_directory_for_lb ? _requests_io_data_tag : request_bits_tag; // @[Scheduler.scala:70:24, :163:21, :248:45, :267:36] wire _requests_io_push_valid_T_1 = ~bypassQueue; // @[Scheduler.scala:256:37, :270:55] wire _requests_io_push_valid_T_2 = _requests_io_push_valid_T & _requests_io_push_valid_T_1; // @[Scheduler.scala:270:{43,52,55}] wire [2:0] requests_io_push_bits_index_hi = _requests_io_push_bits_index_T[6:4]; // @[OneHot.scala:30:18] wire [3:0] requests_io_push_bits_index_lo = _requests_io_push_bits_index_T[3:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_1 = |requests_io_push_bits_index_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_2 = {1'h0, requests_io_push_bits_index_hi} | requests_io_push_bits_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_1 = _requests_io_push_bits_index_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_1 = _requests_io_push_bits_index_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_3 = |requests_io_push_bits_index_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_4 = requests_io_push_bits_index_hi_1 | requests_io_push_bits_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_5 = _requests_io_push_bits_index_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_6 = {_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_7 = {_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_6}; // @[OneHot.scala:32:{10,14}] wire [13:0] _requests_io_push_bits_index_T_8 = {lowerMatches1, 7'h0}; // @[Scheduler.scala:200:8, :275:30] wire [5:0] requests_io_push_bits_index_hi_2 = _requests_io_push_bits_index_T_8[13:8]; // @[OneHot.scala:30:18] wire [7:0] requests_io_push_bits_index_lo_2 = _requests_io_push_bits_index_T_8[7:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_9 = |requests_io_push_bits_index_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_10 = {2'h0, requests_io_push_bits_index_hi_2} | requests_io_push_bits_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_3 = _requests_io_push_bits_index_T_10[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_3 = _requests_io_push_bits_index_T_10[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_11 = |requests_io_push_bits_index_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_12 = requests_io_push_bits_index_hi_3 | requests_io_push_bits_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_4 = _requests_io_push_bits_index_T_12[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_4 = _requests_io_push_bits_index_T_12[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_13 = |requests_io_push_bits_index_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_14 = requests_io_push_bits_index_hi_4 | requests_io_push_bits_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_15 = _requests_io_push_bits_index_T_14[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_16 = {_requests_io_push_bits_index_T_13, _requests_io_push_bits_index_T_15}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_17 = {_requests_io_push_bits_index_T_11, _requests_io_push_bits_index_T_16}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_18 = {_requests_io_push_bits_index_T_9, _requests_io_push_bits_index_T_17}; // @[OneHot.scala:32:{10,14}] wire [20:0] _requests_io_push_bits_index_T_19 = {lowerMatches1, 14'h0}; // @[Scheduler.scala:200:8, :276:30] wire [4:0] requests_io_push_bits_index_hi_5 = _requests_io_push_bits_index_T_19[20:16]; // @[OneHot.scala:30:18] wire [15:0] requests_io_push_bits_index_lo_5 = _requests_io_push_bits_index_T_19[15:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_20 = |requests_io_push_bits_index_hi_5; // @[OneHot.scala:30:18, :32:14] wire [15:0] _requests_io_push_bits_index_T_21 = {11'h0, requests_io_push_bits_index_hi_5} | requests_io_push_bits_index_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] requests_io_push_bits_index_hi_6 = _requests_io_push_bits_index_T_21[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] requests_io_push_bits_index_lo_6 = _requests_io_push_bits_index_T_21[7:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_22 = |requests_io_push_bits_index_hi_6; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_23 = requests_io_push_bits_index_hi_6 | requests_io_push_bits_index_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_7 = _requests_io_push_bits_index_T_23[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_7 = _requests_io_push_bits_index_T_23[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_24 = |requests_io_push_bits_index_hi_7; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_25 = requests_io_push_bits_index_hi_7 | requests_io_push_bits_index_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_8 = _requests_io_push_bits_index_T_25[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_8 = _requests_io_push_bits_index_T_25[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_26 = |requests_io_push_bits_index_hi_8; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_27 = requests_io_push_bits_index_hi_8 | requests_io_push_bits_index_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_28 = _requests_io_push_bits_index_T_27[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_29 = {_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_28}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_30 = {_requests_io_push_bits_index_T_24, _requests_io_push_bits_index_T_29}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_31 = {_requests_io_push_bits_index_T_22, _requests_io_push_bits_index_T_30}; // @[OneHot.scala:32:{10,14}] wire [4:0] _requests_io_push_bits_index_T_32 = {_requests_io_push_bits_index_T_20, _requests_io_push_bits_index_T_31}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_33 = request_bits_prio_0 ? _requests_io_push_bits_index_T_7 : 3'h0; // @[OneHot.scala:32:10] wire [4:0] _requests_io_push_bits_index_T_35 = request_bits_prio_2 ? _requests_io_push_bits_index_T_32 : 5'h0; // @[OneHot.scala:32:10] wire [3:0] _requests_io_push_bits_index_T_36 = {1'h0, _requests_io_push_bits_index_T_33}; // @[Mux.scala:30:73] wire [4:0] _requests_io_push_bits_index_T_37 = {1'h0, _requests_io_push_bits_index_T_36} | _requests_io_push_bits_index_T_35; // @[Mux.scala:30:73] wire [4:0] _requests_io_push_bits_index_WIRE = _requests_io_push_bits_index_T_37; // @[Mux.scala:30:73] wire [6:0] _mshr_insertOH_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:32] wire [7:0] _mshr_insertOH_T_1 = {_mshr_insertOH_T, 1'h0}; // @[package.scala:253:48] wire [6:0] _mshr_insertOH_T_2 = _mshr_insertOH_T_1[6:0]; // @[package.scala:253:{48,53}] wire [6:0] _mshr_insertOH_T_3 = _mshr_insertOH_T | _mshr_insertOH_T_2; // @[package.scala:253:{43,53}] wire [8:0] _mshr_insertOH_T_4 = {_mshr_insertOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [6:0] _mshr_insertOH_T_5 = _mshr_insertOH_T_4[6:0]; // @[package.scala:253:{48,53}] wire [6:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 | _mshr_insertOH_T_5; // @[package.scala:253:{43,53}] wire [10:0] _mshr_insertOH_T_7 = {_mshr_insertOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [6:0] _mshr_insertOH_T_8 = _mshr_insertOH_T_7[6:0]; // @[package.scala:253:{48,53}] wire [6:0] _mshr_insertOH_T_9 = _mshr_insertOH_T_6 | _mshr_insertOH_T_8; // @[package.scala:253:{43,53}] wire [6:0] _mshr_insertOH_T_10 = _mshr_insertOH_T_9; // @[package.scala:253:43, :254:17] wire [7:0] _mshr_insertOH_T_11 = {_mshr_insertOH_T_10, 1'h0}; // @[package.scala:254:17] wire [7:0] _mshr_insertOH_T_12 = ~_mshr_insertOH_T_11; // @[Scheduler.scala:278:{23,47}] wire [6:0] _mshr_insertOH_T_13 = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:55] wire [7:0] _mshr_insertOH_T_14 = {1'h0, _mshr_insertOH_T_12[6:0] & _mshr_insertOH_T_13}; // @[Scheduler.scala:278:{23,53,55}] wire [7:0] mshr_insertOH = {1'h0, _mshr_insertOH_T_14[6:0] & prioFilter}; // @[Scheduler.scala:182:23, :278:{53,69}] wire _T_46 = request_valid & alloc; // @[Scheduler.scala:163:21, :173:15, :280:25] wire _T_25 = _T_46 & mshr_insertOH[0] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_0_io_allocate_bits_tag = _T_25 ? request_bits_tag : _view__T_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_29 = _T_46 & mshr_insertOH[1] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_1_io_allocate_bits_tag = _T_29 ? request_bits_tag : _view__T_1_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_33 = _T_46 & mshr_insertOH[2] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_2_io_allocate_bits_tag = _T_33 ? request_bits_tag : _view__T_2_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_37 = _T_46 & mshr_insertOH[3] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_3_io_allocate_bits_tag = _T_37 ? request_bits_tag : _view__T_3_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_41 = _T_46 & mshr_insertOH[4] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_4_io_allocate_bits_tag = _T_41 ? request_bits_tag : _view__T_4_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_45 = _T_46 & mshr_insertOH[5] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_5_io_allocate_bits_tag = _T_45 ? request_bits_tag : _view__T_5_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70, :287:131, :289:74] wire _T_65 = request_valid & nestC & ~_mshrs_6_io_status_valid & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:71:46, :163:21, :180:70, :193:33, :247:75, :258:16, :259:87, :295:{32,59}] wire _GEN_3 = _T_65 | _T_46 & mshr_insertOH[6] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:193:33, :236:25, :247:75, :258:16, :278:69, :279:18, :280:{25,34,39,83}, :281:27, :295:{32,59,103}, :296:30] assign mshrs_6_io_allocate_bits_tag = _GEN_3 ? request_bits_tag : _view__T_6_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :236:25, :280:83, :281:27, :282:70, :295:103, :296:30, :297:73]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_57 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE : UInt<1>[29] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 node _source_ok_T_49 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[2]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[3]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[4]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[5]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[6]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[7]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[8]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[9]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[10]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[11]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[12]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[13]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[14]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[15]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[16]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[17]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[18]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[19]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[20]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[21]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[22]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[23]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[24]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[25]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[26]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[27]) node source_ok = or(_source_ok_T_75, _source_ok_WIRE[28]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = and(_T_11, _T_24) node _T_257 = and(_T_256, _T_37) node _T_258 = and(_T_257, _T_50) node _T_259 = and(_T_258, _T_63) node _T_260 = and(_T_259, _T_71) node _T_261 = and(_T_260, _T_79) node _T_262 = and(_T_261, _T_87) node _T_263 = and(_T_262, _T_95) node _T_264 = and(_T_263, _T_103) node _T_265 = and(_T_264, _T_111) node _T_266 = and(_T_265, _T_119) node _T_267 = and(_T_266, _T_127) node _T_268 = and(_T_267, _T_135) node _T_269 = and(_T_268, _T_143) node _T_270 = and(_T_269, _T_151) node _T_271 = and(_T_270, _T_159) node _T_272 = and(_T_271, _T_167) node _T_273 = and(_T_272, _T_175) node _T_274 = and(_T_273, _T_183) node _T_275 = and(_T_274, _T_191) node _T_276 = and(_T_275, _T_199) node _T_277 = and(_T_276, _T_207) node _T_278 = and(_T_277, _T_215) node _T_279 = and(_T_278, _T_223) node _T_280 = and(_T_279, _T_231) node _T_281 = and(_T_280, _T_239) node _T_282 = and(_T_281, _T_247) node _T_283 = and(_T_282, _T_255) node _T_284 = asUInt(reset) node _T_285 = eq(_T_284, UInt<1>(0h0)) when _T_285 : node _T_286 = eq(_T_283, UInt<1>(0h0)) when _T_286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_283, UInt<1>(0h1), "") : assert_1 node _T_287 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_287 : node _T_288 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_289 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_292 = shr(io.in.a.bits.source, 2) node _T_293 = eq(_T_292, UInt<1>(0h0)) node _T_294 = leq(UInt<1>(0h0), uncommonBits_4) node _T_295 = and(_T_293, _T_294) node _T_296 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_297 = and(_T_295, _T_296) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_298 = shr(io.in.a.bits.source, 2) node _T_299 = eq(_T_298, UInt<1>(0h1)) node _T_300 = leq(UInt<1>(0h0), uncommonBits_5) node _T_301 = and(_T_299, _T_300) node _T_302 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_303 = and(_T_301, _T_302) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_304 = shr(io.in.a.bits.source, 2) node _T_305 = eq(_T_304, UInt<2>(0h2)) node _T_306 = leq(UInt<1>(0h0), uncommonBits_6) node _T_307 = and(_T_305, _T_306) node _T_308 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_309 = and(_T_307, _T_308) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_310 = shr(io.in.a.bits.source, 2) node _T_311 = eq(_T_310, UInt<2>(0h3)) node _T_312 = leq(UInt<1>(0h0), uncommonBits_7) node _T_313 = and(_T_311, _T_312) node _T_314 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_315 = and(_T_313, _T_314) node _T_316 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_317 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_318 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_319 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_320 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_321 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_322 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_323 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_324 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_340 = or(_T_291, _T_297) node _T_341 = or(_T_340, _T_303) node _T_342 = or(_T_341, _T_309) node _T_343 = or(_T_342, _T_315) node _T_344 = or(_T_343, _T_316) node _T_345 = or(_T_344, _T_317) node _T_346 = or(_T_345, _T_318) node _T_347 = or(_T_346, _T_319) node _T_348 = or(_T_347, _T_320) node _T_349 = or(_T_348, _T_321) node _T_350 = or(_T_349, _T_322) node _T_351 = or(_T_350, _T_323) node _T_352 = or(_T_351, _T_324) node _T_353 = or(_T_352, _T_325) node _T_354 = or(_T_353, _T_326) node _T_355 = or(_T_354, _T_327) node _T_356 = or(_T_355, _T_328) node _T_357 = or(_T_356, _T_329) node _T_358 = or(_T_357, _T_330) node _T_359 = or(_T_358, _T_331) node _T_360 = or(_T_359, _T_332) node _T_361 = or(_T_360, _T_333) node _T_362 = or(_T_361, _T_334) node _T_363 = or(_T_362, _T_335) node _T_364 = or(_T_363, _T_336) node _T_365 = or(_T_364, _T_337) node _T_366 = or(_T_365, _T_338) node _T_367 = or(_T_366, _T_339) node _T_368 = and(_T_290, _T_367) node _T_369 = or(UInt<1>(0h0), _T_368) node _T_370 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<17>(0h100c0))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<29>(0h100000c0))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = or(_T_376, _T_381) node _T_383 = and(_T_371, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = and(_T_369, _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_385, UInt<1>(0h1), "") : assert_2 node _T_389 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_390 = shr(io.in.a.bits.source, 2) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = leq(UInt<1>(0h0), uncommonBits_8) node _T_393 = and(_T_391, _T_392) node _T_394 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_395 = and(_T_393, _T_394) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h1)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_9) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<2>(0h2)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_10) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h3)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_11) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _T_414 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_415 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_416 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_417 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_418 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_419 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_420 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_421 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_424 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_425 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_426 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_427 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_428 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_429 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_431 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_432 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_433 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE : UInt<1>[29] connect _WIRE[0], _T_389 connect _WIRE[1], _T_395 connect _WIRE[2], _T_401 connect _WIRE[3], _T_407 connect _WIRE[4], _T_413 connect _WIRE[5], _T_414 connect _WIRE[6], _T_415 connect _WIRE[7], _T_416 connect _WIRE[8], _T_417 connect _WIRE[9], _T_418 connect _WIRE[10], _T_419 connect _WIRE[11], _T_420 connect _WIRE[12], _T_421 connect _WIRE[13], _T_422 connect _WIRE[14], _T_423 connect _WIRE[15], _T_424 connect _WIRE[16], _T_425 connect _WIRE[17], _T_426 connect _WIRE[18], _T_427 connect _WIRE[19], _T_428 connect _WIRE[20], _T_429 connect _WIRE[21], _T_430 connect _WIRE[22], _T_431 connect _WIRE[23], _T_432 connect _WIRE[24], _T_433 connect _WIRE[25], _T_434 connect _WIRE[26], _T_435 connect _WIRE[27], _T_436 connect _WIRE[28], _T_437 node _T_438 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_439 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_440 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_441 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_442 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_443 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_444 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_445 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_446 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_447 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_448 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_449 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_450 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_452 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_453 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_454 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_455 = mux(_WIRE[5], _T_438, UInt<1>(0h0)) node _T_456 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_457 = mux(_WIRE[7], _T_439, UInt<1>(0h0)) node _T_458 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_459 = mux(_WIRE[9], _T_440, UInt<1>(0h0)) node _T_460 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE[11], _T_441, UInt<1>(0h0)) node _T_462 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_463 = mux(_WIRE[13], _T_442, UInt<1>(0h0)) node _T_464 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = mux(_WIRE[15], _T_443, UInt<1>(0h0)) node _T_466 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = mux(_WIRE[17], _T_444, UInt<1>(0h0)) node _T_468 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_469 = mux(_WIRE[19], _T_445, UInt<1>(0h0)) node _T_470 = mux(_WIRE[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_471 = mux(_WIRE[21], _T_446, UInt<1>(0h0)) node _T_472 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_473 = mux(_WIRE[23], _T_447, UInt<1>(0h0)) node _T_474 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_475 = mux(_WIRE[25], _T_448, UInt<1>(0h0)) node _T_476 = mux(_WIRE[26], UInt<1>(0h0), UInt<1>(0h0)) node _T_477 = mux(_WIRE[27], _T_449, UInt<1>(0h0)) node _T_478 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_479 = or(_T_450, _T_451) node _T_480 = or(_T_479, _T_452) node _T_481 = or(_T_480, _T_453) node _T_482 = or(_T_481, _T_454) node _T_483 = or(_T_482, _T_455) node _T_484 = or(_T_483, _T_456) node _T_485 = or(_T_484, _T_457) node _T_486 = or(_T_485, _T_458) node _T_487 = or(_T_486, _T_459) node _T_488 = or(_T_487, _T_460) node _T_489 = or(_T_488, _T_461) node _T_490 = or(_T_489, _T_462) node _T_491 = or(_T_490, _T_463) node _T_492 = or(_T_491, _T_464) node _T_493 = or(_T_492, _T_465) node _T_494 = or(_T_493, _T_466) node _T_495 = or(_T_494, _T_467) node _T_496 = or(_T_495, _T_468) node _T_497 = or(_T_496, _T_469) node _T_498 = or(_T_497, _T_470) node _T_499 = or(_T_498, _T_471) node _T_500 = or(_T_499, _T_472) node _T_501 = or(_T_500, _T_473) node _T_502 = or(_T_501, _T_474) node _T_503 = or(_T_502, _T_475) node _T_504 = or(_T_503, _T_476) node _T_505 = or(_T_504, _T_477) node _T_506 = or(_T_505, _T_478) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_506 node _T_507 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_508 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_509 = and(_T_507, _T_508) node _T_510 = or(UInt<1>(0h0), _T_509) node _T_511 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<17>(0h100c0))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<29>(0h100000c0))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = or(_T_515, _T_520) node _T_522 = and(_T_510, _T_521) node _T_523 = or(UInt<1>(0h0), _T_522) node _T_524 = and(_WIRE_1, _T_523) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_524, UInt<1>(0h1), "") : assert_3 node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(source_ok, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_531 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(_T_531, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_531, UInt<1>(0h1), "") : assert_5 node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(is_aligned, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_538 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_538, UInt<1>(0h1), "") : assert_7 node _T_542 = not(io.in.a.bits.mask) node _T_543 = eq(_T_542, UInt<1>(0h0)) node _T_544 = asUInt(reset) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(_T_543, UInt<1>(0h0)) when _T_546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_543, UInt<1>(0h1), "") : assert_8 node _T_547 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_548 = asUInt(reset) node _T_549 = eq(_T_548, UInt<1>(0h0)) when _T_549 : node _T_550 = eq(_T_547, UInt<1>(0h0)) when _T_550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_547, UInt<1>(0h1), "") : assert_9 node _T_551 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_551 : node _T_552 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_553 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_554 = and(_T_552, _T_553) node _T_555 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_556 = shr(io.in.a.bits.source, 2) node _T_557 = eq(_T_556, UInt<1>(0h0)) node _T_558 = leq(UInt<1>(0h0), uncommonBits_12) node _T_559 = and(_T_557, _T_558) node _T_560 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_561 = and(_T_559, _T_560) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_562 = shr(io.in.a.bits.source, 2) node _T_563 = eq(_T_562, UInt<1>(0h1)) node _T_564 = leq(UInt<1>(0h0), uncommonBits_13) node _T_565 = and(_T_563, _T_564) node _T_566 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_567 = and(_T_565, _T_566) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_568 = shr(io.in.a.bits.source, 2) node _T_569 = eq(_T_568, UInt<2>(0h2)) node _T_570 = leq(UInt<1>(0h0), uncommonBits_14) node _T_571 = and(_T_569, _T_570) node _T_572 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_573 = and(_T_571, _T_572) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_574 = shr(io.in.a.bits.source, 2) node _T_575 = eq(_T_574, UInt<2>(0h3)) node _T_576 = leq(UInt<1>(0h0), uncommonBits_15) node _T_577 = and(_T_575, _T_576) node _T_578 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_579 = and(_T_577, _T_578) node _T_580 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_581 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_582 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_583 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_584 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_585 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_586 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_587 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_591 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_592 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_602 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_603 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_604 = or(_T_555, _T_561) node _T_605 = or(_T_604, _T_567) node _T_606 = or(_T_605, _T_573) node _T_607 = or(_T_606, _T_579) node _T_608 = or(_T_607, _T_580) node _T_609 = or(_T_608, _T_581) node _T_610 = or(_T_609, _T_582) node _T_611 = or(_T_610, _T_583) node _T_612 = or(_T_611, _T_584) node _T_613 = or(_T_612, _T_585) node _T_614 = or(_T_613, _T_586) node _T_615 = or(_T_614, _T_587) node _T_616 = or(_T_615, _T_588) node _T_617 = or(_T_616, _T_589) node _T_618 = or(_T_617, _T_590) node _T_619 = or(_T_618, _T_591) node _T_620 = or(_T_619, _T_592) node _T_621 = or(_T_620, _T_593) node _T_622 = or(_T_621, _T_594) node _T_623 = or(_T_622, _T_595) node _T_624 = or(_T_623, _T_596) node _T_625 = or(_T_624, _T_597) node _T_626 = or(_T_625, _T_598) node _T_627 = or(_T_626, _T_599) node _T_628 = or(_T_627, _T_600) node _T_629 = or(_T_628, _T_601) node _T_630 = or(_T_629, _T_602) node _T_631 = or(_T_630, _T_603) node _T_632 = and(_T_554, _T_631) node _T_633 = or(UInt<1>(0h0), _T_632) node _T_634 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_635 = or(UInt<1>(0h0), _T_634) node _T_636 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_637 = cvt(_T_636) node _T_638 = and(_T_637, asSInt(UInt<17>(0h100c0))) node _T_639 = asSInt(_T_638) node _T_640 = eq(_T_639, asSInt(UInt<1>(0h0))) node _T_641 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_642 = cvt(_T_641) node _T_643 = and(_T_642, asSInt(UInt<29>(0h100000c0))) node _T_644 = asSInt(_T_643) node _T_645 = eq(_T_644, asSInt(UInt<1>(0h0))) node _T_646 = or(_T_640, _T_645) node _T_647 = and(_T_635, _T_646) node _T_648 = or(UInt<1>(0h0), _T_647) node _T_649 = and(_T_633, _T_648) node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(_T_649, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_649, UInt<1>(0h1), "") : assert_10 node _T_653 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_654 = shr(io.in.a.bits.source, 2) node _T_655 = eq(_T_654, UInt<1>(0h0)) node _T_656 = leq(UInt<1>(0h0), uncommonBits_16) node _T_657 = and(_T_655, _T_656) node _T_658 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_659 = and(_T_657, _T_658) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_660 = shr(io.in.a.bits.source, 2) node _T_661 = eq(_T_660, UInt<1>(0h1)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_17) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_665 = and(_T_663, _T_664) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<2>(0h2)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_18) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<2>(0h3)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_19) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _T_678 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_679 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_680 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_681 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_682 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_683 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_684 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_685 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_694 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_695 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_696 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_697 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_698 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_699 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_700 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_701 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE_2 : UInt<1>[29] connect _WIRE_2[0], _T_653 connect _WIRE_2[1], _T_659 connect _WIRE_2[2], _T_665 connect _WIRE_2[3], _T_671 connect _WIRE_2[4], _T_677 connect _WIRE_2[5], _T_678 connect _WIRE_2[6], _T_679 connect _WIRE_2[7], _T_680 connect _WIRE_2[8], _T_681 connect _WIRE_2[9], _T_682 connect _WIRE_2[10], _T_683 connect _WIRE_2[11], _T_684 connect _WIRE_2[12], _T_685 connect _WIRE_2[13], _T_686 connect _WIRE_2[14], _T_687 connect _WIRE_2[15], _T_688 connect _WIRE_2[16], _T_689 connect _WIRE_2[17], _T_690 connect _WIRE_2[18], _T_691 connect _WIRE_2[19], _T_692 connect _WIRE_2[20], _T_693 connect _WIRE_2[21], _T_694 connect _WIRE_2[22], _T_695 connect _WIRE_2[23], _T_696 connect _WIRE_2[24], _T_697 connect _WIRE_2[25], _T_698 connect _WIRE_2[26], _T_699 connect _WIRE_2[27], _T_700 connect _WIRE_2[28], _T_701 node _T_702 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_703 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_704 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_705 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_706 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_707 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_708 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_709 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_710 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_711 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_712 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_713 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_714 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_715 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_716 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_717 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = mux(_WIRE_2[5], _T_702, UInt<1>(0h0)) node _T_720 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_721 = mux(_WIRE_2[7], _T_703, UInt<1>(0h0)) node _T_722 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_723 = mux(_WIRE_2[9], _T_704, UInt<1>(0h0)) node _T_724 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_725 = mux(_WIRE_2[11], _T_705, UInt<1>(0h0)) node _T_726 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_727 = mux(_WIRE_2[13], _T_706, UInt<1>(0h0)) node _T_728 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_729 = mux(_WIRE_2[15], _T_707, UInt<1>(0h0)) node _T_730 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_731 = mux(_WIRE_2[17], _T_708, UInt<1>(0h0)) node _T_732 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_733 = mux(_WIRE_2[19], _T_709, UInt<1>(0h0)) node _T_734 = mux(_WIRE_2[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_735 = mux(_WIRE_2[21], _T_710, UInt<1>(0h0)) node _T_736 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_737 = mux(_WIRE_2[23], _T_711, UInt<1>(0h0)) node _T_738 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_739 = mux(_WIRE_2[25], _T_712, UInt<1>(0h0)) node _T_740 = mux(_WIRE_2[26], UInt<1>(0h0), UInt<1>(0h0)) node _T_741 = mux(_WIRE_2[27], _T_713, UInt<1>(0h0)) node _T_742 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_743 = or(_T_714, _T_715) node _T_744 = or(_T_743, _T_716) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_718) node _T_747 = or(_T_746, _T_719) node _T_748 = or(_T_747, _T_720) node _T_749 = or(_T_748, _T_721) node _T_750 = or(_T_749, _T_722) node _T_751 = or(_T_750, _T_723) node _T_752 = or(_T_751, _T_724) node _T_753 = or(_T_752, _T_725) node _T_754 = or(_T_753, _T_726) node _T_755 = or(_T_754, _T_727) node _T_756 = or(_T_755, _T_728) node _T_757 = or(_T_756, _T_729) node _T_758 = or(_T_757, _T_730) node _T_759 = or(_T_758, _T_731) node _T_760 = or(_T_759, _T_732) node _T_761 = or(_T_760, _T_733) node _T_762 = or(_T_761, _T_734) node _T_763 = or(_T_762, _T_735) node _T_764 = or(_T_763, _T_736) node _T_765 = or(_T_764, _T_737) node _T_766 = or(_T_765, _T_738) node _T_767 = or(_T_766, _T_739) node _T_768 = or(_T_767, _T_740) node _T_769 = or(_T_768, _T_741) node _T_770 = or(_T_769, _T_742) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_770 node _T_771 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_772 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_773 = and(_T_771, _T_772) node _T_774 = or(UInt<1>(0h0), _T_773) node _T_775 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h100c0))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<29>(0h100000c0))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = or(_T_779, _T_784) node _T_786 = and(_T_774, _T_785) node _T_787 = or(UInt<1>(0h0), _T_786) node _T_788 = and(_WIRE_3, _T_787) node _T_789 = asUInt(reset) node _T_790 = eq(_T_789, UInt<1>(0h0)) when _T_790 : node _T_791 = eq(_T_788, UInt<1>(0h0)) when _T_791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_788, UInt<1>(0h1), "") : assert_11 node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(source_ok, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_795 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(_T_795, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_795, UInt<1>(0h1), "") : assert_13 node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(is_aligned, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_802 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(_T_802, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_802, UInt<1>(0h1), "") : assert_15 node _T_806 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(_T_806, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_806, UInt<1>(0h1), "") : assert_16 node _T_810 = not(io.in.a.bits.mask) node _T_811 = eq(_T_810, UInt<1>(0h0)) node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(_T_811, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_811, UInt<1>(0h1), "") : assert_17 node _T_815 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_816 = asUInt(reset) node _T_817 = eq(_T_816, UInt<1>(0h0)) when _T_817 : node _T_818 = eq(_T_815, UInt<1>(0h0)) when _T_818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_815, UInt<1>(0h1), "") : assert_18 node _T_819 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_819 : node _T_820 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_821 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_822 = and(_T_820, _T_821) node _T_823 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_824 = shr(io.in.a.bits.source, 2) node _T_825 = eq(_T_824, UInt<1>(0h0)) node _T_826 = leq(UInt<1>(0h0), uncommonBits_20) node _T_827 = and(_T_825, _T_826) node _T_828 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_829 = and(_T_827, _T_828) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_830 = shr(io.in.a.bits.source, 2) node _T_831 = eq(_T_830, UInt<1>(0h1)) node _T_832 = leq(UInt<1>(0h0), uncommonBits_21) node _T_833 = and(_T_831, _T_832) node _T_834 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_835 = and(_T_833, _T_834) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_836 = shr(io.in.a.bits.source, 2) node _T_837 = eq(_T_836, UInt<2>(0h2)) node _T_838 = leq(UInt<1>(0h0), uncommonBits_22) node _T_839 = and(_T_837, _T_838) node _T_840 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_841 = and(_T_839, _T_840) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_842 = shr(io.in.a.bits.source, 2) node _T_843 = eq(_T_842, UInt<2>(0h3)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_23) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_847 = and(_T_845, _T_846) node _T_848 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_849 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_850 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_851 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_852 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_853 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_854 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_855 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_857 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_858 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_859 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_860 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_861 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_862 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_863 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_864 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_865 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_866 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_867 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_868 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_869 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_870 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_872 = or(_T_823, _T_829) node _T_873 = or(_T_872, _T_835) node _T_874 = or(_T_873, _T_841) node _T_875 = or(_T_874, _T_847) node _T_876 = or(_T_875, _T_848) node _T_877 = or(_T_876, _T_849) node _T_878 = or(_T_877, _T_850) node _T_879 = or(_T_878, _T_851) node _T_880 = or(_T_879, _T_852) node _T_881 = or(_T_880, _T_853) node _T_882 = or(_T_881, _T_854) node _T_883 = or(_T_882, _T_855) node _T_884 = or(_T_883, _T_856) node _T_885 = or(_T_884, _T_857) node _T_886 = or(_T_885, _T_858) node _T_887 = or(_T_886, _T_859) node _T_888 = or(_T_887, _T_860) node _T_889 = or(_T_888, _T_861) node _T_890 = or(_T_889, _T_862) node _T_891 = or(_T_890, _T_863) node _T_892 = or(_T_891, _T_864) node _T_893 = or(_T_892, _T_865) node _T_894 = or(_T_893, _T_866) node _T_895 = or(_T_894, _T_867) node _T_896 = or(_T_895, _T_868) node _T_897 = or(_T_896, _T_869) node _T_898 = or(_T_897, _T_870) node _T_899 = or(_T_898, _T_871) node _T_900 = and(_T_822, _T_899) node _T_901 = or(UInt<1>(0h0), _T_900) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_901, UInt<1>(0h1), "") : assert_19 node _T_905 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_906 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_907 = and(_T_905, _T_906) node _T_908 = or(UInt<1>(0h0), _T_907) node _T_909 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<17>(0h100c0))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<29>(0h100000c0))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = or(_T_913, _T_918) node _T_920 = and(_T_908, _T_919) node _T_921 = or(UInt<1>(0h0), _T_920) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_921, UInt<1>(0h1), "") : assert_20 node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_928 = asUInt(reset) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(is_aligned, UInt<1>(0h0)) when _T_930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_931 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(_T_931, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_931, UInt<1>(0h1), "") : assert_23 node _T_935 = eq(io.in.a.bits.mask, mask) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_935, UInt<1>(0h1), "") : assert_24 node _T_939 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_939, UInt<1>(0h1), "") : assert_25 node _T_943 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_943 : node _T_944 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_945 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_946 = and(_T_944, _T_945) node _T_947 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_948 = shr(io.in.a.bits.source, 2) node _T_949 = eq(_T_948, UInt<1>(0h0)) node _T_950 = leq(UInt<1>(0h0), uncommonBits_24) node _T_951 = and(_T_949, _T_950) node _T_952 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_954 = shr(io.in.a.bits.source, 2) node _T_955 = eq(_T_954, UInt<1>(0h1)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_25) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_959 = and(_T_957, _T_958) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_960 = shr(io.in.a.bits.source, 2) node _T_961 = eq(_T_960, UInt<2>(0h2)) node _T_962 = leq(UInt<1>(0h0), uncommonBits_26) node _T_963 = and(_T_961, _T_962) node _T_964 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_965 = and(_T_963, _T_964) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_966 = shr(io.in.a.bits.source, 2) node _T_967 = eq(_T_966, UInt<2>(0h3)) node _T_968 = leq(UInt<1>(0h0), uncommonBits_27) node _T_969 = and(_T_967, _T_968) node _T_970 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_971 = and(_T_969, _T_970) node _T_972 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_973 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_974 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_975 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_976 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_977 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_978 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_979 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_980 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_981 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_982 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_983 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_984 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_985 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_986 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_987 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_988 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_989 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_990 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_991 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_992 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_993 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_994 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_995 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_996 = or(_T_947, _T_953) node _T_997 = or(_T_996, _T_959) node _T_998 = or(_T_997, _T_965) node _T_999 = or(_T_998, _T_971) node _T_1000 = or(_T_999, _T_972) node _T_1001 = or(_T_1000, _T_973) node _T_1002 = or(_T_1001, _T_974) node _T_1003 = or(_T_1002, _T_975) node _T_1004 = or(_T_1003, _T_976) node _T_1005 = or(_T_1004, _T_977) node _T_1006 = or(_T_1005, _T_978) node _T_1007 = or(_T_1006, _T_979) node _T_1008 = or(_T_1007, _T_980) node _T_1009 = or(_T_1008, _T_981) node _T_1010 = or(_T_1009, _T_982) node _T_1011 = or(_T_1010, _T_983) node _T_1012 = or(_T_1011, _T_984) node _T_1013 = or(_T_1012, _T_985) node _T_1014 = or(_T_1013, _T_986) node _T_1015 = or(_T_1014, _T_987) node _T_1016 = or(_T_1015, _T_988) node _T_1017 = or(_T_1016, _T_989) node _T_1018 = or(_T_1017, _T_990) node _T_1019 = or(_T_1018, _T_991) node _T_1020 = or(_T_1019, _T_992) node _T_1021 = or(_T_1020, _T_993) node _T_1022 = or(_T_1021, _T_994) node _T_1023 = or(_T_1022, _T_995) node _T_1024 = and(_T_946, _T_1023) node _T_1025 = or(UInt<1>(0h0), _T_1024) node _T_1026 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1027 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1028 = and(_T_1026, _T_1027) node _T_1029 = or(UInt<1>(0h0), _T_1028) node _T_1030 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_1031 = cvt(_T_1030) node _T_1032 = and(_T_1031, asSInt(UInt<17>(0h100c0))) node _T_1033 = asSInt(_T_1032) node _T_1034 = eq(_T_1033, asSInt(UInt<1>(0h0))) node _T_1035 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_1036 = cvt(_T_1035) node _T_1037 = and(_T_1036, asSInt(UInt<29>(0h100000c0))) node _T_1038 = asSInt(_T_1037) node _T_1039 = eq(_T_1038, asSInt(UInt<1>(0h0))) node _T_1040 = or(_T_1034, _T_1039) node _T_1041 = and(_T_1029, _T_1040) node _T_1042 = or(UInt<1>(0h0), _T_1041) node _T_1043 = and(_T_1025, _T_1042) node _T_1044 = asUInt(reset) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) when _T_1045 : node _T_1046 = eq(_T_1043, UInt<1>(0h0)) when _T_1046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1043, UInt<1>(0h1), "") : assert_26 node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(source_ok, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(is_aligned, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1053 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_29 node _T_1057 = eq(io.in.a.bits.mask, mask) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_30 node _T_1061 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1061 : node _T_1062 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1063 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1064 = and(_T_1062, _T_1063) node _T_1065 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1066 = shr(io.in.a.bits.source, 2) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1071 = and(_T_1069, _T_1070) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1072 = shr(io.in.a.bits.source, 2) node _T_1073 = eq(_T_1072, UInt<1>(0h1)) node _T_1074 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1075 = and(_T_1073, _T_1074) node _T_1076 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1077 = and(_T_1075, _T_1076) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1078 = shr(io.in.a.bits.source, 2) node _T_1079 = eq(_T_1078, UInt<2>(0h2)) node _T_1080 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1081 = and(_T_1079, _T_1080) node _T_1082 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1083 = and(_T_1081, _T_1082) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1084 = shr(io.in.a.bits.source, 2) node _T_1085 = eq(_T_1084, UInt<2>(0h3)) node _T_1086 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1087 = and(_T_1085, _T_1086) node _T_1088 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1089 = and(_T_1087, _T_1088) node _T_1090 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1091 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1092 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1093 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1094 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1095 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1096 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1097 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1098 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1099 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1100 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1101 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1102 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1103 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1105 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1106 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1107 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1108 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1109 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1110 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1114 = or(_T_1065, _T_1071) node _T_1115 = or(_T_1114, _T_1077) node _T_1116 = or(_T_1115, _T_1083) node _T_1117 = or(_T_1116, _T_1089) node _T_1118 = or(_T_1117, _T_1090) node _T_1119 = or(_T_1118, _T_1091) node _T_1120 = or(_T_1119, _T_1092) node _T_1121 = or(_T_1120, _T_1093) node _T_1122 = or(_T_1121, _T_1094) node _T_1123 = or(_T_1122, _T_1095) node _T_1124 = or(_T_1123, _T_1096) node _T_1125 = or(_T_1124, _T_1097) node _T_1126 = or(_T_1125, _T_1098) node _T_1127 = or(_T_1126, _T_1099) node _T_1128 = or(_T_1127, _T_1100) node _T_1129 = or(_T_1128, _T_1101) node _T_1130 = or(_T_1129, _T_1102) node _T_1131 = or(_T_1130, _T_1103) node _T_1132 = or(_T_1131, _T_1104) node _T_1133 = or(_T_1132, _T_1105) node _T_1134 = or(_T_1133, _T_1106) node _T_1135 = or(_T_1134, _T_1107) node _T_1136 = or(_T_1135, _T_1108) node _T_1137 = or(_T_1136, _T_1109) node _T_1138 = or(_T_1137, _T_1110) node _T_1139 = or(_T_1138, _T_1111) node _T_1140 = or(_T_1139, _T_1112) node _T_1141 = or(_T_1140, _T_1113) node _T_1142 = and(_T_1064, _T_1141) node _T_1143 = or(UInt<1>(0h0), _T_1142) node _T_1144 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1145 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1146 = and(_T_1144, _T_1145) node _T_1147 = or(UInt<1>(0h0), _T_1146) node _T_1148 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_1149 = cvt(_T_1148) node _T_1150 = and(_T_1149, asSInt(UInt<17>(0h100c0))) node _T_1151 = asSInt(_T_1150) node _T_1152 = eq(_T_1151, asSInt(UInt<1>(0h0))) node _T_1153 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_1154 = cvt(_T_1153) node _T_1155 = and(_T_1154, asSInt(UInt<29>(0h100000c0))) node _T_1156 = asSInt(_T_1155) node _T_1157 = eq(_T_1156, asSInt(UInt<1>(0h0))) node _T_1158 = or(_T_1152, _T_1157) node _T_1159 = and(_T_1147, _T_1158) node _T_1160 = or(UInt<1>(0h0), _T_1159) node _T_1161 = and(_T_1143, _T_1160) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_31 node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(source_ok, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(is_aligned, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1171 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_34 node _T_1175 = not(mask) node _T_1176 = and(io.in.a.bits.mask, _T_1175) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_35 node _T_1181 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1181 : node _T_1182 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1183 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1184 = and(_T_1182, _T_1183) node _T_1185 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1186 = shr(io.in.a.bits.source, 2) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) node _T_1188 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1189 = and(_T_1187, _T_1188) node _T_1190 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1191 = and(_T_1189, _T_1190) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1192 = shr(io.in.a.bits.source, 2) node _T_1193 = eq(_T_1192, UInt<1>(0h1)) node _T_1194 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1195 = and(_T_1193, _T_1194) node _T_1196 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1197 = and(_T_1195, _T_1196) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1198 = shr(io.in.a.bits.source, 2) node _T_1199 = eq(_T_1198, UInt<2>(0h2)) node _T_1200 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1203 = and(_T_1201, _T_1202) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1204 = shr(io.in.a.bits.source, 2) node _T_1205 = eq(_T_1204, UInt<2>(0h3)) node _T_1206 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1207 = and(_T_1205, _T_1206) node _T_1208 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1211 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1212 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1213 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1214 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1215 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1216 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1217 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1218 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1219 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1220 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1221 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1222 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1223 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1224 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1225 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1226 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1227 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1228 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1229 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1234 = or(_T_1185, _T_1191) node _T_1235 = or(_T_1234, _T_1197) node _T_1236 = or(_T_1235, _T_1203) node _T_1237 = or(_T_1236, _T_1209) node _T_1238 = or(_T_1237, _T_1210) node _T_1239 = or(_T_1238, _T_1211) node _T_1240 = or(_T_1239, _T_1212) node _T_1241 = or(_T_1240, _T_1213) node _T_1242 = or(_T_1241, _T_1214) node _T_1243 = or(_T_1242, _T_1215) node _T_1244 = or(_T_1243, _T_1216) node _T_1245 = or(_T_1244, _T_1217) node _T_1246 = or(_T_1245, _T_1218) node _T_1247 = or(_T_1246, _T_1219) node _T_1248 = or(_T_1247, _T_1220) node _T_1249 = or(_T_1248, _T_1221) node _T_1250 = or(_T_1249, _T_1222) node _T_1251 = or(_T_1250, _T_1223) node _T_1252 = or(_T_1251, _T_1224) node _T_1253 = or(_T_1252, _T_1225) node _T_1254 = or(_T_1253, _T_1226) node _T_1255 = or(_T_1254, _T_1227) node _T_1256 = or(_T_1255, _T_1228) node _T_1257 = or(_T_1256, _T_1229) node _T_1258 = or(_T_1257, _T_1230) node _T_1259 = or(_T_1258, _T_1231) node _T_1260 = or(_T_1259, _T_1232) node _T_1261 = or(_T_1260, _T_1233) node _T_1262 = and(_T_1184, _T_1261) node _T_1263 = or(UInt<1>(0h0), _T_1262) node _T_1264 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1265 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_1266 = and(_T_1264, _T_1265) node _T_1267 = or(UInt<1>(0h0), _T_1266) node _T_1268 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_1269 = cvt(_T_1268) node _T_1270 = and(_T_1269, asSInt(UInt<17>(0h100c0))) node _T_1271 = asSInt(_T_1270) node _T_1272 = eq(_T_1271, asSInt(UInt<1>(0h0))) node _T_1273 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_1274 = cvt(_T_1273) node _T_1275 = and(_T_1274, asSInt(UInt<29>(0h100000c0))) node _T_1276 = asSInt(_T_1275) node _T_1277 = eq(_T_1276, asSInt(UInt<1>(0h0))) node _T_1278 = or(_T_1272, _T_1277) node _T_1279 = and(_T_1267, _T_1278) node _T_1280 = or(UInt<1>(0h0), _T_1279) node _T_1281 = and(_T_1263, _T_1280) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_36 node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(source_ok, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(is_aligned, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1291 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_39 node _T_1295 = eq(io.in.a.bits.mask, mask) node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(_T_1295, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1295, UInt<1>(0h1), "") : assert_40 node _T_1299 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1299 : node _T_1300 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1301 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1302 = and(_T_1300, _T_1301) node _T_1303 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1304 = shr(io.in.a.bits.source, 2) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) node _T_1306 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1307 = and(_T_1305, _T_1306) node _T_1308 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1309 = and(_T_1307, _T_1308) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1310 = shr(io.in.a.bits.source, 2) node _T_1311 = eq(_T_1310, UInt<1>(0h1)) node _T_1312 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1313 = and(_T_1311, _T_1312) node _T_1314 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1315 = and(_T_1313, _T_1314) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1316 = shr(io.in.a.bits.source, 2) node _T_1317 = eq(_T_1316, UInt<2>(0h2)) node _T_1318 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1319 = and(_T_1317, _T_1318) node _T_1320 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1321 = and(_T_1319, _T_1320) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1322 = shr(io.in.a.bits.source, 2) node _T_1323 = eq(_T_1322, UInt<2>(0h3)) node _T_1324 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1327 = and(_T_1325, _T_1326) node _T_1328 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1329 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1330 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1331 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1332 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1333 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1334 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1335 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1336 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1337 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1338 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1339 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1340 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1341 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1342 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1343 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1344 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1345 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1346 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1347 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1348 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1349 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1350 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1351 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1352 = or(_T_1303, _T_1309) node _T_1353 = or(_T_1352, _T_1315) node _T_1354 = or(_T_1353, _T_1321) node _T_1355 = or(_T_1354, _T_1327) node _T_1356 = or(_T_1355, _T_1328) node _T_1357 = or(_T_1356, _T_1329) node _T_1358 = or(_T_1357, _T_1330) node _T_1359 = or(_T_1358, _T_1331) node _T_1360 = or(_T_1359, _T_1332) node _T_1361 = or(_T_1360, _T_1333) node _T_1362 = or(_T_1361, _T_1334) node _T_1363 = or(_T_1362, _T_1335) node _T_1364 = or(_T_1363, _T_1336) node _T_1365 = or(_T_1364, _T_1337) node _T_1366 = or(_T_1365, _T_1338) node _T_1367 = or(_T_1366, _T_1339) node _T_1368 = or(_T_1367, _T_1340) node _T_1369 = or(_T_1368, _T_1341) node _T_1370 = or(_T_1369, _T_1342) node _T_1371 = or(_T_1370, _T_1343) node _T_1372 = or(_T_1371, _T_1344) node _T_1373 = or(_T_1372, _T_1345) node _T_1374 = or(_T_1373, _T_1346) node _T_1375 = or(_T_1374, _T_1347) node _T_1376 = or(_T_1375, _T_1348) node _T_1377 = or(_T_1376, _T_1349) node _T_1378 = or(_T_1377, _T_1350) node _T_1379 = or(_T_1378, _T_1351) node _T_1380 = and(_T_1302, _T_1379) node _T_1381 = or(UInt<1>(0h0), _T_1380) node _T_1382 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1383 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = or(UInt<1>(0h0), _T_1384) node _T_1386 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_1387 = cvt(_T_1386) node _T_1388 = and(_T_1387, asSInt(UInt<17>(0h100c0))) node _T_1389 = asSInt(_T_1388) node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0))) node _T_1391 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_1392 = cvt(_T_1391) node _T_1393 = and(_T_1392, asSInt(UInt<29>(0h100000c0))) node _T_1394 = asSInt(_T_1393) node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0))) node _T_1396 = or(_T_1390, _T_1395) node _T_1397 = and(_T_1385, _T_1396) node _T_1398 = or(UInt<1>(0h0), _T_1397) node _T_1399 = and(_T_1381, _T_1398) node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(_T_1399, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1399, UInt<1>(0h1), "") : assert_41 node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(source_ok, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1406 = asUInt(reset) node _T_1407 = eq(_T_1406, UInt<1>(0h0)) when _T_1407 : node _T_1408 = eq(is_aligned, UInt<1>(0h0)) when _T_1408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1409 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1410 = asUInt(reset) node _T_1411 = eq(_T_1410, UInt<1>(0h0)) when _T_1411 : node _T_1412 = eq(_T_1409, UInt<1>(0h0)) when _T_1412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1409, UInt<1>(0h1), "") : assert_44 node _T_1413 = eq(io.in.a.bits.mask, mask) node _T_1414 = asUInt(reset) node _T_1415 = eq(_T_1414, UInt<1>(0h0)) when _T_1415 : node _T_1416 = eq(_T_1413, UInt<1>(0h0)) when _T_1416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1413, UInt<1>(0h1), "") : assert_45 node _T_1417 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1417 : node _T_1418 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1419 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1420 = and(_T_1418, _T_1419) node _T_1421 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1422 = shr(io.in.a.bits.source, 2) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) node _T_1424 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1425 = and(_T_1423, _T_1424) node _T_1426 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1427 = and(_T_1425, _T_1426) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1428 = shr(io.in.a.bits.source, 2) node _T_1429 = eq(_T_1428, UInt<1>(0h1)) node _T_1430 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1433 = and(_T_1431, _T_1432) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1434 = shr(io.in.a.bits.source, 2) node _T_1435 = eq(_T_1434, UInt<2>(0h2)) node _T_1436 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1437 = and(_T_1435, _T_1436) node _T_1438 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1439 = and(_T_1437, _T_1438) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1440 = shr(io.in.a.bits.source, 2) node _T_1441 = eq(_T_1440, UInt<2>(0h3)) node _T_1442 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1443 = and(_T_1441, _T_1442) node _T_1444 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1445 = and(_T_1443, _T_1444) node _T_1446 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1447 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1448 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1449 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1450 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1451 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1452 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1453 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1454 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1455 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1456 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1457 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1458 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1459 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1460 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1461 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1462 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1463 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1464 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1465 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1466 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1467 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1468 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1469 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1470 = or(_T_1421, _T_1427) node _T_1471 = or(_T_1470, _T_1433) node _T_1472 = or(_T_1471, _T_1439) node _T_1473 = or(_T_1472, _T_1445) node _T_1474 = or(_T_1473, _T_1446) node _T_1475 = or(_T_1474, _T_1447) node _T_1476 = or(_T_1475, _T_1448) node _T_1477 = or(_T_1476, _T_1449) node _T_1478 = or(_T_1477, _T_1450) node _T_1479 = or(_T_1478, _T_1451) node _T_1480 = or(_T_1479, _T_1452) node _T_1481 = or(_T_1480, _T_1453) node _T_1482 = or(_T_1481, _T_1454) node _T_1483 = or(_T_1482, _T_1455) node _T_1484 = or(_T_1483, _T_1456) node _T_1485 = or(_T_1484, _T_1457) node _T_1486 = or(_T_1485, _T_1458) node _T_1487 = or(_T_1486, _T_1459) node _T_1488 = or(_T_1487, _T_1460) node _T_1489 = or(_T_1488, _T_1461) node _T_1490 = or(_T_1489, _T_1462) node _T_1491 = or(_T_1490, _T_1463) node _T_1492 = or(_T_1491, _T_1464) node _T_1493 = or(_T_1492, _T_1465) node _T_1494 = or(_T_1493, _T_1466) node _T_1495 = or(_T_1494, _T_1467) node _T_1496 = or(_T_1495, _T_1468) node _T_1497 = or(_T_1496, _T_1469) node _T_1498 = and(_T_1420, _T_1497) node _T_1499 = or(UInt<1>(0h0), _T_1498) node _T_1500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1501 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1502 = and(_T_1500, _T_1501) node _T_1503 = or(UInt<1>(0h0), _T_1502) node _T_1504 = xor(io.in.a.bits.address, UInt<28>(0h80000c0)) node _T_1505 = cvt(_T_1504) node _T_1506 = and(_T_1505, asSInt(UInt<17>(0h100c0))) node _T_1507 = asSInt(_T_1506) node _T_1508 = eq(_T_1507, asSInt(UInt<1>(0h0))) node _T_1509 = xor(io.in.a.bits.address, UInt<32>(0h800000c0)) node _T_1510 = cvt(_T_1509) node _T_1511 = and(_T_1510, asSInt(UInt<29>(0h100000c0))) node _T_1512 = asSInt(_T_1511) node _T_1513 = eq(_T_1512, asSInt(UInt<1>(0h0))) node _T_1514 = or(_T_1508, _T_1513) node _T_1515 = and(_T_1503, _T_1514) node _T_1516 = or(UInt<1>(0h0), _T_1515) node _T_1517 = and(_T_1499, _T_1516) node _T_1518 = asUInt(reset) node _T_1519 = eq(_T_1518, UInt<1>(0h0)) when _T_1519 : node _T_1520 = eq(_T_1517, UInt<1>(0h0)) when _T_1520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1517, UInt<1>(0h1), "") : assert_46 node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(source_ok, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1524 = asUInt(reset) node _T_1525 = eq(_T_1524, UInt<1>(0h0)) when _T_1525 : node _T_1526 = eq(is_aligned, UInt<1>(0h0)) when _T_1526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1527 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(_T_1527, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1527, UInt<1>(0h1), "") : assert_49 node _T_1531 = eq(io.in.a.bits.mask, mask) node _T_1532 = asUInt(reset) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) when _T_1533 : node _T_1534 = eq(_T_1531, UInt<1>(0h0)) when _T_1534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1531, UInt<1>(0h1), "") : assert_50 node _T_1535 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1536 = asUInt(reset) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) when _T_1537 : node _T_1538 = eq(_T_1535, UInt<1>(0h0)) when _T_1538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1535, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1539 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1540 = asUInt(reset) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(_T_1539, UInt<1>(0h0)) when _T_1542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1539, UInt<1>(0h1), "") : assert_52 node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 2) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<1>(0h0)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_83 = shr(io.in.d.bits.source, 2) node _source_ok_T_84 = eq(_source_ok_T_83, UInt<1>(0h1)) node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85) node _source_ok_T_87 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_89 = shr(io.in.d.bits.source, 2) node _source_ok_T_90 = eq(_source_ok_T_89, UInt<2>(0h2)) node _source_ok_T_91 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_92 = and(_source_ok_T_90, _source_ok_T_91) node _source_ok_T_93 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_95 = shr(io.in.d.bits.source, 2) node _source_ok_T_96 = eq(_source_ok_T_95, UInt<2>(0h3)) node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_T_99 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_1 : UInt<1>[29] connect _source_ok_WIRE_1[0], _source_ok_T_76 connect _source_ok_WIRE_1[1], _source_ok_T_82 connect _source_ok_WIRE_1[2], _source_ok_T_88 connect _source_ok_WIRE_1[3], _source_ok_T_94 connect _source_ok_WIRE_1[4], _source_ok_T_100 connect _source_ok_WIRE_1[5], _source_ok_T_101 connect _source_ok_WIRE_1[6], _source_ok_T_102 connect _source_ok_WIRE_1[7], _source_ok_T_103 connect _source_ok_WIRE_1[8], _source_ok_T_104 connect _source_ok_WIRE_1[9], _source_ok_T_105 connect _source_ok_WIRE_1[10], _source_ok_T_106 connect _source_ok_WIRE_1[11], _source_ok_T_107 connect _source_ok_WIRE_1[12], _source_ok_T_108 connect _source_ok_WIRE_1[13], _source_ok_T_109 connect _source_ok_WIRE_1[14], _source_ok_T_110 connect _source_ok_WIRE_1[15], _source_ok_T_111 connect _source_ok_WIRE_1[16], _source_ok_T_112 connect _source_ok_WIRE_1[17], _source_ok_T_113 connect _source_ok_WIRE_1[18], _source_ok_T_114 connect _source_ok_WIRE_1[19], _source_ok_T_115 connect _source_ok_WIRE_1[20], _source_ok_T_116 connect _source_ok_WIRE_1[21], _source_ok_T_117 connect _source_ok_WIRE_1[22], _source_ok_T_118 connect _source_ok_WIRE_1[23], _source_ok_T_119 connect _source_ok_WIRE_1[24], _source_ok_T_120 connect _source_ok_WIRE_1[25], _source_ok_T_121 connect _source_ok_WIRE_1[26], _source_ok_T_122 connect _source_ok_WIRE_1[27], _source_ok_T_123 connect _source_ok_WIRE_1[28], _source_ok_T_124 node _source_ok_T_125 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_1[2]) node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_1[3]) node _source_ok_T_128 = or(_source_ok_T_127, _source_ok_WIRE_1[4]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[5]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[6]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[7]) node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[8]) node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[9]) node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[10]) node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[11]) node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[12]) node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[13]) node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[14]) node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[15]) node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[16]) node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[17]) node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[18]) node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[19]) node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[20]) node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[21]) node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[22]) node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[23]) node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[24]) node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[25]) node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[26]) node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[27]) node source_ok_1 = or(_source_ok_T_151, _source_ok_WIRE_1[28]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0hc)) node _T_1543 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1543 : node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(source_ok_1, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1547 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1548 = asUInt(reset) node _T_1549 = eq(_T_1548, UInt<1>(0h0)) when _T_1549 : node _T_1550 = eq(_T_1547, UInt<1>(0h0)) when _T_1550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1547, UInt<1>(0h1), "") : assert_54 node _T_1551 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1552 = asUInt(reset) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(_T_1551, UInt<1>(0h0)) when _T_1554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1551, UInt<1>(0h1), "") : assert_55 node _T_1555 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_56 node _T_1559 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_57 node _T_1563 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1563 : node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(source_ok_1, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1567 = asUInt(reset) node _T_1568 = eq(_T_1567, UInt<1>(0h0)) when _T_1568 : node _T_1569 = eq(sink_ok, UInt<1>(0h0)) when _T_1569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1570 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1571 = asUInt(reset) node _T_1572 = eq(_T_1571, UInt<1>(0h0)) when _T_1572 : node _T_1573 = eq(_T_1570, UInt<1>(0h0)) when _T_1573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1570, UInt<1>(0h1), "") : assert_60 node _T_1574 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1575 = asUInt(reset) node _T_1576 = eq(_T_1575, UInt<1>(0h0)) when _T_1576 : node _T_1577 = eq(_T_1574, UInt<1>(0h0)) when _T_1577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1574, UInt<1>(0h1), "") : assert_61 node _T_1578 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1579 = asUInt(reset) node _T_1580 = eq(_T_1579, UInt<1>(0h0)) when _T_1580 : node _T_1581 = eq(_T_1578, UInt<1>(0h0)) when _T_1581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1578, UInt<1>(0h1), "") : assert_62 node _T_1582 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1583 = asUInt(reset) node _T_1584 = eq(_T_1583, UInt<1>(0h0)) when _T_1584 : node _T_1585 = eq(_T_1582, UInt<1>(0h0)) when _T_1585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1582, UInt<1>(0h1), "") : assert_63 node _T_1586 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1587 = or(UInt<1>(0h1), _T_1586) node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(_T_1587, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1587, UInt<1>(0h1), "") : assert_64 node _T_1591 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1591 : node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(source_ok_1, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(sink_ok, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1598 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1599 = asUInt(reset) node _T_1600 = eq(_T_1599, UInt<1>(0h0)) when _T_1600 : node _T_1601 = eq(_T_1598, UInt<1>(0h0)) when _T_1601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1598, UInt<1>(0h1), "") : assert_67 node _T_1602 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(_T_1602, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1602, UInt<1>(0h1), "") : assert_68 node _T_1606 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1607 = asUInt(reset) node _T_1608 = eq(_T_1607, UInt<1>(0h0)) when _T_1608 : node _T_1609 = eq(_T_1606, UInt<1>(0h0)) when _T_1609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1606, UInt<1>(0h1), "") : assert_69 node _T_1610 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1611 = or(_T_1610, io.in.d.bits.corrupt) node _T_1612 = asUInt(reset) node _T_1613 = eq(_T_1612, UInt<1>(0h0)) when _T_1613 : node _T_1614 = eq(_T_1611, UInt<1>(0h0)) when _T_1614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1611, UInt<1>(0h1), "") : assert_70 node _T_1615 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1616 = or(UInt<1>(0h1), _T_1615) node _T_1617 = asUInt(reset) node _T_1618 = eq(_T_1617, UInt<1>(0h0)) when _T_1618 : node _T_1619 = eq(_T_1616, UInt<1>(0h0)) when _T_1619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1616, UInt<1>(0h1), "") : assert_71 node _T_1620 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1620 : node _T_1621 = asUInt(reset) node _T_1622 = eq(_T_1621, UInt<1>(0h0)) when _T_1622 : node _T_1623 = eq(source_ok_1, UInt<1>(0h0)) when _T_1623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1624 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1625 = asUInt(reset) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) when _T_1626 : node _T_1627 = eq(_T_1624, UInt<1>(0h0)) when _T_1627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1624, UInt<1>(0h1), "") : assert_73 node _T_1628 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1629 = asUInt(reset) node _T_1630 = eq(_T_1629, UInt<1>(0h0)) when _T_1630 : node _T_1631 = eq(_T_1628, UInt<1>(0h0)) when _T_1631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1628, UInt<1>(0h1), "") : assert_74 node _T_1632 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1633 = or(UInt<1>(0h1), _T_1632) node _T_1634 = asUInt(reset) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) when _T_1635 : node _T_1636 = eq(_T_1633, UInt<1>(0h0)) when _T_1636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1633, UInt<1>(0h1), "") : assert_75 node _T_1637 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1637 : node _T_1638 = asUInt(reset) node _T_1639 = eq(_T_1638, UInt<1>(0h0)) when _T_1639 : node _T_1640 = eq(source_ok_1, UInt<1>(0h0)) when _T_1640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1641 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1642 = asUInt(reset) node _T_1643 = eq(_T_1642, UInt<1>(0h0)) when _T_1643 : node _T_1644 = eq(_T_1641, UInt<1>(0h0)) when _T_1644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1641, UInt<1>(0h1), "") : assert_77 node _T_1645 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1646 = or(_T_1645, io.in.d.bits.corrupt) node _T_1647 = asUInt(reset) node _T_1648 = eq(_T_1647, UInt<1>(0h0)) when _T_1648 : node _T_1649 = eq(_T_1646, UInt<1>(0h0)) when _T_1649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1646, UInt<1>(0h1), "") : assert_78 node _T_1650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1651 = or(UInt<1>(0h1), _T_1650) node _T_1652 = asUInt(reset) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) when _T_1653 : node _T_1654 = eq(_T_1651, UInt<1>(0h0)) when _T_1654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1651, UInt<1>(0h1), "") : assert_79 node _T_1655 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1655 : node _T_1656 = asUInt(reset) node _T_1657 = eq(_T_1656, UInt<1>(0h0)) when _T_1657 : node _T_1658 = eq(source_ok_1, UInt<1>(0h0)) when _T_1658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1659 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1660 = asUInt(reset) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) when _T_1661 : node _T_1662 = eq(_T_1659, UInt<1>(0h0)) when _T_1662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1659, UInt<1>(0h1), "") : assert_81 node _T_1663 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1664 = asUInt(reset) node _T_1665 = eq(_T_1664, UInt<1>(0h0)) when _T_1665 : node _T_1666 = eq(_T_1663, UInt<1>(0h0)) when _T_1666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1663, UInt<1>(0h1), "") : assert_82 node _T_1667 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1668 = or(UInt<1>(0h1), _T_1667) node _T_1669 = asUInt(reset) node _T_1670 = eq(_T_1669, UInt<1>(0h0)) when _T_1670 : node _T_1671 = eq(_T_1668, UInt<1>(0h0)) when _T_1671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1668, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1672 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1673 = asUInt(reset) node _T_1674 = eq(_T_1673, UInt<1>(0h0)) when _T_1674 : node _T_1675 = eq(_T_1672, UInt<1>(0h0)) when _T_1675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1672, UInt<1>(0h1), "") : assert_84 node _T_1676 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) node _T_1678 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1679 = cvt(_T_1678) node _T_1680 = and(_T_1679, asSInt(UInt<1>(0h0))) node _T_1681 = asSInt(_T_1680) node _T_1682 = eq(_T_1681, asSInt(UInt<1>(0h0))) node _T_1683 = or(_T_1677, _T_1682) node _uncommonBits_T_44 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_1684 = shr(io.in.b.bits.source, 2) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) node _T_1686 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1687 = and(_T_1685, _T_1686) node _T_1688 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_1689 = and(_T_1687, _T_1688) node _T_1690 = eq(_T_1689, UInt<1>(0h0)) node _T_1691 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1692 = cvt(_T_1691) node _T_1693 = and(_T_1692, asSInt(UInt<1>(0h0))) node _T_1694 = asSInt(_T_1693) node _T_1695 = eq(_T_1694, asSInt(UInt<1>(0h0))) node _T_1696 = or(_T_1690, _T_1695) node _uncommonBits_T_45 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1697 = shr(io.in.b.bits.source, 2) node _T_1698 = eq(_T_1697, UInt<1>(0h1)) node _T_1699 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1700 = and(_T_1698, _T_1699) node _T_1701 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1702 = and(_T_1700, _T_1701) node _T_1703 = eq(_T_1702, UInt<1>(0h0)) node _T_1704 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1705 = cvt(_T_1704) node _T_1706 = and(_T_1705, asSInt(UInt<1>(0h0))) node _T_1707 = asSInt(_T_1706) node _T_1708 = eq(_T_1707, asSInt(UInt<1>(0h0))) node _T_1709 = or(_T_1703, _T_1708) node _uncommonBits_T_46 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1710 = shr(io.in.b.bits.source, 2) node _T_1711 = eq(_T_1710, UInt<2>(0h2)) node _T_1712 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1713 = and(_T_1711, _T_1712) node _T_1714 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1715 = and(_T_1713, _T_1714) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) node _T_1717 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1718 = cvt(_T_1717) node _T_1719 = and(_T_1718, asSInt(UInt<1>(0h0))) node _T_1720 = asSInt(_T_1719) node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0))) node _T_1722 = or(_T_1716, _T_1721) node _uncommonBits_T_47 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1723 = shr(io.in.b.bits.source, 2) node _T_1724 = eq(_T_1723, UInt<2>(0h3)) node _T_1725 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1726 = and(_T_1724, _T_1725) node _T_1727 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1728 = and(_T_1726, _T_1727) node _T_1729 = eq(_T_1728, UInt<1>(0h0)) node _T_1730 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1731 = cvt(_T_1730) node _T_1732 = and(_T_1731, asSInt(UInt<1>(0h0))) node _T_1733 = asSInt(_T_1732) node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0))) node _T_1735 = or(_T_1729, _T_1734) node _T_1736 = eq(io.in.b.bits.source, UInt<7>(0h4c)) node _T_1737 = eq(_T_1736, UInt<1>(0h0)) node _T_1738 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1739 = cvt(_T_1738) node _T_1740 = and(_T_1739, asSInt(UInt<1>(0h0))) node _T_1741 = asSInt(_T_1740) node _T_1742 = eq(_T_1741, asSInt(UInt<1>(0h0))) node _T_1743 = or(_T_1737, _T_1742) node _T_1744 = eq(io.in.b.bits.source, UInt<7>(0h4e)) node _T_1745 = eq(_T_1744, UInt<1>(0h0)) node _T_1746 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1747 = cvt(_T_1746) node _T_1748 = and(_T_1747, asSInt(UInt<1>(0h0))) node _T_1749 = asSInt(_T_1748) node _T_1750 = eq(_T_1749, asSInt(UInt<1>(0h0))) node _T_1751 = or(_T_1745, _T_1750) node _T_1752 = eq(io.in.b.bits.source, UInt<7>(0h48)) node _T_1753 = eq(_T_1752, UInt<1>(0h0)) node _T_1754 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1755 = cvt(_T_1754) node _T_1756 = and(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = asSInt(_T_1756) node _T_1758 = eq(_T_1757, asSInt(UInt<1>(0h0))) node _T_1759 = or(_T_1753, _T_1758) node _T_1760 = eq(io.in.b.bits.source, UInt<7>(0h4a)) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) node _T_1762 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<1>(0h0))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1761, _T_1766) node _T_1768 = eq(io.in.b.bits.source, UInt<7>(0h44)) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1771 = cvt(_T_1770) node _T_1772 = and(_T_1771, asSInt(UInt<1>(0h0))) node _T_1773 = asSInt(_T_1772) node _T_1774 = eq(_T_1773, asSInt(UInt<1>(0h0))) node _T_1775 = or(_T_1769, _T_1774) node _T_1776 = eq(io.in.b.bits.source, UInt<7>(0h46)) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) node _T_1778 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1779 = cvt(_T_1778) node _T_1780 = and(_T_1779, asSInt(UInt<1>(0h0))) node _T_1781 = asSInt(_T_1780) node _T_1782 = eq(_T_1781, asSInt(UInt<1>(0h0))) node _T_1783 = or(_T_1777, _T_1782) node _T_1784 = eq(io.in.b.bits.source, UInt<7>(0h40)) node _T_1785 = eq(_T_1784, UInt<1>(0h0)) node _T_1786 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1787 = cvt(_T_1786) node _T_1788 = and(_T_1787, asSInt(UInt<1>(0h0))) node _T_1789 = asSInt(_T_1788) node _T_1790 = eq(_T_1789, asSInt(UInt<1>(0h0))) node _T_1791 = or(_T_1785, _T_1790) node _T_1792 = eq(io.in.b.bits.source, UInt<7>(0h42)) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) node _T_1794 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1795 = cvt(_T_1794) node _T_1796 = and(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = asSInt(_T_1796) node _T_1798 = eq(_T_1797, asSInt(UInt<1>(0h0))) node _T_1799 = or(_T_1793, _T_1798) node _T_1800 = eq(io.in.b.bits.source, UInt<6>(0h3c)) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) node _T_1802 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<1>(0h0))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = or(_T_1801, _T_1806) node _T_1808 = eq(io.in.b.bits.source, UInt<6>(0h3e)) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) node _T_1810 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1811 = cvt(_T_1810) node _T_1812 = and(_T_1811, asSInt(UInt<1>(0h0))) node _T_1813 = asSInt(_T_1812) node _T_1814 = eq(_T_1813, asSInt(UInt<1>(0h0))) node _T_1815 = or(_T_1809, _T_1814) node _T_1816 = eq(io.in.b.bits.source, UInt<6>(0h38)) node _T_1817 = eq(_T_1816, UInt<1>(0h0)) node _T_1818 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1819 = cvt(_T_1818) node _T_1820 = and(_T_1819, asSInt(UInt<1>(0h0))) node _T_1821 = asSInt(_T_1820) node _T_1822 = eq(_T_1821, asSInt(UInt<1>(0h0))) node _T_1823 = or(_T_1817, _T_1822) node _T_1824 = eq(io.in.b.bits.source, UInt<6>(0h3a)) node _T_1825 = eq(_T_1824, UInt<1>(0h0)) node _T_1826 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1827 = cvt(_T_1826) node _T_1828 = and(_T_1827, asSInt(UInt<1>(0h0))) node _T_1829 = asSInt(_T_1828) node _T_1830 = eq(_T_1829, asSInt(UInt<1>(0h0))) node _T_1831 = or(_T_1825, _T_1830) node _T_1832 = eq(io.in.b.bits.source, UInt<6>(0h34)) node _T_1833 = eq(_T_1832, UInt<1>(0h0)) node _T_1834 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1835 = cvt(_T_1834) node _T_1836 = and(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = asSInt(_T_1836) node _T_1838 = eq(_T_1837, asSInt(UInt<1>(0h0))) node _T_1839 = or(_T_1833, _T_1838) node _T_1840 = eq(io.in.b.bits.source, UInt<6>(0h36)) node _T_1841 = eq(_T_1840, UInt<1>(0h0)) node _T_1842 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1843 = cvt(_T_1842) node _T_1844 = and(_T_1843, asSInt(UInt<1>(0h0))) node _T_1845 = asSInt(_T_1844) node _T_1846 = eq(_T_1845, asSInt(UInt<1>(0h0))) node _T_1847 = or(_T_1841, _T_1846) node _T_1848 = eq(io.in.b.bits.source, UInt<6>(0h30)) node _T_1849 = eq(_T_1848, UInt<1>(0h0)) node _T_1850 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1851 = cvt(_T_1850) node _T_1852 = and(_T_1851, asSInt(UInt<1>(0h0))) node _T_1853 = asSInt(_T_1852) node _T_1854 = eq(_T_1853, asSInt(UInt<1>(0h0))) node _T_1855 = or(_T_1849, _T_1854) node _T_1856 = eq(io.in.b.bits.source, UInt<6>(0h32)) node _T_1857 = eq(_T_1856, UInt<1>(0h0)) node _T_1858 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1859 = cvt(_T_1858) node _T_1860 = and(_T_1859, asSInt(UInt<1>(0h0))) node _T_1861 = asSInt(_T_1860) node _T_1862 = eq(_T_1861, asSInt(UInt<1>(0h0))) node _T_1863 = or(_T_1857, _T_1862) node _T_1864 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1865 = eq(_T_1864, UInt<1>(0h0)) node _T_1866 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1867 = cvt(_T_1866) node _T_1868 = and(_T_1867, asSInt(UInt<1>(0h0))) node _T_1869 = asSInt(_T_1868) node _T_1870 = eq(_T_1869, asSInt(UInt<1>(0h0))) node _T_1871 = or(_T_1865, _T_1870) node _T_1872 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) node _T_1874 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1875 = cvt(_T_1874) node _T_1876 = and(_T_1875, asSInt(UInt<1>(0h0))) node _T_1877 = asSInt(_T_1876) node _T_1878 = eq(_T_1877, asSInt(UInt<1>(0h0))) node _T_1879 = or(_T_1873, _T_1878) node _T_1880 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) node _T_1882 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1883 = cvt(_T_1882) node _T_1884 = and(_T_1883, asSInt(UInt<1>(0h0))) node _T_1885 = asSInt(_T_1884) node _T_1886 = eq(_T_1885, asSInt(UInt<1>(0h0))) node _T_1887 = or(_T_1881, _T_1886) node _T_1888 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1889 = eq(_T_1888, UInt<1>(0h0)) node _T_1890 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1891 = cvt(_T_1890) node _T_1892 = and(_T_1891, asSInt(UInt<1>(0h0))) node _T_1893 = asSInt(_T_1892) node _T_1894 = eq(_T_1893, asSInt(UInt<1>(0h0))) node _T_1895 = or(_T_1889, _T_1894) node _T_1896 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1897 = eq(_T_1896, UInt<1>(0h0)) node _T_1898 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1899 = cvt(_T_1898) node _T_1900 = and(_T_1899, asSInt(UInt<1>(0h0))) node _T_1901 = asSInt(_T_1900) node _T_1902 = eq(_T_1901, asSInt(UInt<1>(0h0))) node _T_1903 = or(_T_1897, _T_1902) node _T_1904 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1905 = eq(_T_1904, UInt<1>(0h0)) node _T_1906 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1907 = cvt(_T_1906) node _T_1908 = and(_T_1907, asSInt(UInt<1>(0h0))) node _T_1909 = asSInt(_T_1908) node _T_1910 = eq(_T_1909, asSInt(UInt<1>(0h0))) node _T_1911 = or(_T_1905, _T_1910) node _T_1912 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1913 = eq(_T_1912, UInt<1>(0h0)) node _T_1914 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1915 = cvt(_T_1914) node _T_1916 = and(_T_1915, asSInt(UInt<1>(0h0))) node _T_1917 = asSInt(_T_1916) node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0))) node _T_1919 = or(_T_1913, _T_1918) node _T_1920 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) node _T_1922 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1923 = cvt(_T_1922) node _T_1924 = and(_T_1923, asSInt(UInt<1>(0h0))) node _T_1925 = asSInt(_T_1924) node _T_1926 = eq(_T_1925, asSInt(UInt<1>(0h0))) node _T_1927 = or(_T_1921, _T_1926) node _T_1928 = and(_T_1683, _T_1696) node _T_1929 = and(_T_1928, _T_1709) node _T_1930 = and(_T_1929, _T_1722) node _T_1931 = and(_T_1930, _T_1735) node _T_1932 = and(_T_1931, _T_1743) node _T_1933 = and(_T_1932, _T_1751) node _T_1934 = and(_T_1933, _T_1759) node _T_1935 = and(_T_1934, _T_1767) node _T_1936 = and(_T_1935, _T_1775) node _T_1937 = and(_T_1936, _T_1783) node _T_1938 = and(_T_1937, _T_1791) node _T_1939 = and(_T_1938, _T_1799) node _T_1940 = and(_T_1939, _T_1807) node _T_1941 = and(_T_1940, _T_1815) node _T_1942 = and(_T_1941, _T_1823) node _T_1943 = and(_T_1942, _T_1831) node _T_1944 = and(_T_1943, _T_1839) node _T_1945 = and(_T_1944, _T_1847) node _T_1946 = and(_T_1945, _T_1855) node _T_1947 = and(_T_1946, _T_1863) node _T_1948 = and(_T_1947, _T_1871) node _T_1949 = and(_T_1948, _T_1879) node _T_1950 = and(_T_1949, _T_1887) node _T_1951 = and(_T_1950, _T_1895) node _T_1952 = and(_T_1951, _T_1903) node _T_1953 = and(_T_1952, _T_1911) node _T_1954 = and(_T_1953, _T_1919) node _T_1955 = and(_T_1954, _T_1927) node _T_1956 = asUInt(reset) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) when _T_1957 : node _T_1958 = eq(_T_1955, UInt<1>(0h0)) when _T_1958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1955, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h100c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<7>(0h4c)) node _legal_source_T_26 = eq(io.in.b.bits.source, UInt<7>(0h4e)) node _legal_source_T_27 = eq(io.in.b.bits.source, UInt<7>(0h48)) node _legal_source_T_28 = eq(io.in.b.bits.source, UInt<7>(0h4a)) node _legal_source_T_29 = eq(io.in.b.bits.source, UInt<7>(0h44)) node _legal_source_T_30 = eq(io.in.b.bits.source, UInt<7>(0h46)) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<7>(0h40)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<7>(0h42)) node _legal_source_T_33 = eq(io.in.b.bits.source, UInt<6>(0h3c)) node _legal_source_T_34 = eq(io.in.b.bits.source, UInt<6>(0h3e)) node _legal_source_T_35 = eq(io.in.b.bits.source, UInt<6>(0h38)) node _legal_source_T_36 = eq(io.in.b.bits.source, UInt<6>(0h3a)) node _legal_source_T_37 = eq(io.in.b.bits.source, UInt<6>(0h34)) node _legal_source_T_38 = eq(io.in.b.bits.source, UInt<6>(0h36)) node _legal_source_T_39 = eq(io.in.b.bits.source, UInt<6>(0h30)) node _legal_source_T_40 = eq(io.in.b.bits.source, UInt<6>(0h32)) node _legal_source_T_41 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _legal_source_T_42 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _legal_source_T_43 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_44 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _legal_source_T_45 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _legal_source_T_46 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _legal_source_T_47 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _legal_source_T_48 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _legal_source_WIRE : UInt<1>[29] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_25 connect _legal_source_WIRE[6], _legal_source_T_26 connect _legal_source_WIRE[7], _legal_source_T_27 connect _legal_source_WIRE[8], _legal_source_T_28 connect _legal_source_WIRE[9], _legal_source_T_29 connect _legal_source_WIRE[10], _legal_source_T_30 connect _legal_source_WIRE[11], _legal_source_T_31 connect _legal_source_WIRE[12], _legal_source_T_32 connect _legal_source_WIRE[13], _legal_source_T_33 connect _legal_source_WIRE[14], _legal_source_T_34 connect _legal_source_WIRE[15], _legal_source_T_35 connect _legal_source_WIRE[16], _legal_source_T_36 connect _legal_source_WIRE[17], _legal_source_T_37 connect _legal_source_WIRE[18], _legal_source_T_38 connect _legal_source_WIRE[19], _legal_source_T_39 connect _legal_source_WIRE[20], _legal_source_T_40 connect _legal_source_WIRE[21], _legal_source_T_41 connect _legal_source_WIRE[22], _legal_source_T_42 connect _legal_source_WIRE[23], _legal_source_T_43 connect _legal_source_WIRE[24], _legal_source_T_44 connect _legal_source_WIRE[25], _legal_source_T_45 connect _legal_source_WIRE[26], _legal_source_T_46 connect _legal_source_WIRE[27], _legal_source_T_47 connect _legal_source_WIRE[28], _legal_source_T_48 node _legal_source_T_49 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_50 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_51 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_52 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_53 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_54 = mux(_legal_source_WIRE[5], UInt<7>(0h4c), UInt<1>(0h0)) node _legal_source_T_55 = mux(_legal_source_WIRE[6], UInt<7>(0h4e), UInt<1>(0h0)) node _legal_source_T_56 = mux(_legal_source_WIRE[7], UInt<7>(0h48), UInt<1>(0h0)) node _legal_source_T_57 = mux(_legal_source_WIRE[8], UInt<7>(0h4a), UInt<1>(0h0)) node _legal_source_T_58 = mux(_legal_source_WIRE[9], UInt<7>(0h44), UInt<1>(0h0)) node _legal_source_T_59 = mux(_legal_source_WIRE[10], UInt<7>(0h46), UInt<1>(0h0)) node _legal_source_T_60 = mux(_legal_source_WIRE[11], UInt<7>(0h40), UInt<1>(0h0)) node _legal_source_T_61 = mux(_legal_source_WIRE[12], UInt<7>(0h42), UInt<1>(0h0)) node _legal_source_T_62 = mux(_legal_source_WIRE[13], UInt<6>(0h3c), UInt<1>(0h0)) node _legal_source_T_63 = mux(_legal_source_WIRE[14], UInt<6>(0h3e), UInt<1>(0h0)) node _legal_source_T_64 = mux(_legal_source_WIRE[15], UInt<6>(0h38), UInt<1>(0h0)) node _legal_source_T_65 = mux(_legal_source_WIRE[16], UInt<6>(0h3a), UInt<1>(0h0)) node _legal_source_T_66 = mux(_legal_source_WIRE[17], UInt<6>(0h34), UInt<1>(0h0)) node _legal_source_T_67 = mux(_legal_source_WIRE[18], UInt<6>(0h36), UInt<1>(0h0)) node _legal_source_T_68 = mux(_legal_source_WIRE[19], UInt<6>(0h30), UInt<1>(0h0)) node _legal_source_T_69 = mux(_legal_source_WIRE[20], UInt<6>(0h32), UInt<1>(0h0)) node _legal_source_T_70 = mux(_legal_source_WIRE[21], UInt<6>(0h2c), UInt<1>(0h0)) node _legal_source_T_71 = mux(_legal_source_WIRE[22], UInt<6>(0h2e), UInt<1>(0h0)) node _legal_source_T_72 = mux(_legal_source_WIRE[23], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_73 = mux(_legal_source_WIRE[24], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_74 = mux(_legal_source_WIRE[25], UInt<6>(0h24), UInt<1>(0h0)) node _legal_source_T_75 = mux(_legal_source_WIRE[26], UInt<6>(0h26), UInt<1>(0h0)) node _legal_source_T_76 = mux(_legal_source_WIRE[27], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_77 = mux(_legal_source_WIRE[28], UInt<6>(0h22), UInt<1>(0h0)) node _legal_source_T_78 = or(_legal_source_T_49, _legal_source_T_50) node _legal_source_T_79 = or(_legal_source_T_78, _legal_source_T_51) node _legal_source_T_80 = or(_legal_source_T_79, _legal_source_T_52) node _legal_source_T_81 = or(_legal_source_T_80, _legal_source_T_53) node _legal_source_T_82 = or(_legal_source_T_81, _legal_source_T_54) node _legal_source_T_83 = or(_legal_source_T_82, _legal_source_T_55) node _legal_source_T_84 = or(_legal_source_T_83, _legal_source_T_56) node _legal_source_T_85 = or(_legal_source_T_84, _legal_source_T_57) node _legal_source_T_86 = or(_legal_source_T_85, _legal_source_T_58) node _legal_source_T_87 = or(_legal_source_T_86, _legal_source_T_59) node _legal_source_T_88 = or(_legal_source_T_87, _legal_source_T_60) node _legal_source_T_89 = or(_legal_source_T_88, _legal_source_T_61) node _legal_source_T_90 = or(_legal_source_T_89, _legal_source_T_62) node _legal_source_T_91 = or(_legal_source_T_90, _legal_source_T_63) node _legal_source_T_92 = or(_legal_source_T_91, _legal_source_T_64) node _legal_source_T_93 = or(_legal_source_T_92, _legal_source_T_65) node _legal_source_T_94 = or(_legal_source_T_93, _legal_source_T_66) node _legal_source_T_95 = or(_legal_source_T_94, _legal_source_T_67) node _legal_source_T_96 = or(_legal_source_T_95, _legal_source_T_68) node _legal_source_T_97 = or(_legal_source_T_96, _legal_source_T_69) node _legal_source_T_98 = or(_legal_source_T_97, _legal_source_T_70) node _legal_source_T_99 = or(_legal_source_T_98, _legal_source_T_71) node _legal_source_T_100 = or(_legal_source_T_99, _legal_source_T_72) node _legal_source_T_101 = or(_legal_source_T_100, _legal_source_T_73) node _legal_source_T_102 = or(_legal_source_T_101, _legal_source_T_74) node _legal_source_T_103 = or(_legal_source_T_102, _legal_source_T_75) node _legal_source_T_104 = or(_legal_source_T_103, _legal_source_T_76) node _legal_source_T_105 = or(_legal_source_T_104, _legal_source_T_77) wire _legal_source_WIRE_1 : UInt<7> connect _legal_source_WIRE_1, _legal_source_T_105 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1959 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1959 : node _T_1960 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1961 = shr(io.in.b.bits.source, 2) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) node _T_1963 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1964 = and(_T_1962, _T_1963) node _T_1965 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1966 = and(_T_1964, _T_1965) node _uncommonBits_T_49 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1967 = shr(io.in.b.bits.source, 2) node _T_1968 = eq(_T_1967, UInt<1>(0h1)) node _T_1969 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1970 = and(_T_1968, _T_1969) node _T_1971 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1972 = and(_T_1970, _T_1971) node _uncommonBits_T_50 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1973 = shr(io.in.b.bits.source, 2) node _T_1974 = eq(_T_1973, UInt<2>(0h2)) node _T_1975 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1976 = and(_T_1974, _T_1975) node _T_1977 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1978 = and(_T_1976, _T_1977) node _uncommonBits_T_51 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1979 = shr(io.in.b.bits.source, 2) node _T_1980 = eq(_T_1979, UInt<2>(0h3)) node _T_1981 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1982 = and(_T_1980, _T_1981) node _T_1983 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1984 = and(_T_1982, _T_1983) node _T_1985 = eq(io.in.b.bits.source, UInt<7>(0h4c)) node _T_1986 = eq(io.in.b.bits.source, UInt<7>(0h4e)) node _T_1987 = eq(io.in.b.bits.source, UInt<7>(0h48)) node _T_1988 = eq(io.in.b.bits.source, UInt<7>(0h4a)) node _T_1989 = eq(io.in.b.bits.source, UInt<7>(0h44)) node _T_1990 = eq(io.in.b.bits.source, UInt<7>(0h46)) node _T_1991 = eq(io.in.b.bits.source, UInt<7>(0h40)) node _T_1992 = eq(io.in.b.bits.source, UInt<7>(0h42)) node _T_1993 = eq(io.in.b.bits.source, UInt<6>(0h3c)) node _T_1994 = eq(io.in.b.bits.source, UInt<6>(0h3e)) node _T_1995 = eq(io.in.b.bits.source, UInt<6>(0h38)) node _T_1996 = eq(io.in.b.bits.source, UInt<6>(0h3a)) node _T_1997 = eq(io.in.b.bits.source, UInt<6>(0h34)) node _T_1998 = eq(io.in.b.bits.source, UInt<6>(0h36)) node _T_1999 = eq(io.in.b.bits.source, UInt<6>(0h30)) node _T_2000 = eq(io.in.b.bits.source, UInt<6>(0h32)) node _T_2001 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_2002 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_2003 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_2004 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_2005 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_2006 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_2007 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_2008 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _WIRE_4 : UInt<1>[29] connect _WIRE_4[0], _T_1960 connect _WIRE_4[1], _T_1966 connect _WIRE_4[2], _T_1972 connect _WIRE_4[3], _T_1978 connect _WIRE_4[4], _T_1984 connect _WIRE_4[5], _T_1985 connect _WIRE_4[6], _T_1986 connect _WIRE_4[7], _T_1987 connect _WIRE_4[8], _T_1988 connect _WIRE_4[9], _T_1989 connect _WIRE_4[10], _T_1990 connect _WIRE_4[11], _T_1991 connect _WIRE_4[12], _T_1992 connect _WIRE_4[13], _T_1993 connect _WIRE_4[14], _T_1994 connect _WIRE_4[15], _T_1995 connect _WIRE_4[16], _T_1996 connect _WIRE_4[17], _T_1997 connect _WIRE_4[18], _T_1998 connect _WIRE_4[19], _T_1999 connect _WIRE_4[20], _T_2000 connect _WIRE_4[21], _T_2001 connect _WIRE_4[22], _T_2002 connect _WIRE_4[23], _T_2003 connect _WIRE_4[24], _T_2004 connect _WIRE_4[25], _T_2005 connect _WIRE_4[26], _T_2006 connect _WIRE_4[27], _T_2007 connect _WIRE_4[28], _T_2008 node _T_2009 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2010 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2011 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2012 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2013 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2014 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2015 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2016 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2017 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2018 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2019 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2020 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2021 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2022 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2023 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2024 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2025 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2026 = mux(_WIRE_4[5], _T_2009, UInt<1>(0h0)) node _T_2027 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_2028 = mux(_WIRE_4[7], _T_2010, UInt<1>(0h0)) node _T_2029 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_2030 = mux(_WIRE_4[9], _T_2011, UInt<1>(0h0)) node _T_2031 = mux(_WIRE_4[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_2032 = mux(_WIRE_4[11], _T_2012, UInt<1>(0h0)) node _T_2033 = mux(_WIRE_4[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_2034 = mux(_WIRE_4[13], _T_2013, UInt<1>(0h0)) node _T_2035 = mux(_WIRE_4[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_2036 = mux(_WIRE_4[15], _T_2014, UInt<1>(0h0)) node _T_2037 = mux(_WIRE_4[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_2038 = mux(_WIRE_4[17], _T_2015, UInt<1>(0h0)) node _T_2039 = mux(_WIRE_4[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_2040 = mux(_WIRE_4[19], _T_2016, UInt<1>(0h0)) node _T_2041 = mux(_WIRE_4[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_2042 = mux(_WIRE_4[21], _T_2017, UInt<1>(0h0)) node _T_2043 = mux(_WIRE_4[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_2044 = mux(_WIRE_4[23], _T_2018, UInt<1>(0h0)) node _T_2045 = mux(_WIRE_4[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_2046 = mux(_WIRE_4[25], _T_2019, UInt<1>(0h0)) node _T_2047 = mux(_WIRE_4[26], UInt<1>(0h0), UInt<1>(0h0)) node _T_2048 = mux(_WIRE_4[27], _T_2020, UInt<1>(0h0)) node _T_2049 = mux(_WIRE_4[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_2050 = or(_T_2021, _T_2022) node _T_2051 = or(_T_2050, _T_2023) node _T_2052 = or(_T_2051, _T_2024) node _T_2053 = or(_T_2052, _T_2025) node _T_2054 = or(_T_2053, _T_2026) node _T_2055 = or(_T_2054, _T_2027) node _T_2056 = or(_T_2055, _T_2028) node _T_2057 = or(_T_2056, _T_2029) node _T_2058 = or(_T_2057, _T_2030) node _T_2059 = or(_T_2058, _T_2031) node _T_2060 = or(_T_2059, _T_2032) node _T_2061 = or(_T_2060, _T_2033) node _T_2062 = or(_T_2061, _T_2034) node _T_2063 = or(_T_2062, _T_2035) node _T_2064 = or(_T_2063, _T_2036) node _T_2065 = or(_T_2064, _T_2037) node _T_2066 = or(_T_2065, _T_2038) node _T_2067 = or(_T_2066, _T_2039) node _T_2068 = or(_T_2067, _T_2040) node _T_2069 = or(_T_2068, _T_2041) node _T_2070 = or(_T_2069, _T_2042) node _T_2071 = or(_T_2070, _T_2043) node _T_2072 = or(_T_2071, _T_2044) node _T_2073 = or(_T_2072, _T_2045) node _T_2074 = or(_T_2073, _T_2046) node _T_2075 = or(_T_2074, _T_2047) node _T_2076 = or(_T_2075, _T_2048) node _T_2077 = or(_T_2076, _T_2049) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_2077 node _T_2078 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_2079 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_2080 = and(_T_2078, _T_2079) node _T_2081 = or(UInt<1>(0h0), _T_2080) node _T_2082 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_2083 = cvt(_T_2082) node _T_2084 = and(_T_2083, asSInt(UInt<17>(0h100c0))) node _T_2085 = asSInt(_T_2084) node _T_2086 = eq(_T_2085, asSInt(UInt<1>(0h0))) node _T_2087 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_2088 = cvt(_T_2087) node _T_2089 = and(_T_2088, asSInt(UInt<29>(0h100000c0))) node _T_2090 = asSInt(_T_2089) node _T_2091 = eq(_T_2090, asSInt(UInt<1>(0h0))) node _T_2092 = or(_T_2086, _T_2091) node _T_2093 = and(_T_2081, _T_2092) node _T_2094 = or(UInt<1>(0h0), _T_2093) node _T_2095 = and(_WIRE_5, _T_2094) node _T_2096 = asUInt(reset) node _T_2097 = eq(_T_2096, UInt<1>(0h0)) when _T_2097 : node _T_2098 = eq(_T_2095, UInt<1>(0h0)) when _T_2098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_2095, UInt<1>(0h1), "") : assert_86 node _T_2099 = asUInt(reset) node _T_2100 = eq(_T_2099, UInt<1>(0h0)) when _T_2100 : node _T_2101 = eq(address_ok, UInt<1>(0h0)) when _T_2101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_2102 = asUInt(reset) node _T_2103 = eq(_T_2102, UInt<1>(0h0)) when _T_2103 : node _T_2104 = eq(legal_source, UInt<1>(0h0)) when _T_2104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_2105 = asUInt(reset) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(is_aligned_1, UInt<1>(0h0)) when _T_2107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_2108 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_2109 = asUInt(reset) node _T_2110 = eq(_T_2109, UInt<1>(0h0)) when _T_2110 : node _T_2111 = eq(_T_2108, UInt<1>(0h0)) when _T_2111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_2108, UInt<1>(0h1), "") : assert_90 node _T_2112 = eq(io.in.b.bits.mask, mask_1) node _T_2113 = asUInt(reset) node _T_2114 = eq(_T_2113, UInt<1>(0h0)) when _T_2114 : node _T_2115 = eq(_T_2112, UInt<1>(0h0)) when _T_2115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_2112, UInt<1>(0h1), "") : assert_91 node _T_2116 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_2117 = asUInt(reset) node _T_2118 = eq(_T_2117, UInt<1>(0h0)) when _T_2118 : node _T_2119 = eq(_T_2116, UInt<1>(0h0)) when _T_2119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2116, UInt<1>(0h1), "") : assert_92 node _T_2120 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_2120 : node _T_2121 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_2122 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_2123 = and(_T_2121, _T_2122) node _T_2124 = or(UInt<1>(0h0), _T_2123) node _T_2125 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_2126 = cvt(_T_2125) node _T_2127 = and(_T_2126, asSInt(UInt<17>(0h100c0))) node _T_2128 = asSInt(_T_2127) node _T_2129 = eq(_T_2128, asSInt(UInt<1>(0h0))) node _T_2130 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_2131 = cvt(_T_2130) node _T_2132 = and(_T_2131, asSInt(UInt<29>(0h100000c0))) node _T_2133 = asSInt(_T_2132) node _T_2134 = eq(_T_2133, asSInt(UInt<1>(0h0))) node _T_2135 = or(_T_2129, _T_2134) node _T_2136 = and(_T_2124, _T_2135) node _T_2137 = or(UInt<1>(0h0), _T_2136) node _T_2138 = and(UInt<1>(0h0), _T_2137) node _T_2139 = asUInt(reset) node _T_2140 = eq(_T_2139, UInt<1>(0h0)) when _T_2140 : node _T_2141 = eq(_T_2138, UInt<1>(0h0)) when _T_2141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_2138, UInt<1>(0h1), "") : assert_93 node _T_2142 = asUInt(reset) node _T_2143 = eq(_T_2142, UInt<1>(0h0)) when _T_2143 : node _T_2144 = eq(address_ok, UInt<1>(0h0)) when _T_2144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_2145 = asUInt(reset) node _T_2146 = eq(_T_2145, UInt<1>(0h0)) when _T_2146 : node _T_2147 = eq(legal_source, UInt<1>(0h0)) when _T_2147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_2148 = asUInt(reset) node _T_2149 = eq(_T_2148, UInt<1>(0h0)) when _T_2149 : node _T_2150 = eq(is_aligned_1, UInt<1>(0h0)) when _T_2150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_2151 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_2152 = asUInt(reset) node _T_2153 = eq(_T_2152, UInt<1>(0h0)) when _T_2153 : node _T_2154 = eq(_T_2151, UInt<1>(0h0)) when _T_2154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_2151, UInt<1>(0h1), "") : assert_97 node _T_2155 = eq(io.in.b.bits.mask, mask_1) node _T_2156 = asUInt(reset) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) when _T_2157 : node _T_2158 = eq(_T_2155, UInt<1>(0h0)) when _T_2158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2155, UInt<1>(0h1), "") : assert_98 node _T_2159 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_2160 = asUInt(reset) node _T_2161 = eq(_T_2160, UInt<1>(0h0)) when _T_2161 : node _T_2162 = eq(_T_2159, UInt<1>(0h0)) when _T_2162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_2159, UInt<1>(0h1), "") : assert_99 node _T_2163 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_2163 : node _T_2164 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_2165 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_2166 = and(_T_2164, _T_2165) node _T_2167 = or(UInt<1>(0h0), _T_2166) node _T_2168 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_2169 = cvt(_T_2168) node _T_2170 = and(_T_2169, asSInt(UInt<17>(0h100c0))) node _T_2171 = asSInt(_T_2170) node _T_2172 = eq(_T_2171, asSInt(UInt<1>(0h0))) node _T_2173 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_2174 = cvt(_T_2173) node _T_2175 = and(_T_2174, asSInt(UInt<29>(0h100000c0))) node _T_2176 = asSInt(_T_2175) node _T_2177 = eq(_T_2176, asSInt(UInt<1>(0h0))) node _T_2178 = or(_T_2172, _T_2177) node _T_2179 = and(_T_2167, _T_2178) node _T_2180 = or(UInt<1>(0h0), _T_2179) node _T_2181 = and(UInt<1>(0h0), _T_2180) node _T_2182 = asUInt(reset) node _T_2183 = eq(_T_2182, UInt<1>(0h0)) when _T_2183 : node _T_2184 = eq(_T_2181, UInt<1>(0h0)) when _T_2184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_2181, UInt<1>(0h1), "") : assert_100 node _T_2185 = asUInt(reset) node _T_2186 = eq(_T_2185, UInt<1>(0h0)) when _T_2186 : node _T_2187 = eq(address_ok, UInt<1>(0h0)) when _T_2187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_2188 = asUInt(reset) node _T_2189 = eq(_T_2188, UInt<1>(0h0)) when _T_2189 : node _T_2190 = eq(legal_source, UInt<1>(0h0)) when _T_2190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_2191 = asUInt(reset) node _T_2192 = eq(_T_2191, UInt<1>(0h0)) when _T_2192 : node _T_2193 = eq(is_aligned_1, UInt<1>(0h0)) when _T_2193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_2194 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_2195 = asUInt(reset) node _T_2196 = eq(_T_2195, UInt<1>(0h0)) when _T_2196 : node _T_2197 = eq(_T_2194, UInt<1>(0h0)) when _T_2197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_2194, UInt<1>(0h1), "") : assert_104 node _T_2198 = eq(io.in.b.bits.mask, mask_1) node _T_2199 = asUInt(reset) node _T_2200 = eq(_T_2199, UInt<1>(0h0)) when _T_2200 : node _T_2201 = eq(_T_2198, UInt<1>(0h0)) when _T_2201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2198, UInt<1>(0h1), "") : assert_105 node _T_2202 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_2202 : node _T_2203 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_2204 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_2205 = and(_T_2203, _T_2204) node _T_2206 = or(UInt<1>(0h0), _T_2205) node _T_2207 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_2208 = cvt(_T_2207) node _T_2209 = and(_T_2208, asSInt(UInt<17>(0h100c0))) node _T_2210 = asSInt(_T_2209) node _T_2211 = eq(_T_2210, asSInt(UInt<1>(0h0))) node _T_2212 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_2213 = cvt(_T_2212) node _T_2214 = and(_T_2213, asSInt(UInt<29>(0h100000c0))) node _T_2215 = asSInt(_T_2214) node _T_2216 = eq(_T_2215, asSInt(UInt<1>(0h0))) node _T_2217 = or(_T_2211, _T_2216) node _T_2218 = and(_T_2206, _T_2217) node _T_2219 = or(UInt<1>(0h0), _T_2218) node _T_2220 = and(UInt<1>(0h0), _T_2219) node _T_2221 = asUInt(reset) node _T_2222 = eq(_T_2221, UInt<1>(0h0)) when _T_2222 : node _T_2223 = eq(_T_2220, UInt<1>(0h0)) when _T_2223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2220, UInt<1>(0h1), "") : assert_106 node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : node _T_2226 = eq(address_ok, UInt<1>(0h0)) when _T_2226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(legal_source, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_2230 = asUInt(reset) node _T_2231 = eq(_T_2230, UInt<1>(0h0)) when _T_2231 : node _T_2232 = eq(is_aligned_1, UInt<1>(0h0)) when _T_2232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_2233 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_2234 = asUInt(reset) node _T_2235 = eq(_T_2234, UInt<1>(0h0)) when _T_2235 : node _T_2236 = eq(_T_2233, UInt<1>(0h0)) when _T_2236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_2233, UInt<1>(0h1), "") : assert_110 node _T_2237 = not(mask_1) node _T_2238 = and(io.in.b.bits.mask, _T_2237) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) node _T_2240 = asUInt(reset) node _T_2241 = eq(_T_2240, UInt<1>(0h0)) when _T_2241 : node _T_2242 = eq(_T_2239, UInt<1>(0h0)) when _T_2242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2239, UInt<1>(0h1), "") : assert_111 node _T_2243 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_2243 : node _T_2244 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_2245 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_2246 = and(_T_2244, _T_2245) node _T_2247 = or(UInt<1>(0h0), _T_2246) node _T_2248 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_2249 = cvt(_T_2248) node _T_2250 = and(_T_2249, asSInt(UInt<17>(0h100c0))) node _T_2251 = asSInt(_T_2250) node _T_2252 = eq(_T_2251, asSInt(UInt<1>(0h0))) node _T_2253 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_2254 = cvt(_T_2253) node _T_2255 = and(_T_2254, asSInt(UInt<29>(0h100000c0))) node _T_2256 = asSInt(_T_2255) node _T_2257 = eq(_T_2256, asSInt(UInt<1>(0h0))) node _T_2258 = or(_T_2252, _T_2257) node _T_2259 = and(_T_2247, _T_2258) node _T_2260 = or(UInt<1>(0h0), _T_2259) node _T_2261 = and(UInt<1>(0h0), _T_2260) node _T_2262 = asUInt(reset) node _T_2263 = eq(_T_2262, UInt<1>(0h0)) when _T_2263 : node _T_2264 = eq(_T_2261, UInt<1>(0h0)) when _T_2264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_2261, UInt<1>(0h1), "") : assert_112 node _T_2265 = asUInt(reset) node _T_2266 = eq(_T_2265, UInt<1>(0h0)) when _T_2266 : node _T_2267 = eq(address_ok, UInt<1>(0h0)) when _T_2267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_2268 = asUInt(reset) node _T_2269 = eq(_T_2268, UInt<1>(0h0)) when _T_2269 : node _T_2270 = eq(legal_source, UInt<1>(0h0)) when _T_2270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_2271 = asUInt(reset) node _T_2272 = eq(_T_2271, UInt<1>(0h0)) when _T_2272 : node _T_2273 = eq(is_aligned_1, UInt<1>(0h0)) when _T_2273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_2274 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_2275 = asUInt(reset) node _T_2276 = eq(_T_2275, UInt<1>(0h0)) when _T_2276 : node _T_2277 = eq(_T_2274, UInt<1>(0h0)) when _T_2277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_2274, UInt<1>(0h1), "") : assert_116 node _T_2278 = eq(io.in.b.bits.mask, mask_1) node _T_2279 = asUInt(reset) node _T_2280 = eq(_T_2279, UInt<1>(0h0)) when _T_2280 : node _T_2281 = eq(_T_2278, UInt<1>(0h0)) when _T_2281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_2278, UInt<1>(0h1), "") : assert_117 node _T_2282 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_2282 : node _T_2283 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_2284 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_2285 = and(_T_2283, _T_2284) node _T_2286 = or(UInt<1>(0h0), _T_2285) node _T_2287 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_2288 = cvt(_T_2287) node _T_2289 = and(_T_2288, asSInt(UInt<17>(0h100c0))) node _T_2290 = asSInt(_T_2289) node _T_2291 = eq(_T_2290, asSInt(UInt<1>(0h0))) node _T_2292 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_2293 = cvt(_T_2292) node _T_2294 = and(_T_2293, asSInt(UInt<29>(0h100000c0))) node _T_2295 = asSInt(_T_2294) node _T_2296 = eq(_T_2295, asSInt(UInt<1>(0h0))) node _T_2297 = or(_T_2291, _T_2296) node _T_2298 = and(_T_2286, _T_2297) node _T_2299 = or(UInt<1>(0h0), _T_2298) node _T_2300 = and(UInt<1>(0h0), _T_2299) node _T_2301 = asUInt(reset) node _T_2302 = eq(_T_2301, UInt<1>(0h0)) when _T_2302 : node _T_2303 = eq(_T_2300, UInt<1>(0h0)) when _T_2303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_2300, UInt<1>(0h1), "") : assert_118 node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : node _T_2306 = eq(address_ok, UInt<1>(0h0)) when _T_2306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_2307 = asUInt(reset) node _T_2308 = eq(_T_2307, UInt<1>(0h0)) when _T_2308 : node _T_2309 = eq(legal_source, UInt<1>(0h0)) when _T_2309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_2310 = asUInt(reset) node _T_2311 = eq(_T_2310, UInt<1>(0h0)) when _T_2311 : node _T_2312 = eq(is_aligned_1, UInt<1>(0h0)) when _T_2312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_2313 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_2314 = asUInt(reset) node _T_2315 = eq(_T_2314, UInt<1>(0h0)) when _T_2315 : node _T_2316 = eq(_T_2313, UInt<1>(0h0)) when _T_2316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_2313, UInt<1>(0h1), "") : assert_122 node _T_2317 = eq(io.in.b.bits.mask, mask_1) node _T_2318 = asUInt(reset) node _T_2319 = eq(_T_2318, UInt<1>(0h0)) when _T_2319 : node _T_2320 = eq(_T_2317, UInt<1>(0h0)) when _T_2320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_2317, UInt<1>(0h1), "") : assert_123 node _T_2321 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_2321 : node _T_2322 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_2323 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_2324 = and(_T_2322, _T_2323) node _T_2325 = or(UInt<1>(0h0), _T_2324) node _T_2326 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _T_2327 = cvt(_T_2326) node _T_2328 = and(_T_2327, asSInt(UInt<17>(0h100c0))) node _T_2329 = asSInt(_T_2328) node _T_2330 = eq(_T_2329, asSInt(UInt<1>(0h0))) node _T_2331 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _T_2332 = cvt(_T_2331) node _T_2333 = and(_T_2332, asSInt(UInt<29>(0h100000c0))) node _T_2334 = asSInt(_T_2333) node _T_2335 = eq(_T_2334, asSInt(UInt<1>(0h0))) node _T_2336 = or(_T_2330, _T_2335) node _T_2337 = and(_T_2325, _T_2336) node _T_2338 = or(UInt<1>(0h0), _T_2337) node _T_2339 = and(UInt<1>(0h0), _T_2338) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_124 node _T_2343 = asUInt(reset) node _T_2344 = eq(_T_2343, UInt<1>(0h0)) when _T_2344 : node _T_2345 = eq(address_ok, UInt<1>(0h0)) when _T_2345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_2346 = asUInt(reset) node _T_2347 = eq(_T_2346, UInt<1>(0h0)) when _T_2347 : node _T_2348 = eq(legal_source, UInt<1>(0h0)) when _T_2348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_2349 = asUInt(reset) node _T_2350 = eq(_T_2349, UInt<1>(0h0)) when _T_2350 : node _T_2351 = eq(is_aligned_1, UInt<1>(0h0)) when _T_2351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_2352 = eq(io.in.b.bits.mask, mask_1) node _T_2353 = asUInt(reset) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) when _T_2354 : node _T_2355 = eq(_T_2352, UInt<1>(0h0)) when _T_2355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_2352, UInt<1>(0h1), "") : assert_128 node _T_2356 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_2357 = asUInt(reset) node _T_2358 = eq(_T_2357, UInt<1>(0h0)) when _T_2358 : node _T_2359 = eq(_T_2356, UInt<1>(0h0)) when _T_2359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_2356, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_2360 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_2361 = asUInt(reset) node _T_2362 = eq(_T_2361, UInt<1>(0h0)) when _T_2362 : node _T_2363 = eq(_T_2360, UInt<1>(0h0)) when _T_2363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_2360, UInt<1>(0h1), "") : assert_130 node _source_ok_T_152 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_153 = shr(io.in.c.bits.source, 2) node _source_ok_T_154 = eq(_source_ok_T_153, UInt<1>(0h0)) node _source_ok_T_155 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_156 = and(_source_ok_T_154, _source_ok_T_155) node _source_ok_T_157 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_158 = and(_source_ok_T_156, _source_ok_T_157) node _source_ok_uncommonBits_T_9 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_159 = shr(io.in.c.bits.source, 2) node _source_ok_T_160 = eq(_source_ok_T_159, UInt<1>(0h1)) node _source_ok_T_161 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_162 = and(_source_ok_T_160, _source_ok_T_161) node _source_ok_T_163 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_164 = and(_source_ok_T_162, _source_ok_T_163) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_165 = shr(io.in.c.bits.source, 2) node _source_ok_T_166 = eq(_source_ok_T_165, UInt<2>(0h2)) node _source_ok_T_167 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_168 = and(_source_ok_T_166, _source_ok_T_167) node _source_ok_T_169 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_170 = and(_source_ok_T_168, _source_ok_T_169) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_171 = shr(io.in.c.bits.source, 2) node _source_ok_T_172 = eq(_source_ok_T_171, UInt<2>(0h3)) node _source_ok_T_173 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_174 = and(_source_ok_T_172, _source_ok_T_173) node _source_ok_T_175 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_176 = and(_source_ok_T_174, _source_ok_T_175) node _source_ok_T_177 = eq(io.in.c.bits.source, UInt<7>(0h4c)) node _source_ok_T_178 = eq(io.in.c.bits.source, UInt<7>(0h4e)) node _source_ok_T_179 = eq(io.in.c.bits.source, UInt<7>(0h48)) node _source_ok_T_180 = eq(io.in.c.bits.source, UInt<7>(0h4a)) node _source_ok_T_181 = eq(io.in.c.bits.source, UInt<7>(0h44)) node _source_ok_T_182 = eq(io.in.c.bits.source, UInt<7>(0h46)) node _source_ok_T_183 = eq(io.in.c.bits.source, UInt<7>(0h40)) node _source_ok_T_184 = eq(io.in.c.bits.source, UInt<7>(0h42)) node _source_ok_T_185 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _source_ok_T_186 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _source_ok_T_187 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _source_ok_T_188 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _source_ok_T_189 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _source_ok_T_190 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _source_ok_T_191 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _source_ok_T_192 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _source_ok_T_193 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _source_ok_T_194 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _source_ok_T_195 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_196 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _source_ok_T_197 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _source_ok_T_198 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _source_ok_T_199 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _source_ok_T_200 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_2 : UInt<1>[29] connect _source_ok_WIRE_2[0], _source_ok_T_152 connect _source_ok_WIRE_2[1], _source_ok_T_158 connect _source_ok_WIRE_2[2], _source_ok_T_164 connect _source_ok_WIRE_2[3], _source_ok_T_170 connect _source_ok_WIRE_2[4], _source_ok_T_176 connect _source_ok_WIRE_2[5], _source_ok_T_177 connect _source_ok_WIRE_2[6], _source_ok_T_178 connect _source_ok_WIRE_2[7], _source_ok_T_179 connect _source_ok_WIRE_2[8], _source_ok_T_180 connect _source_ok_WIRE_2[9], _source_ok_T_181 connect _source_ok_WIRE_2[10], _source_ok_T_182 connect _source_ok_WIRE_2[11], _source_ok_T_183 connect _source_ok_WIRE_2[12], _source_ok_T_184 connect _source_ok_WIRE_2[13], _source_ok_T_185 connect _source_ok_WIRE_2[14], _source_ok_T_186 connect _source_ok_WIRE_2[15], _source_ok_T_187 connect _source_ok_WIRE_2[16], _source_ok_T_188 connect _source_ok_WIRE_2[17], _source_ok_T_189 connect _source_ok_WIRE_2[18], _source_ok_T_190 connect _source_ok_WIRE_2[19], _source_ok_T_191 connect _source_ok_WIRE_2[20], _source_ok_T_192 connect _source_ok_WIRE_2[21], _source_ok_T_193 connect _source_ok_WIRE_2[22], _source_ok_T_194 connect _source_ok_WIRE_2[23], _source_ok_T_195 connect _source_ok_WIRE_2[24], _source_ok_T_196 connect _source_ok_WIRE_2[25], _source_ok_T_197 connect _source_ok_WIRE_2[26], _source_ok_T_198 connect _source_ok_WIRE_2[27], _source_ok_T_199 connect _source_ok_WIRE_2[28], _source_ok_T_200 node _source_ok_T_201 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_2[2]) node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_2[3]) node _source_ok_T_204 = or(_source_ok_T_203, _source_ok_WIRE_2[4]) node _source_ok_T_205 = or(_source_ok_T_204, _source_ok_WIRE_2[5]) node _source_ok_T_206 = or(_source_ok_T_205, _source_ok_WIRE_2[6]) node _source_ok_T_207 = or(_source_ok_T_206, _source_ok_WIRE_2[7]) node _source_ok_T_208 = or(_source_ok_T_207, _source_ok_WIRE_2[8]) node _source_ok_T_209 = or(_source_ok_T_208, _source_ok_WIRE_2[9]) node _source_ok_T_210 = or(_source_ok_T_209, _source_ok_WIRE_2[10]) node _source_ok_T_211 = or(_source_ok_T_210, _source_ok_WIRE_2[11]) node _source_ok_T_212 = or(_source_ok_T_211, _source_ok_WIRE_2[12]) node _source_ok_T_213 = or(_source_ok_T_212, _source_ok_WIRE_2[13]) node _source_ok_T_214 = or(_source_ok_T_213, _source_ok_WIRE_2[14]) node _source_ok_T_215 = or(_source_ok_T_214, _source_ok_WIRE_2[15]) node _source_ok_T_216 = or(_source_ok_T_215, _source_ok_WIRE_2[16]) node _source_ok_T_217 = or(_source_ok_T_216, _source_ok_WIRE_2[17]) node _source_ok_T_218 = or(_source_ok_T_217, _source_ok_WIRE_2[18]) node _source_ok_T_219 = or(_source_ok_T_218, _source_ok_WIRE_2[19]) node _source_ok_T_220 = or(_source_ok_T_219, _source_ok_WIRE_2[20]) node _source_ok_T_221 = or(_source_ok_T_220, _source_ok_WIRE_2[21]) node _source_ok_T_222 = or(_source_ok_T_221, _source_ok_WIRE_2[22]) node _source_ok_T_223 = or(_source_ok_T_222, _source_ok_WIRE_2[23]) node _source_ok_T_224 = or(_source_ok_T_223, _source_ok_WIRE_2[24]) node _source_ok_T_225 = or(_source_ok_T_224, _source_ok_WIRE_2[25]) node _source_ok_T_226 = or(_source_ok_T_225, _source_ok_WIRE_2[26]) node _source_ok_T_227 = or(_source_ok_T_226, _source_ok_WIRE_2[27]) node source_ok_2 = or(_source_ok_T_227, _source_ok_WIRE_2[28]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h100c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_2364 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_2365 = eq(_T_2364, UInt<1>(0h0)) node _T_2366 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2367 = cvt(_T_2366) node _T_2368 = and(_T_2367, asSInt(UInt<1>(0h0))) node _T_2369 = asSInt(_T_2368) node _T_2370 = eq(_T_2369, asSInt(UInt<1>(0h0))) node _T_2371 = or(_T_2365, _T_2370) node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_2372 = shr(io.in.c.bits.source, 2) node _T_2373 = eq(_T_2372, UInt<1>(0h0)) node _T_2374 = leq(UInt<1>(0h0), uncommonBits_52) node _T_2375 = and(_T_2373, _T_2374) node _T_2376 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_2377 = and(_T_2375, _T_2376) node _T_2378 = eq(_T_2377, UInt<1>(0h0)) node _T_2379 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2380 = cvt(_T_2379) node _T_2381 = and(_T_2380, asSInt(UInt<1>(0h0))) node _T_2382 = asSInt(_T_2381) node _T_2383 = eq(_T_2382, asSInt(UInt<1>(0h0))) node _T_2384 = or(_T_2378, _T_2383) node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_2385 = shr(io.in.c.bits.source, 2) node _T_2386 = eq(_T_2385, UInt<1>(0h1)) node _T_2387 = leq(UInt<1>(0h0), uncommonBits_53) node _T_2388 = and(_T_2386, _T_2387) node _T_2389 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_2390 = and(_T_2388, _T_2389) node _T_2391 = eq(_T_2390, UInt<1>(0h0)) node _T_2392 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2393 = cvt(_T_2392) node _T_2394 = and(_T_2393, asSInt(UInt<1>(0h0))) node _T_2395 = asSInt(_T_2394) node _T_2396 = eq(_T_2395, asSInt(UInt<1>(0h0))) node _T_2397 = or(_T_2391, _T_2396) node _uncommonBits_T_54 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_2398 = shr(io.in.c.bits.source, 2) node _T_2399 = eq(_T_2398, UInt<2>(0h2)) node _T_2400 = leq(UInt<1>(0h0), uncommonBits_54) node _T_2401 = and(_T_2399, _T_2400) node _T_2402 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_2403 = and(_T_2401, _T_2402) node _T_2404 = eq(_T_2403, UInt<1>(0h0)) node _T_2405 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2406 = cvt(_T_2405) node _T_2407 = and(_T_2406, asSInt(UInt<1>(0h0))) node _T_2408 = asSInt(_T_2407) node _T_2409 = eq(_T_2408, asSInt(UInt<1>(0h0))) node _T_2410 = or(_T_2404, _T_2409) node _uncommonBits_T_55 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_2411 = shr(io.in.c.bits.source, 2) node _T_2412 = eq(_T_2411, UInt<2>(0h3)) node _T_2413 = leq(UInt<1>(0h0), uncommonBits_55) node _T_2414 = and(_T_2412, _T_2413) node _T_2415 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_2416 = and(_T_2414, _T_2415) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) node _T_2418 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2419 = cvt(_T_2418) node _T_2420 = and(_T_2419, asSInt(UInt<1>(0h0))) node _T_2421 = asSInt(_T_2420) node _T_2422 = eq(_T_2421, asSInt(UInt<1>(0h0))) node _T_2423 = or(_T_2417, _T_2422) node _T_2424 = eq(io.in.c.bits.source, UInt<7>(0h4c)) node _T_2425 = eq(_T_2424, UInt<1>(0h0)) node _T_2426 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2427 = cvt(_T_2426) node _T_2428 = and(_T_2427, asSInt(UInt<1>(0h0))) node _T_2429 = asSInt(_T_2428) node _T_2430 = eq(_T_2429, asSInt(UInt<1>(0h0))) node _T_2431 = or(_T_2425, _T_2430) node _T_2432 = eq(io.in.c.bits.source, UInt<7>(0h4e)) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) node _T_2434 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2435 = cvt(_T_2434) node _T_2436 = and(_T_2435, asSInt(UInt<1>(0h0))) node _T_2437 = asSInt(_T_2436) node _T_2438 = eq(_T_2437, asSInt(UInt<1>(0h0))) node _T_2439 = or(_T_2433, _T_2438) node _T_2440 = eq(io.in.c.bits.source, UInt<7>(0h48)) node _T_2441 = eq(_T_2440, UInt<1>(0h0)) node _T_2442 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2443 = cvt(_T_2442) node _T_2444 = and(_T_2443, asSInt(UInt<1>(0h0))) node _T_2445 = asSInt(_T_2444) node _T_2446 = eq(_T_2445, asSInt(UInt<1>(0h0))) node _T_2447 = or(_T_2441, _T_2446) node _T_2448 = eq(io.in.c.bits.source, UInt<7>(0h4a)) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) node _T_2450 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2451 = cvt(_T_2450) node _T_2452 = and(_T_2451, asSInt(UInt<1>(0h0))) node _T_2453 = asSInt(_T_2452) node _T_2454 = eq(_T_2453, asSInt(UInt<1>(0h0))) node _T_2455 = or(_T_2449, _T_2454) node _T_2456 = eq(io.in.c.bits.source, UInt<7>(0h44)) node _T_2457 = eq(_T_2456, UInt<1>(0h0)) node _T_2458 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2459 = cvt(_T_2458) node _T_2460 = and(_T_2459, asSInt(UInt<1>(0h0))) node _T_2461 = asSInt(_T_2460) node _T_2462 = eq(_T_2461, asSInt(UInt<1>(0h0))) node _T_2463 = or(_T_2457, _T_2462) node _T_2464 = eq(io.in.c.bits.source, UInt<7>(0h46)) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) node _T_2466 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2467 = cvt(_T_2466) node _T_2468 = and(_T_2467, asSInt(UInt<1>(0h0))) node _T_2469 = asSInt(_T_2468) node _T_2470 = eq(_T_2469, asSInt(UInt<1>(0h0))) node _T_2471 = or(_T_2465, _T_2470) node _T_2472 = eq(io.in.c.bits.source, UInt<7>(0h40)) node _T_2473 = eq(_T_2472, UInt<1>(0h0)) node _T_2474 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2475 = cvt(_T_2474) node _T_2476 = and(_T_2475, asSInt(UInt<1>(0h0))) node _T_2477 = asSInt(_T_2476) node _T_2478 = eq(_T_2477, asSInt(UInt<1>(0h0))) node _T_2479 = or(_T_2473, _T_2478) node _T_2480 = eq(io.in.c.bits.source, UInt<7>(0h42)) node _T_2481 = eq(_T_2480, UInt<1>(0h0)) node _T_2482 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2483 = cvt(_T_2482) node _T_2484 = and(_T_2483, asSInt(UInt<1>(0h0))) node _T_2485 = asSInt(_T_2484) node _T_2486 = eq(_T_2485, asSInt(UInt<1>(0h0))) node _T_2487 = or(_T_2481, _T_2486) node _T_2488 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2489 = eq(_T_2488, UInt<1>(0h0)) node _T_2490 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2491 = cvt(_T_2490) node _T_2492 = and(_T_2491, asSInt(UInt<1>(0h0))) node _T_2493 = asSInt(_T_2492) node _T_2494 = eq(_T_2493, asSInt(UInt<1>(0h0))) node _T_2495 = or(_T_2489, _T_2494) node _T_2496 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2497 = eq(_T_2496, UInt<1>(0h0)) node _T_2498 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2499 = cvt(_T_2498) node _T_2500 = and(_T_2499, asSInt(UInt<1>(0h0))) node _T_2501 = asSInt(_T_2500) node _T_2502 = eq(_T_2501, asSInt(UInt<1>(0h0))) node _T_2503 = or(_T_2497, _T_2502) node _T_2504 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2505 = eq(_T_2504, UInt<1>(0h0)) node _T_2506 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2507 = cvt(_T_2506) node _T_2508 = and(_T_2507, asSInt(UInt<1>(0h0))) node _T_2509 = asSInt(_T_2508) node _T_2510 = eq(_T_2509, asSInt(UInt<1>(0h0))) node _T_2511 = or(_T_2505, _T_2510) node _T_2512 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2513 = eq(_T_2512, UInt<1>(0h0)) node _T_2514 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2515 = cvt(_T_2514) node _T_2516 = and(_T_2515, asSInt(UInt<1>(0h0))) node _T_2517 = asSInt(_T_2516) node _T_2518 = eq(_T_2517, asSInt(UInt<1>(0h0))) node _T_2519 = or(_T_2513, _T_2518) node _T_2520 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2521 = eq(_T_2520, UInt<1>(0h0)) node _T_2522 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2523 = cvt(_T_2522) node _T_2524 = and(_T_2523, asSInt(UInt<1>(0h0))) node _T_2525 = asSInt(_T_2524) node _T_2526 = eq(_T_2525, asSInt(UInt<1>(0h0))) node _T_2527 = or(_T_2521, _T_2526) node _T_2528 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2529 = eq(_T_2528, UInt<1>(0h0)) node _T_2530 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2531 = cvt(_T_2530) node _T_2532 = and(_T_2531, asSInt(UInt<1>(0h0))) node _T_2533 = asSInt(_T_2532) node _T_2534 = eq(_T_2533, asSInt(UInt<1>(0h0))) node _T_2535 = or(_T_2529, _T_2534) node _T_2536 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2537 = eq(_T_2536, UInt<1>(0h0)) node _T_2538 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2539 = cvt(_T_2538) node _T_2540 = and(_T_2539, asSInt(UInt<1>(0h0))) node _T_2541 = asSInt(_T_2540) node _T_2542 = eq(_T_2541, asSInt(UInt<1>(0h0))) node _T_2543 = or(_T_2537, _T_2542) node _T_2544 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2545 = eq(_T_2544, UInt<1>(0h0)) node _T_2546 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2547 = cvt(_T_2546) node _T_2548 = and(_T_2547, asSInt(UInt<1>(0h0))) node _T_2549 = asSInt(_T_2548) node _T_2550 = eq(_T_2549, asSInt(UInt<1>(0h0))) node _T_2551 = or(_T_2545, _T_2550) node _T_2552 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2553 = eq(_T_2552, UInt<1>(0h0)) node _T_2554 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2555 = cvt(_T_2554) node _T_2556 = and(_T_2555, asSInt(UInt<1>(0h0))) node _T_2557 = asSInt(_T_2556) node _T_2558 = eq(_T_2557, asSInt(UInt<1>(0h0))) node _T_2559 = or(_T_2553, _T_2558) node _T_2560 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2561 = eq(_T_2560, UInt<1>(0h0)) node _T_2562 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2563 = cvt(_T_2562) node _T_2564 = and(_T_2563, asSInt(UInt<1>(0h0))) node _T_2565 = asSInt(_T_2564) node _T_2566 = eq(_T_2565, asSInt(UInt<1>(0h0))) node _T_2567 = or(_T_2561, _T_2566) node _T_2568 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2569 = eq(_T_2568, UInt<1>(0h0)) node _T_2570 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2571 = cvt(_T_2570) node _T_2572 = and(_T_2571, asSInt(UInt<1>(0h0))) node _T_2573 = asSInt(_T_2572) node _T_2574 = eq(_T_2573, asSInt(UInt<1>(0h0))) node _T_2575 = or(_T_2569, _T_2574) node _T_2576 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2577 = eq(_T_2576, UInt<1>(0h0)) node _T_2578 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2579 = cvt(_T_2578) node _T_2580 = and(_T_2579, asSInt(UInt<1>(0h0))) node _T_2581 = asSInt(_T_2580) node _T_2582 = eq(_T_2581, asSInt(UInt<1>(0h0))) node _T_2583 = or(_T_2577, _T_2582) node _T_2584 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2585 = eq(_T_2584, UInt<1>(0h0)) node _T_2586 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2587 = cvt(_T_2586) node _T_2588 = and(_T_2587, asSInt(UInt<1>(0h0))) node _T_2589 = asSInt(_T_2588) node _T_2590 = eq(_T_2589, asSInt(UInt<1>(0h0))) node _T_2591 = or(_T_2585, _T_2590) node _T_2592 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2593 = eq(_T_2592, UInt<1>(0h0)) node _T_2594 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2595 = cvt(_T_2594) node _T_2596 = and(_T_2595, asSInt(UInt<1>(0h0))) node _T_2597 = asSInt(_T_2596) node _T_2598 = eq(_T_2597, asSInt(UInt<1>(0h0))) node _T_2599 = or(_T_2593, _T_2598) node _T_2600 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2601 = eq(_T_2600, UInt<1>(0h0)) node _T_2602 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2603 = cvt(_T_2602) node _T_2604 = and(_T_2603, asSInt(UInt<1>(0h0))) node _T_2605 = asSInt(_T_2604) node _T_2606 = eq(_T_2605, asSInt(UInt<1>(0h0))) node _T_2607 = or(_T_2601, _T_2606) node _T_2608 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2609 = eq(_T_2608, UInt<1>(0h0)) node _T_2610 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2611 = cvt(_T_2610) node _T_2612 = and(_T_2611, asSInt(UInt<1>(0h0))) node _T_2613 = asSInt(_T_2612) node _T_2614 = eq(_T_2613, asSInt(UInt<1>(0h0))) node _T_2615 = or(_T_2609, _T_2614) node _T_2616 = and(_T_2371, _T_2384) node _T_2617 = and(_T_2616, _T_2397) node _T_2618 = and(_T_2617, _T_2410) node _T_2619 = and(_T_2618, _T_2423) node _T_2620 = and(_T_2619, _T_2431) node _T_2621 = and(_T_2620, _T_2439) node _T_2622 = and(_T_2621, _T_2447) node _T_2623 = and(_T_2622, _T_2455) node _T_2624 = and(_T_2623, _T_2463) node _T_2625 = and(_T_2624, _T_2471) node _T_2626 = and(_T_2625, _T_2479) node _T_2627 = and(_T_2626, _T_2487) node _T_2628 = and(_T_2627, _T_2495) node _T_2629 = and(_T_2628, _T_2503) node _T_2630 = and(_T_2629, _T_2511) node _T_2631 = and(_T_2630, _T_2519) node _T_2632 = and(_T_2631, _T_2527) node _T_2633 = and(_T_2632, _T_2535) node _T_2634 = and(_T_2633, _T_2543) node _T_2635 = and(_T_2634, _T_2551) node _T_2636 = and(_T_2635, _T_2559) node _T_2637 = and(_T_2636, _T_2567) node _T_2638 = and(_T_2637, _T_2575) node _T_2639 = and(_T_2638, _T_2583) node _T_2640 = and(_T_2639, _T_2591) node _T_2641 = and(_T_2640, _T_2599) node _T_2642 = and(_T_2641, _T_2607) node _T_2643 = and(_T_2642, _T_2615) node _T_2644 = asUInt(reset) node _T_2645 = eq(_T_2644, UInt<1>(0h0)) when _T_2645 : node _T_2646 = eq(_T_2643, UInt<1>(0h0)) when _T_2646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_2643, UInt<1>(0h1), "") : assert_131 node _T_2647 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_2647 : node _T_2648 = asUInt(reset) node _T_2649 = eq(_T_2648, UInt<1>(0h0)) when _T_2649 : node _T_2650 = eq(address_ok_1, UInt<1>(0h0)) when _T_2650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_2651 = asUInt(reset) node _T_2652 = eq(_T_2651, UInt<1>(0h0)) when _T_2652 : node _T_2653 = eq(source_ok_2, UInt<1>(0h0)) when _T_2653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_2654 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2655 = asUInt(reset) node _T_2656 = eq(_T_2655, UInt<1>(0h0)) when _T_2656 : node _T_2657 = eq(_T_2654, UInt<1>(0h0)) when _T_2657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_2654, UInt<1>(0h1), "") : assert_134 node _T_2658 = asUInt(reset) node _T_2659 = eq(_T_2658, UInt<1>(0h0)) when _T_2659 : node _T_2660 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_2661 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2662 = asUInt(reset) node _T_2663 = eq(_T_2662, UInt<1>(0h0)) when _T_2663 : node _T_2664 = eq(_T_2661, UInt<1>(0h0)) when _T_2664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_2661, UInt<1>(0h1), "") : assert_136 node _T_2665 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2666 = asUInt(reset) node _T_2667 = eq(_T_2666, UInt<1>(0h0)) when _T_2667 : node _T_2668 = eq(_T_2665, UInt<1>(0h0)) when _T_2668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_2665, UInt<1>(0h1), "") : assert_137 node _T_2669 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_2669 : node _T_2670 = asUInt(reset) node _T_2671 = eq(_T_2670, UInt<1>(0h0)) when _T_2671 : node _T_2672 = eq(address_ok_1, UInt<1>(0h0)) when _T_2672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_2673 = asUInt(reset) node _T_2674 = eq(_T_2673, UInt<1>(0h0)) when _T_2674 : node _T_2675 = eq(source_ok_2, UInt<1>(0h0)) when _T_2675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_2676 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2677 = asUInt(reset) node _T_2678 = eq(_T_2677, UInt<1>(0h0)) when _T_2678 : node _T_2679 = eq(_T_2676, UInt<1>(0h0)) when _T_2679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_2676, UInt<1>(0h1), "") : assert_140 node _T_2680 = asUInt(reset) node _T_2681 = eq(_T_2680, UInt<1>(0h0)) when _T_2681 : node _T_2682 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_2683 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2684 = asUInt(reset) node _T_2685 = eq(_T_2684, UInt<1>(0h0)) when _T_2685 : node _T_2686 = eq(_T_2683, UInt<1>(0h0)) when _T_2686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_2683, UInt<1>(0h1), "") : assert_142 node _T_2687 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_2687 : node _T_2688 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2689 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2690 = and(_T_2688, _T_2689) node _T_2691 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_2692 = shr(io.in.c.bits.source, 2) node _T_2693 = eq(_T_2692, UInt<1>(0h0)) node _T_2694 = leq(UInt<1>(0h0), uncommonBits_56) node _T_2695 = and(_T_2693, _T_2694) node _T_2696 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_2697 = and(_T_2695, _T_2696) node _uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_2698 = shr(io.in.c.bits.source, 2) node _T_2699 = eq(_T_2698, UInt<1>(0h1)) node _T_2700 = leq(UInt<1>(0h0), uncommonBits_57) node _T_2701 = and(_T_2699, _T_2700) node _T_2702 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_2703 = and(_T_2701, _T_2702) node _uncommonBits_T_58 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_2704 = shr(io.in.c.bits.source, 2) node _T_2705 = eq(_T_2704, UInt<2>(0h2)) node _T_2706 = leq(UInt<1>(0h0), uncommonBits_58) node _T_2707 = and(_T_2705, _T_2706) node _T_2708 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_2709 = and(_T_2707, _T_2708) node _uncommonBits_T_59 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_2710 = shr(io.in.c.bits.source, 2) node _T_2711 = eq(_T_2710, UInt<2>(0h3)) node _T_2712 = leq(UInt<1>(0h0), uncommonBits_59) node _T_2713 = and(_T_2711, _T_2712) node _T_2714 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_2715 = and(_T_2713, _T_2714) node _T_2716 = eq(io.in.c.bits.source, UInt<7>(0h4c)) node _T_2717 = eq(io.in.c.bits.source, UInt<7>(0h4e)) node _T_2718 = eq(io.in.c.bits.source, UInt<7>(0h48)) node _T_2719 = eq(io.in.c.bits.source, UInt<7>(0h4a)) node _T_2720 = eq(io.in.c.bits.source, UInt<7>(0h44)) node _T_2721 = eq(io.in.c.bits.source, UInt<7>(0h46)) node _T_2722 = eq(io.in.c.bits.source, UInt<7>(0h40)) node _T_2723 = eq(io.in.c.bits.source, UInt<7>(0h42)) node _T_2724 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2725 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2726 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2727 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2728 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2729 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2730 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2731 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2732 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2733 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2734 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2735 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2736 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2737 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2738 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2739 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2740 = or(_T_2691, _T_2697) node _T_2741 = or(_T_2740, _T_2703) node _T_2742 = or(_T_2741, _T_2709) node _T_2743 = or(_T_2742, _T_2715) node _T_2744 = or(_T_2743, _T_2716) node _T_2745 = or(_T_2744, _T_2717) node _T_2746 = or(_T_2745, _T_2718) node _T_2747 = or(_T_2746, _T_2719) node _T_2748 = or(_T_2747, _T_2720) node _T_2749 = or(_T_2748, _T_2721) node _T_2750 = or(_T_2749, _T_2722) node _T_2751 = or(_T_2750, _T_2723) node _T_2752 = or(_T_2751, _T_2724) node _T_2753 = or(_T_2752, _T_2725) node _T_2754 = or(_T_2753, _T_2726) node _T_2755 = or(_T_2754, _T_2727) node _T_2756 = or(_T_2755, _T_2728) node _T_2757 = or(_T_2756, _T_2729) node _T_2758 = or(_T_2757, _T_2730) node _T_2759 = or(_T_2758, _T_2731) node _T_2760 = or(_T_2759, _T_2732) node _T_2761 = or(_T_2760, _T_2733) node _T_2762 = or(_T_2761, _T_2734) node _T_2763 = or(_T_2762, _T_2735) node _T_2764 = or(_T_2763, _T_2736) node _T_2765 = or(_T_2764, _T_2737) node _T_2766 = or(_T_2765, _T_2738) node _T_2767 = or(_T_2766, _T_2739) node _T_2768 = and(_T_2690, _T_2767) node _T_2769 = or(UInt<1>(0h0), _T_2768) node _T_2770 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2771 = or(UInt<1>(0h0), _T_2770) node _T_2772 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_2773 = cvt(_T_2772) node _T_2774 = and(_T_2773, asSInt(UInt<17>(0h100c0))) node _T_2775 = asSInt(_T_2774) node _T_2776 = eq(_T_2775, asSInt(UInt<1>(0h0))) node _T_2777 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_2778 = cvt(_T_2777) node _T_2779 = and(_T_2778, asSInt(UInt<29>(0h100000c0))) node _T_2780 = asSInt(_T_2779) node _T_2781 = eq(_T_2780, asSInt(UInt<1>(0h0))) node _T_2782 = or(_T_2776, _T_2781) node _T_2783 = and(_T_2771, _T_2782) node _T_2784 = or(UInt<1>(0h0), _T_2783) node _T_2785 = and(_T_2769, _T_2784) node _T_2786 = asUInt(reset) node _T_2787 = eq(_T_2786, UInt<1>(0h0)) when _T_2787 : node _T_2788 = eq(_T_2785, UInt<1>(0h0)) when _T_2788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2785, UInt<1>(0h1), "") : assert_143 node _T_2789 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_2790 = shr(io.in.c.bits.source, 2) node _T_2791 = eq(_T_2790, UInt<1>(0h0)) node _T_2792 = leq(UInt<1>(0h0), uncommonBits_60) node _T_2793 = and(_T_2791, _T_2792) node _T_2794 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_2795 = and(_T_2793, _T_2794) node _uncommonBits_T_61 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_2796 = shr(io.in.c.bits.source, 2) node _T_2797 = eq(_T_2796, UInt<1>(0h1)) node _T_2798 = leq(UInt<1>(0h0), uncommonBits_61) node _T_2799 = and(_T_2797, _T_2798) node _T_2800 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_2801 = and(_T_2799, _T_2800) node _uncommonBits_T_62 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_2802 = shr(io.in.c.bits.source, 2) node _T_2803 = eq(_T_2802, UInt<2>(0h2)) node _T_2804 = leq(UInt<1>(0h0), uncommonBits_62) node _T_2805 = and(_T_2803, _T_2804) node _T_2806 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_2807 = and(_T_2805, _T_2806) node _uncommonBits_T_63 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_2808 = shr(io.in.c.bits.source, 2) node _T_2809 = eq(_T_2808, UInt<2>(0h3)) node _T_2810 = leq(UInt<1>(0h0), uncommonBits_63) node _T_2811 = and(_T_2809, _T_2810) node _T_2812 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_2813 = and(_T_2811, _T_2812) node _T_2814 = eq(io.in.c.bits.source, UInt<7>(0h4c)) node _T_2815 = eq(io.in.c.bits.source, UInt<7>(0h4e)) node _T_2816 = eq(io.in.c.bits.source, UInt<7>(0h48)) node _T_2817 = eq(io.in.c.bits.source, UInt<7>(0h4a)) node _T_2818 = eq(io.in.c.bits.source, UInt<7>(0h44)) node _T_2819 = eq(io.in.c.bits.source, UInt<7>(0h46)) node _T_2820 = eq(io.in.c.bits.source, UInt<7>(0h40)) node _T_2821 = eq(io.in.c.bits.source, UInt<7>(0h42)) node _T_2822 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2823 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2824 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2825 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2826 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2827 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2828 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2829 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2830 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2831 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2832 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2833 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2834 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2835 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2836 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2837 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_6 : UInt<1>[29] connect _WIRE_6[0], _T_2789 connect _WIRE_6[1], _T_2795 connect _WIRE_6[2], _T_2801 connect _WIRE_6[3], _T_2807 connect _WIRE_6[4], _T_2813 connect _WIRE_6[5], _T_2814 connect _WIRE_6[6], _T_2815 connect _WIRE_6[7], _T_2816 connect _WIRE_6[8], _T_2817 connect _WIRE_6[9], _T_2818 connect _WIRE_6[10], _T_2819 connect _WIRE_6[11], _T_2820 connect _WIRE_6[12], _T_2821 connect _WIRE_6[13], _T_2822 connect _WIRE_6[14], _T_2823 connect _WIRE_6[15], _T_2824 connect _WIRE_6[16], _T_2825 connect _WIRE_6[17], _T_2826 connect _WIRE_6[18], _T_2827 connect _WIRE_6[19], _T_2828 connect _WIRE_6[20], _T_2829 connect _WIRE_6[21], _T_2830 connect _WIRE_6[22], _T_2831 connect _WIRE_6[23], _T_2832 connect _WIRE_6[24], _T_2833 connect _WIRE_6[25], _T_2834 connect _WIRE_6[26], _T_2835 connect _WIRE_6[27], _T_2836 connect _WIRE_6[28], _T_2837 node _T_2838 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2839 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2840 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2841 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2842 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2843 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2844 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2845 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2846 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2847 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2848 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2849 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2850 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2851 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2852 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2853 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2854 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2855 = mux(_WIRE_6[5], _T_2838, UInt<1>(0h0)) node _T_2856 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_2857 = mux(_WIRE_6[7], _T_2839, UInt<1>(0h0)) node _T_2858 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_2859 = mux(_WIRE_6[9], _T_2840, UInt<1>(0h0)) node _T_2860 = mux(_WIRE_6[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_2861 = mux(_WIRE_6[11], _T_2841, UInt<1>(0h0)) node _T_2862 = mux(_WIRE_6[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_2863 = mux(_WIRE_6[13], _T_2842, UInt<1>(0h0)) node _T_2864 = mux(_WIRE_6[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_2865 = mux(_WIRE_6[15], _T_2843, UInt<1>(0h0)) node _T_2866 = mux(_WIRE_6[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_2867 = mux(_WIRE_6[17], _T_2844, UInt<1>(0h0)) node _T_2868 = mux(_WIRE_6[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_2869 = mux(_WIRE_6[19], _T_2845, UInt<1>(0h0)) node _T_2870 = mux(_WIRE_6[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_2871 = mux(_WIRE_6[21], _T_2846, UInt<1>(0h0)) node _T_2872 = mux(_WIRE_6[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_2873 = mux(_WIRE_6[23], _T_2847, UInt<1>(0h0)) node _T_2874 = mux(_WIRE_6[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_2875 = mux(_WIRE_6[25], _T_2848, UInt<1>(0h0)) node _T_2876 = mux(_WIRE_6[26], UInt<1>(0h0), UInt<1>(0h0)) node _T_2877 = mux(_WIRE_6[27], _T_2849, UInt<1>(0h0)) node _T_2878 = mux(_WIRE_6[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_2879 = or(_T_2850, _T_2851) node _T_2880 = or(_T_2879, _T_2852) node _T_2881 = or(_T_2880, _T_2853) node _T_2882 = or(_T_2881, _T_2854) node _T_2883 = or(_T_2882, _T_2855) node _T_2884 = or(_T_2883, _T_2856) node _T_2885 = or(_T_2884, _T_2857) node _T_2886 = or(_T_2885, _T_2858) node _T_2887 = or(_T_2886, _T_2859) node _T_2888 = or(_T_2887, _T_2860) node _T_2889 = or(_T_2888, _T_2861) node _T_2890 = or(_T_2889, _T_2862) node _T_2891 = or(_T_2890, _T_2863) node _T_2892 = or(_T_2891, _T_2864) node _T_2893 = or(_T_2892, _T_2865) node _T_2894 = or(_T_2893, _T_2866) node _T_2895 = or(_T_2894, _T_2867) node _T_2896 = or(_T_2895, _T_2868) node _T_2897 = or(_T_2896, _T_2869) node _T_2898 = or(_T_2897, _T_2870) node _T_2899 = or(_T_2898, _T_2871) node _T_2900 = or(_T_2899, _T_2872) node _T_2901 = or(_T_2900, _T_2873) node _T_2902 = or(_T_2901, _T_2874) node _T_2903 = or(_T_2902, _T_2875) node _T_2904 = or(_T_2903, _T_2876) node _T_2905 = or(_T_2904, _T_2877) node _T_2906 = or(_T_2905, _T_2878) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2906 node _T_2907 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2908 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2909 = and(_T_2907, _T_2908) node _T_2910 = or(UInt<1>(0h0), _T_2909) node _T_2911 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_2912 = cvt(_T_2911) node _T_2913 = and(_T_2912, asSInt(UInt<17>(0h100c0))) node _T_2914 = asSInt(_T_2913) node _T_2915 = eq(_T_2914, asSInt(UInt<1>(0h0))) node _T_2916 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_2917 = cvt(_T_2916) node _T_2918 = and(_T_2917, asSInt(UInt<29>(0h100000c0))) node _T_2919 = asSInt(_T_2918) node _T_2920 = eq(_T_2919, asSInt(UInt<1>(0h0))) node _T_2921 = or(_T_2915, _T_2920) node _T_2922 = and(_T_2910, _T_2921) node _T_2923 = or(UInt<1>(0h0), _T_2922) node _T_2924 = and(_WIRE_7, _T_2923) node _T_2925 = asUInt(reset) node _T_2926 = eq(_T_2925, UInt<1>(0h0)) when _T_2926 : node _T_2927 = eq(_T_2924, UInt<1>(0h0)) when _T_2927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2924, UInt<1>(0h1), "") : assert_144 node _T_2928 = asUInt(reset) node _T_2929 = eq(_T_2928, UInt<1>(0h0)) when _T_2929 : node _T_2930 = eq(source_ok_2, UInt<1>(0h0)) when _T_2930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2931 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2932 = asUInt(reset) node _T_2933 = eq(_T_2932, UInt<1>(0h0)) when _T_2933 : node _T_2934 = eq(_T_2931, UInt<1>(0h0)) when _T_2934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2931, UInt<1>(0h1), "") : assert_146 node _T_2935 = asUInt(reset) node _T_2936 = eq(_T_2935, UInt<1>(0h0)) when _T_2936 : node _T_2937 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2938 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2939 = asUInt(reset) node _T_2940 = eq(_T_2939, UInt<1>(0h0)) when _T_2940 : node _T_2941 = eq(_T_2938, UInt<1>(0h0)) when _T_2941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2938, UInt<1>(0h1), "") : assert_148 node _T_2942 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2943 = asUInt(reset) node _T_2944 = eq(_T_2943, UInt<1>(0h0)) when _T_2944 : node _T_2945 = eq(_T_2942, UInt<1>(0h0)) when _T_2945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2942, UInt<1>(0h1), "") : assert_149 node _T_2946 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2946 : node _T_2947 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2948 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2949 = and(_T_2947, _T_2948) node _T_2950 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_64 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_2951 = shr(io.in.c.bits.source, 2) node _T_2952 = eq(_T_2951, UInt<1>(0h0)) node _T_2953 = leq(UInt<1>(0h0), uncommonBits_64) node _T_2954 = and(_T_2952, _T_2953) node _T_2955 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_2956 = and(_T_2954, _T_2955) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_2957 = shr(io.in.c.bits.source, 2) node _T_2958 = eq(_T_2957, UInt<1>(0h1)) node _T_2959 = leq(UInt<1>(0h0), uncommonBits_65) node _T_2960 = and(_T_2958, _T_2959) node _T_2961 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_2962 = and(_T_2960, _T_2961) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_2963 = shr(io.in.c.bits.source, 2) node _T_2964 = eq(_T_2963, UInt<2>(0h2)) node _T_2965 = leq(UInt<1>(0h0), uncommonBits_66) node _T_2966 = and(_T_2964, _T_2965) node _T_2967 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_2968 = and(_T_2966, _T_2967) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_2969 = shr(io.in.c.bits.source, 2) node _T_2970 = eq(_T_2969, UInt<2>(0h3)) node _T_2971 = leq(UInt<1>(0h0), uncommonBits_67) node _T_2972 = and(_T_2970, _T_2971) node _T_2973 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_2974 = and(_T_2972, _T_2973) node _T_2975 = eq(io.in.c.bits.source, UInt<7>(0h4c)) node _T_2976 = eq(io.in.c.bits.source, UInt<7>(0h4e)) node _T_2977 = eq(io.in.c.bits.source, UInt<7>(0h48)) node _T_2978 = eq(io.in.c.bits.source, UInt<7>(0h4a)) node _T_2979 = eq(io.in.c.bits.source, UInt<7>(0h44)) node _T_2980 = eq(io.in.c.bits.source, UInt<7>(0h46)) node _T_2981 = eq(io.in.c.bits.source, UInt<7>(0h40)) node _T_2982 = eq(io.in.c.bits.source, UInt<7>(0h42)) node _T_2983 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2984 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2985 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2986 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2987 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2988 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2989 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2990 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2991 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2992 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2993 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2994 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2995 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2996 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2997 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2998 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2999 = or(_T_2950, _T_2956) node _T_3000 = or(_T_2999, _T_2962) node _T_3001 = or(_T_3000, _T_2968) node _T_3002 = or(_T_3001, _T_2974) node _T_3003 = or(_T_3002, _T_2975) node _T_3004 = or(_T_3003, _T_2976) node _T_3005 = or(_T_3004, _T_2977) node _T_3006 = or(_T_3005, _T_2978) node _T_3007 = or(_T_3006, _T_2979) node _T_3008 = or(_T_3007, _T_2980) node _T_3009 = or(_T_3008, _T_2981) node _T_3010 = or(_T_3009, _T_2982) node _T_3011 = or(_T_3010, _T_2983) node _T_3012 = or(_T_3011, _T_2984) node _T_3013 = or(_T_3012, _T_2985) node _T_3014 = or(_T_3013, _T_2986) node _T_3015 = or(_T_3014, _T_2987) node _T_3016 = or(_T_3015, _T_2988) node _T_3017 = or(_T_3016, _T_2989) node _T_3018 = or(_T_3017, _T_2990) node _T_3019 = or(_T_3018, _T_2991) node _T_3020 = or(_T_3019, _T_2992) node _T_3021 = or(_T_3020, _T_2993) node _T_3022 = or(_T_3021, _T_2994) node _T_3023 = or(_T_3022, _T_2995) node _T_3024 = or(_T_3023, _T_2996) node _T_3025 = or(_T_3024, _T_2997) node _T_3026 = or(_T_3025, _T_2998) node _T_3027 = and(_T_2949, _T_3026) node _T_3028 = or(UInt<1>(0h0), _T_3027) node _T_3029 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3030 = or(UInt<1>(0h0), _T_3029) node _T_3031 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_3032 = cvt(_T_3031) node _T_3033 = and(_T_3032, asSInt(UInt<17>(0h100c0))) node _T_3034 = asSInt(_T_3033) node _T_3035 = eq(_T_3034, asSInt(UInt<1>(0h0))) node _T_3036 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_3037 = cvt(_T_3036) node _T_3038 = and(_T_3037, asSInt(UInt<29>(0h100000c0))) node _T_3039 = asSInt(_T_3038) node _T_3040 = eq(_T_3039, asSInt(UInt<1>(0h0))) node _T_3041 = or(_T_3035, _T_3040) node _T_3042 = and(_T_3030, _T_3041) node _T_3043 = or(UInt<1>(0h0), _T_3042) node _T_3044 = and(_T_3028, _T_3043) node _T_3045 = asUInt(reset) node _T_3046 = eq(_T_3045, UInt<1>(0h0)) when _T_3046 : node _T_3047 = eq(_T_3044, UInt<1>(0h0)) when _T_3047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_3044, UInt<1>(0h1), "") : assert_150 node _T_3048 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_3049 = shr(io.in.c.bits.source, 2) node _T_3050 = eq(_T_3049, UInt<1>(0h0)) node _T_3051 = leq(UInt<1>(0h0), uncommonBits_68) node _T_3052 = and(_T_3050, _T_3051) node _T_3053 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_3054 = and(_T_3052, _T_3053) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_3055 = shr(io.in.c.bits.source, 2) node _T_3056 = eq(_T_3055, UInt<1>(0h1)) node _T_3057 = leq(UInt<1>(0h0), uncommonBits_69) node _T_3058 = and(_T_3056, _T_3057) node _T_3059 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_3060 = and(_T_3058, _T_3059) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_3061 = shr(io.in.c.bits.source, 2) node _T_3062 = eq(_T_3061, UInt<2>(0h2)) node _T_3063 = leq(UInt<1>(0h0), uncommonBits_70) node _T_3064 = and(_T_3062, _T_3063) node _T_3065 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_3066 = and(_T_3064, _T_3065) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_3067 = shr(io.in.c.bits.source, 2) node _T_3068 = eq(_T_3067, UInt<2>(0h3)) node _T_3069 = leq(UInt<1>(0h0), uncommonBits_71) node _T_3070 = and(_T_3068, _T_3069) node _T_3071 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_3072 = and(_T_3070, _T_3071) node _T_3073 = eq(io.in.c.bits.source, UInt<7>(0h4c)) node _T_3074 = eq(io.in.c.bits.source, UInt<7>(0h4e)) node _T_3075 = eq(io.in.c.bits.source, UInt<7>(0h48)) node _T_3076 = eq(io.in.c.bits.source, UInt<7>(0h4a)) node _T_3077 = eq(io.in.c.bits.source, UInt<7>(0h44)) node _T_3078 = eq(io.in.c.bits.source, UInt<7>(0h46)) node _T_3079 = eq(io.in.c.bits.source, UInt<7>(0h40)) node _T_3080 = eq(io.in.c.bits.source, UInt<7>(0h42)) node _T_3081 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_3082 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_3083 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_3084 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_3085 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_3086 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_3087 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_3088 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_3089 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_3090 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_3091 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_3092 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_3093 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_3094 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_3095 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_3096 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_8 : UInt<1>[29] connect _WIRE_8[0], _T_3048 connect _WIRE_8[1], _T_3054 connect _WIRE_8[2], _T_3060 connect _WIRE_8[3], _T_3066 connect _WIRE_8[4], _T_3072 connect _WIRE_8[5], _T_3073 connect _WIRE_8[6], _T_3074 connect _WIRE_8[7], _T_3075 connect _WIRE_8[8], _T_3076 connect _WIRE_8[9], _T_3077 connect _WIRE_8[10], _T_3078 connect _WIRE_8[11], _T_3079 connect _WIRE_8[12], _T_3080 connect _WIRE_8[13], _T_3081 connect _WIRE_8[14], _T_3082 connect _WIRE_8[15], _T_3083 connect _WIRE_8[16], _T_3084 connect _WIRE_8[17], _T_3085 connect _WIRE_8[18], _T_3086 connect _WIRE_8[19], _T_3087 connect _WIRE_8[20], _T_3088 connect _WIRE_8[21], _T_3089 connect _WIRE_8[22], _T_3090 connect _WIRE_8[23], _T_3091 connect _WIRE_8[24], _T_3092 connect _WIRE_8[25], _T_3093 connect _WIRE_8[26], _T_3094 connect _WIRE_8[27], _T_3095 connect _WIRE_8[28], _T_3096 node _T_3097 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3098 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3099 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3100 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3101 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3102 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3103 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3104 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3105 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3106 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3107 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3108 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3109 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_3110 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_3111 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_3112 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_3113 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_3114 = mux(_WIRE_8[5], _T_3097, UInt<1>(0h0)) node _T_3115 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_3116 = mux(_WIRE_8[7], _T_3098, UInt<1>(0h0)) node _T_3117 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_3118 = mux(_WIRE_8[9], _T_3099, UInt<1>(0h0)) node _T_3119 = mux(_WIRE_8[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_3120 = mux(_WIRE_8[11], _T_3100, UInt<1>(0h0)) node _T_3121 = mux(_WIRE_8[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_3122 = mux(_WIRE_8[13], _T_3101, UInt<1>(0h0)) node _T_3123 = mux(_WIRE_8[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_3124 = mux(_WIRE_8[15], _T_3102, UInt<1>(0h0)) node _T_3125 = mux(_WIRE_8[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_3126 = mux(_WIRE_8[17], _T_3103, UInt<1>(0h0)) node _T_3127 = mux(_WIRE_8[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_3128 = mux(_WIRE_8[19], _T_3104, UInt<1>(0h0)) node _T_3129 = mux(_WIRE_8[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_3130 = mux(_WIRE_8[21], _T_3105, UInt<1>(0h0)) node _T_3131 = mux(_WIRE_8[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_3132 = mux(_WIRE_8[23], _T_3106, UInt<1>(0h0)) node _T_3133 = mux(_WIRE_8[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_3134 = mux(_WIRE_8[25], _T_3107, UInt<1>(0h0)) node _T_3135 = mux(_WIRE_8[26], UInt<1>(0h0), UInt<1>(0h0)) node _T_3136 = mux(_WIRE_8[27], _T_3108, UInt<1>(0h0)) node _T_3137 = mux(_WIRE_8[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_3138 = or(_T_3109, _T_3110) node _T_3139 = or(_T_3138, _T_3111) node _T_3140 = or(_T_3139, _T_3112) node _T_3141 = or(_T_3140, _T_3113) node _T_3142 = or(_T_3141, _T_3114) node _T_3143 = or(_T_3142, _T_3115) node _T_3144 = or(_T_3143, _T_3116) node _T_3145 = or(_T_3144, _T_3117) node _T_3146 = or(_T_3145, _T_3118) node _T_3147 = or(_T_3146, _T_3119) node _T_3148 = or(_T_3147, _T_3120) node _T_3149 = or(_T_3148, _T_3121) node _T_3150 = or(_T_3149, _T_3122) node _T_3151 = or(_T_3150, _T_3123) node _T_3152 = or(_T_3151, _T_3124) node _T_3153 = or(_T_3152, _T_3125) node _T_3154 = or(_T_3153, _T_3126) node _T_3155 = or(_T_3154, _T_3127) node _T_3156 = or(_T_3155, _T_3128) node _T_3157 = or(_T_3156, _T_3129) node _T_3158 = or(_T_3157, _T_3130) node _T_3159 = or(_T_3158, _T_3131) node _T_3160 = or(_T_3159, _T_3132) node _T_3161 = or(_T_3160, _T_3133) node _T_3162 = or(_T_3161, _T_3134) node _T_3163 = or(_T_3162, _T_3135) node _T_3164 = or(_T_3163, _T_3136) node _T_3165 = or(_T_3164, _T_3137) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_3165 node _T_3166 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_3167 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_3168 = and(_T_3166, _T_3167) node _T_3169 = or(UInt<1>(0h0), _T_3168) node _T_3170 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _T_3171 = cvt(_T_3170) node _T_3172 = and(_T_3171, asSInt(UInt<17>(0h100c0))) node _T_3173 = asSInt(_T_3172) node _T_3174 = eq(_T_3173, asSInt(UInt<1>(0h0))) node _T_3175 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _T_3176 = cvt(_T_3175) node _T_3177 = and(_T_3176, asSInt(UInt<29>(0h100000c0))) node _T_3178 = asSInt(_T_3177) node _T_3179 = eq(_T_3178, asSInt(UInt<1>(0h0))) node _T_3180 = or(_T_3174, _T_3179) node _T_3181 = and(_T_3169, _T_3180) node _T_3182 = or(UInt<1>(0h0), _T_3181) node _T_3183 = and(_WIRE_9, _T_3182) node _T_3184 = asUInt(reset) node _T_3185 = eq(_T_3184, UInt<1>(0h0)) when _T_3185 : node _T_3186 = eq(_T_3183, UInt<1>(0h0)) when _T_3186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_3183, UInt<1>(0h1), "") : assert_151 node _T_3187 = asUInt(reset) node _T_3188 = eq(_T_3187, UInt<1>(0h0)) when _T_3188 : node _T_3189 = eq(source_ok_2, UInt<1>(0h0)) when _T_3189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_3190 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_3191 = asUInt(reset) node _T_3192 = eq(_T_3191, UInt<1>(0h0)) when _T_3192 : node _T_3193 = eq(_T_3190, UInt<1>(0h0)) when _T_3193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_3190, UInt<1>(0h1), "") : assert_153 node _T_3194 = asUInt(reset) node _T_3195 = eq(_T_3194, UInt<1>(0h0)) when _T_3195 : node _T_3196 = eq(is_aligned_2, UInt<1>(0h0)) when _T_3196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_3197 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_3198 = asUInt(reset) node _T_3199 = eq(_T_3198, UInt<1>(0h0)) when _T_3199 : node _T_3200 = eq(_T_3197, UInt<1>(0h0)) when _T_3200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_3197, UInt<1>(0h1), "") : assert_155 node _T_3201 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_3201 : node _T_3202 = asUInt(reset) node _T_3203 = eq(_T_3202, UInt<1>(0h0)) when _T_3203 : node _T_3204 = eq(address_ok_1, UInt<1>(0h0)) when _T_3204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_3205 = asUInt(reset) node _T_3206 = eq(_T_3205, UInt<1>(0h0)) when _T_3206 : node _T_3207 = eq(source_ok_2, UInt<1>(0h0)) when _T_3207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_3208 = asUInt(reset) node _T_3209 = eq(_T_3208, UInt<1>(0h0)) when _T_3209 : node _T_3210 = eq(is_aligned_2, UInt<1>(0h0)) when _T_3210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_3211 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_3212 = asUInt(reset) node _T_3213 = eq(_T_3212, UInt<1>(0h0)) when _T_3213 : node _T_3214 = eq(_T_3211, UInt<1>(0h0)) when _T_3214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_3211, UInt<1>(0h1), "") : assert_159 node _T_3215 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_3216 = asUInt(reset) node _T_3217 = eq(_T_3216, UInt<1>(0h0)) when _T_3217 : node _T_3218 = eq(_T_3215, UInt<1>(0h0)) when _T_3218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_3215, UInt<1>(0h1), "") : assert_160 node _T_3219 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_3219 : node _T_3220 = asUInt(reset) node _T_3221 = eq(_T_3220, UInt<1>(0h0)) when _T_3221 : node _T_3222 = eq(address_ok_1, UInt<1>(0h0)) when _T_3222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_3223 = asUInt(reset) node _T_3224 = eq(_T_3223, UInt<1>(0h0)) when _T_3224 : node _T_3225 = eq(source_ok_2, UInt<1>(0h0)) when _T_3225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_3226 = asUInt(reset) node _T_3227 = eq(_T_3226, UInt<1>(0h0)) when _T_3227 : node _T_3228 = eq(is_aligned_2, UInt<1>(0h0)) when _T_3228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_3229 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_3230 = asUInt(reset) node _T_3231 = eq(_T_3230, UInt<1>(0h0)) when _T_3231 : node _T_3232 = eq(_T_3229, UInt<1>(0h0)) when _T_3232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_3229, UInt<1>(0h1), "") : assert_164 node _T_3233 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_3233 : node _T_3234 = asUInt(reset) node _T_3235 = eq(_T_3234, UInt<1>(0h0)) when _T_3235 : node _T_3236 = eq(address_ok_1, UInt<1>(0h0)) when _T_3236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_3237 = asUInt(reset) node _T_3238 = eq(_T_3237, UInt<1>(0h0)) when _T_3238 : node _T_3239 = eq(source_ok_2, UInt<1>(0h0)) when _T_3239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_3240 = asUInt(reset) node _T_3241 = eq(_T_3240, UInt<1>(0h0)) when _T_3241 : node _T_3242 = eq(is_aligned_2, UInt<1>(0h0)) when _T_3242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_3243 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_3244 = asUInt(reset) node _T_3245 = eq(_T_3244, UInt<1>(0h0)) when _T_3245 : node _T_3246 = eq(_T_3243, UInt<1>(0h0)) when _T_3246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_3243, UInt<1>(0h1), "") : assert_168 node _T_3247 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_3248 = asUInt(reset) node _T_3249 = eq(_T_3248, UInt<1>(0h0)) when _T_3249 : node _T_3250 = eq(_T_3247, UInt<1>(0h0)) when _T_3250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_3247, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0hc)) node _T_3251 = asUInt(reset) node _T_3252 = eq(_T_3251, UInt<1>(0h0)) when _T_3252 : node _T_3253 = eq(sink_ok_1, UInt<1>(0h0)) when _T_3253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_3254 = eq(a_first, UInt<1>(0h0)) node _T_3255 = and(io.in.a.valid, _T_3254) when _T_3255 : node _T_3256 = eq(io.in.a.bits.opcode, opcode) node _T_3257 = asUInt(reset) node _T_3258 = eq(_T_3257, UInt<1>(0h0)) when _T_3258 : node _T_3259 = eq(_T_3256, UInt<1>(0h0)) when _T_3259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_3256, UInt<1>(0h1), "") : assert_171 node _T_3260 = eq(io.in.a.bits.param, param) node _T_3261 = asUInt(reset) node _T_3262 = eq(_T_3261, UInt<1>(0h0)) when _T_3262 : node _T_3263 = eq(_T_3260, UInt<1>(0h0)) when _T_3263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_3260, UInt<1>(0h1), "") : assert_172 node _T_3264 = eq(io.in.a.bits.size, size) node _T_3265 = asUInt(reset) node _T_3266 = eq(_T_3265, UInt<1>(0h0)) when _T_3266 : node _T_3267 = eq(_T_3264, UInt<1>(0h0)) when _T_3267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_3264, UInt<1>(0h1), "") : assert_173 node _T_3268 = eq(io.in.a.bits.source, source) node _T_3269 = asUInt(reset) node _T_3270 = eq(_T_3269, UInt<1>(0h0)) when _T_3270 : node _T_3271 = eq(_T_3268, UInt<1>(0h0)) when _T_3271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_3268, UInt<1>(0h1), "") : assert_174 node _T_3272 = eq(io.in.a.bits.address, address) node _T_3273 = asUInt(reset) node _T_3274 = eq(_T_3273, UInt<1>(0h0)) when _T_3274 : node _T_3275 = eq(_T_3272, UInt<1>(0h0)) when _T_3275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_3272, UInt<1>(0h1), "") : assert_175 node _T_3276 = and(io.in.a.ready, io.in.a.valid) node _T_3277 = and(_T_3276, a_first) when _T_3277 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_3278 = eq(d_first, UInt<1>(0h0)) node _T_3279 = and(io.in.d.valid, _T_3278) when _T_3279 : node _T_3280 = eq(io.in.d.bits.opcode, opcode_1) node _T_3281 = asUInt(reset) node _T_3282 = eq(_T_3281, UInt<1>(0h0)) when _T_3282 : node _T_3283 = eq(_T_3280, UInt<1>(0h0)) when _T_3283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_3280, UInt<1>(0h1), "") : assert_176 node _T_3284 = eq(io.in.d.bits.param, param_1) node _T_3285 = asUInt(reset) node _T_3286 = eq(_T_3285, UInt<1>(0h0)) when _T_3286 : node _T_3287 = eq(_T_3284, UInt<1>(0h0)) when _T_3287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_3284, UInt<1>(0h1), "") : assert_177 node _T_3288 = eq(io.in.d.bits.size, size_1) node _T_3289 = asUInt(reset) node _T_3290 = eq(_T_3289, UInt<1>(0h0)) when _T_3290 : node _T_3291 = eq(_T_3288, UInt<1>(0h0)) when _T_3291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_3288, UInt<1>(0h1), "") : assert_178 node _T_3292 = eq(io.in.d.bits.source, source_1) node _T_3293 = asUInt(reset) node _T_3294 = eq(_T_3293, UInt<1>(0h0)) when _T_3294 : node _T_3295 = eq(_T_3292, UInt<1>(0h0)) when _T_3295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_3292, UInt<1>(0h1), "") : assert_179 node _T_3296 = eq(io.in.d.bits.sink, sink) node _T_3297 = asUInt(reset) node _T_3298 = eq(_T_3297, UInt<1>(0h0)) when _T_3298 : node _T_3299 = eq(_T_3296, UInt<1>(0h0)) when _T_3299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_3296, UInt<1>(0h1), "") : assert_180 node _T_3300 = eq(io.in.d.bits.denied, denied) node _T_3301 = asUInt(reset) node _T_3302 = eq(_T_3301, UInt<1>(0h0)) when _T_3302 : node _T_3303 = eq(_T_3300, UInt<1>(0h0)) when _T_3303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_3300, UInt<1>(0h1), "") : assert_181 node _T_3304 = and(io.in.d.ready, io.in.d.valid) node _T_3305 = and(_T_3304, d_first) when _T_3305 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_3306 = eq(b_first, UInt<1>(0h0)) node _T_3307 = and(io.in.b.valid, _T_3306) when _T_3307 : node _T_3308 = eq(io.in.b.bits.opcode, opcode_2) node _T_3309 = asUInt(reset) node _T_3310 = eq(_T_3309, UInt<1>(0h0)) when _T_3310 : node _T_3311 = eq(_T_3308, UInt<1>(0h0)) when _T_3311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_3308, UInt<1>(0h1), "") : assert_182 node _T_3312 = eq(io.in.b.bits.param, param_2) node _T_3313 = asUInt(reset) node _T_3314 = eq(_T_3313, UInt<1>(0h0)) when _T_3314 : node _T_3315 = eq(_T_3312, UInt<1>(0h0)) when _T_3315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_3312, UInt<1>(0h1), "") : assert_183 node _T_3316 = eq(io.in.b.bits.size, size_2) node _T_3317 = asUInt(reset) node _T_3318 = eq(_T_3317, UInt<1>(0h0)) when _T_3318 : node _T_3319 = eq(_T_3316, UInt<1>(0h0)) when _T_3319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_3316, UInt<1>(0h1), "") : assert_184 node _T_3320 = eq(io.in.b.bits.source, source_2) node _T_3321 = asUInt(reset) node _T_3322 = eq(_T_3321, UInt<1>(0h0)) when _T_3322 : node _T_3323 = eq(_T_3320, UInt<1>(0h0)) when _T_3323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_3320, UInt<1>(0h1), "") : assert_185 node _T_3324 = eq(io.in.b.bits.address, address_1) node _T_3325 = asUInt(reset) node _T_3326 = eq(_T_3325, UInt<1>(0h0)) when _T_3326 : node _T_3327 = eq(_T_3324, UInt<1>(0h0)) when _T_3327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_3324, UInt<1>(0h1), "") : assert_186 node _T_3328 = and(io.in.b.ready, io.in.b.valid) node _T_3329 = and(_T_3328, b_first) when _T_3329 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_3330 = eq(c_first, UInt<1>(0h0)) node _T_3331 = and(io.in.c.valid, _T_3330) when _T_3331 : node _T_3332 = eq(io.in.c.bits.opcode, opcode_3) node _T_3333 = asUInt(reset) node _T_3334 = eq(_T_3333, UInt<1>(0h0)) when _T_3334 : node _T_3335 = eq(_T_3332, UInt<1>(0h0)) when _T_3335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_3332, UInt<1>(0h1), "") : assert_187 node _T_3336 = eq(io.in.c.bits.param, param_3) node _T_3337 = asUInt(reset) node _T_3338 = eq(_T_3337, UInt<1>(0h0)) when _T_3338 : node _T_3339 = eq(_T_3336, UInt<1>(0h0)) when _T_3339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_3336, UInt<1>(0h1), "") : assert_188 node _T_3340 = eq(io.in.c.bits.size, size_3) node _T_3341 = asUInt(reset) node _T_3342 = eq(_T_3341, UInt<1>(0h0)) when _T_3342 : node _T_3343 = eq(_T_3340, UInt<1>(0h0)) when _T_3343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_3340, UInt<1>(0h1), "") : assert_189 node _T_3344 = eq(io.in.c.bits.source, source_3) node _T_3345 = asUInt(reset) node _T_3346 = eq(_T_3345, UInt<1>(0h0)) when _T_3346 : node _T_3347 = eq(_T_3344, UInt<1>(0h0)) when _T_3347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_3344, UInt<1>(0h1), "") : assert_190 node _T_3348 = eq(io.in.c.bits.address, address_2) node _T_3349 = asUInt(reset) node _T_3350 = eq(_T_3349, UInt<1>(0h0)) when _T_3350 : node _T_3351 = eq(_T_3348, UInt<1>(0h0)) when _T_3351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_3348, UInt<1>(0h1), "") : assert_191 node _T_3352 = and(io.in.c.ready, io.in.c.valid) node _T_3353 = and(_T_3352, c_first) when _T_3353 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<79>, clock, reset, UInt<79>(0h0) regreset inflight_opcodes : UInt<316>, clock, reset, UInt<316>(0h0) regreset inflight_sizes : UInt<316>, clock, reset, UInt<316>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<79> connect a_set, UInt<79>(0h0) wire a_set_wo_ready : UInt<79> connect a_set_wo_ready, UInt<79>(0h0) wire a_opcodes_set : UInt<316> connect a_opcodes_set, UInt<316>(0h0) wire a_sizes_set : UInt<316> connect a_sizes_set, UInt<316>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_3354 = and(io.in.a.valid, a_first_1) node _T_3355 = and(_T_3354, UInt<1>(0h1)) when _T_3355 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_3356 = and(io.in.a.ready, io.in.a.valid) node _T_3357 = and(_T_3356, a_first_1) node _T_3358 = and(_T_3357, UInt<1>(0h1)) when _T_3358 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_3359 = dshr(inflight, io.in.a.bits.source) node _T_3360 = bits(_T_3359, 0, 0) node _T_3361 = eq(_T_3360, UInt<1>(0h0)) node _T_3362 = asUInt(reset) node _T_3363 = eq(_T_3362, UInt<1>(0h0)) when _T_3363 : node _T_3364 = eq(_T_3361, UInt<1>(0h0)) when _T_3364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_3361, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<79> connect d_clr, UInt<79>(0h0) wire d_clr_wo_ready : UInt<79> connect d_clr_wo_ready, UInt<79>(0h0) wire d_opcodes_clr : UInt<316> connect d_opcodes_clr, UInt<316>(0h0) wire d_sizes_clr : UInt<316> connect d_sizes_clr, UInt<316>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_3365 = and(io.in.d.valid, d_first_1) node _T_3366 = and(_T_3365, UInt<1>(0h1)) node _T_3367 = eq(d_release_ack, UInt<1>(0h0)) node _T_3368 = and(_T_3366, _T_3367) when _T_3368 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_3369 = and(io.in.d.ready, io.in.d.valid) node _T_3370 = and(_T_3369, d_first_1) node _T_3371 = and(_T_3370, UInt<1>(0h1)) node _T_3372 = eq(d_release_ack, UInt<1>(0h0)) node _T_3373 = and(_T_3371, _T_3372) when _T_3373 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_3374 = and(io.in.d.valid, d_first_1) node _T_3375 = and(_T_3374, UInt<1>(0h1)) node _T_3376 = eq(d_release_ack, UInt<1>(0h0)) node _T_3377 = and(_T_3375, _T_3376) when _T_3377 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_3378 = dshr(inflight, io.in.d.bits.source) node _T_3379 = bits(_T_3378, 0, 0) node _T_3380 = or(_T_3379, same_cycle_resp) node _T_3381 = asUInt(reset) node _T_3382 = eq(_T_3381, UInt<1>(0h0)) when _T_3382 : node _T_3383 = eq(_T_3380, UInt<1>(0h0)) when _T_3383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_3380, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_3384 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_3385 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_3386 = or(_T_3384, _T_3385) node _T_3387 = asUInt(reset) node _T_3388 = eq(_T_3387, UInt<1>(0h0)) when _T_3388 : node _T_3389 = eq(_T_3386, UInt<1>(0h0)) when _T_3389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_3386, UInt<1>(0h1), "") : assert_194 node _T_3390 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_3391 = asUInt(reset) node _T_3392 = eq(_T_3391, UInt<1>(0h0)) when _T_3392 : node _T_3393 = eq(_T_3390, UInt<1>(0h0)) when _T_3393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_3390, UInt<1>(0h1), "") : assert_195 else : node _T_3394 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_3395 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_3396 = or(_T_3394, _T_3395) node _T_3397 = asUInt(reset) node _T_3398 = eq(_T_3397, UInt<1>(0h0)) when _T_3398 : node _T_3399 = eq(_T_3396, UInt<1>(0h0)) when _T_3399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_3396, UInt<1>(0h1), "") : assert_196 node _T_3400 = eq(io.in.d.bits.size, a_size_lookup) node _T_3401 = asUInt(reset) node _T_3402 = eq(_T_3401, UInt<1>(0h0)) when _T_3402 : node _T_3403 = eq(_T_3400, UInt<1>(0h0)) when _T_3403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_3400, UInt<1>(0h1), "") : assert_197 node _T_3404 = and(io.in.d.valid, d_first_1) node _T_3405 = and(_T_3404, a_first_1) node _T_3406 = and(_T_3405, io.in.a.valid) node _T_3407 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_3408 = and(_T_3406, _T_3407) node _T_3409 = eq(d_release_ack, UInt<1>(0h0)) node _T_3410 = and(_T_3408, _T_3409) when _T_3410 : node _T_3411 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_3412 = or(_T_3411, io.in.a.ready) node _T_3413 = asUInt(reset) node _T_3414 = eq(_T_3413, UInt<1>(0h0)) when _T_3414 : node _T_3415 = eq(_T_3412, UInt<1>(0h0)) when _T_3415 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_3412, UInt<1>(0h1), "") : assert_198 node _T_3416 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_3417 = orr(a_set_wo_ready) node _T_3418 = eq(_T_3417, UInt<1>(0h0)) node _T_3419 = or(_T_3416, _T_3418) node _T_3420 = asUInt(reset) node _T_3421 = eq(_T_3420, UInt<1>(0h0)) when _T_3421 : node _T_3422 = eq(_T_3419, UInt<1>(0h0)) when _T_3422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_3419, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_146 node _T_3423 = orr(inflight) node _T_3424 = eq(_T_3423, UInt<1>(0h0)) node _T_3425 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_3426 = or(_T_3424, _T_3425) node _T_3427 = lt(watchdog, plusarg_reader.out) node _T_3428 = or(_T_3426, _T_3427) node _T_3429 = asUInt(reset) node _T_3430 = eq(_T_3429, UInt<1>(0h0)) when _T_3430 : node _T_3431 = eq(_T_3428, UInt<1>(0h0)) when _T_3431 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_3428, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_3432 = and(io.in.a.ready, io.in.a.valid) node _T_3433 = and(io.in.d.ready, io.in.d.valid) node _T_3434 = or(_T_3432, _T_3433) when _T_3434 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<79>, clock, reset, UInt<79>(0h0) regreset inflight_opcodes_1 : UInt<316>, clock, reset, UInt<316>(0h0) regreset inflight_sizes_1 : UInt<316>, clock, reset, UInt<316>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<79> connect c_set, UInt<79>(0h0) wire c_set_wo_ready : UInt<79> connect c_set_wo_ready, UInt<79>(0h0) wire c_opcodes_set : UInt<316> connect c_opcodes_set, UInt<316>(0h0) wire c_sizes_set : UInt<316> connect c_sizes_set, UInt<316>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_3435 = and(io.in.c.valid, c_first_1) node _T_3436 = bits(io.in.c.bits.opcode, 2, 2) node _T_3437 = bits(io.in.c.bits.opcode, 1, 1) node _T_3438 = and(_T_3436, _T_3437) node _T_3439 = and(_T_3435, _T_3438) when _T_3439 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_3440 = and(io.in.c.ready, io.in.c.valid) node _T_3441 = and(_T_3440, c_first_1) node _T_3442 = bits(io.in.c.bits.opcode, 2, 2) node _T_3443 = bits(io.in.c.bits.opcode, 1, 1) node _T_3444 = and(_T_3442, _T_3443) node _T_3445 = and(_T_3441, _T_3444) when _T_3445 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_3446 = dshr(inflight_1, io.in.c.bits.source) node _T_3447 = bits(_T_3446, 0, 0) node _T_3448 = eq(_T_3447, UInt<1>(0h0)) node _T_3449 = asUInt(reset) node _T_3450 = eq(_T_3449, UInt<1>(0h0)) when _T_3450 : node _T_3451 = eq(_T_3448, UInt<1>(0h0)) when _T_3451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_3448, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<79> connect d_clr_1, UInt<79>(0h0) wire d_clr_wo_ready_1 : UInt<79> connect d_clr_wo_ready_1, UInt<79>(0h0) wire d_opcodes_clr_1 : UInt<316> connect d_opcodes_clr_1, UInt<316>(0h0) wire d_sizes_clr_1 : UInt<316> connect d_sizes_clr_1, UInt<316>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_3452 = and(io.in.d.valid, d_first_2) node _T_3453 = and(_T_3452, UInt<1>(0h1)) node _T_3454 = and(_T_3453, d_release_ack_1) when _T_3454 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_3455 = and(io.in.d.ready, io.in.d.valid) node _T_3456 = and(_T_3455, d_first_2) node _T_3457 = and(_T_3456, UInt<1>(0h1)) node _T_3458 = and(_T_3457, d_release_ack_1) when _T_3458 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_3459 = and(io.in.d.valid, d_first_2) node _T_3460 = and(_T_3459, UInt<1>(0h1)) node _T_3461 = and(_T_3460, d_release_ack_1) when _T_3461 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_3462 = dshr(inflight_1, io.in.d.bits.source) node _T_3463 = bits(_T_3462, 0, 0) node _T_3464 = or(_T_3463, same_cycle_resp_1) node _T_3465 = asUInt(reset) node _T_3466 = eq(_T_3465, UInt<1>(0h0)) when _T_3466 : node _T_3467 = eq(_T_3464, UInt<1>(0h0)) when _T_3467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_3464, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_3468 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_3469 = asUInt(reset) node _T_3470 = eq(_T_3469, UInt<1>(0h0)) when _T_3470 : node _T_3471 = eq(_T_3468, UInt<1>(0h0)) when _T_3471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_3468, UInt<1>(0h1), "") : assert_203 else : node _T_3472 = eq(io.in.d.bits.size, c_size_lookup) node _T_3473 = asUInt(reset) node _T_3474 = eq(_T_3473, UInt<1>(0h0)) when _T_3474 : node _T_3475 = eq(_T_3472, UInt<1>(0h0)) when _T_3475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_3472, UInt<1>(0h1), "") : assert_204 node _T_3476 = and(io.in.d.valid, d_first_2) node _T_3477 = and(_T_3476, c_first_1) node _T_3478 = and(_T_3477, io.in.c.valid) node _T_3479 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_3480 = and(_T_3478, _T_3479) node _T_3481 = and(_T_3480, d_release_ack_1) node _T_3482 = eq(c_probe_ack, UInt<1>(0h0)) node _T_3483 = and(_T_3481, _T_3482) when _T_3483 : node _T_3484 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_3485 = or(_T_3484, io.in.c.ready) node _T_3486 = asUInt(reset) node _T_3487 = eq(_T_3486, UInt<1>(0h0)) when _T_3487 : node _T_3488 = eq(_T_3485, UInt<1>(0h0)) when _T_3488 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_3485, UInt<1>(0h1), "") : assert_205 node _T_3489 = orr(c_set_wo_ready) when _T_3489 : node _T_3490 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_3491 = asUInt(reset) node _T_3492 = eq(_T_3491, UInt<1>(0h0)) when _T_3492 : node _T_3493 = eq(_T_3490, UInt<1>(0h0)) when _T_3493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_3490, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_147 node _T_3494 = orr(inflight_1) node _T_3495 = eq(_T_3494, UInt<1>(0h0)) node _T_3496 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_3497 = or(_T_3495, _T_3496) node _T_3498 = lt(watchdog_1, plusarg_reader_1.out) node _T_3499 = or(_T_3497, _T_3498) node _T_3500 = asUInt(reset) node _T_3501 = eq(_T_3500, UInt<1>(0h0)) when _T_3501 : node _T_3502 = eq(_T_3499, UInt<1>(0h0)) when _T_3502 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_3499, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_3503 = and(io.in.c.ready, io.in.c.valid) node _T_3504 = and(io.in.d.ready, io.in.d.valid) node _T_3505 = or(_T_3503, _T_3504) when _T_3505 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<12>, clock, reset, UInt<12>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<12> connect d_set, UInt<12>(0h0) node _T_3506 = and(io.in.d.ready, io.in.d.valid) node _T_3507 = and(_T_3506, d_first_3) node _T_3508 = bits(io.in.d.bits.opcode, 2, 2) node _T_3509 = bits(io.in.d.bits.opcode, 1, 1) node _T_3510 = eq(_T_3509, UInt<1>(0h0)) node _T_3511 = and(_T_3508, _T_3510) node _T_3512 = and(_T_3507, _T_3511) when _T_3512 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_3513 = dshr(inflight_2, io.in.d.bits.sink) node _T_3514 = bits(_T_3513, 0, 0) node _T_3515 = eq(_T_3514, UInt<1>(0h0)) node _T_3516 = asUInt(reset) node _T_3517 = eq(_T_3516, UInt<1>(0h0)) when _T_3517 : node _T_3518 = eq(_T_3515, UInt<1>(0h0)) when _T_3518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_3515, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<12> connect e_clr, UInt<12>(0h0) node _T_3519 = and(io.in.e.ready, io.in.e.valid) node _T_3520 = and(_T_3519, UInt<1>(0h1)) node _T_3521 = and(_T_3520, UInt<1>(0h1)) when _T_3521 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_3522 = or(d_set, inflight_2) node _T_3523 = dshr(_T_3522, io.in.e.bits.sink) node _T_3524 = bits(_T_3523, 0, 0) node _T_3525 = asUInt(reset) node _T_3526 = eq(_T_3525, UInt<1>(0h0)) when _T_3526 : node _T_3527 = eq(_T_3524, UInt<1>(0h0)) when _T_3527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_3524, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8
module TLMonitor_57( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [6:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [1:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [1:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [6:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [1:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [6:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [78:0] inflight; // @[Monitor.scala:614:27] reg [315:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [315:0] inflight_sizes; // @[Monitor.scala:618:33] reg [1:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] reg [1:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_1 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_4 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [78:0] inflight_1; // @[Monitor.scala:726:35] reg [315:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [1:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] reg [1:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [127:0] _GEN_6 = {121'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [11:0] inflight_2; // @[Monitor.scala:828:27] reg [1:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [11:0] d_set = _GEN_8 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module Atomics : input clock : Clock input reset : Reset output io : { flip write : UInt<1>, flip a : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}, flip data_in : UInt<128>, data_out : UInt<128>} node adder = bits(io.a.param, 2, 2) node unsigned = bits(io.a.param, 1, 1) node take_max = bits(io.a.param, 0, 0) node _signBit_T = not(io.a.mask) node _signBit_T_1 = shr(_signBit_T, 1) node _signBit_T_2 = cat(UInt<1>(0h1), _signBit_T_1) node signBit = and(io.a.mask, _signBit_T_2) node _inv_d_T = not(io.data_in) node inv_d = mux(adder, io.data_in, _inv_d_T) node _sum_T = bits(io.a.mask, 0, 0) node _sum_T_1 = bits(io.a.mask, 1, 1) node _sum_T_2 = bits(io.a.mask, 2, 2) node _sum_T_3 = bits(io.a.mask, 3, 3) node _sum_T_4 = bits(io.a.mask, 4, 4) node _sum_T_5 = bits(io.a.mask, 5, 5) node _sum_T_6 = bits(io.a.mask, 6, 6) node _sum_T_7 = bits(io.a.mask, 7, 7) node _sum_T_8 = bits(io.a.mask, 8, 8) node _sum_T_9 = bits(io.a.mask, 9, 9) node _sum_T_10 = bits(io.a.mask, 10, 10) node _sum_T_11 = bits(io.a.mask, 11, 11) node _sum_T_12 = bits(io.a.mask, 12, 12) node _sum_T_13 = bits(io.a.mask, 13, 13) node _sum_T_14 = bits(io.a.mask, 14, 14) node _sum_T_15 = bits(io.a.mask, 15, 15) node _sum_T_16 = mux(_sum_T, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_17 = mux(_sum_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_18 = mux(_sum_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_19 = mux(_sum_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_20 = mux(_sum_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_21 = mux(_sum_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_22 = mux(_sum_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_23 = mux(_sum_T_7, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_24 = mux(_sum_T_8, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_25 = mux(_sum_T_9, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_26 = mux(_sum_T_10, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_27 = mux(_sum_T_11, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_28 = mux(_sum_T_12, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_29 = mux(_sum_T_13, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_30 = mux(_sum_T_14, UInt<8>(0hff), UInt<8>(0h0)) node _sum_T_31 = mux(_sum_T_15, UInt<8>(0hff), UInt<8>(0h0)) node sum_lo_lo_lo = cat(_sum_T_17, _sum_T_16) node sum_lo_lo_hi = cat(_sum_T_19, _sum_T_18) node sum_lo_lo = cat(sum_lo_lo_hi, sum_lo_lo_lo) node sum_lo_hi_lo = cat(_sum_T_21, _sum_T_20) node sum_lo_hi_hi = cat(_sum_T_23, _sum_T_22) node sum_lo_hi = cat(sum_lo_hi_hi, sum_lo_hi_lo) node sum_lo = cat(sum_lo_hi, sum_lo_lo) node sum_hi_lo_lo = cat(_sum_T_25, _sum_T_24) node sum_hi_lo_hi = cat(_sum_T_27, _sum_T_26) node sum_hi_lo = cat(sum_hi_lo_hi, sum_hi_lo_lo) node sum_hi_hi_lo = cat(_sum_T_29, _sum_T_28) node sum_hi_hi_hi = cat(_sum_T_31, _sum_T_30) node sum_hi_hi = cat(sum_hi_hi_hi, sum_hi_hi_lo) node sum_hi = cat(sum_hi_hi, sum_hi_lo) node _sum_T_32 = cat(sum_hi, sum_lo) node _sum_T_33 = and(_sum_T_32, io.a.data) node _sum_T_34 = add(_sum_T_33, inv_d) node sum = tail(_sum_T_34, 1) node _sign_a_T = bits(io.a.data, 0, 0) node _sign_a_T_1 = bits(io.a.data, 1, 1) node _sign_a_T_2 = bits(io.a.data, 2, 2) node _sign_a_T_3 = bits(io.a.data, 3, 3) node _sign_a_T_4 = bits(io.a.data, 4, 4) node _sign_a_T_5 = bits(io.a.data, 5, 5) node _sign_a_T_6 = bits(io.a.data, 6, 6) node _sign_a_T_7 = bits(io.a.data, 7, 7) node _sign_a_T_8 = bits(io.a.data, 8, 8) node _sign_a_T_9 = bits(io.a.data, 9, 9) node _sign_a_T_10 = bits(io.a.data, 10, 10) node _sign_a_T_11 = bits(io.a.data, 11, 11) node _sign_a_T_12 = bits(io.a.data, 12, 12) node _sign_a_T_13 = bits(io.a.data, 13, 13) node _sign_a_T_14 = bits(io.a.data, 14, 14) node _sign_a_T_15 = bits(io.a.data, 15, 15) node _sign_a_T_16 = bits(io.a.data, 16, 16) node _sign_a_T_17 = bits(io.a.data, 17, 17) node _sign_a_T_18 = bits(io.a.data, 18, 18) node _sign_a_T_19 = bits(io.a.data, 19, 19) node _sign_a_T_20 = bits(io.a.data, 20, 20) node _sign_a_T_21 = bits(io.a.data, 21, 21) node _sign_a_T_22 = bits(io.a.data, 22, 22) node _sign_a_T_23 = bits(io.a.data, 23, 23) node _sign_a_T_24 = bits(io.a.data, 24, 24) node _sign_a_T_25 = bits(io.a.data, 25, 25) node _sign_a_T_26 = bits(io.a.data, 26, 26) node _sign_a_T_27 = bits(io.a.data, 27, 27) node _sign_a_T_28 = bits(io.a.data, 28, 28) node _sign_a_T_29 = bits(io.a.data, 29, 29) node _sign_a_T_30 = bits(io.a.data, 30, 30) node _sign_a_T_31 = bits(io.a.data, 31, 31) node _sign_a_T_32 = bits(io.a.data, 32, 32) node _sign_a_T_33 = bits(io.a.data, 33, 33) node _sign_a_T_34 = bits(io.a.data, 34, 34) node _sign_a_T_35 = bits(io.a.data, 35, 35) node _sign_a_T_36 = bits(io.a.data, 36, 36) node _sign_a_T_37 = bits(io.a.data, 37, 37) node _sign_a_T_38 = bits(io.a.data, 38, 38) node _sign_a_T_39 = bits(io.a.data, 39, 39) node _sign_a_T_40 = bits(io.a.data, 40, 40) node _sign_a_T_41 = bits(io.a.data, 41, 41) node _sign_a_T_42 = bits(io.a.data, 42, 42) node _sign_a_T_43 = bits(io.a.data, 43, 43) node _sign_a_T_44 = bits(io.a.data, 44, 44) node _sign_a_T_45 = bits(io.a.data, 45, 45) node _sign_a_T_46 = bits(io.a.data, 46, 46) node _sign_a_T_47 = bits(io.a.data, 47, 47) node _sign_a_T_48 = bits(io.a.data, 48, 48) node _sign_a_T_49 = bits(io.a.data, 49, 49) node _sign_a_T_50 = bits(io.a.data, 50, 50) node _sign_a_T_51 = bits(io.a.data, 51, 51) node _sign_a_T_52 = bits(io.a.data, 52, 52) node _sign_a_T_53 = bits(io.a.data, 53, 53) node _sign_a_T_54 = bits(io.a.data, 54, 54) node _sign_a_T_55 = bits(io.a.data, 55, 55) node _sign_a_T_56 = bits(io.a.data, 56, 56) node _sign_a_T_57 = bits(io.a.data, 57, 57) node _sign_a_T_58 = bits(io.a.data, 58, 58) node _sign_a_T_59 = bits(io.a.data, 59, 59) node _sign_a_T_60 = bits(io.a.data, 60, 60) node _sign_a_T_61 = bits(io.a.data, 61, 61) node _sign_a_T_62 = bits(io.a.data, 62, 62) node _sign_a_T_63 = bits(io.a.data, 63, 63) node _sign_a_T_64 = bits(io.a.data, 64, 64) node _sign_a_T_65 = bits(io.a.data, 65, 65) node _sign_a_T_66 = bits(io.a.data, 66, 66) node _sign_a_T_67 = bits(io.a.data, 67, 67) node _sign_a_T_68 = bits(io.a.data, 68, 68) node _sign_a_T_69 = bits(io.a.data, 69, 69) node _sign_a_T_70 = bits(io.a.data, 70, 70) node _sign_a_T_71 = bits(io.a.data, 71, 71) node _sign_a_T_72 = bits(io.a.data, 72, 72) node _sign_a_T_73 = bits(io.a.data, 73, 73) node _sign_a_T_74 = bits(io.a.data, 74, 74) node _sign_a_T_75 = bits(io.a.data, 75, 75) node _sign_a_T_76 = bits(io.a.data, 76, 76) node _sign_a_T_77 = bits(io.a.data, 77, 77) node _sign_a_T_78 = bits(io.a.data, 78, 78) node _sign_a_T_79 = bits(io.a.data, 79, 79) node _sign_a_T_80 = bits(io.a.data, 80, 80) node _sign_a_T_81 = bits(io.a.data, 81, 81) node _sign_a_T_82 = bits(io.a.data, 82, 82) node _sign_a_T_83 = bits(io.a.data, 83, 83) node _sign_a_T_84 = bits(io.a.data, 84, 84) node _sign_a_T_85 = bits(io.a.data, 85, 85) node _sign_a_T_86 = bits(io.a.data, 86, 86) node _sign_a_T_87 = bits(io.a.data, 87, 87) node _sign_a_T_88 = bits(io.a.data, 88, 88) node _sign_a_T_89 = bits(io.a.data, 89, 89) node _sign_a_T_90 = bits(io.a.data, 90, 90) node _sign_a_T_91 = bits(io.a.data, 91, 91) node _sign_a_T_92 = bits(io.a.data, 92, 92) node _sign_a_T_93 = bits(io.a.data, 93, 93) node _sign_a_T_94 = bits(io.a.data, 94, 94) node _sign_a_T_95 = bits(io.a.data, 95, 95) node _sign_a_T_96 = bits(io.a.data, 96, 96) node _sign_a_T_97 = bits(io.a.data, 97, 97) node _sign_a_T_98 = bits(io.a.data, 98, 98) node _sign_a_T_99 = bits(io.a.data, 99, 99) node _sign_a_T_100 = bits(io.a.data, 100, 100) node _sign_a_T_101 = bits(io.a.data, 101, 101) node _sign_a_T_102 = bits(io.a.data, 102, 102) node _sign_a_T_103 = bits(io.a.data, 103, 103) node _sign_a_T_104 = bits(io.a.data, 104, 104) node _sign_a_T_105 = bits(io.a.data, 105, 105) node _sign_a_T_106 = bits(io.a.data, 106, 106) node _sign_a_T_107 = bits(io.a.data, 107, 107) node _sign_a_T_108 = bits(io.a.data, 108, 108) node _sign_a_T_109 = bits(io.a.data, 109, 109) node _sign_a_T_110 = bits(io.a.data, 110, 110) node _sign_a_T_111 = bits(io.a.data, 111, 111) node _sign_a_T_112 = bits(io.a.data, 112, 112) node _sign_a_T_113 = bits(io.a.data, 113, 113) node _sign_a_T_114 = bits(io.a.data, 114, 114) node _sign_a_T_115 = bits(io.a.data, 115, 115) node _sign_a_T_116 = bits(io.a.data, 116, 116) node _sign_a_T_117 = bits(io.a.data, 117, 117) node _sign_a_T_118 = bits(io.a.data, 118, 118) node _sign_a_T_119 = bits(io.a.data, 119, 119) node _sign_a_T_120 = bits(io.a.data, 120, 120) node _sign_a_T_121 = bits(io.a.data, 121, 121) node _sign_a_T_122 = bits(io.a.data, 122, 122) node _sign_a_T_123 = bits(io.a.data, 123, 123) node _sign_a_T_124 = bits(io.a.data, 124, 124) node _sign_a_T_125 = bits(io.a.data, 125, 125) node _sign_a_T_126 = bits(io.a.data, 126, 126) node _sign_a_T_127 = bits(io.a.data, 127, 127) node sign_a_lo_lo_lo = cat(_sign_a_T_15, _sign_a_T_7) node sign_a_lo_lo_hi = cat(_sign_a_T_31, _sign_a_T_23) node sign_a_lo_lo = cat(sign_a_lo_lo_hi, sign_a_lo_lo_lo) node sign_a_lo_hi_lo = cat(_sign_a_T_47, _sign_a_T_39) node sign_a_lo_hi_hi = cat(_sign_a_T_63, _sign_a_T_55) node sign_a_lo_hi = cat(sign_a_lo_hi_hi, sign_a_lo_hi_lo) node sign_a_lo = cat(sign_a_lo_hi, sign_a_lo_lo) node sign_a_hi_lo_lo = cat(_sign_a_T_79, _sign_a_T_71) node sign_a_hi_lo_hi = cat(_sign_a_T_95, _sign_a_T_87) node sign_a_hi_lo = cat(sign_a_hi_lo_hi, sign_a_hi_lo_lo) node sign_a_hi_hi_lo = cat(_sign_a_T_111, _sign_a_T_103) node sign_a_hi_hi_hi = cat(_sign_a_T_127, _sign_a_T_119) node sign_a_hi_hi = cat(sign_a_hi_hi_hi, sign_a_hi_hi_lo) node sign_a_hi = cat(sign_a_hi_hi, sign_a_hi_lo) node _sign_a_T_128 = cat(sign_a_hi, sign_a_lo) node _sign_a_T_129 = and(_sign_a_T_128, signBit) node sign_a = orr(_sign_a_T_129) node _sign_d_T = bits(io.data_in, 0, 0) node _sign_d_T_1 = bits(io.data_in, 1, 1) node _sign_d_T_2 = bits(io.data_in, 2, 2) node _sign_d_T_3 = bits(io.data_in, 3, 3) node _sign_d_T_4 = bits(io.data_in, 4, 4) node _sign_d_T_5 = bits(io.data_in, 5, 5) node _sign_d_T_6 = bits(io.data_in, 6, 6) node _sign_d_T_7 = bits(io.data_in, 7, 7) node _sign_d_T_8 = bits(io.data_in, 8, 8) node _sign_d_T_9 = bits(io.data_in, 9, 9) node _sign_d_T_10 = bits(io.data_in, 10, 10) node _sign_d_T_11 = bits(io.data_in, 11, 11) node _sign_d_T_12 = bits(io.data_in, 12, 12) node _sign_d_T_13 = bits(io.data_in, 13, 13) node _sign_d_T_14 = bits(io.data_in, 14, 14) node _sign_d_T_15 = bits(io.data_in, 15, 15) node _sign_d_T_16 = bits(io.data_in, 16, 16) node _sign_d_T_17 = bits(io.data_in, 17, 17) node _sign_d_T_18 = bits(io.data_in, 18, 18) node _sign_d_T_19 = bits(io.data_in, 19, 19) node _sign_d_T_20 = bits(io.data_in, 20, 20) node _sign_d_T_21 = bits(io.data_in, 21, 21) node _sign_d_T_22 = bits(io.data_in, 22, 22) node _sign_d_T_23 = bits(io.data_in, 23, 23) node _sign_d_T_24 = bits(io.data_in, 24, 24) node _sign_d_T_25 = bits(io.data_in, 25, 25) node _sign_d_T_26 = bits(io.data_in, 26, 26) node _sign_d_T_27 = bits(io.data_in, 27, 27) node _sign_d_T_28 = bits(io.data_in, 28, 28) node _sign_d_T_29 = bits(io.data_in, 29, 29) node _sign_d_T_30 = bits(io.data_in, 30, 30) node _sign_d_T_31 = bits(io.data_in, 31, 31) node _sign_d_T_32 = bits(io.data_in, 32, 32) node _sign_d_T_33 = bits(io.data_in, 33, 33) node _sign_d_T_34 = bits(io.data_in, 34, 34) node _sign_d_T_35 = bits(io.data_in, 35, 35) node _sign_d_T_36 = bits(io.data_in, 36, 36) node _sign_d_T_37 = bits(io.data_in, 37, 37) node _sign_d_T_38 = bits(io.data_in, 38, 38) node _sign_d_T_39 = bits(io.data_in, 39, 39) node _sign_d_T_40 = bits(io.data_in, 40, 40) node _sign_d_T_41 = bits(io.data_in, 41, 41) node _sign_d_T_42 = bits(io.data_in, 42, 42) node _sign_d_T_43 = bits(io.data_in, 43, 43) node _sign_d_T_44 = bits(io.data_in, 44, 44) node _sign_d_T_45 = bits(io.data_in, 45, 45) node _sign_d_T_46 = bits(io.data_in, 46, 46) node _sign_d_T_47 = bits(io.data_in, 47, 47) node _sign_d_T_48 = bits(io.data_in, 48, 48) node _sign_d_T_49 = bits(io.data_in, 49, 49) node _sign_d_T_50 = bits(io.data_in, 50, 50) node _sign_d_T_51 = bits(io.data_in, 51, 51) node _sign_d_T_52 = bits(io.data_in, 52, 52) node _sign_d_T_53 = bits(io.data_in, 53, 53) node _sign_d_T_54 = bits(io.data_in, 54, 54) node _sign_d_T_55 = bits(io.data_in, 55, 55) node _sign_d_T_56 = bits(io.data_in, 56, 56) node _sign_d_T_57 = bits(io.data_in, 57, 57) node _sign_d_T_58 = bits(io.data_in, 58, 58) node _sign_d_T_59 = bits(io.data_in, 59, 59) node _sign_d_T_60 = bits(io.data_in, 60, 60) node _sign_d_T_61 = bits(io.data_in, 61, 61) node _sign_d_T_62 = bits(io.data_in, 62, 62) node _sign_d_T_63 = bits(io.data_in, 63, 63) node _sign_d_T_64 = bits(io.data_in, 64, 64) node _sign_d_T_65 = bits(io.data_in, 65, 65) node _sign_d_T_66 = bits(io.data_in, 66, 66) node _sign_d_T_67 = bits(io.data_in, 67, 67) node _sign_d_T_68 = bits(io.data_in, 68, 68) node _sign_d_T_69 = bits(io.data_in, 69, 69) node _sign_d_T_70 = bits(io.data_in, 70, 70) node _sign_d_T_71 = bits(io.data_in, 71, 71) node _sign_d_T_72 = bits(io.data_in, 72, 72) node _sign_d_T_73 = bits(io.data_in, 73, 73) node _sign_d_T_74 = bits(io.data_in, 74, 74) node _sign_d_T_75 = bits(io.data_in, 75, 75) node _sign_d_T_76 = bits(io.data_in, 76, 76) node _sign_d_T_77 = bits(io.data_in, 77, 77) node _sign_d_T_78 = bits(io.data_in, 78, 78) node _sign_d_T_79 = bits(io.data_in, 79, 79) node _sign_d_T_80 = bits(io.data_in, 80, 80) node _sign_d_T_81 = bits(io.data_in, 81, 81) node _sign_d_T_82 = bits(io.data_in, 82, 82) node _sign_d_T_83 = bits(io.data_in, 83, 83) node _sign_d_T_84 = bits(io.data_in, 84, 84) node _sign_d_T_85 = bits(io.data_in, 85, 85) node _sign_d_T_86 = bits(io.data_in, 86, 86) node _sign_d_T_87 = bits(io.data_in, 87, 87) node _sign_d_T_88 = bits(io.data_in, 88, 88) node _sign_d_T_89 = bits(io.data_in, 89, 89) node _sign_d_T_90 = bits(io.data_in, 90, 90) node _sign_d_T_91 = bits(io.data_in, 91, 91) node _sign_d_T_92 = bits(io.data_in, 92, 92) node _sign_d_T_93 = bits(io.data_in, 93, 93) node _sign_d_T_94 = bits(io.data_in, 94, 94) node _sign_d_T_95 = bits(io.data_in, 95, 95) node _sign_d_T_96 = bits(io.data_in, 96, 96) node _sign_d_T_97 = bits(io.data_in, 97, 97) node _sign_d_T_98 = bits(io.data_in, 98, 98) node _sign_d_T_99 = bits(io.data_in, 99, 99) node _sign_d_T_100 = bits(io.data_in, 100, 100) node _sign_d_T_101 = bits(io.data_in, 101, 101) node _sign_d_T_102 = bits(io.data_in, 102, 102) node _sign_d_T_103 = bits(io.data_in, 103, 103) node _sign_d_T_104 = bits(io.data_in, 104, 104) node _sign_d_T_105 = bits(io.data_in, 105, 105) node _sign_d_T_106 = bits(io.data_in, 106, 106) node _sign_d_T_107 = bits(io.data_in, 107, 107) node _sign_d_T_108 = bits(io.data_in, 108, 108) node _sign_d_T_109 = bits(io.data_in, 109, 109) node _sign_d_T_110 = bits(io.data_in, 110, 110) node _sign_d_T_111 = bits(io.data_in, 111, 111) node _sign_d_T_112 = bits(io.data_in, 112, 112) node _sign_d_T_113 = bits(io.data_in, 113, 113) node _sign_d_T_114 = bits(io.data_in, 114, 114) node _sign_d_T_115 = bits(io.data_in, 115, 115) node _sign_d_T_116 = bits(io.data_in, 116, 116) node _sign_d_T_117 = bits(io.data_in, 117, 117) node _sign_d_T_118 = bits(io.data_in, 118, 118) node _sign_d_T_119 = bits(io.data_in, 119, 119) node _sign_d_T_120 = bits(io.data_in, 120, 120) node _sign_d_T_121 = bits(io.data_in, 121, 121) node _sign_d_T_122 = bits(io.data_in, 122, 122) node _sign_d_T_123 = bits(io.data_in, 123, 123) node _sign_d_T_124 = bits(io.data_in, 124, 124) node _sign_d_T_125 = bits(io.data_in, 125, 125) node _sign_d_T_126 = bits(io.data_in, 126, 126) node _sign_d_T_127 = bits(io.data_in, 127, 127) node sign_d_lo_lo_lo = cat(_sign_d_T_15, _sign_d_T_7) node sign_d_lo_lo_hi = cat(_sign_d_T_31, _sign_d_T_23) node sign_d_lo_lo = cat(sign_d_lo_lo_hi, sign_d_lo_lo_lo) node sign_d_lo_hi_lo = cat(_sign_d_T_47, _sign_d_T_39) node sign_d_lo_hi_hi = cat(_sign_d_T_63, _sign_d_T_55) node sign_d_lo_hi = cat(sign_d_lo_hi_hi, sign_d_lo_hi_lo) node sign_d_lo = cat(sign_d_lo_hi, sign_d_lo_lo) node sign_d_hi_lo_lo = cat(_sign_d_T_79, _sign_d_T_71) node sign_d_hi_lo_hi = cat(_sign_d_T_95, _sign_d_T_87) node sign_d_hi_lo = cat(sign_d_hi_lo_hi, sign_d_hi_lo_lo) node sign_d_hi_hi_lo = cat(_sign_d_T_111, _sign_d_T_103) node sign_d_hi_hi_hi = cat(_sign_d_T_127, _sign_d_T_119) node sign_d_hi_hi = cat(sign_d_hi_hi_hi, sign_d_hi_hi_lo) node sign_d_hi = cat(sign_d_hi_hi, sign_d_hi_lo) node _sign_d_T_128 = cat(sign_d_hi, sign_d_lo) node _sign_d_T_129 = and(_sign_d_T_128, signBit) node sign_d = orr(_sign_d_T_129) node _sign_s_T = bits(sum, 0, 0) node _sign_s_T_1 = bits(sum, 1, 1) node _sign_s_T_2 = bits(sum, 2, 2) node _sign_s_T_3 = bits(sum, 3, 3) node _sign_s_T_4 = bits(sum, 4, 4) node _sign_s_T_5 = bits(sum, 5, 5) node _sign_s_T_6 = bits(sum, 6, 6) node _sign_s_T_7 = bits(sum, 7, 7) node _sign_s_T_8 = bits(sum, 8, 8) node _sign_s_T_9 = bits(sum, 9, 9) node _sign_s_T_10 = bits(sum, 10, 10) node _sign_s_T_11 = bits(sum, 11, 11) node _sign_s_T_12 = bits(sum, 12, 12) node _sign_s_T_13 = bits(sum, 13, 13) node _sign_s_T_14 = bits(sum, 14, 14) node _sign_s_T_15 = bits(sum, 15, 15) node _sign_s_T_16 = bits(sum, 16, 16) node _sign_s_T_17 = bits(sum, 17, 17) node _sign_s_T_18 = bits(sum, 18, 18) node _sign_s_T_19 = bits(sum, 19, 19) node _sign_s_T_20 = bits(sum, 20, 20) node _sign_s_T_21 = bits(sum, 21, 21) node _sign_s_T_22 = bits(sum, 22, 22) node _sign_s_T_23 = bits(sum, 23, 23) node _sign_s_T_24 = bits(sum, 24, 24) node _sign_s_T_25 = bits(sum, 25, 25) node _sign_s_T_26 = bits(sum, 26, 26) node _sign_s_T_27 = bits(sum, 27, 27) node _sign_s_T_28 = bits(sum, 28, 28) node _sign_s_T_29 = bits(sum, 29, 29) node _sign_s_T_30 = bits(sum, 30, 30) node _sign_s_T_31 = bits(sum, 31, 31) node _sign_s_T_32 = bits(sum, 32, 32) node _sign_s_T_33 = bits(sum, 33, 33) node _sign_s_T_34 = bits(sum, 34, 34) node _sign_s_T_35 = bits(sum, 35, 35) node _sign_s_T_36 = bits(sum, 36, 36) node _sign_s_T_37 = bits(sum, 37, 37) node _sign_s_T_38 = bits(sum, 38, 38) node _sign_s_T_39 = bits(sum, 39, 39) node _sign_s_T_40 = bits(sum, 40, 40) node _sign_s_T_41 = bits(sum, 41, 41) node _sign_s_T_42 = bits(sum, 42, 42) node _sign_s_T_43 = bits(sum, 43, 43) node _sign_s_T_44 = bits(sum, 44, 44) node _sign_s_T_45 = bits(sum, 45, 45) node _sign_s_T_46 = bits(sum, 46, 46) node _sign_s_T_47 = bits(sum, 47, 47) node _sign_s_T_48 = bits(sum, 48, 48) node _sign_s_T_49 = bits(sum, 49, 49) node _sign_s_T_50 = bits(sum, 50, 50) node _sign_s_T_51 = bits(sum, 51, 51) node _sign_s_T_52 = bits(sum, 52, 52) node _sign_s_T_53 = bits(sum, 53, 53) node _sign_s_T_54 = bits(sum, 54, 54) node _sign_s_T_55 = bits(sum, 55, 55) node _sign_s_T_56 = bits(sum, 56, 56) node _sign_s_T_57 = bits(sum, 57, 57) node _sign_s_T_58 = bits(sum, 58, 58) node _sign_s_T_59 = bits(sum, 59, 59) node _sign_s_T_60 = bits(sum, 60, 60) node _sign_s_T_61 = bits(sum, 61, 61) node _sign_s_T_62 = bits(sum, 62, 62) node _sign_s_T_63 = bits(sum, 63, 63) node _sign_s_T_64 = bits(sum, 64, 64) node _sign_s_T_65 = bits(sum, 65, 65) node _sign_s_T_66 = bits(sum, 66, 66) node _sign_s_T_67 = bits(sum, 67, 67) node _sign_s_T_68 = bits(sum, 68, 68) node _sign_s_T_69 = bits(sum, 69, 69) node _sign_s_T_70 = bits(sum, 70, 70) node _sign_s_T_71 = bits(sum, 71, 71) node _sign_s_T_72 = bits(sum, 72, 72) node _sign_s_T_73 = bits(sum, 73, 73) node _sign_s_T_74 = bits(sum, 74, 74) node _sign_s_T_75 = bits(sum, 75, 75) node _sign_s_T_76 = bits(sum, 76, 76) node _sign_s_T_77 = bits(sum, 77, 77) node _sign_s_T_78 = bits(sum, 78, 78) node _sign_s_T_79 = bits(sum, 79, 79) node _sign_s_T_80 = bits(sum, 80, 80) node _sign_s_T_81 = bits(sum, 81, 81) node _sign_s_T_82 = bits(sum, 82, 82) node _sign_s_T_83 = bits(sum, 83, 83) node _sign_s_T_84 = bits(sum, 84, 84) node _sign_s_T_85 = bits(sum, 85, 85) node _sign_s_T_86 = bits(sum, 86, 86) node _sign_s_T_87 = bits(sum, 87, 87) node _sign_s_T_88 = bits(sum, 88, 88) node _sign_s_T_89 = bits(sum, 89, 89) node _sign_s_T_90 = bits(sum, 90, 90) node _sign_s_T_91 = bits(sum, 91, 91) node _sign_s_T_92 = bits(sum, 92, 92) node _sign_s_T_93 = bits(sum, 93, 93) node _sign_s_T_94 = bits(sum, 94, 94) node _sign_s_T_95 = bits(sum, 95, 95) node _sign_s_T_96 = bits(sum, 96, 96) node _sign_s_T_97 = bits(sum, 97, 97) node _sign_s_T_98 = bits(sum, 98, 98) node _sign_s_T_99 = bits(sum, 99, 99) node _sign_s_T_100 = bits(sum, 100, 100) node _sign_s_T_101 = bits(sum, 101, 101) node _sign_s_T_102 = bits(sum, 102, 102) node _sign_s_T_103 = bits(sum, 103, 103) node _sign_s_T_104 = bits(sum, 104, 104) node _sign_s_T_105 = bits(sum, 105, 105) node _sign_s_T_106 = bits(sum, 106, 106) node _sign_s_T_107 = bits(sum, 107, 107) node _sign_s_T_108 = bits(sum, 108, 108) node _sign_s_T_109 = bits(sum, 109, 109) node _sign_s_T_110 = bits(sum, 110, 110) node _sign_s_T_111 = bits(sum, 111, 111) node _sign_s_T_112 = bits(sum, 112, 112) node _sign_s_T_113 = bits(sum, 113, 113) node _sign_s_T_114 = bits(sum, 114, 114) node _sign_s_T_115 = bits(sum, 115, 115) node _sign_s_T_116 = bits(sum, 116, 116) node _sign_s_T_117 = bits(sum, 117, 117) node _sign_s_T_118 = bits(sum, 118, 118) node _sign_s_T_119 = bits(sum, 119, 119) node _sign_s_T_120 = bits(sum, 120, 120) node _sign_s_T_121 = bits(sum, 121, 121) node _sign_s_T_122 = bits(sum, 122, 122) node _sign_s_T_123 = bits(sum, 123, 123) node _sign_s_T_124 = bits(sum, 124, 124) node _sign_s_T_125 = bits(sum, 125, 125) node _sign_s_T_126 = bits(sum, 126, 126) node _sign_s_T_127 = bits(sum, 127, 127) node sign_s_lo_lo_lo = cat(_sign_s_T_15, _sign_s_T_7) node sign_s_lo_lo_hi = cat(_sign_s_T_31, _sign_s_T_23) node sign_s_lo_lo = cat(sign_s_lo_lo_hi, sign_s_lo_lo_lo) node sign_s_lo_hi_lo = cat(_sign_s_T_47, _sign_s_T_39) node sign_s_lo_hi_hi = cat(_sign_s_T_63, _sign_s_T_55) node sign_s_lo_hi = cat(sign_s_lo_hi_hi, sign_s_lo_hi_lo) node sign_s_lo = cat(sign_s_lo_hi, sign_s_lo_lo) node sign_s_hi_lo_lo = cat(_sign_s_T_79, _sign_s_T_71) node sign_s_hi_lo_hi = cat(_sign_s_T_95, _sign_s_T_87) node sign_s_hi_lo = cat(sign_s_hi_lo_hi, sign_s_hi_lo_lo) node sign_s_hi_hi_lo = cat(_sign_s_T_111, _sign_s_T_103) node sign_s_hi_hi_hi = cat(_sign_s_T_127, _sign_s_T_119) node sign_s_hi_hi = cat(sign_s_hi_hi_hi, sign_s_hi_hi_lo) node sign_s_hi = cat(sign_s_hi_hi, sign_s_hi_lo) node _sign_s_T_128 = cat(sign_s_hi, sign_s_lo) node _sign_s_T_129 = and(_sign_s_T_128, signBit) node sign_s = orr(_sign_s_T_129) node a_bigger_uneq = eq(unsigned, sign_a) node _a_bigger_T = eq(sign_a, sign_d) node _a_bigger_T_1 = eq(sign_s, UInt<1>(0h0)) node a_bigger = mux(_a_bigger_T, _a_bigger_T_1, a_bigger_uneq) node pick_a = eq(take_max, a_bigger) wire _lut_WIRE : UInt<4>[4] connect _lut_WIRE[0], UInt<3>(0h6) connect _lut_WIRE[1], UInt<4>(0he) connect _lut_WIRE[2], UInt<4>(0h8) connect _lut_WIRE[3], UInt<4>(0hc) node _lut_T = bits(io.a.param, 1, 0) node _logical_T = bits(io.a.data, 0, 0) node _logical_T_1 = bits(io.a.data, 1, 1) node _logical_T_2 = bits(io.a.data, 2, 2) node _logical_T_3 = bits(io.a.data, 3, 3) node _logical_T_4 = bits(io.a.data, 4, 4) node _logical_T_5 = bits(io.a.data, 5, 5) node _logical_T_6 = bits(io.a.data, 6, 6) node _logical_T_7 = bits(io.a.data, 7, 7) node _logical_T_8 = bits(io.a.data, 8, 8) node _logical_T_9 = bits(io.a.data, 9, 9) node _logical_T_10 = bits(io.a.data, 10, 10) node _logical_T_11 = bits(io.a.data, 11, 11) node _logical_T_12 = bits(io.a.data, 12, 12) node _logical_T_13 = bits(io.a.data, 13, 13) node _logical_T_14 = bits(io.a.data, 14, 14) node _logical_T_15 = bits(io.a.data, 15, 15) node _logical_T_16 = bits(io.a.data, 16, 16) node _logical_T_17 = bits(io.a.data, 17, 17) node _logical_T_18 = bits(io.a.data, 18, 18) node _logical_T_19 = bits(io.a.data, 19, 19) node _logical_T_20 = bits(io.a.data, 20, 20) node _logical_T_21 = bits(io.a.data, 21, 21) node _logical_T_22 = bits(io.a.data, 22, 22) node _logical_T_23 = bits(io.a.data, 23, 23) node _logical_T_24 = bits(io.a.data, 24, 24) node _logical_T_25 = bits(io.a.data, 25, 25) node _logical_T_26 = bits(io.a.data, 26, 26) node _logical_T_27 = bits(io.a.data, 27, 27) node _logical_T_28 = bits(io.a.data, 28, 28) node _logical_T_29 = bits(io.a.data, 29, 29) node _logical_T_30 = bits(io.a.data, 30, 30) node _logical_T_31 = bits(io.a.data, 31, 31) node _logical_T_32 = bits(io.a.data, 32, 32) node _logical_T_33 = bits(io.a.data, 33, 33) node _logical_T_34 = bits(io.a.data, 34, 34) node _logical_T_35 = bits(io.a.data, 35, 35) node _logical_T_36 = bits(io.a.data, 36, 36) node _logical_T_37 = bits(io.a.data, 37, 37) node _logical_T_38 = bits(io.a.data, 38, 38) node _logical_T_39 = bits(io.a.data, 39, 39) node _logical_T_40 = bits(io.a.data, 40, 40) node _logical_T_41 = bits(io.a.data, 41, 41) node _logical_T_42 = bits(io.a.data, 42, 42) node _logical_T_43 = bits(io.a.data, 43, 43) node _logical_T_44 = bits(io.a.data, 44, 44) node _logical_T_45 = bits(io.a.data, 45, 45) node _logical_T_46 = bits(io.a.data, 46, 46) node _logical_T_47 = bits(io.a.data, 47, 47) node _logical_T_48 = bits(io.a.data, 48, 48) node _logical_T_49 = bits(io.a.data, 49, 49) node _logical_T_50 = bits(io.a.data, 50, 50) node _logical_T_51 = bits(io.a.data, 51, 51) node _logical_T_52 = bits(io.a.data, 52, 52) node _logical_T_53 = bits(io.a.data, 53, 53) node _logical_T_54 = bits(io.a.data, 54, 54) node _logical_T_55 = bits(io.a.data, 55, 55) node _logical_T_56 = bits(io.a.data, 56, 56) node _logical_T_57 = bits(io.a.data, 57, 57) node _logical_T_58 = bits(io.a.data, 58, 58) node _logical_T_59 = bits(io.a.data, 59, 59) node _logical_T_60 = bits(io.a.data, 60, 60) node _logical_T_61 = bits(io.a.data, 61, 61) node _logical_T_62 = bits(io.a.data, 62, 62) node _logical_T_63 = bits(io.a.data, 63, 63) node _logical_T_64 = bits(io.a.data, 64, 64) node _logical_T_65 = bits(io.a.data, 65, 65) node _logical_T_66 = bits(io.a.data, 66, 66) node _logical_T_67 = bits(io.a.data, 67, 67) node _logical_T_68 = bits(io.a.data, 68, 68) node _logical_T_69 = bits(io.a.data, 69, 69) node _logical_T_70 = bits(io.a.data, 70, 70) node _logical_T_71 = bits(io.a.data, 71, 71) node _logical_T_72 = bits(io.a.data, 72, 72) node _logical_T_73 = bits(io.a.data, 73, 73) node _logical_T_74 = bits(io.a.data, 74, 74) node _logical_T_75 = bits(io.a.data, 75, 75) node _logical_T_76 = bits(io.a.data, 76, 76) node _logical_T_77 = bits(io.a.data, 77, 77) node _logical_T_78 = bits(io.a.data, 78, 78) node _logical_T_79 = bits(io.a.data, 79, 79) node _logical_T_80 = bits(io.a.data, 80, 80) node _logical_T_81 = bits(io.a.data, 81, 81) node _logical_T_82 = bits(io.a.data, 82, 82) node _logical_T_83 = bits(io.a.data, 83, 83) node _logical_T_84 = bits(io.a.data, 84, 84) node _logical_T_85 = bits(io.a.data, 85, 85) node _logical_T_86 = bits(io.a.data, 86, 86) node _logical_T_87 = bits(io.a.data, 87, 87) node _logical_T_88 = bits(io.a.data, 88, 88) node _logical_T_89 = bits(io.a.data, 89, 89) node _logical_T_90 = bits(io.a.data, 90, 90) node _logical_T_91 = bits(io.a.data, 91, 91) node _logical_T_92 = bits(io.a.data, 92, 92) node _logical_T_93 = bits(io.a.data, 93, 93) node _logical_T_94 = bits(io.a.data, 94, 94) node _logical_T_95 = bits(io.a.data, 95, 95) node _logical_T_96 = bits(io.a.data, 96, 96) node _logical_T_97 = bits(io.a.data, 97, 97) node _logical_T_98 = bits(io.a.data, 98, 98) node _logical_T_99 = bits(io.a.data, 99, 99) node _logical_T_100 = bits(io.a.data, 100, 100) node _logical_T_101 = bits(io.a.data, 101, 101) node _logical_T_102 = bits(io.a.data, 102, 102) node _logical_T_103 = bits(io.a.data, 103, 103) node _logical_T_104 = bits(io.a.data, 104, 104) node _logical_T_105 = bits(io.a.data, 105, 105) node _logical_T_106 = bits(io.a.data, 106, 106) node _logical_T_107 = bits(io.a.data, 107, 107) node _logical_T_108 = bits(io.a.data, 108, 108) node _logical_T_109 = bits(io.a.data, 109, 109) node _logical_T_110 = bits(io.a.data, 110, 110) node _logical_T_111 = bits(io.a.data, 111, 111) node _logical_T_112 = bits(io.a.data, 112, 112) node _logical_T_113 = bits(io.a.data, 113, 113) node _logical_T_114 = bits(io.a.data, 114, 114) node _logical_T_115 = bits(io.a.data, 115, 115) node _logical_T_116 = bits(io.a.data, 116, 116) node _logical_T_117 = bits(io.a.data, 117, 117) node _logical_T_118 = bits(io.a.data, 118, 118) node _logical_T_119 = bits(io.a.data, 119, 119) node _logical_T_120 = bits(io.a.data, 120, 120) node _logical_T_121 = bits(io.a.data, 121, 121) node _logical_T_122 = bits(io.a.data, 122, 122) node _logical_T_123 = bits(io.a.data, 123, 123) node _logical_T_124 = bits(io.a.data, 124, 124) node _logical_T_125 = bits(io.a.data, 125, 125) node _logical_T_126 = bits(io.a.data, 126, 126) node _logical_T_127 = bits(io.a.data, 127, 127) node _logical_T_128 = bits(io.data_in, 0, 0) node _logical_T_129 = bits(io.data_in, 1, 1) node _logical_T_130 = bits(io.data_in, 2, 2) node _logical_T_131 = bits(io.data_in, 3, 3) node _logical_T_132 = bits(io.data_in, 4, 4) node _logical_T_133 = bits(io.data_in, 5, 5) node _logical_T_134 = bits(io.data_in, 6, 6) node _logical_T_135 = bits(io.data_in, 7, 7) node _logical_T_136 = bits(io.data_in, 8, 8) node _logical_T_137 = bits(io.data_in, 9, 9) node _logical_T_138 = bits(io.data_in, 10, 10) node _logical_T_139 = bits(io.data_in, 11, 11) node _logical_T_140 = bits(io.data_in, 12, 12) node _logical_T_141 = bits(io.data_in, 13, 13) node _logical_T_142 = bits(io.data_in, 14, 14) node _logical_T_143 = bits(io.data_in, 15, 15) node _logical_T_144 = bits(io.data_in, 16, 16) node _logical_T_145 = bits(io.data_in, 17, 17) node _logical_T_146 = bits(io.data_in, 18, 18) node _logical_T_147 = bits(io.data_in, 19, 19) node _logical_T_148 = bits(io.data_in, 20, 20) node _logical_T_149 = bits(io.data_in, 21, 21) node _logical_T_150 = bits(io.data_in, 22, 22) node _logical_T_151 = bits(io.data_in, 23, 23) node _logical_T_152 = bits(io.data_in, 24, 24) node _logical_T_153 = bits(io.data_in, 25, 25) node _logical_T_154 = bits(io.data_in, 26, 26) node _logical_T_155 = bits(io.data_in, 27, 27) node _logical_T_156 = bits(io.data_in, 28, 28) node _logical_T_157 = bits(io.data_in, 29, 29) node _logical_T_158 = bits(io.data_in, 30, 30) node _logical_T_159 = bits(io.data_in, 31, 31) node _logical_T_160 = bits(io.data_in, 32, 32) node _logical_T_161 = bits(io.data_in, 33, 33) node _logical_T_162 = bits(io.data_in, 34, 34) node _logical_T_163 = bits(io.data_in, 35, 35) node _logical_T_164 = bits(io.data_in, 36, 36) node _logical_T_165 = bits(io.data_in, 37, 37) node _logical_T_166 = bits(io.data_in, 38, 38) node _logical_T_167 = bits(io.data_in, 39, 39) node _logical_T_168 = bits(io.data_in, 40, 40) node _logical_T_169 = bits(io.data_in, 41, 41) node _logical_T_170 = bits(io.data_in, 42, 42) node _logical_T_171 = bits(io.data_in, 43, 43) node _logical_T_172 = bits(io.data_in, 44, 44) node _logical_T_173 = bits(io.data_in, 45, 45) node _logical_T_174 = bits(io.data_in, 46, 46) node _logical_T_175 = bits(io.data_in, 47, 47) node _logical_T_176 = bits(io.data_in, 48, 48) node _logical_T_177 = bits(io.data_in, 49, 49) node _logical_T_178 = bits(io.data_in, 50, 50) node _logical_T_179 = bits(io.data_in, 51, 51) node _logical_T_180 = bits(io.data_in, 52, 52) node _logical_T_181 = bits(io.data_in, 53, 53) node _logical_T_182 = bits(io.data_in, 54, 54) node _logical_T_183 = bits(io.data_in, 55, 55) node _logical_T_184 = bits(io.data_in, 56, 56) node _logical_T_185 = bits(io.data_in, 57, 57) node _logical_T_186 = bits(io.data_in, 58, 58) node _logical_T_187 = bits(io.data_in, 59, 59) node _logical_T_188 = bits(io.data_in, 60, 60) node _logical_T_189 = bits(io.data_in, 61, 61) node _logical_T_190 = bits(io.data_in, 62, 62) node _logical_T_191 = bits(io.data_in, 63, 63) node _logical_T_192 = bits(io.data_in, 64, 64) node _logical_T_193 = bits(io.data_in, 65, 65) node _logical_T_194 = bits(io.data_in, 66, 66) node _logical_T_195 = bits(io.data_in, 67, 67) node _logical_T_196 = bits(io.data_in, 68, 68) node _logical_T_197 = bits(io.data_in, 69, 69) node _logical_T_198 = bits(io.data_in, 70, 70) node _logical_T_199 = bits(io.data_in, 71, 71) node _logical_T_200 = bits(io.data_in, 72, 72) node _logical_T_201 = bits(io.data_in, 73, 73) node _logical_T_202 = bits(io.data_in, 74, 74) node _logical_T_203 = bits(io.data_in, 75, 75) node _logical_T_204 = bits(io.data_in, 76, 76) node _logical_T_205 = bits(io.data_in, 77, 77) node _logical_T_206 = bits(io.data_in, 78, 78) node _logical_T_207 = bits(io.data_in, 79, 79) node _logical_T_208 = bits(io.data_in, 80, 80) node _logical_T_209 = bits(io.data_in, 81, 81) node _logical_T_210 = bits(io.data_in, 82, 82) node _logical_T_211 = bits(io.data_in, 83, 83) node _logical_T_212 = bits(io.data_in, 84, 84) node _logical_T_213 = bits(io.data_in, 85, 85) node _logical_T_214 = bits(io.data_in, 86, 86) node _logical_T_215 = bits(io.data_in, 87, 87) node _logical_T_216 = bits(io.data_in, 88, 88) node _logical_T_217 = bits(io.data_in, 89, 89) node _logical_T_218 = bits(io.data_in, 90, 90) node _logical_T_219 = bits(io.data_in, 91, 91) node _logical_T_220 = bits(io.data_in, 92, 92) node _logical_T_221 = bits(io.data_in, 93, 93) node _logical_T_222 = bits(io.data_in, 94, 94) node _logical_T_223 = bits(io.data_in, 95, 95) node _logical_T_224 = bits(io.data_in, 96, 96) node _logical_T_225 = bits(io.data_in, 97, 97) node _logical_T_226 = bits(io.data_in, 98, 98) node _logical_T_227 = bits(io.data_in, 99, 99) node _logical_T_228 = bits(io.data_in, 100, 100) node _logical_T_229 = bits(io.data_in, 101, 101) node _logical_T_230 = bits(io.data_in, 102, 102) node _logical_T_231 = bits(io.data_in, 103, 103) node _logical_T_232 = bits(io.data_in, 104, 104) node _logical_T_233 = bits(io.data_in, 105, 105) node _logical_T_234 = bits(io.data_in, 106, 106) node _logical_T_235 = bits(io.data_in, 107, 107) node _logical_T_236 = bits(io.data_in, 108, 108) node _logical_T_237 = bits(io.data_in, 109, 109) node _logical_T_238 = bits(io.data_in, 110, 110) node _logical_T_239 = bits(io.data_in, 111, 111) node _logical_T_240 = bits(io.data_in, 112, 112) node _logical_T_241 = bits(io.data_in, 113, 113) node _logical_T_242 = bits(io.data_in, 114, 114) node _logical_T_243 = bits(io.data_in, 115, 115) node _logical_T_244 = bits(io.data_in, 116, 116) node _logical_T_245 = bits(io.data_in, 117, 117) node _logical_T_246 = bits(io.data_in, 118, 118) node _logical_T_247 = bits(io.data_in, 119, 119) node _logical_T_248 = bits(io.data_in, 120, 120) node _logical_T_249 = bits(io.data_in, 121, 121) node _logical_T_250 = bits(io.data_in, 122, 122) node _logical_T_251 = bits(io.data_in, 123, 123) node _logical_T_252 = bits(io.data_in, 124, 124) node _logical_T_253 = bits(io.data_in, 125, 125) node _logical_T_254 = bits(io.data_in, 126, 126) node _logical_T_255 = bits(io.data_in, 127, 127) node _logical_T_256 = cat(_logical_T, _logical_T_128) node _logical_T_257 = dshr(_lut_WIRE[_lut_T], _logical_T_256) node _logical_T_258 = bits(_logical_T_257, 0, 0) node _logical_T_259 = cat(_logical_T_1, _logical_T_129) node _logical_T_260 = dshr(_lut_WIRE[_lut_T], _logical_T_259) node _logical_T_261 = bits(_logical_T_260, 0, 0) node _logical_T_262 = cat(_logical_T_2, _logical_T_130) node _logical_T_263 = dshr(_lut_WIRE[_lut_T], _logical_T_262) node _logical_T_264 = bits(_logical_T_263, 0, 0) node _logical_T_265 = cat(_logical_T_3, _logical_T_131) node _logical_T_266 = dshr(_lut_WIRE[_lut_T], _logical_T_265) node _logical_T_267 = bits(_logical_T_266, 0, 0) node _logical_T_268 = cat(_logical_T_4, _logical_T_132) node _logical_T_269 = dshr(_lut_WIRE[_lut_T], _logical_T_268) node _logical_T_270 = bits(_logical_T_269, 0, 0) node _logical_T_271 = cat(_logical_T_5, _logical_T_133) node _logical_T_272 = dshr(_lut_WIRE[_lut_T], _logical_T_271) node _logical_T_273 = bits(_logical_T_272, 0, 0) node _logical_T_274 = cat(_logical_T_6, _logical_T_134) node _logical_T_275 = dshr(_lut_WIRE[_lut_T], _logical_T_274) node _logical_T_276 = bits(_logical_T_275, 0, 0) node _logical_T_277 = cat(_logical_T_7, _logical_T_135) node _logical_T_278 = dshr(_lut_WIRE[_lut_T], _logical_T_277) node _logical_T_279 = bits(_logical_T_278, 0, 0) node _logical_T_280 = cat(_logical_T_8, _logical_T_136) node _logical_T_281 = dshr(_lut_WIRE[_lut_T], _logical_T_280) node _logical_T_282 = bits(_logical_T_281, 0, 0) node _logical_T_283 = cat(_logical_T_9, _logical_T_137) node _logical_T_284 = dshr(_lut_WIRE[_lut_T], _logical_T_283) node _logical_T_285 = bits(_logical_T_284, 0, 0) node _logical_T_286 = cat(_logical_T_10, _logical_T_138) node _logical_T_287 = dshr(_lut_WIRE[_lut_T], _logical_T_286) node _logical_T_288 = bits(_logical_T_287, 0, 0) node _logical_T_289 = cat(_logical_T_11, _logical_T_139) node _logical_T_290 = dshr(_lut_WIRE[_lut_T], _logical_T_289) node _logical_T_291 = bits(_logical_T_290, 0, 0) node _logical_T_292 = cat(_logical_T_12, _logical_T_140) node _logical_T_293 = dshr(_lut_WIRE[_lut_T], _logical_T_292) node _logical_T_294 = bits(_logical_T_293, 0, 0) node _logical_T_295 = cat(_logical_T_13, _logical_T_141) node _logical_T_296 = dshr(_lut_WIRE[_lut_T], _logical_T_295) node _logical_T_297 = bits(_logical_T_296, 0, 0) node _logical_T_298 = cat(_logical_T_14, _logical_T_142) node _logical_T_299 = dshr(_lut_WIRE[_lut_T], _logical_T_298) node _logical_T_300 = bits(_logical_T_299, 0, 0) node _logical_T_301 = cat(_logical_T_15, _logical_T_143) node _logical_T_302 = dshr(_lut_WIRE[_lut_T], _logical_T_301) node _logical_T_303 = bits(_logical_T_302, 0, 0) node _logical_T_304 = cat(_logical_T_16, _logical_T_144) node _logical_T_305 = dshr(_lut_WIRE[_lut_T], _logical_T_304) node _logical_T_306 = bits(_logical_T_305, 0, 0) node _logical_T_307 = cat(_logical_T_17, _logical_T_145) node _logical_T_308 = dshr(_lut_WIRE[_lut_T], _logical_T_307) node _logical_T_309 = bits(_logical_T_308, 0, 0) node _logical_T_310 = cat(_logical_T_18, _logical_T_146) node _logical_T_311 = dshr(_lut_WIRE[_lut_T], _logical_T_310) node _logical_T_312 = bits(_logical_T_311, 0, 0) node _logical_T_313 = cat(_logical_T_19, _logical_T_147) node _logical_T_314 = dshr(_lut_WIRE[_lut_T], _logical_T_313) node _logical_T_315 = bits(_logical_T_314, 0, 0) node _logical_T_316 = cat(_logical_T_20, _logical_T_148) node _logical_T_317 = dshr(_lut_WIRE[_lut_T], _logical_T_316) node _logical_T_318 = bits(_logical_T_317, 0, 0) node _logical_T_319 = cat(_logical_T_21, _logical_T_149) node _logical_T_320 = dshr(_lut_WIRE[_lut_T], _logical_T_319) node _logical_T_321 = bits(_logical_T_320, 0, 0) node _logical_T_322 = cat(_logical_T_22, _logical_T_150) node _logical_T_323 = dshr(_lut_WIRE[_lut_T], _logical_T_322) node _logical_T_324 = bits(_logical_T_323, 0, 0) node _logical_T_325 = cat(_logical_T_23, _logical_T_151) node _logical_T_326 = dshr(_lut_WIRE[_lut_T], _logical_T_325) node _logical_T_327 = bits(_logical_T_326, 0, 0) node _logical_T_328 = cat(_logical_T_24, _logical_T_152) node _logical_T_329 = dshr(_lut_WIRE[_lut_T], _logical_T_328) node _logical_T_330 = bits(_logical_T_329, 0, 0) node _logical_T_331 = cat(_logical_T_25, _logical_T_153) node _logical_T_332 = dshr(_lut_WIRE[_lut_T], _logical_T_331) node _logical_T_333 = bits(_logical_T_332, 0, 0) node _logical_T_334 = cat(_logical_T_26, _logical_T_154) node _logical_T_335 = dshr(_lut_WIRE[_lut_T], _logical_T_334) node _logical_T_336 = bits(_logical_T_335, 0, 0) node _logical_T_337 = cat(_logical_T_27, _logical_T_155) node _logical_T_338 = dshr(_lut_WIRE[_lut_T], _logical_T_337) node _logical_T_339 = bits(_logical_T_338, 0, 0) node _logical_T_340 = cat(_logical_T_28, _logical_T_156) node _logical_T_341 = dshr(_lut_WIRE[_lut_T], _logical_T_340) node _logical_T_342 = bits(_logical_T_341, 0, 0) node _logical_T_343 = cat(_logical_T_29, _logical_T_157) node _logical_T_344 = dshr(_lut_WIRE[_lut_T], _logical_T_343) node _logical_T_345 = bits(_logical_T_344, 0, 0) node _logical_T_346 = cat(_logical_T_30, _logical_T_158) node _logical_T_347 = dshr(_lut_WIRE[_lut_T], _logical_T_346) node _logical_T_348 = bits(_logical_T_347, 0, 0) node _logical_T_349 = cat(_logical_T_31, _logical_T_159) node _logical_T_350 = dshr(_lut_WIRE[_lut_T], _logical_T_349) node _logical_T_351 = bits(_logical_T_350, 0, 0) node _logical_T_352 = cat(_logical_T_32, _logical_T_160) node _logical_T_353 = dshr(_lut_WIRE[_lut_T], _logical_T_352) node _logical_T_354 = bits(_logical_T_353, 0, 0) node _logical_T_355 = cat(_logical_T_33, _logical_T_161) node _logical_T_356 = dshr(_lut_WIRE[_lut_T], _logical_T_355) node _logical_T_357 = bits(_logical_T_356, 0, 0) node _logical_T_358 = cat(_logical_T_34, _logical_T_162) node _logical_T_359 = dshr(_lut_WIRE[_lut_T], _logical_T_358) node _logical_T_360 = bits(_logical_T_359, 0, 0) node _logical_T_361 = cat(_logical_T_35, _logical_T_163) node _logical_T_362 = dshr(_lut_WIRE[_lut_T], _logical_T_361) node _logical_T_363 = bits(_logical_T_362, 0, 0) node _logical_T_364 = cat(_logical_T_36, _logical_T_164) node _logical_T_365 = dshr(_lut_WIRE[_lut_T], _logical_T_364) node _logical_T_366 = bits(_logical_T_365, 0, 0) node _logical_T_367 = cat(_logical_T_37, _logical_T_165) node _logical_T_368 = dshr(_lut_WIRE[_lut_T], _logical_T_367) node _logical_T_369 = bits(_logical_T_368, 0, 0) node _logical_T_370 = cat(_logical_T_38, _logical_T_166) node _logical_T_371 = dshr(_lut_WIRE[_lut_T], _logical_T_370) node _logical_T_372 = bits(_logical_T_371, 0, 0) node _logical_T_373 = cat(_logical_T_39, _logical_T_167) node _logical_T_374 = dshr(_lut_WIRE[_lut_T], _logical_T_373) node _logical_T_375 = bits(_logical_T_374, 0, 0) node _logical_T_376 = cat(_logical_T_40, _logical_T_168) node _logical_T_377 = dshr(_lut_WIRE[_lut_T], _logical_T_376) node _logical_T_378 = bits(_logical_T_377, 0, 0) node _logical_T_379 = cat(_logical_T_41, _logical_T_169) node _logical_T_380 = dshr(_lut_WIRE[_lut_T], _logical_T_379) node _logical_T_381 = bits(_logical_T_380, 0, 0) node _logical_T_382 = cat(_logical_T_42, _logical_T_170) node _logical_T_383 = dshr(_lut_WIRE[_lut_T], _logical_T_382) node _logical_T_384 = bits(_logical_T_383, 0, 0) node _logical_T_385 = cat(_logical_T_43, _logical_T_171) node _logical_T_386 = dshr(_lut_WIRE[_lut_T], _logical_T_385) node _logical_T_387 = bits(_logical_T_386, 0, 0) node _logical_T_388 = cat(_logical_T_44, _logical_T_172) node _logical_T_389 = dshr(_lut_WIRE[_lut_T], _logical_T_388) node _logical_T_390 = bits(_logical_T_389, 0, 0) node _logical_T_391 = cat(_logical_T_45, _logical_T_173) node _logical_T_392 = dshr(_lut_WIRE[_lut_T], _logical_T_391) node _logical_T_393 = bits(_logical_T_392, 0, 0) node _logical_T_394 = cat(_logical_T_46, _logical_T_174) node _logical_T_395 = dshr(_lut_WIRE[_lut_T], _logical_T_394) node _logical_T_396 = bits(_logical_T_395, 0, 0) node _logical_T_397 = cat(_logical_T_47, _logical_T_175) node _logical_T_398 = dshr(_lut_WIRE[_lut_T], _logical_T_397) node _logical_T_399 = bits(_logical_T_398, 0, 0) node _logical_T_400 = cat(_logical_T_48, _logical_T_176) node _logical_T_401 = dshr(_lut_WIRE[_lut_T], _logical_T_400) node _logical_T_402 = bits(_logical_T_401, 0, 0) node _logical_T_403 = cat(_logical_T_49, _logical_T_177) node _logical_T_404 = dshr(_lut_WIRE[_lut_T], _logical_T_403) node _logical_T_405 = bits(_logical_T_404, 0, 0) node _logical_T_406 = cat(_logical_T_50, _logical_T_178) node _logical_T_407 = dshr(_lut_WIRE[_lut_T], _logical_T_406) node _logical_T_408 = bits(_logical_T_407, 0, 0) node _logical_T_409 = cat(_logical_T_51, _logical_T_179) node _logical_T_410 = dshr(_lut_WIRE[_lut_T], _logical_T_409) node _logical_T_411 = bits(_logical_T_410, 0, 0) node _logical_T_412 = cat(_logical_T_52, _logical_T_180) node _logical_T_413 = dshr(_lut_WIRE[_lut_T], _logical_T_412) node _logical_T_414 = bits(_logical_T_413, 0, 0) node _logical_T_415 = cat(_logical_T_53, _logical_T_181) node _logical_T_416 = dshr(_lut_WIRE[_lut_T], _logical_T_415) node _logical_T_417 = bits(_logical_T_416, 0, 0) node _logical_T_418 = cat(_logical_T_54, _logical_T_182) node _logical_T_419 = dshr(_lut_WIRE[_lut_T], _logical_T_418) node _logical_T_420 = bits(_logical_T_419, 0, 0) node _logical_T_421 = cat(_logical_T_55, _logical_T_183) node _logical_T_422 = dshr(_lut_WIRE[_lut_T], _logical_T_421) node _logical_T_423 = bits(_logical_T_422, 0, 0) node _logical_T_424 = cat(_logical_T_56, _logical_T_184) node _logical_T_425 = dshr(_lut_WIRE[_lut_T], _logical_T_424) node _logical_T_426 = bits(_logical_T_425, 0, 0) node _logical_T_427 = cat(_logical_T_57, _logical_T_185) node _logical_T_428 = dshr(_lut_WIRE[_lut_T], _logical_T_427) node _logical_T_429 = bits(_logical_T_428, 0, 0) node _logical_T_430 = cat(_logical_T_58, _logical_T_186) node _logical_T_431 = dshr(_lut_WIRE[_lut_T], _logical_T_430) node _logical_T_432 = bits(_logical_T_431, 0, 0) node _logical_T_433 = cat(_logical_T_59, _logical_T_187) node _logical_T_434 = dshr(_lut_WIRE[_lut_T], _logical_T_433) node _logical_T_435 = bits(_logical_T_434, 0, 0) node _logical_T_436 = cat(_logical_T_60, _logical_T_188) node _logical_T_437 = dshr(_lut_WIRE[_lut_T], _logical_T_436) node _logical_T_438 = bits(_logical_T_437, 0, 0) node _logical_T_439 = cat(_logical_T_61, _logical_T_189) node _logical_T_440 = dshr(_lut_WIRE[_lut_T], _logical_T_439) node _logical_T_441 = bits(_logical_T_440, 0, 0) node _logical_T_442 = cat(_logical_T_62, _logical_T_190) node _logical_T_443 = dshr(_lut_WIRE[_lut_T], _logical_T_442) node _logical_T_444 = bits(_logical_T_443, 0, 0) node _logical_T_445 = cat(_logical_T_63, _logical_T_191) node _logical_T_446 = dshr(_lut_WIRE[_lut_T], _logical_T_445) node _logical_T_447 = bits(_logical_T_446, 0, 0) node _logical_T_448 = cat(_logical_T_64, _logical_T_192) node _logical_T_449 = dshr(_lut_WIRE[_lut_T], _logical_T_448) node _logical_T_450 = bits(_logical_T_449, 0, 0) node _logical_T_451 = cat(_logical_T_65, _logical_T_193) node _logical_T_452 = dshr(_lut_WIRE[_lut_T], _logical_T_451) node _logical_T_453 = bits(_logical_T_452, 0, 0) node _logical_T_454 = cat(_logical_T_66, _logical_T_194) node _logical_T_455 = dshr(_lut_WIRE[_lut_T], _logical_T_454) node _logical_T_456 = bits(_logical_T_455, 0, 0) node _logical_T_457 = cat(_logical_T_67, _logical_T_195) node _logical_T_458 = dshr(_lut_WIRE[_lut_T], _logical_T_457) node _logical_T_459 = bits(_logical_T_458, 0, 0) node _logical_T_460 = cat(_logical_T_68, _logical_T_196) node _logical_T_461 = dshr(_lut_WIRE[_lut_T], _logical_T_460) node _logical_T_462 = bits(_logical_T_461, 0, 0) node _logical_T_463 = cat(_logical_T_69, _logical_T_197) node _logical_T_464 = dshr(_lut_WIRE[_lut_T], _logical_T_463) node _logical_T_465 = bits(_logical_T_464, 0, 0) node _logical_T_466 = cat(_logical_T_70, _logical_T_198) node _logical_T_467 = dshr(_lut_WIRE[_lut_T], _logical_T_466) node _logical_T_468 = bits(_logical_T_467, 0, 0) node _logical_T_469 = cat(_logical_T_71, _logical_T_199) node _logical_T_470 = dshr(_lut_WIRE[_lut_T], _logical_T_469) node _logical_T_471 = bits(_logical_T_470, 0, 0) node _logical_T_472 = cat(_logical_T_72, _logical_T_200) node _logical_T_473 = dshr(_lut_WIRE[_lut_T], _logical_T_472) node _logical_T_474 = bits(_logical_T_473, 0, 0) node _logical_T_475 = cat(_logical_T_73, _logical_T_201) node _logical_T_476 = dshr(_lut_WIRE[_lut_T], _logical_T_475) node _logical_T_477 = bits(_logical_T_476, 0, 0) node _logical_T_478 = cat(_logical_T_74, _logical_T_202) node _logical_T_479 = dshr(_lut_WIRE[_lut_T], _logical_T_478) node _logical_T_480 = bits(_logical_T_479, 0, 0) node _logical_T_481 = cat(_logical_T_75, _logical_T_203) node _logical_T_482 = dshr(_lut_WIRE[_lut_T], _logical_T_481) node _logical_T_483 = bits(_logical_T_482, 0, 0) node _logical_T_484 = cat(_logical_T_76, _logical_T_204) node _logical_T_485 = dshr(_lut_WIRE[_lut_T], _logical_T_484) node _logical_T_486 = bits(_logical_T_485, 0, 0) node _logical_T_487 = cat(_logical_T_77, _logical_T_205) node _logical_T_488 = dshr(_lut_WIRE[_lut_T], _logical_T_487) node _logical_T_489 = bits(_logical_T_488, 0, 0) node _logical_T_490 = cat(_logical_T_78, _logical_T_206) node _logical_T_491 = dshr(_lut_WIRE[_lut_T], _logical_T_490) node _logical_T_492 = bits(_logical_T_491, 0, 0) node _logical_T_493 = cat(_logical_T_79, _logical_T_207) node _logical_T_494 = dshr(_lut_WIRE[_lut_T], _logical_T_493) node _logical_T_495 = bits(_logical_T_494, 0, 0) node _logical_T_496 = cat(_logical_T_80, _logical_T_208) node _logical_T_497 = dshr(_lut_WIRE[_lut_T], _logical_T_496) node _logical_T_498 = bits(_logical_T_497, 0, 0) node _logical_T_499 = cat(_logical_T_81, _logical_T_209) node _logical_T_500 = dshr(_lut_WIRE[_lut_T], _logical_T_499) node _logical_T_501 = bits(_logical_T_500, 0, 0) node _logical_T_502 = cat(_logical_T_82, _logical_T_210) node _logical_T_503 = dshr(_lut_WIRE[_lut_T], _logical_T_502) node _logical_T_504 = bits(_logical_T_503, 0, 0) node _logical_T_505 = cat(_logical_T_83, _logical_T_211) node _logical_T_506 = dshr(_lut_WIRE[_lut_T], _logical_T_505) node _logical_T_507 = bits(_logical_T_506, 0, 0) node _logical_T_508 = cat(_logical_T_84, _logical_T_212) node _logical_T_509 = dshr(_lut_WIRE[_lut_T], _logical_T_508) node _logical_T_510 = bits(_logical_T_509, 0, 0) node _logical_T_511 = cat(_logical_T_85, _logical_T_213) node _logical_T_512 = dshr(_lut_WIRE[_lut_T], _logical_T_511) node _logical_T_513 = bits(_logical_T_512, 0, 0) node _logical_T_514 = cat(_logical_T_86, _logical_T_214) node _logical_T_515 = dshr(_lut_WIRE[_lut_T], _logical_T_514) node _logical_T_516 = bits(_logical_T_515, 0, 0) node _logical_T_517 = cat(_logical_T_87, _logical_T_215) node _logical_T_518 = dshr(_lut_WIRE[_lut_T], _logical_T_517) node _logical_T_519 = bits(_logical_T_518, 0, 0) node _logical_T_520 = cat(_logical_T_88, _logical_T_216) node _logical_T_521 = dshr(_lut_WIRE[_lut_T], _logical_T_520) node _logical_T_522 = bits(_logical_T_521, 0, 0) node _logical_T_523 = cat(_logical_T_89, _logical_T_217) node _logical_T_524 = dshr(_lut_WIRE[_lut_T], _logical_T_523) node _logical_T_525 = bits(_logical_T_524, 0, 0) node _logical_T_526 = cat(_logical_T_90, _logical_T_218) node _logical_T_527 = dshr(_lut_WIRE[_lut_T], _logical_T_526) node _logical_T_528 = bits(_logical_T_527, 0, 0) node _logical_T_529 = cat(_logical_T_91, _logical_T_219) node _logical_T_530 = dshr(_lut_WIRE[_lut_T], _logical_T_529) node _logical_T_531 = bits(_logical_T_530, 0, 0) node _logical_T_532 = cat(_logical_T_92, _logical_T_220) node _logical_T_533 = dshr(_lut_WIRE[_lut_T], _logical_T_532) node _logical_T_534 = bits(_logical_T_533, 0, 0) node _logical_T_535 = cat(_logical_T_93, _logical_T_221) node _logical_T_536 = dshr(_lut_WIRE[_lut_T], _logical_T_535) node _logical_T_537 = bits(_logical_T_536, 0, 0) node _logical_T_538 = cat(_logical_T_94, _logical_T_222) node _logical_T_539 = dshr(_lut_WIRE[_lut_T], _logical_T_538) node _logical_T_540 = bits(_logical_T_539, 0, 0) node _logical_T_541 = cat(_logical_T_95, _logical_T_223) node _logical_T_542 = dshr(_lut_WIRE[_lut_T], _logical_T_541) node _logical_T_543 = bits(_logical_T_542, 0, 0) node _logical_T_544 = cat(_logical_T_96, _logical_T_224) node _logical_T_545 = dshr(_lut_WIRE[_lut_T], _logical_T_544) node _logical_T_546 = bits(_logical_T_545, 0, 0) node _logical_T_547 = cat(_logical_T_97, _logical_T_225) node _logical_T_548 = dshr(_lut_WIRE[_lut_T], _logical_T_547) node _logical_T_549 = bits(_logical_T_548, 0, 0) node _logical_T_550 = cat(_logical_T_98, _logical_T_226) node _logical_T_551 = dshr(_lut_WIRE[_lut_T], _logical_T_550) node _logical_T_552 = bits(_logical_T_551, 0, 0) node _logical_T_553 = cat(_logical_T_99, _logical_T_227) node _logical_T_554 = dshr(_lut_WIRE[_lut_T], _logical_T_553) node _logical_T_555 = bits(_logical_T_554, 0, 0) node _logical_T_556 = cat(_logical_T_100, _logical_T_228) node _logical_T_557 = dshr(_lut_WIRE[_lut_T], _logical_T_556) node _logical_T_558 = bits(_logical_T_557, 0, 0) node _logical_T_559 = cat(_logical_T_101, _logical_T_229) node _logical_T_560 = dshr(_lut_WIRE[_lut_T], _logical_T_559) node _logical_T_561 = bits(_logical_T_560, 0, 0) node _logical_T_562 = cat(_logical_T_102, _logical_T_230) node _logical_T_563 = dshr(_lut_WIRE[_lut_T], _logical_T_562) node _logical_T_564 = bits(_logical_T_563, 0, 0) node _logical_T_565 = cat(_logical_T_103, _logical_T_231) node _logical_T_566 = dshr(_lut_WIRE[_lut_T], _logical_T_565) node _logical_T_567 = bits(_logical_T_566, 0, 0) node _logical_T_568 = cat(_logical_T_104, _logical_T_232) node _logical_T_569 = dshr(_lut_WIRE[_lut_T], _logical_T_568) node _logical_T_570 = bits(_logical_T_569, 0, 0) node _logical_T_571 = cat(_logical_T_105, _logical_T_233) node _logical_T_572 = dshr(_lut_WIRE[_lut_T], _logical_T_571) node _logical_T_573 = bits(_logical_T_572, 0, 0) node _logical_T_574 = cat(_logical_T_106, _logical_T_234) node _logical_T_575 = dshr(_lut_WIRE[_lut_T], _logical_T_574) node _logical_T_576 = bits(_logical_T_575, 0, 0) node _logical_T_577 = cat(_logical_T_107, _logical_T_235) node _logical_T_578 = dshr(_lut_WIRE[_lut_T], _logical_T_577) node _logical_T_579 = bits(_logical_T_578, 0, 0) node _logical_T_580 = cat(_logical_T_108, _logical_T_236) node _logical_T_581 = dshr(_lut_WIRE[_lut_T], _logical_T_580) node _logical_T_582 = bits(_logical_T_581, 0, 0) node _logical_T_583 = cat(_logical_T_109, _logical_T_237) node _logical_T_584 = dshr(_lut_WIRE[_lut_T], _logical_T_583) node _logical_T_585 = bits(_logical_T_584, 0, 0) node _logical_T_586 = cat(_logical_T_110, _logical_T_238) node _logical_T_587 = dshr(_lut_WIRE[_lut_T], _logical_T_586) node _logical_T_588 = bits(_logical_T_587, 0, 0) node _logical_T_589 = cat(_logical_T_111, _logical_T_239) node _logical_T_590 = dshr(_lut_WIRE[_lut_T], _logical_T_589) node _logical_T_591 = bits(_logical_T_590, 0, 0) node _logical_T_592 = cat(_logical_T_112, _logical_T_240) node _logical_T_593 = dshr(_lut_WIRE[_lut_T], _logical_T_592) node _logical_T_594 = bits(_logical_T_593, 0, 0) node _logical_T_595 = cat(_logical_T_113, _logical_T_241) node _logical_T_596 = dshr(_lut_WIRE[_lut_T], _logical_T_595) node _logical_T_597 = bits(_logical_T_596, 0, 0) node _logical_T_598 = cat(_logical_T_114, _logical_T_242) node _logical_T_599 = dshr(_lut_WIRE[_lut_T], _logical_T_598) node _logical_T_600 = bits(_logical_T_599, 0, 0) node _logical_T_601 = cat(_logical_T_115, _logical_T_243) node _logical_T_602 = dshr(_lut_WIRE[_lut_T], _logical_T_601) node _logical_T_603 = bits(_logical_T_602, 0, 0) node _logical_T_604 = cat(_logical_T_116, _logical_T_244) node _logical_T_605 = dshr(_lut_WIRE[_lut_T], _logical_T_604) node _logical_T_606 = bits(_logical_T_605, 0, 0) node _logical_T_607 = cat(_logical_T_117, _logical_T_245) node _logical_T_608 = dshr(_lut_WIRE[_lut_T], _logical_T_607) node _logical_T_609 = bits(_logical_T_608, 0, 0) node _logical_T_610 = cat(_logical_T_118, _logical_T_246) node _logical_T_611 = dshr(_lut_WIRE[_lut_T], _logical_T_610) node _logical_T_612 = bits(_logical_T_611, 0, 0) node _logical_T_613 = cat(_logical_T_119, _logical_T_247) node _logical_T_614 = dshr(_lut_WIRE[_lut_T], _logical_T_613) node _logical_T_615 = bits(_logical_T_614, 0, 0) node _logical_T_616 = cat(_logical_T_120, _logical_T_248) node _logical_T_617 = dshr(_lut_WIRE[_lut_T], _logical_T_616) node _logical_T_618 = bits(_logical_T_617, 0, 0) node _logical_T_619 = cat(_logical_T_121, _logical_T_249) node _logical_T_620 = dshr(_lut_WIRE[_lut_T], _logical_T_619) node _logical_T_621 = bits(_logical_T_620, 0, 0) node _logical_T_622 = cat(_logical_T_122, _logical_T_250) node _logical_T_623 = dshr(_lut_WIRE[_lut_T], _logical_T_622) node _logical_T_624 = bits(_logical_T_623, 0, 0) node _logical_T_625 = cat(_logical_T_123, _logical_T_251) node _logical_T_626 = dshr(_lut_WIRE[_lut_T], _logical_T_625) node _logical_T_627 = bits(_logical_T_626, 0, 0) node _logical_T_628 = cat(_logical_T_124, _logical_T_252) node _logical_T_629 = dshr(_lut_WIRE[_lut_T], _logical_T_628) node _logical_T_630 = bits(_logical_T_629, 0, 0) node _logical_T_631 = cat(_logical_T_125, _logical_T_253) node _logical_T_632 = dshr(_lut_WIRE[_lut_T], _logical_T_631) node _logical_T_633 = bits(_logical_T_632, 0, 0) node _logical_T_634 = cat(_logical_T_126, _logical_T_254) node _logical_T_635 = dshr(_lut_WIRE[_lut_T], _logical_T_634) node _logical_T_636 = bits(_logical_T_635, 0, 0) node _logical_T_637 = cat(_logical_T_127, _logical_T_255) node _logical_T_638 = dshr(_lut_WIRE[_lut_T], _logical_T_637) node _logical_T_639 = bits(_logical_T_638, 0, 0) node logical_lo_lo_lo_lo_lo_lo = cat(_logical_T_261, _logical_T_258) node logical_lo_lo_lo_lo_lo_hi = cat(_logical_T_267, _logical_T_264) node logical_lo_lo_lo_lo_lo = cat(logical_lo_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo_lo) node logical_lo_lo_lo_lo_hi_lo = cat(_logical_T_273, _logical_T_270) node logical_lo_lo_lo_lo_hi_hi = cat(_logical_T_279, _logical_T_276) node logical_lo_lo_lo_lo_hi = cat(logical_lo_lo_lo_lo_hi_hi, logical_lo_lo_lo_lo_hi_lo) node logical_lo_lo_lo_lo = cat(logical_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo) node logical_lo_lo_lo_hi_lo_lo = cat(_logical_T_285, _logical_T_282) node logical_lo_lo_lo_hi_lo_hi = cat(_logical_T_291, _logical_T_288) node logical_lo_lo_lo_hi_lo = cat(logical_lo_lo_lo_hi_lo_hi, logical_lo_lo_lo_hi_lo_lo) node logical_lo_lo_lo_hi_hi_lo = cat(_logical_T_297, _logical_T_294) node logical_lo_lo_lo_hi_hi_hi = cat(_logical_T_303, _logical_T_300) node logical_lo_lo_lo_hi_hi = cat(logical_lo_lo_lo_hi_hi_hi, logical_lo_lo_lo_hi_hi_lo) node logical_lo_lo_lo_hi = cat(logical_lo_lo_lo_hi_hi, logical_lo_lo_lo_hi_lo) node logical_lo_lo_lo = cat(logical_lo_lo_lo_hi, logical_lo_lo_lo_lo) node logical_lo_lo_hi_lo_lo_lo = cat(_logical_T_309, _logical_T_306) node logical_lo_lo_hi_lo_lo_hi = cat(_logical_T_315, _logical_T_312) node logical_lo_lo_hi_lo_lo = cat(logical_lo_lo_hi_lo_lo_hi, logical_lo_lo_hi_lo_lo_lo) node logical_lo_lo_hi_lo_hi_lo = cat(_logical_T_321, _logical_T_318) node logical_lo_lo_hi_lo_hi_hi = cat(_logical_T_327, _logical_T_324) node logical_lo_lo_hi_lo_hi = cat(logical_lo_lo_hi_lo_hi_hi, logical_lo_lo_hi_lo_hi_lo) node logical_lo_lo_hi_lo = cat(logical_lo_lo_hi_lo_hi, logical_lo_lo_hi_lo_lo) node logical_lo_lo_hi_hi_lo_lo = cat(_logical_T_333, _logical_T_330) node logical_lo_lo_hi_hi_lo_hi = cat(_logical_T_339, _logical_T_336) node logical_lo_lo_hi_hi_lo = cat(logical_lo_lo_hi_hi_lo_hi, logical_lo_lo_hi_hi_lo_lo) node logical_lo_lo_hi_hi_hi_lo = cat(_logical_T_345, _logical_T_342) node logical_lo_lo_hi_hi_hi_hi = cat(_logical_T_351, _logical_T_348) node logical_lo_lo_hi_hi_hi = cat(logical_lo_lo_hi_hi_hi_hi, logical_lo_lo_hi_hi_hi_lo) node logical_lo_lo_hi_hi = cat(logical_lo_lo_hi_hi_hi, logical_lo_lo_hi_hi_lo) node logical_lo_lo_hi = cat(logical_lo_lo_hi_hi, logical_lo_lo_hi_lo) node logical_lo_lo = cat(logical_lo_lo_hi, logical_lo_lo_lo) node logical_lo_hi_lo_lo_lo_lo = cat(_logical_T_357, _logical_T_354) node logical_lo_hi_lo_lo_lo_hi = cat(_logical_T_363, _logical_T_360) node logical_lo_hi_lo_lo_lo = cat(logical_lo_hi_lo_lo_lo_hi, logical_lo_hi_lo_lo_lo_lo) node logical_lo_hi_lo_lo_hi_lo = cat(_logical_T_369, _logical_T_366) node logical_lo_hi_lo_lo_hi_hi = cat(_logical_T_375, _logical_T_372) node logical_lo_hi_lo_lo_hi = cat(logical_lo_hi_lo_lo_hi_hi, logical_lo_hi_lo_lo_hi_lo) node logical_lo_hi_lo_lo = cat(logical_lo_hi_lo_lo_hi, logical_lo_hi_lo_lo_lo) node logical_lo_hi_lo_hi_lo_lo = cat(_logical_T_381, _logical_T_378) node logical_lo_hi_lo_hi_lo_hi = cat(_logical_T_387, _logical_T_384) node logical_lo_hi_lo_hi_lo = cat(logical_lo_hi_lo_hi_lo_hi, logical_lo_hi_lo_hi_lo_lo) node logical_lo_hi_lo_hi_hi_lo = cat(_logical_T_393, _logical_T_390) node logical_lo_hi_lo_hi_hi_hi = cat(_logical_T_399, _logical_T_396) node logical_lo_hi_lo_hi_hi = cat(logical_lo_hi_lo_hi_hi_hi, logical_lo_hi_lo_hi_hi_lo) node logical_lo_hi_lo_hi = cat(logical_lo_hi_lo_hi_hi, logical_lo_hi_lo_hi_lo) node logical_lo_hi_lo = cat(logical_lo_hi_lo_hi, logical_lo_hi_lo_lo) node logical_lo_hi_hi_lo_lo_lo = cat(_logical_T_405, _logical_T_402) node logical_lo_hi_hi_lo_lo_hi = cat(_logical_T_411, _logical_T_408) node logical_lo_hi_hi_lo_lo = cat(logical_lo_hi_hi_lo_lo_hi, logical_lo_hi_hi_lo_lo_lo) node logical_lo_hi_hi_lo_hi_lo = cat(_logical_T_417, _logical_T_414) node logical_lo_hi_hi_lo_hi_hi = cat(_logical_T_423, _logical_T_420) node logical_lo_hi_hi_lo_hi = cat(logical_lo_hi_hi_lo_hi_hi, logical_lo_hi_hi_lo_hi_lo) node logical_lo_hi_hi_lo = cat(logical_lo_hi_hi_lo_hi, logical_lo_hi_hi_lo_lo) node logical_lo_hi_hi_hi_lo_lo = cat(_logical_T_429, _logical_T_426) node logical_lo_hi_hi_hi_lo_hi = cat(_logical_T_435, _logical_T_432) node logical_lo_hi_hi_hi_lo = cat(logical_lo_hi_hi_hi_lo_hi, logical_lo_hi_hi_hi_lo_lo) node logical_lo_hi_hi_hi_hi_lo = cat(_logical_T_441, _logical_T_438) node logical_lo_hi_hi_hi_hi_hi = cat(_logical_T_447, _logical_T_444) node logical_lo_hi_hi_hi_hi = cat(logical_lo_hi_hi_hi_hi_hi, logical_lo_hi_hi_hi_hi_lo) node logical_lo_hi_hi_hi = cat(logical_lo_hi_hi_hi_hi, logical_lo_hi_hi_hi_lo) node logical_lo_hi_hi = cat(logical_lo_hi_hi_hi, logical_lo_hi_hi_lo) node logical_lo_hi = cat(logical_lo_hi_hi, logical_lo_hi_lo) node logical_lo = cat(logical_lo_hi, logical_lo_lo) node logical_hi_lo_lo_lo_lo_lo = cat(_logical_T_453, _logical_T_450) node logical_hi_lo_lo_lo_lo_hi = cat(_logical_T_459, _logical_T_456) node logical_hi_lo_lo_lo_lo = cat(logical_hi_lo_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo_lo) node logical_hi_lo_lo_lo_hi_lo = cat(_logical_T_465, _logical_T_462) node logical_hi_lo_lo_lo_hi_hi = cat(_logical_T_471, _logical_T_468) node logical_hi_lo_lo_lo_hi = cat(logical_hi_lo_lo_lo_hi_hi, logical_hi_lo_lo_lo_hi_lo) node logical_hi_lo_lo_lo = cat(logical_hi_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo) node logical_hi_lo_lo_hi_lo_lo = cat(_logical_T_477, _logical_T_474) node logical_hi_lo_lo_hi_lo_hi = cat(_logical_T_483, _logical_T_480) node logical_hi_lo_lo_hi_lo = cat(logical_hi_lo_lo_hi_lo_hi, logical_hi_lo_lo_hi_lo_lo) node logical_hi_lo_lo_hi_hi_lo = cat(_logical_T_489, _logical_T_486) node logical_hi_lo_lo_hi_hi_hi = cat(_logical_T_495, _logical_T_492) node logical_hi_lo_lo_hi_hi = cat(logical_hi_lo_lo_hi_hi_hi, logical_hi_lo_lo_hi_hi_lo) node logical_hi_lo_lo_hi = cat(logical_hi_lo_lo_hi_hi, logical_hi_lo_lo_hi_lo) node logical_hi_lo_lo = cat(logical_hi_lo_lo_hi, logical_hi_lo_lo_lo) node logical_hi_lo_hi_lo_lo_lo = cat(_logical_T_501, _logical_T_498) node logical_hi_lo_hi_lo_lo_hi = cat(_logical_T_507, _logical_T_504) node logical_hi_lo_hi_lo_lo = cat(logical_hi_lo_hi_lo_lo_hi, logical_hi_lo_hi_lo_lo_lo) node logical_hi_lo_hi_lo_hi_lo = cat(_logical_T_513, _logical_T_510) node logical_hi_lo_hi_lo_hi_hi = cat(_logical_T_519, _logical_T_516) node logical_hi_lo_hi_lo_hi = cat(logical_hi_lo_hi_lo_hi_hi, logical_hi_lo_hi_lo_hi_lo) node logical_hi_lo_hi_lo = cat(logical_hi_lo_hi_lo_hi, logical_hi_lo_hi_lo_lo) node logical_hi_lo_hi_hi_lo_lo = cat(_logical_T_525, _logical_T_522) node logical_hi_lo_hi_hi_lo_hi = cat(_logical_T_531, _logical_T_528) node logical_hi_lo_hi_hi_lo = cat(logical_hi_lo_hi_hi_lo_hi, logical_hi_lo_hi_hi_lo_lo) node logical_hi_lo_hi_hi_hi_lo = cat(_logical_T_537, _logical_T_534) node logical_hi_lo_hi_hi_hi_hi = cat(_logical_T_543, _logical_T_540) node logical_hi_lo_hi_hi_hi = cat(logical_hi_lo_hi_hi_hi_hi, logical_hi_lo_hi_hi_hi_lo) node logical_hi_lo_hi_hi = cat(logical_hi_lo_hi_hi_hi, logical_hi_lo_hi_hi_lo) node logical_hi_lo_hi = cat(logical_hi_lo_hi_hi, logical_hi_lo_hi_lo) node logical_hi_lo = cat(logical_hi_lo_hi, logical_hi_lo_lo) node logical_hi_hi_lo_lo_lo_lo = cat(_logical_T_549, _logical_T_546) node logical_hi_hi_lo_lo_lo_hi = cat(_logical_T_555, _logical_T_552) node logical_hi_hi_lo_lo_lo = cat(logical_hi_hi_lo_lo_lo_hi, logical_hi_hi_lo_lo_lo_lo) node logical_hi_hi_lo_lo_hi_lo = cat(_logical_T_561, _logical_T_558) node logical_hi_hi_lo_lo_hi_hi = cat(_logical_T_567, _logical_T_564) node logical_hi_hi_lo_lo_hi = cat(logical_hi_hi_lo_lo_hi_hi, logical_hi_hi_lo_lo_hi_lo) node logical_hi_hi_lo_lo = cat(logical_hi_hi_lo_lo_hi, logical_hi_hi_lo_lo_lo) node logical_hi_hi_lo_hi_lo_lo = cat(_logical_T_573, _logical_T_570) node logical_hi_hi_lo_hi_lo_hi = cat(_logical_T_579, _logical_T_576) node logical_hi_hi_lo_hi_lo = cat(logical_hi_hi_lo_hi_lo_hi, logical_hi_hi_lo_hi_lo_lo) node logical_hi_hi_lo_hi_hi_lo = cat(_logical_T_585, _logical_T_582) node logical_hi_hi_lo_hi_hi_hi = cat(_logical_T_591, _logical_T_588) node logical_hi_hi_lo_hi_hi = cat(logical_hi_hi_lo_hi_hi_hi, logical_hi_hi_lo_hi_hi_lo) node logical_hi_hi_lo_hi = cat(logical_hi_hi_lo_hi_hi, logical_hi_hi_lo_hi_lo) node logical_hi_hi_lo = cat(logical_hi_hi_lo_hi, logical_hi_hi_lo_lo) node logical_hi_hi_hi_lo_lo_lo = cat(_logical_T_597, _logical_T_594) node logical_hi_hi_hi_lo_lo_hi = cat(_logical_T_603, _logical_T_600) node logical_hi_hi_hi_lo_lo = cat(logical_hi_hi_hi_lo_lo_hi, logical_hi_hi_hi_lo_lo_lo) node logical_hi_hi_hi_lo_hi_lo = cat(_logical_T_609, _logical_T_606) node logical_hi_hi_hi_lo_hi_hi = cat(_logical_T_615, _logical_T_612) node logical_hi_hi_hi_lo_hi = cat(logical_hi_hi_hi_lo_hi_hi, logical_hi_hi_hi_lo_hi_lo) node logical_hi_hi_hi_lo = cat(logical_hi_hi_hi_lo_hi, logical_hi_hi_hi_lo_lo) node logical_hi_hi_hi_hi_lo_lo = cat(_logical_T_621, _logical_T_618) node logical_hi_hi_hi_hi_lo_hi = cat(_logical_T_627, _logical_T_624) node logical_hi_hi_hi_hi_lo = cat(logical_hi_hi_hi_hi_lo_hi, logical_hi_hi_hi_hi_lo_lo) node logical_hi_hi_hi_hi_hi_lo = cat(_logical_T_633, _logical_T_630) node logical_hi_hi_hi_hi_hi_hi = cat(_logical_T_639, _logical_T_636) node logical_hi_hi_hi_hi_hi = cat(logical_hi_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_hi_lo) node logical_hi_hi_hi_hi = cat(logical_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_lo) node logical_hi_hi_hi = cat(logical_hi_hi_hi_hi, logical_hi_hi_hi_lo) node logical_hi_hi = cat(logical_hi_hi_hi, logical_hi_hi_lo) node logical_hi = cat(logical_hi_hi, logical_hi_lo) node logical = cat(logical_hi, logical_lo) node _select_T = mux(pick_a, UInt<1>(0h1), UInt<1>(0h0)) node _select_T_1 = mux(adder, UInt<2>(0h2), _select_T) wire _select_WIRE : UInt<2>[8] connect _select_WIRE[0], UInt<1>(0h1) connect _select_WIRE[1], UInt<1>(0h1) connect _select_WIRE[2], _select_T_1 connect _select_WIRE[3], UInt<2>(0h3) connect _select_WIRE[4], UInt<1>(0h0) connect _select_WIRE[5], UInt<1>(0h0) connect _select_WIRE[6], UInt<1>(0h0) connect _select_WIRE[7], UInt<1>(0h0) node select = mux(io.write, UInt<1>(0h1), _select_WIRE[io.a.opcode]) node _selects_T = bits(io.a.mask, 0, 0) node _selects_T_1 = bits(io.a.mask, 1, 1) node _selects_T_2 = bits(io.a.mask, 2, 2) node _selects_T_3 = bits(io.a.mask, 3, 3) node _selects_T_4 = bits(io.a.mask, 4, 4) node _selects_T_5 = bits(io.a.mask, 5, 5) node _selects_T_6 = bits(io.a.mask, 6, 6) node _selects_T_7 = bits(io.a.mask, 7, 7) node _selects_T_8 = bits(io.a.mask, 8, 8) node _selects_T_9 = bits(io.a.mask, 9, 9) node _selects_T_10 = bits(io.a.mask, 10, 10) node _selects_T_11 = bits(io.a.mask, 11, 11) node _selects_T_12 = bits(io.a.mask, 12, 12) node _selects_T_13 = bits(io.a.mask, 13, 13) node _selects_T_14 = bits(io.a.mask, 14, 14) node _selects_T_15 = bits(io.a.mask, 15, 15) node selects_0 = mux(_selects_T, select, UInt<1>(0h0)) node selects_1 = mux(_selects_T_1, select, UInt<1>(0h0)) node selects_2 = mux(_selects_T_2, select, UInt<1>(0h0)) node selects_3 = mux(_selects_T_3, select, UInt<1>(0h0)) node selects_4 = mux(_selects_T_4, select, UInt<1>(0h0)) node selects_5 = mux(_selects_T_5, select, UInt<1>(0h0)) node selects_6 = mux(_selects_T_6, select, UInt<1>(0h0)) node selects_7 = mux(_selects_T_7, select, UInt<1>(0h0)) node selects_8 = mux(_selects_T_8, select, UInt<1>(0h0)) node selects_9 = mux(_selects_T_9, select, UInt<1>(0h0)) node selects_10 = mux(_selects_T_10, select, UInt<1>(0h0)) node selects_11 = mux(_selects_T_11, select, UInt<1>(0h0)) node selects_12 = mux(_selects_T_12, select, UInt<1>(0h0)) node selects_13 = mux(_selects_T_13, select, UInt<1>(0h0)) node selects_14 = mux(_selects_T_14, select, UInt<1>(0h0)) node selects_15 = mux(_selects_T_15, select, UInt<1>(0h0)) node _io_data_out_T = bits(io.data_in, 7, 0) node _io_data_out_T_1 = bits(io.a.data, 7, 0) node _io_data_out_T_2 = bits(sum, 7, 0) node _io_data_out_T_3 = bits(logical, 7, 0) wire _io_data_out_WIRE : UInt<8>[4] connect _io_data_out_WIRE[0], _io_data_out_T connect _io_data_out_WIRE[1], _io_data_out_T_1 connect _io_data_out_WIRE[2], _io_data_out_T_2 connect _io_data_out_WIRE[3], _io_data_out_T_3 node _io_data_out_T_4 = bits(io.data_in, 15, 8) node _io_data_out_T_5 = bits(io.a.data, 15, 8) node _io_data_out_T_6 = bits(sum, 15, 8) node _io_data_out_T_7 = bits(logical, 15, 8) wire _io_data_out_WIRE_1 : UInt<8>[4] connect _io_data_out_WIRE_1[0], _io_data_out_T_4 connect _io_data_out_WIRE_1[1], _io_data_out_T_5 connect _io_data_out_WIRE_1[2], _io_data_out_T_6 connect _io_data_out_WIRE_1[3], _io_data_out_T_7 node _io_data_out_T_8 = bits(io.data_in, 23, 16) node _io_data_out_T_9 = bits(io.a.data, 23, 16) node _io_data_out_T_10 = bits(sum, 23, 16) node _io_data_out_T_11 = bits(logical, 23, 16) wire _io_data_out_WIRE_2 : UInt<8>[4] connect _io_data_out_WIRE_2[0], _io_data_out_T_8 connect _io_data_out_WIRE_2[1], _io_data_out_T_9 connect _io_data_out_WIRE_2[2], _io_data_out_T_10 connect _io_data_out_WIRE_2[3], _io_data_out_T_11 node _io_data_out_T_12 = bits(io.data_in, 31, 24) node _io_data_out_T_13 = bits(io.a.data, 31, 24) node _io_data_out_T_14 = bits(sum, 31, 24) node _io_data_out_T_15 = bits(logical, 31, 24) wire _io_data_out_WIRE_3 : UInt<8>[4] connect _io_data_out_WIRE_3[0], _io_data_out_T_12 connect _io_data_out_WIRE_3[1], _io_data_out_T_13 connect _io_data_out_WIRE_3[2], _io_data_out_T_14 connect _io_data_out_WIRE_3[3], _io_data_out_T_15 node _io_data_out_T_16 = bits(io.data_in, 39, 32) node _io_data_out_T_17 = bits(io.a.data, 39, 32) node _io_data_out_T_18 = bits(sum, 39, 32) node _io_data_out_T_19 = bits(logical, 39, 32) wire _io_data_out_WIRE_4 : UInt<8>[4] connect _io_data_out_WIRE_4[0], _io_data_out_T_16 connect _io_data_out_WIRE_4[1], _io_data_out_T_17 connect _io_data_out_WIRE_4[2], _io_data_out_T_18 connect _io_data_out_WIRE_4[3], _io_data_out_T_19 node _io_data_out_T_20 = bits(io.data_in, 47, 40) node _io_data_out_T_21 = bits(io.a.data, 47, 40) node _io_data_out_T_22 = bits(sum, 47, 40) node _io_data_out_T_23 = bits(logical, 47, 40) wire _io_data_out_WIRE_5 : UInt<8>[4] connect _io_data_out_WIRE_5[0], _io_data_out_T_20 connect _io_data_out_WIRE_5[1], _io_data_out_T_21 connect _io_data_out_WIRE_5[2], _io_data_out_T_22 connect _io_data_out_WIRE_5[3], _io_data_out_T_23 node _io_data_out_T_24 = bits(io.data_in, 55, 48) node _io_data_out_T_25 = bits(io.a.data, 55, 48) node _io_data_out_T_26 = bits(sum, 55, 48) node _io_data_out_T_27 = bits(logical, 55, 48) wire _io_data_out_WIRE_6 : UInt<8>[4] connect _io_data_out_WIRE_6[0], _io_data_out_T_24 connect _io_data_out_WIRE_6[1], _io_data_out_T_25 connect _io_data_out_WIRE_6[2], _io_data_out_T_26 connect _io_data_out_WIRE_6[3], _io_data_out_T_27 node _io_data_out_T_28 = bits(io.data_in, 63, 56) node _io_data_out_T_29 = bits(io.a.data, 63, 56) node _io_data_out_T_30 = bits(sum, 63, 56) node _io_data_out_T_31 = bits(logical, 63, 56) wire _io_data_out_WIRE_7 : UInt<8>[4] connect _io_data_out_WIRE_7[0], _io_data_out_T_28 connect _io_data_out_WIRE_7[1], _io_data_out_T_29 connect _io_data_out_WIRE_7[2], _io_data_out_T_30 connect _io_data_out_WIRE_7[3], _io_data_out_T_31 node _io_data_out_T_32 = bits(io.data_in, 71, 64) node _io_data_out_T_33 = bits(io.a.data, 71, 64) node _io_data_out_T_34 = bits(sum, 71, 64) node _io_data_out_T_35 = bits(logical, 71, 64) wire _io_data_out_WIRE_8 : UInt<8>[4] connect _io_data_out_WIRE_8[0], _io_data_out_T_32 connect _io_data_out_WIRE_8[1], _io_data_out_T_33 connect _io_data_out_WIRE_8[2], _io_data_out_T_34 connect _io_data_out_WIRE_8[3], _io_data_out_T_35 node _io_data_out_T_36 = bits(io.data_in, 79, 72) node _io_data_out_T_37 = bits(io.a.data, 79, 72) node _io_data_out_T_38 = bits(sum, 79, 72) node _io_data_out_T_39 = bits(logical, 79, 72) wire _io_data_out_WIRE_9 : UInt<8>[4] connect _io_data_out_WIRE_9[0], _io_data_out_T_36 connect _io_data_out_WIRE_9[1], _io_data_out_T_37 connect _io_data_out_WIRE_9[2], _io_data_out_T_38 connect _io_data_out_WIRE_9[3], _io_data_out_T_39 node _io_data_out_T_40 = bits(io.data_in, 87, 80) node _io_data_out_T_41 = bits(io.a.data, 87, 80) node _io_data_out_T_42 = bits(sum, 87, 80) node _io_data_out_T_43 = bits(logical, 87, 80) wire _io_data_out_WIRE_10 : UInt<8>[4] connect _io_data_out_WIRE_10[0], _io_data_out_T_40 connect _io_data_out_WIRE_10[1], _io_data_out_T_41 connect _io_data_out_WIRE_10[2], _io_data_out_T_42 connect _io_data_out_WIRE_10[3], _io_data_out_T_43 node _io_data_out_T_44 = bits(io.data_in, 95, 88) node _io_data_out_T_45 = bits(io.a.data, 95, 88) node _io_data_out_T_46 = bits(sum, 95, 88) node _io_data_out_T_47 = bits(logical, 95, 88) wire _io_data_out_WIRE_11 : UInt<8>[4] connect _io_data_out_WIRE_11[0], _io_data_out_T_44 connect _io_data_out_WIRE_11[1], _io_data_out_T_45 connect _io_data_out_WIRE_11[2], _io_data_out_T_46 connect _io_data_out_WIRE_11[3], _io_data_out_T_47 node _io_data_out_T_48 = bits(io.data_in, 103, 96) node _io_data_out_T_49 = bits(io.a.data, 103, 96) node _io_data_out_T_50 = bits(sum, 103, 96) node _io_data_out_T_51 = bits(logical, 103, 96) wire _io_data_out_WIRE_12 : UInt<8>[4] connect _io_data_out_WIRE_12[0], _io_data_out_T_48 connect _io_data_out_WIRE_12[1], _io_data_out_T_49 connect _io_data_out_WIRE_12[2], _io_data_out_T_50 connect _io_data_out_WIRE_12[3], _io_data_out_T_51 node _io_data_out_T_52 = bits(io.data_in, 111, 104) node _io_data_out_T_53 = bits(io.a.data, 111, 104) node _io_data_out_T_54 = bits(sum, 111, 104) node _io_data_out_T_55 = bits(logical, 111, 104) wire _io_data_out_WIRE_13 : UInt<8>[4] connect _io_data_out_WIRE_13[0], _io_data_out_T_52 connect _io_data_out_WIRE_13[1], _io_data_out_T_53 connect _io_data_out_WIRE_13[2], _io_data_out_T_54 connect _io_data_out_WIRE_13[3], _io_data_out_T_55 node _io_data_out_T_56 = bits(io.data_in, 119, 112) node _io_data_out_T_57 = bits(io.a.data, 119, 112) node _io_data_out_T_58 = bits(sum, 119, 112) node _io_data_out_T_59 = bits(logical, 119, 112) wire _io_data_out_WIRE_14 : UInt<8>[4] connect _io_data_out_WIRE_14[0], _io_data_out_T_56 connect _io_data_out_WIRE_14[1], _io_data_out_T_57 connect _io_data_out_WIRE_14[2], _io_data_out_T_58 connect _io_data_out_WIRE_14[3], _io_data_out_T_59 node _io_data_out_T_60 = bits(io.data_in, 127, 120) node _io_data_out_T_61 = bits(io.a.data, 127, 120) node _io_data_out_T_62 = bits(sum, 127, 120) node _io_data_out_T_63 = bits(logical, 127, 120) wire _io_data_out_WIRE_15 : UInt<8>[4] connect _io_data_out_WIRE_15[0], _io_data_out_T_60 connect _io_data_out_WIRE_15[1], _io_data_out_T_61 connect _io_data_out_WIRE_15[2], _io_data_out_T_62 connect _io_data_out_WIRE_15[3], _io_data_out_T_63 node io_data_out_lo_lo_lo = cat(_io_data_out_WIRE_1[selects_1], _io_data_out_WIRE[selects_0]) node io_data_out_lo_lo_hi = cat(_io_data_out_WIRE_3[selects_3], _io_data_out_WIRE_2[selects_2]) node io_data_out_lo_lo = cat(io_data_out_lo_lo_hi, io_data_out_lo_lo_lo) node io_data_out_lo_hi_lo = cat(_io_data_out_WIRE_5[selects_5], _io_data_out_WIRE_4[selects_4]) node io_data_out_lo_hi_hi = cat(_io_data_out_WIRE_7[selects_7], _io_data_out_WIRE_6[selects_6]) node io_data_out_lo_hi = cat(io_data_out_lo_hi_hi, io_data_out_lo_hi_lo) node io_data_out_lo = cat(io_data_out_lo_hi, io_data_out_lo_lo) node io_data_out_hi_lo_lo = cat(_io_data_out_WIRE_9[selects_9], _io_data_out_WIRE_8[selects_8]) node io_data_out_hi_lo_hi = cat(_io_data_out_WIRE_11[selects_11], _io_data_out_WIRE_10[selects_10]) node io_data_out_hi_lo = cat(io_data_out_hi_lo_hi, io_data_out_hi_lo_lo) node io_data_out_hi_hi_lo = cat(_io_data_out_WIRE_13[selects_13], _io_data_out_WIRE_12[selects_12]) node io_data_out_hi_hi_hi = cat(_io_data_out_WIRE_15[selects_15], _io_data_out_WIRE_14[selects_14]) node io_data_out_hi_hi = cat(io_data_out_hi_hi_hi, io_data_out_hi_hi_lo) node io_data_out_hi = cat(io_data_out_hi_hi, io_data_out_hi_lo) node _io_data_out_T_64 = cat(io_data_out_hi, io_data_out_lo) connect io.data_out, _io_data_out_T_64
module Atomics( // @[Atomics.scala:8:7] input clock, // @[Atomics.scala:8:7] input reset, // @[Atomics.scala:8:7] input io_write, // @[Atomics.scala:10:14] input [2:0] io_a_opcode, // @[Atomics.scala:10:14] input [2:0] io_a_param, // @[Atomics.scala:10:14] input [15:0] io_a_mask, // @[Atomics.scala:10:14] input [127:0] io_a_data, // @[Atomics.scala:10:14] input [127:0] io_data_in, // @[Atomics.scala:10:14] output [127:0] io_data_out // @[Atomics.scala:10:14] ); wire io_write_0 = io_write; // @[Atomics.scala:8:7] wire [2:0] io_a_opcode_0 = io_a_opcode; // @[Atomics.scala:8:7] wire [2:0] io_a_param_0 = io_a_param; // @[Atomics.scala:8:7] wire [15:0] io_a_mask_0 = io_a_mask; // @[Atomics.scala:8:7] wire [127:0] io_a_data_0 = io_a_data; // @[Atomics.scala:8:7] wire [127:0] io_data_in_0 = io_data_in; // @[Atomics.scala:8:7] wire [3:0][3:0] _GEN = '{4'hC, 4'h8, 4'hE, 4'h6}; wire [3:0] _lut_WIRE_0 = 4'h6; // @[Atomics.scala:34:20] wire [3:0] _lut_WIRE_1 = 4'hE; // @[Atomics.scala:34:20] wire [3:0] _lut_WIRE_2 = 4'h8; // @[Atomics.scala:34:20] wire [3:0] _lut_WIRE_3 = 4'hC; // @[Atomics.scala:34:20] wire [1:0] _select_WIRE_0 = 2'h1; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_1 = 2'h1; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_3 = 2'h3; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_4 = 2'h0; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_5 = 2'h0; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_6 = 2'h0; // @[Atomics.scala:45:42] wire [1:0] _select_WIRE_7 = 2'h0; // @[Atomics.scala:45:42] wire io_a_corrupt = 1'h0; // @[Atomics.scala:8:7, :10:14] wire [31:0] io_a_address = 32'h0; // @[Atomics.scala:8:7, :10:14] wire [7:0] io_a_source = 8'h0; // @[Atomics.scala:8:7] wire [2:0] io_a_size = 3'h0; // @[Atomics.scala:8:7, :10:14] wire [127:0] _io_data_out_T_64; // @[Atomics.scala:58:21] wire [127:0] io_data_out_0; // @[Atomics.scala:8:7] wire adder = io_a_param_0[2]; // @[Atomics.scala:8:7, :18:28] wire unsigned_0 = io_a_param_0[1]; // @[Atomics.scala:8:7, :19:28] wire take_max = io_a_param_0[0]; // @[Atomics.scala:8:7, :20:28] wire [15:0] _signBit_T = ~io_a_mask_0; // @[Atomics.scala:8:7, :22:38] wire [14:0] _signBit_T_1 = _signBit_T[15:1]; // @[Atomics.scala:22:{38,49}] wire [15:0] _signBit_T_2 = {1'h1, _signBit_T_1}; // @[Atomics.scala:22:{32,49}] wire [15:0] signBit = io_a_mask_0 & _signBit_T_2; // @[Atomics.scala:8:7, :22:{27,32}] wire [127:0] _inv_d_T = ~io_data_in_0; // @[Atomics.scala:8:7, :23:38] wire [127:0] inv_d = adder ? io_data_in_0 : _inv_d_T; // @[Atomics.scala:8:7, :18:28, :23:{18,38}] wire _sum_T = io_a_mask_0[0]; // @[Atomics.scala:8:7, :24:29] wire _selects_T = io_a_mask_0[0]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_1 = io_a_mask_0[1]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_1 = io_a_mask_0[1]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_2 = io_a_mask_0[2]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_2 = io_a_mask_0[2]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_3 = io_a_mask_0[3]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_3 = io_a_mask_0[3]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_4 = io_a_mask_0[4]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_4 = io_a_mask_0[4]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_5 = io_a_mask_0[5]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_5 = io_a_mask_0[5]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_6 = io_a_mask_0[6]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_6 = io_a_mask_0[6]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_7 = io_a_mask_0[7]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_7 = io_a_mask_0[7]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_8 = io_a_mask_0[8]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_8 = io_a_mask_0[8]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_9 = io_a_mask_0[9]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_9 = io_a_mask_0[9]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_10 = io_a_mask_0[10]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_10 = io_a_mask_0[10]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_11 = io_a_mask_0[11]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_11 = io_a_mask_0[11]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_12 = io_a_mask_0[12]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_12 = io_a_mask_0[12]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_13 = io_a_mask_0[13]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_13 = io_a_mask_0[13]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_14 = io_a_mask_0[14]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_14 = io_a_mask_0[14]; // @[Atomics.scala:8:7, :24:29, :57:27] wire _sum_T_15 = io_a_mask_0[15]; // @[Atomics.scala:8:7, :24:29] wire _selects_T_15 = io_a_mask_0[15]; // @[Atomics.scala:8:7, :24:29, :57:27] wire [7:0] _sum_T_16 = {8{_sum_T}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_17 = {8{_sum_T_1}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_18 = {8{_sum_T_2}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_19 = {8{_sum_T_3}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_20 = {8{_sum_T_4}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_21 = {8{_sum_T_5}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_22 = {8{_sum_T_6}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_23 = {8{_sum_T_7}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_24 = {8{_sum_T_8}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_25 = {8{_sum_T_9}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_26 = {8{_sum_T_10}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_27 = {8{_sum_T_11}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_28 = {8{_sum_T_12}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_29 = {8{_sum_T_13}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_30 = {8{_sum_T_14}}; // @[Atomics.scala:24:29] wire [7:0] _sum_T_31 = {8{_sum_T_15}}; // @[Atomics.scala:24:29] wire [15:0] sum_lo_lo_lo = {_sum_T_17, _sum_T_16}; // @[Atomics.scala:24:29] wire [15:0] sum_lo_lo_hi = {_sum_T_19, _sum_T_18}; // @[Atomics.scala:24:29] wire [31:0] sum_lo_lo = {sum_lo_lo_hi, sum_lo_lo_lo}; // @[Atomics.scala:24:29] wire [15:0] sum_lo_hi_lo = {_sum_T_21, _sum_T_20}; // @[Atomics.scala:24:29] wire [15:0] sum_lo_hi_hi = {_sum_T_23, _sum_T_22}; // @[Atomics.scala:24:29] wire [31:0] sum_lo_hi = {sum_lo_hi_hi, sum_lo_hi_lo}; // @[Atomics.scala:24:29] wire [63:0] sum_lo = {sum_lo_hi, sum_lo_lo}; // @[Atomics.scala:24:29] wire [15:0] sum_hi_lo_lo = {_sum_T_25, _sum_T_24}; // @[Atomics.scala:24:29] wire [15:0] sum_hi_lo_hi = {_sum_T_27, _sum_T_26}; // @[Atomics.scala:24:29] wire [31:0] sum_hi_lo = {sum_hi_lo_hi, sum_hi_lo_lo}; // @[Atomics.scala:24:29] wire [15:0] sum_hi_hi_lo = {_sum_T_29, _sum_T_28}; // @[Atomics.scala:24:29] wire [15:0] sum_hi_hi_hi = {_sum_T_31, _sum_T_30}; // @[Atomics.scala:24:29] wire [31:0] sum_hi_hi = {sum_hi_hi_hi, sum_hi_hi_lo}; // @[Atomics.scala:24:29] wire [63:0] sum_hi = {sum_hi_hi, sum_hi_lo}; // @[Atomics.scala:24:29] wire [127:0] _sum_T_32 = {sum_hi, sum_lo}; // @[Atomics.scala:24:29] wire [127:0] _sum_T_33 = _sum_T_32 & io_a_data_0; // @[Atomics.scala:8:7, :24:{29,44}] wire [128:0] _sum_T_34 = {1'h0, _sum_T_33} + {1'h0, inv_d}; // @[Atomics.scala:8:7, :10:14, :23:18, :24:{44,57}] wire [127:0] sum = _sum_T_34[127:0]; // @[Atomics.scala:24:57] wire _sign_a_T = io_a_data_0[0]; // @[Atomics.scala:8:7, :25:36] wire _logical_T = io_a_data_0[0]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_1 = io_a_data_0[1]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_1 = io_a_data_0[1]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_2 = io_a_data_0[2]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_2 = io_a_data_0[2]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_3 = io_a_data_0[3]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_3 = io_a_data_0[3]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_4 = io_a_data_0[4]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_4 = io_a_data_0[4]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_5 = io_a_data_0[5]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_5 = io_a_data_0[5]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_6 = io_a_data_0[6]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_6 = io_a_data_0[6]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_7 = io_a_data_0[7]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_7 = io_a_data_0[7]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_8 = io_a_data_0[8]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_8 = io_a_data_0[8]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_9 = io_a_data_0[9]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_9 = io_a_data_0[9]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_10 = io_a_data_0[10]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_10 = io_a_data_0[10]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_11 = io_a_data_0[11]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_11 = io_a_data_0[11]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_12 = io_a_data_0[12]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_12 = io_a_data_0[12]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_13 = io_a_data_0[13]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_13 = io_a_data_0[13]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_14 = io_a_data_0[14]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_14 = io_a_data_0[14]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_15 = io_a_data_0[15]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_15 = io_a_data_0[15]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_16 = io_a_data_0[16]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_16 = io_a_data_0[16]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_17 = io_a_data_0[17]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_17 = io_a_data_0[17]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_18 = io_a_data_0[18]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_18 = io_a_data_0[18]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_19 = io_a_data_0[19]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_19 = io_a_data_0[19]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_20 = io_a_data_0[20]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_20 = io_a_data_0[20]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_21 = io_a_data_0[21]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_21 = io_a_data_0[21]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_22 = io_a_data_0[22]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_22 = io_a_data_0[22]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_23 = io_a_data_0[23]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_23 = io_a_data_0[23]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_24 = io_a_data_0[24]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_24 = io_a_data_0[24]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_25 = io_a_data_0[25]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_25 = io_a_data_0[25]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_26 = io_a_data_0[26]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_26 = io_a_data_0[26]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_27 = io_a_data_0[27]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_27 = io_a_data_0[27]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_28 = io_a_data_0[28]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_28 = io_a_data_0[28]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_29 = io_a_data_0[29]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_29 = io_a_data_0[29]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_30 = io_a_data_0[30]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_30 = io_a_data_0[30]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_31 = io_a_data_0[31]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_31 = io_a_data_0[31]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_32 = io_a_data_0[32]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_32 = io_a_data_0[32]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_33 = io_a_data_0[33]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_33 = io_a_data_0[33]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_34 = io_a_data_0[34]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_34 = io_a_data_0[34]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_35 = io_a_data_0[35]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_35 = io_a_data_0[35]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_36 = io_a_data_0[36]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_36 = io_a_data_0[36]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_37 = io_a_data_0[37]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_37 = io_a_data_0[37]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_38 = io_a_data_0[38]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_38 = io_a_data_0[38]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_39 = io_a_data_0[39]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_39 = io_a_data_0[39]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_40 = io_a_data_0[40]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_40 = io_a_data_0[40]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_41 = io_a_data_0[41]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_41 = io_a_data_0[41]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_42 = io_a_data_0[42]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_42 = io_a_data_0[42]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_43 = io_a_data_0[43]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_43 = io_a_data_0[43]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_44 = io_a_data_0[44]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_44 = io_a_data_0[44]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_45 = io_a_data_0[45]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_45 = io_a_data_0[45]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_46 = io_a_data_0[46]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_46 = io_a_data_0[46]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_47 = io_a_data_0[47]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_47 = io_a_data_0[47]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_48 = io_a_data_0[48]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_48 = io_a_data_0[48]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_49 = io_a_data_0[49]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_49 = io_a_data_0[49]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_50 = io_a_data_0[50]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_50 = io_a_data_0[50]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_51 = io_a_data_0[51]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_51 = io_a_data_0[51]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_52 = io_a_data_0[52]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_52 = io_a_data_0[52]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_53 = io_a_data_0[53]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_53 = io_a_data_0[53]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_54 = io_a_data_0[54]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_54 = io_a_data_0[54]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_55 = io_a_data_0[55]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_55 = io_a_data_0[55]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_56 = io_a_data_0[56]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_56 = io_a_data_0[56]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_57 = io_a_data_0[57]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_57 = io_a_data_0[57]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_58 = io_a_data_0[58]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_58 = io_a_data_0[58]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_59 = io_a_data_0[59]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_59 = io_a_data_0[59]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_60 = io_a_data_0[60]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_60 = io_a_data_0[60]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_61 = io_a_data_0[61]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_61 = io_a_data_0[61]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_62 = io_a_data_0[62]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_62 = io_a_data_0[62]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_63 = io_a_data_0[63]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_63 = io_a_data_0[63]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_64 = io_a_data_0[64]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_64 = io_a_data_0[64]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_65 = io_a_data_0[65]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_65 = io_a_data_0[65]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_66 = io_a_data_0[66]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_66 = io_a_data_0[66]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_67 = io_a_data_0[67]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_67 = io_a_data_0[67]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_68 = io_a_data_0[68]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_68 = io_a_data_0[68]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_69 = io_a_data_0[69]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_69 = io_a_data_0[69]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_70 = io_a_data_0[70]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_70 = io_a_data_0[70]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_71 = io_a_data_0[71]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_71 = io_a_data_0[71]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_72 = io_a_data_0[72]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_72 = io_a_data_0[72]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_73 = io_a_data_0[73]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_73 = io_a_data_0[73]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_74 = io_a_data_0[74]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_74 = io_a_data_0[74]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_75 = io_a_data_0[75]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_75 = io_a_data_0[75]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_76 = io_a_data_0[76]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_76 = io_a_data_0[76]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_77 = io_a_data_0[77]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_77 = io_a_data_0[77]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_78 = io_a_data_0[78]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_78 = io_a_data_0[78]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_79 = io_a_data_0[79]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_79 = io_a_data_0[79]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_80 = io_a_data_0[80]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_80 = io_a_data_0[80]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_81 = io_a_data_0[81]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_81 = io_a_data_0[81]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_82 = io_a_data_0[82]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_82 = io_a_data_0[82]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_83 = io_a_data_0[83]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_83 = io_a_data_0[83]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_84 = io_a_data_0[84]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_84 = io_a_data_0[84]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_85 = io_a_data_0[85]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_85 = io_a_data_0[85]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_86 = io_a_data_0[86]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_86 = io_a_data_0[86]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_87 = io_a_data_0[87]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_87 = io_a_data_0[87]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_88 = io_a_data_0[88]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_88 = io_a_data_0[88]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_89 = io_a_data_0[89]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_89 = io_a_data_0[89]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_90 = io_a_data_0[90]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_90 = io_a_data_0[90]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_91 = io_a_data_0[91]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_91 = io_a_data_0[91]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_92 = io_a_data_0[92]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_92 = io_a_data_0[92]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_93 = io_a_data_0[93]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_93 = io_a_data_0[93]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_94 = io_a_data_0[94]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_94 = io_a_data_0[94]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_95 = io_a_data_0[95]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_95 = io_a_data_0[95]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_96 = io_a_data_0[96]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_96 = io_a_data_0[96]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_97 = io_a_data_0[97]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_97 = io_a_data_0[97]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_98 = io_a_data_0[98]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_98 = io_a_data_0[98]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_99 = io_a_data_0[99]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_99 = io_a_data_0[99]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_100 = io_a_data_0[100]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_100 = io_a_data_0[100]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_101 = io_a_data_0[101]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_101 = io_a_data_0[101]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_102 = io_a_data_0[102]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_102 = io_a_data_0[102]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_103 = io_a_data_0[103]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_103 = io_a_data_0[103]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_104 = io_a_data_0[104]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_104 = io_a_data_0[104]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_105 = io_a_data_0[105]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_105 = io_a_data_0[105]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_106 = io_a_data_0[106]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_106 = io_a_data_0[106]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_107 = io_a_data_0[107]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_107 = io_a_data_0[107]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_108 = io_a_data_0[108]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_108 = io_a_data_0[108]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_109 = io_a_data_0[109]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_109 = io_a_data_0[109]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_110 = io_a_data_0[110]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_110 = io_a_data_0[110]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_111 = io_a_data_0[111]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_111 = io_a_data_0[111]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_112 = io_a_data_0[112]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_112 = io_a_data_0[112]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_113 = io_a_data_0[113]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_113 = io_a_data_0[113]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_114 = io_a_data_0[114]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_114 = io_a_data_0[114]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_115 = io_a_data_0[115]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_115 = io_a_data_0[115]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_116 = io_a_data_0[116]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_116 = io_a_data_0[116]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_117 = io_a_data_0[117]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_117 = io_a_data_0[117]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_118 = io_a_data_0[118]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_118 = io_a_data_0[118]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_119 = io_a_data_0[119]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_119 = io_a_data_0[119]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_120 = io_a_data_0[120]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_120 = io_a_data_0[120]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_121 = io_a_data_0[121]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_121 = io_a_data_0[121]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_122 = io_a_data_0[122]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_122 = io_a_data_0[122]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_123 = io_a_data_0[123]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_123 = io_a_data_0[123]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_124 = io_a_data_0[124]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_124 = io_a_data_0[124]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_125 = io_a_data_0[125]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_125 = io_a_data_0[125]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_126 = io_a_data_0[126]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_126 = io_a_data_0[126]; // @[Atomics.scala:8:7, :25:36, :40:32] wire _sign_a_T_127 = io_a_data_0[127]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_127 = io_a_data_0[127]; // @[Atomics.scala:8:7, :25:36, :40:32] wire [1:0] sign_a_lo_lo_lo = {_sign_a_T_15, _sign_a_T_7}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_a_lo_lo_hi = {_sign_a_T_31, _sign_a_T_23}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_a_lo_lo = {sign_a_lo_lo_hi, sign_a_lo_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_a_lo_hi_lo = {_sign_a_T_47, _sign_a_T_39}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_a_lo_hi_hi = {_sign_a_T_63, _sign_a_T_55}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_a_lo_hi = {sign_a_lo_hi_hi, sign_a_lo_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_a_lo = {sign_a_lo_hi, sign_a_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_a_hi_lo_lo = {_sign_a_T_79, _sign_a_T_71}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_a_hi_lo_hi = {_sign_a_T_95, _sign_a_T_87}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_a_hi_lo = {sign_a_hi_lo_hi, sign_a_hi_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_a_hi_hi_lo = {_sign_a_T_111, _sign_a_T_103}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_a_hi_hi_hi = {_sign_a_T_127, _sign_a_T_119}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_a_hi_hi = {sign_a_hi_hi_hi, sign_a_hi_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_a_hi = {sign_a_hi_hi, sign_a_hi_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_a_T_128 = {sign_a_hi, sign_a_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_a_T_129 = _sign_a_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}] wire sign_a = |_sign_a_T_129; // @[Atomics.scala:25:{83,94}] wire _sign_d_T = io_data_in_0[0]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_128 = io_data_in_0[0]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_1 = io_data_in_0[1]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_129 = io_data_in_0[1]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_2 = io_data_in_0[2]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_130 = io_data_in_0[2]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_3 = io_data_in_0[3]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_131 = io_data_in_0[3]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_4 = io_data_in_0[4]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_132 = io_data_in_0[4]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_5 = io_data_in_0[5]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_133 = io_data_in_0[5]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_6 = io_data_in_0[6]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_134 = io_data_in_0[6]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_7 = io_data_in_0[7]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_135 = io_data_in_0[7]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_8 = io_data_in_0[8]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_136 = io_data_in_0[8]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_9 = io_data_in_0[9]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_137 = io_data_in_0[9]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_10 = io_data_in_0[10]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_138 = io_data_in_0[10]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_11 = io_data_in_0[11]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_139 = io_data_in_0[11]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_12 = io_data_in_0[12]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_140 = io_data_in_0[12]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_13 = io_data_in_0[13]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_141 = io_data_in_0[13]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_14 = io_data_in_0[14]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_142 = io_data_in_0[14]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_15 = io_data_in_0[15]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_143 = io_data_in_0[15]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_16 = io_data_in_0[16]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_144 = io_data_in_0[16]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_17 = io_data_in_0[17]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_145 = io_data_in_0[17]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_18 = io_data_in_0[18]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_146 = io_data_in_0[18]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_19 = io_data_in_0[19]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_147 = io_data_in_0[19]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_20 = io_data_in_0[20]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_148 = io_data_in_0[20]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_21 = io_data_in_0[21]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_149 = io_data_in_0[21]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_22 = io_data_in_0[22]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_150 = io_data_in_0[22]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_23 = io_data_in_0[23]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_151 = io_data_in_0[23]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_24 = io_data_in_0[24]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_152 = io_data_in_0[24]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_25 = io_data_in_0[25]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_153 = io_data_in_0[25]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_26 = io_data_in_0[26]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_154 = io_data_in_0[26]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_27 = io_data_in_0[27]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_155 = io_data_in_0[27]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_28 = io_data_in_0[28]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_156 = io_data_in_0[28]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_29 = io_data_in_0[29]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_157 = io_data_in_0[29]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_30 = io_data_in_0[30]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_158 = io_data_in_0[30]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_31 = io_data_in_0[31]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_159 = io_data_in_0[31]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_32 = io_data_in_0[32]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_160 = io_data_in_0[32]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_33 = io_data_in_0[33]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_161 = io_data_in_0[33]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_34 = io_data_in_0[34]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_162 = io_data_in_0[34]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_35 = io_data_in_0[35]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_163 = io_data_in_0[35]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_36 = io_data_in_0[36]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_164 = io_data_in_0[36]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_37 = io_data_in_0[37]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_165 = io_data_in_0[37]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_38 = io_data_in_0[38]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_166 = io_data_in_0[38]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_39 = io_data_in_0[39]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_167 = io_data_in_0[39]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_40 = io_data_in_0[40]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_168 = io_data_in_0[40]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_41 = io_data_in_0[41]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_169 = io_data_in_0[41]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_42 = io_data_in_0[42]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_170 = io_data_in_0[42]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_43 = io_data_in_0[43]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_171 = io_data_in_0[43]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_44 = io_data_in_0[44]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_172 = io_data_in_0[44]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_45 = io_data_in_0[45]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_173 = io_data_in_0[45]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_46 = io_data_in_0[46]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_174 = io_data_in_0[46]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_47 = io_data_in_0[47]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_175 = io_data_in_0[47]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_48 = io_data_in_0[48]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_176 = io_data_in_0[48]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_49 = io_data_in_0[49]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_177 = io_data_in_0[49]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_50 = io_data_in_0[50]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_178 = io_data_in_0[50]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_51 = io_data_in_0[51]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_179 = io_data_in_0[51]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_52 = io_data_in_0[52]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_180 = io_data_in_0[52]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_53 = io_data_in_0[53]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_181 = io_data_in_0[53]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_54 = io_data_in_0[54]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_182 = io_data_in_0[54]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_55 = io_data_in_0[55]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_183 = io_data_in_0[55]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_56 = io_data_in_0[56]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_184 = io_data_in_0[56]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_57 = io_data_in_0[57]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_185 = io_data_in_0[57]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_58 = io_data_in_0[58]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_186 = io_data_in_0[58]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_59 = io_data_in_0[59]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_187 = io_data_in_0[59]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_60 = io_data_in_0[60]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_188 = io_data_in_0[60]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_61 = io_data_in_0[61]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_189 = io_data_in_0[61]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_62 = io_data_in_0[62]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_190 = io_data_in_0[62]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_63 = io_data_in_0[63]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_191 = io_data_in_0[63]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_64 = io_data_in_0[64]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_192 = io_data_in_0[64]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_65 = io_data_in_0[65]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_193 = io_data_in_0[65]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_66 = io_data_in_0[66]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_194 = io_data_in_0[66]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_67 = io_data_in_0[67]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_195 = io_data_in_0[67]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_68 = io_data_in_0[68]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_196 = io_data_in_0[68]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_69 = io_data_in_0[69]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_197 = io_data_in_0[69]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_70 = io_data_in_0[70]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_198 = io_data_in_0[70]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_71 = io_data_in_0[71]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_199 = io_data_in_0[71]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_72 = io_data_in_0[72]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_200 = io_data_in_0[72]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_73 = io_data_in_0[73]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_201 = io_data_in_0[73]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_74 = io_data_in_0[74]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_202 = io_data_in_0[74]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_75 = io_data_in_0[75]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_203 = io_data_in_0[75]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_76 = io_data_in_0[76]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_204 = io_data_in_0[76]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_77 = io_data_in_0[77]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_205 = io_data_in_0[77]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_78 = io_data_in_0[78]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_206 = io_data_in_0[78]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_79 = io_data_in_0[79]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_207 = io_data_in_0[79]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_80 = io_data_in_0[80]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_208 = io_data_in_0[80]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_81 = io_data_in_0[81]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_209 = io_data_in_0[81]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_82 = io_data_in_0[82]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_210 = io_data_in_0[82]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_83 = io_data_in_0[83]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_211 = io_data_in_0[83]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_84 = io_data_in_0[84]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_212 = io_data_in_0[84]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_85 = io_data_in_0[85]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_213 = io_data_in_0[85]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_86 = io_data_in_0[86]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_214 = io_data_in_0[86]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_87 = io_data_in_0[87]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_215 = io_data_in_0[87]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_88 = io_data_in_0[88]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_216 = io_data_in_0[88]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_89 = io_data_in_0[89]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_217 = io_data_in_0[89]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_90 = io_data_in_0[90]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_218 = io_data_in_0[90]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_91 = io_data_in_0[91]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_219 = io_data_in_0[91]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_92 = io_data_in_0[92]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_220 = io_data_in_0[92]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_93 = io_data_in_0[93]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_221 = io_data_in_0[93]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_94 = io_data_in_0[94]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_222 = io_data_in_0[94]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_95 = io_data_in_0[95]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_223 = io_data_in_0[95]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_96 = io_data_in_0[96]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_224 = io_data_in_0[96]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_97 = io_data_in_0[97]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_225 = io_data_in_0[97]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_98 = io_data_in_0[98]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_226 = io_data_in_0[98]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_99 = io_data_in_0[99]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_227 = io_data_in_0[99]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_100 = io_data_in_0[100]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_228 = io_data_in_0[100]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_101 = io_data_in_0[101]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_229 = io_data_in_0[101]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_102 = io_data_in_0[102]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_230 = io_data_in_0[102]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_103 = io_data_in_0[103]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_231 = io_data_in_0[103]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_104 = io_data_in_0[104]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_232 = io_data_in_0[104]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_105 = io_data_in_0[105]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_233 = io_data_in_0[105]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_106 = io_data_in_0[106]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_234 = io_data_in_0[106]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_107 = io_data_in_0[107]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_235 = io_data_in_0[107]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_108 = io_data_in_0[108]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_236 = io_data_in_0[108]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_109 = io_data_in_0[109]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_237 = io_data_in_0[109]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_110 = io_data_in_0[110]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_238 = io_data_in_0[110]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_111 = io_data_in_0[111]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_239 = io_data_in_0[111]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_112 = io_data_in_0[112]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_240 = io_data_in_0[112]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_113 = io_data_in_0[113]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_241 = io_data_in_0[113]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_114 = io_data_in_0[114]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_242 = io_data_in_0[114]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_115 = io_data_in_0[115]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_243 = io_data_in_0[115]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_116 = io_data_in_0[116]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_244 = io_data_in_0[116]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_117 = io_data_in_0[117]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_245 = io_data_in_0[117]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_118 = io_data_in_0[118]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_246 = io_data_in_0[118]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_119 = io_data_in_0[119]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_247 = io_data_in_0[119]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_120 = io_data_in_0[120]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_248 = io_data_in_0[120]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_121 = io_data_in_0[121]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_249 = io_data_in_0[121]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_122 = io_data_in_0[122]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_250 = io_data_in_0[122]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_123 = io_data_in_0[123]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_251 = io_data_in_0[123]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_124 = io_data_in_0[124]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_252 = io_data_in_0[124]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_125 = io_data_in_0[125]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_253 = io_data_in_0[125]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_126 = io_data_in_0[126]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_254 = io_data_in_0[126]; // @[Atomics.scala:8:7, :25:36, :40:55] wire _sign_d_T_127 = io_data_in_0[127]; // @[Atomics.scala:8:7, :25:36] wire _logical_T_255 = io_data_in_0[127]; // @[Atomics.scala:8:7, :25:36, :40:55] wire [1:0] sign_d_lo_lo_lo = {_sign_d_T_15, _sign_d_T_7}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_d_lo_lo_hi = {_sign_d_T_31, _sign_d_T_23}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_d_lo_lo = {sign_d_lo_lo_hi, sign_d_lo_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_d_lo_hi_lo = {_sign_d_T_47, _sign_d_T_39}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_d_lo_hi_hi = {_sign_d_T_63, _sign_d_T_55}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_d_lo_hi = {sign_d_lo_hi_hi, sign_d_lo_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_d_lo = {sign_d_lo_hi, sign_d_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_d_hi_lo_lo = {_sign_d_T_79, _sign_d_T_71}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_d_hi_lo_hi = {_sign_d_T_95, _sign_d_T_87}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_d_hi_lo = {sign_d_hi_lo_hi, sign_d_hi_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_d_hi_hi_lo = {_sign_d_T_111, _sign_d_T_103}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_d_hi_hi_hi = {_sign_d_T_127, _sign_d_T_119}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_d_hi_hi = {sign_d_hi_hi_hi, sign_d_hi_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_d_hi = {sign_d_hi_hi, sign_d_hi_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_d_T_128 = {sign_d_hi, sign_d_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_d_T_129 = _sign_d_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}] wire sign_d = |_sign_d_T_129; // @[Atomics.scala:25:{83,94}] wire _sign_s_T = sum[0]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_1 = sum[1]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_2 = sum[2]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_3 = sum[3]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_4 = sum[4]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_5 = sum[5]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_6 = sum[6]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_7 = sum[7]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_8 = sum[8]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_9 = sum[9]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_10 = sum[10]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_11 = sum[11]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_12 = sum[12]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_13 = sum[13]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_14 = sum[14]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_15 = sum[15]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_16 = sum[16]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_17 = sum[17]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_18 = sum[18]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_19 = sum[19]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_20 = sum[20]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_21 = sum[21]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_22 = sum[22]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_23 = sum[23]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_24 = sum[24]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_25 = sum[25]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_26 = sum[26]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_27 = sum[27]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_28 = sum[28]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_29 = sum[29]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_30 = sum[30]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_31 = sum[31]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_32 = sum[32]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_33 = sum[33]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_34 = sum[34]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_35 = sum[35]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_36 = sum[36]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_37 = sum[37]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_38 = sum[38]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_39 = sum[39]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_40 = sum[40]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_41 = sum[41]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_42 = sum[42]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_43 = sum[43]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_44 = sum[44]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_45 = sum[45]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_46 = sum[46]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_47 = sum[47]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_48 = sum[48]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_49 = sum[49]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_50 = sum[50]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_51 = sum[51]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_52 = sum[52]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_53 = sum[53]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_54 = sum[54]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_55 = sum[55]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_56 = sum[56]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_57 = sum[57]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_58 = sum[58]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_59 = sum[59]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_60 = sum[60]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_61 = sum[61]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_62 = sum[62]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_63 = sum[63]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_64 = sum[64]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_65 = sum[65]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_66 = sum[66]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_67 = sum[67]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_68 = sum[68]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_69 = sum[69]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_70 = sum[70]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_71 = sum[71]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_72 = sum[72]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_73 = sum[73]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_74 = sum[74]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_75 = sum[75]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_76 = sum[76]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_77 = sum[77]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_78 = sum[78]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_79 = sum[79]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_80 = sum[80]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_81 = sum[81]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_82 = sum[82]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_83 = sum[83]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_84 = sum[84]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_85 = sum[85]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_86 = sum[86]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_87 = sum[87]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_88 = sum[88]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_89 = sum[89]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_90 = sum[90]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_91 = sum[91]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_92 = sum[92]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_93 = sum[93]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_94 = sum[94]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_95 = sum[95]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_96 = sum[96]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_97 = sum[97]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_98 = sum[98]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_99 = sum[99]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_100 = sum[100]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_101 = sum[101]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_102 = sum[102]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_103 = sum[103]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_104 = sum[104]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_105 = sum[105]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_106 = sum[106]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_107 = sum[107]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_108 = sum[108]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_109 = sum[109]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_110 = sum[110]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_111 = sum[111]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_112 = sum[112]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_113 = sum[113]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_114 = sum[114]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_115 = sum[115]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_116 = sum[116]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_117 = sum[117]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_118 = sum[118]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_119 = sum[119]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_120 = sum[120]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_121 = sum[121]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_122 = sum[122]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_123 = sum[123]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_124 = sum[124]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_125 = sum[125]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_126 = sum[126]; // @[Atomics.scala:24:57, :25:36] wire _sign_s_T_127 = sum[127]; // @[Atomics.scala:24:57, :25:36] wire [1:0] sign_s_lo_lo_lo = {_sign_s_T_15, _sign_s_T_7}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_s_lo_lo_hi = {_sign_s_T_31, _sign_s_T_23}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_s_lo_lo = {sign_s_lo_lo_hi, sign_s_lo_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_s_lo_hi_lo = {_sign_s_T_47, _sign_s_T_39}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_s_lo_hi_hi = {_sign_s_T_63, _sign_s_T_55}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_s_lo_hi = {sign_s_lo_hi_hi, sign_s_lo_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_s_lo = {sign_s_lo_hi, sign_s_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_s_hi_lo_lo = {_sign_s_T_79, _sign_s_T_71}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_s_hi_lo_hi = {_sign_s_T_95, _sign_s_T_87}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_s_hi_lo = {sign_s_hi_lo_hi, sign_s_hi_lo_lo}; // @[Atomics.scala:25:33] wire [1:0] sign_s_hi_hi_lo = {_sign_s_T_111, _sign_s_T_103}; // @[Atomics.scala:25:{33,36}] wire [1:0] sign_s_hi_hi_hi = {_sign_s_T_127, _sign_s_T_119}; // @[Atomics.scala:25:{33,36}] wire [3:0] sign_s_hi_hi = {sign_s_hi_hi_hi, sign_s_hi_hi_lo}; // @[Atomics.scala:25:33] wire [7:0] sign_s_hi = {sign_s_hi_hi, sign_s_hi_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_s_T_128 = {sign_s_hi, sign_s_lo}; // @[Atomics.scala:25:33] wire [15:0] _sign_s_T_129 = _sign_s_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}] wire sign_s = |_sign_s_T_129; // @[Atomics.scala:25:{83,94}] wire a_bigger_uneq = unsigned_0 == sign_a; // @[Atomics.scala:19:28, :25:94, :29:32] wire _a_bigger_T = sign_a == sign_d; // @[Atomics.scala:25:94, :30:29] wire _a_bigger_T_1 = ~sign_s; // @[Atomics.scala:25:94, :30:41] wire a_bigger = _a_bigger_T ? _a_bigger_T_1 : a_bigger_uneq; // @[Atomics.scala:29:32, :30:{21,29,41}] wire pick_a = take_max == a_bigger; // @[Atomics.scala:20:28, :30:21, :31:25] wire _select_T = pick_a; // @[Atomics.scala:31:25, :48:24] wire [1:0] _lut_T = io_a_param_0[1:0]; // @[Atomics.scala:8:7, :39:15] wire [1:0] _logical_T_256 = {_logical_T, _logical_T_128}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_257 = _GEN[_lut_T] >> _logical_T_256; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_258 = _logical_T_257[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_259 = {_logical_T_1, _logical_T_129}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_260 = _GEN[_lut_T] >> _logical_T_259; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_261 = _logical_T_260[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_262 = {_logical_T_2, _logical_T_130}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_263 = _GEN[_lut_T] >> _logical_T_262; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_264 = _logical_T_263[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_265 = {_logical_T_3, _logical_T_131}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_266 = _GEN[_lut_T] >> _logical_T_265; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_267 = _logical_T_266[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_268 = {_logical_T_4, _logical_T_132}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_269 = _GEN[_lut_T] >> _logical_T_268; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_270 = _logical_T_269[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_271 = {_logical_T_5, _logical_T_133}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_272 = _GEN[_lut_T] >> _logical_T_271; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_273 = _logical_T_272[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_274 = {_logical_T_6, _logical_T_134}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_275 = _GEN[_lut_T] >> _logical_T_274; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_276 = _logical_T_275[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_277 = {_logical_T_7, _logical_T_135}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_278 = _GEN[_lut_T] >> _logical_T_277; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_279 = _logical_T_278[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_280 = {_logical_T_8, _logical_T_136}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_281 = _GEN[_lut_T] >> _logical_T_280; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_282 = _logical_T_281[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_283 = {_logical_T_9, _logical_T_137}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_284 = _GEN[_lut_T] >> _logical_T_283; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_285 = _logical_T_284[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_286 = {_logical_T_10, _logical_T_138}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_287 = _GEN[_lut_T] >> _logical_T_286; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_288 = _logical_T_287[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_289 = {_logical_T_11, _logical_T_139}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_290 = _GEN[_lut_T] >> _logical_T_289; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_291 = _logical_T_290[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_292 = {_logical_T_12, _logical_T_140}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_293 = _GEN[_lut_T] >> _logical_T_292; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_294 = _logical_T_293[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_295 = {_logical_T_13, _logical_T_141}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_296 = _GEN[_lut_T] >> _logical_T_295; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_297 = _logical_T_296[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_298 = {_logical_T_14, _logical_T_142}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_299 = _GEN[_lut_T] >> _logical_T_298; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_300 = _logical_T_299[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_301 = {_logical_T_15, _logical_T_143}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_302 = _GEN[_lut_T] >> _logical_T_301; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_303 = _logical_T_302[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_304 = {_logical_T_16, _logical_T_144}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_305 = _GEN[_lut_T] >> _logical_T_304; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_306 = _logical_T_305[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_307 = {_logical_T_17, _logical_T_145}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_308 = _GEN[_lut_T] >> _logical_T_307; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_309 = _logical_T_308[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_310 = {_logical_T_18, _logical_T_146}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_311 = _GEN[_lut_T] >> _logical_T_310; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_312 = _logical_T_311[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_313 = {_logical_T_19, _logical_T_147}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_314 = _GEN[_lut_T] >> _logical_T_313; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_315 = _logical_T_314[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_316 = {_logical_T_20, _logical_T_148}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_317 = _GEN[_lut_T] >> _logical_T_316; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_318 = _logical_T_317[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_319 = {_logical_T_21, _logical_T_149}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_320 = _GEN[_lut_T] >> _logical_T_319; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_321 = _logical_T_320[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_322 = {_logical_T_22, _logical_T_150}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_323 = _GEN[_lut_T] >> _logical_T_322; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_324 = _logical_T_323[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_325 = {_logical_T_23, _logical_T_151}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_326 = _GEN[_lut_T] >> _logical_T_325; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_327 = _logical_T_326[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_328 = {_logical_T_24, _logical_T_152}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_329 = _GEN[_lut_T] >> _logical_T_328; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_330 = _logical_T_329[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_331 = {_logical_T_25, _logical_T_153}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_332 = _GEN[_lut_T] >> _logical_T_331; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_333 = _logical_T_332[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_334 = {_logical_T_26, _logical_T_154}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_335 = _GEN[_lut_T] >> _logical_T_334; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_336 = _logical_T_335[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_337 = {_logical_T_27, _logical_T_155}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_338 = _GEN[_lut_T] >> _logical_T_337; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_339 = _logical_T_338[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_340 = {_logical_T_28, _logical_T_156}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_341 = _GEN[_lut_T] >> _logical_T_340; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_342 = _logical_T_341[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_343 = {_logical_T_29, _logical_T_157}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_344 = _GEN[_lut_T] >> _logical_T_343; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_345 = _logical_T_344[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_346 = {_logical_T_30, _logical_T_158}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_347 = _GEN[_lut_T] >> _logical_T_346; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_348 = _logical_T_347[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_349 = {_logical_T_31, _logical_T_159}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_350 = _GEN[_lut_T] >> _logical_T_349; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_351 = _logical_T_350[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_352 = {_logical_T_32, _logical_T_160}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_353 = _GEN[_lut_T] >> _logical_T_352; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_354 = _logical_T_353[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_355 = {_logical_T_33, _logical_T_161}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_356 = _GEN[_lut_T] >> _logical_T_355; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_357 = _logical_T_356[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_358 = {_logical_T_34, _logical_T_162}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_359 = _GEN[_lut_T] >> _logical_T_358; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_360 = _logical_T_359[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_361 = {_logical_T_35, _logical_T_163}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_362 = _GEN[_lut_T] >> _logical_T_361; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_363 = _logical_T_362[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_364 = {_logical_T_36, _logical_T_164}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_365 = _GEN[_lut_T] >> _logical_T_364; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_366 = _logical_T_365[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_367 = {_logical_T_37, _logical_T_165}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_368 = _GEN[_lut_T] >> _logical_T_367; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_369 = _logical_T_368[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_370 = {_logical_T_38, _logical_T_166}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_371 = _GEN[_lut_T] >> _logical_T_370; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_372 = _logical_T_371[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_373 = {_logical_T_39, _logical_T_167}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_374 = _GEN[_lut_T] >> _logical_T_373; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_375 = _logical_T_374[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_376 = {_logical_T_40, _logical_T_168}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_377 = _GEN[_lut_T] >> _logical_T_376; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_378 = _logical_T_377[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_379 = {_logical_T_41, _logical_T_169}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_380 = _GEN[_lut_T] >> _logical_T_379; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_381 = _logical_T_380[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_382 = {_logical_T_42, _logical_T_170}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_383 = _GEN[_lut_T] >> _logical_T_382; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_384 = _logical_T_383[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_385 = {_logical_T_43, _logical_T_171}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_386 = _GEN[_lut_T] >> _logical_T_385; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_387 = _logical_T_386[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_388 = {_logical_T_44, _logical_T_172}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_389 = _GEN[_lut_T] >> _logical_T_388; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_390 = _logical_T_389[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_391 = {_logical_T_45, _logical_T_173}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_392 = _GEN[_lut_T] >> _logical_T_391; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_393 = _logical_T_392[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_394 = {_logical_T_46, _logical_T_174}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_395 = _GEN[_lut_T] >> _logical_T_394; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_396 = _logical_T_395[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_397 = {_logical_T_47, _logical_T_175}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_398 = _GEN[_lut_T] >> _logical_T_397; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_399 = _logical_T_398[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_400 = {_logical_T_48, _logical_T_176}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_401 = _GEN[_lut_T] >> _logical_T_400; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_402 = _logical_T_401[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_403 = {_logical_T_49, _logical_T_177}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_404 = _GEN[_lut_T] >> _logical_T_403; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_405 = _logical_T_404[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_406 = {_logical_T_50, _logical_T_178}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_407 = _GEN[_lut_T] >> _logical_T_406; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_408 = _logical_T_407[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_409 = {_logical_T_51, _logical_T_179}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_410 = _GEN[_lut_T] >> _logical_T_409; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_411 = _logical_T_410[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_412 = {_logical_T_52, _logical_T_180}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_413 = _GEN[_lut_T] >> _logical_T_412; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_414 = _logical_T_413[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_415 = {_logical_T_53, _logical_T_181}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_416 = _GEN[_lut_T] >> _logical_T_415; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_417 = _logical_T_416[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_418 = {_logical_T_54, _logical_T_182}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_419 = _GEN[_lut_T] >> _logical_T_418; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_420 = _logical_T_419[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_421 = {_logical_T_55, _logical_T_183}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_422 = _GEN[_lut_T] >> _logical_T_421; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_423 = _logical_T_422[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_424 = {_logical_T_56, _logical_T_184}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_425 = _GEN[_lut_T] >> _logical_T_424; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_426 = _logical_T_425[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_427 = {_logical_T_57, _logical_T_185}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_428 = _GEN[_lut_T] >> _logical_T_427; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_429 = _logical_T_428[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_430 = {_logical_T_58, _logical_T_186}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_431 = _GEN[_lut_T] >> _logical_T_430; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_432 = _logical_T_431[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_433 = {_logical_T_59, _logical_T_187}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_434 = _GEN[_lut_T] >> _logical_T_433; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_435 = _logical_T_434[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_436 = {_logical_T_60, _logical_T_188}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_437 = _GEN[_lut_T] >> _logical_T_436; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_438 = _logical_T_437[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_439 = {_logical_T_61, _logical_T_189}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_440 = _GEN[_lut_T] >> _logical_T_439; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_441 = _logical_T_440[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_442 = {_logical_T_62, _logical_T_190}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_443 = _GEN[_lut_T] >> _logical_T_442; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_444 = _logical_T_443[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_445 = {_logical_T_63, _logical_T_191}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_446 = _GEN[_lut_T] >> _logical_T_445; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_447 = _logical_T_446[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_448 = {_logical_T_64, _logical_T_192}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_449 = _GEN[_lut_T] >> _logical_T_448; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_450 = _logical_T_449[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_451 = {_logical_T_65, _logical_T_193}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_452 = _GEN[_lut_T] >> _logical_T_451; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_453 = _logical_T_452[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_454 = {_logical_T_66, _logical_T_194}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_455 = _GEN[_lut_T] >> _logical_T_454; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_456 = _logical_T_455[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_457 = {_logical_T_67, _logical_T_195}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_458 = _GEN[_lut_T] >> _logical_T_457; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_459 = _logical_T_458[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_460 = {_logical_T_68, _logical_T_196}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_461 = _GEN[_lut_T] >> _logical_T_460; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_462 = _logical_T_461[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_463 = {_logical_T_69, _logical_T_197}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_464 = _GEN[_lut_T] >> _logical_T_463; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_465 = _logical_T_464[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_466 = {_logical_T_70, _logical_T_198}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_467 = _GEN[_lut_T] >> _logical_T_466; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_468 = _logical_T_467[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_469 = {_logical_T_71, _logical_T_199}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_470 = _GEN[_lut_T] >> _logical_T_469; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_471 = _logical_T_470[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_472 = {_logical_T_72, _logical_T_200}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_473 = _GEN[_lut_T] >> _logical_T_472; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_474 = _logical_T_473[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_475 = {_logical_T_73, _logical_T_201}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_476 = _GEN[_lut_T] >> _logical_T_475; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_477 = _logical_T_476[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_478 = {_logical_T_74, _logical_T_202}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_479 = _GEN[_lut_T] >> _logical_T_478; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_480 = _logical_T_479[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_481 = {_logical_T_75, _logical_T_203}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_482 = _GEN[_lut_T] >> _logical_T_481; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_483 = _logical_T_482[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_484 = {_logical_T_76, _logical_T_204}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_485 = _GEN[_lut_T] >> _logical_T_484; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_486 = _logical_T_485[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_487 = {_logical_T_77, _logical_T_205}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_488 = _GEN[_lut_T] >> _logical_T_487; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_489 = _logical_T_488[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_490 = {_logical_T_78, _logical_T_206}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_491 = _GEN[_lut_T] >> _logical_T_490; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_492 = _logical_T_491[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_493 = {_logical_T_79, _logical_T_207}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_494 = _GEN[_lut_T] >> _logical_T_493; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_495 = _logical_T_494[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_496 = {_logical_T_80, _logical_T_208}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_497 = _GEN[_lut_T] >> _logical_T_496; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_498 = _logical_T_497[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_499 = {_logical_T_81, _logical_T_209}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_500 = _GEN[_lut_T] >> _logical_T_499; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_501 = _logical_T_500[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_502 = {_logical_T_82, _logical_T_210}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_503 = _GEN[_lut_T] >> _logical_T_502; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_504 = _logical_T_503[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_505 = {_logical_T_83, _logical_T_211}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_506 = _GEN[_lut_T] >> _logical_T_505; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_507 = _logical_T_506[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_508 = {_logical_T_84, _logical_T_212}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_509 = _GEN[_lut_T] >> _logical_T_508; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_510 = _logical_T_509[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_511 = {_logical_T_85, _logical_T_213}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_512 = _GEN[_lut_T] >> _logical_T_511; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_513 = _logical_T_512[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_514 = {_logical_T_86, _logical_T_214}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_515 = _GEN[_lut_T] >> _logical_T_514; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_516 = _logical_T_515[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_517 = {_logical_T_87, _logical_T_215}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_518 = _GEN[_lut_T] >> _logical_T_517; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_519 = _logical_T_518[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_520 = {_logical_T_88, _logical_T_216}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_521 = _GEN[_lut_T] >> _logical_T_520; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_522 = _logical_T_521[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_523 = {_logical_T_89, _logical_T_217}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_524 = _GEN[_lut_T] >> _logical_T_523; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_525 = _logical_T_524[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_526 = {_logical_T_90, _logical_T_218}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_527 = _GEN[_lut_T] >> _logical_T_526; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_528 = _logical_T_527[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_529 = {_logical_T_91, _logical_T_219}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_530 = _GEN[_lut_T] >> _logical_T_529; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_531 = _logical_T_530[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_532 = {_logical_T_92, _logical_T_220}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_533 = _GEN[_lut_T] >> _logical_T_532; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_534 = _logical_T_533[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_535 = {_logical_T_93, _logical_T_221}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_536 = _GEN[_lut_T] >> _logical_T_535; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_537 = _logical_T_536[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_538 = {_logical_T_94, _logical_T_222}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_539 = _GEN[_lut_T] >> _logical_T_538; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_540 = _logical_T_539[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_541 = {_logical_T_95, _logical_T_223}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_542 = _GEN[_lut_T] >> _logical_T_541; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_543 = _logical_T_542[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_544 = {_logical_T_96, _logical_T_224}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_545 = _GEN[_lut_T] >> _logical_T_544; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_546 = _logical_T_545[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_547 = {_logical_T_97, _logical_T_225}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_548 = _GEN[_lut_T] >> _logical_T_547; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_549 = _logical_T_548[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_550 = {_logical_T_98, _logical_T_226}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_551 = _GEN[_lut_T] >> _logical_T_550; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_552 = _logical_T_551[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_553 = {_logical_T_99, _logical_T_227}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_554 = _GEN[_lut_T] >> _logical_T_553; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_555 = _logical_T_554[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_556 = {_logical_T_100, _logical_T_228}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_557 = _GEN[_lut_T] >> _logical_T_556; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_558 = _logical_T_557[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_559 = {_logical_T_101, _logical_T_229}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_560 = _GEN[_lut_T] >> _logical_T_559; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_561 = _logical_T_560[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_562 = {_logical_T_102, _logical_T_230}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_563 = _GEN[_lut_T] >> _logical_T_562; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_564 = _logical_T_563[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_565 = {_logical_T_103, _logical_T_231}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_566 = _GEN[_lut_T] >> _logical_T_565; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_567 = _logical_T_566[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_568 = {_logical_T_104, _logical_T_232}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_569 = _GEN[_lut_T] >> _logical_T_568; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_570 = _logical_T_569[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_571 = {_logical_T_105, _logical_T_233}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_572 = _GEN[_lut_T] >> _logical_T_571; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_573 = _logical_T_572[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_574 = {_logical_T_106, _logical_T_234}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_575 = _GEN[_lut_T] >> _logical_T_574; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_576 = _logical_T_575[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_577 = {_logical_T_107, _logical_T_235}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_578 = _GEN[_lut_T] >> _logical_T_577; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_579 = _logical_T_578[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_580 = {_logical_T_108, _logical_T_236}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_581 = _GEN[_lut_T] >> _logical_T_580; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_582 = _logical_T_581[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_583 = {_logical_T_109, _logical_T_237}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_584 = _GEN[_lut_T] >> _logical_T_583; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_585 = _logical_T_584[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_586 = {_logical_T_110, _logical_T_238}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_587 = _GEN[_lut_T] >> _logical_T_586; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_588 = _logical_T_587[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_589 = {_logical_T_111, _logical_T_239}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_590 = _GEN[_lut_T] >> _logical_T_589; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_591 = _logical_T_590[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_592 = {_logical_T_112, _logical_T_240}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_593 = _GEN[_lut_T] >> _logical_T_592; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_594 = _logical_T_593[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_595 = {_logical_T_113, _logical_T_241}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_596 = _GEN[_lut_T] >> _logical_T_595; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_597 = _logical_T_596[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_598 = {_logical_T_114, _logical_T_242}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_599 = _GEN[_lut_T] >> _logical_T_598; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_600 = _logical_T_599[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_601 = {_logical_T_115, _logical_T_243}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_602 = _GEN[_lut_T] >> _logical_T_601; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_603 = _logical_T_602[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_604 = {_logical_T_116, _logical_T_244}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_605 = _GEN[_lut_T] >> _logical_T_604; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_606 = _logical_T_605[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_607 = {_logical_T_117, _logical_T_245}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_608 = _GEN[_lut_T] >> _logical_T_607; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_609 = _logical_T_608[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_610 = {_logical_T_118, _logical_T_246}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_611 = _GEN[_lut_T] >> _logical_T_610; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_612 = _logical_T_611[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_613 = {_logical_T_119, _logical_T_247}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_614 = _GEN[_lut_T] >> _logical_T_613; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_615 = _logical_T_614[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_616 = {_logical_T_120, _logical_T_248}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_617 = _GEN[_lut_T] >> _logical_T_616; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_618 = _logical_T_617[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_619 = {_logical_T_121, _logical_T_249}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_620 = _GEN[_lut_T] >> _logical_T_619; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_621 = _logical_T_620[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_622 = {_logical_T_122, _logical_T_250}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_623 = _GEN[_lut_T] >> _logical_T_622; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_624 = _logical_T_623[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_625 = {_logical_T_123, _logical_T_251}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_626 = _GEN[_lut_T] >> _logical_T_625; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_627 = _logical_T_626[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_628 = {_logical_T_124, _logical_T_252}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_629 = _GEN[_lut_T] >> _logical_T_628; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_630 = _logical_T_629[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_631 = {_logical_T_125, _logical_T_253}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_632 = _GEN[_lut_T] >> _logical_T_631; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_633 = _logical_T_632[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_634 = {_logical_T_126, _logical_T_254}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_635 = _GEN[_lut_T] >> _logical_T_634; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_636 = _logical_T_635[0]; // @[Atomics.scala:41:8] wire [1:0] _logical_T_637 = {_logical_T_127, _logical_T_255}; // @[Atomics.scala:40:{32,55}, :41:12] wire [3:0] _logical_T_638 = _GEN[_lut_T] >> _logical_T_637; // @[Atomics.scala:39:15, :41:{8,12}] wire _logical_T_639 = _logical_T_638[0]; // @[Atomics.scala:41:8] wire [1:0] logical_lo_lo_lo_lo_lo_lo = {_logical_T_261, _logical_T_258}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_lo_lo_lo_hi = {_logical_T_267, _logical_T_264}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_lo_lo_lo = {logical_lo_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_lo_lo_hi_lo = {_logical_T_273, _logical_T_270}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_lo_lo_hi_hi = {_logical_T_279, _logical_T_276}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_lo_lo_hi = {logical_lo_lo_lo_lo_hi_hi, logical_lo_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_lo_lo_lo = {logical_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_lo_hi_lo_lo = {_logical_T_285, _logical_T_282}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_lo_hi_lo_hi = {_logical_T_291, _logical_T_288}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_lo_hi_lo = {logical_lo_lo_lo_hi_lo_hi, logical_lo_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_lo_hi_hi_lo = {_logical_T_297, _logical_T_294}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_lo_hi_hi_hi = {_logical_T_303, _logical_T_300}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_lo_hi_hi = {logical_lo_lo_lo_hi_hi_hi, logical_lo_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_lo_lo_hi = {logical_lo_lo_lo_hi_hi, logical_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_lo_lo_lo = {logical_lo_lo_lo_hi, logical_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_hi_lo_lo_lo = {_logical_T_309, _logical_T_306}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_hi_lo_lo_hi = {_logical_T_315, _logical_T_312}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_hi_lo_lo = {logical_lo_lo_hi_lo_lo_hi, logical_lo_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_hi_lo_hi_lo = {_logical_T_321, _logical_T_318}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_hi_lo_hi_hi = {_logical_T_327, _logical_T_324}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_hi_lo_hi = {logical_lo_lo_hi_lo_hi_hi, logical_lo_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_lo_hi_lo = {logical_lo_lo_hi_lo_hi, logical_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_hi_hi_lo_lo = {_logical_T_333, _logical_T_330}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_hi_hi_lo_hi = {_logical_T_339, _logical_T_336}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_hi_hi_lo = {logical_lo_lo_hi_hi_lo_hi, logical_lo_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_lo_hi_hi_hi_lo = {_logical_T_345, _logical_T_342}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_lo_hi_hi_hi_hi = {_logical_T_351, _logical_T_348}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_lo_hi_hi_hi = {logical_lo_lo_hi_hi_hi_hi, logical_lo_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_lo_hi_hi = {logical_lo_lo_hi_hi_hi, logical_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_lo_lo_hi = {logical_lo_lo_hi_hi, logical_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [31:0] logical_lo_lo = {logical_lo_lo_hi, logical_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_lo_lo_lo_lo = {_logical_T_357, _logical_T_354}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_lo_lo_lo_hi = {_logical_T_363, _logical_T_360}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_lo_lo_lo = {logical_lo_hi_lo_lo_lo_hi, logical_lo_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_lo_lo_hi_lo = {_logical_T_369, _logical_T_366}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_lo_lo_hi_hi = {_logical_T_375, _logical_T_372}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_lo_lo_hi = {logical_lo_hi_lo_lo_hi_hi, logical_lo_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_hi_lo_lo = {logical_lo_hi_lo_lo_hi, logical_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_lo_hi_lo_lo = {_logical_T_381, _logical_T_378}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_lo_hi_lo_hi = {_logical_T_387, _logical_T_384}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_lo_hi_lo = {logical_lo_hi_lo_hi_lo_hi, logical_lo_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_lo_hi_hi_lo = {_logical_T_393, _logical_T_390}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_lo_hi_hi_hi = {_logical_T_399, _logical_T_396}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_lo_hi_hi = {logical_lo_hi_lo_hi_hi_hi, logical_lo_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_hi_lo_hi = {logical_lo_hi_lo_hi_hi, logical_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_lo_hi_lo = {logical_lo_hi_lo_hi, logical_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_hi_lo_lo_lo = {_logical_T_405, _logical_T_402}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_hi_lo_lo_hi = {_logical_T_411, _logical_T_408}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_hi_lo_lo = {logical_lo_hi_hi_lo_lo_hi, logical_lo_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_hi_lo_hi_lo = {_logical_T_417, _logical_T_414}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_hi_lo_hi_hi = {_logical_T_423, _logical_T_420}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_hi_lo_hi = {logical_lo_hi_hi_lo_hi_hi, logical_lo_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_hi_hi_lo = {logical_lo_hi_hi_lo_hi, logical_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_hi_hi_lo_lo = {_logical_T_429, _logical_T_426}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_hi_hi_lo_hi = {_logical_T_435, _logical_T_432}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_hi_hi_lo = {logical_lo_hi_hi_hi_lo_hi, logical_lo_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_lo_hi_hi_hi_hi_lo = {_logical_T_441, _logical_T_438}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_lo_hi_hi_hi_hi_hi = {_logical_T_447, _logical_T_444}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_lo_hi_hi_hi_hi = {logical_lo_hi_hi_hi_hi_hi, logical_lo_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_lo_hi_hi_hi = {logical_lo_hi_hi_hi_hi, logical_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_lo_hi_hi = {logical_lo_hi_hi_hi, logical_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [31:0] logical_lo_hi = {logical_lo_hi_hi, logical_lo_hi_lo}; // @[Atomics.scala:40:20] wire [63:0] logical_lo = {logical_lo_hi, logical_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_lo_lo_lo_lo = {_logical_T_453, _logical_T_450}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_lo_lo_lo_hi = {_logical_T_459, _logical_T_456}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_lo_lo_lo = {logical_hi_lo_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_lo_lo_hi_lo = {_logical_T_465, _logical_T_462}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_lo_lo_hi_hi = {_logical_T_471, _logical_T_468}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_lo_lo_hi = {logical_hi_lo_lo_lo_hi_hi, logical_hi_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_lo_lo_lo = {logical_hi_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_lo_hi_lo_lo = {_logical_T_477, _logical_T_474}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_lo_hi_lo_hi = {_logical_T_483, _logical_T_480}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_lo_hi_lo = {logical_hi_lo_lo_hi_lo_hi, logical_hi_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_lo_hi_hi_lo = {_logical_T_489, _logical_T_486}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_lo_hi_hi_hi = {_logical_T_495, _logical_T_492}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_lo_hi_hi = {logical_hi_lo_lo_hi_hi_hi, logical_hi_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_lo_lo_hi = {logical_hi_lo_lo_hi_hi, logical_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_hi_lo_lo = {logical_hi_lo_lo_hi, logical_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_hi_lo_lo_lo = {_logical_T_501, _logical_T_498}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_hi_lo_lo_hi = {_logical_T_507, _logical_T_504}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_hi_lo_lo = {logical_hi_lo_hi_lo_lo_hi, logical_hi_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_hi_lo_hi_lo = {_logical_T_513, _logical_T_510}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_hi_lo_hi_hi = {_logical_T_519, _logical_T_516}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_hi_lo_hi = {logical_hi_lo_hi_lo_hi_hi, logical_hi_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_lo_hi_lo = {logical_hi_lo_hi_lo_hi, logical_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_hi_hi_lo_lo = {_logical_T_525, _logical_T_522}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_hi_hi_lo_hi = {_logical_T_531, _logical_T_528}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_hi_hi_lo = {logical_hi_lo_hi_hi_lo_hi, logical_hi_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_lo_hi_hi_hi_lo = {_logical_T_537, _logical_T_534}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_lo_hi_hi_hi_hi = {_logical_T_543, _logical_T_540}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_lo_hi_hi_hi = {logical_hi_lo_hi_hi_hi_hi, logical_hi_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_lo_hi_hi = {logical_hi_lo_hi_hi_hi, logical_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_hi_lo_hi = {logical_hi_lo_hi_hi, logical_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [31:0] logical_hi_lo = {logical_hi_lo_hi, logical_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_lo_lo_lo_lo = {_logical_T_549, _logical_T_546}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_lo_lo_lo_hi = {_logical_T_555, _logical_T_552}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_lo_lo_lo = {logical_hi_hi_lo_lo_lo_hi, logical_hi_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_lo_lo_hi_lo = {_logical_T_561, _logical_T_558}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_lo_lo_hi_hi = {_logical_T_567, _logical_T_564}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_lo_lo_hi = {logical_hi_hi_lo_lo_hi_hi, logical_hi_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_hi_lo_lo = {logical_hi_hi_lo_lo_hi, logical_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_lo_hi_lo_lo = {_logical_T_573, _logical_T_570}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_lo_hi_lo_hi = {_logical_T_579, _logical_T_576}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_lo_hi_lo = {logical_hi_hi_lo_hi_lo_hi, logical_hi_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_lo_hi_hi_lo = {_logical_T_585, _logical_T_582}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_lo_hi_hi_hi = {_logical_T_591, _logical_T_588}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_lo_hi_hi = {logical_hi_hi_lo_hi_hi_hi, logical_hi_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_hi_lo_hi = {logical_hi_hi_lo_hi_hi, logical_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_hi_hi_lo = {logical_hi_hi_lo_hi, logical_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_hi_lo_lo_lo = {_logical_T_597, _logical_T_594}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_hi_lo_lo_hi = {_logical_T_603, _logical_T_600}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_hi_lo_lo = {logical_hi_hi_hi_lo_lo_hi, logical_hi_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_hi_lo_hi_lo = {_logical_T_609, _logical_T_606}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_hi_lo_hi_hi = {_logical_T_615, _logical_T_612}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_hi_lo_hi = {logical_hi_hi_hi_lo_hi_hi, logical_hi_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_hi_hi_lo = {logical_hi_hi_hi_lo_hi, logical_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_hi_hi_lo_lo = {_logical_T_621, _logical_T_618}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_hi_hi_lo_hi = {_logical_T_627, _logical_T_624}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_hi_hi_lo = {logical_hi_hi_hi_hi_lo_hi, logical_hi_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20] wire [1:0] logical_hi_hi_hi_hi_hi_lo = {_logical_T_633, _logical_T_630}; // @[Atomics.scala:40:20, :41:8] wire [1:0] logical_hi_hi_hi_hi_hi_hi = {_logical_T_639, _logical_T_636}; // @[Atomics.scala:40:20, :41:8] wire [3:0] logical_hi_hi_hi_hi_hi = {logical_hi_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [7:0] logical_hi_hi_hi_hi = {logical_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [15:0] logical_hi_hi_hi = {logical_hi_hi_hi_hi, logical_hi_hi_hi_lo}; // @[Atomics.scala:40:20] wire [31:0] logical_hi_hi = {logical_hi_hi_hi, logical_hi_hi_lo}; // @[Atomics.scala:40:20] wire [63:0] logical_hi = {logical_hi_hi, logical_hi_lo}; // @[Atomics.scala:40:20] wire [127:0] logical = {logical_hi, logical_lo}; // @[Atomics.scala:40:20] wire [1:0] _select_T_1 = adder ? 2'h2 : {1'h0, _select_T}; // @[Atomics.scala:8:7, :10:14, :18:28, :48:{8,24}] wire [1:0] _select_WIRE_2 = _select_T_1; // @[Atomics.scala:45:42, :48:8] wire [7:0][1:0] _GEN_0 = {{2'h0}, {2'h0}, {2'h0}, {2'h0}, {2'h3}, {_select_WIRE_2}, {2'h1}, {2'h1}}; // @[Atomics.scala:45:{19,42}] wire [1:0] select = io_write_0 ? 2'h1 : _GEN_0[io_a_opcode_0]; // @[Atomics.scala:8:7, :45:19] wire [1:0] selects_0 = _selects_T ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_1 = _selects_T_1 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_2 = _selects_T_2 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_3 = _selects_T_3 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_4 = _selects_T_4 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_5 = _selects_T_5 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_6 = _selects_T_6 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_7 = _selects_T_7 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_8 = _selects_T_8 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_9 = _selects_T_9 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_10 = _selects_T_10 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_11 = _selects_T_11 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_12 = _selects_T_12 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_13 = _selects_T_13 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_14 = _selects_T_14 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [1:0] selects_15 = _selects_T_15 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}] wire [7:0] _io_data_out_T = io_data_in_0[7:0]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_0 = _io_data_out_T; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_1 = io_a_data_0[7:0]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_1 = _io_data_out_T_1; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_2 = sum[7:0]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_2 = _io_data_out_T_2; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_3 = logical[7:0]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_3 = _io_data_out_T_3; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_4 = io_data_in_0[15:8]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_1_0 = _io_data_out_T_4; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_5 = io_a_data_0[15:8]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_1_1 = _io_data_out_T_5; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_6 = sum[15:8]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_1_2 = _io_data_out_T_6; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_7 = logical[15:8]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_1_3 = _io_data_out_T_7; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_8 = io_data_in_0[23:16]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_2_0 = _io_data_out_T_8; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_9 = io_a_data_0[23:16]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_2_1 = _io_data_out_T_9; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_10 = sum[23:16]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_2_2 = _io_data_out_T_10; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_11 = logical[23:16]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_2_3 = _io_data_out_T_11; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_12 = io_data_in_0[31:24]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_3_0 = _io_data_out_T_12; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_13 = io_a_data_0[31:24]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_3_1 = _io_data_out_T_13; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_14 = sum[31:24]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_3_2 = _io_data_out_T_14; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_15 = logical[31:24]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_3_3 = _io_data_out_T_15; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_16 = io_data_in_0[39:32]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_4_0 = _io_data_out_T_16; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_17 = io_a_data_0[39:32]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_4_1 = _io_data_out_T_17; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_18 = sum[39:32]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_4_2 = _io_data_out_T_18; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_19 = logical[39:32]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_4_3 = _io_data_out_T_19; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_20 = io_data_in_0[47:40]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_5_0 = _io_data_out_T_20; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_21 = io_a_data_0[47:40]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_5_1 = _io_data_out_T_21; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_22 = sum[47:40]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_5_2 = _io_data_out_T_22; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_23 = logical[47:40]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_5_3 = _io_data_out_T_23; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_24 = io_data_in_0[55:48]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_6_0 = _io_data_out_T_24; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_25 = io_a_data_0[55:48]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_6_1 = _io_data_out_T_25; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_26 = sum[55:48]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_6_2 = _io_data_out_T_26; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_27 = logical[55:48]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_6_3 = _io_data_out_T_27; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_28 = io_data_in_0[63:56]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_7_0 = _io_data_out_T_28; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_29 = io_a_data_0[63:56]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_7_1 = _io_data_out_T_29; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_30 = sum[63:56]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_7_2 = _io_data_out_T_30; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_31 = logical[63:56]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_7_3 = _io_data_out_T_31; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_32 = io_data_in_0[71:64]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_8_0 = _io_data_out_T_32; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_33 = io_a_data_0[71:64]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_8_1 = _io_data_out_T_33; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_34 = sum[71:64]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_8_2 = _io_data_out_T_34; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_35 = logical[71:64]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_8_3 = _io_data_out_T_35; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_36 = io_data_in_0[79:72]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_9_0 = _io_data_out_T_36; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_37 = io_a_data_0[79:72]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_9_1 = _io_data_out_T_37; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_38 = sum[79:72]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_9_2 = _io_data_out_T_38; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_39 = logical[79:72]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_9_3 = _io_data_out_T_39; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_40 = io_data_in_0[87:80]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_10_0 = _io_data_out_T_40; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_41 = io_a_data_0[87:80]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_10_1 = _io_data_out_T_41; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_42 = sum[87:80]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_10_2 = _io_data_out_T_42; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_43 = logical[87:80]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_10_3 = _io_data_out_T_43; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_44 = io_data_in_0[95:88]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_11_0 = _io_data_out_T_44; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_45 = io_a_data_0[95:88]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_11_1 = _io_data_out_T_45; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_46 = sum[95:88]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_11_2 = _io_data_out_T_46; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_47 = logical[95:88]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_11_3 = _io_data_out_T_47; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_48 = io_data_in_0[103:96]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_12_0 = _io_data_out_T_48; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_49 = io_a_data_0[103:96]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_12_1 = _io_data_out_T_49; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_50 = sum[103:96]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_12_2 = _io_data_out_T_50; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_51 = logical[103:96]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_12_3 = _io_data_out_T_51; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_52 = io_data_in_0[111:104]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_13_0 = _io_data_out_T_52; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_53 = io_a_data_0[111:104]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_13_1 = _io_data_out_T_53; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_54 = sum[111:104]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_13_2 = _io_data_out_T_54; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_55 = logical[111:104]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_13_3 = _io_data_out_T_55; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_56 = io_data_in_0[119:112]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_14_0 = _io_data_out_T_56; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_57 = io_a_data_0[119:112]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_14_1 = _io_data_out_T_57; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_58 = sum[119:112]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_14_2 = _io_data_out_T_58; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_59 = logical[119:112]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_14_3 = _io_data_out_T_59; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_60 = io_data_in_0[127:120]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_15_0 = _io_data_out_T_60; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_61 = io_a_data_0[127:120]; // @[Atomics.scala:8:7, :59:59] wire [7:0] _io_data_out_WIRE_15_1 = _io_data_out_T_61; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_62 = sum[127:120]; // @[Atomics.scala:24:57, :59:59] wire [7:0] _io_data_out_WIRE_15_2 = _io_data_out_T_62; // @[Atomics.scala:59:{12,59}] wire [7:0] _io_data_out_T_63 = logical[127:120]; // @[Atomics.scala:40:20, :59:59] wire [7:0] _io_data_out_WIRE_15_3 = _io_data_out_T_63; // @[Atomics.scala:59:{12,59}] wire [3:0][7:0] _GEN_1 = {{_io_data_out_WIRE_1_3}, {_io_data_out_WIRE_1_2}, {_io_data_out_WIRE_1_1}, {_io_data_out_WIRE_1_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_2 = {{_io_data_out_WIRE_3}, {_io_data_out_WIRE_2}, {_io_data_out_WIRE_1}, {_io_data_out_WIRE_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_lo_lo_lo = {_GEN_1[selects_1], _GEN_2[selects_0]}; // @[Atomics.scala:57:47, :58:21] wire [3:0][7:0] _GEN_3 = {{_io_data_out_WIRE_3_3}, {_io_data_out_WIRE_3_2}, {_io_data_out_WIRE_3_1}, {_io_data_out_WIRE_3_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_4 = {{_io_data_out_WIRE_2_3}, {_io_data_out_WIRE_2_2}, {_io_data_out_WIRE_2_1}, {_io_data_out_WIRE_2_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_lo_lo_hi = {_GEN_3[selects_3], _GEN_4[selects_2]}; // @[Atomics.scala:57:47, :58:21] wire [31:0] io_data_out_lo_lo = {io_data_out_lo_lo_hi, io_data_out_lo_lo_lo}; // @[Atomics.scala:58:21] wire [3:0][7:0] _GEN_5 = {{_io_data_out_WIRE_5_3}, {_io_data_out_WIRE_5_2}, {_io_data_out_WIRE_5_1}, {_io_data_out_WIRE_5_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_6 = {{_io_data_out_WIRE_4_3}, {_io_data_out_WIRE_4_2}, {_io_data_out_WIRE_4_1}, {_io_data_out_WIRE_4_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_lo_hi_lo = {_GEN_5[selects_5], _GEN_6[selects_4]}; // @[Atomics.scala:57:47, :58:21] wire [3:0][7:0] _GEN_7 = {{_io_data_out_WIRE_7_3}, {_io_data_out_WIRE_7_2}, {_io_data_out_WIRE_7_1}, {_io_data_out_WIRE_7_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_8 = {{_io_data_out_WIRE_6_3}, {_io_data_out_WIRE_6_2}, {_io_data_out_WIRE_6_1}, {_io_data_out_WIRE_6_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_lo_hi_hi = {_GEN_7[selects_7], _GEN_8[selects_6]}; // @[Atomics.scala:57:47, :58:21] wire [31:0] io_data_out_lo_hi = {io_data_out_lo_hi_hi, io_data_out_lo_hi_lo}; // @[Atomics.scala:58:21] wire [63:0] io_data_out_lo = {io_data_out_lo_hi, io_data_out_lo_lo}; // @[Atomics.scala:58:21] wire [3:0][7:0] _GEN_9 = {{_io_data_out_WIRE_9_3}, {_io_data_out_WIRE_9_2}, {_io_data_out_WIRE_9_1}, {_io_data_out_WIRE_9_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_10 = {{_io_data_out_WIRE_8_3}, {_io_data_out_WIRE_8_2}, {_io_data_out_WIRE_8_1}, {_io_data_out_WIRE_8_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_hi_lo_lo = {_GEN_9[selects_9], _GEN_10[selects_8]}; // @[Atomics.scala:57:47, :58:21] wire [3:0][7:0] _GEN_11 = {{_io_data_out_WIRE_11_3}, {_io_data_out_WIRE_11_2}, {_io_data_out_WIRE_11_1}, {_io_data_out_WIRE_11_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_12 = {{_io_data_out_WIRE_10_3}, {_io_data_out_WIRE_10_2}, {_io_data_out_WIRE_10_1}, {_io_data_out_WIRE_10_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_hi_lo_hi = {_GEN_11[selects_11], _GEN_12[selects_10]}; // @[Atomics.scala:57:47, :58:21] wire [31:0] io_data_out_hi_lo = {io_data_out_hi_lo_hi, io_data_out_hi_lo_lo}; // @[Atomics.scala:58:21] wire [3:0][7:0] _GEN_13 = {{_io_data_out_WIRE_13_3}, {_io_data_out_WIRE_13_2}, {_io_data_out_WIRE_13_1}, {_io_data_out_WIRE_13_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_14 = {{_io_data_out_WIRE_12_3}, {_io_data_out_WIRE_12_2}, {_io_data_out_WIRE_12_1}, {_io_data_out_WIRE_12_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_hi_hi_lo = {_GEN_13[selects_13], _GEN_14[selects_12]}; // @[Atomics.scala:57:47, :58:21] wire [3:0][7:0] _GEN_15 = {{_io_data_out_WIRE_15_3}, {_io_data_out_WIRE_15_2}, {_io_data_out_WIRE_15_1}, {_io_data_out_WIRE_15_0}}; // @[Atomics.scala:58:21, :59:12] wire [3:0][7:0] _GEN_16 = {{_io_data_out_WIRE_14_3}, {_io_data_out_WIRE_14_2}, {_io_data_out_WIRE_14_1}, {_io_data_out_WIRE_14_0}}; // @[Atomics.scala:58:21, :59:12] wire [15:0] io_data_out_hi_hi_hi = {_GEN_15[selects_15], _GEN_16[selects_14]}; // @[Atomics.scala:57:47, :58:21] wire [31:0] io_data_out_hi_hi = {io_data_out_hi_hi_hi, io_data_out_hi_hi_lo}; // @[Atomics.scala:58:21] wire [63:0] io_data_out_hi = {io_data_out_hi_hi, io_data_out_hi_lo}; // @[Atomics.scala:58:21] assign _io_data_out_T_64 = {io_data_out_hi, io_data_out_lo}; // @[Atomics.scala:58:21] assign io_data_out_0 = _io_data_out_T_64; // @[Atomics.scala:8:7, :58:21] assign io_data_out = io_data_out_0; // @[Atomics.scala:8:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_173 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_190 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_173( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_190 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_8 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_16 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_8 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<5>(0h11), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0h9), io.in.bits.egress_id) node _T_2 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _T_3 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _T_5 = or(_T, _T_1) node _T_6 = or(_T_5, _T_2) node _T_7 = or(_T_6, _T_3) node _T_8 = or(_T_7, _T_4) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = and(io.in.valid, _T_9) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_11, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<3>(0h4) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h2) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0h9), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<4>(0hc), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0h8), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0hb), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0h9), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h4)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] node _T_15 = and(io.in.ready, io.in.valid) node _T_16 = and(_T_15, io.in.bits.head) node _T_17 = and(_T_16, at_dest) when _T_17 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) node _T_18 = eq(UInt<3>(0h5), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_19 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_20 = and(route_q.io.enq.valid, _T_19) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_17 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_8 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] node _T_25 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_26 = and(vcalloc_q.io.enq.valid, _T_25) node _T_27 = eq(_T_26, UInt<1>(0h0)) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node c_lo = cat(c_lo_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _c_T = cat(c_hi, c_lo) node _c_T_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_lo_hi_1 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node c_lo_1 = cat(c_lo_hi_1, io.out_credit_available.`0`[0]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node c_hi_1 = cat(c_hi_hi_1, io.out_credit_available.`0`[3]) node _c_T_2 = cat(c_hi_1, c_lo_1) node _c_T_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_channel_oh_0 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 5, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_10 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1
module IngressUnit_8( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = io_in_bits_egress_id == 5'h9; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'hB; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 4'hC : 4'h0) | {_route_buffer_io_enq_bits_flow_egress_node_id_T_13, 3'h0} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hB : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire [1:0] route_buffer_io_enq_bits_flow_egress_node_id = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_13}; // @[IngressUnit.scala:30:72, :45:50] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 == 4'h4; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 != 4'h4; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_229 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_229( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLAsyncCrossingSource_a9d32s1k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_36 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} invalidate nodeOut.e.safe.sink_reset_n invalidate nodeOut.e.safe.source_reset_n invalidate nodeOut.e.safe.widx_valid invalidate nodeOut.e.safe.ridx_valid invalidate nodeOut.e.widx invalidate nodeOut.e.ridx invalidate nodeOut.e.mem[0].sink invalidate nodeOut.d.safe.sink_reset_n invalidate nodeOut.d.safe.source_reset_n invalidate nodeOut.d.safe.widx_valid invalidate nodeOut.d.safe.ridx_valid invalidate nodeOut.d.widx invalidate nodeOut.d.ridx invalidate nodeOut.d.mem[0].corrupt invalidate nodeOut.d.mem[0].data invalidate nodeOut.d.mem[0].denied invalidate nodeOut.d.mem[0].sink invalidate nodeOut.d.mem[0].source invalidate nodeOut.d.mem[0].size invalidate nodeOut.d.mem[0].param invalidate nodeOut.d.mem[0].opcode invalidate nodeOut.c.safe.sink_reset_n invalidate nodeOut.c.safe.source_reset_n invalidate nodeOut.c.safe.widx_valid invalidate nodeOut.c.safe.ridx_valid invalidate nodeOut.c.widx invalidate nodeOut.c.ridx invalidate nodeOut.c.mem[0].corrupt invalidate nodeOut.c.mem[0].data invalidate nodeOut.c.mem[0].address invalidate nodeOut.c.mem[0].source invalidate nodeOut.c.mem[0].size invalidate nodeOut.c.mem[0].param invalidate nodeOut.c.mem[0].opcode invalidate nodeOut.b.safe.sink_reset_n invalidate nodeOut.b.safe.source_reset_n invalidate nodeOut.b.safe.widx_valid invalidate nodeOut.b.safe.ridx_valid invalidate nodeOut.b.widx invalidate nodeOut.b.ridx invalidate nodeOut.b.mem[0].corrupt invalidate nodeOut.b.mem[0].data invalidate nodeOut.b.mem[0].mask invalidate nodeOut.b.mem[0].address invalidate nodeOut.b.mem[0].source invalidate nodeOut.b.mem[0].size invalidate nodeOut.b.mem[0].param invalidate nodeOut.b.mem[0].opcode invalidate nodeOut.a.safe.sink_reset_n invalidate nodeOut.a.safe.source_reset_n invalidate nodeOut.a.safe.widx_valid invalidate nodeOut.a.safe.ridx_valid invalidate nodeOut.a.widx invalidate nodeOut.a.ridx invalidate nodeOut.a.mem[0].corrupt invalidate nodeOut.a.mem[0].data invalidate nodeOut.a.mem[0].mask invalidate nodeOut.a.mem[0].address invalidate nodeOut.a.mem[0].source invalidate nodeOut.a.mem[0].size invalidate nodeOut.a.mem[0].param invalidate nodeOut.a.mem[0].opcode connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_source of AsyncQueueSource_TLBundleA_a9d32s1k1z2u connect nodeOut_a_source.clock, clock connect nodeOut_a_source.reset, reset connect nodeOut_a_source.io.enq, nodeIn.a connect nodeOut_a_source.io.async.safe.sink_reset_n, nodeOut.a.safe.sink_reset_n connect nodeOut.a.safe.source_reset_n, nodeOut_a_source.io.async.safe.source_reset_n connect nodeOut.a.safe.widx_valid, nodeOut_a_source.io.async.safe.widx_valid connect nodeOut_a_source.io.async.safe.ridx_valid, nodeOut.a.safe.ridx_valid connect nodeOut.a.widx, nodeOut_a_source.io.async.widx connect nodeOut_a_source.io.async.ridx, nodeOut.a.ridx connect nodeOut.a.mem, nodeOut_a_source.io.async.mem inst nodeIn_d_sink of AsyncQueueSink_TLBundleD_a9d32s1k1z2u connect nodeIn_d_sink.clock, clock connect nodeIn_d_sink.reset, reset connect nodeIn_d_sink.io.async, nodeOut.d connect nodeIn.d.bits, nodeIn_d_sink.io.deq.bits connect nodeIn.d.valid, nodeIn_d_sink.io.deq.valid connect nodeIn_d_sink.io.deq.ready, nodeIn.d.ready node _T = and(nodeIn.a.valid, nodeIn.a.ready) node _T_1 = eq(nodeIn.a.ready, UInt<1>(0h0)) node _T_2 = and(nodeIn.a.valid, _T_1) node _T_3 = eq(nodeIn.a.valid, UInt<1>(0h0)) node _T_4 = and(_T_3, nodeIn.a.ready) node _T_5 = eq(nodeIn.a.valid, UInt<1>(0h0)) node _T_6 = eq(nodeIn.a.ready, UInt<1>(0h0)) node _T_7 = and(_T_5, _T_6) node _T_8 = and(nodeIn.d.valid, nodeIn.d.ready) node _T_9 = eq(nodeIn.d.ready, UInt<1>(0h0)) node _T_10 = and(nodeIn.d.valid, _T_9) node _T_11 = eq(nodeIn.d.valid, UInt<1>(0h0)) node _T_12 = and(_T_11, nodeIn.d.ready) node _T_13 = eq(nodeIn.d.valid, UInt<1>(0h0)) node _T_14 = eq(nodeIn.d.ready, UInt<1>(0h0)) node _T_15 = and(_T_13, _T_14) wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect nodeOut.b.ridx, UInt<1>(0h0) connect nodeOut.c.widx, UInt<1>(0h0) connect nodeOut.e.widx, UInt<1>(0h0)
module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9] wire auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9] wire auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_b_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeOut_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeOut_b_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_c_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_b_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_c_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] auto_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_mem_0_mask = 4'hF; // @[MixedNode.scala:542:17] wire auto_in_a_bits_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_denied = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_denied = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_in_a_bits_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_a_mem_0_size = 2'h2; // @[MixedNode.scala:542:17] wire [2:0] auto_in_a_bits_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17] wire nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_widx; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_ridx; // @[MixedNode.scala:542:17] wire nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17] wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] TLMonitor_36 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_async_mem_0_opcode (nodeOut_a_mem_0_opcode), .io_async_mem_0_address (nodeOut_a_mem_0_address), .io_async_mem_0_data (nodeOut_a_mem_0_data), .io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17] .io_async_widx (nodeOut_a_widx), .io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17] .io_async_safe_widx_valid (nodeOut_a_safe_widx_valid), .io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n), .io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17] ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt), .io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17] .io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17] .io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17] .io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17] .io_async_ridx (nodeOut_d_ridx), .io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17] .io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid), .io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17] .io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17] .io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SinkA : input clock : Clock input reset : Reset output io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}}, flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, pb_beat : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}} inst putbuffer of ListBuffer_PutBufferAEntry_q40_e40 connect putbuffer.clock, clock connect putbuffer.reset, reset regreset lists : UInt<40>, clock, reset, UInt<40>(0h0) wire lists_set : UInt<40> connect lists_set, UInt<40>(0h0) wire lists_clr : UInt<40> connect lists_clr, UInt<40>(0h0) node _lists_T = or(lists, lists_set) node _lists_T_1 = not(lists_clr) node _lists_T_2 = and(_lists_T, _lists_T_1) connect lists, _lists_T_2 node _free_T = andr(lists) node free = eq(_free_T, UInt<1>(0h0)) node _freeOH_T = not(lists) node _freeOH_T_1 = shl(_freeOH_T, 1) node _freeOH_T_2 = bits(_freeOH_T_1, 39, 0) node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2) node _freeOH_T_4 = shl(_freeOH_T_3, 2) node _freeOH_T_5 = bits(_freeOH_T_4, 39, 0) node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5) node _freeOH_T_7 = shl(_freeOH_T_6, 4) node _freeOH_T_8 = bits(_freeOH_T_7, 39, 0) node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8) node _freeOH_T_10 = shl(_freeOH_T_9, 8) node _freeOH_T_11 = bits(_freeOH_T_10, 39, 0) node _freeOH_T_12 = or(_freeOH_T_9, _freeOH_T_11) node _freeOH_T_13 = shl(_freeOH_T_12, 16) node _freeOH_T_14 = bits(_freeOH_T_13, 39, 0) node _freeOH_T_15 = or(_freeOH_T_12, _freeOH_T_14) node _freeOH_T_16 = shl(_freeOH_T_15, 32) node _freeOH_T_17 = bits(_freeOH_T_16, 39, 0) node _freeOH_T_18 = or(_freeOH_T_15, _freeOH_T_17) node _freeOH_T_19 = bits(_freeOH_T_18, 39, 0) node _freeOH_T_20 = shl(_freeOH_T_19, 1) node _freeOH_T_21 = not(_freeOH_T_20) node _freeOH_T_22 = not(lists) node freeOH = and(_freeOH_T_21, _freeOH_T_22) node freeIdx_hi = bits(freeOH, 40, 32) node freeIdx_lo = bits(freeOH, 31, 0) node _freeIdx_T = orr(freeIdx_hi) node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo) node freeIdx_hi_1 = bits(_freeIdx_T_1, 31, 16) node freeIdx_lo_1 = bits(_freeIdx_T_1, 15, 0) node _freeIdx_T_2 = orr(freeIdx_hi_1) node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1) node freeIdx_hi_2 = bits(_freeIdx_T_3, 15, 8) node freeIdx_lo_2 = bits(_freeIdx_T_3, 7, 0) node _freeIdx_T_4 = orr(freeIdx_hi_2) node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2) node freeIdx_hi_3 = bits(_freeIdx_T_5, 7, 4) node freeIdx_lo_3 = bits(_freeIdx_T_5, 3, 0) node _freeIdx_T_6 = orr(freeIdx_hi_3) node _freeIdx_T_7 = or(freeIdx_hi_3, freeIdx_lo_3) node freeIdx_hi_4 = bits(_freeIdx_T_7, 3, 2) node freeIdx_lo_4 = bits(_freeIdx_T_7, 1, 0) node _freeIdx_T_8 = orr(freeIdx_hi_4) node _freeIdx_T_9 = or(freeIdx_hi_4, freeIdx_lo_4) node _freeIdx_T_10 = bits(_freeIdx_T_9, 1, 1) node _freeIdx_T_11 = cat(_freeIdx_T_8, _freeIdx_T_10) node _freeIdx_T_12 = cat(_freeIdx_T_6, _freeIdx_T_11) node _freeIdx_T_13 = cat(_freeIdx_T_4, _freeIdx_T_12) node _freeIdx_T_14 = cat(_freeIdx_T_2, _freeIdx_T_13) node freeIdx = cat(_freeIdx_T, _freeIdx_T_14) node _first_T = and(io.a.ready, io.a.valid) node _first_beats1_decode_T = dshl(UInt<6>(0h3f), io.a.bits.size) node _first_beats1_decode_T_1 = bits(_first_beats1_decode_T, 5, 0) node _first_beats1_decode_T_2 = not(_first_beats1_decode_T_1) node first_beats1_decode = shr(_first_beats1_decode_T_2, 3) node _first_beats1_opdata_T = bits(io.a.bits.opcode, 2, 2) node first_beats1_opdata = eq(_first_beats1_opdata_T, UInt<1>(0h0)) node first_beats1 = mux(first_beats1_opdata, first_beats1_decode, UInt<1>(0h0)) regreset first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _first_counter1_T = sub(first_counter, UInt<1>(0h1)) node first_counter1 = tail(_first_counter1_T, 1) node first = eq(first_counter, UInt<1>(0h0)) node _first_last_T = eq(first_counter, UInt<1>(0h1)) node _first_last_T_1 = eq(first_beats1, UInt<1>(0h0)) node first_last = or(_first_last_T, _first_last_T_1) node first_done = and(first_last, _first_T) node _first_count_T = not(first_counter1) node first_count = and(first_beats1, _first_count_T) when _first_T : node _first_counter_T = mux(first, first_beats1, first_counter1) connect first_counter, _first_counter_T node _hasData_opdata_T = bits(io.a.bits.opcode, 2, 2) node hasData = eq(_hasData_opdata_T, UInt<1>(0h0)) node _req_block_T = eq(io.req.ready, UInt<1>(0h0)) node req_block = and(first, _req_block_T) node _buf_block_T = eq(putbuffer.io.push.ready, UInt<1>(0h0)) node buf_block = and(hasData, _buf_block_T) node _set_block_T = and(hasData, first) node _set_block_T_1 = eq(free, UInt<1>(0h0)) node set_block = and(_set_block_T, _set_block_T_1) node _T = and(io.a.valid, req_block) node _T_1 = and(io.a.valid, buf_block) node _T_2 = and(io.a.valid, set_block) node _io_a_ready_T = eq(req_block, UInt<1>(0h0)) node _io_a_ready_T_1 = eq(buf_block, UInt<1>(0h0)) node _io_a_ready_T_2 = and(_io_a_ready_T, _io_a_ready_T_1) node _io_a_ready_T_3 = eq(set_block, UInt<1>(0h0)) node _io_a_ready_T_4 = and(_io_a_ready_T_2, _io_a_ready_T_3) connect io.a.ready, _io_a_ready_T_4 node _io_req_valid_T = and(io.a.valid, first) node _io_req_valid_T_1 = eq(buf_block, UInt<1>(0h0)) node _io_req_valid_T_2 = and(_io_req_valid_T, _io_req_valid_T_1) node _io_req_valid_T_3 = eq(set_block, UInt<1>(0h0)) node _io_req_valid_T_4 = and(_io_req_valid_T_2, _io_req_valid_T_3) connect io.req.valid, _io_req_valid_T_4 node _putbuffer_io_push_valid_T = and(io.a.valid, hasData) node _putbuffer_io_push_valid_T_1 = eq(req_block, UInt<1>(0h0)) node _putbuffer_io_push_valid_T_2 = and(_putbuffer_io_push_valid_T, _putbuffer_io_push_valid_T_1) node _putbuffer_io_push_valid_T_3 = eq(set_block, UInt<1>(0h0)) node _putbuffer_io_push_valid_T_4 = and(_putbuffer_io_push_valid_T_2, _putbuffer_io_push_valid_T_3) connect putbuffer.io.push.valid, _putbuffer_io_push_valid_T_4 node _T_3 = and(io.a.valid, first) node _T_4 = and(_T_3, hasData) node _T_5 = eq(req_block, UInt<1>(0h0)) node _T_6 = and(_T_4, _T_5) node _T_7 = eq(buf_block, UInt<1>(0h0)) node _T_8 = and(_T_6, _T_7) when _T_8 : connect lists_set, freeOH node _offset_T = bits(io.a.bits.address, 0, 0) node _offset_T_1 = bits(io.a.bits.address, 1, 1) node _offset_T_2 = bits(io.a.bits.address, 2, 2) node _offset_T_3 = bits(io.a.bits.address, 3, 3) node _offset_T_4 = bits(io.a.bits.address, 4, 4) node _offset_T_5 = bits(io.a.bits.address, 5, 5) node _offset_T_6 = bits(io.a.bits.address, 6, 6) node _offset_T_7 = bits(io.a.bits.address, 7, 7) node _offset_T_8 = bits(io.a.bits.address, 8, 8) node _offset_T_9 = bits(io.a.bits.address, 9, 9) node _offset_T_10 = bits(io.a.bits.address, 10, 10) node _offset_T_11 = bits(io.a.bits.address, 11, 11) node _offset_T_12 = bits(io.a.bits.address, 12, 12) node _offset_T_13 = bits(io.a.bits.address, 13, 13) node _offset_T_14 = bits(io.a.bits.address, 14, 14) node _offset_T_15 = bits(io.a.bits.address, 15, 15) node _offset_T_16 = bits(io.a.bits.address, 16, 16) node _offset_T_17 = bits(io.a.bits.address, 17, 17) node _offset_T_18 = bits(io.a.bits.address, 18, 18) node _offset_T_19 = bits(io.a.bits.address, 19, 19) node _offset_T_20 = bits(io.a.bits.address, 20, 20) node _offset_T_21 = bits(io.a.bits.address, 21, 21) node _offset_T_22 = bits(io.a.bits.address, 22, 22) node _offset_T_23 = bits(io.a.bits.address, 23, 23) node _offset_T_24 = bits(io.a.bits.address, 24, 24) node _offset_T_25 = bits(io.a.bits.address, 25, 25) node _offset_T_26 = bits(io.a.bits.address, 26, 26) node _offset_T_27 = bits(io.a.bits.address, 27, 27) node offset_lo_lo_lo_hi = cat(_offset_T_2, _offset_T_1) node offset_lo_lo_lo = cat(offset_lo_lo_lo_hi, _offset_T) node offset_lo_lo_hi_lo = cat(_offset_T_4, _offset_T_3) node offset_lo_lo_hi_hi = cat(_offset_T_6, _offset_T_5) node offset_lo_lo_hi = cat(offset_lo_lo_hi_hi, offset_lo_lo_hi_lo) node offset_lo_lo = cat(offset_lo_lo_hi, offset_lo_lo_lo) node offset_lo_hi_lo_hi = cat(_offset_T_9, _offset_T_8) node offset_lo_hi_lo = cat(offset_lo_hi_lo_hi, _offset_T_7) node offset_lo_hi_hi_lo = cat(_offset_T_11, _offset_T_10) node offset_lo_hi_hi_hi = cat(_offset_T_13, _offset_T_12) node offset_lo_hi_hi = cat(offset_lo_hi_hi_hi, offset_lo_hi_hi_lo) node offset_lo_hi = cat(offset_lo_hi_hi, offset_lo_hi_lo) node offset_lo = cat(offset_lo_hi, offset_lo_lo) node offset_hi_lo_lo_hi = cat(_offset_T_16, _offset_T_15) node offset_hi_lo_lo = cat(offset_hi_lo_lo_hi, _offset_T_14) node offset_hi_lo_hi_lo = cat(_offset_T_18, _offset_T_17) node offset_hi_lo_hi_hi = cat(_offset_T_20, _offset_T_19) node offset_hi_lo_hi = cat(offset_hi_lo_hi_hi, offset_hi_lo_hi_lo) node offset_hi_lo = cat(offset_hi_lo_hi, offset_hi_lo_lo) node offset_hi_hi_lo_hi = cat(_offset_T_23, _offset_T_22) node offset_hi_hi_lo = cat(offset_hi_hi_lo_hi, _offset_T_21) node offset_hi_hi_hi_lo = cat(_offset_T_25, _offset_T_24) node offset_hi_hi_hi_hi = cat(_offset_T_27, _offset_T_26) node offset_hi_hi_hi = cat(offset_hi_hi_hi_hi, offset_hi_hi_hi_lo) node offset_hi_hi = cat(offset_hi_hi_hi, offset_hi_hi_lo) node offset_hi = cat(offset_hi_hi, offset_hi_lo) node offset = cat(offset_hi, offset_lo) node set = shr(offset, 6) node tag = shr(set, 10) node tag_1 = bits(tag, 11, 0) node set_1 = bits(set, 9, 0) node offset_1 = bits(offset, 5, 0) reg put_r : UInt<6>, clock when first : connect put_r, freeIdx node put = mux(first, freeIdx, put_r) wire _WIRE : UInt<1>[3] connect _WIRE[0], UInt<1>(0h1) connect _WIRE[1], UInt<1>(0h0) connect _WIRE[2], UInt<1>(0h0) connect io.req.bits.prio, _WIRE connect io.req.bits.control, UInt<1>(0h0) connect io.req.bits.opcode, io.a.bits.opcode connect io.req.bits.param, io.a.bits.param connect io.req.bits.size, io.a.bits.size connect io.req.bits.source, io.a.bits.source connect io.req.bits.offset, offset_1 connect io.req.bits.set, set_1 connect io.req.bits.tag, tag_1 connect io.req.bits.put, put connect putbuffer.io.push.bits.index, put connect putbuffer.io.push.bits.data.data, io.a.bits.data connect putbuffer.io.push.bits.data.mask, io.a.bits.mask connect putbuffer.io.push.bits.data.corrupt, io.a.bits.corrupt connect putbuffer.io.pop.bits, io.pb_pop.bits.index node _putbuffer_io_pop_valid_T = and(io.pb_pop.ready, io.pb_pop.valid) connect putbuffer.io.pop.valid, _putbuffer_io_pop_valid_T node _io_pb_pop_ready_T = dshr(putbuffer.io.valid, io.pb_pop.bits.index) node _io_pb_pop_ready_T_1 = bits(_io_pb_pop_ready_T, 0, 0) connect io.pb_pop.ready, _io_pb_pop_ready_T_1 connect io.pb_beat, putbuffer.io.data node _T_9 = and(io.pb_pop.ready, io.pb_pop.valid) node _T_10 = and(_T_9, io.pb_pop.bits.last) when _T_10 : node lists_clr_shiftAmount = bits(io.pb_pop.bits.index, 5, 0) node _lists_clr_T = dshl(UInt<1>(0h1), lists_clr_shiftAmount) node _lists_clr_T_1 = bits(_lists_clr_T, 39, 0) connect lists_clr, _lists_clr_T_1
module SinkA( // @[SinkA.scala:38:7] input clock, // @[SinkA.scala:38:7] input reset, // @[SinkA.scala:38:7] input io_req_ready, // @[SinkA.scala:40:14] output io_req_valid, // @[SinkA.scala:40:14] output [2:0] io_req_bits_opcode, // @[SinkA.scala:40:14] output [2:0] io_req_bits_param, // @[SinkA.scala:40:14] output [2:0] io_req_bits_size, // @[SinkA.scala:40:14] output [4:0] io_req_bits_source, // @[SinkA.scala:40:14] output [11:0] io_req_bits_tag, // @[SinkA.scala:40:14] output [5:0] io_req_bits_offset, // @[SinkA.scala:40:14] output [5:0] io_req_bits_put, // @[SinkA.scala:40:14] output [9:0] io_req_bits_set, // @[SinkA.scala:40:14] output io_a_ready, // @[SinkA.scala:40:14] input io_a_valid, // @[SinkA.scala:40:14] input [2:0] io_a_bits_opcode, // @[SinkA.scala:40:14] input [2:0] io_a_bits_param, // @[SinkA.scala:40:14] input [2:0] io_a_bits_size, // @[SinkA.scala:40:14] input [4:0] io_a_bits_source, // @[SinkA.scala:40:14] input [31:0] io_a_bits_address, // @[SinkA.scala:40:14] input [7:0] io_a_bits_mask, // @[SinkA.scala:40:14] input [63:0] io_a_bits_data, // @[SinkA.scala:40:14] input io_a_bits_corrupt, // @[SinkA.scala:40:14] output io_pb_pop_ready, // @[SinkA.scala:40:14] input io_pb_pop_valid, // @[SinkA.scala:40:14] input [5:0] io_pb_pop_bits_index, // @[SinkA.scala:40:14] input io_pb_pop_bits_last, // @[SinkA.scala:40:14] output [63:0] io_pb_beat_data, // @[SinkA.scala:40:14] output [7:0] io_pb_beat_mask, // @[SinkA.scala:40:14] output io_pb_beat_corrupt // @[SinkA.scala:40:14] ); wire _putbuffer_io_push_ready; // @[SinkA.scala:51:25] wire [39:0] _putbuffer_io_valid; // @[SinkA.scala:51:25] wire io_req_ready_0 = io_req_ready; // @[SinkA.scala:38:7] wire io_a_valid_0 = io_a_valid; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_opcode_0 = io_a_bits_opcode; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_param_0 = io_a_bits_param; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_size_0 = io_a_bits_size; // @[SinkA.scala:38:7] wire [4:0] io_a_bits_source_0 = io_a_bits_source; // @[SinkA.scala:38:7] wire [31:0] io_a_bits_address_0 = io_a_bits_address; // @[SinkA.scala:38:7] wire [7:0] io_a_bits_mask_0 = io_a_bits_mask; // @[SinkA.scala:38:7] wire [63:0] io_a_bits_data_0 = io_a_bits_data; // @[SinkA.scala:38:7] wire io_a_bits_corrupt_0 = io_a_bits_corrupt; // @[SinkA.scala:38:7] wire io_pb_pop_valid_0 = io_pb_pop_valid; // @[SinkA.scala:38:7] wire [5:0] io_pb_pop_bits_index_0 = io_pb_pop_bits_index; // @[SinkA.scala:38:7] wire io_pb_pop_bits_last_0 = io_pb_pop_bits_last; // @[SinkA.scala:38:7] wire io_req_bits_prio_1 = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_prio_2 = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_control = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_prio_0 = 1'h1; // @[SinkA.scala:38:7] wire _io_req_valid_T_4; // @[SinkA.scala:79:50] wire [11:0] tag_1; // @[Parameters.scala:217:9] wire [5:0] offset_1; // @[Parameters.scala:217:50] wire [5:0] put; // @[SinkA.scala:84:16] wire [9:0] set_1; // @[Parameters.scala:217:28] wire _io_a_ready_T_4; // @[SinkA.scala:78:39] wire [2:0] io_req_bits_opcode_0 = io_a_bits_opcode_0; // @[SinkA.scala:38:7] wire [2:0] io_req_bits_param_0 = io_a_bits_param_0; // @[SinkA.scala:38:7] wire [2:0] io_req_bits_size_0 = io_a_bits_size_0; // @[SinkA.scala:38:7] wire [4:0] io_req_bits_source_0 = io_a_bits_source_0; // @[SinkA.scala:38:7] wire _io_pb_pop_ready_T_1; // @[SinkA.scala:105:40] wire [5:0] lists_clr_shiftAmount = io_pb_pop_bits_index_0; // @[OneHot.scala:64:49] wire [11:0] io_req_bits_tag_0; // @[SinkA.scala:38:7] wire [5:0] io_req_bits_offset_0; // @[SinkA.scala:38:7] wire [5:0] io_req_bits_put_0; // @[SinkA.scala:38:7] wire [9:0] io_req_bits_set_0; // @[SinkA.scala:38:7] wire io_req_valid_0; // @[SinkA.scala:38:7] wire io_a_ready_0; // @[SinkA.scala:38:7] wire io_pb_pop_ready_0; // @[SinkA.scala:38:7] wire [63:0] io_pb_beat_data_0; // @[SinkA.scala:38:7] wire [7:0] io_pb_beat_mask_0; // @[SinkA.scala:38:7] wire io_pb_beat_corrupt_0; // @[SinkA.scala:38:7] reg [39:0] lists; // @[SinkA.scala:52:22] wire [39:0] lists_set; // @[SinkA.scala:54:27] wire [39:0] lists_clr; // @[SinkA.scala:55:27] wire [39:0] _lists_T = lists | lists_set; // @[SinkA.scala:52:22, :54:27, :56:19] wire [39:0] _lists_T_1 = ~lists_clr; // @[SinkA.scala:55:27, :56:34] wire [39:0] _lists_T_2 = _lists_T & _lists_T_1; // @[SinkA.scala:56:{19,32,34}] wire _free_T = &lists; // @[SinkA.scala:52:22, :58:21] wire free = ~_free_T; // @[SinkA.scala:58:{14,21}] wire [39:0] _freeOH_T = ~lists; // @[SinkA.scala:52:22, :59:25] wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48] wire [39:0] _freeOH_T_2 = _freeOH_T_1[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}] wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_5 = _freeOH_T_4[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}] wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_8 = _freeOH_T_7[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}] wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_11 = _freeOH_T_10[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}] wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_14 = _freeOH_T_13[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}] wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_17 = _freeOH_T_16[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_18 = _freeOH_T_15 | _freeOH_T_17; // @[package.scala:253:{43,53}] wire [39:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17] wire [40:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17] wire [40:0] _freeOH_T_21 = ~_freeOH_T_20; // @[SinkA.scala:59:{16,33}] wire [39:0] _freeOH_T_22 = ~lists; // @[SinkA.scala:52:22, :59:{25,41}] wire [40:0] freeOH = {1'h0, _freeOH_T_21[39:0] & _freeOH_T_22}; // @[SinkA.scala:59:{16,39,41}] wire [8:0] freeIdx_hi = freeOH[40:32]; // @[OneHot.scala:30:18] wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18] wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14] wire [31:0] _freeIdx_T_1 = {23'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_8 = |freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 | freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}] wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}] wire _first_T = io_a_ready_0 & io_a_valid_0; // @[Decoupled.scala:51:35] wire [12:0] _first_beats1_decode_T = 13'h3F << io_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _first_beats1_decode_T_1 = _first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _first_beats1_decode_T_2 = ~_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] first_beats1_decode = _first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _first_beats1_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37] wire _hasData_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37] wire first_beats1_opdata = ~_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] first_beats1 = first_beats1_opdata ? first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] first_counter; // @[Edges.scala:229:27] wire [3:0] _first_counter1_T = {1'h0, first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] first_counter1 = _first_counter1_T[2:0]; // @[Edges.scala:230:28] wire first = first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _first_last_T = first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _first_last_T_1 = first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire first_last = _first_last_T | _first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire first_done = first_last & _first_T; // @[Decoupled.scala:51:35] wire [2:0] _first_count_T = ~first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] first_count = first_beats1 & _first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _first_counter_T = first ? first_beats1 : first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire _req_block_T = ~io_req_ready_0; // @[SinkA.scala:38:7, :70:28] wire req_block = first & _req_block_T; // @[Edges.scala:231:25] wire _buf_block_T = ~_putbuffer_io_push_ready; // @[SinkA.scala:51:25, :71:30] wire buf_block = hasData & _buf_block_T; // @[Edges.scala:92:28] wire _set_block_T = hasData & first; // @[Edges.scala:92:28, :231:25] wire _set_block_T_1 = ~free; // @[SinkA.scala:58:14, :72:39] wire set_block = _set_block_T & _set_block_T_1; // @[SinkA.scala:72:{27,36,39}] wire _io_a_ready_T = ~req_block; // @[SinkA.scala:70:25, :78:14] wire _io_a_ready_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28] wire _io_a_ready_T_2 = _io_a_ready_T & _io_a_ready_T_1; // @[SinkA.scala:78:{14,25,28}] wire _io_a_ready_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42] assign _io_a_ready_T_4 = _io_a_ready_T_2 & _io_a_ready_T_3; // @[SinkA.scala:78:{25,39,42}] assign io_a_ready_0 = _io_a_ready_T_4; // @[SinkA.scala:38:7, :78:39] wire _io_req_valid_T = io_a_valid_0 & first; // @[Edges.scala:231:25] wire _io_req_valid_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28, :79:39] wire _io_req_valid_T_2 = _io_req_valid_T & _io_req_valid_T_1; // @[SinkA.scala:79:{27,36,39}] wire _io_req_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :79:53] assign _io_req_valid_T_4 = _io_req_valid_T_2 & _io_req_valid_T_3; // @[SinkA.scala:79:{36,50,53}] assign io_req_valid_0 = _io_req_valid_T_4; // @[SinkA.scala:38:7, :79:50] wire _putbuffer_io_push_valid_T = io_a_valid_0 & hasData; // @[Edges.scala:92:28] wire _putbuffer_io_push_valid_T_1 = ~req_block; // @[SinkA.scala:70:25, :78:14, :80:52] wire _putbuffer_io_push_valid_T_2 = _putbuffer_io_push_valid_T & _putbuffer_io_push_valid_T_1; // @[SinkA.scala:80:{38,49,52}] wire _putbuffer_io_push_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :80:66] wire _putbuffer_io_push_valid_T_4 = _putbuffer_io_push_valid_T_2 & _putbuffer_io_push_valid_T_3; // @[SinkA.scala:80:{49,63,66}] assign lists_set = _io_req_valid_T & hasData & ~req_block & ~buf_block ? freeOH[39:0] : 40'h0; // @[Edges.scala:92:28] wire _offset_T = io_a_bits_address_0[0]; // @[SinkA.scala:38:7] wire _offset_T_1 = io_a_bits_address_0[1]; // @[SinkA.scala:38:7] wire _offset_T_2 = io_a_bits_address_0[2]; // @[SinkA.scala:38:7] wire _offset_T_3 = io_a_bits_address_0[3]; // @[SinkA.scala:38:7] wire _offset_T_4 = io_a_bits_address_0[4]; // @[SinkA.scala:38:7] wire _offset_T_5 = io_a_bits_address_0[5]; // @[SinkA.scala:38:7] wire _offset_T_6 = io_a_bits_address_0[6]; // @[SinkA.scala:38:7] wire _offset_T_7 = io_a_bits_address_0[7]; // @[SinkA.scala:38:7] wire _offset_T_8 = io_a_bits_address_0[8]; // @[SinkA.scala:38:7] wire _offset_T_9 = io_a_bits_address_0[9]; // @[SinkA.scala:38:7] wire _offset_T_10 = io_a_bits_address_0[10]; // @[SinkA.scala:38:7] wire _offset_T_11 = io_a_bits_address_0[11]; // @[SinkA.scala:38:7] wire _offset_T_12 = io_a_bits_address_0[12]; // @[SinkA.scala:38:7] wire _offset_T_13 = io_a_bits_address_0[13]; // @[SinkA.scala:38:7] wire _offset_T_14 = io_a_bits_address_0[14]; // @[SinkA.scala:38:7] wire _offset_T_15 = io_a_bits_address_0[15]; // @[SinkA.scala:38:7] wire _offset_T_16 = io_a_bits_address_0[16]; // @[SinkA.scala:38:7] wire _offset_T_17 = io_a_bits_address_0[17]; // @[SinkA.scala:38:7] wire _offset_T_18 = io_a_bits_address_0[18]; // @[SinkA.scala:38:7] wire _offset_T_19 = io_a_bits_address_0[19]; // @[SinkA.scala:38:7] wire _offset_T_20 = io_a_bits_address_0[20]; // @[SinkA.scala:38:7] wire _offset_T_21 = io_a_bits_address_0[21]; // @[SinkA.scala:38:7] wire _offset_T_22 = io_a_bits_address_0[22]; // @[SinkA.scala:38:7] wire _offset_T_23 = io_a_bits_address_0[23]; // @[SinkA.scala:38:7] wire _offset_T_24 = io_a_bits_address_0[24]; // @[SinkA.scala:38:7] wire _offset_T_25 = io_a_bits_address_0[25]; // @[SinkA.scala:38:7] wire _offset_T_26 = io_a_bits_address_0[26]; // @[SinkA.scala:38:7] wire _offset_T_27 = io_a_bits_address_0[27]; // @[SinkA.scala:38:7] wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_lo = {_offset_T_4, _offset_T_3}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_hi = {_offset_T_6, _offset_T_5}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, offset_lo_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_lo_hi_lo_hi = {_offset_T_9, _offset_T_8}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_7}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_lo = {_offset_T_11, _offset_T_10}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_hi = {_offset_T_13, _offset_T_12}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21] wire [13:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_lo_lo_hi = {_offset_T_16, _offset_T_15}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_14}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_lo = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_hi = {_offset_T_20, _offset_T_19}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, offset_hi_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_lo_hi = {_offset_T_23, _offset_T_22}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, _offset_T_21}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_lo = {_offset_T_25, _offset_T_24}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_hi = {_offset_T_27, _offset_T_26}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21] wire [13:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21] wire [27:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21] wire [21:0] set = offset[27:6]; // @[Parameters.scala:214:21, :215:22] wire [11:0] tag = set[21:10]; // @[Parameters.scala:215:22, :216:19] assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9] assign io_req_bits_tag_0 = tag_1; // @[SinkA.scala:38:7] assign set_1 = set[9:0]; // @[Parameters.scala:215:22, :217:28] assign io_req_bits_set_0 = set_1; // @[SinkA.scala:38:7] assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50] assign io_req_bits_offset_0 = offset_1; // @[SinkA.scala:38:7] reg [5:0] put_r; // @[SinkA.scala:84:42] assign put = first ? freeIdx : put_r; // @[OneHot.scala:32:10] assign io_req_bits_put_0 = put; // @[SinkA.scala:38:7, :84:16] wire _putbuffer_io_pop_valid_T = io_pb_pop_ready_0 & io_pb_pop_valid_0; // @[Decoupled.scala:51:35] wire [39:0] _io_pb_pop_ready_T = _putbuffer_io_valid >> io_pb_pop_bits_index_0; // @[SinkA.scala:38:7, :51:25, :105:40] assign _io_pb_pop_ready_T_1 = _io_pb_pop_ready_T[0]; // @[SinkA.scala:105:40] assign io_pb_pop_ready_0 = _io_pb_pop_ready_T_1; // @[SinkA.scala:38:7, :105:40] wire [63:0] _lists_clr_T = 64'h1 << lists_clr_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [39:0] _lists_clr_T_1 = _lists_clr_T[39:0]; // @[OneHot.scala:65:{12,27}] assign lists_clr = _putbuffer_io_pop_valid_T & io_pb_pop_bits_last_0 ? _lists_clr_T_1 : 40'h0; // @[OneHot.scala:65:27] always @(posedge clock) begin // @[SinkA.scala:38:7] if (reset) begin // @[SinkA.scala:38:7] lists <= 40'h0; // @[SinkA.scala:52:22] first_counter <= 3'h0; // @[Edges.scala:229:27] end else begin // @[SinkA.scala:38:7] lists <= _lists_T_2; // @[SinkA.scala:52:22, :56:32] if (_first_T) // @[Decoupled.scala:51:35] first_counter <= _first_counter_T; // @[Edges.scala:229:27, :236:21] end if (first) // @[Edges.scala:231:25] put_r <= freeIdx; // @[OneHot.scala:32:10] always @(posedge) ListBuffer_PutBufferAEntry_q40_e40 putbuffer ( // @[SinkA.scala:51:25] .clock (clock), .reset (reset), .io_push_ready (_putbuffer_io_push_ready), .io_push_valid (_putbuffer_io_push_valid_T_4), // @[SinkA.scala:80:63] .io_push_bits_index (put), // @[SinkA.scala:84:16] .io_push_bits_data_data (io_a_bits_data_0), // @[SinkA.scala:38:7] .io_push_bits_data_mask (io_a_bits_mask_0), // @[SinkA.scala:38:7] .io_push_bits_data_corrupt (io_a_bits_corrupt_0), // @[SinkA.scala:38:7] .io_valid (_putbuffer_io_valid), .io_pop_valid (_putbuffer_io_pop_valid_T), // @[Decoupled.scala:51:35] .io_pop_bits (io_pb_pop_bits_index_0), // @[SinkA.scala:38:7] .io_data_data (io_pb_beat_data_0), .io_data_mask (io_pb_beat_mask_0), .io_data_corrupt (io_pb_beat_corrupt_0) ); // @[SinkA.scala:51:25] assign io_req_valid = io_req_valid_0; // @[SinkA.scala:38:7] assign io_req_bits_opcode = io_req_bits_opcode_0; // @[SinkA.scala:38:7] assign io_req_bits_param = io_req_bits_param_0; // @[SinkA.scala:38:7] assign io_req_bits_size = io_req_bits_size_0; // @[SinkA.scala:38:7] assign io_req_bits_source = io_req_bits_source_0; // @[SinkA.scala:38:7] assign io_req_bits_tag = io_req_bits_tag_0; // @[SinkA.scala:38:7] assign io_req_bits_offset = io_req_bits_offset_0; // @[SinkA.scala:38:7] assign io_req_bits_put = io_req_bits_put_0; // @[SinkA.scala:38:7] assign io_req_bits_set = io_req_bits_set_0; // @[SinkA.scala:38:7] assign io_a_ready = io_a_ready_0; // @[SinkA.scala:38:7] assign io_pb_pop_ready = io_pb_pop_ready_0; // @[SinkA.scala:38:7] assign io_pb_beat_data = io_pb_beat_data_0; // @[SinkA.scala:38:7] assign io_pb_beat_mask = io_pb_beat_mask_0; // @[SinkA.scala:38:7] assign io_pb_beat_corrupt = io_pb_beat_corrupt_0; // @[SinkA.scala:38:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_21 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_42 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_21 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<2>(0h2), io.in.bits.egress_id) node _T_1 = eq(UInt<3>(0h4), io.in.bits.egress_id) node _T_2 = eq(UInt<3>(0h6), io.in.bits.egress_id) node _T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<3>(0h7) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h3) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<2>(0h2), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<3>(0h4), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<3>(0h6), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<2>(0h3), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<2> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<2>(0h2), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<3>(0h4), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<3>(0h6), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h7)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`0`[8], io.router_resp.vc_sel.`0`[8] connect route_q.io.enq.bits.vc_sel.`0`[9], io.router_resp.vc_sel.`0`[9] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[8], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[9], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_16 = eq(UInt<5>(0h13), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(UInt<5>(0h14), io.in.bits.egress_id) when _T_17 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_18 = eq(UInt<5>(0h15), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_19 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_20 = and(route_q.io.enq.valid, _T_19) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_43 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_21 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`0`[8], io.vcalloc_resp.vc_sel.`0`[8] connect vcalloc_q.io.enq.bits.vc_sel.`0`[9], io.vcalloc_resp.vc_sel.`0`[9] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_25 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_26 = and(vcalloc_q.io.enq.valid, _T_25) node _T_27 = eq(_T_26, UInt<1>(0h0)) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_lo_hi = cat(c_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node c_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node c_hi_hi = cat(c_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node _c_T_1 = cat(c_hi_1, c_lo_1) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_lo_hi_1 = cat(c_lo_hi_hi_1, io.out_credit_available.`0`[2]) node c_lo_2 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node c_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node c_hi_hi_1 = cat(c_hi_hi_hi_1, io.out_credit_available.`0`[7]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_2) node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _c_T_3 = cat(c_hi_3, c_lo_3) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node _out_channel_oh_T_6 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node _out_channel_oh_T_7 = or(_out_channel_oh_T_6, vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_channel_oh_0 = or(_out_channel_oh_T_7, vcalloc_q.io.deq.bits.vc_sel.`0`[9]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_lo_hi = cat(out_bundle_bits_out_virt_channel_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_bundle_bits_out_virt_channel_hi_hi = cat(out_bundle_bits_out_virt_channel_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 9, 8) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 7, 4) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 3, 2) node out_bundle_bits_out_virt_channel_lo_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 0) node _out_bundle_bits_out_virt_channel_T_5 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_6 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_3) node _out_bundle_bits_out_virt_channel_T_7 = bits(_out_bundle_bits_out_virt_channel_T_6, 1, 1) node _out_bundle_bits_out_virt_channel_T_8 = cat(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_7) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_8) node _out_bundle_bits_out_virt_channel_T_10 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_10, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_13 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_14 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_15 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_12) node _out_bundle_bits_out_virt_channel_T_16 = or(_out_bundle_bits_out_virt_channel_T_15, _out_bundle_bits_out_virt_channel_T_13) node _out_bundle_bits_out_virt_channel_T_17 = or(_out_bundle_bits_out_virt_channel_T_16, _out_bundle_bits_out_virt_channel_T_14) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<4> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_17 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1
module IngressUnit_21( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [3:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 4'h4; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 4'h6; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 4'h8; // @[IngressUnit.scala:30:72] wire [3:0] route_buffer_io_enq_bits_flow_egress_node = {2'h0, {_route_buffer_io_enq_bits_flow_egress_node_id_T_2, _route_buffer_io_enq_bits_flow_egress_node_id_T_1} | {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_3}}}; // @[Mux.scala:30:73] wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_37 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_337 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_338 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_339 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_340 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_37( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_337 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_338 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_339 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_340 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_53 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<8>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 7, 0) node _source_ok_T = shr(io.in.a.bits.source, 8) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<8>(0h9f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits = bits(_uncommonBits_T, 7, 0) node _T_4 = shr(io.in.a.bits.source, 8) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<8>(0h9f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 7, 0) node _T_24 = shr(io.in.a.bits.source, 8) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<8>(0h9f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 7, 0) node _T_86 = shr(io.in.a.bits.source, 8) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<8>(0h9f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 7, 0) node _T_152 = shr(io.in.a.bits.source, 8) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<8>(0h9f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 7, 0) node _T_199 = shr(io.in.a.bits.source, 8) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<8>(0h9f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 7, 0) node _T_240 = shr(io.in.a.bits.source, 8) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<8>(0h9f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 7, 0) node _T_283 = shr(io.in.a.bits.source, 8) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<8>(0h9f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 7, 0) node _T_321 = shr(io.in.a.bits.source, 8) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<8>(0h9f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 7, 0) node _T_359 = shr(io.in.a.bits.source, 8) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<8>(0h9f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<8>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 7, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 8) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<8>(0h9f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<160>, clock, reset, UInt<160>(0h0) regreset inflight_opcodes : UInt<640>, clock, reset, UInt<640>(0h0) regreset inflight_sizes : UInt<640>, clock, reset, UInt<640>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<160> connect a_set, UInt<160>(0h0) wire a_set_wo_ready : UInt<160> connect a_set_wo_ready, UInt<160>(0h0) wire a_opcodes_set : UInt<640> connect a_opcodes_set, UInt<640>(0h0) wire a_sizes_set : UInt<640> connect a_sizes_set, UInt<640>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<160> connect d_clr, UInt<160>(0h0) wire d_clr_wo_ready : UInt<160> connect d_clr_wo_ready, UInt<160>(0h0) wire d_opcodes_clr : UInt<640> connect d_opcodes_clr, UInt<640>(0h0) wire d_sizes_clr : UInt<640> connect d_sizes_clr, UInt<640>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_106 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<160>, clock, reset, UInt<160>(0h0) regreset inflight_opcodes_1 : UInt<640>, clock, reset, UInt<640>(0h0) regreset inflight_sizes_1 : UInt<640>, clock, reset, UInt<640>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<160> connect c_set, UInt<160>(0h0) wire c_set_wo_ready : UInt<160> connect c_set_wo_ready, UInt<160>(0h0) wire c_opcodes_set : UInt<640> connect c_opcodes_set, UInt<640>(0h0) wire c_sizes_set : UInt<640> connect c_sizes_set, UInt<640>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<160> connect d_clr_1, UInt<160>(0h0) wire d_clr_wo_ready_1 : UInt<160> connect d_clr_wo_ready_1, UInt<160>(0h0) wire d_opcodes_clr_1 : UInt<640> connect d_opcodes_clr_1, UInt<640>(0h0) wire d_sizes_clr_1 : UInt<640> connect d_sizes_clr_1, UInt<640>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_107 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_53( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2049:0] _c_sizes_set_T_1 = 2050'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [639:0] c_opcodes_set = 640'h0; // @[Monitor.scala:740:34] wire [639:0] c_sizes_set = 640'h0; // @[Monitor.scala:741:34] wire [159:0] c_set = 160'h0; // @[Monitor.scala:738:34] wire [159:0] c_set_wo_ready = 160'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 8'hA0; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [7:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [7:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 8'hA0; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [159:0] inflight; // @[Monitor.scala:614:27] reg [639:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [639:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [159:0] a_set; // @[Monitor.scala:626:34] wire [159:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [639:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [639:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [639:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [639:0] _a_opcode_lookup_T_6 = {636'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [639:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[639:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [639:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [639:0] _a_size_lookup_T_6 = {636'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [639:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[639:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[159:0] : 160'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[159:0] : 160'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[639:0] : 640'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2049:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[639:0] : 640'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [159:0] d_clr; // @[Monitor.scala:664:34] wire [159:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [639:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [639:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[159:0] : 160'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[159:0] : 160'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[639:0] : 640'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[639:0] : 640'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [159:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [159:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [159:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [639:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [639:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [639:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [639:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [639:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [639:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [159:0] inflight_1; // @[Monitor.scala:726:35] wire [159:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [639:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [639:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [639:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [639:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [639:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [639:0] _c_opcode_lookup_T_6 = {636'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [639:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[639:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [639:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [639:0] _c_size_lookup_T_6 = {636'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [639:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[639:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [159:0] d_clr_1; // @[Monitor.scala:774:34] wire [159:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [639:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [639:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[159:0] : 160'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[159:0] : 160'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[639:0] : 640'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[639:0] : 640'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [159:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [159:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [639:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [639:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [639:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [639:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker : input clock : Clock input reset : Reset output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}} node _legal_address_T = xor(io.paddr, UInt<1>(0h0)) node _legal_address_T_1 = cvt(_legal_address_T) node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) node _legal_address_T_3 = asSInt(_legal_address_T_2) node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000)) node _legal_address_T_6 = cvt(_legal_address_T_5) node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) node _legal_address_T_8 = asSInt(_legal_address_T_7) node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000)) node _legal_address_T_11 = cvt(_legal_address_T_10) node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000))) node _legal_address_T_13 = asSInt(_legal_address_T_12) node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000)) node _legal_address_T_16 = cvt(_legal_address_T_15) node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) node _legal_address_T_18 = asSInt(_legal_address_T_17) node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) node _legal_address_T_20 = xor(io.paddr, UInt<21>(0h100000)) node _legal_address_T_21 = cvt(_legal_address_T_20) node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000))) node _legal_address_T_23 = asSInt(_legal_address_T_22) node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) node _legal_address_T_25 = xor(io.paddr, UInt<21>(0h110000)) node _legal_address_T_26 = cvt(_legal_address_T_25) node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) node _legal_address_T_28 = asSInt(_legal_address_T_27) node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) node _legal_address_T_30 = xor(io.paddr, UInt<26>(0h2000000)) node _legal_address_T_31 = cvt(_legal_address_T_30) node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<17>(0h10000))) node _legal_address_T_33 = asSInt(_legal_address_T_32) node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) node _legal_address_T_35 = xor(io.paddr, UInt<26>(0h2010000)) node _legal_address_T_36 = cvt(_legal_address_T_35) node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) node _legal_address_T_38 = asSInt(_legal_address_T_37) node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) node _legal_address_T_40 = xor(io.paddr, UInt<28>(0h8000000)) node _legal_address_T_41 = cvt(_legal_address_T_40) node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<17>(0h10000))) node _legal_address_T_43 = asSInt(_legal_address_T_42) node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) node _legal_address_T_45 = xor(io.paddr, UInt<28>(0hc000000)) node _legal_address_T_46 = cvt(_legal_address_T_45) node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<27>(0h4000000))) node _legal_address_T_48 = asSInt(_legal_address_T_47) node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10020000)) node _legal_address_T_51 = cvt(_legal_address_T_50) node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) node _legal_address_T_53 = asSInt(_legal_address_T_52) node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) node _legal_address_T_55 = xor(io.paddr, UInt<29>(0h10040000)) node _legal_address_T_56 = cvt(_legal_address_T_55) node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<19>(0h40000))) node _legal_address_T_58 = asSInt(_legal_address_T_57) node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) node _legal_address_T_60 = xor(io.paddr, UInt<32>(0h80000000)) node _legal_address_T_61 = cvt(_legal_address_T_60) node _legal_address_T_62 = and(_legal_address_T_61, asSInt(UInt<29>(0h10000000))) node _legal_address_T_63 = asSInt(_legal_address_T_62) node _legal_address_T_64 = eq(_legal_address_T_63, asSInt(UInt<1>(0h0))) wire _legal_address_WIRE : UInt<1>[13] connect _legal_address_WIRE[0], _legal_address_T_4 connect _legal_address_WIRE[1], _legal_address_T_9 connect _legal_address_WIRE[2], _legal_address_T_14 connect _legal_address_WIRE[3], _legal_address_T_19 connect _legal_address_WIRE[4], _legal_address_T_24 connect _legal_address_WIRE[5], _legal_address_T_29 connect _legal_address_WIRE[6], _legal_address_T_34 connect _legal_address_WIRE[7], _legal_address_T_39 connect _legal_address_WIRE[8], _legal_address_T_44 connect _legal_address_WIRE[9], _legal_address_T_49 connect _legal_address_WIRE[10], _legal_address_T_54 connect _legal_address_WIRE[11], _legal_address_T_59 connect _legal_address_WIRE[12], _legal_address_T_64 node _legal_address_T_65 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) node _legal_address_T_66 = or(_legal_address_T_65, _legal_address_WIRE[2]) node _legal_address_T_67 = or(_legal_address_T_66, _legal_address_WIRE[3]) node _legal_address_T_68 = or(_legal_address_T_67, _legal_address_WIRE[4]) node _legal_address_T_69 = or(_legal_address_T_68, _legal_address_WIRE[5]) node _legal_address_T_70 = or(_legal_address_T_69, _legal_address_WIRE[6]) node _legal_address_T_71 = or(_legal_address_T_70, _legal_address_WIRE[7]) node _legal_address_T_72 = or(_legal_address_T_71, _legal_address_WIRE[8]) node _legal_address_T_73 = or(_legal_address_T_72, _legal_address_WIRE[9]) node _legal_address_T_74 = or(_legal_address_T_73, _legal_address_WIRE[10]) node _legal_address_T_75 = or(_legal_address_T_74, _legal_address_WIRE[11]) node legal_address = or(_legal_address_T_75, _legal_address_WIRE[12]) node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T) node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2) node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5) node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h9c011000))) node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7) node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10) node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h9c000000))) node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12) node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_15 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_cacheable_T_16 = cvt(_io_resp_cacheable_T_15) node _io_resp_cacheable_T_17 = and(_io_resp_cacheable_T_16, asSInt(UInt<33>(0h9c011000))) node _io_resp_cacheable_T_18 = asSInt(_io_resp_cacheable_T_17) node _io_resp_cacheable_T_19 = eq(_io_resp_cacheable_T_18, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_20 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9) node _io_resp_cacheable_T_21 = or(_io_resp_cacheable_T_20, _io_resp_cacheable_T_14) node _io_resp_cacheable_T_22 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_19) node _io_resp_cacheable_T_23 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_cacheable_T_24 = cvt(_io_resp_cacheable_T_23) node _io_resp_cacheable_T_25 = and(_io_resp_cacheable_T_24, asSInt(UInt<33>(0h9c010000))) node _io_resp_cacheable_T_26 = asSInt(_io_resp_cacheable_T_25) node _io_resp_cacheable_T_27 = eq(_io_resp_cacheable_T_26, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_28 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_cacheable_T_29 = cvt(_io_resp_cacheable_T_28) node _io_resp_cacheable_T_30 = and(_io_resp_cacheable_T_29, asSInt(UInt<33>(0h90000000))) node _io_resp_cacheable_T_31 = asSInt(_io_resp_cacheable_T_30) node _io_resp_cacheable_T_32 = eq(_io_resp_cacheable_T_31, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_33 = or(_io_resp_cacheable_T_27, _io_resp_cacheable_T_32) node _io_resp_cacheable_T_34 = mux(_io_resp_cacheable_T_22, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_cacheable_T_35 = mux(_io_resp_cacheable_T_33, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_cacheable_T_36 = or(_io_resp_cacheable_T_34, _io_resp_cacheable_T_35) wire _io_resp_cacheable_WIRE : UInt<1> connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_36 node _io_resp_cacheable_T_37 = and(legal_address, _io_resp_cacheable_WIRE) connect io.resp.cacheable, _io_resp_cacheable_T_37 node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_r_T_1 = cvt(_io_resp_r_T) node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0))) node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2) node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0))) node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1)) connect io.resp.r, _io_resp_r_T_5 node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_w_T_1 = cvt(_io_resp_w_T) node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2) node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0))) node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_w_T_6 = cvt(_io_resp_w_T_5) node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7) node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0))) node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_w_T_11 = cvt(_io_resp_w_T_10) node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12) node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0))) node _io_resp_w_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_16 = cvt(_io_resp_w_T_15) node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17) node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0))) node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_21 = cvt(_io_resp_w_T_20) node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22) node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0))) node _io_resp_w_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_w_T_26 = cvt(_io_resp_w_T_25) node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0h9a100000))) node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27) node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0))) node _io_resp_w_T_30 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_w_T_31 = cvt(_io_resp_w_T_30) node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32) node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0))) node _io_resp_w_T_35 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_w_T_36 = cvt(_io_resp_w_T_35) node _io_resp_w_T_37 = and(_io_resp_w_T_36, asSInt(UInt<33>(0h90000000))) node _io_resp_w_T_38 = asSInt(_io_resp_w_T_37) node _io_resp_w_T_39 = eq(_io_resp_w_T_38, asSInt(UInt<1>(0h0))) node _io_resp_w_T_40 = or(_io_resp_w_T_4, _io_resp_w_T_9) node _io_resp_w_T_41 = or(_io_resp_w_T_40, _io_resp_w_T_14) node _io_resp_w_T_42 = or(_io_resp_w_T_41, _io_resp_w_T_19) node _io_resp_w_T_43 = or(_io_resp_w_T_42, _io_resp_w_T_24) node _io_resp_w_T_44 = or(_io_resp_w_T_43, _io_resp_w_T_29) node _io_resp_w_T_45 = or(_io_resp_w_T_44, _io_resp_w_T_34) node _io_resp_w_T_46 = or(_io_resp_w_T_45, _io_resp_w_T_39) node _io_resp_w_T_47 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_w_T_48 = cvt(_io_resp_w_T_47) node _io_resp_w_T_49 = and(_io_resp_w_T_48, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_50 = asSInt(_io_resp_w_T_49) node _io_resp_w_T_51 = eq(_io_resp_w_T_50, asSInt(UInt<1>(0h0))) node _io_resp_w_T_52 = mux(_io_resp_w_T_46, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_w_T_53 = mux(_io_resp_w_T_51, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_w_T_54 = or(_io_resp_w_T_52, _io_resp_w_T_53) wire _io_resp_w_WIRE : UInt<1> connect _io_resp_w_WIRE, _io_resp_w_T_54 node _io_resp_w_T_55 = and(legal_address, _io_resp_w_WIRE) connect io.resp.w, _io_resp_w_T_55 node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_pp_T_1 = cvt(_io_resp_pp_T) node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2) node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5) node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7) node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10) node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12) node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15) node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17) node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20) node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22) node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25) node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0h9a100000))) node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27) node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_30 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30) node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32) node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_35 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_pp_T_36 = cvt(_io_resp_pp_T_35) node _io_resp_pp_T_37 = and(_io_resp_pp_T_36, asSInt(UInt<33>(0h90000000))) node _io_resp_pp_T_38 = asSInt(_io_resp_pp_T_37) node _io_resp_pp_T_39 = eq(_io_resp_pp_T_38, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_40 = or(_io_resp_pp_T_4, _io_resp_pp_T_9) node _io_resp_pp_T_41 = or(_io_resp_pp_T_40, _io_resp_pp_T_14) node _io_resp_pp_T_42 = or(_io_resp_pp_T_41, _io_resp_pp_T_19) node _io_resp_pp_T_43 = or(_io_resp_pp_T_42, _io_resp_pp_T_24) node _io_resp_pp_T_44 = or(_io_resp_pp_T_43, _io_resp_pp_T_29) node _io_resp_pp_T_45 = or(_io_resp_pp_T_44, _io_resp_pp_T_34) node _io_resp_pp_T_46 = or(_io_resp_pp_T_45, _io_resp_pp_T_39) node _io_resp_pp_T_47 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_pp_T_48 = cvt(_io_resp_pp_T_47) node _io_resp_pp_T_49 = and(_io_resp_pp_T_48, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_50 = asSInt(_io_resp_pp_T_49) node _io_resp_pp_T_51 = eq(_io_resp_pp_T_50, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_52 = mux(_io_resp_pp_T_46, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_pp_T_53 = mux(_io_resp_pp_T_51, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_pp_T_54 = or(_io_resp_pp_T_52, _io_resp_pp_T_53) wire _io_resp_pp_WIRE : UInt<1> connect _io_resp_pp_WIRE, _io_resp_pp_T_54 node _io_resp_pp_T_55 = and(legal_address, _io_resp_pp_WIRE) connect io.resp.pp, _io_resp_pp_T_55 node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_al_T_1 = cvt(_io_resp_al_T) node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2) node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0))) node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_al_T_6 = cvt(_io_resp_al_T_5) node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7) node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0))) node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_al_T_11 = cvt(_io_resp_al_T_10) node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12) node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0))) node _io_resp_al_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_16 = cvt(_io_resp_al_T_15) node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17) node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0))) node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_21 = cvt(_io_resp_al_T_20) node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22) node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0))) node _io_resp_al_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_al_T_26 = cvt(_io_resp_al_T_25) node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0h9a100000))) node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27) node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0))) node _io_resp_al_T_30 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_al_T_31 = cvt(_io_resp_al_T_30) node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32) node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0))) node _io_resp_al_T_35 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_al_T_36 = cvt(_io_resp_al_T_35) node _io_resp_al_T_37 = and(_io_resp_al_T_36, asSInt(UInt<33>(0h90000000))) node _io_resp_al_T_38 = asSInt(_io_resp_al_T_37) node _io_resp_al_T_39 = eq(_io_resp_al_T_38, asSInt(UInt<1>(0h0))) node _io_resp_al_T_40 = or(_io_resp_al_T_4, _io_resp_al_T_9) node _io_resp_al_T_41 = or(_io_resp_al_T_40, _io_resp_al_T_14) node _io_resp_al_T_42 = or(_io_resp_al_T_41, _io_resp_al_T_19) node _io_resp_al_T_43 = or(_io_resp_al_T_42, _io_resp_al_T_24) node _io_resp_al_T_44 = or(_io_resp_al_T_43, _io_resp_al_T_29) node _io_resp_al_T_45 = or(_io_resp_al_T_44, _io_resp_al_T_34) node _io_resp_al_T_46 = or(_io_resp_al_T_45, _io_resp_al_T_39) node _io_resp_al_T_47 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_al_T_48 = cvt(_io_resp_al_T_47) node _io_resp_al_T_49 = and(_io_resp_al_T_48, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_50 = asSInt(_io_resp_al_T_49) node _io_resp_al_T_51 = eq(_io_resp_al_T_50, asSInt(UInt<1>(0h0))) node _io_resp_al_T_52 = mux(_io_resp_al_T_46, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_al_T_53 = mux(_io_resp_al_T_51, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_al_T_54 = or(_io_resp_al_T_52, _io_resp_al_T_53) wire _io_resp_al_WIRE : UInt<1> connect _io_resp_al_WIRE, _io_resp_al_T_54 node _io_resp_al_T_55 = and(legal_address, _io_resp_al_WIRE) connect io.resp.al, _io_resp_al_T_55 node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_aa_T_1 = cvt(_io_resp_aa_T) node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2) node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5) node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7) node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10) node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12) node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15) node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17) node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20) node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22) node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25) node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0h9a100000))) node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27) node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_30 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30) node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32) node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_35 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_aa_T_36 = cvt(_io_resp_aa_T_35) node _io_resp_aa_T_37 = and(_io_resp_aa_T_36, asSInt(UInt<33>(0h90000000))) node _io_resp_aa_T_38 = asSInt(_io_resp_aa_T_37) node _io_resp_aa_T_39 = eq(_io_resp_aa_T_38, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_40 = or(_io_resp_aa_T_4, _io_resp_aa_T_9) node _io_resp_aa_T_41 = or(_io_resp_aa_T_40, _io_resp_aa_T_14) node _io_resp_aa_T_42 = or(_io_resp_aa_T_41, _io_resp_aa_T_19) node _io_resp_aa_T_43 = or(_io_resp_aa_T_42, _io_resp_aa_T_24) node _io_resp_aa_T_44 = or(_io_resp_aa_T_43, _io_resp_aa_T_29) node _io_resp_aa_T_45 = or(_io_resp_aa_T_44, _io_resp_aa_T_34) node _io_resp_aa_T_46 = or(_io_resp_aa_T_45, _io_resp_aa_T_39) node _io_resp_aa_T_47 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_aa_T_48 = cvt(_io_resp_aa_T_47) node _io_resp_aa_T_49 = and(_io_resp_aa_T_48, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_50 = asSInt(_io_resp_aa_T_49) node _io_resp_aa_T_51 = eq(_io_resp_aa_T_50, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_52 = mux(_io_resp_aa_T_46, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_aa_T_53 = mux(_io_resp_aa_T_51, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_aa_T_54 = or(_io_resp_aa_T_52, _io_resp_aa_T_53) wire _io_resp_aa_WIRE : UInt<1> connect _io_resp_aa_WIRE, _io_resp_aa_T_54 node _io_resp_aa_T_55 = and(legal_address, _io_resp_aa_WIRE) connect io.resp.aa, _io_resp_aa_T_55 node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_x_T_1 = cvt(_io_resp_x_T) node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2) node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0))) node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_x_T_6 = cvt(_io_resp_x_T_5) node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7) node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0))) node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_x_T_11 = cvt(_io_resp_x_T_10) node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12) node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0))) node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_x_T_16 = cvt(_io_resp_x_T_15) node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17) node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0))) node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_x_T_21 = cvt(_io_resp_x_T_20) node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0h90000000))) node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22) node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0))) node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9) node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14) node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19) node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24) node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000)) node _io_resp_x_T_30 = cvt(_io_resp_x_T_29) node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31) node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0))) node _io_resp_x_T_34 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_x_T_35 = cvt(_io_resp_x_T_34) node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0h9e103000))) node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36) node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0))) node _io_resp_x_T_39 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_x_T_40 = cvt(_io_resp_x_T_39) node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41) node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0))) node _io_resp_x_T_44 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_x_T_45 = cvt(_io_resp_x_T_44) node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46) node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0))) node _io_resp_x_T_49 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_x_T_50 = cvt(_io_resp_x_T_49) node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0h9c000000))) node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51) node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0))) node _io_resp_x_T_54 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_x_T_55 = cvt(_io_resp_x_T_54) node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0h9e100000))) node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56) node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0))) node _io_resp_x_T_59 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_x_T_60 = cvt(_io_resp_x_T_59) node _io_resp_x_T_61 = and(_io_resp_x_T_60, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_62 = asSInt(_io_resp_x_T_61) node _io_resp_x_T_63 = eq(_io_resp_x_T_62, asSInt(UInt<1>(0h0))) node _io_resp_x_T_64 = or(_io_resp_x_T_33, _io_resp_x_T_38) node _io_resp_x_T_65 = or(_io_resp_x_T_64, _io_resp_x_T_43) node _io_resp_x_T_66 = or(_io_resp_x_T_65, _io_resp_x_T_48) node _io_resp_x_T_67 = or(_io_resp_x_T_66, _io_resp_x_T_53) node _io_resp_x_T_68 = or(_io_resp_x_T_67, _io_resp_x_T_58) node _io_resp_x_T_69 = or(_io_resp_x_T_68, _io_resp_x_T_63) node _io_resp_x_T_70 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_x_T_71 = mux(_io_resp_x_T_69, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_x_T_72 = or(_io_resp_x_T_70, _io_resp_x_T_71) wire _io_resp_x_WIRE : UInt<1> connect _io_resp_x_WIRE, _io_resp_x_T_72 node _io_resp_x_T_73 = and(legal_address, _io_resp_x_WIRE) connect io.resp.x, _io_resp_x_T_73 node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_eff_T_1 = cvt(_io_resp_eff_T) node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0h9e112000))) node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2) node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5) node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0h9e103000))) node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7) node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10) node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12) node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15) node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17) node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_20 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20) node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0h9c000000))) node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22) node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25) node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0h9e100000))) node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27) node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_30 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_eff_T_31 = cvt(_io_resp_eff_T_30) node _io_resp_eff_T_32 = and(_io_resp_eff_T_31, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_33 = asSInt(_io_resp_eff_T_32) node _io_resp_eff_T_34 = eq(_io_resp_eff_T_33, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_35 = or(_io_resp_eff_T_4, _io_resp_eff_T_9) node _io_resp_eff_T_36 = or(_io_resp_eff_T_35, _io_resp_eff_T_14) node _io_resp_eff_T_37 = or(_io_resp_eff_T_36, _io_resp_eff_T_19) node _io_resp_eff_T_38 = or(_io_resp_eff_T_37, _io_resp_eff_T_24) node _io_resp_eff_T_39 = or(_io_resp_eff_T_38, _io_resp_eff_T_29) node _io_resp_eff_T_40 = or(_io_resp_eff_T_39, _io_resp_eff_T_34) node _io_resp_eff_T_41 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_eff_T_42 = cvt(_io_resp_eff_T_41) node _io_resp_eff_T_43 = and(_io_resp_eff_T_42, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_44 = asSInt(_io_resp_eff_T_43) node _io_resp_eff_T_45 = eq(_io_resp_eff_T_44, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_46 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_eff_T_47 = cvt(_io_resp_eff_T_46) node _io_resp_eff_T_48 = and(_io_resp_eff_T_47, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_49 = asSInt(_io_resp_eff_T_48) node _io_resp_eff_T_50 = eq(_io_resp_eff_T_49, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_51 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_eff_T_52 = cvt(_io_resp_eff_T_51) node _io_resp_eff_T_53 = and(_io_resp_eff_T_52, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_54 = asSInt(_io_resp_eff_T_53) node _io_resp_eff_T_55 = eq(_io_resp_eff_T_54, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_56 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_eff_T_57 = cvt(_io_resp_eff_T_56) node _io_resp_eff_T_58 = and(_io_resp_eff_T_57, asSInt(UInt<33>(0h90000000))) node _io_resp_eff_T_59 = asSInt(_io_resp_eff_T_58) node _io_resp_eff_T_60 = eq(_io_resp_eff_T_59, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_61 = or(_io_resp_eff_T_45, _io_resp_eff_T_50) node _io_resp_eff_T_62 = or(_io_resp_eff_T_61, _io_resp_eff_T_55) node _io_resp_eff_T_63 = or(_io_resp_eff_T_62, _io_resp_eff_T_60) node _io_resp_eff_T_64 = mux(_io_resp_eff_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_eff_T_65 = mux(_io_resp_eff_T_63, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_eff_T_66 = or(_io_resp_eff_T_64, _io_resp_eff_T_65) wire _io_resp_eff_WIRE : UInt<1> connect _io_resp_eff_WIRE, _io_resp_eff_T_66 node _io_resp_eff_T_67 = and(legal_address, _io_resp_eff_WIRE) connect io.resp.eff, _io_resp_eff_T_67
module PMAChecker( // @[PMA.scala:18:7] input [39:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [8:0] _GEN = io_paddr[20:12] ^ 9'h100; // @[Parameters.scala:137:31] wire [9:0] _GEN_0 = io_paddr[25:16] ^ 10'h200; // @[Parameters.scala:137:31] wire [13:0] _GEN_1 = io_paddr[25:12] ^ 14'h2010; // @[Parameters.scala:137:31] wire [11:0] _GEN_2 = io_paddr[27:16] ^ 12'h800; // @[Parameters.scala:137:31] wire [3:0] _GEN_3 = io_paddr[31:28] ^ 4'h8; // @[Parameters.scala:137:31] wire legal_address = io_paddr[39:12] == 28'h0 | {io_paddr[39:13], ~(io_paddr[12])} == 28'h0 | {io_paddr[39:14], ~(io_paddr[13:12])} == 28'h0 | {io_paddr[39:17], ~(io_paddr[16])} == 24'h0 | {io_paddr[39:21], _GEN} == 28'h0 | {io_paddr[39:21], io_paddr[20:12] ^ 9'h110} == 28'h0 | {io_paddr[39:26], _GEN_0} == 24'h0 | {io_paddr[39:26], _GEN_1} == 28'h0 | {io_paddr[39:28], _GEN_2} == 24'h0 | {io_paddr[39:28], ~(io_paddr[27:26])} == 14'h0 | {io_paddr[39:29], io_paddr[28:12] ^ 17'h10020} == 28'h0 | {io_paddr[39:29], io_paddr[28:18] ^ 11'h401} == 22'h0 | {io_paddr[39:32], _GEN_3} == 12'h0; // @[PMA.scala:19:14, :36:58] wire [3:0] _GEN_4 = io_paddr[28:25] ^ 4'h8; // @[Parameters.scala:137:31] wire [1:0] _GEN_5 = {_GEN_3[3], io_paddr[28]}; // @[Parameters.scala:137:{31,41,46}] wire [4:0] _GEN_6 = {io_paddr[31], io_paddr[28:27], io_paddr[20], io_paddr[16]}; // @[Parameters.scala:137:{31,41,46}] wire [5:0] _GEN_7 = {io_paddr[31], io_paddr[28:27], io_paddr[25], _GEN[8], io_paddr[12]}; // @[Parameters.scala:137:{31,41,46}] wire [6:0] _GEN_8 = {io_paddr[31], io_paddr[28:27], _GEN_1[13], io_paddr[20], _GEN_1[4], io_paddr[12]}; // @[Parameters.scala:137:{31,41,46}] wire [2:0] _GEN_9 = {io_paddr[31], io_paddr[28], _GEN_2[11]}; // @[Parameters.scala:137:{31,41,46}] wire [5:0] _GEN_10 = {io_paddr[31], io_paddr[28], _GEN_2[11], io_paddr[25], io_paddr[20], io_paddr[16]}; // @[Parameters.scala:137:{31,41,46}] wire [4:0] _GEN_11 = {io_paddr[31], _GEN_4[3:2], io_paddr[25], io_paddr[20]}; // @[Parameters.scala:137:{31,41,46}] wire [6:0] _GEN_12 = {io_paddr[31], _GEN_4[3:2], io_paddr[25], io_paddr[20], io_paddr[16], io_paddr[12]}; // @[Parameters.scala:137:{31,41,46}] assign io_resp_cacheable = legal_address & ({io_paddr[31], io_paddr[28], _GEN_2[11:10], io_paddr[16]} == 5'h0 | ~(|_GEN_5)); // @[Parameters.scala:629:89] assign io_resp_r = legal_address; // @[PMA.scala:18:7, :36:58] assign io_resp_w = legal_address & (~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8) | ~(|_GEN_9) | ~(|_GEN_10) | ~(|_GEN_11) | ~(|_GEN_12) | ~(|_GEN_5)); // @[Parameters.scala:629:89] assign io_resp_pp = legal_address & (~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8) | ~(|_GEN_9) | ~(|_GEN_10) | ~(|_GEN_11) | ~(|_GEN_12) | ~(|_GEN_5)); // @[Parameters.scala:629:89] assign io_resp_al = legal_address & (~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8) | ~(|_GEN_9) | ~(|_GEN_10) | ~(|_GEN_11) | ~(|_GEN_12) | ~(|_GEN_5)); // @[Parameters.scala:629:89] assign io_resp_aa = legal_address & (~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8) | ~(|_GEN_9) | ~(|_GEN_10) | ~(|_GEN_11) | ~(|_GEN_12) | ~(|_GEN_5)); // @[Parameters.scala:629:89] assign io_resp_x = legal_address & ({io_paddr[31], io_paddr[28:25], io_paddr[20], io_paddr[16], io_paddr[13:12]} == 9'h0 | {io_paddr[31], io_paddr[28:25], io_paddr[20], io_paddr[16], ~(io_paddr[13:12])} == 9'h0 | {io_paddr[31], io_paddr[28:25], io_paddr[20], ~(io_paddr[16])} == 7'h0 | {io_paddr[31], io_paddr[28], _GEN_2[11:9], io_paddr[20], io_paddr[16]} == 7'h0 | ~(|_GEN_5)); // @[Parameters.scala:629:89] assign io_resp_eff = legal_address & ({io_paddr[31], io_paddr[28:25], io_paddr[20], io_paddr[16], io_paddr[13]} == 8'h0 | {io_paddr[31], io_paddr[28:25], _GEN[8], io_paddr[13:12]} == 8'h0 | {io_paddr[31], io_paddr[28:26], _GEN_0[9], io_paddr[20], io_paddr[16]} == 7'h0 | {io_paddr[31], io_paddr[28:26], _GEN_1[13], io_paddr[20], _GEN_1[4], io_paddr[13:12]} == 9'h0 | {io_paddr[31], io_paddr[28], ~(io_paddr[27:26])} == 4'h0 | {io_paddr[31], _GEN_4, io_paddr[20]} == 6'h0 | {io_paddr[31], _GEN_4, io_paddr[20], io_paddr[16], io_paddr[13:12]} == 9'h0); // @[Parameters.scala:629:89] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c : input clock : Clock input reset : Reset output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate anonIn.e.bits.sink invalidate anonIn.e.valid invalidate anonIn.e.ready invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.c.bits.corrupt invalidate anonIn.c.bits.data invalidate anonIn.c.bits.address invalidate anonIn.c.bits.source invalidate anonIn.c.bits.size invalidate anonIn.c.bits.param invalidate anonIn.c.bits.opcode invalidate anonIn.c.valid invalidate anonIn.c.ready invalidate anonIn.b.bits.corrupt invalidate anonIn.b.bits.data invalidate anonIn.b.bits.mask invalidate anonIn.b.bits.address invalidate anonIn.b.bits.source invalidate anonIn.b.bits.size invalidate anonIn.b.bits.param invalidate anonIn.b.bits.opcode invalidate anonIn.b.valid invalidate anonIn.b.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready inst monitor of TLMonitor_39 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, anonIn.e.bits.sink connect monitor.io.in.e.valid, anonIn.e.valid connect monitor.io.in.e.ready, anonIn.e.ready connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.c.bits.corrupt, anonIn.c.bits.corrupt connect monitor.io.in.c.bits.data, anonIn.c.bits.data connect monitor.io.in.c.bits.address, anonIn.c.bits.address connect monitor.io.in.c.bits.source, anonIn.c.bits.source connect monitor.io.in.c.bits.size, anonIn.c.bits.size connect monitor.io.in.c.bits.param, anonIn.c.bits.param connect monitor.io.in.c.bits.opcode, anonIn.c.bits.opcode connect monitor.io.in.c.valid, anonIn.c.valid connect monitor.io.in.c.ready, anonIn.c.ready connect monitor.io.in.b.bits.corrupt, anonIn.b.bits.corrupt connect monitor.io.in.b.bits.data, anonIn.b.bits.data connect monitor.io.in.b.bits.mask, anonIn.b.bits.mask connect monitor.io.in.b.bits.address, anonIn.b.bits.address connect monitor.io.in.b.bits.source, anonIn.b.bits.source connect monitor.io.in.b.bits.size, anonIn.b.bits.size connect monitor.io.in.b.bits.param, anonIn.b.bits.param connect monitor.io.in.b.bits.opcode, anonIn.b.bits.opcode connect monitor.io.in.b.valid, anonIn.b.valid connect monitor.io.in.b.ready, anonIn.b.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_40 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate anonOut.e.bits.sink invalidate anonOut.e.valid invalidate anonOut.e.ready invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.c.bits.corrupt invalidate anonOut.c.bits.data invalidate anonOut.c.bits.address invalidate anonOut.c.bits.source invalidate anonOut.c.bits.size invalidate anonOut.c.bits.param invalidate anonOut.c.bits.opcode invalidate anonOut.c.valid invalidate anonOut.c.ready invalidate anonOut.b.bits.corrupt invalidate anonOut.b.bits.data invalidate anonOut.b.bits.mask invalidate anonOut.b.bits.address invalidate anonOut.b.bits.source invalidate anonOut.b.bits.size invalidate anonOut.b.bits.param invalidate anonOut.b.bits.opcode invalidate anonOut.b.valid invalidate anonOut.b.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T connect anonIn.b.bits.corrupt, in[0].b.bits.corrupt connect anonIn.b.bits.data, in[0].b.bits.data connect anonIn.b.bits.mask, in[0].b.bits.mask connect anonIn.b.bits.address, in[0].b.bits.address connect anonIn.b.bits.source, in[0].b.bits.source connect anonIn.b.bits.size, in[0].b.bits.size connect anonIn.b.bits.param, in[0].b.bits.param connect anonIn.b.bits.opcode, in[0].b.bits.opcode connect anonIn.b.valid, in[0].b.valid connect in[0].b.ready, anonIn.b.ready node _anonIn_b_bits_source_T = bits(in[0].b.bits.source, 0, 0) connect anonIn.b.bits.source, _anonIn_b_bits_source_T connect in[0].c.bits.corrupt, anonIn.c.bits.corrupt connect in[0].c.bits.data, anonIn.c.bits.data connect in[0].c.bits.address, anonIn.c.bits.address connect in[0].c.bits.source, anonIn.c.bits.source connect in[0].c.bits.size, anonIn.c.bits.size connect in[0].c.bits.param, anonIn.c.bits.param connect in[0].c.bits.opcode, anonIn.c.bits.opcode connect in[0].c.valid, anonIn.c.valid connect anonIn.c.ready, in[0].c.ready node _in_0_c_bits_source_T = or(anonIn.c.bits.source, UInt<1>(0h0)) connect in[0].c.bits.source, _in_0_c_bits_source_T connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 0, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T connect in[0].e.bits.sink, anonIn.e.bits.sink connect in[0].e.valid, anonIn.e.valid connect anonIn.e.ready, in[0].e.ready connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt connect in[1].a.bits.data, anonIn_1.a.bits.data connect in[1].a.bits.mask, anonIn_1.a.bits.mask connect in[1].a.bits.address, anonIn_1.a.bits.address connect in[1].a.bits.source, anonIn_1.a.bits.source connect in[1].a.bits.size, anonIn_1.a.bits.size connect in[1].a.bits.param, anonIn_1.a.bits.param connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode connect in[1].a.valid, anonIn_1.a.valid connect anonIn_1.a.ready, in[1].a.ready node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<2>(0h2)) connect in[1].a.bits.source, _in_1_a_bits_source_T invalidate in[1].b.bits.corrupt invalidate in[1].b.bits.data invalidate in[1].b.bits.mask invalidate in[1].b.bits.address invalidate in[1].b.bits.source invalidate in[1].b.bits.size invalidate in[1].b.bits.param invalidate in[1].b.bits.opcode invalidate in[1].b.valid invalidate in[1].b.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready connect in[1].b.ready, UInt<1>(0h1) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) invalidate in[1].c.bits.corrupt invalidate in[1].c.bits.data invalidate in[1].c.bits.address invalidate in[1].c.bits.source invalidate in[1].c.bits.size invalidate in[1].c.bits.param invalidate in[1].c.bits.opcode invalidate in[1].c.valid invalidate in[1].c.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<1>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<3>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready invalidate _WIRE_5.bits.corrupt invalidate _WIRE_5.bits.data invalidate _WIRE_5.bits.address invalidate _WIRE_5.bits.source invalidate _WIRE_5.bits.size invalidate _WIRE_5.bits.param invalidate _WIRE_5.bits.opcode invalidate _WIRE_5.valid invalidate _WIRE_5.ready connect in[1].c.valid, UInt<1>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt connect anonIn_1.d.bits.data, in[1].d.bits.data connect anonIn_1.d.bits.denied, in[1].d.bits.denied connect anonIn_1.d.bits.sink, in[1].d.bits.sink connect anonIn_1.d.bits.source, in[1].d.bits.source connect anonIn_1.d.bits.size, in[1].d.bits.size connect anonIn_1.d.bits.param, in[1].d.bits.param connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode connect anonIn_1.d.valid, in[1].d.valid connect in[1].d.ready, anonIn_1.d.ready connect anonIn_1.d.bits.source, UInt<1>(0h0) invalidate in[1].e.bits.sink invalidate in[1].e.valid invalidate in[1].e.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_8.bits.sink, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.sink invalidate _WIRE_9.valid invalidate _WIRE_9.ready connect in[1].e.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[1] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready connect out[0].b.bits.corrupt, anonOut.b.bits.corrupt connect out[0].b.bits.data, anonOut.b.bits.data connect out[0].b.bits.mask, anonOut.b.bits.mask connect out[0].b.bits.address, anonOut.b.bits.address connect out[0].b.bits.source, anonOut.b.bits.source connect out[0].b.bits.size, anonOut.b.bits.size connect out[0].b.bits.param, anonOut.b.bits.param connect out[0].b.bits.opcode, anonOut.b.bits.opcode connect out[0].b.valid, anonOut.b.valid connect anonOut.b.ready, out[0].b.ready connect anonOut.c.bits.corrupt, out[0].c.bits.corrupt connect anonOut.c.bits.data, out[0].c.bits.data connect anonOut.c.bits.address, out[0].c.bits.address connect anonOut.c.bits.source, out[0].c.bits.source connect anonOut.c.bits.size, out[0].c.bits.size connect anonOut.c.bits.param, out[0].c.bits.param connect anonOut.c.bits.opcode, out[0].c.bits.opcode connect anonOut.c.valid, out[0].c.valid connect out[0].c.ready, anonOut.c.ready connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T connect anonOut.e.bits.sink, out[0].e.bits.sink connect anonOut.e.valid, out[0].e.valid connect out[0].e.ready, anonOut.e.ready node _anonOut_e_bits_sink_T = bits(out[0].e.bits.sink, 2, 0) connect anonOut.e.bits.sink, _anonOut_e_bits_sink_T node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9) node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(in[1].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9) node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<1>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 0, 0) node _requestBOI_T = shr(out[0].b.bits.source, 1) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<1>(0h1)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) node requestBOI_0_1 = eq(out[0].b.bits.source, UInt<2>(0h2)) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<1>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 0, 0) node _requestDOI_T = shr(out[0].d.bits.source, 1) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<1>(0h1)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<2>(0h2)) node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<3>(0h0)) node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 2, 0) node _requestEIO_T = shr(in[0].e.bits.sink, 3) node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0)) node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits) node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2) node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<3>(0h7)) node requestEIO_0_0 = and(_requestEIO_T_3, _requestEIO_T_4) node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<3>(0h0)) node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 2, 0) node _requestEIO_T_5 = shr(in[1].e.bits.sink, 3) node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0)) node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1) node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7) node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<3>(0h7)) node requestEIO_1_0 = and(_requestEIO_T_8, _requestEIO_T_9) node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3) node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0) node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0)) node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size) node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3) node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0) node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect in[0].a.ready, portsAOI_filtered[0].ready wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered_1[0].bits, in[1].a.bits node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 connect in[1].a.ready, portsAOI_filtered_1[0].ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[0].bits.data, out[0].b.bits.data connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[0].bits.address, out[0].b.bits.address connect portsBIO_filtered[0].bits.source, out[0].b.bits.source connect portsBIO_filtered[0].bits.size, out[0].b.bits.size connect portsBIO_filtered[0].bits.param, out[0].b.bits.param connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[1].bits.data, out[0].b.bits.data connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[1].bits.address, out[0].b.bits.address connect portsBIO_filtered[1].bits.source, out[0].b.bits.source connect portsBIO_filtered[1].bits.size, out[0].b.bits.size connect portsBIO_filtered[1].bits.param, out[0].b.bits.param connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T) connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_2 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1) wire _portsBIO_out_0_b_ready_WIRE : UInt<1> connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_2 connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered[0].bits, in[0].c.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect in[0].c.ready, portsCOI_filtered[0].ready wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered_1[0].bits, in[1].c.bits node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2) connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 connect in[1].c.ready, portsCOI_filtered_1[0].ready wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[1].bits.data, out[0].d.bits.data connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[1].bits.source, out[0].d.bits.source connect portsDIO_filtered[1].bits.size, out[0].d.bits.size connect portsDIO_filtered[1].bits.param, out[0].d.bits.param connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) wire _portsDIO_out_0_d_ready_WIRE : UInt<1> connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[1] connect portsEOI_filtered[0].bits, in[0].e.bits node _portsEOI_filtered_0_valid_T = or(requestEIO_0_0, UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect in[0].e.ready, portsEOI_filtered[0].ready wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[1] connect portsEOI_filtered_1[0].bits, in[1].e.bits node _portsEOI_filtered_0_valid_T_2 = or(requestEIO_1_0, UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2) connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 connect in[1].e.ready, portsEOI_filtered_1[0].ready regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, out[0].a.ready) node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsAOI_filtered[0].valid) node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) connect portsAOI_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) wire _out_0_a_valid_WIRE : UInt<1> connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) connect out[0].a.valid, _out_0_a_valid_T_4 wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) wire _out_0_a_bits_WIRE_1 : UInt<1> connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) wire _out_0_a_bits_WIRE_2 : UInt<64> connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) wire _out_0_a_bits_WIRE_3 : UInt<8> connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 wire _out_0_a_bits_WIRE_4 : { } connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 wire _out_0_a_bits_WIRE_5 : { } connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) wire _out_0_a_bits_WIRE_6 : UInt<32> connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11 connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6 node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) wire _out_0_a_bits_WIRE_7 : UInt<2> connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14 connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7 node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) wire _out_0_a_bits_WIRE_8 : UInt<4> connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17 connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8 node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) wire _out_0_a_bits_WIRE_9 : UInt<3> connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20 connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9 node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) wire _out_0_a_bits_WIRE_10 : UInt<3> connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23 connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10 connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt connect out[0].a.bits.data, _out_0_a_bits_WIRE.data connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask connect out[0].a.bits.address, _out_0_a_bits_WIRE.address connect out[0].a.bits.source, _out_0_a_bits_WIRE.source connect out[0].a.bits.size, _out_0_a_bits_WIRE.size connect out[0].a.bits.param, _out_0_a_bits_WIRE.param connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode connect out[0].c, portsCOI_filtered[0] connect out[0].e, portsEOI_filtered[0] connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) connect in[0].b, portsBIO_filtered[0] connect in[0].d, portsDIO_filtered[0] invalidate in[1].b.bits.corrupt invalidate in[1].b.bits.data invalidate in[1].b.bits.mask invalidate in[1].b.bits.address invalidate in[1].b.bits.source invalidate in[1].b.bits.size invalidate in[1].b.bits.param invalidate in[1].b.bits.opcode connect in[1].d, portsDIO_filtered[1] connect portsBIO_filtered[1].ready, UInt<1>(0h0)
module TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire requestDOI_0_1 = auto_anon_out_d_bits_source == 2'h2; // @[Parameters.scala:46:9] wire portsBIO_filtered_0_valid = auto_anon_out_b_valid & ~(auto_anon_out_b_bits_source[1]); // @[Xbar.scala:355:40] wire portsDIO_filtered_0_valid = auto_anon_out_d_valid & ~(auto_anon_out_d_bits_source[1]); // @[Xbar.scala:355:40] wire portsDIO_filtered_1_valid = auto_anon_out_d_valid & requestDOI_0_1; // @[Xbar.scala:355:40] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire [1:0] readys_valid = {auto_anon_in_1_a_valid, auto_anon_in_0_a_valid}; // @[Arbiter.scala:68:51] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [1:0] readys_readys = ~({readys_mask[1], _readys_filter_T_1[1] | readys_mask[0]} & ({_readys_filter_T_1[0], auto_anon_in_1_a_valid} | _readys_filter_T_1)); // @[package.scala:262:43] wire winner_0 = readys_readys[0] & auto_anon_in_0_a_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_1 = readys_readys[1] & auto_anon_in_1_a_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire _out_0_a_valid_T = auto_anon_in_0_a_valid | auto_anon_in_1_a_valid; // @[Arbiter.scala:79:31]
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_39 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[3], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_51 = and(io.pred_wakeup_port.valid, _T_50) when _T_51 : connect ppred, UInt<1>(0h1) node _T_52 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(_T_53, UInt<1>(0h0)) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_59 = and(io.spec_ld_wakeup[0].valid, _T_58) node _T_60 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_61 = and(_T_59, _T_60) when _T_61 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_62 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_62, UInt<1>(0h1), "") : assert_4 node _T_66 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_67 = and(io.spec_ld_wakeup[0].valid, _T_66) node _T_68 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_69 = and(_T_67, _T_68) when _T_69 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_70 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_70, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_74 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_75 = neq(_T_74, UInt<1>(0h0)) when _T_75 : connect next_state, UInt<2>(0h0) node _T_76 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_76 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_77 = eq(state, UInt<2>(0h1)) when _T_77 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_78 = eq(state, UInt<2>(0h2)) when _T_78 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_79 = eq(state, UInt<2>(0h2)) when _T_79 : node _T_80 = and(p1, p2) node _T_81 = and(_T_80, ppred) when _T_81 : skip else : node _T_82 = and(p1, ppred) when _T_82 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_83 = and(p2, ppred) when _T_83 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state
module IssueSlot_39( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] next_uop_ppred = 4'h0; // @[issue-slot.scala:103:21] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire next_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_prs3_busy = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_ppred_busy = 1'h0; // @[issue-slot.scala:103:21] wire _p3_T = 1'h1; // @[issue-slot.scala:171:11] wire _ppred_T = 1'h1; // @[issue-slot.scala:172:14] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = ~io_in_uop_valid_0 & p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = ~io_in_uop_valid_0 & p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :99:29, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_46 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<1>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 0, 0) node _source_ok_T = shr(io.in.a.bits.source, 1) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<1>(0h1)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<3>(0h4)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_7 node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<1>(0h0)) node uncommonBits = bits(_uncommonBits_T, 0, 0) node _T_4 = shr(io.in.a.bits.source, 1) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<1>(0h1)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_28 = cvt(_T_27) node _T_29 = and(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = asSInt(_T_29) node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0))) node _T_32 = or(_T_26, _T_31) node _T_33 = and(_T_16, _T_24) node _T_34 = and(_T_33, _T_32) node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : node _T_37 = eq(_T_34, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_34, UInt<1>(0h1), "") : assert_1 node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_38 : node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_41 = and(_T_39, _T_40) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<1>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 0, 0) node _T_42 = shr(io.in.a.bits.source, 1) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = leq(UInt<1>(0h0), uncommonBits_1) node _T_45 = and(_T_43, _T_44) node _T_46 = leq(uncommonBits_1, UInt<1>(0h1)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_49 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_50 = or(_T_47, _T_48) node _T_51 = or(_T_50, _T_49) node _T_52 = and(_T_41, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_59, _T_64) node _T_96 = or(_T_95, _T_69) node _T_97 = or(_T_96, _T_74) node _T_98 = or(_T_97, _T_79) node _T_99 = or(_T_98, _T_84) node _T_100 = or(_T_99, _T_89) node _T_101 = or(_T_100, _T_94) node _T_102 = and(_T_54, _T_101) node _T_103 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = or(_T_109, _T_114) node _T_116 = and(_T_104, _T_115) node _T_117 = or(UInt<1>(0h0), _T_102) node _T_118 = or(_T_117, _T_116) node _T_119 = and(_T_53, _T_118) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_119, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<1>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 0, 0) node _T_123 = shr(io.in.a.bits.source, 1) node _T_124 = eq(_T_123, UInt<1>(0h0)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_2) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_2, UInt<1>(0h1)) node _T_128 = and(_T_126, _T_127) node _T_129 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_130 = eq(io.in.a.bits.source, UInt<3>(0h4)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_128 connect _WIRE[1], _T_129 connect _WIRE[2], _T_130 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = mux(_WIRE[0], _T_131, UInt<1>(0h0)) node _T_133 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_135 = or(_T_132, _T_133) node _T_136 = or(_T_135, _T_134) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_136 node _T_137 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_138 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_139 = and(_T_137, _T_138) node _T_140 = or(UInt<1>(0h0), _T_139) node _T_141 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<14>(0h2000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<18>(0h2f000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<27>(0h4000000))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<29>(0h10000000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_145, _T_150) node _T_192 = or(_T_191, _T_155) node _T_193 = or(_T_192, _T_160) node _T_194 = or(_T_193, _T_165) node _T_195 = or(_T_194, _T_170) node _T_196 = or(_T_195, _T_175) node _T_197 = or(_T_196, _T_180) node _T_198 = or(_T_197, _T_185) node _T_199 = or(_T_198, _T_190) node _T_200 = and(_T_140, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = and(_WIRE_1, _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_202, UInt<1>(0h1), "") : assert_3 node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(source_ok, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_209 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_209, UInt<1>(0h1), "") : assert_5 node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(is_aligned, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_216, UInt<1>(0h1), "") : assert_7 node _T_220 = not(io.in.a.bits.mask) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_221, UInt<1>(0h1), "") : assert_8 node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_225, UInt<1>(0h1), "") : assert_9 node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_229 : node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<1>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 0, 0) node _T_233 = shr(io.in.a.bits.source, 1) node _T_234 = eq(_T_233, UInt<1>(0h0)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_3) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_3, UInt<1>(0h1)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_240 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_241 = or(_T_238, _T_239) node _T_242 = or(_T_241, _T_240) node _T_243 = and(_T_232, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<14>(0h2000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<18>(0h2f000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<27>(0h4000000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_250, _T_255) node _T_287 = or(_T_286, _T_260) node _T_288 = or(_T_287, _T_265) node _T_289 = or(_T_288, _T_270) node _T_290 = or(_T_289, _T_275) node _T_291 = or(_T_290, _T_280) node _T_292 = or(_T_291, _T_285) node _T_293 = and(_T_245, _T_292) node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_293) node _T_309 = or(_T_308, _T_307) node _T_310 = and(_T_244, _T_309) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_310, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<1>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 0, 0) node _T_314 = shr(io.in.a.bits.source, 1) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = leq(UInt<1>(0h0), uncommonBits_4) node _T_317 = and(_T_315, _T_316) node _T_318 = leq(uncommonBits_4, UInt<1>(0h1)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_321 = eq(io.in.a.bits.source, UInt<3>(0h4)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_319 connect _WIRE_2[1], _T_320 connect _WIRE_2[2], _T_321 node _T_322 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_323 = mux(_WIRE_2[0], _T_322, UInt<1>(0h0)) node _T_324 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_325 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_326 = or(_T_323, _T_324) node _T_327 = or(_T_326, _T_325) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_327 node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_329 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_330 = and(_T_328, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<14>(0h2000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<13>(0h1000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<18>(0h2f000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<17>(0h10000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_358 = cvt(_T_357) node _T_359 = and(_T_358, asSInt(UInt<13>(0h1000))) node _T_360 = asSInt(_T_359) node _T_361 = eq(_T_360, asSInt(UInt<1>(0h0))) node _T_362 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_368 = cvt(_T_367) node _T_369 = and(_T_368, asSInt(UInt<27>(0h4000000))) node _T_370 = asSInt(_T_369) node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0))) node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<29>(0h10000000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = or(_T_336, _T_341) node _T_383 = or(_T_382, _T_346) node _T_384 = or(_T_383, _T_351) node _T_385 = or(_T_384, _T_356) node _T_386 = or(_T_385, _T_361) node _T_387 = or(_T_386, _T_366) node _T_388 = or(_T_387, _T_371) node _T_389 = or(_T_388, _T_376) node _T_390 = or(_T_389, _T_381) node _T_391 = and(_T_331, _T_390) node _T_392 = or(UInt<1>(0h0), _T_391) node _T_393 = and(_WIRE_3, _T_392) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_393, UInt<1>(0h1), "") : assert_11 node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(source_ok, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_400 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_400, UInt<1>(0h1), "") : assert_13 node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(is_aligned, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_407, UInt<1>(0h1), "") : assert_15 node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_411, UInt<1>(0h1), "") : assert_16 node _T_415 = not(io.in.a.bits.mask) node _T_416 = eq(_T_415, UInt<1>(0h0)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_416, UInt<1>(0h1), "") : assert_17 node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_420, UInt<1>(0h1), "") : assert_18 node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_424 : node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_427 = and(_T_425, _T_426) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<1>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 0, 0) node _T_428 = shr(io.in.a.bits.source, 1) node _T_429 = eq(_T_428, UInt<1>(0h0)) node _T_430 = leq(UInt<1>(0h0), uncommonBits_5) node _T_431 = and(_T_429, _T_430) node _T_432 = leq(uncommonBits_5, UInt<1>(0h1)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_435 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_436 = or(_T_433, _T_434) node _T_437 = or(_T_436, _T_435) node _T_438 = and(_T_427, _T_437) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_439, UInt<1>(0h1), "") : assert_19 node _T_443 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_444 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_445 = and(_T_443, _T_444) node _T_446 = or(UInt<1>(0h0), _T_445) node _T_447 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = and(_T_446, _T_451) node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_455 = and(_T_453, _T_454) node _T_456 = or(UInt<1>(0h0), _T_455) node _T_457 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<14>(0h2000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<18>(0h2f000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<17>(0h10000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<13>(0h1000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<17>(0h10000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<27>(0h4000000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<29>(0h10000000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = or(_T_461, _T_466) node _T_503 = or(_T_502, _T_471) node _T_504 = or(_T_503, _T_476) node _T_505 = or(_T_504, _T_481) node _T_506 = or(_T_505, _T_486) node _T_507 = or(_T_506, _T_491) node _T_508 = or(_T_507, _T_496) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_456, _T_509) node _T_511 = or(UInt<1>(0h0), _T_452) node _T_512 = or(_T_511, _T_510) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_512, UInt<1>(0h1), "") : assert_20 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_522, UInt<1>(0h1), "") : assert_23 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_526, UInt<1>(0h1), "") : assert_24 node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_530, UInt<1>(0h1), "") : assert_25 node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_534 : node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<1>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 0, 0) node _T_538 = shr(io.in.a.bits.source, 1) node _T_539 = eq(_T_538, UInt<1>(0h0)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_6) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_6, UInt<1>(0h1)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_545 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_546 = or(_T_543, _T_544) node _T_547 = or(_T_546, _T_545) node _T_548 = and(_T_537, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_551 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_552 = and(_T_550, _T_551) node _T_553 = or(UInt<1>(0h0), _T_552) node _T_554 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = and(_T_553, _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<14>(0h2000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_570 = cvt(_T_569) node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000))) node _T_572 = asSInt(_T_571) node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0))) node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<27>(0h4000000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<29>(0h10000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = or(_T_568, _T_573) node _T_605 = or(_T_604, _T_578) node _T_606 = or(_T_605, _T_583) node _T_607 = or(_T_606, _T_588) node _T_608 = or(_T_607, _T_593) node _T_609 = or(_T_608, _T_598) node _T_610 = or(_T_609, _T_603) node _T_611 = and(_T_563, _T_610) node _T_612 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<17>(0h10000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = and(_T_612, _T_617) node _T_619 = or(UInt<1>(0h0), _T_559) node _T_620 = or(_T_619, _T_611) node _T_621 = or(_T_620, _T_618) node _T_622 = and(_T_549, _T_621) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_622, UInt<1>(0h1), "") : assert_26 node _T_626 = asUInt(reset) node _T_627 = eq(_T_626, UInt<1>(0h0)) when _T_627 : node _T_628 = eq(source_ok, UInt<1>(0h0)) when _T_628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(is_aligned, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_632 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_632, UInt<1>(0h1), "") : assert_29 node _T_636 = eq(io.in.a.bits.mask, mask) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_636, UInt<1>(0h1), "") : assert_30 node _T_640 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_640 : node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_643 = and(_T_641, _T_642) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<1>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 0, 0) node _T_644 = shr(io.in.a.bits.source, 1) node _T_645 = eq(_T_644, UInt<1>(0h0)) node _T_646 = leq(UInt<1>(0h0), uncommonBits_7) node _T_647 = and(_T_645, _T_646) node _T_648 = leq(uncommonBits_7, UInt<1>(0h1)) node _T_649 = and(_T_647, _T_648) node _T_650 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_651 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_652 = or(_T_649, _T_650) node _T_653 = or(_T_652, _T_651) node _T_654 = and(_T_643, _T_653) node _T_655 = or(UInt<1>(0h0), _T_654) node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = and(_T_659, _T_664) node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_667 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_668 = and(_T_666, _T_667) node _T_669 = or(UInt<1>(0h0), _T_668) node _T_670 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<14>(0h2000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<18>(0h2f000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<17>(0h10000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_686 = cvt(_T_685) node _T_687 = and(_T_686, asSInt(UInt<13>(0h1000))) node _T_688 = asSInt(_T_687) node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0))) node _T_690 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<17>(0h10000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_696 = cvt(_T_695) node _T_697 = and(_T_696, asSInt(UInt<27>(0h4000000))) node _T_698 = asSInt(_T_697) node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0))) node _T_700 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<29>(0h10000000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = or(_T_674, _T_679) node _T_711 = or(_T_710, _T_684) node _T_712 = or(_T_711, _T_689) node _T_713 = or(_T_712, _T_694) node _T_714 = or(_T_713, _T_699) node _T_715 = or(_T_714, _T_704) node _T_716 = or(_T_715, _T_709) node _T_717 = and(_T_669, _T_716) node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_720 = cvt(_T_719) node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000))) node _T_722 = asSInt(_T_721) node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) node _T_724 = and(_T_718, _T_723) node _T_725 = or(UInt<1>(0h0), _T_665) node _T_726 = or(_T_725, _T_717) node _T_727 = or(_T_726, _T_724) node _T_728 = and(_T_655, _T_727) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_728, UInt<1>(0h1), "") : assert_31 node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(source_ok, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(is_aligned, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_738 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_738, UInt<1>(0h1), "") : assert_34 node _T_742 = not(mask) node _T_743 = and(io.in.a.bits.mask, _T_742) node _T_744 = eq(_T_743, UInt<1>(0h0)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_744, UInt<1>(0h1), "") : assert_35 node _T_748 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_748 : node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_750 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<1>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 0, 0) node _T_752 = shr(io.in.a.bits.source, 1) node _T_753 = eq(_T_752, UInt<1>(0h0)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_8) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_8, UInt<1>(0h1)) node _T_757 = and(_T_755, _T_756) node _T_758 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_759 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_760 = or(_T_757, _T_758) node _T_761 = or(_T_760, _T_759) node _T_762 = and(_T_751, _T_761) node _T_763 = or(UInt<1>(0h0), _T_762) node _T_764 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_765 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_766 = and(_T_764, _T_765) node _T_767 = or(UInt<1>(0h0), _T_766) node _T_768 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_769 = cvt(_T_768) node _T_770 = and(_T_769, asSInt(UInt<14>(0h2000))) node _T_771 = asSInt(_T_770) node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0))) node _T_773 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_774 = cvt(_T_773) node _T_775 = and(_T_774, asSInt(UInt<13>(0h1000))) node _T_776 = asSInt(_T_775) node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0))) node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<18>(0h2f000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_784 = cvt(_T_783) node _T_785 = and(_T_784, asSInt(UInt<17>(0h10000))) node _T_786 = asSInt(_T_785) node _T_787 = eq(_T_786, asSInt(UInt<1>(0h0))) node _T_788 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_789 = cvt(_T_788) node _T_790 = and(_T_789, asSInt(UInt<13>(0h1000))) node _T_791 = asSInt(_T_790) node _T_792 = eq(_T_791, asSInt(UInt<1>(0h0))) node _T_793 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_794 = cvt(_T_793) node _T_795 = and(_T_794, asSInt(UInt<17>(0h10000))) node _T_796 = asSInt(_T_795) node _T_797 = eq(_T_796, asSInt(UInt<1>(0h0))) node _T_798 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_799 = cvt(_T_798) node _T_800 = and(_T_799, asSInt(UInt<27>(0h4000000))) node _T_801 = asSInt(_T_800) node _T_802 = eq(_T_801, asSInt(UInt<1>(0h0))) node _T_803 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<13>(0h1000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_809 = cvt(_T_808) node _T_810 = and(_T_809, asSInt(UInt<29>(0h10000000))) node _T_811 = asSInt(_T_810) node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0))) node _T_813 = or(_T_772, _T_777) node _T_814 = or(_T_813, _T_782) node _T_815 = or(_T_814, _T_787) node _T_816 = or(_T_815, _T_792) node _T_817 = or(_T_816, _T_797) node _T_818 = or(_T_817, _T_802) node _T_819 = or(_T_818, _T_807) node _T_820 = or(_T_819, _T_812) node _T_821 = and(_T_767, _T_820) node _T_822 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_823 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_824 = cvt(_T_823) node _T_825 = and(_T_824, asSInt(UInt<17>(0h10000))) node _T_826 = asSInt(_T_825) node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0))) node _T_828 = and(_T_822, _T_827) node _T_829 = or(UInt<1>(0h0), _T_821) node _T_830 = or(_T_829, _T_828) node _T_831 = and(_T_763, _T_830) node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_T_831, UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_831, UInt<1>(0h1), "") : assert_36 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(source_ok, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(is_aligned, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_841 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(_T_841, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_841, UInt<1>(0h1), "") : assert_39 node _T_845 = eq(io.in.a.bits.mask, mask) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_845, UInt<1>(0h1), "") : assert_40 node _T_849 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_849 : node _T_850 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_851 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_852 = and(_T_850, _T_851) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<1>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 0, 0) node _T_853 = shr(io.in.a.bits.source, 1) node _T_854 = eq(_T_853, UInt<1>(0h0)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_9) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_9, UInt<1>(0h1)) node _T_858 = and(_T_856, _T_857) node _T_859 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_860 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_861 = or(_T_858, _T_859) node _T_862 = or(_T_861, _T_860) node _T_863 = and(_T_852, _T_862) node _T_864 = or(UInt<1>(0h0), _T_863) node _T_865 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_866 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_867 = and(_T_865, _T_866) node _T_868 = or(UInt<1>(0h0), _T_867) node _T_869 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<14>(0h2000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<18>(0h2f000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<17>(0h10000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<13>(0h1000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<17>(0h10000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<29>(0h10000000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = or(_T_873, _T_878) node _T_915 = or(_T_914, _T_883) node _T_916 = or(_T_915, _T_888) node _T_917 = or(_T_916, _T_893) node _T_918 = or(_T_917, _T_898) node _T_919 = or(_T_918, _T_903) node _T_920 = or(_T_919, _T_908) node _T_921 = or(_T_920, _T_913) node _T_922 = and(_T_868, _T_921) node _T_923 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_924 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = and(_T_923, _T_928) node _T_930 = or(UInt<1>(0h0), _T_922) node _T_931 = or(_T_930, _T_929) node _T_932 = and(_T_864, _T_931) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_932, UInt<1>(0h1), "") : assert_41 node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(source_ok, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(is_aligned, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_942 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_942, UInt<1>(0h1), "") : assert_44 node _T_946 = eq(io.in.a.bits.mask, mask) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_946, UInt<1>(0h1), "") : assert_45 node _T_950 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_950 : node _T_951 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_952 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<1>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 0, 0) node _T_954 = shr(io.in.a.bits.source, 1) node _T_955 = eq(_T_954, UInt<1>(0h0)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_10) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_10, UInt<1>(0h1)) node _T_959 = and(_T_957, _T_958) node _T_960 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_961 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_962 = or(_T_959, _T_960) node _T_963 = or(_T_962, _T_961) node _T_964 = and(_T_953, _T_963) node _T_965 = or(UInt<1>(0h0), _T_964) node _T_966 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_967 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_968 = and(_T_966, _T_967) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_971 = cvt(_T_970) node _T_972 = and(_T_971, asSInt(UInt<13>(0h1000))) node _T_973 = asSInt(_T_972) node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0))) node _T_975 = and(_T_969, _T_974) node _T_976 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_977 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_978 = cvt(_T_977) node _T_979 = and(_T_978, asSInt(UInt<14>(0h2000))) node _T_980 = asSInt(_T_979) node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0))) node _T_982 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<17>(0h10000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<18>(0h2f000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<13>(0h1000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<27>(0h4000000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = or(_T_981, _T_986) node _T_1013 = or(_T_1012, _T_991) node _T_1014 = or(_T_1013, _T_996) node _T_1015 = or(_T_1014, _T_1001) node _T_1016 = or(_T_1015, _T_1006) node _T_1017 = or(_T_1016, _T_1011) node _T_1018 = and(_T_976, _T_1017) node _T_1019 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1020 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1021 = and(_T_1019, _T_1020) node _T_1022 = or(UInt<1>(0h0), _T_1021) node _T_1023 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1024 = cvt(_T_1023) node _T_1025 = and(_T_1024, asSInt(UInt<17>(0h10000))) node _T_1026 = asSInt(_T_1025) node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0))) node _T_1028 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1029 = cvt(_T_1028) node _T_1030 = and(_T_1029, asSInt(UInt<29>(0h10000000))) node _T_1031 = asSInt(_T_1030) node _T_1032 = eq(_T_1031, asSInt(UInt<1>(0h0))) node _T_1033 = or(_T_1027, _T_1032) node _T_1034 = and(_T_1022, _T_1033) node _T_1035 = or(UInt<1>(0h0), _T_975) node _T_1036 = or(_T_1035, _T_1018) node _T_1037 = or(_T_1036, _T_1034) node _T_1038 = and(_T_965, _T_1037) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_46 node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(source_ok, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(is_aligned, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1048 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_49 node _T_1052 = eq(io.in.a.bits.mask, mask) node _T_1053 = asUInt(reset) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) when _T_1054 : node _T_1055 = eq(_T_1052, UInt<1>(0h0)) when _T_1055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1052, UInt<1>(0h1), "") : assert_50 node _T_1056 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1060 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<1>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 0, 0) node _source_ok_T_9 = shr(io.in.d.bits.source, 1) node _source_ok_T_10 = eq(_source_ok_T_9, UInt<1>(0h0)) node _source_ok_T_11 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = leq(source_ok_uncommonBits_1, UInt<1>(0h1)) node _source_ok_T_14 = and(_source_ok_T_12, _source_ok_T_13) node _source_ok_T_15 = eq(io.in.d.bits.source, UInt<2>(0h2)) node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<3>(0h4)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_14 connect _source_ok_WIRE_1[1], _source_ok_T_15 connect _source_ok_WIRE_1[2], _source_ok_T_16 node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1064 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1064 : node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(source_ok_1, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1068 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_54 node _T_1072 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_55 node _T_1076 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_56 node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_57 node _T_1084 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1084 : node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(source_ok_1, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(sink_ok, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1091 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1092 = asUInt(reset) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) when _T_1093 : node _T_1094 = eq(_T_1091, UInt<1>(0h0)) when _T_1094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1091, UInt<1>(0h1), "") : assert_60 node _T_1095 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_T_1095, UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1095, UInt<1>(0h1), "") : assert_61 node _T_1099 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_62 node _T_1103 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(_T_1103, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1103, UInt<1>(0h1), "") : assert_63 node _T_1107 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1108 = or(UInt<1>(0h1), _T_1107) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_64 node _T_1112 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1112 : node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(source_ok_1, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(sink_ok, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1119 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_67 node _T_1123 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_68 node _T_1127 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_69 node _T_1131 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1132 = or(_T_1131, io.in.d.bits.corrupt) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_70 node _T_1136 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1137 = or(UInt<1>(0h1), _T_1136) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_71 node _T_1141 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1141 : node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(source_ok_1, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1145 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_73 node _T_1149 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_74 node _T_1153 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1154 = or(UInt<1>(0h1), _T_1153) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_75 node _T_1158 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1158 : node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(source_ok_1, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1162 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_77 node _T_1166 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1167 = or(_T_1166, io.in.d.bits.corrupt) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_78 node _T_1171 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1172 = or(UInt<1>(0h1), _T_1171) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_79 node _T_1176 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1176 : node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(source_ok_1, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1180 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_81 node _T_1184 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_82 node _T_1188 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1189 = or(UInt<1>(0h1), _T_1188) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1193 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<1>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 0, 0) node _T_1197 = shr(io.in.b.bits.source, 1) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1200 = and(_T_1198, _T_1199) node _T_1201 = leq(uncommonBits_11, UInt<1>(0h1)) node _T_1202 = and(_T_1200, _T_1201) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) node _T_1204 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1205 = cvt(_T_1204) node _T_1206 = and(_T_1205, asSInt(UInt<1>(0h0))) node _T_1207 = asSInt(_T_1206) node _T_1208 = eq(_T_1207, asSInt(UInt<1>(0h0))) node _T_1209 = or(_T_1203, _T_1208) node _T_1210 = eq(io.in.b.bits.source, UInt<2>(0h2)) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) node _T_1212 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1213 = cvt(_T_1212) node _T_1214 = and(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = asSInt(_T_1214) node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = or(_T_1211, _T_1216) node _T_1218 = eq(io.in.b.bits.source, UInt<3>(0h4)) node _T_1219 = eq(_T_1218, UInt<1>(0h0)) node _T_1220 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<1>(0h0))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = or(_T_1219, _T_1224) node _T_1226 = and(_T_1209, _T_1217) node _T_1227 = and(_T_1226, _T_1225) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<1>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 0, 0) node _legal_source_T = shr(io.in.b.bits.source, 1) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<1>(0h1)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<2>(0h2)) node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<3>(0h4)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_7 node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<2>(0h2), UInt<1>(0h0)) node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10) wire _legal_source_WIRE_1 : UInt<3> connect _legal_source_WIRE_1, _legal_source_T_12 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1231 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1231 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<1>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 0, 0) node _T_1232 = shr(io.in.b.bits.source, 1) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) node _T_1234 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1235 = and(_T_1233, _T_1234) node _T_1236 = leq(uncommonBits_12, UInt<1>(0h1)) node _T_1237 = and(_T_1235, _T_1236) node _T_1238 = eq(io.in.b.bits.source, UInt<2>(0h2)) node _T_1239 = eq(io.in.b.bits.source, UInt<3>(0h4)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1237 connect _WIRE_4[1], _T_1238 connect _WIRE_4[2], _T_1239 node _T_1240 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1241 = mux(_WIRE_4[0], _T_1240, UInt<1>(0h0)) node _T_1242 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1243 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1242) node _T_1245 = or(_T_1244, _T_1243) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1245 node _T_1246 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1247 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1248 = and(_T_1246, _T_1247) node _T_1249 = or(UInt<1>(0h0), _T_1248) node _T_1250 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1251 = cvt(_T_1250) node _T_1252 = and(_T_1251, asSInt(UInt<14>(0h2000))) node _T_1253 = asSInt(_T_1252) node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) node _T_1255 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1256 = cvt(_T_1255) node _T_1257 = and(_T_1256, asSInt(UInt<13>(0h1000))) node _T_1258 = asSInt(_T_1257) node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0))) node _T_1260 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1261 = cvt(_T_1260) node _T_1262 = and(_T_1261, asSInt(UInt<17>(0h10000))) node _T_1263 = asSInt(_T_1262) node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1266 = cvt(_T_1265) node _T_1267 = and(_T_1266, asSInt(UInt<18>(0h2f000))) node _T_1268 = asSInt(_T_1267) node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0))) node _T_1270 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1271 = cvt(_T_1270) node _T_1272 = and(_T_1271, asSInt(UInt<17>(0h10000))) node _T_1273 = asSInt(_T_1272) node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0))) node _T_1275 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1276 = cvt(_T_1275) node _T_1277 = and(_T_1276, asSInt(UInt<13>(0h1000))) node _T_1278 = asSInt(_T_1277) node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0))) node _T_1280 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1281 = cvt(_T_1280) node _T_1282 = and(_T_1281, asSInt(UInt<17>(0h10000))) node _T_1283 = asSInt(_T_1282) node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0))) node _T_1285 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1286 = cvt(_T_1285) node _T_1287 = and(_T_1286, asSInt(UInt<27>(0h4000000))) node _T_1288 = asSInt(_T_1287) node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0))) node _T_1290 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1291 = cvt(_T_1290) node _T_1292 = and(_T_1291, asSInt(UInt<13>(0h1000))) node _T_1293 = asSInt(_T_1292) node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) node _T_1295 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1296 = cvt(_T_1295) node _T_1297 = and(_T_1296, asSInt(UInt<29>(0h10000000))) node _T_1298 = asSInt(_T_1297) node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0))) node _T_1300 = or(_T_1254, _T_1259) node _T_1301 = or(_T_1300, _T_1264) node _T_1302 = or(_T_1301, _T_1269) node _T_1303 = or(_T_1302, _T_1274) node _T_1304 = or(_T_1303, _T_1279) node _T_1305 = or(_T_1304, _T_1284) node _T_1306 = or(_T_1305, _T_1289) node _T_1307 = or(_T_1306, _T_1294) node _T_1308 = or(_T_1307, _T_1299) node _T_1309 = and(_T_1249, _T_1308) node _T_1310 = or(UInt<1>(0h0), _T_1309) node _T_1311 = and(_WIRE_5, _T_1310) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_86 node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(address_ok, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1318 = asUInt(reset) node _T_1319 = eq(_T_1318, UInt<1>(0h0)) when _T_1319 : node _T_1320 = eq(legal_source, UInt<1>(0h0)) when _T_1320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1321 = asUInt(reset) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) when _T_1322 : node _T_1323 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1324 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_90 node _T_1328 = eq(io.in.b.bits.mask, mask_1) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_91 node _T_1332 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(_T_1332, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1332, UInt<1>(0h1), "") : assert_92 node _T_1336 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1336 : node _T_1337 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1338 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1339 = and(_T_1337, _T_1338) node _T_1340 = or(UInt<1>(0h0), _T_1339) node _T_1341 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1342 = cvt(_T_1341) node _T_1343 = and(_T_1342, asSInt(UInt<14>(0h2000))) node _T_1344 = asSInt(_T_1343) node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0))) node _T_1346 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1347 = cvt(_T_1346) node _T_1348 = and(_T_1347, asSInt(UInt<13>(0h1000))) node _T_1349 = asSInt(_T_1348) node _T_1350 = eq(_T_1349, asSInt(UInt<1>(0h0))) node _T_1351 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1352 = cvt(_T_1351) node _T_1353 = and(_T_1352, asSInt(UInt<17>(0h10000))) node _T_1354 = asSInt(_T_1353) node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0))) node _T_1356 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1357 = cvt(_T_1356) node _T_1358 = and(_T_1357, asSInt(UInt<18>(0h2f000))) node _T_1359 = asSInt(_T_1358) node _T_1360 = eq(_T_1359, asSInt(UInt<1>(0h0))) node _T_1361 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1362 = cvt(_T_1361) node _T_1363 = and(_T_1362, asSInt(UInt<17>(0h10000))) node _T_1364 = asSInt(_T_1363) node _T_1365 = eq(_T_1364, asSInt(UInt<1>(0h0))) node _T_1366 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1367 = cvt(_T_1366) node _T_1368 = and(_T_1367, asSInt(UInt<13>(0h1000))) node _T_1369 = asSInt(_T_1368) node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0))) node _T_1371 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1372 = cvt(_T_1371) node _T_1373 = and(_T_1372, asSInt(UInt<17>(0h10000))) node _T_1374 = asSInt(_T_1373) node _T_1375 = eq(_T_1374, asSInt(UInt<1>(0h0))) node _T_1376 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1377 = cvt(_T_1376) node _T_1378 = and(_T_1377, asSInt(UInt<27>(0h4000000))) node _T_1379 = asSInt(_T_1378) node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0))) node _T_1381 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1382 = cvt(_T_1381) node _T_1383 = and(_T_1382, asSInt(UInt<13>(0h1000))) node _T_1384 = asSInt(_T_1383) node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0))) node _T_1386 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1387 = cvt(_T_1386) node _T_1388 = and(_T_1387, asSInt(UInt<29>(0h10000000))) node _T_1389 = asSInt(_T_1388) node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0))) node _T_1391 = or(_T_1345, _T_1350) node _T_1392 = or(_T_1391, _T_1355) node _T_1393 = or(_T_1392, _T_1360) node _T_1394 = or(_T_1393, _T_1365) node _T_1395 = or(_T_1394, _T_1370) node _T_1396 = or(_T_1395, _T_1375) node _T_1397 = or(_T_1396, _T_1380) node _T_1398 = or(_T_1397, _T_1385) node _T_1399 = or(_T_1398, _T_1390) node _T_1400 = and(_T_1340, _T_1399) node _T_1401 = or(UInt<1>(0h0), _T_1400) node _T_1402 = and(UInt<1>(0h0), _T_1401) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_93 node _T_1406 = asUInt(reset) node _T_1407 = eq(_T_1406, UInt<1>(0h0)) when _T_1407 : node _T_1408 = eq(address_ok, UInt<1>(0h0)) when _T_1408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1409 = asUInt(reset) node _T_1410 = eq(_T_1409, UInt<1>(0h0)) when _T_1410 : node _T_1411 = eq(legal_source, UInt<1>(0h0)) when _T_1411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1412 = asUInt(reset) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) when _T_1413 : node _T_1414 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1415 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1416 = asUInt(reset) node _T_1417 = eq(_T_1416, UInt<1>(0h0)) when _T_1417 : node _T_1418 = eq(_T_1415, UInt<1>(0h0)) when _T_1418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1415, UInt<1>(0h1), "") : assert_97 node _T_1419 = eq(io.in.b.bits.mask, mask_1) node _T_1420 = asUInt(reset) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(_T_1419, UInt<1>(0h0)) when _T_1422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1419, UInt<1>(0h1), "") : assert_98 node _T_1423 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1424 = asUInt(reset) node _T_1425 = eq(_T_1424, UInt<1>(0h0)) when _T_1425 : node _T_1426 = eq(_T_1423, UInt<1>(0h0)) when _T_1426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1423, UInt<1>(0h1), "") : assert_99 node _T_1427 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1427 : node _T_1428 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1429 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1430 = and(_T_1428, _T_1429) node _T_1431 = or(UInt<1>(0h0), _T_1430) node _T_1432 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1433 = cvt(_T_1432) node _T_1434 = and(_T_1433, asSInt(UInt<14>(0h2000))) node _T_1435 = asSInt(_T_1434) node _T_1436 = eq(_T_1435, asSInt(UInt<1>(0h0))) node _T_1437 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1438 = cvt(_T_1437) node _T_1439 = and(_T_1438, asSInt(UInt<13>(0h1000))) node _T_1440 = asSInt(_T_1439) node _T_1441 = eq(_T_1440, asSInt(UInt<1>(0h0))) node _T_1442 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1443 = cvt(_T_1442) node _T_1444 = and(_T_1443, asSInt(UInt<17>(0h10000))) node _T_1445 = asSInt(_T_1444) node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0))) node _T_1447 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1448 = cvt(_T_1447) node _T_1449 = and(_T_1448, asSInt(UInt<18>(0h2f000))) node _T_1450 = asSInt(_T_1449) node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0))) node _T_1452 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1453 = cvt(_T_1452) node _T_1454 = and(_T_1453, asSInt(UInt<17>(0h10000))) node _T_1455 = asSInt(_T_1454) node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0))) node _T_1457 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1458 = cvt(_T_1457) node _T_1459 = and(_T_1458, asSInt(UInt<13>(0h1000))) node _T_1460 = asSInt(_T_1459) node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0))) node _T_1462 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1463 = cvt(_T_1462) node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000))) node _T_1465 = asSInt(_T_1464) node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0))) node _T_1467 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1468 = cvt(_T_1467) node _T_1469 = and(_T_1468, asSInt(UInt<27>(0h4000000))) node _T_1470 = asSInt(_T_1469) node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0))) node _T_1472 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1473 = cvt(_T_1472) node _T_1474 = and(_T_1473, asSInt(UInt<13>(0h1000))) node _T_1475 = asSInt(_T_1474) node _T_1476 = eq(_T_1475, asSInt(UInt<1>(0h0))) node _T_1477 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1478 = cvt(_T_1477) node _T_1479 = and(_T_1478, asSInt(UInt<29>(0h10000000))) node _T_1480 = asSInt(_T_1479) node _T_1481 = eq(_T_1480, asSInt(UInt<1>(0h0))) node _T_1482 = or(_T_1436, _T_1441) node _T_1483 = or(_T_1482, _T_1446) node _T_1484 = or(_T_1483, _T_1451) node _T_1485 = or(_T_1484, _T_1456) node _T_1486 = or(_T_1485, _T_1461) node _T_1487 = or(_T_1486, _T_1466) node _T_1488 = or(_T_1487, _T_1471) node _T_1489 = or(_T_1488, _T_1476) node _T_1490 = or(_T_1489, _T_1481) node _T_1491 = and(_T_1431, _T_1490) node _T_1492 = or(UInt<1>(0h0), _T_1491) node _T_1493 = and(UInt<1>(0h0), _T_1492) node _T_1494 = asUInt(reset) node _T_1495 = eq(_T_1494, UInt<1>(0h0)) when _T_1495 : node _T_1496 = eq(_T_1493, UInt<1>(0h0)) when _T_1496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1493, UInt<1>(0h1), "") : assert_100 node _T_1497 = asUInt(reset) node _T_1498 = eq(_T_1497, UInt<1>(0h0)) when _T_1498 : node _T_1499 = eq(address_ok, UInt<1>(0h0)) when _T_1499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1500 = asUInt(reset) node _T_1501 = eq(_T_1500, UInt<1>(0h0)) when _T_1501 : node _T_1502 = eq(legal_source, UInt<1>(0h0)) when _T_1502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1503 = asUInt(reset) node _T_1504 = eq(_T_1503, UInt<1>(0h0)) when _T_1504 : node _T_1505 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1506 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1507 = asUInt(reset) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) when _T_1508 : node _T_1509 = eq(_T_1506, UInt<1>(0h0)) when _T_1509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1506, UInt<1>(0h1), "") : assert_104 node _T_1510 = eq(io.in.b.bits.mask, mask_1) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_105 node _T_1514 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1514 : node _T_1515 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1516 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1517 = and(_T_1515, _T_1516) node _T_1518 = or(UInt<1>(0h0), _T_1517) node _T_1519 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1520 = cvt(_T_1519) node _T_1521 = and(_T_1520, asSInt(UInt<14>(0h2000))) node _T_1522 = asSInt(_T_1521) node _T_1523 = eq(_T_1522, asSInt(UInt<1>(0h0))) node _T_1524 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1525 = cvt(_T_1524) node _T_1526 = and(_T_1525, asSInt(UInt<13>(0h1000))) node _T_1527 = asSInt(_T_1526) node _T_1528 = eq(_T_1527, asSInt(UInt<1>(0h0))) node _T_1529 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1530 = cvt(_T_1529) node _T_1531 = and(_T_1530, asSInt(UInt<17>(0h10000))) node _T_1532 = asSInt(_T_1531) node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0))) node _T_1534 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<18>(0h2f000))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1540 = cvt(_T_1539) node _T_1541 = and(_T_1540, asSInt(UInt<17>(0h10000))) node _T_1542 = asSInt(_T_1541) node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0))) node _T_1544 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1545 = cvt(_T_1544) node _T_1546 = and(_T_1545, asSInt(UInt<13>(0h1000))) node _T_1547 = asSInt(_T_1546) node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1550 = cvt(_T_1549) node _T_1551 = and(_T_1550, asSInt(UInt<17>(0h10000))) node _T_1552 = asSInt(_T_1551) node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0))) node _T_1554 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1555 = cvt(_T_1554) node _T_1556 = and(_T_1555, asSInt(UInt<27>(0h4000000))) node _T_1557 = asSInt(_T_1556) node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) node _T_1559 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1560 = cvt(_T_1559) node _T_1561 = and(_T_1560, asSInt(UInt<13>(0h1000))) node _T_1562 = asSInt(_T_1561) node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0))) node _T_1564 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1565 = cvt(_T_1564) node _T_1566 = and(_T_1565, asSInt(UInt<29>(0h10000000))) node _T_1567 = asSInt(_T_1566) node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0))) node _T_1569 = or(_T_1523, _T_1528) node _T_1570 = or(_T_1569, _T_1533) node _T_1571 = or(_T_1570, _T_1538) node _T_1572 = or(_T_1571, _T_1543) node _T_1573 = or(_T_1572, _T_1548) node _T_1574 = or(_T_1573, _T_1553) node _T_1575 = or(_T_1574, _T_1558) node _T_1576 = or(_T_1575, _T_1563) node _T_1577 = or(_T_1576, _T_1568) node _T_1578 = and(_T_1518, _T_1577) node _T_1579 = or(UInt<1>(0h0), _T_1578) node _T_1580 = and(UInt<1>(0h0), _T_1579) node _T_1581 = asUInt(reset) node _T_1582 = eq(_T_1581, UInt<1>(0h0)) when _T_1582 : node _T_1583 = eq(_T_1580, UInt<1>(0h0)) when _T_1583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1580, UInt<1>(0h1), "") : assert_106 node _T_1584 = asUInt(reset) node _T_1585 = eq(_T_1584, UInt<1>(0h0)) when _T_1585 : node _T_1586 = eq(address_ok, UInt<1>(0h0)) when _T_1586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1587 = asUInt(reset) node _T_1588 = eq(_T_1587, UInt<1>(0h0)) when _T_1588 : node _T_1589 = eq(legal_source, UInt<1>(0h0)) when _T_1589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1593 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(_T_1593, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1593, UInt<1>(0h1), "") : assert_110 node _T_1597 = not(mask_1) node _T_1598 = and(io.in.b.bits.mask, _T_1597) node _T_1599 = eq(_T_1598, UInt<1>(0h0)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_111 node _T_1603 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1603 : node _T_1604 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1605 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1606 = and(_T_1604, _T_1605) node _T_1607 = or(UInt<1>(0h0), _T_1606) node _T_1608 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1609 = cvt(_T_1608) node _T_1610 = and(_T_1609, asSInt(UInt<14>(0h2000))) node _T_1611 = asSInt(_T_1610) node _T_1612 = eq(_T_1611, asSInt(UInt<1>(0h0))) node _T_1613 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1614 = cvt(_T_1613) node _T_1615 = and(_T_1614, asSInt(UInt<13>(0h1000))) node _T_1616 = asSInt(_T_1615) node _T_1617 = eq(_T_1616, asSInt(UInt<1>(0h0))) node _T_1618 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1619 = cvt(_T_1618) node _T_1620 = and(_T_1619, asSInt(UInt<17>(0h10000))) node _T_1621 = asSInt(_T_1620) node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0))) node _T_1623 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1624 = cvt(_T_1623) node _T_1625 = and(_T_1624, asSInt(UInt<18>(0h2f000))) node _T_1626 = asSInt(_T_1625) node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0))) node _T_1628 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1629 = cvt(_T_1628) node _T_1630 = and(_T_1629, asSInt(UInt<17>(0h10000))) node _T_1631 = asSInt(_T_1630) node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0))) node _T_1633 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1634 = cvt(_T_1633) node _T_1635 = and(_T_1634, asSInt(UInt<13>(0h1000))) node _T_1636 = asSInt(_T_1635) node _T_1637 = eq(_T_1636, asSInt(UInt<1>(0h0))) node _T_1638 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1639 = cvt(_T_1638) node _T_1640 = and(_T_1639, asSInt(UInt<17>(0h10000))) node _T_1641 = asSInt(_T_1640) node _T_1642 = eq(_T_1641, asSInt(UInt<1>(0h0))) node _T_1643 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1644 = cvt(_T_1643) node _T_1645 = and(_T_1644, asSInt(UInt<27>(0h4000000))) node _T_1646 = asSInt(_T_1645) node _T_1647 = eq(_T_1646, asSInt(UInt<1>(0h0))) node _T_1648 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1649 = cvt(_T_1648) node _T_1650 = and(_T_1649, asSInt(UInt<13>(0h1000))) node _T_1651 = asSInt(_T_1650) node _T_1652 = eq(_T_1651, asSInt(UInt<1>(0h0))) node _T_1653 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1654 = cvt(_T_1653) node _T_1655 = and(_T_1654, asSInt(UInt<29>(0h10000000))) node _T_1656 = asSInt(_T_1655) node _T_1657 = eq(_T_1656, asSInt(UInt<1>(0h0))) node _T_1658 = or(_T_1612, _T_1617) node _T_1659 = or(_T_1658, _T_1622) node _T_1660 = or(_T_1659, _T_1627) node _T_1661 = or(_T_1660, _T_1632) node _T_1662 = or(_T_1661, _T_1637) node _T_1663 = or(_T_1662, _T_1642) node _T_1664 = or(_T_1663, _T_1647) node _T_1665 = or(_T_1664, _T_1652) node _T_1666 = or(_T_1665, _T_1657) node _T_1667 = and(_T_1607, _T_1666) node _T_1668 = or(UInt<1>(0h0), _T_1667) node _T_1669 = and(UInt<1>(0h0), _T_1668) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_112 node _T_1673 = asUInt(reset) node _T_1674 = eq(_T_1673, UInt<1>(0h0)) when _T_1674 : node _T_1675 = eq(address_ok, UInt<1>(0h0)) when _T_1675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1676 = asUInt(reset) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) when _T_1677 : node _T_1678 = eq(legal_source, UInt<1>(0h0)) when _T_1678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1679 = asUInt(reset) node _T_1680 = eq(_T_1679, UInt<1>(0h0)) when _T_1680 : node _T_1681 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1682 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1683 = asUInt(reset) node _T_1684 = eq(_T_1683, UInt<1>(0h0)) when _T_1684 : node _T_1685 = eq(_T_1682, UInt<1>(0h0)) when _T_1685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1682, UInt<1>(0h1), "") : assert_116 node _T_1686 = eq(io.in.b.bits.mask, mask_1) node _T_1687 = asUInt(reset) node _T_1688 = eq(_T_1687, UInt<1>(0h0)) when _T_1688 : node _T_1689 = eq(_T_1686, UInt<1>(0h0)) when _T_1689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1686, UInt<1>(0h1), "") : assert_117 node _T_1690 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1690 : node _T_1691 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1692 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1693 = and(_T_1691, _T_1692) node _T_1694 = or(UInt<1>(0h0), _T_1693) node _T_1695 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1696 = cvt(_T_1695) node _T_1697 = and(_T_1696, asSInt(UInt<14>(0h2000))) node _T_1698 = asSInt(_T_1697) node _T_1699 = eq(_T_1698, asSInt(UInt<1>(0h0))) node _T_1700 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1701 = cvt(_T_1700) node _T_1702 = and(_T_1701, asSInt(UInt<13>(0h1000))) node _T_1703 = asSInt(_T_1702) node _T_1704 = eq(_T_1703, asSInt(UInt<1>(0h0))) node _T_1705 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1706 = cvt(_T_1705) node _T_1707 = and(_T_1706, asSInt(UInt<17>(0h10000))) node _T_1708 = asSInt(_T_1707) node _T_1709 = eq(_T_1708, asSInt(UInt<1>(0h0))) node _T_1710 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1711 = cvt(_T_1710) node _T_1712 = and(_T_1711, asSInt(UInt<18>(0h2f000))) node _T_1713 = asSInt(_T_1712) node _T_1714 = eq(_T_1713, asSInt(UInt<1>(0h0))) node _T_1715 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1716 = cvt(_T_1715) node _T_1717 = and(_T_1716, asSInt(UInt<17>(0h10000))) node _T_1718 = asSInt(_T_1717) node _T_1719 = eq(_T_1718, asSInt(UInt<1>(0h0))) node _T_1720 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1721 = cvt(_T_1720) node _T_1722 = and(_T_1721, asSInt(UInt<13>(0h1000))) node _T_1723 = asSInt(_T_1722) node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0))) node _T_1725 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1726 = cvt(_T_1725) node _T_1727 = and(_T_1726, asSInt(UInt<17>(0h10000))) node _T_1728 = asSInt(_T_1727) node _T_1729 = eq(_T_1728, asSInt(UInt<1>(0h0))) node _T_1730 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1731 = cvt(_T_1730) node _T_1732 = and(_T_1731, asSInt(UInt<27>(0h4000000))) node _T_1733 = asSInt(_T_1732) node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0))) node _T_1735 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1736 = cvt(_T_1735) node _T_1737 = and(_T_1736, asSInt(UInt<13>(0h1000))) node _T_1738 = asSInt(_T_1737) node _T_1739 = eq(_T_1738, asSInt(UInt<1>(0h0))) node _T_1740 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1741 = cvt(_T_1740) node _T_1742 = and(_T_1741, asSInt(UInt<29>(0h10000000))) node _T_1743 = asSInt(_T_1742) node _T_1744 = eq(_T_1743, asSInt(UInt<1>(0h0))) node _T_1745 = or(_T_1699, _T_1704) node _T_1746 = or(_T_1745, _T_1709) node _T_1747 = or(_T_1746, _T_1714) node _T_1748 = or(_T_1747, _T_1719) node _T_1749 = or(_T_1748, _T_1724) node _T_1750 = or(_T_1749, _T_1729) node _T_1751 = or(_T_1750, _T_1734) node _T_1752 = or(_T_1751, _T_1739) node _T_1753 = or(_T_1752, _T_1744) node _T_1754 = and(_T_1694, _T_1753) node _T_1755 = or(UInt<1>(0h0), _T_1754) node _T_1756 = and(UInt<1>(0h0), _T_1755) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_118 node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(address_ok, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(legal_source, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1769 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_122 node _T_1773 = eq(io.in.b.bits.mask, mask_1) node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(_T_1773, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1773, UInt<1>(0h1), "") : assert_123 node _T_1777 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1777 : node _T_1778 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1779 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1780 = and(_T_1778, _T_1779) node _T_1781 = or(UInt<1>(0h0), _T_1780) node _T_1782 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1783 = cvt(_T_1782) node _T_1784 = and(_T_1783, asSInt(UInt<14>(0h2000))) node _T_1785 = asSInt(_T_1784) node _T_1786 = eq(_T_1785, asSInt(UInt<1>(0h0))) node _T_1787 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1788 = cvt(_T_1787) node _T_1789 = and(_T_1788, asSInt(UInt<13>(0h1000))) node _T_1790 = asSInt(_T_1789) node _T_1791 = eq(_T_1790, asSInt(UInt<1>(0h0))) node _T_1792 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1793 = cvt(_T_1792) node _T_1794 = and(_T_1793, asSInt(UInt<17>(0h10000))) node _T_1795 = asSInt(_T_1794) node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1798 = cvt(_T_1797) node _T_1799 = and(_T_1798, asSInt(UInt<18>(0h2f000))) node _T_1800 = asSInt(_T_1799) node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) node _T_1802 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<17>(0h10000))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1808 = cvt(_T_1807) node _T_1809 = and(_T_1808, asSInt(UInt<13>(0h1000))) node _T_1810 = asSInt(_T_1809) node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) node _T_1812 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<27>(0h4000000))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1823 = cvt(_T_1822) node _T_1824 = and(_T_1823, asSInt(UInt<13>(0h1000))) node _T_1825 = asSInt(_T_1824) node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) node _T_1827 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1828 = cvt(_T_1827) node _T_1829 = and(_T_1828, asSInt(UInt<29>(0h10000000))) node _T_1830 = asSInt(_T_1829) node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) node _T_1832 = or(_T_1786, _T_1791) node _T_1833 = or(_T_1832, _T_1796) node _T_1834 = or(_T_1833, _T_1801) node _T_1835 = or(_T_1834, _T_1806) node _T_1836 = or(_T_1835, _T_1811) node _T_1837 = or(_T_1836, _T_1816) node _T_1838 = or(_T_1837, _T_1821) node _T_1839 = or(_T_1838, _T_1826) node _T_1840 = or(_T_1839, _T_1831) node _T_1841 = and(_T_1781, _T_1840) node _T_1842 = or(UInt<1>(0h0), _T_1841) node _T_1843 = and(UInt<1>(0h0), _T_1842) node _T_1844 = asUInt(reset) node _T_1845 = eq(_T_1844, UInt<1>(0h0)) when _T_1845 : node _T_1846 = eq(_T_1843, UInt<1>(0h0)) when _T_1846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1843, UInt<1>(0h1), "") : assert_124 node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(address_ok, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1850 = asUInt(reset) node _T_1851 = eq(_T_1850, UInt<1>(0h0)) when _T_1851 : node _T_1852 = eq(legal_source, UInt<1>(0h0)) when _T_1852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1853 = asUInt(reset) node _T_1854 = eq(_T_1853, UInt<1>(0h0)) when _T_1854 : node _T_1855 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1856 = eq(io.in.b.bits.mask, mask_1) node _T_1857 = asUInt(reset) node _T_1858 = eq(_T_1857, UInt<1>(0h0)) when _T_1858 : node _T_1859 = eq(_T_1856, UInt<1>(0h0)) when _T_1859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1856, UInt<1>(0h1), "") : assert_128 node _T_1860 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1861 = asUInt(reset) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : node _T_1863 = eq(_T_1860, UInt<1>(0h0)) when _T_1863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1860, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1864 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(_T_1864, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1864, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<1>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 0, 0) node _source_ok_T_18 = shr(io.in.c.bits.source, 1) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_2, UInt<1>(0h1)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_T_24 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<3>(0h4)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_23 connect _source_ok_WIRE_2[1], _source_ok_T_24 connect _source_ok_WIRE_2[2], _source_ok_T_25 node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<1>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 0, 0) node _T_1868 = shr(io.in.c.bits.source, 1) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) node _T_1870 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1871 = and(_T_1869, _T_1870) node _T_1872 = leq(uncommonBits_13, UInt<1>(0h1)) node _T_1873 = and(_T_1871, _T_1872) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) node _T_1875 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1876 = cvt(_T_1875) node _T_1877 = and(_T_1876, asSInt(UInt<1>(0h0))) node _T_1878 = asSInt(_T_1877) node _T_1879 = eq(_T_1878, asSInt(UInt<1>(0h0))) node _T_1880 = or(_T_1874, _T_1879) node _T_1881 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1882 = eq(_T_1881, UInt<1>(0h0)) node _T_1883 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1884 = cvt(_T_1883) node _T_1885 = and(_T_1884, asSInt(UInt<1>(0h0))) node _T_1886 = asSInt(_T_1885) node _T_1887 = eq(_T_1886, asSInt(UInt<1>(0h0))) node _T_1888 = or(_T_1882, _T_1887) node _T_1889 = eq(io.in.c.bits.source, UInt<3>(0h4)) node _T_1890 = eq(_T_1889, UInt<1>(0h0)) node _T_1891 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1892 = cvt(_T_1891) node _T_1893 = and(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = asSInt(_T_1893) node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = or(_T_1890, _T_1895) node _T_1897 = and(_T_1880, _T_1888) node _T_1898 = and(_T_1897, _T_1896) node _T_1899 = asUInt(reset) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) when _T_1900 : node _T_1901 = eq(_T_1898, UInt<1>(0h0)) when _T_1901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1898, UInt<1>(0h1), "") : assert_131 node _T_1902 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1902 : node _T_1903 = asUInt(reset) node _T_1904 = eq(_T_1903, UInt<1>(0h0)) when _T_1904 : node _T_1905 = eq(address_ok_1, UInt<1>(0h0)) when _T_1905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1906 = asUInt(reset) node _T_1907 = eq(_T_1906, UInt<1>(0h0)) when _T_1907 : node _T_1908 = eq(source_ok_2, UInt<1>(0h0)) when _T_1908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1909 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1910 = asUInt(reset) node _T_1911 = eq(_T_1910, UInt<1>(0h0)) when _T_1911 : node _T_1912 = eq(_T_1909, UInt<1>(0h0)) when _T_1912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1909, UInt<1>(0h1), "") : assert_134 node _T_1913 = asUInt(reset) node _T_1914 = eq(_T_1913, UInt<1>(0h0)) when _T_1914 : node _T_1915 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1916 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1917 = asUInt(reset) node _T_1918 = eq(_T_1917, UInt<1>(0h0)) when _T_1918 : node _T_1919 = eq(_T_1916, UInt<1>(0h0)) when _T_1919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1916, UInt<1>(0h1), "") : assert_136 node _T_1920 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1921 = asUInt(reset) node _T_1922 = eq(_T_1921, UInt<1>(0h0)) when _T_1922 : node _T_1923 = eq(_T_1920, UInt<1>(0h0)) when _T_1923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1920, UInt<1>(0h1), "") : assert_137 node _T_1924 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1924 : node _T_1925 = asUInt(reset) node _T_1926 = eq(_T_1925, UInt<1>(0h0)) when _T_1926 : node _T_1927 = eq(address_ok_1, UInt<1>(0h0)) when _T_1927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1928 = asUInt(reset) node _T_1929 = eq(_T_1928, UInt<1>(0h0)) when _T_1929 : node _T_1930 = eq(source_ok_2, UInt<1>(0h0)) when _T_1930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1931 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1932 = asUInt(reset) node _T_1933 = eq(_T_1932, UInt<1>(0h0)) when _T_1933 : node _T_1934 = eq(_T_1931, UInt<1>(0h0)) when _T_1934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1931, UInt<1>(0h1), "") : assert_140 node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1938 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1939 = asUInt(reset) node _T_1940 = eq(_T_1939, UInt<1>(0h0)) when _T_1940 : node _T_1941 = eq(_T_1938, UInt<1>(0h0)) when _T_1941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1938, UInt<1>(0h1), "") : assert_142 node _T_1942 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1942 : node _T_1943 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1944 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1945 = and(_T_1943, _T_1944) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<1>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 0, 0) node _T_1946 = shr(io.in.c.bits.source, 1) node _T_1947 = eq(_T_1946, UInt<1>(0h0)) node _T_1948 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1949 = and(_T_1947, _T_1948) node _T_1950 = leq(uncommonBits_14, UInt<1>(0h1)) node _T_1951 = and(_T_1949, _T_1950) node _T_1952 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1953 = eq(io.in.c.bits.source, UInt<3>(0h4)) node _T_1954 = or(_T_1951, _T_1952) node _T_1955 = or(_T_1954, _T_1953) node _T_1956 = and(_T_1945, _T_1955) node _T_1957 = or(UInt<1>(0h0), _T_1956) node _T_1958 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1959 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1960 = cvt(_T_1959) node _T_1961 = and(_T_1960, asSInt(UInt<14>(0h2000))) node _T_1962 = asSInt(_T_1961) node _T_1963 = eq(_T_1962, asSInt(UInt<1>(0h0))) node _T_1964 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1965 = cvt(_T_1964) node _T_1966 = and(_T_1965, asSInt(UInt<13>(0h1000))) node _T_1967 = asSInt(_T_1966) node _T_1968 = eq(_T_1967, asSInt(UInt<1>(0h0))) node _T_1969 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1970 = cvt(_T_1969) node _T_1971 = and(_T_1970, asSInt(UInt<17>(0h10000))) node _T_1972 = asSInt(_T_1971) node _T_1973 = eq(_T_1972, asSInt(UInt<1>(0h0))) node _T_1974 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1975 = cvt(_T_1974) node _T_1976 = and(_T_1975, asSInt(UInt<18>(0h2f000))) node _T_1977 = asSInt(_T_1976) node _T_1978 = eq(_T_1977, asSInt(UInt<1>(0h0))) node _T_1979 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1980 = cvt(_T_1979) node _T_1981 = and(_T_1980, asSInt(UInt<17>(0h10000))) node _T_1982 = asSInt(_T_1981) node _T_1983 = eq(_T_1982, asSInt(UInt<1>(0h0))) node _T_1984 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1985 = cvt(_T_1984) node _T_1986 = and(_T_1985, asSInt(UInt<13>(0h1000))) node _T_1987 = asSInt(_T_1986) node _T_1988 = eq(_T_1987, asSInt(UInt<1>(0h0))) node _T_1989 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1990 = cvt(_T_1989) node _T_1991 = and(_T_1990, asSInt(UInt<27>(0h4000000))) node _T_1992 = asSInt(_T_1991) node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) node _T_1994 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1995 = cvt(_T_1994) node _T_1996 = and(_T_1995, asSInt(UInt<13>(0h1000))) node _T_1997 = asSInt(_T_1996) node _T_1998 = eq(_T_1997, asSInt(UInt<1>(0h0))) node _T_1999 = or(_T_1963, _T_1968) node _T_2000 = or(_T_1999, _T_1973) node _T_2001 = or(_T_2000, _T_1978) node _T_2002 = or(_T_2001, _T_1983) node _T_2003 = or(_T_2002, _T_1988) node _T_2004 = or(_T_2003, _T_1993) node _T_2005 = or(_T_2004, _T_1998) node _T_2006 = and(_T_1958, _T_2005) node _T_2007 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2008 = or(UInt<1>(0h0), _T_2007) node _T_2009 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2010 = cvt(_T_2009) node _T_2011 = and(_T_2010, asSInt(UInt<17>(0h10000))) node _T_2012 = asSInt(_T_2011) node _T_2013 = eq(_T_2012, asSInt(UInt<1>(0h0))) node _T_2014 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2015 = cvt(_T_2014) node _T_2016 = and(_T_2015, asSInt(UInt<29>(0h10000000))) node _T_2017 = asSInt(_T_2016) node _T_2018 = eq(_T_2017, asSInt(UInt<1>(0h0))) node _T_2019 = or(_T_2013, _T_2018) node _T_2020 = and(_T_2008, _T_2019) node _T_2021 = or(UInt<1>(0h0), _T_2006) node _T_2022 = or(_T_2021, _T_2020) node _T_2023 = and(_T_1957, _T_2022) node _T_2024 = asUInt(reset) node _T_2025 = eq(_T_2024, UInt<1>(0h0)) when _T_2025 : node _T_2026 = eq(_T_2023, UInt<1>(0h0)) when _T_2026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2023, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<1>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 0, 0) node _T_2027 = shr(io.in.c.bits.source, 1) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) node _T_2029 = leq(UInt<1>(0h0), uncommonBits_15) node _T_2030 = and(_T_2028, _T_2029) node _T_2031 = leq(uncommonBits_15, UInt<1>(0h1)) node _T_2032 = and(_T_2030, _T_2031) node _T_2033 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_2034 = eq(io.in.c.bits.source, UInt<3>(0h4)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_2032 connect _WIRE_6[1], _T_2033 connect _WIRE_6[2], _T_2034 node _T_2035 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2036 = mux(_WIRE_6[0], _T_2035, UInt<1>(0h0)) node _T_2037 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2038 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2039 = or(_T_2036, _T_2037) node _T_2040 = or(_T_2039, _T_2038) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2040 node _T_2041 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2042 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2043 = and(_T_2041, _T_2042) node _T_2044 = or(UInt<1>(0h0), _T_2043) node _T_2045 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2046 = cvt(_T_2045) node _T_2047 = and(_T_2046, asSInt(UInt<14>(0h2000))) node _T_2048 = asSInt(_T_2047) node _T_2049 = eq(_T_2048, asSInt(UInt<1>(0h0))) node _T_2050 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2051 = cvt(_T_2050) node _T_2052 = and(_T_2051, asSInt(UInt<13>(0h1000))) node _T_2053 = asSInt(_T_2052) node _T_2054 = eq(_T_2053, asSInt(UInt<1>(0h0))) node _T_2055 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2056 = cvt(_T_2055) node _T_2057 = and(_T_2056, asSInt(UInt<17>(0h10000))) node _T_2058 = asSInt(_T_2057) node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0))) node _T_2060 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<18>(0h2f000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<17>(0h10000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<13>(0h1000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<17>(0h10000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<27>(0h4000000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<29>(0h10000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = or(_T_2049, _T_2054) node _T_2096 = or(_T_2095, _T_2059) node _T_2097 = or(_T_2096, _T_2064) node _T_2098 = or(_T_2097, _T_2069) node _T_2099 = or(_T_2098, _T_2074) node _T_2100 = or(_T_2099, _T_2079) node _T_2101 = or(_T_2100, _T_2084) node _T_2102 = or(_T_2101, _T_2089) node _T_2103 = or(_T_2102, _T_2094) node _T_2104 = and(_T_2044, _T_2103) node _T_2105 = or(UInt<1>(0h0), _T_2104) node _T_2106 = and(_WIRE_7, _T_2105) node _T_2107 = asUInt(reset) node _T_2108 = eq(_T_2107, UInt<1>(0h0)) when _T_2108 : node _T_2109 = eq(_T_2106, UInt<1>(0h0)) when _T_2109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2106, UInt<1>(0h1), "") : assert_144 node _T_2110 = asUInt(reset) node _T_2111 = eq(_T_2110, UInt<1>(0h0)) when _T_2111 : node _T_2112 = eq(source_ok_2, UInt<1>(0h0)) when _T_2112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2113 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2114 = asUInt(reset) node _T_2115 = eq(_T_2114, UInt<1>(0h0)) when _T_2115 : node _T_2116 = eq(_T_2113, UInt<1>(0h0)) when _T_2116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2113, UInt<1>(0h1), "") : assert_146 node _T_2117 = asUInt(reset) node _T_2118 = eq(_T_2117, UInt<1>(0h0)) when _T_2118 : node _T_2119 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2120 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2121 = asUInt(reset) node _T_2122 = eq(_T_2121, UInt<1>(0h0)) when _T_2122 : node _T_2123 = eq(_T_2120, UInt<1>(0h0)) when _T_2123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2120, UInt<1>(0h1), "") : assert_148 node _T_2124 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2125 = asUInt(reset) node _T_2126 = eq(_T_2125, UInt<1>(0h0)) when _T_2126 : node _T_2127 = eq(_T_2124, UInt<1>(0h0)) when _T_2127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2124, UInt<1>(0h1), "") : assert_149 node _T_2128 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2128 : node _T_2129 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2130 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2131 = and(_T_2129, _T_2130) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<1>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 0, 0) node _T_2132 = shr(io.in.c.bits.source, 1) node _T_2133 = eq(_T_2132, UInt<1>(0h0)) node _T_2134 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2135 = and(_T_2133, _T_2134) node _T_2136 = leq(uncommonBits_16, UInt<1>(0h1)) node _T_2137 = and(_T_2135, _T_2136) node _T_2138 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_2139 = eq(io.in.c.bits.source, UInt<3>(0h4)) node _T_2140 = or(_T_2137, _T_2138) node _T_2141 = or(_T_2140, _T_2139) node _T_2142 = and(_T_2131, _T_2141) node _T_2143 = or(UInt<1>(0h0), _T_2142) node _T_2144 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2145 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2146 = cvt(_T_2145) node _T_2147 = and(_T_2146, asSInt(UInt<14>(0h2000))) node _T_2148 = asSInt(_T_2147) node _T_2149 = eq(_T_2148, asSInt(UInt<1>(0h0))) node _T_2150 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2151 = cvt(_T_2150) node _T_2152 = and(_T_2151, asSInt(UInt<13>(0h1000))) node _T_2153 = asSInt(_T_2152) node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0))) node _T_2155 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2156 = cvt(_T_2155) node _T_2157 = and(_T_2156, asSInt(UInt<17>(0h10000))) node _T_2158 = asSInt(_T_2157) node _T_2159 = eq(_T_2158, asSInt(UInt<1>(0h0))) node _T_2160 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2161 = cvt(_T_2160) node _T_2162 = and(_T_2161, asSInt(UInt<18>(0h2f000))) node _T_2163 = asSInt(_T_2162) node _T_2164 = eq(_T_2163, asSInt(UInt<1>(0h0))) node _T_2165 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2166 = cvt(_T_2165) node _T_2167 = and(_T_2166, asSInt(UInt<17>(0h10000))) node _T_2168 = asSInt(_T_2167) node _T_2169 = eq(_T_2168, asSInt(UInt<1>(0h0))) node _T_2170 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2171 = cvt(_T_2170) node _T_2172 = and(_T_2171, asSInt(UInt<13>(0h1000))) node _T_2173 = asSInt(_T_2172) node _T_2174 = eq(_T_2173, asSInt(UInt<1>(0h0))) node _T_2175 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2176 = cvt(_T_2175) node _T_2177 = and(_T_2176, asSInt(UInt<27>(0h4000000))) node _T_2178 = asSInt(_T_2177) node _T_2179 = eq(_T_2178, asSInt(UInt<1>(0h0))) node _T_2180 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2181 = cvt(_T_2180) node _T_2182 = and(_T_2181, asSInt(UInt<13>(0h1000))) node _T_2183 = asSInt(_T_2182) node _T_2184 = eq(_T_2183, asSInt(UInt<1>(0h0))) node _T_2185 = or(_T_2149, _T_2154) node _T_2186 = or(_T_2185, _T_2159) node _T_2187 = or(_T_2186, _T_2164) node _T_2188 = or(_T_2187, _T_2169) node _T_2189 = or(_T_2188, _T_2174) node _T_2190 = or(_T_2189, _T_2179) node _T_2191 = or(_T_2190, _T_2184) node _T_2192 = and(_T_2144, _T_2191) node _T_2193 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2194 = or(UInt<1>(0h0), _T_2193) node _T_2195 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2196 = cvt(_T_2195) node _T_2197 = and(_T_2196, asSInt(UInt<17>(0h10000))) node _T_2198 = asSInt(_T_2197) node _T_2199 = eq(_T_2198, asSInt(UInt<1>(0h0))) node _T_2200 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2201 = cvt(_T_2200) node _T_2202 = and(_T_2201, asSInt(UInt<29>(0h10000000))) node _T_2203 = asSInt(_T_2202) node _T_2204 = eq(_T_2203, asSInt(UInt<1>(0h0))) node _T_2205 = or(_T_2199, _T_2204) node _T_2206 = and(_T_2194, _T_2205) node _T_2207 = or(UInt<1>(0h0), _T_2192) node _T_2208 = or(_T_2207, _T_2206) node _T_2209 = and(_T_2143, _T_2208) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<1>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 0, 0) node _T_2213 = shr(io.in.c.bits.source, 1) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) node _T_2215 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2216 = and(_T_2214, _T_2215) node _T_2217 = leq(uncommonBits_17, UInt<1>(0h1)) node _T_2218 = and(_T_2216, _T_2217) node _T_2219 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_2220 = eq(io.in.c.bits.source, UInt<3>(0h4)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2218 connect _WIRE_8[1], _T_2219 connect _WIRE_8[2], _T_2220 node _T_2221 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2222 = mux(_WIRE_8[0], _T_2221, UInt<1>(0h0)) node _T_2223 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2224 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2225 = or(_T_2222, _T_2223) node _T_2226 = or(_T_2225, _T_2224) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2226 node _T_2227 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2228 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2229 = and(_T_2227, _T_2228) node _T_2230 = or(UInt<1>(0h0), _T_2229) node _T_2231 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2232 = cvt(_T_2231) node _T_2233 = and(_T_2232, asSInt(UInt<14>(0h2000))) node _T_2234 = asSInt(_T_2233) node _T_2235 = eq(_T_2234, asSInt(UInt<1>(0h0))) node _T_2236 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2237 = cvt(_T_2236) node _T_2238 = and(_T_2237, asSInt(UInt<13>(0h1000))) node _T_2239 = asSInt(_T_2238) node _T_2240 = eq(_T_2239, asSInt(UInt<1>(0h0))) node _T_2241 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2242 = cvt(_T_2241) node _T_2243 = and(_T_2242, asSInt(UInt<17>(0h10000))) node _T_2244 = asSInt(_T_2243) node _T_2245 = eq(_T_2244, asSInt(UInt<1>(0h0))) node _T_2246 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2247 = cvt(_T_2246) node _T_2248 = and(_T_2247, asSInt(UInt<18>(0h2f000))) node _T_2249 = asSInt(_T_2248) node _T_2250 = eq(_T_2249, asSInt(UInt<1>(0h0))) node _T_2251 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2252 = cvt(_T_2251) node _T_2253 = and(_T_2252, asSInt(UInt<17>(0h10000))) node _T_2254 = asSInt(_T_2253) node _T_2255 = eq(_T_2254, asSInt(UInt<1>(0h0))) node _T_2256 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2257 = cvt(_T_2256) node _T_2258 = and(_T_2257, asSInt(UInt<13>(0h1000))) node _T_2259 = asSInt(_T_2258) node _T_2260 = eq(_T_2259, asSInt(UInt<1>(0h0))) node _T_2261 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2262 = cvt(_T_2261) node _T_2263 = and(_T_2262, asSInt(UInt<17>(0h10000))) node _T_2264 = asSInt(_T_2263) node _T_2265 = eq(_T_2264, asSInt(UInt<1>(0h0))) node _T_2266 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2267 = cvt(_T_2266) node _T_2268 = and(_T_2267, asSInt(UInt<27>(0h4000000))) node _T_2269 = asSInt(_T_2268) node _T_2270 = eq(_T_2269, asSInt(UInt<1>(0h0))) node _T_2271 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2272 = cvt(_T_2271) node _T_2273 = and(_T_2272, asSInt(UInt<13>(0h1000))) node _T_2274 = asSInt(_T_2273) node _T_2275 = eq(_T_2274, asSInt(UInt<1>(0h0))) node _T_2276 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2277 = cvt(_T_2276) node _T_2278 = and(_T_2277, asSInt(UInt<29>(0h10000000))) node _T_2279 = asSInt(_T_2278) node _T_2280 = eq(_T_2279, asSInt(UInt<1>(0h0))) node _T_2281 = or(_T_2235, _T_2240) node _T_2282 = or(_T_2281, _T_2245) node _T_2283 = or(_T_2282, _T_2250) node _T_2284 = or(_T_2283, _T_2255) node _T_2285 = or(_T_2284, _T_2260) node _T_2286 = or(_T_2285, _T_2265) node _T_2287 = or(_T_2286, _T_2270) node _T_2288 = or(_T_2287, _T_2275) node _T_2289 = or(_T_2288, _T_2280) node _T_2290 = and(_T_2230, _T_2289) node _T_2291 = or(UInt<1>(0h0), _T_2290) node _T_2292 = and(_WIRE_9, _T_2291) node _T_2293 = asUInt(reset) node _T_2294 = eq(_T_2293, UInt<1>(0h0)) when _T_2294 : node _T_2295 = eq(_T_2292, UInt<1>(0h0)) when _T_2295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2292, UInt<1>(0h1), "") : assert_151 node _T_2296 = asUInt(reset) node _T_2297 = eq(_T_2296, UInt<1>(0h0)) when _T_2297 : node _T_2298 = eq(source_ok_2, UInt<1>(0h0)) when _T_2298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2299 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : node _T_2302 = eq(_T_2299, UInt<1>(0h0)) when _T_2302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2299, UInt<1>(0h1), "") : assert_153 node _T_2303 = asUInt(reset) node _T_2304 = eq(_T_2303, UInt<1>(0h0)) when _T_2304 : node _T_2305 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2306 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2307 = asUInt(reset) node _T_2308 = eq(_T_2307, UInt<1>(0h0)) when _T_2308 : node _T_2309 = eq(_T_2306, UInt<1>(0h0)) when _T_2309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2306, UInt<1>(0h1), "") : assert_155 node _T_2310 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2310 : node _T_2311 = asUInt(reset) node _T_2312 = eq(_T_2311, UInt<1>(0h0)) when _T_2312 : node _T_2313 = eq(address_ok_1, UInt<1>(0h0)) when _T_2313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2314 = asUInt(reset) node _T_2315 = eq(_T_2314, UInt<1>(0h0)) when _T_2315 : node _T_2316 = eq(source_ok_2, UInt<1>(0h0)) when _T_2316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2317 = asUInt(reset) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) when _T_2318 : node _T_2319 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2320 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2321 = asUInt(reset) node _T_2322 = eq(_T_2321, UInt<1>(0h0)) when _T_2322 : node _T_2323 = eq(_T_2320, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2320, UInt<1>(0h1), "") : assert_159 node _T_2324 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2325 = asUInt(reset) node _T_2326 = eq(_T_2325, UInt<1>(0h0)) when _T_2326 : node _T_2327 = eq(_T_2324, UInt<1>(0h0)) when _T_2327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2324, UInt<1>(0h1), "") : assert_160 node _T_2328 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2328 : node _T_2329 = asUInt(reset) node _T_2330 = eq(_T_2329, UInt<1>(0h0)) when _T_2330 : node _T_2331 = eq(address_ok_1, UInt<1>(0h0)) when _T_2331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(source_ok_2, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2335 = asUInt(reset) node _T_2336 = eq(_T_2335, UInt<1>(0h0)) when _T_2336 : node _T_2337 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2338 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2339 = asUInt(reset) node _T_2340 = eq(_T_2339, UInt<1>(0h0)) when _T_2340 : node _T_2341 = eq(_T_2338, UInt<1>(0h0)) when _T_2341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2338, UInt<1>(0h1), "") : assert_164 node _T_2342 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2342 : node _T_2343 = asUInt(reset) node _T_2344 = eq(_T_2343, UInt<1>(0h0)) when _T_2344 : node _T_2345 = eq(address_ok_1, UInt<1>(0h0)) when _T_2345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2346 = asUInt(reset) node _T_2347 = eq(_T_2346, UInt<1>(0h0)) when _T_2347 : node _T_2348 = eq(source_ok_2, UInt<1>(0h0)) when _T_2348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2349 = asUInt(reset) node _T_2350 = eq(_T_2349, UInt<1>(0h0)) when _T_2350 : node _T_2351 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2352 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2353 = asUInt(reset) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) when _T_2354 : node _T_2355 = eq(_T_2352, UInt<1>(0h0)) when _T_2355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2352, UInt<1>(0h1), "") : assert_168 node _T_2356 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2357 = asUInt(reset) node _T_2358 = eq(_T_2357, UInt<1>(0h0)) when _T_2358 : node _T_2359 = eq(_T_2356, UInt<1>(0h0)) when _T_2359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2356, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2363 = eq(a_first, UInt<1>(0h0)) node _T_2364 = and(io.in.a.valid, _T_2363) when _T_2364 : node _T_2365 = eq(io.in.a.bits.opcode, opcode) node _T_2366 = asUInt(reset) node _T_2367 = eq(_T_2366, UInt<1>(0h0)) when _T_2367 : node _T_2368 = eq(_T_2365, UInt<1>(0h0)) when _T_2368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2365, UInt<1>(0h1), "") : assert_171 node _T_2369 = eq(io.in.a.bits.param, param) node _T_2370 = asUInt(reset) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) when _T_2371 : node _T_2372 = eq(_T_2369, UInt<1>(0h0)) when _T_2372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2369, UInt<1>(0h1), "") : assert_172 node _T_2373 = eq(io.in.a.bits.size, size) node _T_2374 = asUInt(reset) node _T_2375 = eq(_T_2374, UInt<1>(0h0)) when _T_2375 : node _T_2376 = eq(_T_2373, UInt<1>(0h0)) when _T_2376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2373, UInt<1>(0h1), "") : assert_173 node _T_2377 = eq(io.in.a.bits.source, source) node _T_2378 = asUInt(reset) node _T_2379 = eq(_T_2378, UInt<1>(0h0)) when _T_2379 : node _T_2380 = eq(_T_2377, UInt<1>(0h0)) when _T_2380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2377, UInt<1>(0h1), "") : assert_174 node _T_2381 = eq(io.in.a.bits.address, address) node _T_2382 = asUInt(reset) node _T_2383 = eq(_T_2382, UInt<1>(0h0)) when _T_2383 : node _T_2384 = eq(_T_2381, UInt<1>(0h0)) when _T_2384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2381, UInt<1>(0h1), "") : assert_175 node _T_2385 = and(io.in.a.ready, io.in.a.valid) node _T_2386 = and(_T_2385, a_first) when _T_2386 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2387 = eq(d_first, UInt<1>(0h0)) node _T_2388 = and(io.in.d.valid, _T_2387) when _T_2388 : node _T_2389 = eq(io.in.d.bits.opcode, opcode_1) node _T_2390 = asUInt(reset) node _T_2391 = eq(_T_2390, UInt<1>(0h0)) when _T_2391 : node _T_2392 = eq(_T_2389, UInt<1>(0h0)) when _T_2392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2389, UInt<1>(0h1), "") : assert_176 node _T_2393 = eq(io.in.d.bits.param, param_1) node _T_2394 = asUInt(reset) node _T_2395 = eq(_T_2394, UInt<1>(0h0)) when _T_2395 : node _T_2396 = eq(_T_2393, UInt<1>(0h0)) when _T_2396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2393, UInt<1>(0h1), "") : assert_177 node _T_2397 = eq(io.in.d.bits.size, size_1) node _T_2398 = asUInt(reset) node _T_2399 = eq(_T_2398, UInt<1>(0h0)) when _T_2399 : node _T_2400 = eq(_T_2397, UInt<1>(0h0)) when _T_2400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2397, UInt<1>(0h1), "") : assert_178 node _T_2401 = eq(io.in.d.bits.source, source_1) node _T_2402 = asUInt(reset) node _T_2403 = eq(_T_2402, UInt<1>(0h0)) when _T_2403 : node _T_2404 = eq(_T_2401, UInt<1>(0h0)) when _T_2404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2401, UInt<1>(0h1), "") : assert_179 node _T_2405 = eq(io.in.d.bits.sink, sink) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_180 node _T_2409 = eq(io.in.d.bits.denied, denied) node _T_2410 = asUInt(reset) node _T_2411 = eq(_T_2410, UInt<1>(0h0)) when _T_2411 : node _T_2412 = eq(_T_2409, UInt<1>(0h0)) when _T_2412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2409, UInt<1>(0h1), "") : assert_181 node _T_2413 = and(io.in.d.ready, io.in.d.valid) node _T_2414 = and(_T_2413, d_first) when _T_2414 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2415 = eq(b_first, UInt<1>(0h0)) node _T_2416 = and(io.in.b.valid, _T_2415) when _T_2416 : node _T_2417 = eq(io.in.b.bits.opcode, opcode_2) node _T_2418 = asUInt(reset) node _T_2419 = eq(_T_2418, UInt<1>(0h0)) when _T_2419 : node _T_2420 = eq(_T_2417, UInt<1>(0h0)) when _T_2420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2417, UInt<1>(0h1), "") : assert_182 node _T_2421 = eq(io.in.b.bits.param, param_2) node _T_2422 = asUInt(reset) node _T_2423 = eq(_T_2422, UInt<1>(0h0)) when _T_2423 : node _T_2424 = eq(_T_2421, UInt<1>(0h0)) when _T_2424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2421, UInt<1>(0h1), "") : assert_183 node _T_2425 = eq(io.in.b.bits.size, size_2) node _T_2426 = asUInt(reset) node _T_2427 = eq(_T_2426, UInt<1>(0h0)) when _T_2427 : node _T_2428 = eq(_T_2425, UInt<1>(0h0)) when _T_2428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2425, UInt<1>(0h1), "") : assert_184 node _T_2429 = eq(io.in.b.bits.source, source_2) node _T_2430 = asUInt(reset) node _T_2431 = eq(_T_2430, UInt<1>(0h0)) when _T_2431 : node _T_2432 = eq(_T_2429, UInt<1>(0h0)) when _T_2432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2429, UInt<1>(0h1), "") : assert_185 node _T_2433 = eq(io.in.b.bits.address, address_1) node _T_2434 = asUInt(reset) node _T_2435 = eq(_T_2434, UInt<1>(0h0)) when _T_2435 : node _T_2436 = eq(_T_2433, UInt<1>(0h0)) when _T_2436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2433, UInt<1>(0h1), "") : assert_186 node _T_2437 = and(io.in.b.ready, io.in.b.valid) node _T_2438 = and(_T_2437, b_first) when _T_2438 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2439 = eq(c_first, UInt<1>(0h0)) node _T_2440 = and(io.in.c.valid, _T_2439) when _T_2440 : node _T_2441 = eq(io.in.c.bits.opcode, opcode_3) node _T_2442 = asUInt(reset) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) when _T_2443 : node _T_2444 = eq(_T_2441, UInt<1>(0h0)) when _T_2444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2441, UInt<1>(0h1), "") : assert_187 node _T_2445 = eq(io.in.c.bits.param, param_3) node _T_2446 = asUInt(reset) node _T_2447 = eq(_T_2446, UInt<1>(0h0)) when _T_2447 : node _T_2448 = eq(_T_2445, UInt<1>(0h0)) when _T_2448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2445, UInt<1>(0h1), "") : assert_188 node _T_2449 = eq(io.in.c.bits.size, size_3) node _T_2450 = asUInt(reset) node _T_2451 = eq(_T_2450, UInt<1>(0h0)) when _T_2451 : node _T_2452 = eq(_T_2449, UInt<1>(0h0)) when _T_2452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2449, UInt<1>(0h1), "") : assert_189 node _T_2453 = eq(io.in.c.bits.source, source_3) node _T_2454 = asUInt(reset) node _T_2455 = eq(_T_2454, UInt<1>(0h0)) when _T_2455 : node _T_2456 = eq(_T_2453, UInt<1>(0h0)) when _T_2456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2453, UInt<1>(0h1), "") : assert_190 node _T_2457 = eq(io.in.c.bits.address, address_2) node _T_2458 = asUInt(reset) node _T_2459 = eq(_T_2458, UInt<1>(0h0)) when _T_2459 : node _T_2460 = eq(_T_2457, UInt<1>(0h0)) when _T_2460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2457, UInt<1>(0h1), "") : assert_191 node _T_2461 = and(io.in.c.ready, io.in.c.valid) node _T_2462 = and(_T_2461, c_first) when _T_2462 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<5>, clock, reset, UInt<5>(0h0) regreset inflight_opcodes : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<5> connect a_set, UInt<5>(0h0) wire a_set_wo_ready : UInt<5> connect a_set_wo_ready, UInt<5>(0h0) wire a_opcodes_set : UInt<20> connect a_opcodes_set, UInt<20>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2463 = and(io.in.a.valid, a_first_1) node _T_2464 = and(_T_2463, UInt<1>(0h1)) when _T_2464 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2465 = and(io.in.a.ready, io.in.a.valid) node _T_2466 = and(_T_2465, a_first_1) node _T_2467 = and(_T_2466, UInt<1>(0h1)) when _T_2467 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2468 = dshr(inflight, io.in.a.bits.source) node _T_2469 = bits(_T_2468, 0, 0) node _T_2470 = eq(_T_2469, UInt<1>(0h0)) node _T_2471 = asUInt(reset) node _T_2472 = eq(_T_2471, UInt<1>(0h0)) when _T_2472 : node _T_2473 = eq(_T_2470, UInt<1>(0h0)) when _T_2473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2470, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<5> connect d_clr, UInt<5>(0h0) wire d_clr_wo_ready : UInt<5> connect d_clr_wo_ready, UInt<5>(0h0) wire d_opcodes_clr : UInt<20> connect d_opcodes_clr, UInt<20>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2474 = and(io.in.d.valid, d_first_1) node _T_2475 = and(_T_2474, UInt<1>(0h1)) node _T_2476 = eq(d_release_ack, UInt<1>(0h0)) node _T_2477 = and(_T_2475, _T_2476) when _T_2477 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2478 = and(io.in.d.ready, io.in.d.valid) node _T_2479 = and(_T_2478, d_first_1) node _T_2480 = and(_T_2479, UInt<1>(0h1)) node _T_2481 = eq(d_release_ack, UInt<1>(0h0)) node _T_2482 = and(_T_2480, _T_2481) when _T_2482 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2483 = and(io.in.d.valid, d_first_1) node _T_2484 = and(_T_2483, UInt<1>(0h1)) node _T_2485 = eq(d_release_ack, UInt<1>(0h0)) node _T_2486 = and(_T_2484, _T_2485) when _T_2486 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2487 = dshr(inflight, io.in.d.bits.source) node _T_2488 = bits(_T_2487, 0, 0) node _T_2489 = or(_T_2488, same_cycle_resp) node _T_2490 = asUInt(reset) node _T_2491 = eq(_T_2490, UInt<1>(0h0)) when _T_2491 : node _T_2492 = eq(_T_2489, UInt<1>(0h0)) when _T_2492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2489, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2493 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2494 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2495 = or(_T_2493, _T_2494) node _T_2496 = asUInt(reset) node _T_2497 = eq(_T_2496, UInt<1>(0h0)) when _T_2497 : node _T_2498 = eq(_T_2495, UInt<1>(0h0)) when _T_2498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2495, UInt<1>(0h1), "") : assert_194 node _T_2499 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2500 = asUInt(reset) node _T_2501 = eq(_T_2500, UInt<1>(0h0)) when _T_2501 : node _T_2502 = eq(_T_2499, UInt<1>(0h0)) when _T_2502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2499, UInt<1>(0h1), "") : assert_195 else : node _T_2503 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2504 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2505 = or(_T_2503, _T_2504) node _T_2506 = asUInt(reset) node _T_2507 = eq(_T_2506, UInt<1>(0h0)) when _T_2507 : node _T_2508 = eq(_T_2505, UInt<1>(0h0)) when _T_2508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2505, UInt<1>(0h1), "") : assert_196 node _T_2509 = eq(io.in.d.bits.size, a_size_lookup) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_197 node _T_2513 = and(io.in.d.valid, d_first_1) node _T_2514 = and(_T_2513, a_first_1) node _T_2515 = and(_T_2514, io.in.a.valid) node _T_2516 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2517 = and(_T_2515, _T_2516) node _T_2518 = eq(d_release_ack, UInt<1>(0h0)) node _T_2519 = and(_T_2517, _T_2518) when _T_2519 : node _T_2520 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2521 = or(_T_2520, io.in.a.ready) node _T_2522 = asUInt(reset) node _T_2523 = eq(_T_2522, UInt<1>(0h0)) when _T_2523 : node _T_2524 = eq(_T_2521, UInt<1>(0h0)) when _T_2524 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2521, UInt<1>(0h1), "") : assert_198 node _T_2525 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2526 = orr(a_set_wo_ready) node _T_2527 = eq(_T_2526, UInt<1>(0h0)) node _T_2528 = or(_T_2525, _T_2527) node _T_2529 = asUInt(reset) node _T_2530 = eq(_T_2529, UInt<1>(0h0)) when _T_2530 : node _T_2531 = eq(_T_2528, UInt<1>(0h0)) when _T_2531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2528, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_93 node _T_2532 = orr(inflight) node _T_2533 = eq(_T_2532, UInt<1>(0h0)) node _T_2534 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2535 = or(_T_2533, _T_2534) node _T_2536 = lt(watchdog, plusarg_reader.out) node _T_2537 = or(_T_2535, _T_2536) node _T_2538 = asUInt(reset) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) when _T_2539 : node _T_2540 = eq(_T_2537, UInt<1>(0h0)) when _T_2540 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2537, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2541 = and(io.in.a.ready, io.in.a.valid) node _T_2542 = and(io.in.d.ready, io.in.d.valid) node _T_2543 = or(_T_2541, _T_2542) when _T_2543 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<5>, clock, reset, UInt<5>(0h0) regreset inflight_opcodes_1 : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<5> connect c_set, UInt<5>(0h0) wire c_set_wo_ready : UInt<5> connect c_set_wo_ready, UInt<5>(0h0) wire c_opcodes_set : UInt<20> connect c_opcodes_set, UInt<20>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2544 = and(io.in.c.valid, c_first_1) node _T_2545 = bits(io.in.c.bits.opcode, 2, 2) node _T_2546 = bits(io.in.c.bits.opcode, 1, 1) node _T_2547 = and(_T_2545, _T_2546) node _T_2548 = and(_T_2544, _T_2547) when _T_2548 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2549 = and(io.in.c.ready, io.in.c.valid) node _T_2550 = and(_T_2549, c_first_1) node _T_2551 = bits(io.in.c.bits.opcode, 2, 2) node _T_2552 = bits(io.in.c.bits.opcode, 1, 1) node _T_2553 = and(_T_2551, _T_2552) node _T_2554 = and(_T_2550, _T_2553) when _T_2554 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2555 = dshr(inflight_1, io.in.c.bits.source) node _T_2556 = bits(_T_2555, 0, 0) node _T_2557 = eq(_T_2556, UInt<1>(0h0)) node _T_2558 = asUInt(reset) node _T_2559 = eq(_T_2558, UInt<1>(0h0)) when _T_2559 : node _T_2560 = eq(_T_2557, UInt<1>(0h0)) when _T_2560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2557, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<5> connect d_clr_1, UInt<5>(0h0) wire d_clr_wo_ready_1 : UInt<5> connect d_clr_wo_ready_1, UInt<5>(0h0) wire d_opcodes_clr_1 : UInt<20> connect d_opcodes_clr_1, UInt<20>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2561 = and(io.in.d.valid, d_first_2) node _T_2562 = and(_T_2561, UInt<1>(0h1)) node _T_2563 = and(_T_2562, d_release_ack_1) when _T_2563 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2564 = and(io.in.d.ready, io.in.d.valid) node _T_2565 = and(_T_2564, d_first_2) node _T_2566 = and(_T_2565, UInt<1>(0h1)) node _T_2567 = and(_T_2566, d_release_ack_1) when _T_2567 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2568 = and(io.in.d.valid, d_first_2) node _T_2569 = and(_T_2568, UInt<1>(0h1)) node _T_2570 = and(_T_2569, d_release_ack_1) when _T_2570 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2571 = dshr(inflight_1, io.in.d.bits.source) node _T_2572 = bits(_T_2571, 0, 0) node _T_2573 = or(_T_2572, same_cycle_resp_1) node _T_2574 = asUInt(reset) node _T_2575 = eq(_T_2574, UInt<1>(0h0)) when _T_2575 : node _T_2576 = eq(_T_2573, UInt<1>(0h0)) when _T_2576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2573, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2577 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2578 = asUInt(reset) node _T_2579 = eq(_T_2578, UInt<1>(0h0)) when _T_2579 : node _T_2580 = eq(_T_2577, UInt<1>(0h0)) when _T_2580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2577, UInt<1>(0h1), "") : assert_203 else : node _T_2581 = eq(io.in.d.bits.size, c_size_lookup) node _T_2582 = asUInt(reset) node _T_2583 = eq(_T_2582, UInt<1>(0h0)) when _T_2583 : node _T_2584 = eq(_T_2581, UInt<1>(0h0)) when _T_2584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2581, UInt<1>(0h1), "") : assert_204 node _T_2585 = and(io.in.d.valid, d_first_2) node _T_2586 = and(_T_2585, c_first_1) node _T_2587 = and(_T_2586, io.in.c.valid) node _T_2588 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2589 = and(_T_2587, _T_2588) node _T_2590 = and(_T_2589, d_release_ack_1) node _T_2591 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2592 = and(_T_2590, _T_2591) when _T_2592 : node _T_2593 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2594 = or(_T_2593, io.in.c.ready) node _T_2595 = asUInt(reset) node _T_2596 = eq(_T_2595, UInt<1>(0h0)) when _T_2596 : node _T_2597 = eq(_T_2594, UInt<1>(0h0)) when _T_2597 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2594, UInt<1>(0h1), "") : assert_205 node _T_2598 = orr(c_set_wo_ready) when _T_2598 : node _T_2599 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2600 = asUInt(reset) node _T_2601 = eq(_T_2600, UInt<1>(0h0)) when _T_2601 : node _T_2602 = eq(_T_2599, UInt<1>(0h0)) when _T_2602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2599, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_94 node _T_2603 = orr(inflight_1) node _T_2604 = eq(_T_2603, UInt<1>(0h0)) node _T_2605 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2606 = or(_T_2604, _T_2605) node _T_2607 = lt(watchdog_1, plusarg_reader_1.out) node _T_2608 = or(_T_2606, _T_2607) node _T_2609 = asUInt(reset) node _T_2610 = eq(_T_2609, UInt<1>(0h0)) when _T_2610 : node _T_2611 = eq(_T_2608, UInt<1>(0h0)) when _T_2611 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2608, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2612 = and(io.in.c.ready, io.in.c.valid) node _T_2613 = and(io.in.d.ready, io.in.d.valid) node _T_2614 = or(_T_2612, _T_2613) when _T_2614 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2615 = and(io.in.d.ready, io.in.d.valid) node _T_2616 = and(_T_2615, d_first_3) node _T_2617 = bits(io.in.d.bits.opcode, 2, 2) node _T_2618 = bits(io.in.d.bits.opcode, 1, 1) node _T_2619 = eq(_T_2618, UInt<1>(0h0)) node _T_2620 = and(_T_2617, _T_2619) node _T_2621 = and(_T_2616, _T_2620) when _T_2621 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2622 = dshr(inflight_2, io.in.d.bits.sink) node _T_2623 = bits(_T_2622, 0, 0) node _T_2624 = eq(_T_2623, UInt<1>(0h0)) node _T_2625 = asUInt(reset) node _T_2626 = eq(_T_2625, UInt<1>(0h0)) when _T_2626 : node _T_2627 = eq(_T_2624, UInt<1>(0h0)) when _T_2627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2624, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2628 = and(io.in.e.ready, io.in.e.valid) node _T_2629 = and(_T_2628, UInt<1>(0h1)) node _T_2630 = and(_T_2629, UInt<1>(0h1)) when _T_2630 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2631 = or(d_set, inflight_2) node _T_2632 = dshr(_T_2631, io.in.e.bits.sink) node _T_2633 = bits(_T_2632, 0, 0) node _T_2634 = asUInt(reset) node _T_2635 = eq(_T_2634, UInt<1>(0h0)) when _T_2635 : node _T_2636 = eq(_T_2633, UInt<1>(0h0)) when _T_2636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2633, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8
module TLMonitor_46( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_8 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_13 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [2:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [2:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [2:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [2:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire source_ok_uncommonBits = _source_ok_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T = io_in_a_bits_source_0[2:1]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 3'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = io_in_a_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31] wire _source_ok_T_8 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_8 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire uncommonBits = _uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_1 = _uncommonBits_T_1[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_2 = _uncommonBits_T_2[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_3 = _uncommonBits_T_3[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_4 = _uncommonBits_T_4[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_5 = _uncommonBits_T_5[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_6 = _uncommonBits_T_6[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_7 = _uncommonBits_T_7[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_8 = _uncommonBits_T_8[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_9 = _uncommonBits_T_9[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_10 = _uncommonBits_T_10[0]; // @[Parameters.scala:52:{29,56}] wire source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_9 = io_in_d_bits_source_0[2:1]; // @[Monitor.scala:36:7] wire _source_ok_T_10 = _source_ok_T_9 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_14 = _source_ok_T_12; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_0 = _source_ok_T_14; // @[Parameters.scala:1138:31] wire _source_ok_T_15 = io_in_d_bits_source_0 == 3'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_15; // @[Parameters.scala:1138:31] wire _source_ok_T_16 = io_in_d_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_16; // @[Parameters.scala:1138:31] wire _source_ok_T_17 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_17 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire uncommonBits_11 = _uncommonBits_T_11[0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _legal_source_T = io_in_b_bits_source_0[2:1]; // @[Monitor.scala:36:7] wire _legal_source_T_6 = io_in_b_bits_source_0 == 3'h2; // @[Monitor.scala:36:7] wire _legal_source_T_7 = io_in_b_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire legal_source_uncommonBits = _legal_source_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_1 = _legal_source_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_3 = _legal_source_T_1; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_5 = _legal_source_T_3; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_7; // @[Parameters.scala:1138:31] wire [1:0] _legal_source_T_9 = {_legal_source_WIRE_1, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_11 = _legal_source_T_9; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_10 = {_legal_source_WIRE_2, 2'h0}; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_12 = {1'h0, _legal_source_T_11} | _legal_source_T_10; // @[Mux.scala:30:73] wire [2:0] _legal_source_WIRE_1_0 = _legal_source_T_12; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire uncommonBits_12 = _uncommonBits_T_12[0]; // @[Parameters.scala:52:{29,56}] wire source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_18 = io_in_c_bits_source_0[2:1]; // @[Monitor.scala:36:7] wire _source_ok_T_19 = _source_ok_T_18 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_0 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = io_in_c_bits_source_0 == 3'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_c_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_26 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire uncommonBits_13 = _uncommonBits_T_13[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_14 = _uncommonBits_T_14[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_15 = _uncommonBits_T_15[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_16 = _uncommonBits_T_16[0]; // @[Parameters.scala:52:{29,56}] wire uncommonBits_17 = _uncommonBits_T_17[0]; // @[Parameters.scala:52:{29,56}] wire _T_2541 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2541; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2541; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [2:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2615 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2615; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2615; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2615; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2615; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [2:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2612 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2612; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2612; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [2:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [4:0] inflight; // @[Monitor.scala:614:27] reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [4:0] a_set; // @[Monitor.scala:626:34] wire [4:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [19:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [5:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [5:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [5:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [5:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [5:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [19:0] _a_opcode_lookup_T_6 = {16'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [19:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [5:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [5:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [5:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [5:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [5:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {32'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [7:0] _GEN_21 = 8'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [7:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2467 = _T_2541 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2467 ? _a_set_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2467 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2467 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [5:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [66:0] _a_opcodes_set_T_1 = {63'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2467 ? _a_opcodes_set_T_1[19:0] : 20'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [5:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [67:0] _a_sizes_set_T_1 = {63'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2467 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [4:0] d_clr; // @[Monitor.scala:664:34] wire [4:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [19:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2513 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [7:0] _GEN_23 = 8'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2513 & ~d_release_ack ? _d_clr_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2482 = _T_2615 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2482 ? _d_clr_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [78:0] _d_opcodes_clr_T_5 = 79'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2482 ? _d_opcodes_clr_T_5[19:0] : 20'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [78:0] _d_sizes_clr_T_5 = 79'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2482 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [4:0] inflight_1; // @[Monitor.scala:726:35] reg [19:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [4:0] c_set; // @[Monitor.scala:738:34] wire [4:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [19:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [19:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [19:0] _c_opcode_lookup_T_6 = {16'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [19:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[19:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {32'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [7:0] _GEN_24 = 8'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [7:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2554 = _T_2612 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2554 ? _c_set_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2554 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2554 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [5:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [66:0] _c_opcodes_set_T_1 = {63'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2554 ? _c_opcodes_set_T_1[19:0] : 20'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [5:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [67:0] _c_sizes_set_T_1 = {63'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2554 ? _c_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [4:0] d_clr_1; // @[Monitor.scala:774:34] wire [4:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [19:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2585 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2585 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2567 = _T_2615 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2567 ? _d_clr_T_1[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [78:0] _d_opcodes_clr_T_11 = 79'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2567 ? _d_opcodes_clr_T_11[19:0] : 20'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [78:0] _d_sizes_clr_T_11 = 79'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2567 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [4:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [4:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [19:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [19:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2621 = _T_2615 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2621 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2630 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2630 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module FPToInt : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock when io.in.valid : connect in, io.in.bits reg valid : UInt<1>, clock connect valid, io.in.valid inst dcmp of CompareRecFN_16 connect dcmp.io.a, in.in1 connect dcmp.io.b, in.in2 node _dcmp_io_signaling_T = bits(in.rm, 1, 1) node _dcmp_io_signaling_T_1 = eq(_dcmp_io_signaling_T, UInt<1>(0h0)) connect dcmp.io.signaling, _dcmp_io_signaling_T_1 node toint_ieee_unrecoded_rawIn_exp = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 9) node toint_ieee_unrecoded_rawIn_isZero = eq(_toint_ieee_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isNaN_T) connect toint_ieee_unrecoded_rawIn.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isInf_T_1) connect toint_ieee_unrecoded_rawIn.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_2 connect toint_ieee_unrecoded_rawIn.isZero, toint_ieee_unrecoded_rawIn_isZero node _toint_ieee_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn.sign, _toint_ieee_unrecoded_rawIn_out_sign_T node _toint_ieee_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_unrecoded_rawIn_exp) connect toint_ieee_unrecoded_rawIn.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T node _toint_ieee_unrecoded_rawIn_out_sig_T = eq(toint_ieee_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T) node _toint_ieee_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2) connect toint_ieee_unrecoded_rawIn.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_3 node toint_ieee_unrecoded_isSubnormal = lt(toint_ieee_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T = bits(toint_ieee_unrecoded_rawIn.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T) node toint_ieee_unrecoded_denormShiftDist = tail(_toint_ieee_unrecoded_denormShiftDist_T_1, 1) node _toint_ieee_unrecoded_denormFract_T = shr(toint_ieee_unrecoded_rawIn.sig, 1) node _toint_ieee_unrecoded_denormFract_T_1 = dshr(_toint_ieee_unrecoded_denormFract_T, toint_ieee_unrecoded_denormShiftDist) node toint_ieee_unrecoded_denormFract = bits(_toint_ieee_unrecoded_denormFract_T_1, 51, 0) node _toint_ieee_unrecoded_expOut_T = bits(toint_ieee_unrecoded_rawIn.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_1 = sub(_toint_ieee_unrecoded_expOut_T, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_2 = tail(_toint_ieee_unrecoded_expOut_T_1, 1) node _toint_ieee_unrecoded_expOut_T_3 = mux(toint_ieee_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_2) node _toint_ieee_unrecoded_expOut_T_4 = or(toint_ieee_unrecoded_rawIn.isNaN, toint_ieee_unrecoded_rawIn.isInf) node _toint_ieee_unrecoded_expOut_T_5 = mux(_toint_ieee_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut = or(_toint_ieee_unrecoded_expOut_T_3, _toint_ieee_unrecoded_expOut_T_5) node _toint_ieee_unrecoded_fractOut_T = bits(toint_ieee_unrecoded_rawIn.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_1 = mux(toint_ieee_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T) node toint_ieee_unrecoded_fractOut = mux(toint_ieee_unrecoded_isSubnormal, toint_ieee_unrecoded_denormFract, _toint_ieee_unrecoded_fractOut_T_1) node toint_ieee_unrecoded_hi = cat(toint_ieee_unrecoded_rawIn.sign, toint_ieee_unrecoded_expOut) node toint_ieee_unrecoded = cat(toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut) node _toint_ieee_prevRecoded_T = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_1 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_2 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi = cat(_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1) node toint_ieee_prevRecoded = cat(toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp = bits(toint_ieee_prevRecoded, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(toint_ieee_prevRecoded, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevRecoded, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist) node toint_ieee_prevUnrecoded_unrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_1, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T) node toint_ieee_prevUnrecoded_unrecoded_fractOut = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, toint_ieee_prevUnrecoded_unrecoded_denormFract, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1) node toint_ieee_prevUnrecoded_unrecoded_hi = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, toint_ieee_prevUnrecoded_unrecoded_expOut) node toint_ieee_prevUnrecoded_unrecoded = cat(toint_ieee_prevUnrecoded_unrecoded_hi, toint_ieee_prevUnrecoded_unrecoded_fractOut) node _toint_ieee_prevUnrecoded_prevRecoded_T = bits(toint_ieee_prevRecoded, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_1 = bits(toint_ieee_prevRecoded, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_2 = bits(toint_ieee_prevRecoded, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi = cat(_toint_ieee_prevUnrecoded_prevRecoded_T, _toint_ieee_prevUnrecoded_prevRecoded_T_1) node toint_ieee_prevUnrecoded_prevRecoded = cat(toint_ieee_prevUnrecoded_prevRecoded_hi, _toint_ieee_prevUnrecoded_prevRecoded_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(toint_ieee_prevUnrecoded_prevRecoded, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(toint_ieee_prevUnrecoded_prevRecoded, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1) node toint_ieee_prevUnrecoded_prevUnrecoded_hi = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut) node toint_ieee_prevUnrecoded_prevUnrecoded = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut) node _toint_ieee_prevUnrecoded_T = shr(toint_ieee_prevUnrecoded_unrecoded, 16) node _toint_ieee_prevUnrecoded_T_1 = bits(toint_ieee_prevRecoded, 31, 29) node _toint_ieee_prevUnrecoded_T_2 = andr(_toint_ieee_prevUnrecoded_T_1) node _toint_ieee_prevUnrecoded_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded, 15, 0) node _toint_ieee_prevUnrecoded_T_4 = mux(_toint_ieee_prevUnrecoded_T_2, toint_ieee_prevUnrecoded_prevUnrecoded, _toint_ieee_prevUnrecoded_T_3) node toint_ieee_prevUnrecoded = cat(_toint_ieee_prevUnrecoded_T, _toint_ieee_prevUnrecoded_T_4) node _toint_ieee_T = shr(toint_ieee_unrecoded, 32) node _toint_ieee_T_1 = bits(in.in1, 63, 61) node _toint_ieee_T_2 = andr(_toint_ieee_T_1) node _toint_ieee_T_3 = bits(toint_ieee_unrecoded, 31, 0) node _toint_ieee_T_4 = mux(_toint_ieee_T_2, toint_ieee_prevUnrecoded, _toint_ieee_T_3) node _toint_ieee_T_5 = cat(_toint_ieee_T, _toint_ieee_T_4) node _toint_ieee_T_6 = bits(_toint_ieee_T_5, 15, 0) node _toint_ieee_T_7 = bits(_toint_ieee_T_6, 15, 15) node _toint_ieee_T_8 = mux(_toint_ieee_T_7, UInt<16>(0hffff), UInt<16>(0h0)) node _toint_ieee_T_9 = cat(_toint_ieee_T_8, _toint_ieee_T_6) node _toint_ieee_T_10 = cat(_toint_ieee_T_9, _toint_ieee_T_9) node toint_ieee_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 9) node toint_ieee_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_unrecoded_rawIn_1.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isInf_T_4) connect toint_ieee_unrecoded_rawIn_1.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_5 connect toint_ieee_unrecoded_rawIn_1.isZero, toint_ieee_unrecoded_rawIn_isZero_1 node _toint_ieee_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn_1.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_1 node _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_unrecoded_rawIn_exp_1) connect toint_ieee_unrecoded_rawIn_1.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_1 node _toint_ieee_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_4) node _toint_ieee_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6) connect toint_ieee_unrecoded_rawIn_1.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_7 node toint_ieee_unrecoded_isSubnormal_1 = lt(toint_ieee_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_2) node toint_ieee_unrecoded_denormShiftDist_1 = tail(_toint_ieee_unrecoded_denormShiftDist_T_3, 1) node _toint_ieee_unrecoded_denormFract_T_2 = shr(toint_ieee_unrecoded_rawIn_1.sig, 1) node _toint_ieee_unrecoded_denormFract_T_3 = dshr(_toint_ieee_unrecoded_denormFract_T_2, toint_ieee_unrecoded_denormShiftDist_1) node toint_ieee_unrecoded_denormFract_1 = bits(_toint_ieee_unrecoded_denormFract_T_3, 51, 0) node _toint_ieee_unrecoded_expOut_T_6 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_7 = sub(_toint_ieee_unrecoded_expOut_T_6, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_8 = tail(_toint_ieee_unrecoded_expOut_T_7, 1) node _toint_ieee_unrecoded_expOut_T_9 = mux(toint_ieee_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_8) node _toint_ieee_unrecoded_expOut_T_10 = or(toint_ieee_unrecoded_rawIn_1.isNaN, toint_ieee_unrecoded_rawIn_1.isInf) node _toint_ieee_unrecoded_expOut_T_11 = mux(_toint_ieee_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut_1 = or(_toint_ieee_unrecoded_expOut_T_9, _toint_ieee_unrecoded_expOut_T_11) node _toint_ieee_unrecoded_fractOut_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_3 = mux(toint_ieee_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_2) node toint_ieee_unrecoded_fractOut_1 = mux(toint_ieee_unrecoded_isSubnormal_1, toint_ieee_unrecoded_denormFract_1, _toint_ieee_unrecoded_fractOut_T_3) node toint_ieee_unrecoded_hi_1 = cat(toint_ieee_unrecoded_rawIn_1.sign, toint_ieee_unrecoded_expOut_1) node toint_ieee_unrecoded_1 = cat(toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1) node _toint_ieee_prevRecoded_T_3 = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_4 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_5 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi_1 = cat(_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4) node toint_ieee_prevRecoded_1 = cat(toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(toint_ieee_prevRecoded_1, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevRecoded_1, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevRecoded_1, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1) node toint_ieee_prevUnrecoded_unrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_7, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2) node toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_unrecoded_denormFract_1, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3) node toint_ieee_prevUnrecoded_unrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_1) node toint_ieee_prevUnrecoded_unrecoded_1 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_1, toint_ieee_prevUnrecoded_unrecoded_fractOut_1) node _toint_ieee_prevUnrecoded_prevRecoded_T_3 = bits(toint_ieee_prevRecoded_1, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_4 = bits(toint_ieee_prevRecoded_1, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_5 = bits(toint_ieee_prevRecoded_1, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi_1 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_3, _toint_ieee_prevUnrecoded_prevRecoded_T_4) node toint_ieee_prevUnrecoded_prevRecoded_1 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_1, _toint_ieee_prevUnrecoded_prevRecoded_T_5) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3) node toint_ieee_prevUnrecoded_prevUnrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1) node toint_ieee_prevUnrecoded_prevUnrecoded_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1) node _toint_ieee_prevUnrecoded_T_5 = shr(toint_ieee_prevUnrecoded_unrecoded_1, 16) node _toint_ieee_prevUnrecoded_T_6 = bits(toint_ieee_prevRecoded_1, 31, 29) node _toint_ieee_prevUnrecoded_T_7 = andr(_toint_ieee_prevUnrecoded_T_6) node _toint_ieee_prevUnrecoded_T_8 = bits(toint_ieee_prevUnrecoded_unrecoded_1, 15, 0) node _toint_ieee_prevUnrecoded_T_9 = mux(_toint_ieee_prevUnrecoded_T_7, toint_ieee_prevUnrecoded_prevUnrecoded_1, _toint_ieee_prevUnrecoded_T_8) node toint_ieee_prevUnrecoded_1 = cat(_toint_ieee_prevUnrecoded_T_5, _toint_ieee_prevUnrecoded_T_9) node _toint_ieee_T_11 = shr(toint_ieee_unrecoded_1, 32) node _toint_ieee_T_12 = bits(in.in1, 63, 61) node _toint_ieee_T_13 = andr(_toint_ieee_T_12) node _toint_ieee_T_14 = bits(toint_ieee_unrecoded_1, 31, 0) node _toint_ieee_T_15 = mux(_toint_ieee_T_13, toint_ieee_prevUnrecoded_1, _toint_ieee_T_14) node _toint_ieee_T_16 = cat(_toint_ieee_T_11, _toint_ieee_T_15) node _toint_ieee_T_17 = bits(_toint_ieee_T_16, 31, 0) node _toint_ieee_T_18 = cat(_toint_ieee_T_17, _toint_ieee_T_17) node toint_ieee_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 9) node toint_ieee_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_unrecoded_rawIn_2.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isInf_T_7) connect toint_ieee_unrecoded_rawIn_2.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_8 connect toint_ieee_unrecoded_rawIn_2.isZero, toint_ieee_unrecoded_rawIn_isZero_2 node _toint_ieee_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn_2.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_2 node _toint_ieee_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_unrecoded_rawIn_exp_2) connect toint_ieee_unrecoded_rawIn_2.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_2 node _toint_ieee_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_8) node _toint_ieee_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_9, _toint_ieee_unrecoded_rawIn_out_sig_T_10) connect toint_ieee_unrecoded_rawIn_2.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_11 node toint_ieee_unrecoded_isSubnormal_2 = lt(toint_ieee_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_4) node toint_ieee_unrecoded_denormShiftDist_2 = tail(_toint_ieee_unrecoded_denormShiftDist_T_5, 1) node _toint_ieee_unrecoded_denormFract_T_4 = shr(toint_ieee_unrecoded_rawIn_2.sig, 1) node _toint_ieee_unrecoded_denormFract_T_5 = dshr(_toint_ieee_unrecoded_denormFract_T_4, toint_ieee_unrecoded_denormShiftDist_2) node toint_ieee_unrecoded_denormFract_2 = bits(_toint_ieee_unrecoded_denormFract_T_5, 51, 0) node _toint_ieee_unrecoded_expOut_T_12 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_13 = sub(_toint_ieee_unrecoded_expOut_T_12, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_14 = tail(_toint_ieee_unrecoded_expOut_T_13, 1) node _toint_ieee_unrecoded_expOut_T_15 = mux(toint_ieee_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_14) node _toint_ieee_unrecoded_expOut_T_16 = or(toint_ieee_unrecoded_rawIn_2.isNaN, toint_ieee_unrecoded_rawIn_2.isInf) node _toint_ieee_unrecoded_expOut_T_17 = mux(_toint_ieee_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut_2 = or(_toint_ieee_unrecoded_expOut_T_15, _toint_ieee_unrecoded_expOut_T_17) node _toint_ieee_unrecoded_fractOut_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_5 = mux(toint_ieee_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_4) node toint_ieee_unrecoded_fractOut_2 = mux(toint_ieee_unrecoded_isSubnormal_2, toint_ieee_unrecoded_denormFract_2, _toint_ieee_unrecoded_fractOut_T_5) node toint_ieee_unrecoded_hi_2 = cat(toint_ieee_unrecoded_rawIn_2.sign, toint_ieee_unrecoded_expOut_2) node toint_ieee_unrecoded_2 = cat(toint_ieee_unrecoded_hi_2, toint_ieee_unrecoded_fractOut_2) node _toint_ieee_prevRecoded_T_6 = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_7 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_8 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi_2 = cat(_toint_ieee_prevRecoded_T_6, _toint_ieee_prevRecoded_T_7) node toint_ieee_prevRecoded_2 = cat(toint_ieee_prevRecoded_hi_2, _toint_ieee_prevRecoded_T_8) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(toint_ieee_prevRecoded_2, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevRecoded_2, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevRecoded_2, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2) node toint_ieee_prevUnrecoded_unrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_13, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4) node toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_unrecoded_denormFract_2, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5) node toint_ieee_prevUnrecoded_unrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_2) node toint_ieee_prevUnrecoded_unrecoded_2 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_2, toint_ieee_prevUnrecoded_unrecoded_fractOut_2) node _toint_ieee_prevUnrecoded_prevRecoded_T_6 = bits(toint_ieee_prevRecoded_2, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_7 = bits(toint_ieee_prevRecoded_2, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_8 = bits(toint_ieee_prevRecoded_2, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi_2 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_6, _toint_ieee_prevUnrecoded_prevRecoded_T_7) node toint_ieee_prevUnrecoded_prevRecoded_2 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_2, _toint_ieee_prevUnrecoded_prevRecoded_T_8) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5) node toint_ieee_prevUnrecoded_prevUnrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2) node toint_ieee_prevUnrecoded_prevUnrecoded_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_2, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2) node _toint_ieee_prevUnrecoded_T_10 = shr(toint_ieee_prevUnrecoded_unrecoded_2, 16) node _toint_ieee_prevUnrecoded_T_11 = bits(toint_ieee_prevRecoded_2, 31, 29) node _toint_ieee_prevUnrecoded_T_12 = andr(_toint_ieee_prevUnrecoded_T_11) node _toint_ieee_prevUnrecoded_T_13 = bits(toint_ieee_prevUnrecoded_unrecoded_2, 15, 0) node _toint_ieee_prevUnrecoded_T_14 = mux(_toint_ieee_prevUnrecoded_T_12, toint_ieee_prevUnrecoded_prevUnrecoded_2, _toint_ieee_prevUnrecoded_T_13) node toint_ieee_prevUnrecoded_2 = cat(_toint_ieee_prevUnrecoded_T_10, _toint_ieee_prevUnrecoded_T_14) node _toint_ieee_T_19 = shr(toint_ieee_unrecoded_2, 32) node _toint_ieee_T_20 = bits(in.in1, 63, 61) node _toint_ieee_T_21 = andr(_toint_ieee_T_20) node _toint_ieee_T_22 = bits(toint_ieee_unrecoded_2, 31, 0) node _toint_ieee_T_23 = mux(_toint_ieee_T_21, toint_ieee_prevUnrecoded_2, _toint_ieee_T_22) node _toint_ieee_T_24 = cat(_toint_ieee_T_19, _toint_ieee_T_23) node _toint_ieee_T_25 = bits(_toint_ieee_T_24, 63, 0) node _toint_ieee_T_26 = eq(in.typeTagOut, UInt<1>(0h1)) node _toint_ieee_T_27 = mux(_toint_ieee_T_26, _toint_ieee_T_18, _toint_ieee_T_10) node _toint_ieee_T_28 = eq(in.typeTagOut, UInt<2>(0h2)) node _toint_ieee_T_29 = mux(_toint_ieee_T_28, _toint_ieee_T_25, _toint_ieee_T_27) node _toint_ieee_T_30 = eq(in.typeTagOut, UInt<2>(0h3)) node toint_ieee = mux(_toint_ieee_T_30, _toint_ieee_T_25, _toint_ieee_T_29) wire toint : UInt connect toint, toint_ieee node _intType_T = bits(in.fmt, 0, 0) wire intType : UInt<1> connect intType, _intType_T node io_out_bits_store_unrecoded_rawIn_exp = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_unrecoded_rawIn.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_unrecoded_rawIn.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_unrecoded_rawIn.isZero, io_out_bits_store_unrecoded_rawIn_isZero node _io_out_bits_store_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T node _io_out_bits_store_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_unrecoded_rawIn_exp) connect io_out_bits_store_unrecoded_rawIn.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T node _io_out_bits_store_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_unrecoded_rawIn.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 node io_out_bits_store_unrecoded_isSubnormal = lt(io_out_bits_store_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T) node io_out_bits_store_unrecoded_denormShiftDist = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_unrecoded_denormFract_T = shr(io_out_bits_store_unrecoded_rawIn.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_unrecoded_denormFract_T, io_out_bits_store_unrecoded_denormShiftDist) node io_out_bits_store_unrecoded_denormFract = bits(_io_out_bits_store_unrecoded_denormFract_T_1, 51, 0) node _io_out_bits_store_unrecoded_expOut_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_1 = sub(_io_out_bits_store_unrecoded_expOut_T, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_2 = tail(_io_out_bits_store_unrecoded_expOut_T_1, 1) node _io_out_bits_store_unrecoded_expOut_T_3 = mux(io_out_bits_store_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_2) node _io_out_bits_store_unrecoded_expOut_T_4 = or(io_out_bits_store_unrecoded_rawIn.isNaN, io_out_bits_store_unrecoded_rawIn.isInf) node _io_out_bits_store_unrecoded_expOut_T_5 = mux(_io_out_bits_store_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut = or(_io_out_bits_store_unrecoded_expOut_T_3, _io_out_bits_store_unrecoded_expOut_T_5) node _io_out_bits_store_unrecoded_fractOut_T = bits(io_out_bits_store_unrecoded_rawIn.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_1 = mux(io_out_bits_store_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T) node io_out_bits_store_unrecoded_fractOut = mux(io_out_bits_store_unrecoded_isSubnormal, io_out_bits_store_unrecoded_denormFract, _io_out_bits_store_unrecoded_fractOut_T_1) node io_out_bits_store_unrecoded_hi = cat(io_out_bits_store_unrecoded_rawIn.sign, io_out_bits_store_unrecoded_expOut) node io_out_bits_store_unrecoded = cat(io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut) node _io_out_bits_store_prevRecoded_T = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_1 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_2 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi = cat(_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1) node io_out_bits_store_prevRecoded = cat(io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp = bits(io_out_bits_store_prevRecoded, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevRecoded, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevRecoded, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_unrecoded_denormFract, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1) node io_out_bits_store_prevUnrecoded_unrecoded_hi = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut) node io_out_bits_store_prevUnrecoded_unrecoded = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi, io_out_bits_store_prevUnrecoded_unrecoded_fractOut) node _io_out_bits_store_prevUnrecoded_prevRecoded_T = bits(io_out_bits_store_prevRecoded, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_1 = bits(io_out_bits_store_prevRecoded, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_2 = bits(io_out_bits_store_prevRecoded, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T, _io_out_bits_store_prevUnrecoded_prevRecoded_T_1) node io_out_bits_store_prevUnrecoded_prevRecoded = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi, _io_out_bits_store_prevUnrecoded_prevRecoded_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut) node io_out_bits_store_prevUnrecoded_prevUnrecoded = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut) node _io_out_bits_store_prevUnrecoded_T = shr(io_out_bits_store_prevUnrecoded_unrecoded, 16) node _io_out_bits_store_prevUnrecoded_T_1 = bits(io_out_bits_store_prevRecoded, 31, 29) node _io_out_bits_store_prevUnrecoded_T_2 = andr(_io_out_bits_store_prevUnrecoded_T_1) node _io_out_bits_store_prevUnrecoded_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded, 15, 0) node _io_out_bits_store_prevUnrecoded_T_4 = mux(_io_out_bits_store_prevUnrecoded_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded, _io_out_bits_store_prevUnrecoded_T_3) node io_out_bits_store_prevUnrecoded = cat(_io_out_bits_store_prevUnrecoded_T, _io_out_bits_store_prevUnrecoded_T_4) node _io_out_bits_store_T = shr(io_out_bits_store_unrecoded, 32) node _io_out_bits_store_T_1 = bits(in.in1, 63, 61) node _io_out_bits_store_T_2 = andr(_io_out_bits_store_T_1) node _io_out_bits_store_T_3 = bits(io_out_bits_store_unrecoded, 31, 0) node _io_out_bits_store_T_4 = mux(_io_out_bits_store_T_2, io_out_bits_store_prevUnrecoded, _io_out_bits_store_T_3) node _io_out_bits_store_T_5 = cat(_io_out_bits_store_T, _io_out_bits_store_T_4) node _io_out_bits_store_T_6 = bits(_io_out_bits_store_T_5, 15, 0) node _io_out_bits_store_T_7 = cat(_io_out_bits_store_T_6, _io_out_bits_store_T_6) node _io_out_bits_store_T_8 = cat(_io_out_bits_store_T_7, _io_out_bits_store_T_7) node io_out_bits_store_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_unrecoded_rawIn_1.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_unrecoded_rawIn_1.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_unrecoded_rawIn_1.isZero, io_out_bits_store_unrecoded_rawIn_isZero_1 node _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn_1.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_unrecoded_rawIn_exp_1) connect io_out_bits_store_unrecoded_rawIn_1.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_unrecoded_rawIn_1.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 node io_out_bits_store_unrecoded_isSubnormal_1 = lt(io_out_bits_store_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_2) node io_out_bits_store_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_unrecoded_denormFract_T_2 = shr(io_out_bits_store_unrecoded_rawIn_1.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_unrecoded_denormFract_T_2, io_out_bits_store_unrecoded_denormShiftDist_1) node io_out_bits_store_unrecoded_denormFract_1 = bits(_io_out_bits_store_unrecoded_denormFract_T_3, 51, 0) node _io_out_bits_store_unrecoded_expOut_T_6 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_7 = sub(_io_out_bits_store_unrecoded_expOut_T_6, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_8 = tail(_io_out_bits_store_unrecoded_expOut_T_7, 1) node _io_out_bits_store_unrecoded_expOut_T_9 = mux(io_out_bits_store_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_8) node _io_out_bits_store_unrecoded_expOut_T_10 = or(io_out_bits_store_unrecoded_rawIn_1.isNaN, io_out_bits_store_unrecoded_rawIn_1.isInf) node _io_out_bits_store_unrecoded_expOut_T_11 = mux(_io_out_bits_store_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut_1 = or(_io_out_bits_store_unrecoded_expOut_T_9, _io_out_bits_store_unrecoded_expOut_T_11) node _io_out_bits_store_unrecoded_fractOut_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_3 = mux(io_out_bits_store_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_2) node io_out_bits_store_unrecoded_fractOut_1 = mux(io_out_bits_store_unrecoded_isSubnormal_1, io_out_bits_store_unrecoded_denormFract_1, _io_out_bits_store_unrecoded_fractOut_T_3) node io_out_bits_store_unrecoded_hi_1 = cat(io_out_bits_store_unrecoded_rawIn_1.sign, io_out_bits_store_unrecoded_expOut_1) node io_out_bits_store_unrecoded_1 = cat(io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1) node _io_out_bits_store_prevRecoded_T_3 = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_4 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_5 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi_1 = cat(_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4) node io_out_bits_store_prevRecoded_1 = cat(io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevRecoded_1, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevRecoded_1, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevRecoded_1, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3) node io_out_bits_store_prevUnrecoded_unrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_1) node io_out_bits_store_prevUnrecoded_unrecoded_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_1, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_3 = bits(io_out_bits_store_prevRecoded_1, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_4 = bits(io_out_bits_store_prevRecoded_1, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_5 = bits(io_out_bits_store_prevRecoded_1, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi_1 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_3, _io_out_bits_store_prevUnrecoded_prevRecoded_T_4) node io_out_bits_store_prevUnrecoded_prevRecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_1, _io_out_bits_store_prevUnrecoded_prevRecoded_T_5) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1) node _io_out_bits_store_prevUnrecoded_T_5 = shr(io_out_bits_store_prevUnrecoded_unrecoded_1, 16) node _io_out_bits_store_prevUnrecoded_T_6 = bits(io_out_bits_store_prevRecoded_1, 31, 29) node _io_out_bits_store_prevUnrecoded_T_7 = andr(_io_out_bits_store_prevUnrecoded_T_6) node _io_out_bits_store_prevUnrecoded_T_8 = bits(io_out_bits_store_prevUnrecoded_unrecoded_1, 15, 0) node _io_out_bits_store_prevUnrecoded_T_9 = mux(_io_out_bits_store_prevUnrecoded_T_7, io_out_bits_store_prevUnrecoded_prevUnrecoded_1, _io_out_bits_store_prevUnrecoded_T_8) node io_out_bits_store_prevUnrecoded_1 = cat(_io_out_bits_store_prevUnrecoded_T_5, _io_out_bits_store_prevUnrecoded_T_9) node _io_out_bits_store_T_9 = shr(io_out_bits_store_unrecoded_1, 32) node _io_out_bits_store_T_10 = bits(in.in1, 63, 61) node _io_out_bits_store_T_11 = andr(_io_out_bits_store_T_10) node _io_out_bits_store_T_12 = bits(io_out_bits_store_unrecoded_1, 31, 0) node _io_out_bits_store_T_13 = mux(_io_out_bits_store_T_11, io_out_bits_store_prevUnrecoded_1, _io_out_bits_store_T_12) node _io_out_bits_store_T_14 = cat(_io_out_bits_store_T_9, _io_out_bits_store_T_13) node _io_out_bits_store_T_15 = bits(_io_out_bits_store_T_14, 31, 0) node _io_out_bits_store_T_16 = cat(_io_out_bits_store_T_15, _io_out_bits_store_T_15) node io_out_bits_store_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_unrecoded_rawIn_2.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_unrecoded_rawIn_2.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_unrecoded_rawIn_2.isZero, io_out_bits_store_unrecoded_rawIn_isZero_2 node _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn_2.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_unrecoded_rawIn_exp_2) connect io_out_bits_store_unrecoded_rawIn_2.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_unrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_unrecoded_rawIn_2.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 node io_out_bits_store_unrecoded_isSubnormal_2 = lt(io_out_bits_store_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_4) node io_out_bits_store_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_unrecoded_denormFract_T_4 = shr(io_out_bits_store_unrecoded_rawIn_2.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_unrecoded_denormFract_T_4, io_out_bits_store_unrecoded_denormShiftDist_2) node io_out_bits_store_unrecoded_denormFract_2 = bits(_io_out_bits_store_unrecoded_denormFract_T_5, 51, 0) node _io_out_bits_store_unrecoded_expOut_T_12 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_13 = sub(_io_out_bits_store_unrecoded_expOut_T_12, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_14 = tail(_io_out_bits_store_unrecoded_expOut_T_13, 1) node _io_out_bits_store_unrecoded_expOut_T_15 = mux(io_out_bits_store_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_14) node _io_out_bits_store_unrecoded_expOut_T_16 = or(io_out_bits_store_unrecoded_rawIn_2.isNaN, io_out_bits_store_unrecoded_rawIn_2.isInf) node _io_out_bits_store_unrecoded_expOut_T_17 = mux(_io_out_bits_store_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut_2 = or(_io_out_bits_store_unrecoded_expOut_T_15, _io_out_bits_store_unrecoded_expOut_T_17) node _io_out_bits_store_unrecoded_fractOut_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_5 = mux(io_out_bits_store_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_4) node io_out_bits_store_unrecoded_fractOut_2 = mux(io_out_bits_store_unrecoded_isSubnormal_2, io_out_bits_store_unrecoded_denormFract_2, _io_out_bits_store_unrecoded_fractOut_T_5) node io_out_bits_store_unrecoded_hi_2 = cat(io_out_bits_store_unrecoded_rawIn_2.sign, io_out_bits_store_unrecoded_expOut_2) node io_out_bits_store_unrecoded_2 = cat(io_out_bits_store_unrecoded_hi_2, io_out_bits_store_unrecoded_fractOut_2) node _io_out_bits_store_prevRecoded_T_6 = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_7 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_8 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi_2 = cat(_io_out_bits_store_prevRecoded_T_6, _io_out_bits_store_prevRecoded_T_7) node io_out_bits_store_prevRecoded_2 = cat(io_out_bits_store_prevRecoded_hi_2, _io_out_bits_store_prevRecoded_T_8) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevRecoded_2, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevRecoded_2, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevRecoded_2, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5) node io_out_bits_store_prevUnrecoded_unrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_2) node io_out_bits_store_prevUnrecoded_unrecoded_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_2, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_6 = bits(io_out_bits_store_prevRecoded_2, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_7 = bits(io_out_bits_store_prevRecoded_2, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_8 = bits(io_out_bits_store_prevRecoded_2, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi_2 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_6, _io_out_bits_store_prevUnrecoded_prevRecoded_T_7) node io_out_bits_store_prevUnrecoded_prevRecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_2, _io_out_bits_store_prevUnrecoded_prevRecoded_T_8) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2) node _io_out_bits_store_prevUnrecoded_T_10 = shr(io_out_bits_store_prevUnrecoded_unrecoded_2, 16) node _io_out_bits_store_prevUnrecoded_T_11 = bits(io_out_bits_store_prevRecoded_2, 31, 29) node _io_out_bits_store_prevUnrecoded_T_12 = andr(_io_out_bits_store_prevUnrecoded_T_11) node _io_out_bits_store_prevUnrecoded_T_13 = bits(io_out_bits_store_prevUnrecoded_unrecoded_2, 15, 0) node _io_out_bits_store_prevUnrecoded_T_14 = mux(_io_out_bits_store_prevUnrecoded_T_12, io_out_bits_store_prevUnrecoded_prevUnrecoded_2, _io_out_bits_store_prevUnrecoded_T_13) node io_out_bits_store_prevUnrecoded_2 = cat(_io_out_bits_store_prevUnrecoded_T_10, _io_out_bits_store_prevUnrecoded_T_14) node _io_out_bits_store_T_17 = shr(io_out_bits_store_unrecoded_2, 32) node _io_out_bits_store_T_18 = bits(in.in1, 63, 61) node _io_out_bits_store_T_19 = andr(_io_out_bits_store_T_18) node _io_out_bits_store_T_20 = bits(io_out_bits_store_unrecoded_2, 31, 0) node _io_out_bits_store_T_21 = mux(_io_out_bits_store_T_19, io_out_bits_store_prevUnrecoded_2, _io_out_bits_store_T_20) node _io_out_bits_store_T_22 = cat(_io_out_bits_store_T_17, _io_out_bits_store_T_21) node _io_out_bits_store_T_23 = bits(_io_out_bits_store_T_22, 63, 0) node _io_out_bits_store_T_24 = eq(in.typeTagOut, UInt<1>(0h1)) node _io_out_bits_store_T_25 = mux(_io_out_bits_store_T_24, _io_out_bits_store_T_16, _io_out_bits_store_T_8) node _io_out_bits_store_T_26 = eq(in.typeTagOut, UInt<2>(0h2)) node _io_out_bits_store_T_27 = mux(_io_out_bits_store_T_26, _io_out_bits_store_T_23, _io_out_bits_store_T_25) node _io_out_bits_store_T_28 = eq(in.typeTagOut, UInt<2>(0h3)) node _io_out_bits_store_T_29 = mux(_io_out_bits_store_T_28, _io_out_bits_store_T_23, _io_out_bits_store_T_27) connect io.out.bits.store, _io_out_bits_store_T_29 node _io_out_bits_toint_T = bits(toint, 31, 0) node _io_out_bits_toint_T_1 = bits(_io_out_bits_toint_T, 31, 31) node _io_out_bits_toint_T_2 = mux(_io_out_bits_toint_T_1, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_out_bits_toint_T_3 = cat(_io_out_bits_toint_T_2, _io_out_bits_toint_T) node _io_out_bits_toint_T_4 = bits(toint, 63, 0) node _io_out_bits_toint_T_5 = eq(intType, UInt<1>(0h1)) node _io_out_bits_toint_T_6 = mux(_io_out_bits_toint_T_5, _io_out_bits_toint_T_4, _io_out_bits_toint_T_3) connect io.out.bits.toint, _io_out_bits_toint_T_6 connect io.out.bits.exc, UInt<1>(0h0) node _T = bits(in.rm, 0, 0) when _T : node classify_out_sign = bits(in.in1, 64, 64) node classify_out_fractIn = bits(in.in1, 51, 0) node classify_out_expIn = bits(in.in1, 63, 52) node _classify_out_fractOut_T = shl(classify_out_fractIn, 11) node classify_out_fractOut = shr(_classify_out_fractOut_T, 53) node classify_out_expOut_expCode = bits(classify_out_expIn, 11, 9) node _classify_out_expOut_commonCase_T = add(classify_out_expIn, UInt<6>(0h20)) node _classify_out_expOut_commonCase_T_1 = tail(_classify_out_expOut_commonCase_T, 1) node _classify_out_expOut_commonCase_T_2 = sub(_classify_out_expOut_commonCase_T_1, UInt<12>(0h800)) node classify_out_expOut_commonCase = tail(_classify_out_expOut_commonCase_T_2, 1) node _classify_out_expOut_T = eq(classify_out_expOut_expCode, UInt<1>(0h0)) node _classify_out_expOut_T_1 = geq(classify_out_expOut_expCode, UInt<3>(0h6)) node _classify_out_expOut_T_2 = or(_classify_out_expOut_T, _classify_out_expOut_T_1) node _classify_out_expOut_T_3 = bits(classify_out_expOut_commonCase, 2, 0) node _classify_out_expOut_T_4 = cat(classify_out_expOut_expCode, _classify_out_expOut_T_3) node _classify_out_expOut_T_5 = bits(classify_out_expOut_commonCase, 5, 0) node classify_out_expOut = mux(_classify_out_expOut_T_2, _classify_out_expOut_T_4, _classify_out_expOut_T_5) node classify_out_hi = cat(classify_out_sign, classify_out_expOut) node _classify_out_T = cat(classify_out_hi, classify_out_fractOut) node classify_out_sign_1 = bits(_classify_out_T, 16, 16) node classify_out_code = bits(_classify_out_T, 15, 13) node classify_out_codeHi = bits(classify_out_code, 2, 1) node classify_out_isSpecial = eq(classify_out_codeHi, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T = bits(_classify_out_T, 13, 10) node classify_out_isHighSubnormalIn = lt(_classify_out_isHighSubnormalIn_T, UInt<2>(0h2)) node _classify_out_isSubnormal_T = eq(classify_out_code, UInt<1>(0h1)) node _classify_out_isSubnormal_T_1 = eq(classify_out_codeHi, UInt<1>(0h1)) node _classify_out_isSubnormal_T_2 = and(_classify_out_isSubnormal_T_1, classify_out_isHighSubnormalIn) node classify_out_isSubnormal = or(_classify_out_isSubnormal_T, _classify_out_isSubnormal_T_2) node _classify_out_isNormal_T = eq(classify_out_codeHi, UInt<1>(0h1)) node _classify_out_isNormal_T_1 = eq(classify_out_isHighSubnormalIn, UInt<1>(0h0)) node _classify_out_isNormal_T_2 = and(_classify_out_isNormal_T, _classify_out_isNormal_T_1) node _classify_out_isNormal_T_3 = eq(classify_out_codeHi, UInt<2>(0h2)) node classify_out_isNormal = or(_classify_out_isNormal_T_2, _classify_out_isNormal_T_3) node classify_out_isZero = eq(classify_out_code, UInt<1>(0h0)) node _classify_out_isInf_T = bits(classify_out_code, 0, 0) node _classify_out_isInf_T_1 = eq(_classify_out_isInf_T, UInt<1>(0h0)) node classify_out_isInf = and(classify_out_isSpecial, _classify_out_isInf_T_1) node classify_out_isNaN = andr(classify_out_code) node _classify_out_isSNaN_T = bits(_classify_out_T, 9, 9) node _classify_out_isSNaN_T_1 = eq(_classify_out_isSNaN_T, UInt<1>(0h0)) node classify_out_isSNaN = and(classify_out_isNaN, _classify_out_isSNaN_T_1) node _classify_out_isQNaN_T = bits(_classify_out_T, 9, 9) node classify_out_isQNaN = and(classify_out_isNaN, _classify_out_isQNaN_T) node _classify_out_T_1 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_2 = and(classify_out_isInf, _classify_out_T_1) node _classify_out_T_3 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_4 = and(classify_out_isNormal, _classify_out_T_3) node _classify_out_T_5 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_6 = and(classify_out_isSubnormal, _classify_out_T_5) node _classify_out_T_7 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_8 = and(classify_out_isZero, _classify_out_T_7) node _classify_out_T_9 = and(classify_out_isZero, classify_out_sign_1) node _classify_out_T_10 = and(classify_out_isSubnormal, classify_out_sign_1) node _classify_out_T_11 = and(classify_out_isNormal, classify_out_sign_1) node _classify_out_T_12 = and(classify_out_isInf, classify_out_sign_1) node classify_out_lo_lo = cat(_classify_out_T_11, _classify_out_T_12) node classify_out_lo_hi_hi = cat(_classify_out_T_8, _classify_out_T_9) node classify_out_lo_hi = cat(classify_out_lo_hi_hi, _classify_out_T_10) node classify_out_lo = cat(classify_out_lo_hi, classify_out_lo_lo) node classify_out_hi_lo = cat(_classify_out_T_4, _classify_out_T_6) node classify_out_hi_hi_hi = cat(classify_out_isQNaN, classify_out_isSNaN) node classify_out_hi_hi = cat(classify_out_hi_hi_hi, _classify_out_T_2) node classify_out_hi_1 = cat(classify_out_hi_hi, classify_out_hi_lo) node _classify_out_T_13 = cat(classify_out_hi_1, classify_out_lo) node classify_out_sign_2 = bits(in.in1, 64, 64) node classify_out_fractIn_1 = bits(in.in1, 51, 0) node classify_out_expIn_1 = bits(in.in1, 63, 52) node _classify_out_fractOut_T_1 = shl(classify_out_fractIn_1, 24) node classify_out_fractOut_1 = shr(_classify_out_fractOut_T_1, 53) node classify_out_expOut_expCode_1 = bits(classify_out_expIn_1, 11, 9) node _classify_out_expOut_commonCase_T_3 = add(classify_out_expIn_1, UInt<9>(0h100)) node _classify_out_expOut_commonCase_T_4 = tail(_classify_out_expOut_commonCase_T_3, 1) node _classify_out_expOut_commonCase_T_5 = sub(_classify_out_expOut_commonCase_T_4, UInt<12>(0h800)) node classify_out_expOut_commonCase_1 = tail(_classify_out_expOut_commonCase_T_5, 1) node _classify_out_expOut_T_6 = eq(classify_out_expOut_expCode_1, UInt<1>(0h0)) node _classify_out_expOut_T_7 = geq(classify_out_expOut_expCode_1, UInt<3>(0h6)) node _classify_out_expOut_T_8 = or(_classify_out_expOut_T_6, _classify_out_expOut_T_7) node _classify_out_expOut_T_9 = bits(classify_out_expOut_commonCase_1, 5, 0) node _classify_out_expOut_T_10 = cat(classify_out_expOut_expCode_1, _classify_out_expOut_T_9) node _classify_out_expOut_T_11 = bits(classify_out_expOut_commonCase_1, 8, 0) node classify_out_expOut_1 = mux(_classify_out_expOut_T_8, _classify_out_expOut_T_10, _classify_out_expOut_T_11) node classify_out_hi_2 = cat(classify_out_sign_2, classify_out_expOut_1) node _classify_out_T_14 = cat(classify_out_hi_2, classify_out_fractOut_1) node classify_out_sign_3 = bits(_classify_out_T_14, 32, 32) node classify_out_code_1 = bits(_classify_out_T_14, 31, 29) node classify_out_codeHi_1 = bits(classify_out_code_1, 2, 1) node classify_out_isSpecial_1 = eq(classify_out_codeHi_1, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T_1 = bits(_classify_out_T_14, 29, 23) node classify_out_isHighSubnormalIn_1 = lt(_classify_out_isHighSubnormalIn_T_1, UInt<2>(0h2)) node _classify_out_isSubnormal_T_3 = eq(classify_out_code_1, UInt<1>(0h1)) node _classify_out_isSubnormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) node _classify_out_isSubnormal_T_5 = and(_classify_out_isSubnormal_T_4, classify_out_isHighSubnormalIn_1) node classify_out_isSubnormal_1 = or(_classify_out_isSubnormal_T_3, _classify_out_isSubnormal_T_5) node _classify_out_isNormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) node _classify_out_isNormal_T_5 = eq(classify_out_isHighSubnormalIn_1, UInt<1>(0h0)) node _classify_out_isNormal_T_6 = and(_classify_out_isNormal_T_4, _classify_out_isNormal_T_5) node _classify_out_isNormal_T_7 = eq(classify_out_codeHi_1, UInt<2>(0h2)) node classify_out_isNormal_1 = or(_classify_out_isNormal_T_6, _classify_out_isNormal_T_7) node classify_out_isZero_1 = eq(classify_out_code_1, UInt<1>(0h0)) node _classify_out_isInf_T_2 = bits(classify_out_code_1, 0, 0) node _classify_out_isInf_T_3 = eq(_classify_out_isInf_T_2, UInt<1>(0h0)) node classify_out_isInf_1 = and(classify_out_isSpecial_1, _classify_out_isInf_T_3) node classify_out_isNaN_1 = andr(classify_out_code_1) node _classify_out_isSNaN_T_2 = bits(_classify_out_T_14, 22, 22) node _classify_out_isSNaN_T_3 = eq(_classify_out_isSNaN_T_2, UInt<1>(0h0)) node classify_out_isSNaN_1 = and(classify_out_isNaN_1, _classify_out_isSNaN_T_3) node _classify_out_isQNaN_T_1 = bits(_classify_out_T_14, 22, 22) node classify_out_isQNaN_1 = and(classify_out_isNaN_1, _classify_out_isQNaN_T_1) node _classify_out_T_15 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_16 = and(classify_out_isInf_1, _classify_out_T_15) node _classify_out_T_17 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_18 = and(classify_out_isNormal_1, _classify_out_T_17) node _classify_out_T_19 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_20 = and(classify_out_isSubnormal_1, _classify_out_T_19) node _classify_out_T_21 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_22 = and(classify_out_isZero_1, _classify_out_T_21) node _classify_out_T_23 = and(classify_out_isZero_1, classify_out_sign_3) node _classify_out_T_24 = and(classify_out_isSubnormal_1, classify_out_sign_3) node _classify_out_T_25 = and(classify_out_isNormal_1, classify_out_sign_3) node _classify_out_T_26 = and(classify_out_isInf_1, classify_out_sign_3) node classify_out_lo_lo_1 = cat(_classify_out_T_25, _classify_out_T_26) node classify_out_lo_hi_hi_1 = cat(_classify_out_T_22, _classify_out_T_23) node classify_out_lo_hi_1 = cat(classify_out_lo_hi_hi_1, _classify_out_T_24) node classify_out_lo_1 = cat(classify_out_lo_hi_1, classify_out_lo_lo_1) node classify_out_hi_lo_1 = cat(_classify_out_T_18, _classify_out_T_20) node classify_out_hi_hi_hi_1 = cat(classify_out_isQNaN_1, classify_out_isSNaN_1) node classify_out_hi_hi_1 = cat(classify_out_hi_hi_hi_1, _classify_out_T_16) node classify_out_hi_3 = cat(classify_out_hi_hi_1, classify_out_hi_lo_1) node _classify_out_T_27 = cat(classify_out_hi_3, classify_out_lo_1) node classify_out_sign_4 = bits(in.in1, 64, 64) node classify_out_code_2 = bits(in.in1, 63, 61) node classify_out_codeHi_2 = bits(classify_out_code_2, 2, 1) node classify_out_isSpecial_2 = eq(classify_out_codeHi_2, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T_2 = bits(in.in1, 61, 52) node classify_out_isHighSubnormalIn_2 = lt(_classify_out_isHighSubnormalIn_T_2, UInt<2>(0h2)) node _classify_out_isSubnormal_T_6 = eq(classify_out_code_2, UInt<1>(0h1)) node _classify_out_isSubnormal_T_7 = eq(classify_out_codeHi_2, UInt<1>(0h1)) node _classify_out_isSubnormal_T_8 = and(_classify_out_isSubnormal_T_7, classify_out_isHighSubnormalIn_2) node classify_out_isSubnormal_2 = or(_classify_out_isSubnormal_T_6, _classify_out_isSubnormal_T_8) node _classify_out_isNormal_T_8 = eq(classify_out_codeHi_2, UInt<1>(0h1)) node _classify_out_isNormal_T_9 = eq(classify_out_isHighSubnormalIn_2, UInt<1>(0h0)) node _classify_out_isNormal_T_10 = and(_classify_out_isNormal_T_8, _classify_out_isNormal_T_9) node _classify_out_isNormal_T_11 = eq(classify_out_codeHi_2, UInt<2>(0h2)) node classify_out_isNormal_2 = or(_classify_out_isNormal_T_10, _classify_out_isNormal_T_11) node classify_out_isZero_2 = eq(classify_out_code_2, UInt<1>(0h0)) node _classify_out_isInf_T_4 = bits(classify_out_code_2, 0, 0) node _classify_out_isInf_T_5 = eq(_classify_out_isInf_T_4, UInt<1>(0h0)) node classify_out_isInf_2 = and(classify_out_isSpecial_2, _classify_out_isInf_T_5) node classify_out_isNaN_2 = andr(classify_out_code_2) node _classify_out_isSNaN_T_4 = bits(in.in1, 51, 51) node _classify_out_isSNaN_T_5 = eq(_classify_out_isSNaN_T_4, UInt<1>(0h0)) node classify_out_isSNaN_2 = and(classify_out_isNaN_2, _classify_out_isSNaN_T_5) node _classify_out_isQNaN_T_2 = bits(in.in1, 51, 51) node classify_out_isQNaN_2 = and(classify_out_isNaN_2, _classify_out_isQNaN_T_2) node _classify_out_T_28 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_29 = and(classify_out_isInf_2, _classify_out_T_28) node _classify_out_T_30 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_31 = and(classify_out_isNormal_2, _classify_out_T_30) node _classify_out_T_32 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_33 = and(classify_out_isSubnormal_2, _classify_out_T_32) node _classify_out_T_34 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_35 = and(classify_out_isZero_2, _classify_out_T_34) node _classify_out_T_36 = and(classify_out_isZero_2, classify_out_sign_4) node _classify_out_T_37 = and(classify_out_isSubnormal_2, classify_out_sign_4) node _classify_out_T_38 = and(classify_out_isNormal_2, classify_out_sign_4) node _classify_out_T_39 = and(classify_out_isInf_2, classify_out_sign_4) node classify_out_lo_lo_2 = cat(_classify_out_T_38, _classify_out_T_39) node classify_out_lo_hi_hi_2 = cat(_classify_out_T_35, _classify_out_T_36) node classify_out_lo_hi_2 = cat(classify_out_lo_hi_hi_2, _classify_out_T_37) node classify_out_lo_2 = cat(classify_out_lo_hi_2, classify_out_lo_lo_2) node classify_out_hi_lo_2 = cat(_classify_out_T_31, _classify_out_T_33) node classify_out_hi_hi_hi_2 = cat(classify_out_isQNaN_2, classify_out_isSNaN_2) node classify_out_hi_hi_2 = cat(classify_out_hi_hi_hi_2, _classify_out_T_29) node classify_out_hi_4 = cat(classify_out_hi_hi_2, classify_out_hi_lo_2) node _classify_out_T_40 = cat(classify_out_hi_4, classify_out_lo_2) node _classify_out_T_41 = eq(in.typeTagOut, UInt<1>(0h1)) node _classify_out_T_42 = mux(_classify_out_T_41, _classify_out_T_27, _classify_out_T_13) node _classify_out_T_43 = eq(in.typeTagOut, UInt<2>(0h2)) node _classify_out_T_44 = mux(_classify_out_T_43, _classify_out_T_40, _classify_out_T_42) node _classify_out_T_45 = eq(in.typeTagOut, UInt<2>(0h3)) node classify_out = mux(_classify_out_T_45, _classify_out_T_40, _classify_out_T_44) node _toint_T = shr(toint_ieee, 32) node _toint_T_1 = shl(_toint_T, 32) node _toint_T_2 = or(classify_out, _toint_T_1) connect toint, _toint_T_2 connect intType, UInt<1>(0h0) when in.wflags : node _toint_T_3 = not(in.rm) node _toint_T_4 = cat(dcmp.io.lt, dcmp.io.eq) node _toint_T_5 = and(_toint_T_3, _toint_T_4) node _toint_T_6 = orr(_toint_T_5) node _toint_T_7 = shr(toint_ieee, 32) node _toint_T_8 = shl(_toint_T_7, 32) node _toint_T_9 = or(_toint_T_6, _toint_T_8) connect toint, _toint_T_9 connect io.out.bits.exc, dcmp.io.exceptionFlags connect intType, UInt<1>(0h0) node _T_1 = eq(in.ren2, UInt<1>(0h0)) when _T_1 : node cvtType = bits(in.typ, 1, 1) connect intType, cvtType inst conv of RecFNToIN_e11_s53_i64 connect conv.clock, clock connect conv.reset, reset connect conv.io.in, in.in1 connect conv.io.roundingMode, in.rm node _conv_io_signedOut_T = bits(in.typ, 0, 0) node _conv_io_signedOut_T_1 = not(_conv_io_signedOut_T) connect conv.io.signedOut, _conv_io_signedOut_T_1 connect toint, conv.io.out node _io_out_bits_exc_T = bits(conv.io.intExceptionFlags, 2, 1) node _io_out_bits_exc_T_1 = orr(_io_out_bits_exc_T) node _io_out_bits_exc_T_2 = bits(conv.io.intExceptionFlags, 0, 0) node io_out_bits_exc_hi = cat(_io_out_bits_exc_T_1, UInt<3>(0h0)) node _io_out_bits_exc_T_3 = cat(io_out_bits_exc_hi, _io_out_bits_exc_T_2) connect io.out.bits.exc, _io_out_bits_exc_T_3 node _T_2 = eq(cvtType, UInt<1>(0h0)) when _T_2 : inst narrow of RecFNToIN_e11_s53_i32 connect narrow.clock, clock connect narrow.reset, reset connect narrow.io.in, in.in1 connect narrow.io.roundingMode, in.rm node _narrow_io_signedOut_T = bits(in.typ, 0, 0) node _narrow_io_signedOut_T_1 = not(_narrow_io_signedOut_T) connect narrow.io.signedOut, _narrow_io_signedOut_T_1 node _excSign_T = bits(in.in1, 64, 64) node _excSign_T_1 = bits(in.in1, 63, 61) node _excSign_T_2 = andr(_excSign_T_1) node _excSign_T_3 = eq(_excSign_T_2, UInt<1>(0h0)) node excSign = and(_excSign_T, _excSign_T_3) node _excOut_T = eq(conv.io.signedOut, excSign) node _excOut_T_1 = eq(excSign, UInt<1>(0h0)) node _excOut_T_2 = mux(_excOut_T_1, UInt<31>(0h7fffffff), UInt<31>(0h0)) node excOut = cat(_excOut_T, _excOut_T_2) node _invalid_T = bits(conv.io.intExceptionFlags, 2, 2) node _invalid_T_1 = bits(narrow.io.intExceptionFlags, 1, 1) node invalid = or(_invalid_T, _invalid_T_1) when invalid : node _toint_T_10 = shr(conv.io.out, 32) node _toint_T_11 = cat(_toint_T_10, excOut) connect toint, _toint_T_11 node _io_out_bits_exc_T_4 = eq(invalid, UInt<1>(0h0)) node _io_out_bits_exc_T_5 = bits(conv.io.intExceptionFlags, 0, 0) node _io_out_bits_exc_T_6 = and(_io_out_bits_exc_T_4, _io_out_bits_exc_T_5) node io_out_bits_exc_hi_1 = cat(invalid, UInt<3>(0h0)) node _io_out_bits_exc_T_7 = cat(io_out_bits_exc_hi_1, _io_out_bits_exc_T_6) connect io.out.bits.exc, _io_out_bits_exc_T_7 connect io.out.valid, valid node _io_out_bits_lt_T = asSInt(dcmp.io.a) node _io_out_bits_lt_T_1 = lt(_io_out_bits_lt_T, asSInt(UInt<1>(0h0))) node _io_out_bits_lt_T_2 = asSInt(dcmp.io.b) node _io_out_bits_lt_T_3 = geq(_io_out_bits_lt_T_2, asSInt(UInt<1>(0h0))) node _io_out_bits_lt_T_4 = and(_io_out_bits_lt_T_1, _io_out_bits_lt_T_3) node _io_out_bits_lt_T_5 = or(dcmp.io.lt, _io_out_bits_lt_T_4) connect io.out.bits.lt, _io_out_bits_lt_T_5 connect io.out.bits.in, in
module FPToInt( // @[FPU.scala:453:7] input clock, // @[FPU.scala:453:7] input reset, // @[FPU.scala:453:7] input io_in_valid, // @[FPU.scala:461:14] input io_in_bits_ldst, // @[FPU.scala:461:14] input io_in_bits_wen, // @[FPU.scala:461:14] input io_in_bits_ren1, // @[FPU.scala:461:14] input io_in_bits_ren2, // @[FPU.scala:461:14] input io_in_bits_ren3, // @[FPU.scala:461:14] input io_in_bits_swap12, // @[FPU.scala:461:14] input io_in_bits_swap23, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:461:14] input io_in_bits_fromint, // @[FPU.scala:461:14] input io_in_bits_toint, // @[FPU.scala:461:14] input io_in_bits_fastpipe, // @[FPU.scala:461:14] input io_in_bits_fma, // @[FPU.scala:461:14] input io_in_bits_div, // @[FPU.scala:461:14] input io_in_bits_sqrt, // @[FPU.scala:461:14] input io_in_bits_wflags, // @[FPU.scala:461:14] input io_in_bits_vec, // @[FPU.scala:461:14] input [2:0] io_in_bits_rm, // @[FPU.scala:461:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:461:14] input [1:0] io_in_bits_typ, // @[FPU.scala:461:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:461:14] input [64:0] io_in_bits_in1, // @[FPU.scala:461:14] input [64:0] io_in_bits_in2, // @[FPU.scala:461:14] input [64:0] io_in_bits_in3, // @[FPU.scala:461:14] output [2:0] io_out_bits_in_rm, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in1, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in2, // @[FPU.scala:461:14] output io_out_bits_lt, // @[FPU.scala:461:14] output [63:0] io_out_bits_store, // @[FPU.scala:461:14] output [63:0] io_out_bits_toint, // @[FPU.scala:461:14] output [4:0] io_out_bits_exc // @[FPU.scala:461:14] ); wire [2:0] _narrow_io_intExceptionFlags; // @[FPU.scala:508:30] wire [63:0] _conv_io_out; // @[FPU.scala:498:24] wire [2:0] _conv_io_intExceptionFlags; // @[FPU.scala:498:24] wire _dcmp_io_lt; // @[FPU.scala:469:20] wire _dcmp_io_eq; // @[FPU.scala:469:20] wire [4:0] _dcmp_io_exceptionFlags; // @[FPU.scala:469:20] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:453:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:453:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:453:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:453:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:453:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:453:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:453:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:453:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:453:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:453:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:453:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:453:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:453:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:453:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:453:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:453:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:453:7] wire _io_out_bits_lt_T_5; // @[FPU.scala:524:32] wire [63:0] _io_out_bits_store_T_29; // @[package.scala:39:76] wire [63:0] _io_out_bits_toint_T_6; // @[package.scala:39:76] wire io_out_bits_in_ldst; // @[FPU.scala:453:7] wire io_out_bits_in_wen; // @[FPU.scala:453:7] wire io_out_bits_in_ren1; // @[FPU.scala:453:7] wire io_out_bits_in_ren2; // @[FPU.scala:453:7] wire io_out_bits_in_ren3; // @[FPU.scala:453:7] wire io_out_bits_in_swap12; // @[FPU.scala:453:7] wire io_out_bits_in_swap23; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagIn; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagOut; // @[FPU.scala:453:7] wire io_out_bits_in_fromint; // @[FPU.scala:453:7] wire io_out_bits_in_toint; // @[FPU.scala:453:7] wire io_out_bits_in_fastpipe; // @[FPU.scala:453:7] wire io_out_bits_in_fma; // @[FPU.scala:453:7] wire io_out_bits_in_div; // @[FPU.scala:453:7] wire io_out_bits_in_sqrt; // @[FPU.scala:453:7] wire io_out_bits_in_wflags; // @[FPU.scala:453:7] wire io_out_bits_in_vec; // @[FPU.scala:453:7] wire [2:0] io_out_bits_in_rm_0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmaCmd; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typ; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmt; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in1_0; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in2_0; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in3; // @[FPU.scala:453:7] wire io_out_bits_lt_0; // @[FPU.scala:453:7] wire [63:0] io_out_bits_store_0; // @[FPU.scala:453:7] wire [63:0] io_out_bits_toint_0; // @[FPU.scala:453:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:453:7] wire io_out_valid; // @[FPU.scala:453:7] reg in_ldst; // @[FPU.scala:466:21] assign io_out_bits_in_ldst = in_ldst; // @[FPU.scala:453:7, :466:21] reg in_wen; // @[FPU.scala:466:21] assign io_out_bits_in_wen = in_wen; // @[FPU.scala:453:7, :466:21] reg in_ren1; // @[FPU.scala:466:21] assign io_out_bits_in_ren1 = in_ren1; // @[FPU.scala:453:7, :466:21] reg in_ren2; // @[FPU.scala:466:21] assign io_out_bits_in_ren2 = in_ren2; // @[FPU.scala:453:7, :466:21] reg in_ren3; // @[FPU.scala:466:21] assign io_out_bits_in_ren3 = in_ren3; // @[FPU.scala:453:7, :466:21] reg in_swap12; // @[FPU.scala:466:21] assign io_out_bits_in_swap12 = in_swap12; // @[FPU.scala:453:7, :466:21] reg in_swap23; // @[FPU.scala:466:21] assign io_out_bits_in_swap23 = in_swap23; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagIn; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagIn = in_typeTagIn; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagOut; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagOut = in_typeTagOut; // @[FPU.scala:453:7, :466:21] reg in_fromint; // @[FPU.scala:466:21] assign io_out_bits_in_fromint = in_fromint; // @[FPU.scala:453:7, :466:21] reg in_toint; // @[FPU.scala:466:21] assign io_out_bits_in_toint = in_toint; // @[FPU.scala:453:7, :466:21] reg in_fastpipe; // @[FPU.scala:466:21] assign io_out_bits_in_fastpipe = in_fastpipe; // @[FPU.scala:453:7, :466:21] reg in_fma; // @[FPU.scala:466:21] assign io_out_bits_in_fma = in_fma; // @[FPU.scala:453:7, :466:21] reg in_div; // @[FPU.scala:466:21] assign io_out_bits_in_div = in_div; // @[FPU.scala:453:7, :466:21] reg in_sqrt; // @[FPU.scala:466:21] assign io_out_bits_in_sqrt = in_sqrt; // @[FPU.scala:453:7, :466:21] reg in_wflags; // @[FPU.scala:466:21] assign io_out_bits_in_wflags = in_wflags; // @[FPU.scala:453:7, :466:21] reg in_vec; // @[FPU.scala:466:21] assign io_out_bits_in_vec = in_vec; // @[FPU.scala:453:7, :466:21] reg [2:0] in_rm; // @[FPU.scala:466:21] assign io_out_bits_in_rm_0 = in_rm; // @[FPU.scala:453:7, :466:21] reg [1:0] in_fmaCmd; // @[FPU.scala:466:21] assign io_out_bits_in_fmaCmd = in_fmaCmd; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typ; // @[FPU.scala:466:21] assign io_out_bits_in_typ = in_typ; // @[FPU.scala:453:7, :466:21] reg [1:0] in_fmt; // @[FPU.scala:466:21] assign io_out_bits_in_fmt = in_fmt; // @[FPU.scala:453:7, :466:21] reg [64:0] in_in1; // @[FPU.scala:466:21] assign io_out_bits_in_in1_0 = in_in1; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T = in_in1; // @[FPU.scala:466:21, :524:46] reg [64:0] in_in2; // @[FPU.scala:466:21] assign io_out_bits_in_in2_0 = in_in2; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T_2 = in_in2; // @[FPU.scala:466:21, :524:72] reg [64:0] in_in3; // @[FPU.scala:466:21] assign io_out_bits_in_in3 = in_in3; // @[FPU.scala:453:7, :466:21] reg valid; // @[FPU.scala:467:22] assign io_out_valid = valid; // @[FPU.scala:453:7, :467:22] wire _dcmp_io_signaling_T = in_rm[1]; // @[FPU.scala:466:21, :472:30] wire _dcmp_io_signaling_T_1 = ~_dcmp_io_signaling_T; // @[FPU.scala:472:{24,30}] wire [11:0] toint_ieee_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] toint_ieee_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] toint_ieee_unrecoded_rawIn_exp_2 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_2 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] classify_out_expIn = in_in1[63:52]; // @[FPU.scala:276:18, :466:21] wire [11:0] classify_out_expIn_1 = in_in1[63:52]; // @[FPU.scala:276:18, :466:21] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T = toint_ieee_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero = _toint_ieee_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_isZero_0 = toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T = toint_ieee_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial = &_toint_ieee_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _toint_ieee_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire _toint_ieee_unrecoded_rawIn_out_sign_T_2 = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 = in_in1[64]; // @[FPU.scala:466:21] wire classify_out_sign = in_in1[64]; // @[FPU.scala:274:17, :466:21] wire classify_out_sign_2 = in_in1[64]; // @[FPU.scala:274:17, :466:21] wire classify_out_sign_4 = in_in1[64]; // @[FPU.scala:253:17, :466:21] wire _excSign_T = in_in1[64]; // @[FPU.scala:466:21, :513:31] assign toint_ieee_unrecoded_rawIn_sign = _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T = ~toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_10 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_10 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] classify_out_fractIn = in_in1[51:0]; // @[FPU.scala:275:20, :466:21] wire [51:0] classify_out_fractIn_1 = in_in1[51:0]; // @[FPU.scala:275:20, :466:21] assign _toint_ieee_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal = $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T = toint_ieee_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist = _toint_ieee_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T = toint_ieee_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_1 = _toint_ieee_unrecoded_denormFract_T >> toint_ieee_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract = _toint_ieee_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T = toint_ieee_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_2 = _toint_ieee_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_3 = toint_ieee_unrecoded_isSubnormal ? 11'h0 : _toint_ieee_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_4 = toint_ieee_unrecoded_rawIn_isNaN | toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_5 = {11{_toint_ieee_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut = _toint_ieee_unrecoded_expOut_T_3 | _toint_ieee_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T = toint_ieee_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_1 = toint_ieee_unrecoded_rawIn_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut = toint_ieee_unrecoded_isSubnormal ? toint_ieee_unrecoded_denormFract : _toint_ieee_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi = {toint_ieee_unrecoded_rawIn_sign, toint_ieee_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded = {toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_6 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T_6 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _toint_ieee_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _toint_ieee_prevRecoded_T_7 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_7 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_8 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_8 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [1:0] toint_ieee_prevRecoded_hi = {_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded = {toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp = toint_ieee_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T = toint_ieee_prevRecoded[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = toint_ieee_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut = toint_ieee_prevUnrecoded_unrecoded_isSubnormal ? toint_ieee_prevUnrecoded_unrecoded_denormFract : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi = {toint_ieee_prevUnrecoded_unrecoded_rawIn_sign, toint_ieee_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded = {toint_ieee_prevUnrecoded_unrecoded_hi, toint_ieee_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T = toint_ieee_prevRecoded[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_1 = toint_ieee_prevRecoded[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_2 = toint_ieee_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi = {_toint_ieee_prevUnrecoded_prevRecoded_T, _toint_ieee_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded = {toint_ieee_prevUnrecoded_prevRecoded_hi, _toint_ieee_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp = toint_ieee_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = toint_ieee_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = toint_ieee_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded = {toint_ieee_prevUnrecoded_prevUnrecoded_hi, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T = toint_ieee_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_1 = toint_ieee_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_2 = &_toint_ieee_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_3 = toint_ieee_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_4 = _toint_ieee_prevUnrecoded_T_2 ? toint_ieee_prevUnrecoded_prevUnrecoded : _toint_ieee_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded = {_toint_ieee_prevUnrecoded_T, _toint_ieee_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T = toint_ieee_unrecoded[63:32]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _toint_ieee_T_12 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _toint_ieee_T_20 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_10 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_18 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] classify_out_code_2 = in_in1[63:61]; // @[FPU.scala:249:25, :254:17, :466:21] wire [2:0] _excSign_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire _toint_ieee_T_2 = &_toint_ieee_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_3 = toint_ieee_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_4 = _toint_ieee_T_2 ? toint_ieee_prevUnrecoded : _toint_ieee_T_3; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_5 = {_toint_ieee_T, _toint_ieee_T_4}; // @[FPU.scala:446:{10,21,44}] wire [15:0] _toint_ieee_T_6 = _toint_ieee_T_5[15:0]; // @[FPU.scala:446:10, :475:107] wire _toint_ieee_T_7 = _toint_ieee_T_6[15]; // @[package.scala:132:38] wire [15:0] _toint_ieee_T_8 = {16{_toint_ieee_T_7}}; // @[package.scala:132:{20,38}] wire [31:0] _toint_ieee_T_9 = {_toint_ieee_T_8, _toint_ieee_T_6}; // @[package.scala:132:{15,20}] wire [63:0] _toint_ieee_T_10 = {2{_toint_ieee_T_9}}; // @[package.scala:132:15] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero_1 = _toint_ieee_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_1_isZero = toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_1_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_1_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign toint_ieee_unrecoded_rawIn_1_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_1_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _toint_ieee_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_1_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal_1 = $signed(toint_ieee_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_2 = toint_ieee_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist_1 = _toint_ieee_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T_2 = toint_ieee_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_3 = _toint_ieee_unrecoded_denormFract_T_2 >> toint_ieee_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract_1 = _toint_ieee_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T_6 = toint_ieee_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_8 = _toint_ieee_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_9 = toint_ieee_unrecoded_isSubnormal_1 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_10 = toint_ieee_unrecoded_rawIn_1_isNaN | toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_11 = {11{_toint_ieee_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut_1 = _toint_ieee_unrecoded_expOut_T_9 | _toint_ieee_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T_2 = toint_ieee_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_3 = toint_ieee_unrecoded_rawIn_1_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut_1 = toint_ieee_unrecoded_isSubnormal_1 ? toint_ieee_unrecoded_denormFract_1 : _toint_ieee_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi_1 = {toint_ieee_unrecoded_rawIn_1_sign, toint_ieee_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded_1 = {toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] toint_ieee_prevRecoded_hi_1 = {_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded_1 = {toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1 = toint_ieee_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = toint_ieee_prevRecoded_1[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = toint_ieee_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut_1 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_unrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi_1 = {toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded_1 = {toint_ieee_prevUnrecoded_unrecoded_hi_1, toint_ieee_prevUnrecoded_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T_3 = toint_ieee_prevRecoded_1[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_4 = toint_ieee_prevRecoded_1[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_5 = toint_ieee_prevRecoded_1[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi_1 = {_toint_ieee_prevUnrecoded_prevRecoded_T_3, _toint_ieee_prevUnrecoded_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded_1 = {toint_ieee_prevUnrecoded_prevRecoded_hi_1, _toint_ieee_prevUnrecoded_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = toint_ieee_prevUnrecoded_prevRecoded_1[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = toint_ieee_prevUnrecoded_prevRecoded_1[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = toint_ieee_prevUnrecoded_prevRecoded_1[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi_1 = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded_1 = {toint_ieee_prevUnrecoded_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T_5 = toint_ieee_prevUnrecoded_unrecoded_1[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_6 = toint_ieee_prevRecoded_1[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_7 = &_toint_ieee_prevUnrecoded_T_6; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_8 = toint_ieee_prevUnrecoded_unrecoded_1[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_9 = _toint_ieee_prevUnrecoded_T_7 ? toint_ieee_prevUnrecoded_prevUnrecoded_1 : _toint_ieee_prevUnrecoded_T_8; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded_1 = {_toint_ieee_prevUnrecoded_T_5, _toint_ieee_prevUnrecoded_T_9}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_11 = toint_ieee_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _toint_ieee_T_13 = &_toint_ieee_T_12; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_14 = toint_ieee_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_15 = _toint_ieee_T_13 ? toint_ieee_prevUnrecoded_1 : _toint_ieee_T_14; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_16 = {_toint_ieee_T_11, _toint_ieee_T_15}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_17 = _toint_ieee_T_16[31:0]; // @[FPU.scala:446:10, :476:109] wire [63:0] _toint_ieee_T_18 = {2{_toint_ieee_T_17}}; // @[FPU.scala:476:{63,109}] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_2 = toint_ieee_unrecoded_rawIn_exp_2[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero_2 = _toint_ieee_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_2_isZero = toint_ieee_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_2 = toint_ieee_unrecoded_rawIn_exp_2[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial_2 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_4 = toint_ieee_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_6 = toint_ieee_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_2 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_2_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_8 = toint_ieee_unrecoded_rawIn_isSpecial_2 & _toint_ieee_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_2_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign toint_ieee_unrecoded_rawIn_2_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_2_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T_8 = ~toint_ieee_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _toint_ieee_unrecoded_rawIn_out_sig_T_11 = {_toint_ieee_unrecoded_rawIn_out_sig_T_9, _toint_ieee_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_2_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal_2 = $signed(toint_ieee_unrecoded_rawIn_2_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_4 = toint_ieee_unrecoded_rawIn_2_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_5 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist_2 = _toint_ieee_unrecoded_denormShiftDist_T_5[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T_4 = toint_ieee_unrecoded_rawIn_2_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_5 = _toint_ieee_unrecoded_denormFract_T_4 >> toint_ieee_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract_2 = _toint_ieee_unrecoded_denormFract_T_5[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T_12 = toint_ieee_unrecoded_rawIn_2_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_13 = {1'h0, _toint_ieee_unrecoded_expOut_T_12} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_14 = _toint_ieee_unrecoded_expOut_T_13[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_15 = toint_ieee_unrecoded_isSubnormal_2 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_16 = toint_ieee_unrecoded_rawIn_2_isNaN | toint_ieee_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_17 = {11{_toint_ieee_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut_2 = _toint_ieee_unrecoded_expOut_T_15 | _toint_ieee_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T_4 = toint_ieee_unrecoded_rawIn_2_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_5 = toint_ieee_unrecoded_rawIn_2_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut_2 = toint_ieee_unrecoded_isSubnormal_2 ? toint_ieee_unrecoded_denormFract_2 : _toint_ieee_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi_2 = {toint_ieee_unrecoded_rawIn_2_sign, toint_ieee_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded_2 = {toint_ieee_unrecoded_hi_2, toint_ieee_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] toint_ieee_prevRecoded_hi_2 = {_toint_ieee_prevRecoded_T_6, _toint_ieee_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded_2 = {toint_ieee_prevRecoded_hi_2, _toint_ieee_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2 = toint_ieee_prevRecoded_2[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isZero = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = toint_ieee_prevRecoded_2[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = toint_ieee_prevRecoded_2[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2 = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract_2 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_16 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut_2 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? toint_ieee_prevUnrecoded_unrecoded_denormFract_2 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi_2 = {toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign, toint_ieee_prevUnrecoded_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded_2 = {toint_ieee_prevUnrecoded_unrecoded_hi_2, toint_ieee_prevUnrecoded_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T_6 = toint_ieee_prevRecoded_2[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_7 = toint_ieee_prevRecoded_2[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_8 = toint_ieee_prevRecoded_2[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi_2 = {_toint_ieee_prevUnrecoded_prevRecoded_T_6, _toint_ieee_prevUnrecoded_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded_2 = {toint_ieee_prevUnrecoded_prevRecoded_hi_2, _toint_ieee_prevUnrecoded_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = toint_ieee_prevUnrecoded_prevRecoded_2[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isZero = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = toint_ieee_prevUnrecoded_prevRecoded_2[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = toint_ieee_prevUnrecoded_prevRecoded_2[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi_2 = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded_2 = {toint_ieee_prevUnrecoded_prevUnrecoded_hi_2, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T_10 = toint_ieee_prevUnrecoded_unrecoded_2[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_11 = toint_ieee_prevRecoded_2[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_12 = &_toint_ieee_prevUnrecoded_T_11; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_13 = toint_ieee_prevUnrecoded_unrecoded_2[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_14 = _toint_ieee_prevUnrecoded_T_12 ? toint_ieee_prevUnrecoded_prevUnrecoded_2 : _toint_ieee_prevUnrecoded_T_13; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded_2 = {_toint_ieee_prevUnrecoded_T_10, _toint_ieee_prevUnrecoded_T_14}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_19 = toint_ieee_unrecoded_2[63:32]; // @[FPU.scala:446:21] wire _toint_ieee_T_21 = &_toint_ieee_T_20; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_22 = toint_ieee_unrecoded_2[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_23 = _toint_ieee_T_21 ? toint_ieee_prevUnrecoded_2 : _toint_ieee_T_22; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_24 = {_toint_ieee_T_19, _toint_ieee_T_23}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _toint_ieee_T_25 = _toint_ieee_T_24; // @[FPU.scala:446:10, :476:109] wire _GEN = in_typeTagOut == 2'h1; // @[package.scala:39:86] wire _toint_ieee_T_26; // @[package.scala:39:86] assign _toint_ieee_T_26 = _GEN; // @[package.scala:39:86] wire _io_out_bits_store_T_24; // @[package.scala:39:86] assign _io_out_bits_store_T_24 = _GEN; // @[package.scala:39:86] wire _classify_out_T_41; // @[package.scala:39:86] assign _classify_out_T_41 = _GEN; // @[package.scala:39:86] wire [63:0] _toint_ieee_T_27 = _toint_ieee_T_26 ? _toint_ieee_T_18 : _toint_ieee_T_10; // @[package.scala:39:{76,86}] wire _GEN_0 = in_typeTagOut == 2'h2; // @[package.scala:39:86] wire _toint_ieee_T_28; // @[package.scala:39:86] assign _toint_ieee_T_28 = _GEN_0; // @[package.scala:39:86] wire _io_out_bits_store_T_26; // @[package.scala:39:86] assign _io_out_bits_store_T_26 = _GEN_0; // @[package.scala:39:86] wire _classify_out_T_43; // @[package.scala:39:86] assign _classify_out_T_43 = _GEN_0; // @[package.scala:39:86] wire [63:0] _toint_ieee_T_29 = _toint_ieee_T_28 ? _toint_ieee_T_25 : _toint_ieee_T_27; // @[package.scala:39:{76,86}] wire _toint_ieee_T_30 = &in_typeTagOut; // @[package.scala:39:86] wire [63:0] toint_ieee = _toint_ieee_T_30 ? _toint_ieee_T_25 : _toint_ieee_T_29; // @[package.scala:39:{76,86}] wire [63:0] toint; // @[FPU.scala:478:26] wire [63:0] _io_out_bits_toint_T_4 = toint; // @[FPU.scala:478:26, :481:59] wire _intType_T = in_fmt[0]; // @[FPU.scala:466:21, :479:35] wire intType; // @[FPU.scala:479:28] wire _io_out_bits_toint_T_5 = intType; // @[package.scala:39:86] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T = io_out_bits_store_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero = _io_out_bits_store_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_isZero_0 = io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T = io_out_bits_store_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal = $signed(io_out_bits_store_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T = io_out_bits_store_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist = _io_out_bits_store_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T = io_out_bits_store_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_1 = _io_out_bits_store_unrecoded_denormFract_T >> io_out_bits_store_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract = _io_out_bits_store_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T = io_out_bits_store_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_2 = _io_out_bits_store_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_3 = io_out_bits_store_unrecoded_isSubnormal ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_4 = io_out_bits_store_unrecoded_rawIn_isNaN | io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_5 = {11{_io_out_bits_store_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut = _io_out_bits_store_unrecoded_expOut_T_3 | _io_out_bits_store_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T = io_out_bits_store_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_1 = io_out_bits_store_unrecoded_rawIn_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut = io_out_bits_store_unrecoded_isSubnormal ? io_out_bits_store_unrecoded_denormFract : _io_out_bits_store_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi = {io_out_bits_store_unrecoded_rawIn_sign, io_out_bits_store_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded = {io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi = {_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded = {io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp = io_out_bits_store_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T = io_out_bits_store_prevRecoded[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded = {io_out_bits_store_prevUnrecoded_unrecoded_hi, io_out_bits_store_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T = io_out_bits_store_prevRecoded[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_1 = io_out_bits_store_prevRecoded[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_2 = io_out_bits_store_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi = {_io_out_bits_store_prevUnrecoded_prevRecoded_T, _io_out_bits_store_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded = {io_out_bits_store_prevUnrecoded_prevRecoded_hi, _io_out_bits_store_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp = io_out_bits_store_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = io_out_bits_store_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T = io_out_bits_store_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_1 = io_out_bits_store_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_2 = &_io_out_bits_store_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_3 = io_out_bits_store_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_4 = _io_out_bits_store_prevUnrecoded_T_2 ? io_out_bits_store_prevUnrecoded_prevUnrecoded : _io_out_bits_store_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded = {_io_out_bits_store_prevUnrecoded_T, _io_out_bits_store_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T = io_out_bits_store_unrecoded[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_2 = &_io_out_bits_store_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_3 = io_out_bits_store_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_4 = _io_out_bits_store_T_2 ? io_out_bits_store_prevUnrecoded : _io_out_bits_store_T_3; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_5 = {_io_out_bits_store_T, _io_out_bits_store_T_4}; // @[FPU.scala:446:{10,21,44}] wire [15:0] _io_out_bits_store_T_6 = _io_out_bits_store_T_5[15:0]; // @[FPU.scala:446:10, :480:82] wire [31:0] _io_out_bits_store_T_7 = {2{_io_out_bits_store_T_6}}; // @[FPU.scala:480:{49,82}] wire [63:0] _io_out_bits_store_T_8 = {2{_io_out_bits_store_T_7}}; // @[FPU.scala:480:49] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero_1 = _io_out_bits_store_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_1_isZero = io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_1_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_1_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_1_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_1_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_1_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_2 = io_out_bits_store_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_1 = _io_out_bits_store_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_3 = _io_out_bits_store_unrecoded_denormFract_T_2 >> io_out_bits_store_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract_1 = _io_out_bits_store_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_6 = io_out_bits_store_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_8 = _io_out_bits_store_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_9 = io_out_bits_store_unrecoded_isSubnormal_1 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_10 = io_out_bits_store_unrecoded_rawIn_1_isNaN | io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_11 = {11{_io_out_bits_store_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut_1 = _io_out_bits_store_unrecoded_expOut_T_9 | _io_out_bits_store_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_3 = io_out_bits_store_unrecoded_rawIn_1_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut_1 = io_out_bits_store_unrecoded_isSubnormal_1 ? io_out_bits_store_unrecoded_denormFract_1 : _io_out_bits_store_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi_1 = {io_out_bits_store_unrecoded_rawIn_1_sign, io_out_bits_store_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded_1 = {io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi_1 = {_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded_1 = {io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1 = io_out_bits_store_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevRecoded_1[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded_1 = {io_out_bits_store_prevUnrecoded_unrecoded_hi_1, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_3 = io_out_bits_store_prevRecoded_1[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_4 = io_out_bits_store_prevRecoded_1[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_5 = io_out_bits_store_prevRecoded_1[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi_1 = {_io_out_bits_store_prevUnrecoded_prevRecoded_T_3, _io_out_bits_store_prevUnrecoded_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded_1 = {io_out_bits_store_prevUnrecoded_prevRecoded_hi_1, _io_out_bits_store_prevUnrecoded_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = io_out_bits_store_prevUnrecoded_prevRecoded_1[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevUnrecoded_prevRecoded_1[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevUnrecoded_prevRecoded_1[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_1 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_1[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_6 = io_out_bits_store_prevRecoded_1[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_7 = &_io_out_bits_store_prevUnrecoded_T_6; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_8 = io_out_bits_store_prevUnrecoded_unrecoded_1[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_9 = _io_out_bits_store_prevUnrecoded_T_7 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_1 : _io_out_bits_store_prevUnrecoded_T_8; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded_1 = {_io_out_bits_store_prevUnrecoded_T_5, _io_out_bits_store_prevUnrecoded_T_9}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_9 = io_out_bits_store_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_11 = &_io_out_bits_store_T_10; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_12 = io_out_bits_store_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_13 = _io_out_bits_store_T_11 ? io_out_bits_store_prevUnrecoded_1 : _io_out_bits_store_T_12; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_14 = {_io_out_bits_store_T_9, _io_out_bits_store_T_13}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_15 = _io_out_bits_store_T_14[31:0]; // @[FPU.scala:446:10, :480:82] wire [63:0] _io_out_bits_store_T_16 = {2{_io_out_bits_store_T_15}}; // @[FPU.scala:480:{49,82}] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_2 = io_out_bits_store_unrecoded_rawIn_exp_2[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero_2 = _io_out_bits_store_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_2_isZero = io_out_bits_store_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_unrecoded_rawIn_exp_2[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_2_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_2_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_2_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_2_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_2_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal_2 = $signed(io_out_bits_store_unrecoded_rawIn_2_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_4 = io_out_bits_store_unrecoded_rawIn_2_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_5 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_2 = _io_out_bits_store_unrecoded_denormShiftDist_T_5[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_4 = io_out_bits_store_unrecoded_rawIn_2_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_5 = _io_out_bits_store_unrecoded_denormFract_T_4 >> io_out_bits_store_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract_2 = _io_out_bits_store_unrecoded_denormFract_T_5[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_12 = io_out_bits_store_unrecoded_rawIn_2_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_12} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_14 = _io_out_bits_store_unrecoded_expOut_T_13[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_15 = io_out_bits_store_unrecoded_isSubnormal_2 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_16 = io_out_bits_store_unrecoded_rawIn_2_isNaN | io_out_bits_store_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_17 = {11{_io_out_bits_store_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut_2 = _io_out_bits_store_unrecoded_expOut_T_15 | _io_out_bits_store_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_4 = io_out_bits_store_unrecoded_rawIn_2_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_5 = io_out_bits_store_unrecoded_rawIn_2_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut_2 = io_out_bits_store_unrecoded_isSubnormal_2 ? io_out_bits_store_unrecoded_denormFract_2 : _io_out_bits_store_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi_2 = {io_out_bits_store_unrecoded_rawIn_2_sign, io_out_bits_store_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded_2 = {io_out_bits_store_unrecoded_hi_2, io_out_bits_store_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi_2 = {_io_out_bits_store_prevRecoded_T_6, _io_out_bits_store_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded_2 = {io_out_bits_store_prevRecoded_hi_2, _io_out_bits_store_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2 = io_out_bits_store_prevRecoded_2[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isZero = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = io_out_bits_store_prevRecoded_2[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = io_out_bits_store_prevRecoded_2[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2 = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut_2 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi_2 = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded_2 = {io_out_bits_store_prevUnrecoded_unrecoded_hi_2, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_6 = io_out_bits_store_prevRecoded_2[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_7 = io_out_bits_store_prevRecoded_2[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_8 = io_out_bits_store_prevRecoded_2[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi_2 = {_io_out_bits_store_prevUnrecoded_prevRecoded_T_6, _io_out_bits_store_prevUnrecoded_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded_2 = {io_out_bits_store_prevUnrecoded_prevRecoded_hi_2, _io_out_bits_store_prevUnrecoded_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = io_out_bits_store_prevUnrecoded_prevRecoded_2[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isZero = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = io_out_bits_store_prevUnrecoded_prevRecoded_2[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = io_out_bits_store_prevUnrecoded_prevRecoded_2[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_2 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T_10 = io_out_bits_store_prevUnrecoded_unrecoded_2[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_11 = io_out_bits_store_prevRecoded_2[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_12 = &_io_out_bits_store_prevUnrecoded_T_11; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_13 = io_out_bits_store_prevUnrecoded_unrecoded_2[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_14 = _io_out_bits_store_prevUnrecoded_T_12 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_2 : _io_out_bits_store_prevUnrecoded_T_13; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded_2 = {_io_out_bits_store_prevUnrecoded_T_10, _io_out_bits_store_prevUnrecoded_T_14}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_17 = io_out_bits_store_unrecoded_2[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_19 = &_io_out_bits_store_T_18; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_20 = io_out_bits_store_unrecoded_2[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_21 = _io_out_bits_store_T_19 ? io_out_bits_store_prevUnrecoded_2 : _io_out_bits_store_T_20; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_22 = {_io_out_bits_store_T_17, _io_out_bits_store_T_21}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _io_out_bits_store_T_23 = _io_out_bits_store_T_22; // @[FPU.scala:446:10, :480:82] wire [63:0] _io_out_bits_store_T_25 = _io_out_bits_store_T_24 ? _io_out_bits_store_T_16 : _io_out_bits_store_T_8; // @[package.scala:39:{76,86}] wire [63:0] _io_out_bits_store_T_27 = _io_out_bits_store_T_26 ? _io_out_bits_store_T_23 : _io_out_bits_store_T_25; // @[package.scala:39:{76,86}] wire _io_out_bits_store_T_28 = &in_typeTagOut; // @[package.scala:39:86] assign _io_out_bits_store_T_29 = _io_out_bits_store_T_28 ? _io_out_bits_store_T_23 : _io_out_bits_store_T_27; // @[package.scala:39:{76,86}] assign io_out_bits_store_0 = _io_out_bits_store_T_29; // @[package.scala:39:76] wire [31:0] _io_out_bits_toint_T = toint[31:0]; // @[FPU.scala:478:26, :481:59] wire _io_out_bits_toint_T_1 = _io_out_bits_toint_T[31]; // @[package.scala:132:38] wire [31:0] _io_out_bits_toint_T_2 = {32{_io_out_bits_toint_T_1}}; // @[package.scala:132:{20,38}] wire [63:0] _io_out_bits_toint_T_3 = {_io_out_bits_toint_T_2, _io_out_bits_toint_T}; // @[package.scala:132:{15,20}] assign _io_out_bits_toint_T_6 = _io_out_bits_toint_T_5 ? _io_out_bits_toint_T_4 : _io_out_bits_toint_T_3; // @[package.scala:39:{76,86}, :132:15] assign io_out_bits_toint_0 = _io_out_bits_toint_T_6; // @[package.scala:39:76] wire [62:0] _classify_out_fractOut_T = {classify_out_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] classify_out_fractOut = _classify_out_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] classify_out_expOut_expCode = classify_out_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _classify_out_expOut_commonCase_T = {1'h0, classify_out_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _classify_out_expOut_commonCase_T_1 = _classify_out_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _classify_out_expOut_commonCase_T_2 = {1'h0, _classify_out_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] classify_out_expOut_commonCase = _classify_out_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _classify_out_expOut_T = classify_out_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _classify_out_expOut_T_1 = classify_out_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _classify_out_expOut_T_2 = _classify_out_expOut_T | _classify_out_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _classify_out_expOut_T_3 = classify_out_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _classify_out_expOut_T_4 = {classify_out_expOut_expCode, _classify_out_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _classify_out_expOut_T_5 = classify_out_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] classify_out_expOut = _classify_out_expOut_T_2 ? _classify_out_expOut_T_4 : _classify_out_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] classify_out_hi = {classify_out_sign, classify_out_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] _classify_out_T = {classify_out_hi, classify_out_fractOut}; // @[FPU.scala:277:38, :283:8] wire classify_out_sign_1 = _classify_out_T[16]; // @[FPU.scala:253:17, :283:8] wire [2:0] classify_out_code = _classify_out_T[15:13]; // @[FPU.scala:254:17, :283:8] wire [1:0] classify_out_codeHi = classify_out_code[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial = &classify_out_codeHi; // @[FPU.scala:255:22, :256:28] wire [3:0] _classify_out_isHighSubnormalIn_T = _classify_out_T[13:10]; // @[FPU.scala:258:30, :283:8] wire classify_out_isHighSubnormalIn = _classify_out_isHighSubnormalIn_T < 4'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T = classify_out_code == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_1 = classify_out_codeHi == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_1; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_1 = _GEN_1; // @[FPU.scala:259:46] wire _classify_out_isNormal_T; // @[FPU.scala:260:27] assign _classify_out_isNormal_T = _GEN_1; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_2 = _classify_out_isSubnormal_T_1 & classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal = _classify_out_isSubnormal_T | _classify_out_isSubnormal_T_2; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_1 = ~classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_2 = _classify_out_isNormal_T & _classify_out_isNormal_T_1; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_3 = classify_out_codeHi == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal = _classify_out_isNormal_T_2 | _classify_out_isNormal_T_3; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero = classify_out_code == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T = classify_out_code[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_1 = ~_classify_out_isInf_T; // @[FPU.scala:262:{30,35}] wire classify_out_isInf = classify_out_isSpecial & _classify_out_isInf_T_1; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN = &classify_out_code; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T = _classify_out_T[9]; // @[FPU.scala:264:29, :283:8] wire _classify_out_isQNaN_T = _classify_out_T[9]; // @[FPU.scala:264:29, :265:28, :283:8] wire _classify_out_isSNaN_T_1 = ~_classify_out_isSNaN_T; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN = classify_out_isNaN & _classify_out_isSNaN_T_1; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN = classify_out_isNaN & _classify_out_isQNaN_T; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_1 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_2 = classify_out_isInf & _classify_out_T_1; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_3 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_4 = classify_out_isNormal & _classify_out_T_3; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_5 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_6 = classify_out_isSubnormal & _classify_out_T_5; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_7 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_8 = classify_out_isZero & _classify_out_T_7; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_9 = classify_out_isZero & classify_out_sign_1; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_10 = classify_out_isSubnormal & classify_out_sign_1; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_11 = classify_out_isNormal & classify_out_sign_1; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_12 = classify_out_isInf & classify_out_sign_1; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo = {_classify_out_T_11, _classify_out_T_12}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi = {_classify_out_T_8, _classify_out_T_9}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi = {classify_out_lo_hi_hi, _classify_out_T_10}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo = {classify_out_lo_hi, classify_out_lo_lo}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo = {_classify_out_T_4, _classify_out_T_6}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi = {classify_out_isQNaN, classify_out_isSNaN}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi = {classify_out_hi_hi_hi, _classify_out_T_2}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_1 = {classify_out_hi_hi, classify_out_hi_lo}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_13 = {classify_out_hi_1, classify_out_lo}; // @[FPU.scala:267:8] wire [75:0] _classify_out_fractOut_T_1 = {classify_out_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] classify_out_fractOut_1 = _classify_out_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] classify_out_expOut_expCode_1 = classify_out_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _classify_out_expOut_commonCase_T_3 = {1'h0, classify_out_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _classify_out_expOut_commonCase_T_4 = _classify_out_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31] wire [12:0] _classify_out_expOut_commonCase_T_5 = {1'h0, _classify_out_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] classify_out_expOut_commonCase_1 = _classify_out_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50] wire _classify_out_expOut_T_6 = classify_out_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19] wire _classify_out_expOut_T_7 = classify_out_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38] wire _classify_out_expOut_T_8 = _classify_out_expOut_T_6 | _classify_out_expOut_T_7; // @[FPU.scala:281:{19,27,38}] wire [5:0] _classify_out_expOut_T_9 = classify_out_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _classify_out_expOut_T_10 = {classify_out_expOut_expCode_1, _classify_out_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _classify_out_expOut_T_11 = classify_out_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] classify_out_expOut_1 = _classify_out_expOut_T_8 ? _classify_out_expOut_T_10 : _classify_out_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] classify_out_hi_2 = {classify_out_sign_2, classify_out_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] _classify_out_T_14 = {classify_out_hi_2, classify_out_fractOut_1}; // @[FPU.scala:277:38, :283:8] wire classify_out_sign_3 = _classify_out_T_14[32]; // @[FPU.scala:253:17, :283:8] wire [2:0] classify_out_code_1 = _classify_out_T_14[31:29]; // @[FPU.scala:254:17, :283:8] wire [1:0] classify_out_codeHi_1 = classify_out_code_1[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial_1 = &classify_out_codeHi_1; // @[FPU.scala:255:22, :256:28] wire [6:0] _classify_out_isHighSubnormalIn_T_1 = _classify_out_T_14[29:23]; // @[FPU.scala:258:30, :283:8] wire classify_out_isHighSubnormalIn_1 = _classify_out_isHighSubnormalIn_T_1 < 7'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T_3 = classify_out_code_1 == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_2 = classify_out_codeHi_1 == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_4; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_4 = _GEN_2; // @[FPU.scala:259:46] wire _classify_out_isNormal_T_4; // @[FPU.scala:260:27] assign _classify_out_isNormal_T_4 = _GEN_2; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_5 = _classify_out_isSubnormal_T_4 & classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal_1 = _classify_out_isSubnormal_T_3 | _classify_out_isSubnormal_T_5; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_5 = ~classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_6 = _classify_out_isNormal_T_4 & _classify_out_isNormal_T_5; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_7 = classify_out_codeHi_1 == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal_1 = _classify_out_isNormal_T_6 | _classify_out_isNormal_T_7; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero_1 = classify_out_code_1 == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T_2 = classify_out_code_1[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_3 = ~_classify_out_isInf_T_2; // @[FPU.scala:262:{30,35}] wire classify_out_isInf_1 = classify_out_isSpecial_1 & _classify_out_isInf_T_3; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN_1 = &classify_out_code_1; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T_2 = _classify_out_T_14[22]; // @[FPU.scala:264:29, :283:8] wire _classify_out_isQNaN_T_1 = _classify_out_T_14[22]; // @[FPU.scala:264:29, :265:28, :283:8] wire _classify_out_isSNaN_T_3 = ~_classify_out_isSNaN_T_2; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN_1 = classify_out_isNaN_1 & _classify_out_isSNaN_T_3; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN_1 = classify_out_isNaN_1 & _classify_out_isQNaN_T_1; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_15 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_16 = classify_out_isInf_1 & _classify_out_T_15; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_17 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_18 = classify_out_isNormal_1 & _classify_out_T_17; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_19 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_20 = classify_out_isSubnormal_1 & _classify_out_T_19; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_21 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_22 = classify_out_isZero_1 & _classify_out_T_21; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_23 = classify_out_isZero_1 & classify_out_sign_3; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_24 = classify_out_isSubnormal_1 & classify_out_sign_3; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_25 = classify_out_isNormal_1 & classify_out_sign_3; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_26 = classify_out_isInf_1 & classify_out_sign_3; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo_1 = {_classify_out_T_25, _classify_out_T_26}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi_1 = {_classify_out_T_22, _classify_out_T_23}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi_1 = {classify_out_lo_hi_hi_1, _classify_out_T_24}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo_1 = {classify_out_lo_hi_1, classify_out_lo_lo_1}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo_1 = {_classify_out_T_18, _classify_out_T_20}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi_1 = {classify_out_isQNaN_1, classify_out_isSNaN_1}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi_1 = {classify_out_hi_hi_hi_1, _classify_out_T_16}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_3 = {classify_out_hi_hi_1, classify_out_hi_lo_1}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_27 = {classify_out_hi_3, classify_out_lo_1}; // @[FPU.scala:267:8] wire [1:0] classify_out_codeHi_2 = classify_out_code_2[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial_2 = &classify_out_codeHi_2; // @[FPU.scala:255:22, :256:28] wire [9:0] _classify_out_isHighSubnormalIn_T_2 = in_in1[61:52]; // @[FPU.scala:258:30, :466:21] wire classify_out_isHighSubnormalIn_2 = _classify_out_isHighSubnormalIn_T_2 < 10'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T_6 = classify_out_code_2 == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_3 = classify_out_codeHi_2 == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_7; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_7 = _GEN_3; // @[FPU.scala:259:46] wire _classify_out_isNormal_T_8; // @[FPU.scala:260:27] assign _classify_out_isNormal_T_8 = _GEN_3; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_8 = _classify_out_isSubnormal_T_7 & classify_out_isHighSubnormalIn_2; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal_2 = _classify_out_isSubnormal_T_6 | _classify_out_isSubnormal_T_8; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_9 = ~classify_out_isHighSubnormalIn_2; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_10 = _classify_out_isNormal_T_8 & _classify_out_isNormal_T_9; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_11 = classify_out_codeHi_2 == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal_2 = _classify_out_isNormal_T_10 | _classify_out_isNormal_T_11; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero_2 = classify_out_code_2 == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T_4 = classify_out_code_2[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_5 = ~_classify_out_isInf_T_4; // @[FPU.scala:262:{30,35}] wire classify_out_isInf_2 = classify_out_isSpecial_2 & _classify_out_isInf_T_5; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN_2 = &classify_out_code_2; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T_4 = in_in1[51]; // @[FPU.scala:264:29, :466:21] wire _classify_out_isQNaN_T_2 = in_in1[51]; // @[FPU.scala:264:29, :265:28, :466:21] wire _classify_out_isSNaN_T_5 = ~_classify_out_isSNaN_T_4; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN_2 = classify_out_isNaN_2 & _classify_out_isSNaN_T_5; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN_2 = classify_out_isNaN_2 & _classify_out_isQNaN_T_2; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_28 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_29 = classify_out_isInf_2 & _classify_out_T_28; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_30 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_31 = classify_out_isNormal_2 & _classify_out_T_30; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_32 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_33 = classify_out_isSubnormal_2 & _classify_out_T_32; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_34 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_35 = classify_out_isZero_2 & _classify_out_T_34; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_36 = classify_out_isZero_2 & classify_out_sign_4; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_37 = classify_out_isSubnormal_2 & classify_out_sign_4; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_38 = classify_out_isNormal_2 & classify_out_sign_4; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_39 = classify_out_isInf_2 & classify_out_sign_4; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo_2 = {_classify_out_T_38, _classify_out_T_39}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi_2 = {_classify_out_T_35, _classify_out_T_36}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi_2 = {classify_out_lo_hi_hi_2, _classify_out_T_37}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo_2 = {classify_out_lo_hi_2, classify_out_lo_lo_2}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo_2 = {_classify_out_T_31, _classify_out_T_33}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi_2 = {classify_out_isQNaN_2, classify_out_isSNaN_2}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi_2 = {classify_out_hi_hi_hi_2, _classify_out_T_29}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_4 = {classify_out_hi_hi_2, classify_out_hi_lo_2}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_40 = {classify_out_hi_4, classify_out_lo_2}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_42 = _classify_out_T_41 ? _classify_out_T_27 : _classify_out_T_13; // @[package.scala:39:{76,86}] wire [9:0] _classify_out_T_44 = _classify_out_T_43 ? _classify_out_T_40 : _classify_out_T_42; // @[package.scala:39:{76,86}] wire _classify_out_T_45 = &in_typeTagOut; // @[package.scala:39:86] wire [9:0] classify_out = _classify_out_T_45 ? _classify_out_T_40 : _classify_out_T_44; // @[package.scala:39:{76,86}] wire [31:0] _toint_T = toint_ieee[63:32]; // @[package.scala:39:76] wire [31:0] _toint_T_7 = toint_ieee[63:32]; // @[package.scala:39:76] wire [63:0] _toint_T_1 = {_toint_T, 32'h0}; // @[FPU.scala:486:{41,52}] wire [63:0] _toint_T_2 = {54'h0, classify_out} | _toint_T_1; // @[package.scala:39:76] wire [2:0] _toint_T_3 = ~in_rm; // @[FPU.scala:466:21, :491:15] wire [1:0] _toint_T_4 = {_dcmp_io_lt, _dcmp_io_eq}; // @[FPU.scala:469:20, :491:27] wire [2:0] _toint_T_5 = {1'h0, _toint_T_3[1:0] & _toint_T_4}; // @[FPU.scala:491:{15,22,27}] wire _toint_T_6 = |_toint_T_5; // @[FPU.scala:491:{22,53}] wire [63:0] _toint_T_8 = {_toint_T_7, 32'h0}; // @[FPU.scala:491:{71,82}] wire [63:0] _toint_T_9 = {63'h0, _toint_T_6} | _toint_T_8; // @[FPU.scala:491:{53,57,82}] wire cvtType = in_typ[1]; // @[package.scala:163:13] assign intType = in_wflags ? ~in_ren2 & cvtType : ~(in_rm[0]) & _intType_T; // @[package.scala:163:13] wire _conv_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35] wire _narrow_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35, :511:41] wire _conv_io_signedOut_T_1 = ~_conv_io_signedOut_T; // @[FPU.scala:501:{28,35}] wire [1:0] _io_out_bits_exc_T = _conv_io_intExceptionFlags[2:1]; // @[FPU.scala:498:24, :503:55] wire _io_out_bits_exc_T_1 = |_io_out_bits_exc_T; // @[FPU.scala:503:{55,62}] wire _io_out_bits_exc_T_2 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102] wire _io_out_bits_exc_T_5 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102, :517:90] wire [3:0] io_out_bits_exc_hi = {_io_out_bits_exc_T_1, 3'h0}; // @[FPU.scala:503:{29,62}] wire [4:0] _io_out_bits_exc_T_3 = {io_out_bits_exc_hi, _io_out_bits_exc_T_2}; // @[FPU.scala:503:{29,102}] wire _narrow_io_signedOut_T_1 = ~_narrow_io_signedOut_T; // @[FPU.scala:511:{34,41}] wire _excSign_T_2 = &_excSign_T_1; // @[FPU.scala:249:{25,56}] wire _excSign_T_3 = ~_excSign_T_2; // @[FPU.scala:249:56, :513:62] wire excSign = _excSign_T & _excSign_T_3; // @[FPU.scala:513:{31,59,62}] wire _excOut_T = _conv_io_signedOut_T_1 == excSign; // @[FPU.scala:501:28, :513:59, :514:46] wire _excOut_T_1 = ~excSign; // @[FPU.scala:513:59, :514:69] wire [30:0] _excOut_T_2 = {31{_excOut_T_1}}; // @[FPU.scala:514:{63,69}] wire [31:0] excOut = {_excOut_T, _excOut_T_2}; // @[FPU.scala:514:{27,46,63}] wire _invalid_T = _conv_io_intExceptionFlags[2]; // @[FPU.scala:498:24, :515:50] wire _invalid_T_1 = _narrow_io_intExceptionFlags[1]; // @[FPU.scala:508:30, :515:84] wire invalid = _invalid_T | _invalid_T_1; // @[FPU.scala:515:{50,54,84}] wire [31:0] _toint_T_10 = _conv_io_out[63:32]; // @[FPU.scala:498:24, :516:53] wire [63:0] _toint_T_11 = {_toint_T_10, excOut}; // @[FPU.scala:514:27, :516:{40,53}] assign toint = in_wflags ? (in_ren2 ? _toint_T_9 : ~cvtType & invalid ? _toint_T_11 : _conv_io_out) : in_rm[0] ? _toint_T_2 : toint_ieee; // @[package.scala:39:76, :163:13] wire _io_out_bits_exc_T_4 = ~invalid; // @[FPU.scala:515:54, :517:53] wire _io_out_bits_exc_T_6 = _io_out_bits_exc_T_4 & _io_out_bits_exc_T_5; // @[FPU.scala:517:{53,62,90}] wire [3:0] io_out_bits_exc_hi_1 = {invalid, 3'h0}; // @[FPU.scala:515:54, :517:33] wire [4:0] _io_out_bits_exc_T_7 = {io_out_bits_exc_hi_1, _io_out_bits_exc_T_6}; // @[FPU.scala:517:{33,62}] assign io_out_bits_exc_0 = in_wflags ? (in_ren2 ? _dcmp_io_exceptionFlags : cvtType ? _io_out_bits_exc_T_3 : _io_out_bits_exc_T_7) : 5'h0; // @[package.scala:163:13] wire _io_out_bits_lt_T_1 = $signed(_io_out_bits_lt_T) < 65'sh0; // @[FPU.scala:524:{46,53}] wire _io_out_bits_lt_T_3 = $signed(_io_out_bits_lt_T_2) > -65'sh1; // @[FPU.scala:524:{72,79}] wire _io_out_bits_lt_T_4 = _io_out_bits_lt_T_1 & _io_out_bits_lt_T_3; // @[FPU.scala:524:{53,59,79}] assign _io_out_bits_lt_T_5 = _dcmp_io_lt | _io_out_bits_lt_T_4; // @[FPU.scala:469:20, :524:{32,59}] assign io_out_bits_lt_0 = _io_out_bits_lt_T_5; // @[FPU.scala:453:7, :524:32] always @(posedge clock) begin // @[FPU.scala:453:7] if (io_in_valid_0) begin // @[FPU.scala:453:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:453:7, :466:21] in_wen <= io_in_bits_wen_0; // @[FPU.scala:453:7, :466:21] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:453:7, :466:21] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:453:7, :466:21] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:453:7, :466:21] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:453:7, :466:21] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:453:7, :466:21] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:453:7, :466:21] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:453:7, :466:21] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:453:7, :466:21] in_toint <= io_in_bits_toint_0; // @[FPU.scala:453:7, :466:21] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:453:7, :466:21] in_fma <= io_in_bits_fma_0; // @[FPU.scala:453:7, :466:21] in_div <= io_in_bits_div_0; // @[FPU.scala:453:7, :466:21] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:453:7, :466:21] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:453:7, :466:21] in_vec <= io_in_bits_vec_0; // @[FPU.scala:453:7, :466:21] in_rm <= io_in_bits_rm_0; // @[FPU.scala:453:7, :466:21] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:453:7, :466:21] in_typ <= io_in_bits_typ_0; // @[FPU.scala:453:7, :466:21] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:453:7, :466:21] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:453:7, :466:21] in_in2 <= io_in_bits_in2_0; // @[FPU.scala:453:7, :466:21] in_in3 <= io_in_bits_in3_0; // @[FPU.scala:453:7, :466:21] end valid <= io_in_valid_0; // @[FPU.scala:453:7, :467:22] always @(posedge) CompareRecFN_16 dcmp ( // @[FPU.scala:469:20] .io_a (in_in1), // @[FPU.scala:466:21] .io_b (in_in2), // @[FPU.scala:466:21] .io_signaling (_dcmp_io_signaling_T_1), // @[FPU.scala:472:24] .io_lt (_dcmp_io_lt), .io_eq (_dcmp_io_eq), .io_exceptionFlags (_dcmp_io_exceptionFlags) ); // @[FPU.scala:469:20] RecFNToIN_e11_s53_i64 conv ( // @[FPU.scala:498:24] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_conv_io_signedOut_T_1), // @[FPU.scala:501:28] .io_out (_conv_io_out), .io_intExceptionFlags (_conv_io_intExceptionFlags) ); // @[FPU.scala:498:24] RecFNToIN_e11_s53_i32 narrow ( // @[FPU.scala:508:30] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_narrow_io_signedOut_T_1), // @[FPU.scala:511:34] .io_intExceptionFlags (_narrow_io_intExceptionFlags) ); // @[FPU.scala:508:30] assign io_out_bits_in_rm = io_out_bits_in_rm_0; // @[FPU.scala:453:7] assign io_out_bits_in_in1 = io_out_bits_in_in1_0; // @[FPU.scala:453:7] assign io_out_bits_in_in2 = io_out_bits_in_in2_0; // @[FPU.scala:453:7] assign io_out_bits_lt = io_out_bits_lt_0; // @[FPU.scala:453:7] assign io_out_bits_store = io_out_bits_store_0; // @[FPU.scala:453:7] assign io_out_bits_toint = io_out_bits_toint_0; // @[FPU.scala:453:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:453:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLSlaveACDToNoC_3 : input clock : Clock input reset : Reset output io : { tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}}, flits : { flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}} invalidate io.tilelink.e.bits.sink invalidate io.tilelink.e.valid invalidate io.tilelink.e.ready invalidate io.tilelink.d.bits.corrupt invalidate io.tilelink.d.bits.data invalidate io.tilelink.d.bits.denied invalidate io.tilelink.d.bits.sink invalidate io.tilelink.d.bits.source invalidate io.tilelink.d.bits.size invalidate io.tilelink.d.bits.param invalidate io.tilelink.d.bits.opcode invalidate io.tilelink.d.valid invalidate io.tilelink.d.ready invalidate io.tilelink.c.bits.corrupt invalidate io.tilelink.c.bits.data invalidate io.tilelink.c.bits.address invalidate io.tilelink.c.bits.source invalidate io.tilelink.c.bits.size invalidate io.tilelink.c.bits.param invalidate io.tilelink.c.bits.opcode invalidate io.tilelink.c.valid invalidate io.tilelink.c.ready invalidate io.tilelink.b.bits.corrupt invalidate io.tilelink.b.bits.data invalidate io.tilelink.b.bits.mask invalidate io.tilelink.b.bits.address invalidate io.tilelink.b.bits.source invalidate io.tilelink.b.bits.size invalidate io.tilelink.b.bits.param invalidate io.tilelink.b.bits.opcode invalidate io.tilelink.b.valid invalidate io.tilelink.b.ready invalidate io.tilelink.a.bits.corrupt invalidate io.tilelink.a.bits.data invalidate io.tilelink.a.bits.mask invalidate io.tilelink.a.bits.address invalidate io.tilelink.a.bits.source invalidate io.tilelink.a.bits.size invalidate io.tilelink.a.bits.param invalidate io.tilelink.a.bits.opcode invalidate io.tilelink.a.valid invalidate io.tilelink.a.ready inst a of TLAFromNoC_3 connect a.clock, clock connect a.reset, reset inst c of TLCFromNoC_3 connect c.clock, clock connect c.reset, reset inst d of TLDToNoC_3 connect d.clock, clock connect d.reset, reset connect io.tilelink.a.bits, a.io.protocol.bits connect io.tilelink.a.valid, a.io.protocol.valid connect a.io.protocol.ready, io.tilelink.a.ready connect io.tilelink.c.bits, c.io.protocol.bits connect io.tilelink.c.valid, c.io.protocol.valid connect c.io.protocol.ready, io.tilelink.c.ready connect d.io.protocol, io.tilelink.d connect a.io.flit, io.flits.a connect c.io.flit, io.flits.c connect io.flits.d.bits, d.io.flit.bits connect io.flits.d.valid, d.io.flit.valid connect d.io.flit.ready, io.flits.d.ready
module TLSlaveACDToNoC_3( // @[Tilelink.scala:161:7] input clock, // @[Tilelink.scala:161:7] input reset, // @[Tilelink.scala:161:7] input io_tilelink_a_ready, // @[Tilelink.scala:168:14] output io_tilelink_a_valid, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:168:14] output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:168:14] output [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:168:14] output [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:168:14] output [15:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:168:14] output [127:0] io_tilelink_a_bits_data, // @[Tilelink.scala:168:14] output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:168:14] input io_tilelink_c_ready, // @[Tilelink.scala:168:14] output io_tilelink_c_valid, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:168:14] output [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:168:14] output [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:168:14] output [6:0] io_tilelink_c_bits_source, // @[Tilelink.scala:168:14] output [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:168:14] output [127:0] io_tilelink_c_bits_data, // @[Tilelink.scala:168:14] output io_tilelink_c_bits_corrupt, // @[Tilelink.scala:168:14] output io_tilelink_d_ready, // @[Tilelink.scala:168:14] input io_tilelink_d_valid, // @[Tilelink.scala:168:14] input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:168:14] input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:168:14] input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:168:14] input [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:168:14] input [5:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:168:14] input io_tilelink_d_bits_denied, // @[Tilelink.scala:168:14] input [127:0] io_tilelink_d_bits_data, // @[Tilelink.scala:168:14] input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:168:14] output io_flits_a_ready, // @[Tilelink.scala:168:14] input io_flits_a_valid, // @[Tilelink.scala:168:14] input io_flits_a_bits_head, // @[Tilelink.scala:168:14] input io_flits_a_bits_tail, // @[Tilelink.scala:168:14] input [144:0] io_flits_a_bits_payload, // @[Tilelink.scala:168:14] output io_flits_c_ready, // @[Tilelink.scala:168:14] input io_flits_c_valid, // @[Tilelink.scala:168:14] input io_flits_c_bits_head, // @[Tilelink.scala:168:14] input io_flits_c_bits_tail, // @[Tilelink.scala:168:14] input [144:0] io_flits_c_bits_payload, // @[Tilelink.scala:168:14] input io_flits_d_ready, // @[Tilelink.scala:168:14] output io_flits_d_valid, // @[Tilelink.scala:168:14] output io_flits_d_bits_head, // @[Tilelink.scala:168:14] output io_flits_d_bits_tail, // @[Tilelink.scala:168:14] output [144:0] io_flits_d_bits_payload, // @[Tilelink.scala:168:14] output [3:0] io_flits_d_bits_egress_id // @[Tilelink.scala:168:14] ); wire [128:0] _d_io_flit_bits_payload; // @[Tilelink.scala:179:17] TLAFromNoC a ( // @[Tilelink.scala:177:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload) ); // @[Tilelink.scala:177:17] TLCFromNoC_1 c ( // @[Tilelink.scala:178:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (io_flits_c_bits_payload[128:0]) // @[Tilelink.scala:185:14] ); // @[Tilelink.scala:178:17] TLDToNoC_3 d ( // @[Tilelink.scala:179:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (_d_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_d_bits_egress_id) ); // @[Tilelink.scala:179:17] assign io_flits_d_bits_payload = {16'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:161:7, :179:17, :186:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_router_21ClockSinkDomain : output auto : { routers_debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, routers_source_nodes_out_4 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, routers_source_nodes_out_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_4 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_19 connect routers.clock, childClock connect routers.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0 connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1 connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2 connect routers.auto.dest_nodes_in_3, auto.routers_dest_nodes_in_3 connect routers.auto.dest_nodes_in_4, auto.routers_dest_nodes_in_4 connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit connect routers.auto.source_nodes_out_3.vc_free, auto.routers_source_nodes_out_3.vc_free connect routers.auto.source_nodes_out_3.credit_return, auto.routers_source_nodes_out_3.credit_return connect auto.routers_source_nodes_out_3.flit, routers.auto.source_nodes_out_3.flit connect routers.auto.source_nodes_out_4.vc_free, auto.routers_source_nodes_out_4.vc_free connect routers.auto.source_nodes_out_4.credit_return, auto.routers_source_nodes_out_4.credit_return connect auto.routers_source_nodes_out_4.flit, routers.auto.source_nodes_out_4.flit connect auto.routers_debug_out, routers.auto.debug_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset
module TLNoC_router_21ClockSinkDomain( // @[ClockDomain.scala:14:9] output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_4_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_4_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_4_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_4_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_4_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_4_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_4_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_4_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_4_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_4_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_4_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_4_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_4_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_4_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_4_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_4_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_4_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_4_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_4_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_4_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_19 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_va_stall_4 (auto_routers_debug_out_va_stall_4), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_debug_out_sa_stall_4 (auto_routers_debug_out_sa_stall_4), .auto_source_nodes_out_4_flit_0_valid (auto_routers_source_nodes_out_4_flit_0_valid), .auto_source_nodes_out_4_flit_0_bits_head (auto_routers_source_nodes_out_4_flit_0_bits_head), .auto_source_nodes_out_4_flit_0_bits_tail (auto_routers_source_nodes_out_4_flit_0_bits_tail), .auto_source_nodes_out_4_flit_0_bits_payload (auto_routers_source_nodes_out_4_flit_0_bits_payload), .auto_source_nodes_out_4_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_4_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_4_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_4_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_4_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node), .auto_source_nodes_out_4_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_4_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_4_flit_0_bits_virt_channel_id), .auto_source_nodes_out_4_credit_return (auto_routers_source_nodes_out_4_credit_return), .auto_source_nodes_out_4_vc_free (auto_routers_source_nodes_out_4_vc_free), .auto_source_nodes_out_3_flit_0_valid (auto_routers_source_nodes_out_3_flit_0_valid), .auto_source_nodes_out_3_flit_0_bits_head (auto_routers_source_nodes_out_3_flit_0_bits_head), .auto_source_nodes_out_3_flit_0_bits_tail (auto_routers_source_nodes_out_3_flit_0_bits_tail), .auto_source_nodes_out_3_flit_0_bits_payload (auto_routers_source_nodes_out_3_flit_0_bits_payload), .auto_source_nodes_out_3_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_3_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_3_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node), .auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_3_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id), .auto_source_nodes_out_3_credit_return (auto_routers_source_nodes_out_3_credit_return), .auto_source_nodes_out_3_vc_free (auto_routers_source_nodes_out_3_vc_free), .auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid), .auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head), .auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail), .auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload), .auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id), .auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return), .auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_4_flit_0_valid (auto_routers_dest_nodes_in_4_flit_0_valid), .auto_dest_nodes_in_4_flit_0_bits_head (auto_routers_dest_nodes_in_4_flit_0_bits_head), .auto_dest_nodes_in_4_flit_0_bits_tail (auto_routers_dest_nodes_in_4_flit_0_bits_tail), .auto_dest_nodes_in_4_flit_0_bits_payload (auto_routers_dest_nodes_in_4_flit_0_bits_payload), .auto_dest_nodes_in_4_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_4_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_4_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_4_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_4_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_4_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_4_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_4_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_4_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_4_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_4_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_4_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_4_credit_return (auto_routers_dest_nodes_in_4_credit_return), .auto_dest_nodes_in_4_vc_free (auto_routers_dest_nodes_in_4_vc_free), .auto_dest_nodes_in_3_flit_0_valid (auto_routers_dest_nodes_in_3_flit_0_valid), .auto_dest_nodes_in_3_flit_0_bits_head (auto_routers_dest_nodes_in_3_flit_0_bits_head), .auto_dest_nodes_in_3_flit_0_bits_tail (auto_routers_dest_nodes_in_3_flit_0_bits_tail), .auto_dest_nodes_in_3_flit_0_bits_payload (auto_routers_dest_nodes_in_3_flit_0_bits_payload), .auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_3_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_3_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_3_credit_return (auto_routers_dest_nodes_in_3_credit_return), .auto_dest_nodes_in_3_vc_free (auto_routers_dest_nodes_in_3_vc_free), .auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid), .auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head), .auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail), .auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload), .auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return), .auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_125 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_125( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_90 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_91 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [7:0] io_in_a_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_a_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi = 4'hF; // @[Misc.scala:222:10] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [8:0] a_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Tile_166 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_422 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_166( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_422 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SerialRAM : input clock : Clock input reset : Reset output auto : { } output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}}, tsi : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}}, tsi2tl_state : UInt} inst serdesser of TLSerdesser_SerialRAM connect serdesser.clock, clock connect serdesser.reset, reset inst tsi2tl of TSIToTileLink connect tsi2tl.clock, clock connect tsi2tl.reset, reset inst buffer of TLBuffer_a32d64s1k6z4u connect buffer.clock, clock connect buffer.reset, reset connect buffer.auto.in, tsi2tl.auto.out connect serdesser.auto.manager_in, buffer.auto.out inst phy of DecoupledSerialPhy_1 connect phy.io.outer_clock, clock connect phy.io.outer_reset, reset connect phy.io.inner_clock, clock connect phy.io.inner_reset, reset connect io.ser.out.bits, phy.io.outer_ser.out.bits connect io.ser.out.valid, phy.io.outer_ser.out.valid connect phy.io.outer_ser.out.ready, io.ser.out.ready connect phy.io.outer_ser.in, io.ser.in connect phy.io.inner_ser[0], serdesser.io.ser[0] connect phy.io.inner_ser[1], serdesser.io.ser[1] connect phy.io.inner_ser[2], serdesser.io.ser[2] connect phy.io.inner_ser[3], serdesser.io.ser[3] connect phy.io.inner_ser[4], serdesser.io.ser[4] connect io.tsi.out.bits, tsi2tl.io.tsi.out.bits connect io.tsi.out.valid, tsi2tl.io.tsi.out.valid connect tsi2tl.io.tsi.out.ready, io.tsi.out.ready connect tsi2tl.io.tsi.in, io.tsi.in connect io.tsi2tl_state, tsi2tl.io.state extmodule SimTSI : input clock : Clock input reset : UInt<1> input tsi : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}} output exit : UInt<32> defname = SimTSI parameter CHIPID = 0
module SerialRAM( // @[TSIHarness.scala:122:9] input clock, // @[TSIHarness.scala:122:9] input reset, // @[TSIHarness.scala:122:9] output io_ser_in_ready, // @[TSIHarness.scala:123:16] input io_ser_in_valid, // @[TSIHarness.scala:123:16] input [31:0] io_ser_in_bits_phit, // @[TSIHarness.scala:123:16] input io_ser_out_ready, // @[TSIHarness.scala:123:16] output io_ser_out_valid, // @[TSIHarness.scala:123:16] output [31:0] io_ser_out_bits_phit, // @[TSIHarness.scala:123:16] output io_tsi_in_ready, // @[TSIHarness.scala:123:16] input io_tsi_in_valid, // @[TSIHarness.scala:123:16] input [31:0] io_tsi_in_bits, // @[TSIHarness.scala:123:16] input io_tsi_out_ready, // @[TSIHarness.scala:123:16] output io_tsi_out_valid, // @[TSIHarness.scala:123:16] output [31:0] io_tsi_out_bits // @[TSIHarness.scala:123:16] ); wire _phy_io_inner_ser_0_in_valid; // @[TSIHarness.scala:129:21] wire [31:0] _phy_io_inner_ser_0_in_bits_flit; // @[TSIHarness.scala:129:21] wire _phy_io_inner_ser_1_in_valid; // @[TSIHarness.scala:129:21] wire [31:0] _phy_io_inner_ser_1_in_bits_flit; // @[TSIHarness.scala:129:21] wire _phy_io_inner_ser_2_in_valid; // @[TSIHarness.scala:129:21] wire [31:0] _phy_io_inner_ser_2_in_bits_flit; // @[TSIHarness.scala:129:21] wire _phy_io_inner_ser_2_out_ready; // @[TSIHarness.scala:129:21] wire _phy_io_inner_ser_3_in_valid; // @[TSIHarness.scala:129:21] wire [31:0] _phy_io_inner_ser_3_in_bits_flit; // @[TSIHarness.scala:129:21] wire _phy_io_inner_ser_4_in_valid; // @[TSIHarness.scala:129:21] wire [31:0] _phy_io_inner_ser_4_in_bits_flit; // @[TSIHarness.scala:129:21] wire _phy_io_inner_ser_4_out_ready; // @[TSIHarness.scala:129:21] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28] wire [31:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28] wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28] wire _tsi2tl_auto_out_a_valid; // @[TSIHarness.scala:76:28] wire [2:0] _tsi2tl_auto_out_a_bits_opcode; // @[TSIHarness.scala:76:28] wire [3:0] _tsi2tl_auto_out_a_bits_size; // @[TSIHarness.scala:76:28] wire [31:0] _tsi2tl_auto_out_a_bits_address; // @[TSIHarness.scala:76:28] wire [7:0] _tsi2tl_auto_out_a_bits_mask; // @[TSIHarness.scala:76:28] wire [63:0] _tsi2tl_auto_out_a_bits_data; // @[TSIHarness.scala:76:28] wire _tsi2tl_auto_out_d_ready; // @[TSIHarness.scala:76:28] wire _serdesser_auto_manager_in_a_ready; // @[TSIHarness.scala:66:29] wire _serdesser_auto_manager_in_d_valid; // @[TSIHarness.scala:66:29] wire [2:0] _serdesser_auto_manager_in_d_bits_opcode; // @[TSIHarness.scala:66:29] wire [1:0] _serdesser_auto_manager_in_d_bits_param; // @[TSIHarness.scala:66:29] wire [3:0] _serdesser_auto_manager_in_d_bits_size; // @[TSIHarness.scala:66:29] wire _serdesser_auto_manager_in_d_bits_source; // @[TSIHarness.scala:66:29] wire [5:0] _serdesser_auto_manager_in_d_bits_sink; // @[TSIHarness.scala:66:29] wire _serdesser_auto_manager_in_d_bits_denied; // @[TSIHarness.scala:66:29] wire [63:0] _serdesser_auto_manager_in_d_bits_data; // @[TSIHarness.scala:66:29] wire _serdesser_auto_manager_in_d_bits_corrupt; // @[TSIHarness.scala:66:29] wire _serdesser_io_ser_0_in_ready; // @[TSIHarness.scala:66:29] wire [31:0] _serdesser_io_ser_0_out_bits_flit; // @[TSIHarness.scala:66:29] wire _serdesser_io_ser_1_in_ready; // @[TSIHarness.scala:66:29] wire _serdesser_io_ser_2_in_ready; // @[TSIHarness.scala:66:29] wire _serdesser_io_ser_2_out_valid; // @[TSIHarness.scala:66:29] wire [31:0] _serdesser_io_ser_2_out_bits_flit; // @[TSIHarness.scala:66:29] wire _serdesser_io_ser_3_in_ready; // @[TSIHarness.scala:66:29] wire _serdesser_io_ser_4_in_ready; // @[TSIHarness.scala:66:29] wire _serdesser_io_ser_4_out_valid; // @[TSIHarness.scala:66:29] wire [31:0] _serdesser_io_ser_4_out_bits_flit; // @[TSIHarness.scala:66:29] TLSerdesser_SerialRAM serdesser ( // @[TSIHarness.scala:66:29] .clock (clock), .reset (reset), .auto_manager_in_a_ready (_serdesser_auto_manager_in_a_ready), .auto_manager_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28] .auto_manager_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28] .auto_manager_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28] .auto_manager_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28] .auto_manager_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28] .auto_manager_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28] .auto_manager_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28] .auto_manager_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28] .auto_manager_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28] .auto_manager_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28] .auto_manager_in_d_valid (_serdesser_auto_manager_in_d_valid), .auto_manager_in_d_bits_opcode (_serdesser_auto_manager_in_d_bits_opcode), .auto_manager_in_d_bits_param (_serdesser_auto_manager_in_d_bits_param), .auto_manager_in_d_bits_size (_serdesser_auto_manager_in_d_bits_size), .auto_manager_in_d_bits_source (_serdesser_auto_manager_in_d_bits_source), .auto_manager_in_d_bits_sink (_serdesser_auto_manager_in_d_bits_sink), .auto_manager_in_d_bits_denied (_serdesser_auto_manager_in_d_bits_denied), .auto_manager_in_d_bits_data (_serdesser_auto_manager_in_d_bits_data), .auto_manager_in_d_bits_corrupt (_serdesser_auto_manager_in_d_bits_corrupt), .io_ser_0_in_ready (_serdesser_io_ser_0_in_ready), .io_ser_0_in_valid (_phy_io_inner_ser_0_in_valid), // @[TSIHarness.scala:129:21] .io_ser_0_in_bits_flit (_phy_io_inner_ser_0_in_bits_flit), // @[TSIHarness.scala:129:21] .io_ser_0_out_bits_flit (_serdesser_io_ser_0_out_bits_flit), .io_ser_1_in_ready (_serdesser_io_ser_1_in_ready), .io_ser_1_in_valid (_phy_io_inner_ser_1_in_valid), // @[TSIHarness.scala:129:21] .io_ser_1_in_bits_flit (_phy_io_inner_ser_1_in_bits_flit), // @[TSIHarness.scala:129:21] .io_ser_2_in_ready (_serdesser_io_ser_2_in_ready), .io_ser_2_in_valid (_phy_io_inner_ser_2_in_valid), // @[TSIHarness.scala:129:21] .io_ser_2_in_bits_flit (_phy_io_inner_ser_2_in_bits_flit), // @[TSIHarness.scala:129:21] .io_ser_2_out_ready (_phy_io_inner_ser_2_out_ready), // @[TSIHarness.scala:129:21] .io_ser_2_out_valid (_serdesser_io_ser_2_out_valid), .io_ser_2_out_bits_flit (_serdesser_io_ser_2_out_bits_flit), .io_ser_3_in_ready (_serdesser_io_ser_3_in_ready), .io_ser_3_in_valid (_phy_io_inner_ser_3_in_valid), // @[TSIHarness.scala:129:21] .io_ser_3_in_bits_flit (_phy_io_inner_ser_3_in_bits_flit), // @[TSIHarness.scala:129:21] .io_ser_4_in_ready (_serdesser_io_ser_4_in_ready), .io_ser_4_in_valid (_phy_io_inner_ser_4_in_valid), // @[TSIHarness.scala:129:21] .io_ser_4_in_bits_flit (_phy_io_inner_ser_4_in_bits_flit), // @[TSIHarness.scala:129:21] .io_ser_4_out_ready (_phy_io_inner_ser_4_out_ready), // @[TSIHarness.scala:129:21] .io_ser_4_out_valid (_serdesser_io_ser_4_out_valid), .io_ser_4_out_bits_flit (_serdesser_io_ser_4_out_bits_flit) ); // @[TSIHarness.scala:66:29] TSIToTileLink tsi2tl ( // @[TSIHarness.scala:76:28] .clock (clock), .reset (reset), .auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_a_valid (_tsi2tl_auto_out_a_valid), .auto_out_a_bits_opcode (_tsi2tl_auto_out_a_bits_opcode), .auto_out_a_bits_size (_tsi2tl_auto_out_a_bits_size), .auto_out_a_bits_address (_tsi2tl_auto_out_a_bits_address), .auto_out_a_bits_mask (_tsi2tl_auto_out_a_bits_mask), .auto_out_a_bits_data (_tsi2tl_auto_out_a_bits_data), .auto_out_d_ready (_tsi2tl_auto_out_d_ready), .auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .io_tsi_in_ready (io_tsi_in_ready), .io_tsi_in_valid (io_tsi_in_valid), .io_tsi_in_bits (io_tsi_in_bits), .io_tsi_out_ready (io_tsi_out_ready), .io_tsi_out_valid (io_tsi_out_valid), .io_tsi_out_bits (io_tsi_out_bits) ); // @[TSIHarness.scala:76:28] TLBuffer_a32d64s1k6z4u buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_tsi2tl_auto_out_a_valid), // @[TSIHarness.scala:76:28] .auto_in_a_bits_opcode (_tsi2tl_auto_out_a_bits_opcode), // @[TSIHarness.scala:76:28] .auto_in_a_bits_size (_tsi2tl_auto_out_a_bits_size), // @[TSIHarness.scala:76:28] .auto_in_a_bits_address (_tsi2tl_auto_out_a_bits_address), // @[TSIHarness.scala:76:28] .auto_in_a_bits_mask (_tsi2tl_auto_out_a_bits_mask), // @[TSIHarness.scala:76:28] .auto_in_a_bits_data (_tsi2tl_auto_out_a_bits_data), // @[TSIHarness.scala:76:28] .auto_in_d_ready (_tsi2tl_auto_out_d_ready), // @[TSIHarness.scala:76:28] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_out_a_ready (_serdesser_auto_manager_in_a_ready), // @[TSIHarness.scala:66:29] .auto_out_a_valid (_buffer_auto_out_a_valid), .auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode), .auto_out_a_bits_param (_buffer_auto_out_a_bits_param), .auto_out_a_bits_size (_buffer_auto_out_a_bits_size), .auto_out_a_bits_source (_buffer_auto_out_a_bits_source), .auto_out_a_bits_address (_buffer_auto_out_a_bits_address), .auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask), .auto_out_a_bits_data (_buffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), .auto_out_d_ready (_buffer_auto_out_d_ready), .auto_out_d_valid (_serdesser_auto_manager_in_d_valid), // @[TSIHarness.scala:66:29] .auto_out_d_bits_opcode (_serdesser_auto_manager_in_d_bits_opcode), // @[TSIHarness.scala:66:29] .auto_out_d_bits_param (_serdesser_auto_manager_in_d_bits_param), // @[TSIHarness.scala:66:29] .auto_out_d_bits_size (_serdesser_auto_manager_in_d_bits_size), // @[TSIHarness.scala:66:29] .auto_out_d_bits_source (_serdesser_auto_manager_in_d_bits_source), // @[TSIHarness.scala:66:29] .auto_out_d_bits_sink (_serdesser_auto_manager_in_d_bits_sink), // @[TSIHarness.scala:66:29] .auto_out_d_bits_denied (_serdesser_auto_manager_in_d_bits_denied), // @[TSIHarness.scala:66:29] .auto_out_d_bits_data (_serdesser_auto_manager_in_d_bits_data), // @[TSIHarness.scala:66:29] .auto_out_d_bits_corrupt (_serdesser_auto_manager_in_d_bits_corrupt) // @[TSIHarness.scala:66:29] ); // @[Buffer.scala:75:28] DecoupledSerialPhy phy ( // @[TSIHarness.scala:129:21] .io_outer_clock (clock), .io_outer_reset (reset), .io_inner_clock (clock), .io_inner_reset (reset), .io_outer_ser_in_ready (io_ser_in_ready), .io_outer_ser_in_valid (io_ser_in_valid), .io_outer_ser_in_bits_phit (io_ser_in_bits_phit), .io_outer_ser_out_ready (io_ser_out_ready), .io_outer_ser_out_valid (io_ser_out_valid), .io_outer_ser_out_bits_phit (io_ser_out_bits_phit), .io_inner_ser_0_in_ready (_serdesser_io_ser_0_in_ready), // @[TSIHarness.scala:66:29] .io_inner_ser_0_in_valid (_phy_io_inner_ser_0_in_valid), .io_inner_ser_0_in_bits_flit (_phy_io_inner_ser_0_in_bits_flit), .io_inner_ser_0_out_bits_flit (_serdesser_io_ser_0_out_bits_flit), // @[TSIHarness.scala:66:29] .io_inner_ser_1_in_ready (_serdesser_io_ser_1_in_ready), // @[TSIHarness.scala:66:29] .io_inner_ser_1_in_valid (_phy_io_inner_ser_1_in_valid), .io_inner_ser_1_in_bits_flit (_phy_io_inner_ser_1_in_bits_flit), .io_inner_ser_1_out_ready (/* unused */), .io_inner_ser_1_out_valid (1'h0), // @[TSIHarness.scala:66:29, :76:28, :129:21] .io_inner_ser_1_out_bits_flit (32'h0), // @[TSIHarness.scala:66:29, :129:21] .io_inner_ser_2_in_ready (_serdesser_io_ser_2_in_ready), // @[TSIHarness.scala:66:29] .io_inner_ser_2_in_valid (_phy_io_inner_ser_2_in_valid), .io_inner_ser_2_in_bits_flit (_phy_io_inner_ser_2_in_bits_flit), .io_inner_ser_2_out_ready (_phy_io_inner_ser_2_out_ready), .io_inner_ser_2_out_valid (_serdesser_io_ser_2_out_valid), // @[TSIHarness.scala:66:29] .io_inner_ser_2_out_bits_flit (_serdesser_io_ser_2_out_bits_flit), // @[TSIHarness.scala:66:29] .io_inner_ser_3_in_ready (_serdesser_io_ser_3_in_ready), // @[TSIHarness.scala:66:29] .io_inner_ser_3_in_valid (_phy_io_inner_ser_3_in_valid), .io_inner_ser_3_in_bits_flit (_phy_io_inner_ser_3_in_bits_flit), .io_inner_ser_3_out_ready (/* unused */), .io_inner_ser_3_out_valid (1'h0), // @[TSIHarness.scala:66:29, :76:28, :129:21] .io_inner_ser_3_out_bits_flit (32'h0), // @[TSIHarness.scala:66:29, :129:21] .io_inner_ser_4_in_ready (_serdesser_io_ser_4_in_ready), // @[TSIHarness.scala:66:29] .io_inner_ser_4_in_valid (_phy_io_inner_ser_4_in_valid), .io_inner_ser_4_in_bits_flit (_phy_io_inner_ser_4_in_bits_flit), .io_inner_ser_4_out_ready (_phy_io_inner_ser_4_out_ready), .io_inner_ser_4_out_valid (_serdesser_io_ser_4_out_valid), // @[TSIHarness.scala:66:29] .io_inner_ser_4_out_bits_flit (_serdesser_io_ser_4_out_bits_flit) // @[TSIHarness.scala:66:29] ); // @[TSIHarness.scala:129:21] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_164 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_420 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_164( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_420 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RegisterReadDecode_9 : input clock : Clock input reset : Reset output io : { flip iss_valid : UInt<1>, flip iss_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rrd_valid : UInt<1>, rrd_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}} connect io.rrd_uop, io.iss_uop wire rrd_cs : { br_type : UInt<4>, use_alupipe : UInt<1>, use_muldivpipe : UInt<1>, use_mempipe : UInt<1>, op_fcn : UInt<5>, fcn_dw : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, rf_wen : UInt<1>, csr_cmd : UInt<3>} wire rrd_cs_decoder_decoded_plaInput : UInt<7> node rrd_cs_decoder_decoded_invInputs = not(rrd_cs_decoder_decoded_plaInput) wire rrd_cs_decoder_decoded : UInt<24> node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo) node rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1) node rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2) node rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3) node rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4) node rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5) node rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6) node rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_6) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7) node rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_7) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8) node rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_8) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9) node rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_9) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10) node rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_10) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11) node rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_11) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12) node rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_12) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13) node rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_13) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14) node rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_14) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15) node rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_15) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16) node rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_16) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17) node rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_17) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18) node rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_18) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19) node rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_19) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20) node rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_20) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21) node rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_21) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21) node rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_22) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23) node rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_23) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22) node rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_24) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23) node rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_25) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24) node rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_26) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25) node rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_27) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26) node rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_28) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27) node rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_29) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28) node rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_30) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29) node rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_31) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30) node rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_32) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31) node rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_33) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32) node rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_34) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33) node rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_35) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34) node rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_36) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35) node rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_37) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36) node rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_38) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37) node rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_39) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38) node rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_40) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39) node rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_41) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40) node rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_42) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41) node rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_43) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42) node rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_44) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43) node rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_45) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44) node rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_46) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45) node rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_47) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46) node rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_48) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49) node rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_49) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47) node rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_50) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48) node rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_51) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49) node rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_52) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50) node rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_53) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51) node rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_54) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52) node rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_55) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53) node rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_56) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54) node rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_57) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55) node rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_58) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56) node rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_59) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57) node rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_60) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58) node rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_61) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59) node rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_62) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60) node rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_63) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61) node rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_64) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_20_2, rrd_cs_decoder_decoded_andMatrixOutputs_49_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_52_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_28_2, rrd_cs_decoder_decoded_andMatrixOutputs_27_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_43_2, rrd_cs_decoder_decoded_andMatrixOutputs_39_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_3_2, rrd_cs_decoder_decoded_andMatrixOutputs_29_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_3) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_26_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_22_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_15_2, rrd_cs_decoder_decoded_andMatrixOutputs_59_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_9_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_51_2, rrd_cs_decoder_decoded_andMatrixOutputs_8_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_42_2, rrd_cs_decoder_decoded_andMatrixOutputs_12_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_8) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_31_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_8_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_33_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_0_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_46_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_60_2, rrd_cs_decoder_decoded_andMatrixOutputs_44_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_36_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_10) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_10_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_52_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_23_2, rrd_cs_decoder_decoded_andMatrixOutputs_45_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_25_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_24_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_57_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_48_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_37_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_12) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_19_2, rrd_cs_decoder_decoded_andMatrixOutputs_64_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_13_2, rrd_cs_decoder_decoded_andMatrixOutputs_62_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_1_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_35_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_14) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_30_2, rrd_cs_decoder_decoded_andMatrixOutputs_23_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_47_2, rrd_cs_decoder_decoded_andMatrixOutputs_38_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_53_2, rrd_cs_decoder_decoded_andMatrixOutputs_63_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_7_2, rrd_cs_decoder_decoded_andMatrixOutputs_14_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_16) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_18_2, rrd_cs_decoder_decoded_andMatrixOutputs_55_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_52_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_18) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_18_2, rrd_cs_decoder_decoded_andMatrixOutputs_55_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_52_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_20) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_61_2, rrd_cs_decoder_decoded_andMatrixOutputs_5_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_6_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_22) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_54_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_24) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_16_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_26) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_4, _rrd_cs_decoder_decoded_orMatrixOutputs_T_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_6) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_7) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_13, _rrd_cs_decoder_decoded_orMatrixOutputs_T_11) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_9) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_17) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_15) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_23, _rrd_cs_decoder_decoded_orMatrixOutputs_T_21) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_19) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_27) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_25) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6) node rrd_cs_decoder_decoded_orMatrixOutputs = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7) node _rrd_cs_decoder_decoded_invMatrixOutputs_T = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 0, 0) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 1, 1) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 2, 2) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 3, 3) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 4, 4) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 5, 5) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 6, 6) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 7, 7) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 8, 8) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 9, 9) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 10, 10) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 11, 11) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 12, 12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 13, 13) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 14, 14) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 15, 15) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 16, 16) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 17, 17) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 18, 18) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 19, 19) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_20) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 20, 20) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 21, 21) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 22, 22) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 23, 23) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_21) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_25, _rrd_cs_decoder_decoded_invMatrixOutputs_T_24) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo) connect rrd_cs_decoder_decoded, rrd_cs_decoder_decoded_invMatrixOutputs connect rrd_cs_decoder_decoded_plaInput, io.rrd_uop.uopc node rrd_cs_decoder_0 = bits(rrd_cs_decoder_decoded, 23, 20) node rrd_cs_decoder_1 = bits(rrd_cs_decoder_decoded, 19, 19) node rrd_cs_decoder_2 = bits(rrd_cs_decoder_decoded, 18, 18) node rrd_cs_decoder_3 = bits(rrd_cs_decoder_decoded, 17, 17) node rrd_cs_decoder_4 = bits(rrd_cs_decoder_decoded, 16, 13) node rrd_cs_decoder_5 = bits(rrd_cs_decoder_decoded, 12, 12) node rrd_cs_decoder_6 = bits(rrd_cs_decoder_decoded, 11, 10) node rrd_cs_decoder_7 = bits(rrd_cs_decoder_decoded, 9, 7) node rrd_cs_decoder_8 = bits(rrd_cs_decoder_decoded, 6, 4) node rrd_cs_decoder_9 = bits(rrd_cs_decoder_decoded, 3, 3) node rrd_cs_decoder_10 = bits(rrd_cs_decoder_decoded, 2, 0) connect rrd_cs.br_type, rrd_cs_decoder_0 connect rrd_cs.use_alupipe, rrd_cs_decoder_1 connect rrd_cs.use_muldivpipe, rrd_cs_decoder_2 connect rrd_cs.use_mempipe, rrd_cs_decoder_3 connect rrd_cs.op_fcn, rrd_cs_decoder_4 connect rrd_cs.fcn_dw, rrd_cs_decoder_5 connect rrd_cs.op1_sel, rrd_cs_decoder_6 connect rrd_cs.op2_sel, rrd_cs_decoder_7 connect rrd_cs.imm_sel, rrd_cs_decoder_8 connect rrd_cs.rf_wen, rrd_cs_decoder_9 connect rrd_cs.csr_cmd, rrd_cs_decoder_10 connect io.rrd_uop.ctrl.br_type, rrd_cs.br_type connect io.rrd_uop.ctrl.op1_sel, rrd_cs.op1_sel connect io.rrd_uop.ctrl.op2_sel, rrd_cs.op2_sel connect io.rrd_uop.ctrl.imm_sel, rrd_cs.imm_sel connect io.rrd_uop.ctrl.op_fcn, rrd_cs.op_fcn connect io.rrd_uop.ctrl.fcn_dw, rrd_cs.fcn_dw node _io_rrd_uop_ctrl_is_load_T = eq(io.rrd_uop.uopc, UInt<7>(0h1)) connect io.rrd_uop.ctrl.is_load, _io_rrd_uop_ctrl_is_load_T node _io_rrd_uop_ctrl_is_sta_T = eq(io.rrd_uop.uopc, UInt<7>(0h2)) node _io_rrd_uop_ctrl_is_sta_T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _io_rrd_uop_ctrl_is_sta_T_2 = or(_io_rrd_uop_ctrl_is_sta_T, _io_rrd_uop_ctrl_is_sta_T_1) connect io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_sta_T_2 node _io_rrd_uop_ctrl_is_std_T = eq(io.rrd_uop.uopc, UInt<7>(0h3)) node _io_rrd_uop_ctrl_is_std_T_1 = eq(io.rrd_uop.lrs2_rtype, UInt<2>(0h0)) node _io_rrd_uop_ctrl_is_std_T_2 = and(io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_std_T_1) node _io_rrd_uop_ctrl_is_std_T_3 = or(_io_rrd_uop_ctrl_is_std_T, _io_rrd_uop_ctrl_is_std_T_2) connect io.rrd_uop.ctrl.is_std, _io_rrd_uop_ctrl_is_std_T_3 node _T = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h1)) node _T_2 = eq(io.rrd_uop.mem_cmd, UInt<3>(0h6)) node _T_3 = and(_T_1, _T_2) node _T_4 = or(_T, _T_3) when _T_4 : connect io.rrd_uop.imm_packed, UInt<1>(0h0) node _csr_ren_T = eq(rrd_cs.csr_cmd, UInt<3>(0h6)) node _csr_ren_T_1 = eq(rrd_cs.csr_cmd, UInt<3>(0h7)) node _csr_ren_T_2 = or(_csr_ren_T, _csr_ren_T_1) node _csr_ren_T_3 = eq(io.rrd_uop.prs1, UInt<1>(0h0)) node csr_ren = and(_csr_ren_T_2, _csr_ren_T_3) node _io_rrd_uop_ctrl_csr_cmd_T = mux(csr_ren, UInt<3>(0h2), rrd_cs.csr_cmd) connect io.rrd_uop.ctrl.csr_cmd, _io_rrd_uop_ctrl_csr_cmd_T connect io.rrd_valid, io.iss_valid
module RegisterReadDecode_9( // @[func-unit-decode.scala:307:7] input clock, // @[func-unit-decode.scala:307:7] input reset, // @[func-unit-decode.scala:307:7] input io_iss_valid, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_uopc, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_inst, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_debug_inst, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_rvc, // @[func-unit-decode.scala:310:14] input [39:0] io_iss_uop_debug_pc, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_iq_type, // @[func-unit-decode.scala:310:14] input [9:0] io_iss_uop_fu_code, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_iw_state, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_br, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jalr, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jal, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sfb, // @[func-unit-decode.scala:310:14] input [15:0] io_iss_uop_br_mask, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_br_tag, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ftq_idx, // @[func-unit-decode.scala:310:14] input io_iss_uop_edge_inst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_pc_lob, // @[func-unit-decode.scala:310:14] input io_iss_uop_taken, // @[func-unit-decode.scala:310:14] input [19:0] io_iss_uop_imm_packed, // @[func-unit-decode.scala:310:14] input [11:0] io_iss_uop_csr_addr, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_rob_idx, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ldq_idx, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_stq_idx, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_rxq_idx, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_pdst, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs1, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs2, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_prs3, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ppred, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs1_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs2_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs3_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_ppred_busy, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_stale_pdst, // @[func-unit-decode.scala:310:14] input io_iss_uop_exception, // @[func-unit-decode.scala:310:14] input [63:0] io_iss_uop_exc_cause, // @[func-unit-decode.scala:310:14] input io_iss_uop_bypassable, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_mem_cmd, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_mem_size, // @[func-unit-decode.scala:310:14] input io_iss_uop_mem_signed, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fence, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fencei, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_amo, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_ldq, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_stq, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_unique, // @[func-unit-decode.scala:310:14] input io_iss_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_ldst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs2, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs3, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_val, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_dst_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] input io_iss_uop_frs3_en, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_val, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_single, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_tsrc, // @[func-unit-decode.scala:310:14] output io_rrd_valid, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_uopc, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_inst, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_debug_inst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_rvc, // @[func-unit-decode.scala:310:14] output [39:0] io_rrd_uop_debug_pc, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_iq_type, // @[func-unit-decode.scala:310:14] output [9:0] io_rrd_uop_fu_code, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_iw_state, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_br, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jalr, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jal, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sfb, // @[func-unit-decode.scala:310:14] output [15:0] io_rrd_uop_br_mask, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_br_tag, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ftq_idx, // @[func-unit-decode.scala:310:14] output io_rrd_uop_edge_inst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_pc_lob, // @[func-unit-decode.scala:310:14] output io_rrd_uop_taken, // @[func-unit-decode.scala:310:14] output [19:0] io_rrd_uop_imm_packed, // @[func-unit-decode.scala:310:14] output [11:0] io_rrd_uop_csr_addr, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_rob_idx, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ldq_idx, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_stq_idx, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_rxq_idx, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_pdst, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs1, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs2, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_prs3, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ppred, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs1_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs2_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs3_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ppred_busy, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_stale_pdst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_exception, // @[func-unit-decode.scala:310:14] output [63:0] io_rrd_uop_exc_cause, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bypassable, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_mem_cmd, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_mem_size, // @[func-unit-decode.scala:310:14] output io_rrd_uop_mem_signed, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fence, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fencei, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_amo, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_ldq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_stq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_unique, // @[func-unit-decode.scala:310:14] output io_rrd_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_ldst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs2, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs3, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_val, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_dst_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] output io_rrd_uop_frs3_en, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_val, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_single, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_tsrc // @[func-unit-decode.scala:310:14] ); wire io_iss_valid_0 = io_iss_valid; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_uopc_0 = io_iss_uop_uopc; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_inst_0 = io_iss_uop_inst; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_debug_inst_0 = io_iss_uop_debug_inst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_rvc_0 = io_iss_uop_is_rvc; // @[func-unit-decode.scala:307:7] wire [39:0] io_iss_uop_debug_pc_0 = io_iss_uop_debug_pc; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_iq_type_0 = io_iss_uop_iq_type; // @[func-unit-decode.scala:307:7] wire [9:0] io_iss_uop_fu_code_0 = io_iss_uop_fu_code; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_ctrl_br_type_0 = io_iss_uop_ctrl_br_type; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_ctrl_op1_sel_0 = io_iss_uop_ctrl_op1_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_op2_sel_0 = io_iss_uop_ctrl_op2_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_imm_sel_0 = io_iss_uop_ctrl_imm_sel; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ctrl_op_fcn_0 = io_iss_uop_ctrl_op_fcn; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_fcn_dw_0 = io_iss_uop_ctrl_fcn_dw; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_csr_cmd_0 = io_iss_uop_ctrl_csr_cmd; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_load_0 = io_iss_uop_ctrl_is_load; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_sta_0 = io_iss_uop_ctrl_is_sta; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_std_0 = io_iss_uop_ctrl_is_std; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_iw_state_0 = io_iss_uop_iw_state; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_br_0 = io_iss_uop_is_br; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jalr_0 = io_iss_uop_is_jalr; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jal_0 = io_iss_uop_is_jal; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sfb_0 = io_iss_uop_is_sfb; // @[func-unit-decode.scala:307:7] wire [15:0] io_iss_uop_br_mask_0 = io_iss_uop_br_mask; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_br_tag_0 = io_iss_uop_br_tag; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ftq_idx_0 = io_iss_uop_ftq_idx; // @[func-unit-decode.scala:307:7] wire io_iss_uop_edge_inst_0 = io_iss_uop_edge_inst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_pc_lob_0 = io_iss_uop_pc_lob; // @[func-unit-decode.scala:307:7] wire io_iss_uop_taken_0 = io_iss_uop_taken; // @[func-unit-decode.scala:307:7] wire [19:0] io_iss_uop_imm_packed_0 = io_iss_uop_imm_packed; // @[func-unit-decode.scala:307:7] wire [11:0] io_iss_uop_csr_addr_0 = io_iss_uop_csr_addr; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_rob_idx_0 = io_iss_uop_rob_idx; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ldq_idx_0 = io_iss_uop_ldq_idx; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_stq_idx_0 = io_iss_uop_stq_idx; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_rxq_idx_0 = io_iss_uop_rxq_idx; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_pdst_0 = io_iss_uop_pdst; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs1_0 = io_iss_uop_prs1; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs2; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_prs3_0 = io_iss_uop_prs3; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ppred_0 = io_iss_uop_ppred; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs1_busy_0 = io_iss_uop_prs1_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs2_busy_0 = io_iss_uop_prs2_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs3_busy_0 = io_iss_uop_prs3_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ppred_busy_0 = io_iss_uop_ppred_busy; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_stale_pdst_0 = io_iss_uop_stale_pdst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_exception_0 = io_iss_uop_exception; // @[func-unit-decode.scala:307:7] wire [63:0] io_iss_uop_exc_cause_0 = io_iss_uop_exc_cause; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bypassable_0 = io_iss_uop_bypassable; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_mem_cmd_0 = io_iss_uop_mem_cmd; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_mem_size_0 = io_iss_uop_mem_size; // @[func-unit-decode.scala:307:7] wire io_iss_uop_mem_signed_0 = io_iss_uop_mem_signed; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fence_0 = io_iss_uop_is_fence; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fencei_0 = io_iss_uop_is_fencei; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_amo_0 = io_iss_uop_is_amo; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_ldq_0 = io_iss_uop_uses_ldq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_stq_0 = io_iss_uop_uses_stq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_unique_0 = io_iss_uop_is_unique; // @[func-unit-decode.scala:307:7] wire io_iss_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_ldst_0 = io_iss_uop_ldst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs1_0 = io_iss_uop_lrs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs2_0 = io_iss_uop_lrs2; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs3_0 = io_iss_uop_lrs3; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_val_0 = io_iss_uop_ldst_val; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_dst_rtype_0 = io_iss_uop_dst_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype; // @[func-unit-decode.scala:307:7] wire io_iss_uop_frs3_en_0 = io_iss_uop_frs3_en; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_val_0 = io_iss_uop_fp_val; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_single_0 = io_iss_uop_fp_single; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc; // @[func-unit-decode.scala:307:7] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = 2'h0; // @[pla.scala:102:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = 3'h0; // @[pla.scala:102:36] wire io_iss_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_iss_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_valid_0 = io_iss_valid_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_uopc_0 = io_iss_uop_uopc_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_inst_0 = io_iss_uop_inst_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_debug_inst_0 = io_iss_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_rvc_0 = io_iss_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] wire [39:0] io_rrd_uop_debug_pc_0 = io_iss_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_iq_type_0 = io_iss_uop_iq_type_0; // @[func-unit-decode.scala:307:7] wire [9:0] io_rrd_uop_fu_code_0 = io_iss_uop_fu_code_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_iw_state_0 = io_iss_uop_iw_state_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_br_0 = io_iss_uop_is_br_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jalr_0 = io_iss_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jal_0 = io_iss_uop_is_jal_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sfb_0 = io_iss_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] wire [15:0] io_rrd_uop_br_mask_0 = io_iss_uop_br_mask_0; // @[func-unit-decode.scala:307:7] wire [3:0] io_rrd_uop_br_tag_0 = io_iss_uop_br_tag_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ftq_idx_0 = io_iss_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_edge_inst_0 = io_iss_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_pc_lob_0 = io_iss_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_taken_0 = io_iss_uop_taken_0; // @[func-unit-decode.scala:307:7] wire [11:0] io_rrd_uop_csr_addr_0 = io_iss_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_rob_idx_0 = io_iss_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ldq_idx_0 = io_iss_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_stq_idx_0 = io_iss_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_rxq_idx_0 = io_iss_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_pdst_0 = io_iss_uop_pdst_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs1_0 = io_iss_uop_prs1_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs2_0 = io_iss_uop_prs2_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_prs3_0 = io_iss_uop_prs3_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ppred_0 = io_iss_uop_ppred_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs1_busy_0 = io_iss_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs2_busy_0 = io_iss_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs3_busy_0 = io_iss_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ppred_busy_0 = io_iss_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_stale_pdst_0 = io_iss_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_exception_0 = io_iss_uop_exception_0; // @[func-unit-decode.scala:307:7] wire [63:0] io_rrd_uop_exc_cause_0 = io_iss_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bypassable_0 = io_iss_uop_bypassable_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_mem_cmd_0 = io_iss_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_mem_size_0 = io_iss_uop_mem_size_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_mem_signed_0 = io_iss_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fence_0 = io_iss_uop_is_fence_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fencei_0 = io_iss_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_amo_0 = io_iss_uop_is_amo_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_ldq_0 = io_iss_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_stq_0 = io_iss_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_unique_0 = io_iss_uop_is_unique_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_ldst_0 = io_iss_uop_ldst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs1_0 = io_iss_uop_lrs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs2_0 = io_iss_uop_lrs2_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs3_0 = io_iss_uop_lrs3_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_val_0 = io_iss_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_dst_rtype_0 = io_iss_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_frs3_en_0 = io_iss_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_val_0 = io_iss_uop_fp_val_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_single_0 = io_iss_uop_fp_single_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] wire [6:0] rrd_cs_decoder_decoded_plaInput = io_rrd_uop_uopc_0; // @[pla.scala:77:22] wire [3:0] rrd_cs_br_type; // @[func-unit-decode.scala:330:20] wire [1:0] rrd_cs_op1_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_op2_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_imm_sel; // @[func-unit-decode.scala:330:20] wire [4:0] rrd_cs_op_fcn; // @[func-unit-decode.scala:330:20] wire rrd_cs_fcn_dw; // @[func-unit-decode.scala:330:20] wire [2:0] _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:349:33] wire _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:339:46] wire _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:340:57] wire _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:341:57] wire [3:0] io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] wire [19:0] io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] wire [3:0] rrd_cs_decoder_0; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_br_type_0 = rrd_cs_br_type; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_1; // @[Decode.scala:50:77] wire rrd_cs_decoder_2; // @[Decode.scala:50:77] wire rrd_cs_decoder_3; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op_fcn_0 = rrd_cs_op_fcn; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_5; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_fcn_dw_0 = rrd_cs_fcn_dw; // @[func-unit-decode.scala:307:7, :330:20] wire [1:0] rrd_cs_decoder_6; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op1_sel_0 = rrd_cs_op1_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_7; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op2_sel_0 = rrd_cs_op2_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_8; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_imm_sel_0 = rrd_cs_imm_sel; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_9; // @[Decode.scala:50:77] wire [2:0] rrd_cs_decoder_10; // @[Decode.scala:50:77] wire rrd_cs_use_alupipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_muldivpipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_mempipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_rf_wen; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20] wire [6:0] rrd_cs_decoder_decoded_invInputs = ~rrd_cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [23:0] rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [23:0] rrd_cs_decoder_decoded; // @[pla.scala:81:23] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T = {rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = rrd_cs_decoder_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = rrd_cs_decoder_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_20_2, rrd_cs_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_28_2, rrd_cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_43_2, rrd_cs_decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [6:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T = {rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_3_2, rrd_cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_26_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_15_2, rrd_cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_5; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_51_2, rrd_cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_42_2, rrd_cs_decoder_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_31_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_8_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_4_2, rrd_cs_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_60_2, rrd_cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_10_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_23_2, rrd_cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [12:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_19_2, rrd_cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_13_2, rrd_cs_decoder_decoded_andMatrixOutputs_62_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_30_2, rrd_cs_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_47_2, rrd_cs_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_53_2, rrd_cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_7_2, rrd_cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [7:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_16; // @[pla.scala:114:{19,36}] wire [1:0] _GEN = {rrd_cs_decoder_decoded_andMatrixOutputs_18_2, rrd_cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_7; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = _GEN; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_8; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = _GEN; // @[pla.scala:114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_18; // @[pla.scala:114:{19,36}] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_20; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_61_2, rrd_cs_decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_26; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_4, _rrd_cs_decoder_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, 3'h0}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, 1'h0}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, 1'h0}; // @[pla.scala:102:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [11:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_13, _rrd_cs_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_17}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_23, _rrd_cs_decoder_decoded_orMatrixOutputs_T_21}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_19}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_27}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:102:36] wire [11:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:102:36] wire [23:0] rrd_cs_decoder_decoded_orMatrixOutputs = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:102:36] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T = rrd_cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = rrd_cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = rrd_cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = rrd_cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = rrd_cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = rrd_cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = rrd_cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = rrd_cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = rrd_cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = rrd_cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = rrd_cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = rrd_cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = rrd_cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_12; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = rrd_cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = rrd_cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = rrd_cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = rrd_cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = rrd_cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = rrd_cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = rrd_cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_20; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = rrd_cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = rrd_cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = rrd_cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = rrd_cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :123:40] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :123:40, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_25, _rrd_cs_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [11:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded_invMatrixOutputs = {rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded = rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign rrd_cs_decoder_0 = rrd_cs_decoder_decoded[23:20]; // @[pla.scala:81:23] assign rrd_cs_br_type = rrd_cs_decoder_0; // @[Decode.scala:50:77] assign rrd_cs_decoder_1 = rrd_cs_decoder_decoded[19]; // @[pla.scala:81:23] assign rrd_cs_use_alupipe = rrd_cs_decoder_1; // @[Decode.scala:50:77] assign rrd_cs_decoder_2 = rrd_cs_decoder_decoded[18]; // @[pla.scala:81:23] assign rrd_cs_use_muldivpipe = rrd_cs_decoder_2; // @[Decode.scala:50:77] assign rrd_cs_decoder_3 = rrd_cs_decoder_decoded[17]; // @[pla.scala:81:23] assign rrd_cs_use_mempipe = rrd_cs_decoder_3; // @[Decode.scala:50:77] wire [3:0] rrd_cs_decoder_4 = rrd_cs_decoder_decoded[16:13]; // @[pla.scala:81:23] assign rrd_cs_decoder_5 = rrd_cs_decoder_decoded[12]; // @[pla.scala:81:23] assign rrd_cs_fcn_dw = rrd_cs_decoder_5; // @[Decode.scala:50:77] assign rrd_cs_decoder_6 = rrd_cs_decoder_decoded[11:10]; // @[pla.scala:81:23] assign rrd_cs_op1_sel = rrd_cs_decoder_6; // @[Decode.scala:50:77] assign rrd_cs_decoder_7 = rrd_cs_decoder_decoded[9:7]; // @[pla.scala:81:23] assign rrd_cs_op2_sel = rrd_cs_decoder_7; // @[Decode.scala:50:77] assign rrd_cs_decoder_8 = rrd_cs_decoder_decoded[6:4]; // @[pla.scala:81:23] assign rrd_cs_imm_sel = rrd_cs_decoder_8; // @[Decode.scala:50:77] assign rrd_cs_decoder_9 = rrd_cs_decoder_decoded[3]; // @[pla.scala:81:23] assign rrd_cs_rf_wen = rrd_cs_decoder_9; // @[Decode.scala:50:77] assign rrd_cs_decoder_10 = rrd_cs_decoder_decoded[2:0]; // @[pla.scala:81:23] assign rrd_cs_csr_cmd = rrd_cs_decoder_10; // @[Decode.scala:50:77] assign rrd_cs_op_fcn = {1'h0, rrd_cs_decoder_4}; // @[Decode.scala:50:77] assign _io_rrd_uop_ctrl_is_load_T = io_rrd_uop_uopc_0 == 7'h1; // @[func-unit-decode.scala:307:7, :339:46] assign io_rrd_uop_ctrl_is_load_0 = _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:307:7, :339:46] wire _io_rrd_uop_ctrl_is_sta_T = io_rrd_uop_uopc_0 == 7'h2; // @[func-unit-decode.scala:307:7, :340:46] wire _io_rrd_uop_ctrl_is_sta_T_1 = io_rrd_uop_uopc_0 == 7'h43; // @[func-unit-decode.scala:307:7, :340:76] assign _io_rrd_uop_ctrl_is_sta_T_2 = _io_rrd_uop_ctrl_is_sta_T | _io_rrd_uop_ctrl_is_sta_T_1; // @[func-unit-decode.scala:340:{46,57,76}] assign io_rrd_uop_ctrl_is_sta_0 = _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:307:7, :340:57] wire _io_rrd_uop_ctrl_is_std_T = io_rrd_uop_uopc_0 == 7'h3; // @[func-unit-decode.scala:307:7, :341:46] wire _io_rrd_uop_ctrl_is_std_T_1 = io_rrd_uop_lrs2_rtype_0 == 2'h0; // @[func-unit-decode.scala:307:7, :341:109] wire _io_rrd_uop_ctrl_is_std_T_2 = io_rrd_uop_ctrl_is_sta_0 & _io_rrd_uop_ctrl_is_std_T_1; // @[func-unit-decode.scala:307:7, :341:{84,109}] assign _io_rrd_uop_ctrl_is_std_T_3 = _io_rrd_uop_ctrl_is_std_T | _io_rrd_uop_ctrl_is_std_T_2; // @[func-unit-decode.scala:341:{46,57,84}] assign io_rrd_uop_ctrl_is_std_0 = _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:307:7, :341:57] assign io_rrd_uop_imm_packed_0 = _io_rrd_uop_ctrl_is_sta_T_1 | _io_rrd_uop_ctrl_is_load_T & io_rrd_uop_mem_cmd_0 == 5'h6 ? 20'h0 : io_iss_uop_imm_packed_0; // @[func-unit-decode.scala:307:7, :320:16, :339:46, :340:76, :343:{39,69,91,103}, :344:27] wire _csr_ren_T = rrd_cs_csr_cmd == 3'h6; // @[func-unit-decode.scala:330:20, :348:33] wire _csr_ren_T_1 = &rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:61] wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[func-unit-decode.scala:348:{33,43,61}] wire _csr_ren_T_3 = io_rrd_uop_prs1_0 == 7'h0; // @[pla.scala:114:36] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[func-unit-decode.scala:348:{43,72,82}] assign _io_rrd_uop_ctrl_csr_cmd_T = csr_ren ? 3'h2 : rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:72, :349:33] assign io_rrd_uop_ctrl_csr_cmd_0 = _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:307:7, :349:33] assign io_rrd_valid = io_rrd_valid_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uopc = io_rrd_uop_uopc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_inst = io_rrd_uop_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_inst = io_rrd_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_rvc = io_rrd_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_pc = io_rrd_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iq_type = io_rrd_uop_iq_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fu_code = io_rrd_uop_fu_code_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_br_type = io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op1_sel = io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op2_sel = io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_imm_sel = io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op_fcn = io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_fcn_dw = io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_csr_cmd = io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_load = io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_sta = io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_std = io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iw_state = io_rrd_uop_iw_state_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_br = io_rrd_uop_is_br_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jalr = io_rrd_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jal = io_rrd_uop_is_jal_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sfb = io_rrd_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_mask = io_rrd_uop_br_mask_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_tag = io_rrd_uop_br_tag_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ftq_idx = io_rrd_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_edge_inst = io_rrd_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pc_lob = io_rrd_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_taken = io_rrd_uop_taken_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_imm_packed = io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_csr_addr = io_rrd_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rob_idx = io_rrd_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldq_idx = io_rrd_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stq_idx = io_rrd_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rxq_idx = io_rrd_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pdst = io_rrd_uop_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1 = io_rrd_uop_prs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2 = io_rrd_uop_prs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3 = io_rrd_uop_prs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred = io_rrd_uop_ppred_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1_busy = io_rrd_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2_busy = io_rrd_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3_busy = io_rrd_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred_busy = io_rrd_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stale_pdst = io_rrd_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exception = io_rrd_uop_exception_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exc_cause = io_rrd_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bypassable = io_rrd_uop_bypassable_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_cmd = io_rrd_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_size = io_rrd_uop_mem_size_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_signed = io_rrd_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fence = io_rrd_uop_is_fence_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fencei = io_rrd_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_amo = io_rrd_uop_is_amo_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_ldq = io_rrd_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_stq = io_rrd_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sys_pc2epc = io_rrd_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_unique = io_rrd_uop_is_unique_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_flush_on_commit = io_rrd_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_is_rs1 = io_rrd_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst = io_rrd_uop_ldst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1 = io_rrd_uop_lrs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2 = io_rrd_uop_lrs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs3 = io_rrd_uop_lrs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_val = io_rrd_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_dst_rtype = io_rrd_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1_rtype = io_rrd_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2_rtype = io_rrd_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_frs3_en = io_rrd_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_val = io_rrd_uop_fp_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_single = io_rrd_uop_fp_single_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_pf_if = io_rrd_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ae_if = io_rrd_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ma_if = io_rrd_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_debug_if = io_rrd_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_xcpt_if = io_rrd_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_fsrc = io_rrd_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_tsrc = io_rrd_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLSlaveToNoC_6 : input clock : Clock input reset : Reset output io : { tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flits : { flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}} inst a of TLAFromNoC_6 connect a.clock, clock connect a.reset, reset inst b of TLBToNoC_6 connect b.clock, clock connect b.reset, reset inst c of TLCFromNoC_6 connect c.clock, clock connect c.reset, reset inst d of TLDToNoC_6 connect d.clock, clock connect d.reset, reset inst e of TLEFromNoC_6 connect e.clock, clock connect e.reset, reset connect io.tilelink.a.bits, a.io.protocol.bits connect io.tilelink.a.valid, a.io.protocol.valid connect a.io.protocol.ready, io.tilelink.a.ready wire _b_io_protocol_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _b_io_protocol_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_io_protocol_WIRE.bits.data, UInt<64>(0h0) connect _b_io_protocol_WIRE.bits.mask, UInt<8>(0h0) connect _b_io_protocol_WIRE.bits.address, UInt<29>(0h0) connect _b_io_protocol_WIRE.bits.source, UInt<7>(0h0) connect _b_io_protocol_WIRE.bits.size, UInt<4>(0h0) connect _b_io_protocol_WIRE.bits.param, UInt<2>(0h0) connect _b_io_protocol_WIRE.bits.opcode, UInt<3>(0h0) connect _b_io_protocol_WIRE.valid, UInt<1>(0h0) connect _b_io_protocol_WIRE.ready, UInt<1>(0h0) wire _b_io_protocol_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _b_io_protocol_WIRE_1.bits, _b_io_protocol_WIRE.bits connect _b_io_protocol_WIRE_1.valid, _b_io_protocol_WIRE.valid connect _b_io_protocol_WIRE_1.ready, _b_io_protocol_WIRE.ready connect b.io.protocol, _b_io_protocol_WIRE_1 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<3>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.bits, c.io.protocol.bits connect _WIRE_1.valid, c.io.protocol.valid connect c.io.protocol.ready, _WIRE_1.ready connect d.io.protocol, io.tilelink.d wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_2.bits.sink, UInt<1>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.bits, e.io.protocol.bits connect _WIRE_3.valid, e.io.protocol.valid connect e.io.protocol.ready, _WIRE_3.ready connect a.io.flit, io.flits.a connect io.flits.b.bits, b.io.flit.bits connect io.flits.b.valid, b.io.flit.valid connect b.io.flit.ready, io.flits.b.ready connect c.io.flit, io.flits.c connect io.flits.d.bits, d.io.flit.bits connect io.flits.d.valid, d.io.flit.valid connect d.io.flit.ready, io.flits.d.ready connect e.io.flit, io.flits.e
module TLSlaveToNoC_6( // @[Tilelink.scala:125:7] input clock, // @[Tilelink.scala:125:7] input reset, // @[Tilelink.scala:125:7] input io_tilelink_a_ready, // @[Tilelink.scala:132:14] output io_tilelink_a_valid, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:132:14] output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:132:14] output [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:132:14] output [28:0] io_tilelink_a_bits_address, // @[Tilelink.scala:132:14] output [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:132:14] output [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:132:14] output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:132:14] output io_tilelink_d_ready, // @[Tilelink.scala:132:14] input io_tilelink_d_valid, // @[Tilelink.scala:132:14] input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:132:14] input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:132:14] input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:132:14] input [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:132:14] input io_tilelink_d_bits_sink, // @[Tilelink.scala:132:14] input io_tilelink_d_bits_denied, // @[Tilelink.scala:132:14] input [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:132:14] input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:132:14] output io_flits_a_ready, // @[Tilelink.scala:132:14] input io_flits_a_valid, // @[Tilelink.scala:132:14] input io_flits_a_bits_head, // @[Tilelink.scala:132:14] input io_flits_a_bits_tail, // @[Tilelink.scala:132:14] input [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:132:14] output io_flits_c_ready, // @[Tilelink.scala:132:14] input io_flits_c_valid, // @[Tilelink.scala:132:14] input io_flits_c_bits_head, // @[Tilelink.scala:132:14] input io_flits_c_bits_tail, // @[Tilelink.scala:132:14] input io_flits_d_ready, // @[Tilelink.scala:132:14] output io_flits_d_valid, // @[Tilelink.scala:132:14] output io_flits_d_bits_head, // @[Tilelink.scala:132:14] output io_flits_d_bits_tail, // @[Tilelink.scala:132:14] output [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:132:14] output io_flits_e_ready, // @[Tilelink.scala:132:14] input io_flits_e_valid, // @[Tilelink.scala:132:14] input io_flits_e_bits_head, // @[Tilelink.scala:132:14] input io_flits_e_bits_tail // @[Tilelink.scala:132:14] ); wire [64:0] _d_io_flit_bits_payload; // @[Tilelink.scala:146:17] TLAFromNoC_5 a ( // @[Tilelink.scala:143:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload) ); // @[Tilelink.scala:143:17] TLCFromNoC_5 c ( // @[Tilelink.scala:145:17] .clock (clock), .reset (reset), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail) ); // @[Tilelink.scala:145:17] TLDToNoC_6 d ( // @[Tilelink.scala:146:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (_d_io_flit_bits_payload) ); // @[Tilelink.scala:146:17] TLEFromNoC_5 e ( // @[Tilelink.scala:147:17] .clock (clock), .reset (reset), .io_flit_ready (io_flits_e_ready), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_tail (io_flits_e_bits_tail) ); // @[Tilelink.scala:147:17] assign io_flits_d_bits_payload = {8'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:125:7, :146:17, :157:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_133 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_133( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TageTable_22 : input clock : Clock input reset : Reset output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f3_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<7>(0h7f)) when _T : connect doing_reset, UInt<1>(0h0) node _T_1 = shr(io.f1_req_pc, 4) node idx_history_hist_chunks_0 = bits(io.f1_req_ghist, 6, 0) node idx_history_hist_chunks_1 = bits(io.f1_req_ghist, 13, 7) node idx_history_hist_chunks_2 = bits(io.f1_req_ghist, 20, 14) node idx_history_hist_chunks_3 = bits(io.f1_req_ghist, 27, 21) node idx_history_hist_chunks_4 = bits(io.f1_req_ghist, 31, 28) node _idx_history_T = xor(idx_history_hist_chunks_0, idx_history_hist_chunks_1) node _idx_history_T_1 = xor(_idx_history_T, idx_history_hist_chunks_2) node _idx_history_T_2 = xor(_idx_history_T_1, idx_history_hist_chunks_3) node idx_history = xor(_idx_history_T_2, idx_history_hist_chunks_4) node _idx_T = xor(_T_1, idx_history) node s1_hashed_idx = bits(_idx_T, 6, 0) node tag_history_hist_chunks_0 = bits(io.f1_req_ghist, 8, 0) node tag_history_hist_chunks_1 = bits(io.f1_req_ghist, 17, 9) node tag_history_hist_chunks_2 = bits(io.f1_req_ghist, 26, 18) node tag_history_hist_chunks_3 = bits(io.f1_req_ghist, 31, 27) node _tag_history_T = xor(tag_history_hist_chunks_0, tag_history_hist_chunks_1) node _tag_history_T_1 = xor(_tag_history_T, tag_history_hist_chunks_2) node tag_history = xor(_tag_history_T_1, tag_history_hist_chunks_3) node _tag_T = shr(_T_1, 7) node _tag_T_1 = xor(_tag_T, tag_history) node s1_tag = bits(_tag_T_1, 8, 0) smem hi_us : UInt<1>[4] [128] smem lo_us : UInt<1>[4] [128] smem table : UInt<13>[4] [128] reg s2_tag : UInt, clock connect s2_tag, s1_tag wire _s2_req_rtage_WIRE : UInt<7> invalidate _s2_req_rtage_WIRE when io.f1_req_valid : connect _s2_req_rtage_WIRE, s1_hashed_idx read mport s2_req_rtage_MPORT = table[_s2_req_rtage_WIRE], clock wire _s2_req_rtage_WIRE_1 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_2 : UInt<13> connect _s2_req_rtage_WIRE_2, s2_req_rtage_MPORT[0] node _s2_req_rtage_T = bits(_s2_req_rtage_WIRE_2, 2, 0) connect _s2_req_rtage_WIRE_1.ctr, _s2_req_rtage_T node _s2_req_rtage_T_1 = bits(_s2_req_rtage_WIRE_2, 11, 3) connect _s2_req_rtage_WIRE_1.tag, _s2_req_rtage_T_1 node _s2_req_rtage_T_2 = bits(_s2_req_rtage_WIRE_2, 12, 12) connect _s2_req_rtage_WIRE_1.valid, _s2_req_rtage_T_2 wire _s2_req_rtage_WIRE_3 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_4 : UInt<13> connect _s2_req_rtage_WIRE_4, s2_req_rtage_MPORT[1] node _s2_req_rtage_T_3 = bits(_s2_req_rtage_WIRE_4, 2, 0) connect _s2_req_rtage_WIRE_3.ctr, _s2_req_rtage_T_3 node _s2_req_rtage_T_4 = bits(_s2_req_rtage_WIRE_4, 11, 3) connect _s2_req_rtage_WIRE_3.tag, _s2_req_rtage_T_4 node _s2_req_rtage_T_5 = bits(_s2_req_rtage_WIRE_4, 12, 12) connect _s2_req_rtage_WIRE_3.valid, _s2_req_rtage_T_5 wire _s2_req_rtage_WIRE_5 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_6 : UInt<13> connect _s2_req_rtage_WIRE_6, s2_req_rtage_MPORT[2] node _s2_req_rtage_T_6 = bits(_s2_req_rtage_WIRE_6, 2, 0) connect _s2_req_rtage_WIRE_5.ctr, _s2_req_rtage_T_6 node _s2_req_rtage_T_7 = bits(_s2_req_rtage_WIRE_6, 11, 3) connect _s2_req_rtage_WIRE_5.tag, _s2_req_rtage_T_7 node _s2_req_rtage_T_8 = bits(_s2_req_rtage_WIRE_6, 12, 12) connect _s2_req_rtage_WIRE_5.valid, _s2_req_rtage_T_8 wire _s2_req_rtage_WIRE_7 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_8 : UInt<13> connect _s2_req_rtage_WIRE_8, s2_req_rtage_MPORT[3] node _s2_req_rtage_T_9 = bits(_s2_req_rtage_WIRE_8, 2, 0) connect _s2_req_rtage_WIRE_7.ctr, _s2_req_rtage_T_9 node _s2_req_rtage_T_10 = bits(_s2_req_rtage_WIRE_8, 11, 3) connect _s2_req_rtage_WIRE_7.tag, _s2_req_rtage_T_10 node _s2_req_rtage_T_11 = bits(_s2_req_rtage_WIRE_8, 12, 12) connect _s2_req_rtage_WIRE_7.valid, _s2_req_rtage_T_11 wire s2_req_rtage : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}[4] connect s2_req_rtage[0].ctr, _s2_req_rtage_WIRE_1.ctr connect s2_req_rtage[0].tag, _s2_req_rtage_WIRE_1.tag connect s2_req_rtage[0].valid, _s2_req_rtage_WIRE_1.valid connect s2_req_rtage[1].ctr, _s2_req_rtage_WIRE_3.ctr connect s2_req_rtage[1].tag, _s2_req_rtage_WIRE_3.tag connect s2_req_rtage[1].valid, _s2_req_rtage_WIRE_3.valid connect s2_req_rtage[2].ctr, _s2_req_rtage_WIRE_5.ctr connect s2_req_rtage[2].tag, _s2_req_rtage_WIRE_5.tag connect s2_req_rtage[2].valid, _s2_req_rtage_WIRE_5.valid connect s2_req_rtage[3].ctr, _s2_req_rtage_WIRE_7.ctr connect s2_req_rtage[3].tag, _s2_req_rtage_WIRE_7.tag connect s2_req_rtage[3].valid, _s2_req_rtage_WIRE_7.valid wire _s2_req_rhius_WIRE : UInt<7> invalidate _s2_req_rhius_WIRE when io.f1_req_valid : connect _s2_req_rhius_WIRE, s1_hashed_idx read mport s2_req_rhius = hi_us[_s2_req_rhius_WIRE], clock wire _s2_req_rlous_WIRE : UInt<7> invalidate _s2_req_rlous_WIRE when io.f1_req_valid : connect _s2_req_rlous_WIRE, s1_hashed_idx read mport s2_req_rlous = lo_us[_s2_req_rlous_WIRE], clock node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag) node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T) node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2) node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag) node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4) node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6) node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag) node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8) node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10) node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag) node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12) node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14) wire s2_req_rhits : UInt<1>[4] connect s2_req_rhits[0], _s2_req_rhits_T_3 connect s2_req_rhits[1], _s2_req_rhits_T_7 connect s2_req_rhits[2], _s2_req_rhits_T_11 connect s2_req_rhits[3], _s2_req_rhits_T_15 reg io_f3_resp_0_valid_REG : UInt<1>, clock connect io_f3_resp_0_valid_REG, s2_req_rhits[0] connect io.f3_resp[0].valid, io_f3_resp_0_valid_REG node _io_f3_resp_0_bits_u_T = cat(s2_req_rhius[0], s2_req_rlous[0]) reg io_f3_resp_0_bits_u_REG : UInt, clock connect io_f3_resp_0_bits_u_REG, _io_f3_resp_0_bits_u_T connect io.f3_resp[0].bits.u, io_f3_resp_0_bits_u_REG reg io_f3_resp_0_bits_ctr_REG : UInt, clock connect io_f3_resp_0_bits_ctr_REG, s2_req_rtage[0].ctr connect io.f3_resp[0].bits.ctr, io_f3_resp_0_bits_ctr_REG reg io_f3_resp_1_valid_REG : UInt<1>, clock connect io_f3_resp_1_valid_REG, s2_req_rhits[1] connect io.f3_resp[1].valid, io_f3_resp_1_valid_REG node _io_f3_resp_1_bits_u_T = cat(s2_req_rhius[1], s2_req_rlous[1]) reg io_f3_resp_1_bits_u_REG : UInt, clock connect io_f3_resp_1_bits_u_REG, _io_f3_resp_1_bits_u_T connect io.f3_resp[1].bits.u, io_f3_resp_1_bits_u_REG reg io_f3_resp_1_bits_ctr_REG : UInt, clock connect io_f3_resp_1_bits_ctr_REG, s2_req_rtage[1].ctr connect io.f3_resp[1].bits.ctr, io_f3_resp_1_bits_ctr_REG reg io_f3_resp_2_valid_REG : UInt<1>, clock connect io_f3_resp_2_valid_REG, s2_req_rhits[2] connect io.f3_resp[2].valid, io_f3_resp_2_valid_REG node _io_f3_resp_2_bits_u_T = cat(s2_req_rhius[2], s2_req_rlous[2]) reg io_f3_resp_2_bits_u_REG : UInt, clock connect io_f3_resp_2_bits_u_REG, _io_f3_resp_2_bits_u_T connect io.f3_resp[2].bits.u, io_f3_resp_2_bits_u_REG reg io_f3_resp_2_bits_ctr_REG : UInt, clock connect io_f3_resp_2_bits_ctr_REG, s2_req_rtage[2].ctr connect io.f3_resp[2].bits.ctr, io_f3_resp_2_bits_ctr_REG reg io_f3_resp_3_valid_REG : UInt<1>, clock connect io_f3_resp_3_valid_REG, s2_req_rhits[3] connect io.f3_resp[3].valid, io_f3_resp_3_valid_REG node _io_f3_resp_3_bits_u_T = cat(s2_req_rhius[3], s2_req_rlous[3]) reg io_f3_resp_3_bits_u_REG : UInt, clock connect io_f3_resp_3_bits_u_REG, _io_f3_resp_3_bits_u_T connect io.f3_resp[3].bits.u, io_f3_resp_3_bits_u_REG reg io_f3_resp_3_bits_ctr_REG : UInt, clock connect io_f3_resp_3_bits_ctr_REG, s2_req_rtage[3].ctr connect io.f3_resp[3].bits.ctr, io_f3_resp_3_bits_ctr_REG regreset clear_u_ctr : UInt<19>, clock, reset, UInt<19>(0h0) when doing_reset : connect clear_u_ctr, UInt<1>(0h1) else : node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1)) node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1) connect clear_u_ctr, _clear_u_ctr_T_1 node _doing_clear_u_T = bits(clear_u_ctr, 10, 0) node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0)) node _doing_clear_u_hi_T = bits(clear_u_ctr, 18, 18) node _doing_clear_u_hi_T_1 = eq(_doing_clear_u_hi_T, UInt<1>(0h1)) node doing_clear_u_hi = and(doing_clear_u, _doing_clear_u_hi_T_1) node _doing_clear_u_lo_T = bits(clear_u_ctr, 18, 18) node _doing_clear_u_lo_T_1 = eq(_doing_clear_u_lo_T, UInt<1>(0h0)) node doing_clear_u_lo = and(doing_clear_u, _doing_clear_u_lo_T_1) node clear_u_idx = shr(clear_u_ctr, 11) node _T_2 = shr(io.update_pc, 4) node idx_history_hist_chunks_0_1 = bits(io.update_hist, 6, 0) node idx_history_hist_chunks_1_1 = bits(io.update_hist, 13, 7) node idx_history_hist_chunks_2_1 = bits(io.update_hist, 20, 14) node idx_history_hist_chunks_3_1 = bits(io.update_hist, 27, 21) node idx_history_hist_chunks_4_1 = bits(io.update_hist, 31, 28) node _idx_history_T_3 = xor(idx_history_hist_chunks_0_1, idx_history_hist_chunks_1_1) node _idx_history_T_4 = xor(_idx_history_T_3, idx_history_hist_chunks_2_1) node _idx_history_T_5 = xor(_idx_history_T_4, idx_history_hist_chunks_3_1) node idx_history_1 = xor(_idx_history_T_5, idx_history_hist_chunks_4_1) node _idx_T_1 = xor(_T_2, idx_history_1) node update_idx = bits(_idx_T_1, 6, 0) node tag_history_hist_chunks_0_1 = bits(io.update_hist, 8, 0) node tag_history_hist_chunks_1_1 = bits(io.update_hist, 17, 9) node tag_history_hist_chunks_2_1 = bits(io.update_hist, 26, 18) node tag_history_hist_chunks_3_1 = bits(io.update_hist, 31, 27) node _tag_history_T_2 = xor(tag_history_hist_chunks_0_1, tag_history_hist_chunks_1_1) node _tag_history_T_3 = xor(_tag_history_T_2, tag_history_hist_chunks_2_1) node tag_history_1 = xor(_tag_history_T_3, tag_history_hist_chunks_3_1) node _tag_T_2 = shr(_T_2, 7) node _tag_T_3 = xor(_tag_T_2, tag_history_1) node update_tag = bits(_tag_T_3, 8, 0) wire update_wdata : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}[4] node _T_3 = mux(doing_reset, reset_idx, update_idx) wire _WIRE : UInt<13>[4] connect _WIRE[0], UInt<13>(0h0) connect _WIRE[1], UInt<13>(0h0) connect _WIRE[2], UInt<13>(0h0) connect _WIRE[3], UInt<13>(0h0) node hi = cat(update_wdata[0].valid, update_wdata[0].tag) node _T_4 = cat(hi, update_wdata[0].ctr) node hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag) node _T_5 = cat(hi_1, update_wdata[1].ctr) node hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag) node _T_6 = cat(hi_2, update_wdata[2].ctr) node hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag) node _T_7 = cat(hi_3, update_wdata[3].ctr) wire _WIRE_1 : UInt<13>[4] connect _WIRE_1[0], _T_4 connect _WIRE_1[1], _T_5 connect _WIRE_1[2], _T_6 connect _WIRE_1[3], _T_7 node _T_8 = mux(doing_reset, _WIRE, _WIRE_1) node _T_9 = not(UInt<4>(0h0)) node lo = cat(io.update_mask[1], io.update_mask[0]) node hi_4 = cat(io.update_mask[3], io.update_mask[2]) node _T_10 = cat(hi_4, lo) node _T_11 = mux(doing_reset, _T_9, _T_10) node _T_12 = bits(_T_11, 0, 0) node _T_13 = bits(_T_11, 1, 1) node _T_14 = bits(_T_11, 2, 2) node _T_15 = bits(_T_11, 3, 3) write mport MPORT = table[_T_3], clock when _T_12 : connect MPORT[0], _T_8[0] when _T_13 : connect MPORT[1], _T_8[1] when _T_14 : connect MPORT[2], _T_8[2] when _T_15 : connect MPORT[3], _T_8[3] wire update_hi_wdata : UInt<1>[4] node _T_16 = mux(doing_clear_u_hi, clear_u_idx, update_idx) node _T_17 = mux(doing_reset, reset_idx, _T_16) node _T_18 = or(doing_reset, doing_clear_u_hi) wire _WIRE_2 : UInt<1>[4] connect _WIRE_2[0], UInt<1>(0h0) connect _WIRE_2[1], UInt<1>(0h0) connect _WIRE_2[2], UInt<1>(0h0) connect _WIRE_2[3], UInt<1>(0h0) node _T_19 = mux(_T_18, _WIRE_2, update_hi_wdata) node _T_20 = or(doing_reset, doing_clear_u_hi) node _T_21 = not(UInt<4>(0h0)) node lo_1 = cat(io.update_u_mask[1], io.update_u_mask[0]) node hi_5 = cat(io.update_u_mask[3], io.update_u_mask[2]) node _T_22 = cat(hi_5, lo_1) node _T_23 = mux(_T_20, _T_21, _T_22) node _T_24 = bits(_T_23, 0, 0) node _T_25 = bits(_T_23, 1, 1) node _T_26 = bits(_T_23, 2, 2) node _T_27 = bits(_T_23, 3, 3) node _T_28 = bits(_T_17, 6, 0) write mport MPORT_1 = hi_us[_T_28], clock when _T_24 : connect MPORT_1[0], _T_19[0] when _T_25 : connect MPORT_1[1], _T_19[1] when _T_26 : connect MPORT_1[2], _T_19[2] when _T_27 : connect MPORT_1[3], _T_19[3] wire update_lo_wdata : UInt<1>[4] node _T_29 = mux(doing_clear_u_lo, clear_u_idx, update_idx) node _T_30 = mux(doing_reset, reset_idx, _T_29) node _T_31 = or(doing_reset, doing_clear_u_lo) wire _WIRE_3 : UInt<1>[4] connect _WIRE_3[0], UInt<1>(0h0) connect _WIRE_3[1], UInt<1>(0h0) connect _WIRE_3[2], UInt<1>(0h0) connect _WIRE_3[3], UInt<1>(0h0) node _T_32 = mux(_T_31, _WIRE_3, update_lo_wdata) node _T_33 = or(doing_reset, doing_clear_u_lo) node _T_34 = not(UInt<4>(0h0)) node lo_2 = cat(io.update_u_mask[1], io.update_u_mask[0]) node hi_6 = cat(io.update_u_mask[3], io.update_u_mask[2]) node _T_35 = cat(hi_6, lo_2) node _T_36 = mux(_T_33, _T_34, _T_35) node _T_37 = bits(_T_36, 0, 0) node _T_38 = bits(_T_36, 1, 1) node _T_39 = bits(_T_36, 2, 2) node _T_40 = bits(_T_36, 3, 3) node _T_41 = bits(_T_30, 6, 0) write mport MPORT_2 = lo_us[_T_41], clock when _T_37 : connect MPORT_2[0], _T_32[0] when _T_38 : connect MPORT_2[1], _T_32[1] when _T_39 : connect MPORT_2[2], _T_32[2] when _T_40 : connect MPORT_2[3], _T_32[3] reg wrbypass_tags : UInt<9>[2], clock reg wrbypass_idxs : UInt<7>[2], clock reg wrbypass : UInt<3>[4][2], clock regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0) node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag) node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1) node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx) node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3) node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag) node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6) node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx) node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8) wire wrbypass_hits : UInt<1>[2] connect wrbypass_hits[0], _wrbypass_hits_T_4 connect wrbypass_hits[1], _wrbypass_hits_T_9 node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1]) node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1)) node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1) node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4) node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1) node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8) node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9) node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1) node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14) node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1) node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18) node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19) node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20) node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21) connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22 connect update_wdata[0].valid, UInt<1>(0h1) connect update_wdata[0].tag, update_tag node _update_hi_wdata_0_T = bits(io.update_u[0], 1, 1) connect update_hi_wdata[0], _update_hi_wdata_0_T node _update_lo_wdata_0_T = bits(io.update_u[0], 0, 0) connect update_lo_wdata[0], _update_lo_wdata_0_T node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1) node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4) node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1) node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8) node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9) node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1) node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14) node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1) node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18) node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19) node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20) node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21) connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22 connect update_wdata[1].valid, UInt<1>(0h1) connect update_wdata[1].tag, update_tag node _update_hi_wdata_1_T = bits(io.update_u[1], 1, 1) connect update_hi_wdata[1], _update_hi_wdata_1_T node _update_lo_wdata_1_T = bits(io.update_u[1], 0, 0) connect update_lo_wdata[1], _update_lo_wdata_1_T node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1) node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4) node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1) node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8) node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9) node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1) node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14) node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1) node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18) node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19) node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20) node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21) connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22 connect update_wdata[2].valid, UInt<1>(0h1) connect update_wdata[2].tag, update_tag node _update_hi_wdata_2_T = bits(io.update_u[2], 1, 1) connect update_hi_wdata[2], _update_hi_wdata_2_T node _update_lo_wdata_2_T = bits(io.update_u[2], 0, 0) connect update_lo_wdata[2], _update_lo_wdata_2_T node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1) node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4) node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1) node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8) node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9) node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1) node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14) node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1) node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18) node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19) node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20) node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21) connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22 connect update_wdata[3].valid, UInt<1>(0h1) connect update_wdata[3].tag, update_tag node _update_hi_wdata_3_T = bits(io.update_u[3], 1, 1) connect update_hi_wdata[3], _update_hi_wdata_3_T node _update_lo_wdata_3_T = bits(io.update_u[3], 0, 0) connect update_lo_wdata[3], _update_lo_wdata_3_T node _T_42 = or(io.update_mask[0], io.update_mask[1]) node _T_43 = or(_T_42, io.update_mask[2]) node _T_44 = or(_T_43, io.update_mask[3]) when _T_44 : node _T_45 = or(wrbypass_hits[0], wrbypass_hits[1]) when _T_45 : wire _WIRE_4 : UInt<3>[4] connect _WIRE_4[0], update_wdata[0].ctr connect _WIRE_4[1], update_wdata[1].ctr connect _WIRE_4[2], update_wdata[2].ctr connect _WIRE_4[3], update_wdata[3].ctr connect wrbypass[wrbypass_hit_idx], _WIRE_4 else : wire _WIRE_5 : UInt<3>[4] connect _WIRE_5[0], update_wdata[0].ctr connect _WIRE_5[1], update_wdata[1].ctr connect _WIRE_5[2], update_wdata[2].ctr connect _WIRE_5[3], update_wdata[3].ctr connect wrbypass[wrbypass_enq_idx], _WIRE_5 connect wrbypass_tags[wrbypass_enq_idx], update_tag connect wrbypass_idxs[wrbypass_enq_idx], update_idx node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1)) node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1) node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0) connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2
module TageTable_22( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f3_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14] output io_f3_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14] output io_f3_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14] output io_f3_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8] wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8] wire [12:0] table_MPORT_data_3; // @[tage.scala:123:8] wire [12:0] table_MPORT_data_2; // @[tage.scala:123:8] wire [12:0] table_MPORT_data_1; // @[tage.scala:123:8] wire [12:0] table_MPORT_data_0; // @[tage.scala:123:8] wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87] wire [51:0] _table_R0_data; // @[tage.scala:91:27] wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27] wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26] wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [6:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2 = io_f1_req_ghist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3 = io_f1_req_ghist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [3:0] idx_history_hist_chunks_4 = io_f1_req_ghist_0[31:28]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_1 = _idx_history_T ^ idx_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_2 = _idx_history_T_1 ^ idx_history_hist_chunks_3; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history = {_idx_history_T_2[6:4], _idx_history_T_2[3:0] ^ idx_history_hist_chunks_4}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T = io_f1_req_pc_0[39:11]; // @[frontend.scala:162:35] wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[10:4] ^ idx_history}; // @[frontend.scala:162:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40] wire [6:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32] wire [6:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32] wire [8:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2 = io_f1_req_ghist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [4:0] tag_history_hist_chunks_3 = io_f1_req_ghist_0[31:27]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_1 = _tag_history_T ^ tag_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history = {_tag_history_T_1[8:5], _tag_history_T_1[4:0] ^ tag_history_hist_chunks_3}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_1 = {_tag_T[28:9], _tag_T[8:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] s1_tag = _tag_T_1[8:0]; // @[tage.scala:62:{50,64}] wire [12:0] _s2_req_rtage_WIRE_2 = _table_R0_data[12:0]; // @[tage.scala:91:27, :97:87] wire [12:0] _s2_req_rtage_WIRE_4 = _table_R0_data[25:13]; // @[tage.scala:91:27, :97:87] wire [12:0] _s2_req_rtage_WIRE_6 = _table_R0_data[38:26]; // @[tage.scala:91:27, :97:87] wire [12:0] _s2_req_rtage_WIRE_8 = _table_R0_data[51:39]; // @[tage.scala:91:27, :97:87] reg [8:0] s2_tag; // @[tage.scala:95:29] wire _s2_req_rtage_T_2; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_T_1; // @[tage.scala:97:87] wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87] wire [8:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87] assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[11:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87] assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[12]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87] wire _s2_req_rtage_T_5; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_T_4; // @[tage.scala:97:87] wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87] wire [8:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87] assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[11:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87] assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[12]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87] wire _s2_req_rtage_T_8; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_T_7; // @[tage.scala:97:87] wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87] wire [8:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87] assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[11:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87] assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[12]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87] wire _s2_req_rtage_T_11; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_T_10; // @[tage.scala:97:87] wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87] wire [8:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87] assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[11:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87] assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[12]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _doing_clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54] wire _doing_clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54, :114:54] wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}] wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}] wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}] wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [6:0] idx_history_hist_chunks_0_1 = io_update_hist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1_1 = io_update_hist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2_1 = io_update_hist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3_1 = io_update_hist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [3:0] idx_history_hist_chunks_4_1 = io_update_hist_0[31:28]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T_3 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_4 = _idx_history_T_3 ^ idx_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_5 = _idx_history_T_4 ^ idx_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history_1 = {_idx_history_T_5[6:4], _idx_history_T_5[3:0] ^ idx_history_hist_chunks_4_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_2 = io_update_pc_0[39:11]; // @[frontend.scala:162:35] wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[10:4] ^ idx_history_1}; // @[frontend.scala:162:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [8:0] tag_history_hist_chunks_0_1 = io_update_hist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1_1 = io_update_hist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2_1 = io_update_hist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [4:0] tag_history_hist_chunks_3_1 = io_update_hist_0[31:27]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T_2 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_3 = _tag_history_T_2 ^ tag_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history_1 = {_tag_history_T_3[8:5], _tag_history_T_3[4:0] ^ tag_history_hist_chunks_3_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_3 = {_tag_T_2[28:9], _tag_T_2[8:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] update_tag = _tag_T_3[8:0]; // @[tage.scala:62:{50,64}] wire [8:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [8:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [8:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [8:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26] wire [9:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102] wire [9:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102] wire [9:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102] wire [9:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102] assign table_MPORT_data_0 = doing_reset ? 13'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_1 = doing_reset ? 13'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_2 = doing_reset ? 13'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_3 = doing_reset ? 13'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90] wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90] wire _update_hi_wdata_0_T; // @[tage.scala:166:44] wire _update_hi_wdata_1_T; // @[tage.scala:166:44] wire _update_hi_wdata_2_T; // @[tage.scala:166:44] wire _update_hi_wdata_3_T; // @[tage.scala:166:44] wire update_hi_wdata_0; // @[tage.scala:127:29] wire update_hi_wdata_1; // @[tage.scala:127:29] wire update_hi_wdata_2; // @[tage.scala:127:29] wire update_hi_wdata_3; // @[tage.scala:127:29] wire _T_20 = doing_reset | doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21] assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}] wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80] wire [1:0] lo_1; // @[tage.scala:131:80] assign lo_1 = _GEN; // @[tage.scala:131:80] wire [1:0] lo_2; // @[tage.scala:138:80] assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80] wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80] wire [1:0] hi_5; // @[tage.scala:131:80] assign hi_5 = _GEN_0; // @[tage.scala:131:80] wire [1:0] hi_6; // @[tage.scala:138:80] assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80] wire _update_lo_wdata_0_T; // @[tage.scala:167:44] wire _update_lo_wdata_1_T; // @[tage.scala:167:44] wire _update_lo_wdata_2_T; // @[tage.scala:167:44] wire _update_lo_wdata_3_T; // @[tage.scala:167:44] wire update_lo_wdata_0; // @[tage.scala:134:29] wire update_lo_wdata_1; // @[tage.scala:134:29] wire update_lo_wdata_2; // @[tage.scala:134:29] wire update_lo_wdata_3; // @[tage.scala:134:29] wire _T_33 = doing_reset | doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21] assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}] reg [8:0] wrbypass_tags_0; // @[tage.scala:141:29] reg [8:0] wrbypass_tags_1; // @[tage.scala:141:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:142:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:142:29] reg [2:0] wrbypass_0_0; // @[tage.scala:143:29] reg [2:0] wrbypass_0_1; // @[tage.scala:143:29] reg [2:0] wrbypass_0_2; // @[tage.scala:143:29] reg [2:0] wrbypass_0_3; // @[tage.scala:143:29] reg [2:0] wrbypass_1_0; // @[tage.scala:143:29] reg [2:0] wrbypass_1_1; // @[tage.scala:143:29] reg [2:0] wrbypass_1_2; // @[tage.scala:143:29] reg [2:0] wrbypass_1_3; // @[tage.scala:143:29] reg wrbypass_enq_idx; // @[tage.scala:144:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37] wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:146:33, :151:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}] wire _T_44 = io_update_mask_0_0 | io_update_mask_1_0 | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :170:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_44 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] wire _GEN_15 = ~_T_44 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_44 | wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39] end else // @[tage.scala:144:33, :170:38, :171:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29] io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38] io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38] io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38] io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38] io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38] if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29] if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29] if (~_T_44 | _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] end else begin // @[tage.scala:143:29, :170:38, :171:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end always @(posedge) hi_us_21 hi_us ( // @[tage.scala:89:27] .R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_hi_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}] .W0_clk (clock), .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8] .W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}] ); // @[tage.scala:89:27] lo_us_21 lo_us ( // @[tage.scala:90:27] .R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_lo_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}] .W0_clk (clock), .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8] .W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}] ); // @[tage.scala:90:27] table_21 table_0 ( // @[tage.scala:91:27] .R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_table_R0_data), .W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8] .W0_clk (clock), .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8] .W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}] ); // @[tage.scala:91:27] assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToIN_e11_s53_i64_5 : input clock : Clock input reset : Reset output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<64>, intExceptionFlags : UInt<3>} node rawIn_exp = bits(io.in, 63, 52) node _rawIn_isZero_T = bits(rawIn_exp, 11, 9) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 64, 64) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 51, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node magGeOne = bits(rawIn.sExp, 11, 11) node posExp = bits(rawIn.sExp, 10, 0) node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0)) node _magJustBelowOne_T_1 = andr(posExp) node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1) node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _shiftedSig_T = bits(rawIn.sig, 51, 0) node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T) node _shiftedSig_T_2 = bits(rawIn.sExp, 5, 0) node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0)) node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3) node _alignedSig_T = shr(shiftedSig, 51) node _alignedSig_T_1 = bits(shiftedSig, 50, 0) node _alignedSig_T_2 = orr(_alignedSig_T_1) node alignedSig = cat(_alignedSig_T, _alignedSig_T_2) node _unroundedInt_T = shr(alignedSig, 2) node unroundedInt = or(UInt<64>(0h0), _unroundedInt_T) node _common_inexact_T = bits(alignedSig, 1, 0) node _common_inexact_T_1 = orr(_common_inexact_T) node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0)) node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2) node _roundIncr_near_even_T = bits(alignedSig, 2, 1) node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T) node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2) node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3) node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4) node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6) node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7) node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8) node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1) node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T) node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne) node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even) node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag) node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1) node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd) node _roundIncr_T_4 = and(rawIn.sign, common_inexact) node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4) node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5) node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0)) node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact) node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8) node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9) node _complUnroundedInt_T = not(unroundedInt) node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt) node _roundedInt_T = xor(roundIncr, rawIn.sign) node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1)) node _roundedInt_T_2 = tail(_roundedInt_T_1, 1) node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt) node _roundedInt_T_4 = and(roundingMode_odd, common_inexact) node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4) node magGeOne_atOverflowEdge = eq(posExp, UInt<6>(0h3f)) node _roundCarryBut2_T = bits(unroundedInt, 61, 0) node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T) node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr) node _common_overflow_T = geq(posExp, UInt<7>(0h40)) node _common_overflow_T_1 = bits(unroundedInt, 62, 0) node _common_overflow_T_2 = orr(_common_overflow_T_1) node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr) node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3) node _common_overflow_T_5 = eq(posExp, UInt<6>(0h3e)) node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2) node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6) node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7) node _common_overflow_T_9 = bits(unroundedInt, 62, 62) node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9) node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2) node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11) node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12) node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13) node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0)) node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign) node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr) node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17) node invalidExc = or(rawIn.isNaN, rawIn.isInf) node _overflow_T = eq(invalidExc, UInt<1>(0h0)) node overflow = and(_overflow_T, common_overflow) node _inexact_T = eq(invalidExc, UInt<1>(0h0)) node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0)) node _inexact_T_2 = and(_inexact_T, _inexact_T_1) node inexact = and(_inexact_T_2, common_inexact) node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0)) node excSign = and(_excSign_T, rawIn.sign) node _excOut_T = eq(io.signedOut, excSign) node _excOut_T_1 = mux(_excOut_T, UInt<64>(0h8000000000000000), UInt<1>(0h0)) node _excOut_T_2 = eq(excSign, UInt<1>(0h0)) node _excOut_T_3 = mux(_excOut_T_2, UInt<63>(0h7fffffffffffffff), UInt<1>(0h0)) node excOut = or(_excOut_T_1, _excOut_T_3) node _io_out_T = or(invalidExc, common_overflow) node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt) connect io.out, _io_out_T_1 node _io_intExceptionFlags_T = cat(invalidExc, overflow) node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact) connect io.intExceptionFlags, _io_intExceptionFlags_T_1
module RecFNToIN_e11_s53_i64_5( // @[RecFNToIN.scala:46:7] input clock, // @[RecFNToIN.scala:46:7] input reset, // @[RecFNToIN.scala:46:7] input [64:0] io_in, // @[RecFNToIN.scala:49:16] input [2:0] io_roundingMode, // @[RecFNToIN.scala:49:16] input io_signedOut, // @[RecFNToIN.scala:49:16] output [63:0] io_out, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire [64:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToIN.scala:46:7] wire io_signedOut_0 = io_signedOut; // @[RecFNToIN.scala:46:7] wire [63:0] _io_out_T_1; // @[RecFNToIN.scala:145:18] wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52] wire [63:0] io_out_0; // @[RecFNToIN.scala:46:7] wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire magGeOne = rawIn_sExp[11]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] posExp = rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27] wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47] wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[rawFloatFromRecFN.scala:52:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RecFNToIN.scala:46:7, :68:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RecFNToIN.scala:46:7, :69:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RecFNToIN.scala:46:7, :70:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RecFNToIN.scala:46:7, :71:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RecFNToIN.scala:46:7, :72:53] wire [51:0] _shiftedSig_T = rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}] wire [5:0] _shiftedSig_T_2 = rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 6'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27] wire [115:0] shiftedSig = {63'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16] wire [64:0] _alignedSig_T = shiftedSig[115:51]; // @[RecFNToIN.scala:83:49, :89:20] wire [50:0] _alignedSig_T_1 = shiftedSig[50:0]; // @[RecFNToIN.scala:83:49, :89:51] wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}] wire [65:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}] wire [63:0] _unroundedInt_T = alignedSig[65:2]; // @[RecFNToIN.scala:89:38, :90:52] wire [63:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}] wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50] wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64] wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39] wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}] wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}] wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39] wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}] wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}] wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}] wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}] wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}] wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}] wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26] wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56] wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}] wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}] wire _roundIncr_T = roundingMode_near_even & roundIncr_near_even; // @[RecFNToIN.scala:67:53, :94:78, :98:35] wire _roundIncr_T_1 = roundingMode_near_maxMag & roundIncr_near_maxMag; // @[RecFNToIN.scala:71:53, :96:61, :99:35] wire _roundIncr_T_2 = _roundIncr_T | _roundIncr_T_1; // @[RecFNToIN.scala:98:{35,61}, :99:35] wire _roundIncr_T_3 = roundingMode_min | roundingMode_odd; // @[RecFNToIN.scala:69:53, :72:53, :100:28] wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_5 = _roundIncr_T_3 & _roundIncr_T_4; // @[RecFNToIN.scala:100:{28,49}, :101:26] wire _roundIncr_T_6 = _roundIncr_T_2 | _roundIncr_T_5; // @[RecFNToIN.scala:98:61, :99:61, :100:49] wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}] wire _roundIncr_T_9 = roundingMode_max & _roundIncr_T_8; // @[RecFNToIN.scala:70:53, :102:{27,43}] wire roundIncr = _roundIncr_T_6 | _roundIncr_T_9; // @[RecFNToIN.scala:99:61, :101:46, :102:27] wire [63:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45] wire [63:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23] wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [64:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 65'h1; // @[RecFNToIN.scala:103:32, :106:31] wire [63:0] _roundedInt_T_2 = _roundedInt_T_1[63:0]; // @[RecFNToIN.scala:106:31] wire [63:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31] wire _roundedInt_T_4 = roundingMode_odd & common_inexact; // @[RecFNToIN.scala:72:53, :92:29, :108:31] wire [63:0] roundedInt = {_roundedInt_T_3[63:1], _roundedInt_T_3[0] | _roundedInt_T_4}; // @[RecFNToIN.scala:105:12, :108:{11,31}] wire magGeOne_atOverflowEdge = posExp == 11'h3F; // @[RecFNToIN.scala:62:28, :110:43] wire [61:0] _roundCarryBut2_T = unroundedInt[61:0]; // @[RecFNToIN.scala:90:40, :113:38] wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}] wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}] wire _common_overflow_T = |(posExp[10:6]); // @[RecFNToIN.scala:62:28, :116:21] wire [62:0] _common_overflow_T_1 = unroundedInt[62:0]; // @[RecFNToIN.scala:90:40, :120:42] wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}] wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}] wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64] wire _common_overflow_T_5 = posExp == 11'h3E; // @[RecFNToIN.scala:62:28, :122:38] wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}] wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60] wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_9 = unroundedInt[62]; // @[RecFNToIN.scala:90:40, :126:42] wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42] wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57] wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_13 = io_signedOut_0 ? _common_overflow_T_8 : _common_overflow_T_12; // @[RecFNToIN.scala:46:7, :117:20, :118:24, :124:32] wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20] wire _common_overflow_T_15 = ~io_signedOut_0; // @[RecFNToIN.scala:46:7, :128:13] wire _common_overflow_T_16 = _common_overflow_T_15 & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_17 = _common_overflow_T_16 & roundIncr; // @[RecFNToIN.scala:101:46, :128:{27,41}] wire common_overflow = magGeOne ? _common_overflow_T_14 : _common_overflow_T_17; // @[RecFNToIN.scala:61:30, :115:12, :116:36, :128:41] wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20] wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}] wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20] wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35] wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}] wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}] wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _excOut_T = io_signedOut_0 == excSign; // @[RecFNToIN.scala:46:7, :137:32, :139:27] wire [63:0] _excOut_T_1 = {_excOut_T, 63'h0}; // @[RecFNToIN.scala:139:{12,27}] wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13] wire [62:0] _excOut_T_3 = {63{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}] wire [63:0] excOut = {_excOut_T_1[63], _excOut_T_1[62:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12] wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30] assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}] assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18] wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40] assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}] assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52] assign io_out = io_out_0; // @[RecFNToIN.scala:46:7] assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncAsyncCrossingSink_n1x1 : input clock : Clock input reset : Reset output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} wire nodeIn : { sync : UInt<1>[1]} invalidate nodeIn.sync[0] wire nodeOut : UInt<1>[1] invalidate nodeOut[0] connect auto.out, nodeOut connect nodeIn, auto.in inst chain of SynchronizerShiftReg_w1_d3 connect chain.clock, clock connect chain.reset, reset connect chain.io.d, nodeIn.sync[0] wire _WIRE : UInt<1>[1] wire _WIRE_1 : UInt<1> connect _WIRE_1, chain.io.q node _T = bits(_WIRE_1, 0, 0) connect _WIRE[0], _T connect nodeOut, _WIRE
module IntSyncAsyncCrossingSink_n1x1( // @[Crossing.scala:74:9] input clock, // @[Crossing.scala:74:9] input reset, // @[Crossing.scala:74:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:74:9] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:74:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:74:9] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:74:9] SynchronizerShiftReg_w1_d3 chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (nodeIn_sync_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_0) ); // @[ShiftReg.scala:45:23] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:74:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_21 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h11)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 node _source_ok_T_30 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[2]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[3]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[4]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[5]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[6]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[7]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_37, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = and(_T_11, _T_24) node _T_105 = and(_T_104, _T_37) node _T_106 = and(_T_105, _T_50) node _T_107 = and(_T_106, _T_63) node _T_108 = and(_T_107, _T_71) node _T_109 = and(_T_108, _T_79) node _T_110 = and(_T_109, _T_87) node _T_111 = and(_T_110, _T_95) node _T_112 = and(_T_111, _T_103) node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(_T_112, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_112, UInt<1>(0h1), "") : assert_1 node _T_116 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_116 : node _T_117 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_118 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<1>(0h0)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_4) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_127 = shr(io.in.a.bits.source, 2) node _T_128 = eq(_T_127, UInt<1>(0h1)) node _T_129 = leq(UInt<1>(0h0), uncommonBits_5) node _T_130 = and(_T_128, _T_129) node _T_131 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_132 = and(_T_130, _T_131) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_133 = shr(io.in.a.bits.source, 2) node _T_134 = eq(_T_133, UInt<2>(0h2)) node _T_135 = leq(UInt<1>(0h0), uncommonBits_6) node _T_136 = and(_T_134, _T_135) node _T_137 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_138 = and(_T_136, _T_137) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_139 = shr(io.in.a.bits.source, 2) node _T_140 = eq(_T_139, UInt<2>(0h3)) node _T_141 = leq(UInt<1>(0h0), uncommonBits_7) node _T_142 = and(_T_140, _T_141) node _T_143 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_144 = and(_T_142, _T_143) node _T_145 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_146 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_120, _T_126) node _T_151 = or(_T_150, _T_132) node _T_152 = or(_T_151, _T_138) node _T_153 = or(_T_152, _T_144) node _T_154 = or(_T_153, _T_145) node _T_155 = or(_T_154, _T_146) node _T_156 = or(_T_155, _T_147) node _T_157 = or(_T_156, _T_148) node _T_158 = or(_T_157, _T_149) node _T_159 = and(_T_119, _T_158) node _T_160 = or(UInt<1>(0h0), _T_159) node _T_161 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<13>(0h1000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = and(_T_161, _T_166) node _T_168 = or(UInt<1>(0h0), _T_167) node _T_169 = and(_T_160, _T_168) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_169, UInt<1>(0h1), "") : assert_2 node _T_173 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_174 = shr(io.in.a.bits.source, 2) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = leq(UInt<1>(0h0), uncommonBits_8) node _T_177 = and(_T_175, _T_176) node _T_178 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_179 = and(_T_177, _T_178) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_180 = shr(io.in.a.bits.source, 2) node _T_181 = eq(_T_180, UInt<1>(0h1)) node _T_182 = leq(UInt<1>(0h0), uncommonBits_9) node _T_183 = and(_T_181, _T_182) node _T_184 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_185 = and(_T_183, _T_184) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_186 = shr(io.in.a.bits.source, 2) node _T_187 = eq(_T_186, UInt<2>(0h2)) node _T_188 = leq(UInt<1>(0h0), uncommonBits_10) node _T_189 = and(_T_187, _T_188) node _T_190 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_191 = and(_T_189, _T_190) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_192 = shr(io.in.a.bits.source, 2) node _T_193 = eq(_T_192, UInt<2>(0h3)) node _T_194 = leq(UInt<1>(0h0), uncommonBits_11) node _T_195 = and(_T_193, _T_194) node _T_196 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_201 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_202 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[10] connect _WIRE[0], _T_173 connect _WIRE[1], _T_179 connect _WIRE[2], _T_185 connect _WIRE[3], _T_191 connect _WIRE[4], _T_197 connect _WIRE[5], _T_198 connect _WIRE[6], _T_199 connect _WIRE[7], _T_200 connect _WIRE[8], _T_201 connect _WIRE[9], _T_202 node _T_203 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_204 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_205 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_207 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = mux(_WIRE[6], _T_203, UInt<1>(0h0)) node _T_211 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_212 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_213 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = or(_T_204, _T_205) node _T_215 = or(_T_214, _T_206) node _T_216 = or(_T_215, _T_207) node _T_217 = or(_T_216, _T_208) node _T_218 = or(_T_217, _T_209) node _T_219 = or(_T_218, _T_210) node _T_220 = or(_T_219, _T_211) node _T_221 = or(_T_220, _T_212) node _T_222 = or(_T_221, _T_213) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_222 node _T_223 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_224 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_225 = and(_T_223, _T_224) node _T_226 = or(UInt<1>(0h0), _T_225) node _T_227 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<13>(0h1000))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = and(_T_226, _T_231) node _T_233 = or(UInt<1>(0h0), _T_232) node _T_234 = and(_WIRE_1, _T_233) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_234, UInt<1>(0h1), "") : assert_3 node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(source_ok, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_241 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : node _T_244 = eq(_T_241, UInt<1>(0h0)) when _T_244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_241, UInt<1>(0h1), "") : assert_5 node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(is_aligned, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_248, UInt<1>(0h1), "") : assert_7 node _T_252 = not(io.in.a.bits.mask) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_253, UInt<1>(0h1), "") : assert_8 node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_T_257, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_257, UInt<1>(0h1), "") : assert_9 node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_261 : node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_12) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_13) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h2)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_14) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h3)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_15) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _T_290 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_293 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_294 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_295 = or(_T_265, _T_271) node _T_296 = or(_T_295, _T_277) node _T_297 = or(_T_296, _T_283) node _T_298 = or(_T_297, _T_289) node _T_299 = or(_T_298, _T_290) node _T_300 = or(_T_299, _T_291) node _T_301 = or(_T_300, _T_292) node _T_302 = or(_T_301, _T_293) node _T_303 = or(_T_302, _T_294) node _T_304 = and(_T_264, _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_307 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_308 = cvt(_T_307) node _T_309 = and(_T_308, asSInt(UInt<13>(0h1000))) node _T_310 = asSInt(_T_309) node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) node _T_312 = and(_T_306, _T_311) node _T_313 = or(UInt<1>(0h0), _T_312) node _T_314 = and(_T_305, _T_313) node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(_T_314, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_314, UInt<1>(0h1), "") : assert_10 node _T_318 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<1>(0h0)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_16) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_325 = shr(io.in.a.bits.source, 2) node _T_326 = eq(_T_325, UInt<1>(0h1)) node _T_327 = leq(UInt<1>(0h0), uncommonBits_17) node _T_328 = and(_T_326, _T_327) node _T_329 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_330 = and(_T_328, _T_329) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_331 = shr(io.in.a.bits.source, 2) node _T_332 = eq(_T_331, UInt<2>(0h2)) node _T_333 = leq(UInt<1>(0h0), uncommonBits_18) node _T_334 = and(_T_332, _T_333) node _T_335 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_336 = and(_T_334, _T_335) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_337 = shr(io.in.a.bits.source, 2) node _T_338 = eq(_T_337, UInt<2>(0h3)) node _T_339 = leq(UInt<1>(0h0), uncommonBits_19) node _T_340 = and(_T_338, _T_339) node _T_341 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_342 = and(_T_340, _T_341) node _T_343 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_347 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[10] connect _WIRE_2[0], _T_318 connect _WIRE_2[1], _T_324 connect _WIRE_2[2], _T_330 connect _WIRE_2[3], _T_336 connect _WIRE_2[4], _T_342 connect _WIRE_2[5], _T_343 connect _WIRE_2[6], _T_344 connect _WIRE_2[7], _T_345 connect _WIRE_2[8], _T_346 connect _WIRE_2[9], _T_347 node _T_348 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_349 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_350 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_351 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_352 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_353 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_354 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = mux(_WIRE_2[6], _T_348, UInt<1>(0h0)) node _T_356 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_357 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = or(_T_349, _T_350) node _T_360 = or(_T_359, _T_351) node _T_361 = or(_T_360, _T_352) node _T_362 = or(_T_361, _T_353) node _T_363 = or(_T_362, _T_354) node _T_364 = or(_T_363, _T_355) node _T_365 = or(_T_364, _T_356) node _T_366 = or(_T_365, _T_357) node _T_367 = or(_T_366, _T_358) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_367 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = and(_T_371, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = and(_WIRE_3, _T_378) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_379, UInt<1>(0h1), "") : assert_11 node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(source_ok, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_386, UInt<1>(0h1), "") : assert_13 node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(is_aligned, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_393, UInt<1>(0h1), "") : assert_15 node _T_397 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_397, UInt<1>(0h1), "") : assert_16 node _T_401 = not(io.in.a.bits.mask) node _T_402 = eq(_T_401, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_402, UInt<1>(0h1), "") : assert_17 node _T_406 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_406, UInt<1>(0h1), "") : assert_18 node _T_410 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_410 : node _T_411 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_412 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_413 = and(_T_411, _T_412) node _T_414 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h0)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_20) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<1>(0h1)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_21) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h2)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_22) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<2>(0h3)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_23) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_444 = or(_T_414, _T_420) node _T_445 = or(_T_444, _T_426) node _T_446 = or(_T_445, _T_432) node _T_447 = or(_T_446, _T_438) node _T_448 = or(_T_447, _T_439) node _T_449 = or(_T_448, _T_440) node _T_450 = or(_T_449, _T_441) node _T_451 = or(_T_450, _T_442) node _T_452 = or(_T_451, _T_443) node _T_453 = and(_T_413, _T_452) node _T_454 = or(UInt<1>(0h0), _T_453) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_454, UInt<1>(0h1), "") : assert_19 node _T_458 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_459 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_460 = and(_T_458, _T_459) node _T_461 = or(UInt<1>(0h0), _T_460) node _T_462 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = and(_T_461, _T_466) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_468, UInt<1>(0h1), "") : assert_20 node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(source_ok, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(is_aligned, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_478 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_T_478, UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_478, UInt<1>(0h1), "") : assert_23 node _T_482 = eq(io.in.a.bits.mask, mask) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_482, UInt<1>(0h1), "") : assert_24 node _T_486 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_486, UInt<1>(0h1), "") : assert_25 node _T_490 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_490 : node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_492 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_493 = and(_T_491, _T_492) node _T_494 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_495 = shr(io.in.a.bits.source, 2) node _T_496 = eq(_T_495, UInt<1>(0h0)) node _T_497 = leq(UInt<1>(0h0), uncommonBits_24) node _T_498 = and(_T_496, _T_497) node _T_499 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_500 = and(_T_498, _T_499) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_501 = shr(io.in.a.bits.source, 2) node _T_502 = eq(_T_501, UInt<1>(0h1)) node _T_503 = leq(UInt<1>(0h0), uncommonBits_25) node _T_504 = and(_T_502, _T_503) node _T_505 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_506 = and(_T_504, _T_505) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_507 = shr(io.in.a.bits.source, 2) node _T_508 = eq(_T_507, UInt<2>(0h2)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_26) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_512 = and(_T_510, _T_511) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_513 = shr(io.in.a.bits.source, 2) node _T_514 = eq(_T_513, UInt<2>(0h3)) node _T_515 = leq(UInt<1>(0h0), uncommonBits_27) node _T_516 = and(_T_514, _T_515) node _T_517 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_520 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_521 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_523 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_524 = or(_T_494, _T_500) node _T_525 = or(_T_524, _T_506) node _T_526 = or(_T_525, _T_512) node _T_527 = or(_T_526, _T_518) node _T_528 = or(_T_527, _T_519) node _T_529 = or(_T_528, _T_520) node _T_530 = or(_T_529, _T_521) node _T_531 = or(_T_530, _T_522) node _T_532 = or(_T_531, _T_523) node _T_533 = and(_T_493, _T_532) node _T_534 = or(UInt<1>(0h0), _T_533) node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _T_538 = or(UInt<1>(0h0), _T_537) node _T_539 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = and(_T_538, _T_543) node _T_545 = or(UInt<1>(0h0), _T_544) node _T_546 = and(_T_534, _T_545) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_546, UInt<1>(0h1), "") : assert_26 node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(source_ok, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(is_aligned, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_556 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_556, UInt<1>(0h1), "") : assert_29 node _T_560 = eq(io.in.a.bits.mask, mask) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_560, UInt<1>(0h1), "") : assert_30 node _T_564 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_564 : node _T_565 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_566 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_567 = and(_T_565, _T_566) node _T_568 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_569 = shr(io.in.a.bits.source, 2) node _T_570 = eq(_T_569, UInt<1>(0h0)) node _T_571 = leq(UInt<1>(0h0), uncommonBits_28) node _T_572 = and(_T_570, _T_571) node _T_573 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_574 = and(_T_572, _T_573) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_575 = shr(io.in.a.bits.source, 2) node _T_576 = eq(_T_575, UInt<1>(0h1)) node _T_577 = leq(UInt<1>(0h0), uncommonBits_29) node _T_578 = and(_T_576, _T_577) node _T_579 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_580 = and(_T_578, _T_579) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_581 = shr(io.in.a.bits.source, 2) node _T_582 = eq(_T_581, UInt<2>(0h2)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_30) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_586 = and(_T_584, _T_585) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_587 = shr(io.in.a.bits.source, 2) node _T_588 = eq(_T_587, UInt<2>(0h3)) node _T_589 = leq(UInt<1>(0h0), uncommonBits_31) node _T_590 = and(_T_588, _T_589) node _T_591 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_592 = and(_T_590, _T_591) node _T_593 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_597 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_598 = or(_T_568, _T_574) node _T_599 = or(_T_598, _T_580) node _T_600 = or(_T_599, _T_586) node _T_601 = or(_T_600, _T_592) node _T_602 = or(_T_601, _T_593) node _T_603 = or(_T_602, _T_594) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_596) node _T_606 = or(_T_605, _T_597) node _T_607 = and(_T_567, _T_606) node _T_608 = or(UInt<1>(0h0), _T_607) node _T_609 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_610 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_611 = and(_T_609, _T_610) node _T_612 = or(UInt<1>(0h0), _T_611) node _T_613 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<13>(0h1000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = and(_T_612, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = and(_T_608, _T_619) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_620, UInt<1>(0h1), "") : assert_31 node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(source_ok, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(is_aligned, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_630 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_630, UInt<1>(0h1), "") : assert_34 node _T_634 = not(mask) node _T_635 = and(io.in.a.bits.mask, _T_634) node _T_636 = eq(_T_635, UInt<1>(0h0)) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_636, UInt<1>(0h1), "") : assert_35 node _T_640 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_640 : node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_645 = shr(io.in.a.bits.source, 2) node _T_646 = eq(_T_645, UInt<1>(0h0)) node _T_647 = leq(UInt<1>(0h0), uncommonBits_32) node _T_648 = and(_T_646, _T_647) node _T_649 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_650 = and(_T_648, _T_649) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_651 = shr(io.in.a.bits.source, 2) node _T_652 = eq(_T_651, UInt<1>(0h1)) node _T_653 = leq(UInt<1>(0h0), uncommonBits_33) node _T_654 = and(_T_652, _T_653) node _T_655 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_656 = and(_T_654, _T_655) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_657 = shr(io.in.a.bits.source, 2) node _T_658 = eq(_T_657, UInt<2>(0h2)) node _T_659 = leq(UInt<1>(0h0), uncommonBits_34) node _T_660 = and(_T_658, _T_659) node _T_661 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_662 = and(_T_660, _T_661) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_663 = shr(io.in.a.bits.source, 2) node _T_664 = eq(_T_663, UInt<2>(0h3)) node _T_665 = leq(UInt<1>(0h0), uncommonBits_35) node _T_666 = and(_T_664, _T_665) node _T_667 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_668 = and(_T_666, _T_667) node _T_669 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_673 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_674 = or(_T_644, _T_650) node _T_675 = or(_T_674, _T_656) node _T_676 = or(_T_675, _T_662) node _T_677 = or(_T_676, _T_668) node _T_678 = or(_T_677, _T_669) node _T_679 = or(_T_678, _T_670) node _T_680 = or(_T_679, _T_671) node _T_681 = or(_T_680, _T_672) node _T_682 = or(_T_681, _T_673) node _T_683 = and(_T_643, _T_682) node _T_684 = or(UInt<1>(0h0), _T_683) node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_687 = and(_T_685, _T_686) node _T_688 = or(UInt<1>(0h0), _T_687) node _T_689 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_690 = cvt(_T_689) node _T_691 = and(_T_690, asSInt(UInt<13>(0h1000))) node _T_692 = asSInt(_T_691) node _T_693 = eq(_T_692, asSInt(UInt<1>(0h0))) node _T_694 = and(_T_688, _T_693) node _T_695 = or(UInt<1>(0h0), _T_694) node _T_696 = and(_T_684, _T_695) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_696, UInt<1>(0h1), "") : assert_36 node _T_700 = asUInt(reset) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(source_ok, UInt<1>(0h0)) when _T_702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(is_aligned, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_706 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(_T_706, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_706, UInt<1>(0h1), "") : assert_39 node _T_710 = eq(io.in.a.bits.mask, mask) node _T_711 = asUInt(reset) node _T_712 = eq(_T_711, UInt<1>(0h0)) when _T_712 : node _T_713 = eq(_T_710, UInt<1>(0h0)) when _T_713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_710, UInt<1>(0h1), "") : assert_40 node _T_714 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_714 : node _T_715 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_716 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_717 = and(_T_715, _T_716) node _T_718 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_719 = shr(io.in.a.bits.source, 2) node _T_720 = eq(_T_719, UInt<1>(0h0)) node _T_721 = leq(UInt<1>(0h0), uncommonBits_36) node _T_722 = and(_T_720, _T_721) node _T_723 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_724 = and(_T_722, _T_723) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_725 = shr(io.in.a.bits.source, 2) node _T_726 = eq(_T_725, UInt<1>(0h1)) node _T_727 = leq(UInt<1>(0h0), uncommonBits_37) node _T_728 = and(_T_726, _T_727) node _T_729 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_730 = and(_T_728, _T_729) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_731 = shr(io.in.a.bits.source, 2) node _T_732 = eq(_T_731, UInt<2>(0h2)) node _T_733 = leq(UInt<1>(0h0), uncommonBits_38) node _T_734 = and(_T_732, _T_733) node _T_735 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_736 = and(_T_734, _T_735) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<2>(0h3)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_39) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _T_743 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_744 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_745 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_746 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_747 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_748 = or(_T_718, _T_724) node _T_749 = or(_T_748, _T_730) node _T_750 = or(_T_749, _T_736) node _T_751 = or(_T_750, _T_742) node _T_752 = or(_T_751, _T_743) node _T_753 = or(_T_752, _T_744) node _T_754 = or(_T_753, _T_745) node _T_755 = or(_T_754, _T_746) node _T_756 = or(_T_755, _T_747) node _T_757 = and(_T_717, _T_756) node _T_758 = or(UInt<1>(0h0), _T_757) node _T_759 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_760 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_761 = and(_T_759, _T_760) node _T_762 = or(UInt<1>(0h0), _T_761) node _T_763 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_764 = cvt(_T_763) node _T_765 = and(_T_764, asSInt(UInt<13>(0h1000))) node _T_766 = asSInt(_T_765) node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0))) node _T_768 = and(_T_762, _T_767) node _T_769 = or(UInt<1>(0h0), _T_768) node _T_770 = and(_T_758, _T_769) node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(_T_770, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_770, UInt<1>(0h1), "") : assert_41 node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(source_ok, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(is_aligned, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_780 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(_T_780, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_780, UInt<1>(0h1), "") : assert_44 node _T_784 = eq(io.in.a.bits.mask, mask) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_784, UInt<1>(0h1), "") : assert_45 node _T_788 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_788 : node _T_789 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_790 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_791 = and(_T_789, _T_790) node _T_792 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_793 = shr(io.in.a.bits.source, 2) node _T_794 = eq(_T_793, UInt<1>(0h0)) node _T_795 = leq(UInt<1>(0h0), uncommonBits_40) node _T_796 = and(_T_794, _T_795) node _T_797 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_798 = and(_T_796, _T_797) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_799 = shr(io.in.a.bits.source, 2) node _T_800 = eq(_T_799, UInt<1>(0h1)) node _T_801 = leq(UInt<1>(0h0), uncommonBits_41) node _T_802 = and(_T_800, _T_801) node _T_803 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_804 = and(_T_802, _T_803) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_805 = shr(io.in.a.bits.source, 2) node _T_806 = eq(_T_805, UInt<2>(0h2)) node _T_807 = leq(UInt<1>(0h0), uncommonBits_42) node _T_808 = and(_T_806, _T_807) node _T_809 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_810 = and(_T_808, _T_809) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_811 = shr(io.in.a.bits.source, 2) node _T_812 = eq(_T_811, UInt<2>(0h3)) node _T_813 = leq(UInt<1>(0h0), uncommonBits_43) node _T_814 = and(_T_812, _T_813) node _T_815 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_816 = and(_T_814, _T_815) node _T_817 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_818 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_819 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_820 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_821 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_822 = or(_T_792, _T_798) node _T_823 = or(_T_822, _T_804) node _T_824 = or(_T_823, _T_810) node _T_825 = or(_T_824, _T_816) node _T_826 = or(_T_825, _T_817) node _T_827 = or(_T_826, _T_818) node _T_828 = or(_T_827, _T_819) node _T_829 = or(_T_828, _T_820) node _T_830 = or(_T_829, _T_821) node _T_831 = and(_T_791, _T_830) node _T_832 = or(UInt<1>(0h0), _T_831) node _T_833 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_834 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_835 = and(_T_833, _T_834) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_838 = cvt(_T_837) node _T_839 = and(_T_838, asSInt(UInt<13>(0h1000))) node _T_840 = asSInt(_T_839) node _T_841 = eq(_T_840, asSInt(UInt<1>(0h0))) node _T_842 = and(_T_836, _T_841) node _T_843 = or(UInt<1>(0h0), _T_842) node _T_844 = and(_T_832, _T_843) node _T_845 = asUInt(reset) node _T_846 = eq(_T_845, UInt<1>(0h0)) when _T_846 : node _T_847 = eq(_T_844, UInt<1>(0h0)) when _T_847 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_844, UInt<1>(0h1), "") : assert_46 node _T_848 = asUInt(reset) node _T_849 = eq(_T_848, UInt<1>(0h0)) when _T_849 : node _T_850 = eq(source_ok, UInt<1>(0h0)) when _T_850 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(is_aligned, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_854 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(_T_854, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_854, UInt<1>(0h1), "") : assert_49 node _T_858 = eq(io.in.a.bits.mask, mask) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_858, UInt<1>(0h1), "") : assert_50 node _T_862 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(_T_862, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_862, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_866 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_867 = asUInt(reset) node _T_868 = eq(_T_867, UInt<1>(0h0)) when _T_868 : node _T_869 = eq(_T_866, UInt<1>(0h0)) when _T_869 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_866, UInt<1>(0h1), "") : assert_52 node _source_ok_T_38 = eq(io.in.d.bits.source, UInt<5>(0h11)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_39 = shr(io.in.d.bits.source, 2) node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h0)) node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h1)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h2)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h3)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_65 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_66 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_38 connect _source_ok_WIRE_1[1], _source_ok_T_44 connect _source_ok_WIRE_1[2], _source_ok_T_50 connect _source_ok_WIRE_1[3], _source_ok_T_56 connect _source_ok_WIRE_1[4], _source_ok_T_62 connect _source_ok_WIRE_1[5], _source_ok_T_63 connect _source_ok_WIRE_1[6], _source_ok_T_64 connect _source_ok_WIRE_1[7], _source_ok_T_65 connect _source_ok_WIRE_1[8], _source_ok_T_66 connect _source_ok_WIRE_1[9], _source_ok_T_67 node _source_ok_T_68 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[2]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[3]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[4]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE_1[5]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[6]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[7]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_75, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_870 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_870 : node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(source_ok_1, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_874 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_874, UInt<1>(0h1), "") : assert_54 node _T_878 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_878, UInt<1>(0h1), "") : assert_55 node _T_882 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_882, UInt<1>(0h1), "") : assert_56 node _T_886 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(_T_886, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_886, UInt<1>(0h1), "") : assert_57 node _T_890 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_890 : node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(source_ok_1, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(sink_ok, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_897 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(_T_897, UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_897, UInt<1>(0h1), "") : assert_60 node _T_901 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_901, UInt<1>(0h1), "") : assert_61 node _T_905 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(_T_905, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_905, UInt<1>(0h1), "") : assert_62 node _T_909 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(_T_909, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_909, UInt<1>(0h1), "") : assert_63 node _T_913 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_914 = or(UInt<1>(0h1), _T_913) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_914, UInt<1>(0h1), "") : assert_64 node _T_918 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_918 : node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(source_ok_1, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(sink_ok, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_925 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_925, UInt<1>(0h1), "") : assert_67 node _T_929 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_929, UInt<1>(0h1), "") : assert_68 node _T_933 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_933, UInt<1>(0h1), "") : assert_69 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(_T_937, io.in.d.bits.corrupt) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_938, UInt<1>(0h1), "") : assert_70 node _T_942 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_943 = or(UInt<1>(0h1), _T_942) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_943, UInt<1>(0h1), "") : assert_71 node _T_947 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_947 : node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(source_ok_1, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_951 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_951, UInt<1>(0h1), "") : assert_73 node _T_955 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_955, UInt<1>(0h1), "") : assert_74 node _T_959 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_960 = or(UInt<1>(0h1), _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_960, UInt<1>(0h1), "") : assert_75 node _T_964 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_964 : node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(source_ok_1, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_968 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_968, UInt<1>(0h1), "") : assert_77 node _T_972 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_973 = or(_T_972, io.in.d.bits.corrupt) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_973, UInt<1>(0h1), "") : assert_78 node _T_977 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_978 = or(UInt<1>(0h1), _T_977) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_978, UInt<1>(0h1), "") : assert_79 node _T_982 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_982 : node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(source_ok_1, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_986 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_986, UInt<1>(0h1), "") : assert_81 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_990, UInt<1>(0h1), "") : assert_82 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_995, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<14>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_999 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_T_999, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_999, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1003 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1004 = asUInt(reset) node _T_1005 = eq(_T_1004, UInt<1>(0h0)) when _T_1005 : node _T_1006 = eq(_T_1003, UInt<1>(0h0)) when _T_1006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1003, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1007 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1011 = eq(a_first, UInt<1>(0h0)) node _T_1012 = and(io.in.a.valid, _T_1011) when _T_1012 : node _T_1013 = eq(io.in.a.bits.opcode, opcode) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_87 node _T_1017 = eq(io.in.a.bits.param, param) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_88 node _T_1021 = eq(io.in.a.bits.size, size) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_89 node _T_1025 = eq(io.in.a.bits.source, source) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_90 node _T_1029 = eq(io.in.a.bits.address, address) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_91 node _T_1033 = and(io.in.a.ready, io.in.a.valid) node _T_1034 = and(_T_1033, a_first) when _T_1034 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1035 = eq(d_first, UInt<1>(0h0)) node _T_1036 = and(io.in.d.valid, _T_1035) when _T_1036 : node _T_1037 = eq(io.in.d.bits.opcode, opcode_1) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_92 node _T_1041 = eq(io.in.d.bits.param, param_1) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_93 node _T_1045 = eq(io.in.d.bits.size, size_1) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_94 node _T_1049 = eq(io.in.d.bits.source, source_1) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_95 node _T_1053 = eq(io.in.d.bits.sink, sink) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_96 node _T_1057 = eq(io.in.d.bits.denied, denied) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_97 node _T_1061 = and(io.in.d.ready, io.in.d.valid) node _T_1062 = and(_T_1061, d_first) when _T_1062 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1063 = and(io.in.a.valid, a_first_1) node _T_1064 = and(_T_1063, UInt<1>(0h1)) when _T_1064 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1065 = and(io.in.a.ready, io.in.a.valid) node _T_1066 = and(_T_1065, a_first_1) node _T_1067 = and(_T_1066, UInt<1>(0h1)) when _T_1067 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1068 = dshr(inflight, io.in.a.bits.source) node _T_1069 = bits(_T_1068, 0, 0) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1074 = and(io.in.d.valid, d_first_1) node _T_1075 = and(_T_1074, UInt<1>(0h1)) node _T_1076 = eq(d_release_ack, UInt<1>(0h0)) node _T_1077 = and(_T_1075, _T_1076) when _T_1077 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1078 = and(io.in.d.ready, io.in.d.valid) node _T_1079 = and(_T_1078, d_first_1) node _T_1080 = and(_T_1079, UInt<1>(0h1)) node _T_1081 = eq(d_release_ack, UInt<1>(0h0)) node _T_1082 = and(_T_1080, _T_1081) when _T_1082 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1083 = and(io.in.d.valid, d_first_1) node _T_1084 = and(_T_1083, UInt<1>(0h1)) node _T_1085 = eq(d_release_ack, UInt<1>(0h0)) node _T_1086 = and(_T_1084, _T_1085) when _T_1086 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1087 = dshr(inflight, io.in.d.bits.source) node _T_1088 = bits(_T_1087, 0, 0) node _T_1089 = or(_T_1088, same_cycle_resp) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1093 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1094 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1095 = or(_T_1093, _T_1094) node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_T_1095, UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1095, UInt<1>(0h1), "") : assert_100 node _T_1099 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_101 else : node _T_1103 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1104 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1105 = or(_T_1103, _T_1104) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_102 node _T_1109 = eq(io.in.d.bits.size, a_size_lookup) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_103 node _T_1113 = and(io.in.d.valid, d_first_1) node _T_1114 = and(_T_1113, a_first_1) node _T_1115 = and(_T_1114, io.in.a.valid) node _T_1116 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1117 = and(_T_1115, _T_1116) node _T_1118 = eq(d_release_ack, UInt<1>(0h0)) node _T_1119 = and(_T_1117, _T_1118) when _T_1119 : node _T_1120 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1121 = or(_T_1120, io.in.a.ready) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_104 node _T_1125 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1126 = orr(a_set_wo_ready) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) node _T_1128 = or(_T_1125, _T_1127) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_42 node _T_1132 = orr(inflight) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) node _T_1134 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1135 = or(_T_1133, _T_1134) node _T_1136 = lt(watchdog, plusarg_reader.out) node _T_1137 = or(_T_1135, _T_1136) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1141 = and(io.in.a.ready, io.in.a.valid) node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = or(_T_1141, _T_1142) when _T_1143 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1144 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1145 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1146 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1147 = and(_T_1145, _T_1146) node _T_1148 = and(_T_1144, _T_1147) when _T_1148 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1149 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1150 = and(_T_1149, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1151 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1152 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1153 = and(_T_1151, _T_1152) node _T_1154 = and(_T_1150, _T_1153) when _T_1154 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1155 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1156 = bits(_T_1155, 0, 0) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1161 = and(io.in.d.valid, d_first_2) node _T_1162 = and(_T_1161, UInt<1>(0h1)) node _T_1163 = and(_T_1162, d_release_ack_1) when _T_1163 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1164 = and(io.in.d.ready, io.in.d.valid) node _T_1165 = and(_T_1164, d_first_2) node _T_1166 = and(_T_1165, UInt<1>(0h1)) node _T_1167 = and(_T_1166, d_release_ack_1) when _T_1167 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1168 = and(io.in.d.valid, d_first_2) node _T_1169 = and(_T_1168, UInt<1>(0h1)) node _T_1170 = and(_T_1169, d_release_ack_1) when _T_1170 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1171 = dshr(inflight_1, io.in.d.bits.source) node _T_1172 = bits(_T_1171, 0, 0) node _T_1173 = or(_T_1172, same_cycle_resp_1) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1177 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_109 else : node _T_1181 = eq(io.in.d.bits.size, c_size_lookup) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_110 node _T_1185 = and(io.in.d.valid, d_first_2) node _T_1186 = and(_T_1185, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1187 = and(_T_1186, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1188 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1189 = and(_T_1187, _T_1188) node _T_1190 = and(_T_1189, d_release_ack_1) node _T_1191 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1192 = and(_T_1190, _T_1191) when _T_1192 : node _T_1193 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1194 = or(_T_1193, _WIRE_27.ready) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_111 node _T_1198 = orr(c_set_wo_ready) when _T_1198 : node _T_1199 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_43 node _T_1203 = orr(inflight_1) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog_1, plusarg_reader_1.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<14>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1212 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_21( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module DigitalTop : output auto : { flip chipyard_prcictrl_domain_reset_setter_clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, mbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}, cbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}} output psd : { } output resetctrl : { flip hartIsInReset : UInt<1>[1]} output debug : { flip clock : Clock, flip reset : Reset, systemjtag : { flip jtag : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}}, flip reset : Reset, flip mfr_id : UInt<11>, flip part_number : UInt<16>, flip version : UInt<4>}, ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>} output mem_tl : { } output mem_axi4 : { `0` : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} output mmio_axi4 : { } input l2_frontend_bus_axi4 : { } input custom_boot : UInt<1> output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock} output serial_tl_0_debug : { ser_busy : UInt<1>, des_busy : UInt<1>} output uart_0 : { txd : UInt<1>, flip rxd : UInt<1>} output clock_tap : Clock input interrupts : UInt<0> wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst ibus of ClockSinkDomain inst sbus of SystemBus inst pbus of PeripheryBus_pbus inst fbus of FrontBus inst cbus of PeripheryBus_cbus inst mbus of MemoryBus inst coh_wrapper of CoherenceManagerWrapper inst tile_prci_domain of TilePRCIDomain inst xbar of IntXbar_i1_o1_1 inst xbar_1 of IntXbar_i1_o1_2 inst xbar_2 of IntXbar_i1_o1_3 inst tileHartIdNexusNode of BundleBridgeNexus_UInt1_1 inst broadcast of BundleBridgeNexus_UInt32_1 inst clint_domain of CLINTClockSinkDomain inst plic_domain of PLICClockSinkDomain inst tlDM of TLDebugModule inst debugCustomXbarOpt of DebugCustomXbar inst nexus of BundleBridgeNexus_TraceBundle inst nexus_1 of BundleBridgeNexus_TraceCoreInterface inst bootrom_domain of BootROMClockSinkDomain inst bank of ScratchpadBank inst serial_tl_domain of SerialTL0ClockSinkDomain inst uartClockDomainWrapper of TLUARTClockSinkDomain inst intsink of IntSyncSyncCrossingSink_n1x1_5 inst chipyard_prcictrl_domain of ChipyardPRCICtrlClockSinkDomain inst aggregator of ClockGroupAggregator_allClocks inst clockNamePrefixer of ClockGroupParameterModifier inst frequencySpecifier of ClockGroupParameterModifier_1 inst clockGroupCombiner of ClockGroupCombiner inst clockTapNode of ClockGroup_6 inst globalNoCDomain of ClockSinkDomain_1 inst reRoCCManagerIdNexusNode of BundleBridgeNexus_NoOutput_8 wire allClockGroupsNodeOut : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeOut.member.sbus_0.reset invalidate allClockGroupsNodeOut.member.sbus_0.clock invalidate allClockGroupsNodeOut.member.sbus_1.reset invalidate allClockGroupsNodeOut.member.sbus_1.clock wire x1_allClockGroupsNodeOut : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut.member.pbus_0.reset invalidate x1_allClockGroupsNodeOut.member.pbus_0.clock wire x1_allClockGroupsNodeOut_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.clock wire x1_allClockGroupsNodeOut_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.clock wire x1_allClockGroupsNodeOut_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.clock wire x1_allClockGroupsNodeOut_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.clock wire allClockGroupsNodeIn : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeIn.member.sbus_0.reset invalidate allClockGroupsNodeIn.member.sbus_0.clock invalidate allClockGroupsNodeIn.member.sbus_1.reset invalidate allClockGroupsNodeIn.member.sbus_1.clock wire x1_allClockGroupsNodeIn : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn.member.pbus_0.reset invalidate x1_allClockGroupsNodeIn.member.pbus_0.clock wire x1_allClockGroupsNodeIn_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.clock wire x1_allClockGroupsNodeIn_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.clock wire x1_allClockGroupsNodeIn_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.clock wire x1_allClockGroupsNodeIn_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.clock connect allClockGroupsNodeOut, allClockGroupsNodeIn connect x1_allClockGroupsNodeOut, x1_allClockGroupsNodeIn connect x1_allClockGroupsNodeOut_1, x1_allClockGroupsNodeIn_1 connect x1_allClockGroupsNodeOut_2, x1_allClockGroupsNodeIn_2 connect x1_allClockGroupsNodeOut_3, x1_allClockGroupsNodeIn_3 connect x1_allClockGroupsNodeOut_4, x1_allClockGroupsNodeIn_4 wire tileHaltSinkNodeIn : UInt<1>[1] invalidate tileHaltSinkNodeIn[0] wire tileWFISinkNodeIn : UInt<1>[1] invalidate tileWFISinkNodeIn[0] wire tileCeaseSinkNodeIn : UInt<1>[1] invalidate tileCeaseSinkNodeIn[0] wire domainIn : { clock : Clock, reset : Reset} invalidate domainIn.reset invalidate domainIn.clock wire debugNodesOut : { sync : UInt<1>[1]} invalidate debugNodesOut.sync[0] wire debugNodesIn : { sync : UInt<1>[1]} invalidate debugNodesIn.sync[0] connect debugNodesOut, debugNodesIn wire traceCoreNodesIn : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn.cause invalidate traceCoreNodesIn.tval invalidate traceCoreNodesIn.priv invalidate traceCoreNodesIn.group[0].ilastsize invalidate traceCoreNodesIn.group[0].itype invalidate traceCoreNodesIn.group[0].iaddr invalidate traceCoreNodesIn.group[0].iretire wire traceNodesIn : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn.time invalidate traceNodesIn.insns[0].tval invalidate traceNodesIn.insns[0].cause invalidate traceNodesIn.insns[0].interrupt invalidate traceNodesIn.insns[0].exception invalidate traceNodesIn.insns[0].priv invalidate traceNodesIn.insns[0].insn invalidate traceNodesIn.insns[0].iaddr invalidate traceNodesIn.insns[0].valid wire memAXI4NodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}} invalidate memAXI4NodeIn.r.bits.last invalidate memAXI4NodeIn.r.bits.resp invalidate memAXI4NodeIn.r.bits.data invalidate memAXI4NodeIn.r.bits.id invalidate memAXI4NodeIn.r.valid invalidate memAXI4NodeIn.r.ready invalidate memAXI4NodeIn.ar.bits.qos invalidate memAXI4NodeIn.ar.bits.prot invalidate memAXI4NodeIn.ar.bits.cache invalidate memAXI4NodeIn.ar.bits.lock invalidate memAXI4NodeIn.ar.bits.burst invalidate memAXI4NodeIn.ar.bits.size invalidate memAXI4NodeIn.ar.bits.len invalidate memAXI4NodeIn.ar.bits.addr invalidate memAXI4NodeIn.ar.bits.id invalidate memAXI4NodeIn.ar.valid invalidate memAXI4NodeIn.ar.ready invalidate memAXI4NodeIn.b.bits.resp invalidate memAXI4NodeIn.b.bits.id invalidate memAXI4NodeIn.b.valid invalidate memAXI4NodeIn.b.ready invalidate memAXI4NodeIn.w.bits.last invalidate memAXI4NodeIn.w.bits.strb invalidate memAXI4NodeIn.w.bits.data invalidate memAXI4NodeIn.w.valid invalidate memAXI4NodeIn.w.ready invalidate memAXI4NodeIn.aw.bits.qos invalidate memAXI4NodeIn.aw.bits.prot invalidate memAXI4NodeIn.aw.bits.cache invalidate memAXI4NodeIn.aw.bits.lock invalidate memAXI4NodeIn.aw.bits.burst invalidate memAXI4NodeIn.aw.bits.size invalidate memAXI4NodeIn.aw.bits.len invalidate memAXI4NodeIn.aw.bits.addr invalidate memAXI4NodeIn.aw.bits.id invalidate memAXI4NodeIn.aw.valid invalidate memAXI4NodeIn.aw.ready wire bootROMResetVectorSourceNodeOut : UInt<32> invalidate bootROMResetVectorSourceNodeOut wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn wire ioNodeIn : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeIn.rxd invalidate ioNodeIn.txd wire clockTapIn : { clock : Clock, reset : Reset} invalidate clockTapIn.reset invalidate clockTapIn.clock connect plic_domain.auto.plic_int_in[0], ibus.auto.int_bus_anon_out[0] connect sbus.auto.sbus_clock_groups_in, allClockGroupsNodeOut connect pbus.auto.pbus_clock_groups_in, x1_allClockGroupsNodeOut connect fbus.auto.fbus_clock_groups_in, x1_allClockGroupsNodeOut_1 connect mbus.auto.mbus_clock_groups_in, x1_allClockGroupsNodeOut_2 connect cbus.auto.cbus_clock_groups_in, x1_allClockGroupsNodeOut_3 connect clockTapNode.auto.in, x1_allClockGroupsNodeOut_4 connect coh_wrapper.auto.coh_clock_groups_in, sbus.auto.sbus_clock_groups_out connect ibus.auto.clock_in, sbus.auto.fixedClockNode_anon_out_0 connect tile_prci_domain.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_1 connect globalNoCDomain.auto.clock_in, sbus.auto.fixedClockNode_anon_out_2 connect uartClockDomainWrapper.auto.clock_in, pbus.auto.fixedClockNode_anon_out connect serial_tl_domain.auto.clock_in, fbus.auto.fixedClockNode_anon_out connect clint_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_0 connect plic_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_1 connect domainIn, cbus.auto.fixedClockNode_anon_out_2 connect bootrom_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_3 connect chipyard_prcictrl_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_4 connect bank.auto.clock_in, mbus.auto.fixedClockNode_anon_out_0 connect coh_wrapper.auto.l2_ctrls_ctrl_in, cbus.auto.coupler_to_l2_ctrl_buffer_out connect cbus.auto.bus_xing_in, sbus.auto.coupler_to_bus_named_cbus_bus_xing_out connect pbus.auto.bus_xing_in, cbus.auto.coupler_to_bus_named_pbus_bus_xing_out connect sbus.auto.coupler_from_bus_named_fbus_bus_xing_in, fbus.auto.bus_xing_out connect coh_wrapper.auto.coherent_jbar_anon_in, sbus.auto.coupler_to_bus_named_coh_widget_anon_out connect mbus.auto.bus_xing_in, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out connect nexus.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_source_out connect nexus_1.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_core_source_out connect tileHaltSinkNodeIn, xbar.auto.anon_out connect tileWFISinkNodeIn, xbar_1.auto.anon_out connect tileCeaseSinkNodeIn, xbar_2.auto.anon_out connect tile_prci_domain.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out connect tile_prci_domain.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out connect clint_domain.auto.clint_in, cbus.auto.coupler_to_clint_fragmenter_anon_out connect plic_domain.auto.plic_in, cbus.auto.coupler_to_plic_fragmenter_anon_out connect debugNodesIn, tlDM.auto.dmOuter_int_out connect fbus.auto.coupler_from_debug_sb_widget_anon_in, tlDM.auto.dmInner_dmInner_sb2tlOpt_out connect tlDM.auto.dmInner_dmInner_tl_in, cbus.auto.coupler_to_debug_fragmenter_anon_out connect tlDM.auto.dmInner_dmInner_custom_in, debugCustomXbarOpt.auto.out connect tile_prci_domain.auto.intsink_in.sync[0], debugNodesOut.sync[0] connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_0, tile_prci_domain.auto.tl_master_clock_xing_out_0 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_1, tile_prci_domain.auto.tl_master_clock_xing_out_1 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_2, tile_prci_domain.auto.tl_master_clock_xing_out_2 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_3, tile_prci_domain.auto.tl_master_clock_xing_out_3 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_4, tile_prci_domain.auto.tl_master_clock_xing_out_4 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_5, tile_prci_domain.auto.tl_master_clock_xing_out_5 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_6, tile_prci_domain.auto.tl_master_clock_xing_out_6 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_7, tile_prci_domain.auto.tl_master_clock_xing_out_7 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_8, tile_prci_domain.auto.tl_master_clock_xing_out_8 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_9, tile_prci_domain.auto.tl_master_clock_xing_out_9 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_10, tile_prci_domain.auto.tl_master_clock_xing_out_10 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_11, tile_prci_domain.auto.tl_master_clock_xing_out_11 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_12, tile_prci_domain.auto.tl_master_clock_xing_out_12 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_13, tile_prci_domain.auto.tl_master_clock_xing_out_13 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_14, tile_prci_domain.auto.tl_master_clock_xing_out_14 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_15, tile_prci_domain.auto.tl_master_clock_xing_out_15 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_16, tile_prci_domain.auto.tl_master_clock_xing_out_16 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_17, tile_prci_domain.auto.tl_master_clock_xing_out_17 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_18, tile_prci_domain.auto.tl_master_clock_xing_out_18 connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out.sync[1] connect tile_prci_domain.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_0.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_1.sync[0] connect xbar.auto.anon_in[0], tile_prci_domain.auto.intsink_out_0[0] connect xbar_1.auto.anon_in[0], tile_prci_domain.auto.intsink_out_1[0] connect xbar_2.auto.anon_in[0], tile_prci_domain.auto.intsink_out_2[0] connect traceNodesIn, nexus.auto.out connect traceCoreNodesIn, nexus_1.auto.out connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.r, memAXI4NodeIn.r connect memAXI4NodeIn.ar.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.bits connect memAXI4NodeIn.ar.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.ready, memAXI4NodeIn.ar.ready connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.b, memAXI4NodeIn.b connect memAXI4NodeIn.w.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.bits connect memAXI4NodeIn.w.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.ready, memAXI4NodeIn.w.ready connect memAXI4NodeIn.aw.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.bits connect memAXI4NodeIn.aw.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.ready, memAXI4NodeIn.aw.ready connect broadcast.auto.in, bootROMResetVectorSourceNodeOut connect bootrom_domain.auto.bootrom_in, cbus.auto.coupler_to_bootrom_fragmenter_anon_out connect bank.auto.xbar_anon_in, mbus.auto.buffer_out connect fbus.auto.coupler_from_port_named_serial_tl_0_in_buffer_in, serial_tl_domain.auto.serdesser_client_out connect uartClockDomainWrapper.auto.uart_0_io_out.rxd, ioNodeIn.rxd connect ioNodeIn.txd, uartClockDomainWrapper.auto.uart_0_io_out.txd connect uartClockDomainWrapper.auto.uart_0_control_xing_in, pbus.auto.coupler_to_device_named_uart_0_control_xing_out connect ibus.auto.int_bus_anon_in[0], intsink.auto.out[0] connect intsink.auto.in.sync[0], intXingOut.sync[0] connect intXingIn, uartClockDomainWrapper.auto.uart_0_int_xing_out connect chipyard_prcictrl_domain.auto.xbar_anon_in, cbus.auto.coupler_to_prci_ctrl_fixer_anon_out connect clockNamePrefixer.auto.clock_name_prefixer_in_0, aggregator.auto.out_0 connect clockNamePrefixer.auto.clock_name_prefixer_in_1, aggregator.auto.out_1 connect clockNamePrefixer.auto.clock_name_prefixer_in_2, aggregator.auto.out_2 connect clockNamePrefixer.auto.clock_name_prefixer_in_3, aggregator.auto.out_3 connect clockNamePrefixer.auto.clock_name_prefixer_in_4, aggregator.auto.out_4 connect clockNamePrefixer.auto.clock_name_prefixer_in_5, aggregator.auto.out_5 connect allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_0 connect x1_allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_1 connect x1_allClockGroupsNodeIn_1, clockNamePrefixer.auto.clock_name_prefixer_out_2 connect x1_allClockGroupsNodeIn_2, clockNamePrefixer.auto.clock_name_prefixer_out_3 connect x1_allClockGroupsNodeIn_3, clockNamePrefixer.auto.clock_name_prefixer_out_4 connect x1_allClockGroupsNodeIn_4, clockNamePrefixer.auto.clock_name_prefixer_out_5 connect aggregator.auto.in, frequencySpecifier.auto.frequency_specifier_out connect frequencySpecifier.auto.frequency_specifier_in, clockGroupCombiner.auto.clock_group_combiner_out connect clockGroupCombiner.auto.clock_group_combiner_in, chipyard_prcictrl_domain.auto.resetSynchronizer_out connect clockTapIn, clockTapNode.auto.out connect auto.cbus_fixedClockNode_anon_out, cbus.auto.fixedClockNode_anon_out_5 connect auto.mbus_fixedClockNode_anon_out, mbus.auto.fixedClockNode_anon_out_1 connect chipyard_prcictrl_domain.auto.reset_setter_clock_in, auto.chipyard_prcictrl_domain_reset_setter_clock_in connect tlDM.io.tl_reset, domainIn.reset connect tlDM.io.tl_clock, domainIn.clock connect tlDM.io.hartIsInReset[0], resetctrl.hartIsInReset[0] connect tlDM.io.debug_reset, debug.reset connect tlDM.io.debug_clock, debug.clock connect debug.ndreset, tlDM.io.ctrl.ndreset connect debug.dmactive, tlDM.io.ctrl.dmactive connect tlDM.io.ctrl.dmactiveAck, debug.dmactiveAck connect tlDM.io.ctrl.debugUnavail[0], UInt<1>(0h0) inst dtm of DebugTransportModuleJTAG connect dtm.io.jtag, debug.systemjtag.jtag connect dtm.io.jtag_clock, debug.systemjtag.jtag.TCK connect dtm.io.jtag_reset, debug.systemjtag.reset connect dtm.io.jtag_mfr_id, debug.systemjtag.mfr_id connect dtm.io.jtag_part_number, debug.systemjtag.part_number connect dtm.io.jtag_version, debug.systemjtag.version connect dtm.rf_reset, debug.systemjtag.reset connect tlDM.io.dmi.dmi, dtm.io.dmi connect tlDM.io.dmi.dmiClock, debug.systemjtag.jtag.TCK connect tlDM.io.dmi.dmiReset, debug.systemjtag.reset connect mem_axi4.`0`, memAXI4NodeIn connect bootROMResetVectorSourceNodeOut, UInt<17>(0h10000) connect cbus.custom_boot, custom_boot connect serial_tl_domain.serial_tl_0.clock_in, serial_tl_0.clock_in connect serial_tl_0.out.bits, serial_tl_domain.serial_tl_0.out.bits connect serial_tl_0.out.valid, serial_tl_domain.serial_tl_0.out.valid connect serial_tl_domain.serial_tl_0.out.ready, serial_tl_0.out.ready connect serial_tl_domain.serial_tl_0.in, serial_tl_0.in connect serial_tl_0_debug, serial_tl_domain.serial_tl_0_debug connect uart_0, ioNodeIn connect clock_tap, clockTapIn.clock regreset int_rtc_tick_c_value : UInt<10>, clint_domain.clock, clint_domain.reset, UInt<10>(0h0) wire int_rtc_tick : UInt<1> connect int_rtc_tick, UInt<1>(0h0) when UInt<1>(0h1) : node int_rtc_tick_wrap_wrap = eq(int_rtc_tick_c_value, UInt<10>(0h3e7)) node _int_rtc_tick_wrap_value_T = add(int_rtc_tick_c_value, UInt<1>(0h1)) node _int_rtc_tick_wrap_value_T_1 = tail(_int_rtc_tick_wrap_value_T, 1) connect int_rtc_tick_c_value, _int_rtc_tick_wrap_value_T_1 when int_rtc_tick_wrap_wrap : connect int_rtc_tick_c_value, UInt<1>(0h0) connect int_rtc_tick, int_rtc_tick_wrap_wrap connect clint_domain.tick, int_rtc_tick extmodule GenericDigitalInIOCell : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell extmodule GenericDigitalOutIOCell : output pad : UInt<1> input o : UInt<1> input oe : UInt<1> defname = GenericDigitalOutIOCell extmodule GenericDigitalInIOCell_1 : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell
module DigitalTop( // @[DigitalTop.scala:47:7] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25] input debug_clock, // @[Periphery.scala:125:19] input debug_reset, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19] output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19] input debug_systemjtag_reset, // @[Periphery.scala:125:19] output debug_dmactive, // @[Periphery.scala:125:19] input debug_dmactiveAck, // @[Periphery.scala:125:19] input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21] input custom_boot, // @[CustomBootPin.scala:73:27] output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24] input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24] output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24] output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24] output uart_0_txd, // @[BundleBridgeSink.scala:25:19] input uart_0_rxd, // @[BundleBridgeSink.scala:25:19] output clock_tap // @[CanHaveClockTap.scala:23:23] ); wire clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire [63:0] nexus_auto_out_time; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_0_tval; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_out_insns_0_cause; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_interrupt; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_exception; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_out_insns_0_priv; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_out_insns_0_insn; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_0_iaddr; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_valid; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_time; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_0_tval; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_insns_0_cause; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_interrupt; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_exception; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_in_insns_0_priv; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_in_insns_0_insn; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_0_iaddr; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_valid; // @[BundleBridgeNexus.scala:20:9] wire ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21] wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21] wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21] wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21] wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [9:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44] wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44] wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44] wire [13:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44] wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44] wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38] wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38] wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38] wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_serial_tl_0_debug_ser_busy; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_serial_tl_0_debug_des_busy; // @[PeripheryTLSerial.scala:116:38] wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28] wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28] wire [3:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28] wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28] wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28] wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28] wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [13:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26] wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26] wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26] wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26] wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26] wire [13:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26] wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26] wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26] wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26] wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [13:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [13:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_clock; // @[BusWrapper.scala:89:28] wire _clint_domain_reset; // @[BusWrapper.scala:89:28] wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39] wire _tile_prci_domain_auto_intsink_out_1_0; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_18_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_18_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_18_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_address; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_18_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_18_e_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_18_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_17_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_17_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_16_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_16_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_15_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_15_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_14_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_14_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_13_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_13_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_12_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_12_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_11_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_11_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_10_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_10_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_9_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_9_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_8_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_8_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_7_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_7_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_6_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_6_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_5_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_5_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_4_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_4_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_3_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_3_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_2_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_size; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_2_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_1_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_0_d_ready; // @[HasTiles.scala:163:38] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [8:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [13:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26] wire [3:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26] wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26] wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala:30:26] wire [3:0] _mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [9:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [13:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [13:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [13:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [13:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [9:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [13:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [8:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26] wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [13:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [9:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_b_valid; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_b_bits_param; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_b_bits_address; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_c_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_size; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_size; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_size; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size; // @[SystemBus.scala:31:26] wire [8:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size; // @[SystemBus.scala:31:26] wire [8:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26] wire [8:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26] wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_2_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_2_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[SystemBus.scala:31:26] wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock; // @[DigitalTop.scala:47:7] wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset; // @[DigitalTop.scala:47:7] wire resetctrl_hartIsInReset_0_0 = resetctrl_hartIsInReset_0; // @[DigitalTop.scala:47:7] wire debug_clock_0 = debug_clock; // @[DigitalTop.scala:47:7] wire debug_reset_0 = debug_reset; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TCK_0 = debug_systemjtag_jtag_TCK; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TMS_0 = debug_systemjtag_jtag_TMS; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDI_0 = debug_systemjtag_jtag_TDI; // @[DigitalTop.scala:47:7] wire debug_systemjtag_reset_0 = debug_systemjtag_reset; // @[DigitalTop.scala:47:7] wire debug_dmactiveAck_0 = debug_dmactiveAck; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_ready_0 = mem_axi4_0_aw_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_ready_0 = mem_axi4_0_w_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_b_valid_0 = mem_axi4_0_b_valid; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_b_bits_id_0 = mem_axi4_0_b_bits_id; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_b_bits_resp_0 = mem_axi4_0_b_bits_resp; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_ready_0 = mem_axi4_0_ar_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_valid_0 = mem_axi4_0_r_valid; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_r_bits_id_0 = mem_axi4_0_r_bits_id; // @[DigitalTop.scala:47:7] wire [63:0] mem_axi4_0_r_bits_data_0 = mem_axi4_0_r_bits_data; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_r_bits_resp_0 = mem_axi4_0_r_bits_resp; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_bits_last_0 = mem_axi4_0_r_bits_last; // @[DigitalTop.scala:47:7] wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[DigitalTop.scala:47:7] wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[DigitalTop.scala:47:7] wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[DigitalTop.scala:47:7] wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[DigitalTop.scala:47:7] wire uart_0_rxd_0 = uart_0_rxd; // @[DigitalTop.scala:47:7] wire [10:0] debug_systemjtag_mfr_id = 11'h0; // @[DigitalTop.scala:47:7] wire [15:0] debug_systemjtag_part_number = 16'h0; // @[DigitalTop.scala:47:7] wire [3:0] debug_systemjtag_version = 4'h0; // @[DigitalTop.scala:47:7] wire [3:0] nexus_1_auto_in_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_in_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_out_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_out_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_nodeIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] nexus_1_nodeIn_priv = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] nexus_1_nodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] nexus_1_nodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreNodesIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] traceCoreNodesIn_priv = 4'h0; // @[MixedNode.scala:551:17] wire [31:0] broadcast_auto_in = 32'h10000; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_auto_out = 32'h10000; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_nodeIn = 32'h10000; // @[MixedNode.scala:551:17] wire [31:0] broadcast_nodeOut = 32'h10000; // @[MixedNode.scala:542:17] wire [31:0] bootROMResetVectorSourceNodeOut = 32'h10000; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_auto_in_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_in_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_in_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_nodeIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeIn_tval = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeIn_cause = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_nodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_nodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreNodesIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceCoreNodesIn_tval = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceCoreNodesIn_cause = 32'h0; // @[MixedNode.scala:551:17] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire ibus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_auto_in_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_in_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_out_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_out_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_nodeIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17] wire nexus_1_nodeIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17] wire nexus_1_nodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire clockNamePrefixer_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockNamePrefixer_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockNamePrefixer__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire frequencySpecifier_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire frequencySpecifier_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire frequencySpecifier__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockTapNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockTapNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockTapNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire tileHaltSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire tileCeaseSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreNodesIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreNodesIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_ready = mem_axi4_0_aw_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17] wire [31:0] memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_ready = mem_axi4_0_w_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17] wire [63:0] memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_b_valid = mem_axi4_0_b_valid_0; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_b_bits_id = mem_axi4_0_b_bits_id_0; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_b_bits_resp = mem_axi4_0_b_bits_resp_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_ready = mem_axi4_0_ar_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17] wire [31:0] memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_valid = mem_axi4_0_r_valid_0; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_r_bits_id = mem_axi4_0_r_bits_id_0; // @[MixedNode.scala:551:17] wire [63:0] memAXI4NodeIn_r_bits_data = mem_axi4_0_r_bits_data_0; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_r_bits_resp = mem_axi4_0_r_bits_resp_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_bits_last = mem_axi4_0_r_bits_last_0; // @[MixedNode.scala:551:17] wire ioNodeIn_txd; // @[MixedNode.scala:551:17] wire ioNodeIn_rxd = uart_0_rxd_0; // @[MixedNode.scala:551:17] wire auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] wire auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] wire auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] wire auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDO_driven; // @[DigitalTop.scala:47:7] wire debug_ndreset; // @[DigitalTop.scala:47:7] wire debug_dmactive_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7] wire [31:0] mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7] wire [63:0] mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7] wire [31:0] mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7] wire serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7] wire [31:0] serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7] wire serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7] wire uart_0_txd_0; // @[DigitalTop.scala:47:7] wire clockTapIn_clock; // @[MixedNode.scala:551:17] wire ibus_clockNodeIn_clock = ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_in_0; // @[ClockDomain.scala:14:9] wire ibus_clockNodeIn_reset = ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_out_0; // @[ClockDomain.scala:14:9] wire ibus_childClock; // @[LazyModuleImp.scala:155:31] wire ibus_childReset; // @[LazyModuleImp.scala:158:31] assign ibus_childClock = ibus_clockNodeIn_clock; // @[MixedNode.scala:551:17] assign ibus_childReset = ibus_clockNodeIn_reset; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_valid = nexus_auto_in_insns_0_valid; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_0_iaddr = nexus_auto_in_insns_0_iaddr; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeIn_insns_0_insn = nexus_auto_in_insns_0_insn; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeIn_insns_0_priv = nexus_auto_in_insns_0_priv; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_exception = nexus_auto_in_insns_0_exception; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_interrupt = nexus_auto_in_insns_0_interrupt; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_insns_0_cause = nexus_auto_in_insns_0_cause; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_0_tval = nexus_auto_in_insns_0_tval; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_time = nexus_auto_in_time; // @[MixedNode.scala:551:17] wire nexus_nodeOut_insns_0_valid; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17] wire traceNodesIn_insns_0_valid = nexus_auto_out_insns_0_valid; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeOut_insns_0_insn; // @[MixedNode.scala:542:17] wire [39:0] traceNodesIn_insns_0_iaddr = nexus_auto_out_insns_0_iaddr; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeOut_insns_0_priv; // @[MixedNode.scala:542:17] wire [31:0] traceNodesIn_insns_0_insn = nexus_auto_out_insns_0_insn; // @[MixedNode.scala:551:17] wire nexus_nodeOut_insns_0_exception; // @[MixedNode.scala:542:17] wire [2:0] traceNodesIn_insns_0_priv = nexus_auto_out_insns_0_priv; // @[MixedNode.scala:551:17] wire nexus_nodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17] wire traceNodesIn_insns_0_exception = nexus_auto_out_insns_0_exception; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeOut_insns_0_cause; // @[MixedNode.scala:542:17] wire traceNodesIn_insns_0_interrupt = nexus_auto_out_insns_0_interrupt; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeOut_insns_0_tval; // @[MixedNode.scala:542:17] wire [63:0] traceNodesIn_insns_0_cause = nexus_auto_out_insns_0_cause; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeOut_time; // @[MixedNode.scala:542:17] wire [39:0] traceNodesIn_insns_0_tval = nexus_auto_out_insns_0_tval; // @[MixedNode.scala:551:17] wire [63:0] traceNodesIn_time = nexus_auto_out_time; // @[MixedNode.scala:551:17] assign nexus_nodeOut_insns_0_valid = nexus_nodeIn_insns_0_valid; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_iaddr = nexus_nodeIn_insns_0_iaddr; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_insn = nexus_nodeIn_insns_0_insn; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_priv = nexus_nodeIn_insns_0_priv; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_exception = nexus_nodeIn_insns_0_exception; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_interrupt = nexus_nodeIn_insns_0_interrupt; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_cause = nexus_nodeIn_insns_0_cause; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_tval = nexus_nodeIn_insns_0_tval; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_time = nexus_nodeIn_time; // @[MixedNode.scala:542:17, :551:17] assign nexus_auto_out_insns_0_valid = nexus_nodeOut_insns_0_valid; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_iaddr = nexus_nodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_insn = nexus_nodeOut_insns_0_insn; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_priv = nexus_nodeOut_insns_0_priv; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_exception = nexus_nodeOut_insns_0_exception; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_interrupt = nexus_nodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_cause = nexus_nodeOut_insns_0_cause; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_tval = nexus_nodeOut_insns_0_tval; // @[MixedNode.scala:542:17] assign nexus_auto_out_time = nexus_nodeOut_time; // @[MixedNode.scala:542:17] wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_3_member_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_3_member_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_2_member_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_2_member_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_1_member_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_1_member_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_member_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_member_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[MixedNode.scala:551:17] wire allClockGroupsNodeIn_member_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[MixedNode.scala:551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock = clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire clockTapNode_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset = clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_nodeOut_reset; // @[MixedNode.scala:542:17] assign clockTapIn_clock = clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockTapIn_reset = clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_out_clock = clockTapNode_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_out_reset = clockTapNode_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockTapNode_nodeOut_clock = clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign clockTapNode_nodeOut_reset = clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] wire allClockGroupsNodeOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] assign clockTapNode_auto_in_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_in_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] assign allClockGroupsNodeOut_member_sbus_1_clock = allClockGroupsNodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_1_reset = allClockGroupsNodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_0_clock = allClockGroupsNodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_0_reset = allClockGroupsNodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_member_pbus_0_clock = x1_allClockGroupsNodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_member_pbus_0_reset = x1_allClockGroupsNodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_1_member_fbus_0_clock = x1_allClockGroupsNodeIn_1_member_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_1_member_fbus_0_reset = x1_allClockGroupsNodeIn_1_member_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_2_member_mbus_0_clock = x1_allClockGroupsNodeIn_2_member_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_2_member_mbus_0_reset = x1_allClockGroupsNodeIn_2_member_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_3_member_cbus_0_clock = x1_allClockGroupsNodeIn_3_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_3_member_cbus_0_reset = x1_allClockGroupsNodeIn_3_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] wire tileWFISinkNodeIn_0; // @[MixedNode.scala:551:17] wire domainIn_clock; // @[MixedNode.scala:551:17] wire domainIn_reset; // @[MixedNode.scala:551:17] wire debugNodesIn_sync_0; // @[MixedNode.scala:551:17] wire debugNodesOut_sync_0; // @[MixedNode.scala:542:17] assign debugNodesOut_sync_0 = debugNodesIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign mem_axi4_0_aw_valid_0 = memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_id_0 = memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_addr_0 = memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_len_0 = memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_size_0 = memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_burst_0 = memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_lock_0 = memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_cache_0 = memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_prot_0 = memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_qos_0 = memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_valid_0 = memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_data_0 = memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_strb_0 = memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_last_0 = memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17] assign mem_axi4_0_b_ready_0 = memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_valid_0 = memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_id_0 = memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_addr_0 = memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_len_0 = memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_size_0 = memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_burst_0 = memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_lock_0 = memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_cache_0 = memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_prot_0 = memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_qos_0 = memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17] assign mem_axi4_0_r_ready_0 = memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign uart_0_txd_0 = ioNodeIn_txd; // @[MixedNode.scala:551:17] reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40] wire int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24] wire int_rtc_tick; // @[Counter.scala:117:24] assign int_rtc_tick_wrap_wrap = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24] assign int_rtc_tick = int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24, :117:24] wire [10:0] _int_rtc_tick_wrap_value_T = {1'h0, int_rtc_tick_c_value} + 11'h1; // @[Counter.scala:61:40, :77:24] wire [9:0] _int_rtc_tick_wrap_value_T_1 = _int_rtc_tick_wrap_value_T[9:0]; // @[Counter.scala:77:24] always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28] if (_clint_domain_reset) // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40] else // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= int_rtc_tick_wrap_wrap ? 10'h0 : _int_rtc_tick_wrap_value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] always @(posedge) IntXbar_i1_o1 ibus_int_bus ( // @[InterruptBus.scala:19:27] .auto_anon_in_0 (ibus_auto_int_bus_anon_in_0), // @[ClockDomain.scala:14:9] .auto_anon_out_0 (ibus_auto_int_bus_anon_out_0) ); // @[InterruptBus.scala:19:27] SystemBus sbus ( // @[SystemBus.scala:31:26] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_18_b_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_b_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_b_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_b_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_b_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_b_bits_address (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_b_bits_address), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_c_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_c_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_18_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_18_e_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_18_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_18_e_bits_sink), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_17_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_16_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_15_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_14_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_13_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_12_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_11_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_10_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_9_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_8_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_7_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_6_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_5_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_4_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_3_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_2_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_1_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_0_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), .auto_coupler_to_bus_named_coh_widget_anon_out_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), .auto_coupler_to_bus_named_coh_widget_anon_out_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), .auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), .auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid (_fbus_auto_bus_xing_out_a_valid), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready (_fbus_auto_bus_xing_out_d_ready), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready (_cbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid (_cbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_fixedClockNode_anon_out_2_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), .auto_fixedClockNode_anon_out_2_reset (_sbus_auto_fixedClockNode_anon_out_2_reset), .auto_fixedClockNode_anon_out_1_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), .auto_fixedClockNode_anon_out_1_reset (_sbus_auto_fixedClockNode_anon_out_1_reset), .auto_fixedClockNode_anon_out_0_clock (ibus_auto_clock_in_clock), .auto_fixedClockNode_anon_out_0_reset (ibus_auto_clock_in_reset), .auto_sbus_clock_groups_in_member_sbus_1_clock (allClockGroupsNodeOut_member_sbus_1_clock), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_1_reset (allClockGroupsNodeOut_member_sbus_1_reset), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_0_clock (allClockGroupsNodeOut_member_sbus_0_clock), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_0_reset (allClockGroupsNodeOut_member_sbus_0_reset), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_out_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), .auto_sbus_clock_groups_out_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) ); // @[SystemBus.scala:31:26] PeripheryBus_pbus pbus ( // @[PeripheryBus.scala:37:26] .auto_coupler_to_device_named_uart_0_control_xing_out_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), .auto_coupler_to_device_named_uart_0_control_xing_out_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), .auto_coupler_to_device_named_uart_0_control_xing_out_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), // @[UART.scala:270:44] .auto_fixedClockNode_anon_out_clock (_pbus_auto_fixedClockNode_anon_out_clock), .auto_fixedClockNode_anon_out_reset (_pbus_auto_fixedClockNode_anon_out_reset), .auto_pbus_clock_groups_in_member_pbus_0_clock (x1_allClockGroupsNodeOut_member_pbus_0_clock), // @[MixedNode.scala:542:17] .auto_pbus_clock_groups_in_member_pbus_0_reset (x1_allClockGroupsNodeOut_member_pbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_pbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_d_valid (_pbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt) ); // @[PeripheryBus.scala:37:26] FrontBus fbus ( // @[FrontBus.scala:23:26] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), .auto_coupler_from_debug_sb_widget_anon_in_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), .auto_coupler_from_debug_sb_widget_anon_in_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), .auto_fixedClockNode_anon_out_clock (_fbus_auto_fixedClockNode_anon_out_clock), .auto_fixedClockNode_anon_out_reset (_fbus_auto_fixedClockNode_anon_out_reset), .auto_fbus_clock_groups_in_member_fbus_0_clock (x1_allClockGroupsNodeOut_1_member_fbus_0_clock), // @[MixedNode.scala:542:17] .auto_fbus_clock_groups_in_member_fbus_0_reset (x1_allClockGroupsNodeOut_1_member_fbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_out_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), // @[SystemBus.scala:31:26] .auto_bus_xing_out_a_valid (_fbus_auto_bus_xing_out_a_valid), .auto_bus_xing_out_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), .auto_bus_xing_out_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), .auto_bus_xing_out_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), .auto_bus_xing_out_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), .auto_bus_xing_out_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), .auto_bus_xing_out_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), .auto_bus_xing_out_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), .auto_bus_xing_out_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), .auto_bus_xing_out_d_ready (_fbus_auto_bus_xing_out_d_ready), .auto_bus_xing_out_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt) // @[SystemBus.scala:31:26] ); // @[FrontBus.scala:23:26] PeripheryBus_cbus cbus ( // @[PeripheryBus.scala:37:26] .auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), .auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), .auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_bootrom_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), .auto_coupler_to_bootrom_fragmenter_anon_out_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_debug_fragmenter_anon_out_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_debug_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), .auto_coupler_to_debug_fragmenter_anon_out_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), // @[Periphery.scala:88:26] .auto_coupler_to_plic_fragmenter_anon_out_a_ready (_plic_domain_auto_plic_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_plic_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), .auto_coupler_to_plic_fragmenter_anon_out_d_valid (_plic_domain_auto_plic_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_a_ready (_clint_domain_auto_clint_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_clint_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), .auto_coupler_to_clint_fragmenter_anon_out_d_valid (_clint_domain_auto_clint_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready (_pbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid (_pbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_coupler_to_l2_ctrl_buffer_out_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), .auto_coupler_to_l2_ctrl_buffer_out_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), .auto_coupler_to_l2_ctrl_buffer_out_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_fixedClockNode_anon_out_5_clock (auto_cbus_fixedClockNode_anon_out_clock_0), .auto_fixedClockNode_anon_out_5_reset (auto_cbus_fixedClockNode_anon_out_reset_0), .auto_fixedClockNode_anon_out_4_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), .auto_fixedClockNode_anon_out_4_reset (_cbus_auto_fixedClockNode_anon_out_4_reset), .auto_fixedClockNode_anon_out_3_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), .auto_fixedClockNode_anon_out_3_reset (_cbus_auto_fixedClockNode_anon_out_3_reset), .auto_fixedClockNode_anon_out_2_clock (domainIn_clock), .auto_fixedClockNode_anon_out_2_reset (domainIn_reset), .auto_fixedClockNode_anon_out_1_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), .auto_fixedClockNode_anon_out_1_reset (_cbus_auto_fixedClockNode_anon_out_1_reset), .auto_fixedClockNode_anon_out_0_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), .auto_fixedClockNode_anon_out_0_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), .auto_cbus_clock_groups_in_member_cbus_0_clock (x1_allClockGroupsNodeOut_3_member_cbus_0_clock), // @[MixedNode.scala:542:17] .auto_cbus_clock_groups_in_member_cbus_0_reset (x1_allClockGroupsNodeOut_3_member_cbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_cbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), // @[SystemBus.scala:31:26] .auto_bus_xing_in_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), // @[SystemBus.scala:31:26] .auto_bus_xing_in_d_valid (_cbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), .custom_boot (custom_boot) ); // @[PeripheryBus.scala:37:26] MemoryBus mbus ( // @[MemoryBus.scala:30:26] .auto_buffer_out_a_ready (_bank_auto_xbar_anon_in_a_ready), // @[Scratchpad.scala:65:28] .auto_buffer_out_a_valid (_mbus_auto_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param (_mbus_auto_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size (_mbus_auto_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source (_mbus_auto_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address (_mbus_auto_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data (_mbus_auto_buffer_out_a_bits_data), .auto_buffer_out_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), .auto_buffer_out_d_ready (_mbus_auto_buffer_out_d_ready), .auto_buffer_out_d_valid (_bank_auto_xbar_anon_in_d_valid), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), // @[Scratchpad.scala:65:28] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready (memAXI4NodeIn_aw_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid (memAXI4NodeIn_aw_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id (memAXI4NodeIn_aw_bits_id), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr (memAXI4NodeIn_aw_bits_addr), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len (memAXI4NodeIn_aw_bits_len), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size (memAXI4NodeIn_aw_bits_size), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst (memAXI4NodeIn_aw_bits_burst), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock (memAXI4NodeIn_aw_bits_lock), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache (memAXI4NodeIn_aw_bits_cache), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot (memAXI4NodeIn_aw_bits_prot), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos (memAXI4NodeIn_aw_bits_qos), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready (memAXI4NodeIn_w_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid (memAXI4NodeIn_w_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data (memAXI4NodeIn_w_bits_data), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb (memAXI4NodeIn_w_bits_strb), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last (memAXI4NodeIn_w_bits_last), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready (memAXI4NodeIn_b_ready), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid (memAXI4NodeIn_b_valid), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id (memAXI4NodeIn_b_bits_id), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp (memAXI4NodeIn_b_bits_resp), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready (memAXI4NodeIn_ar_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid (memAXI4NodeIn_ar_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id (memAXI4NodeIn_ar_bits_id), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr (memAXI4NodeIn_ar_bits_addr), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len (memAXI4NodeIn_ar_bits_len), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size (memAXI4NodeIn_ar_bits_size), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst (memAXI4NodeIn_ar_bits_burst), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock (memAXI4NodeIn_ar_bits_lock), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache (memAXI4NodeIn_ar_bits_cache), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot (memAXI4NodeIn_ar_bits_prot), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos (memAXI4NodeIn_ar_bits_qos), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready (memAXI4NodeIn_r_ready), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid (memAXI4NodeIn_r_valid), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id (memAXI4NodeIn_r_bits_id), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data (memAXI4NodeIn_r_bits_data), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp (memAXI4NodeIn_r_bits_resp), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last (memAXI4NodeIn_r_bits_last), // @[MixedNode.scala:551:17] .auto_fixedClockNode_anon_out_1_clock (auto_mbus_fixedClockNode_anon_out_clock_0), .auto_fixedClockNode_anon_out_1_reset (auto_mbus_fixedClockNode_anon_out_reset_0), .auto_fixedClockNode_anon_out_0_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), .auto_fixedClockNode_anon_out_0_reset (_mbus_auto_fixedClockNode_anon_out_0_reset), .auto_mbus_clock_groups_in_member_mbus_0_clock (x1_allClockGroupsNodeOut_2_member_mbus_0_clock), // @[MixedNode.scala:542:17] .auto_mbus_clock_groups_in_member_mbus_0_reset (x1_allClockGroupsNodeOut_2_member_mbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_mbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_d_valid (_mbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt) ); // @[MemoryBus.scala:30:26] CoherenceManagerWrapper coh_wrapper ( // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready (_mbus_auto_bus_xing_in_a_ready), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid (_mbus_auto_bus_xing_in_d_valid), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt), // @[MemoryBus.scala:30:26] .auto_coherent_jbar_anon_in_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), .auto_coherent_jbar_anon_in_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), .auto_coherent_jbar_anon_in_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), .auto_coherent_jbar_anon_in_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), .auto_coherent_jbar_anon_in_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), .auto_coherent_jbar_anon_in_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), .auto_coherent_jbar_anon_in_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), .auto_coherent_jbar_anon_in_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), .auto_coherent_jbar_anon_in_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), .auto_coherent_jbar_anon_in_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), .auto_coherent_jbar_anon_in_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), .auto_coherent_jbar_anon_in_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), .auto_coherent_jbar_anon_in_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), .auto_coherent_jbar_anon_in_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), .auto_coherent_jbar_anon_in_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), // @[SystemBus.scala:31:26] .auto_l2_ctrls_ctrl_in_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), .auto_l2_ctrls_ctrl_in_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), .auto_l2_ctrls_ctrl_in_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), .auto_l2_ctrls_ctrl_in_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), .auto_l2_ctrls_ctrl_in_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), .auto_l2_ctrls_ctrl_in_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), .auto_coh_clock_groups_in_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), // @[SystemBus.scala:31:26] .auto_coh_clock_groups_in_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) // @[SystemBus.scala:31:26] ); // @[BankedCoherenceParams.scala:56:31] TilePRCIDomain tile_prci_domain ( // @[HasTiles.scala:163:38] .auto_intsink_out_1_0 (_tile_prci_domain_auto_intsink_out_1_0), .auto_intsink_in_sync_0 (debugNodesOut_sync_0), // @[MixedNode.scala:542:17] .auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid (nexus_auto_in_insns_0_valid), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr (nexus_auto_in_insns_0_iaddr), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn (nexus_auto_in_insns_0_insn), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv (nexus_auto_in_insns_0_priv), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception (nexus_auto_in_insns_0_exception), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt (nexus_auto_in_insns_0_interrupt), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause (nexus_auto_in_insns_0_cause), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval (nexus_auto_in_insns_0_tval), .auto_element_reset_domain_rockettile_trace_source_out_time (nexus_auto_in_time), .auto_element_reset_domain_rockettile_hartid_in (_tileHartIdNexusNode_auto_out), // @[HasTiles.scala:75:39] .auto_int_in_clock_xing_in_2_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_0_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_0_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), // @[BusWrapper.scala:89:28] .auto_tl_master_clock_xing_out_18_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_valid), .auto_tl_master_clock_xing_out_18_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_opcode), .auto_tl_master_clock_xing_out_18_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_param), .auto_tl_master_clock_xing_out_18_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_size), .auto_tl_master_clock_xing_out_18_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_source), .auto_tl_master_clock_xing_out_18_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_address), .auto_tl_master_clock_xing_out_18_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_mask), .auto_tl_master_clock_xing_out_18_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_data), .auto_tl_master_clock_xing_out_18_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_18_a_bits_corrupt), .auto_tl_master_clock_xing_out_18_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_18_b_ready), .auto_tl_master_clock_xing_out_18_b_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_b_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_b_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_b_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_b_bits_address (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_b_bits_address), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_c_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_c_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_valid), .auto_tl_master_clock_xing_out_18_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_opcode), .auto_tl_master_clock_xing_out_18_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_param), .auto_tl_master_clock_xing_out_18_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_size), .auto_tl_master_clock_xing_out_18_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_source), .auto_tl_master_clock_xing_out_18_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_address), .auto_tl_master_clock_xing_out_18_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_data), .auto_tl_master_clock_xing_out_18_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_18_c_bits_corrupt), .auto_tl_master_clock_xing_out_18_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_18_d_ready), .auto_tl_master_clock_xing_out_18_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_18_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_18_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_18_e_valid), .auto_tl_master_clock_xing_out_18_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_18_e_bits_sink), .auto_tl_master_clock_xing_out_17_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_17_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_valid), .auto_tl_master_clock_xing_out_17_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_opcode), .auto_tl_master_clock_xing_out_17_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_param), .auto_tl_master_clock_xing_out_17_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_size), .auto_tl_master_clock_xing_out_17_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_source), .auto_tl_master_clock_xing_out_17_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_address), .auto_tl_master_clock_xing_out_17_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_mask), .auto_tl_master_clock_xing_out_17_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_data), .auto_tl_master_clock_xing_out_17_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_17_a_bits_corrupt), .auto_tl_master_clock_xing_out_17_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_17_d_ready), .auto_tl_master_clock_xing_out_17_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_17_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_17_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_17_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_17_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_17_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_17_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_17_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_17_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_17_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_16_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_16_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_valid), .auto_tl_master_clock_xing_out_16_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_opcode), .auto_tl_master_clock_xing_out_16_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_param), .auto_tl_master_clock_xing_out_16_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_size), .auto_tl_master_clock_xing_out_16_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_source), .auto_tl_master_clock_xing_out_16_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_address), .auto_tl_master_clock_xing_out_16_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_mask), .auto_tl_master_clock_xing_out_16_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_data), .auto_tl_master_clock_xing_out_16_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_16_a_bits_corrupt), .auto_tl_master_clock_xing_out_16_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_16_d_ready), .auto_tl_master_clock_xing_out_16_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_16_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_16_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_16_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_16_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_16_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_16_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_16_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_16_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_16_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_15_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_15_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_valid), .auto_tl_master_clock_xing_out_15_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_opcode), .auto_tl_master_clock_xing_out_15_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_param), .auto_tl_master_clock_xing_out_15_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_size), .auto_tl_master_clock_xing_out_15_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_source), .auto_tl_master_clock_xing_out_15_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_address), .auto_tl_master_clock_xing_out_15_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_mask), .auto_tl_master_clock_xing_out_15_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_data), .auto_tl_master_clock_xing_out_15_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_15_a_bits_corrupt), .auto_tl_master_clock_xing_out_15_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_15_d_ready), .auto_tl_master_clock_xing_out_15_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_15_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_15_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_15_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_15_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_15_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_15_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_15_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_15_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_15_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_14_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_14_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_valid), .auto_tl_master_clock_xing_out_14_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_opcode), .auto_tl_master_clock_xing_out_14_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_param), .auto_tl_master_clock_xing_out_14_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_size), .auto_tl_master_clock_xing_out_14_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_source), .auto_tl_master_clock_xing_out_14_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_address), .auto_tl_master_clock_xing_out_14_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_mask), .auto_tl_master_clock_xing_out_14_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_data), .auto_tl_master_clock_xing_out_14_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_14_a_bits_corrupt), .auto_tl_master_clock_xing_out_14_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_14_d_ready), .auto_tl_master_clock_xing_out_14_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_14_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_14_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_14_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_14_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_14_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_14_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_14_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_14_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_14_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_13_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_13_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_valid), .auto_tl_master_clock_xing_out_13_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_opcode), .auto_tl_master_clock_xing_out_13_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_param), .auto_tl_master_clock_xing_out_13_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_size), .auto_tl_master_clock_xing_out_13_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_source), .auto_tl_master_clock_xing_out_13_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_address), .auto_tl_master_clock_xing_out_13_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_mask), .auto_tl_master_clock_xing_out_13_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_data), .auto_tl_master_clock_xing_out_13_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_13_a_bits_corrupt), .auto_tl_master_clock_xing_out_13_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_13_d_ready), .auto_tl_master_clock_xing_out_13_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_13_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_13_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_13_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_13_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_13_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_13_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_13_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_13_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_13_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_12_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_12_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_valid), .auto_tl_master_clock_xing_out_12_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_opcode), .auto_tl_master_clock_xing_out_12_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_param), .auto_tl_master_clock_xing_out_12_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_size), .auto_tl_master_clock_xing_out_12_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_source), .auto_tl_master_clock_xing_out_12_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_address), .auto_tl_master_clock_xing_out_12_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_mask), .auto_tl_master_clock_xing_out_12_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_data), .auto_tl_master_clock_xing_out_12_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_12_a_bits_corrupt), .auto_tl_master_clock_xing_out_12_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_12_d_ready), .auto_tl_master_clock_xing_out_12_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_12_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_12_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_12_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_12_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_12_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_12_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_12_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_12_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_12_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_11_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_11_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_valid), .auto_tl_master_clock_xing_out_11_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_opcode), .auto_tl_master_clock_xing_out_11_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_param), .auto_tl_master_clock_xing_out_11_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_size), .auto_tl_master_clock_xing_out_11_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_source), .auto_tl_master_clock_xing_out_11_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_address), .auto_tl_master_clock_xing_out_11_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_mask), .auto_tl_master_clock_xing_out_11_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_data), .auto_tl_master_clock_xing_out_11_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_11_a_bits_corrupt), .auto_tl_master_clock_xing_out_11_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_11_d_ready), .auto_tl_master_clock_xing_out_11_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_11_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_11_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_11_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_11_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_11_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_11_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_11_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_11_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_11_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_10_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_10_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_valid), .auto_tl_master_clock_xing_out_10_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_opcode), .auto_tl_master_clock_xing_out_10_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_param), .auto_tl_master_clock_xing_out_10_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_size), .auto_tl_master_clock_xing_out_10_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_source), .auto_tl_master_clock_xing_out_10_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_address), .auto_tl_master_clock_xing_out_10_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_mask), .auto_tl_master_clock_xing_out_10_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_data), .auto_tl_master_clock_xing_out_10_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_10_a_bits_corrupt), .auto_tl_master_clock_xing_out_10_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_10_d_ready), .auto_tl_master_clock_xing_out_10_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_10_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_10_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_10_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_10_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_10_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_10_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_10_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_10_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_10_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_9_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_9_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_valid), .auto_tl_master_clock_xing_out_9_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_opcode), .auto_tl_master_clock_xing_out_9_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_param), .auto_tl_master_clock_xing_out_9_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_size), .auto_tl_master_clock_xing_out_9_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_source), .auto_tl_master_clock_xing_out_9_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_address), .auto_tl_master_clock_xing_out_9_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_mask), .auto_tl_master_clock_xing_out_9_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_data), .auto_tl_master_clock_xing_out_9_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_9_a_bits_corrupt), .auto_tl_master_clock_xing_out_9_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_9_d_ready), .auto_tl_master_clock_xing_out_9_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_9_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_9_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_9_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_9_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_9_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_9_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_9_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_9_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_9_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_8_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_8_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_valid), .auto_tl_master_clock_xing_out_8_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_opcode), .auto_tl_master_clock_xing_out_8_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_param), .auto_tl_master_clock_xing_out_8_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_size), .auto_tl_master_clock_xing_out_8_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_source), .auto_tl_master_clock_xing_out_8_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_address), .auto_tl_master_clock_xing_out_8_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_mask), .auto_tl_master_clock_xing_out_8_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_data), .auto_tl_master_clock_xing_out_8_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_8_a_bits_corrupt), .auto_tl_master_clock_xing_out_8_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_8_d_ready), .auto_tl_master_clock_xing_out_8_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_8_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_8_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_8_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_8_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_8_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_8_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_8_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_8_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_8_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_7_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_7_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_valid), .auto_tl_master_clock_xing_out_7_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_opcode), .auto_tl_master_clock_xing_out_7_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_param), .auto_tl_master_clock_xing_out_7_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_size), .auto_tl_master_clock_xing_out_7_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_source), .auto_tl_master_clock_xing_out_7_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_address), .auto_tl_master_clock_xing_out_7_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_mask), .auto_tl_master_clock_xing_out_7_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_data), .auto_tl_master_clock_xing_out_7_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_7_a_bits_corrupt), .auto_tl_master_clock_xing_out_7_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_7_d_ready), .auto_tl_master_clock_xing_out_7_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_7_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_7_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_7_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_7_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_7_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_7_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_7_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_7_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_6_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_6_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_valid), .auto_tl_master_clock_xing_out_6_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_opcode), .auto_tl_master_clock_xing_out_6_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_param), .auto_tl_master_clock_xing_out_6_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_size), .auto_tl_master_clock_xing_out_6_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_source), .auto_tl_master_clock_xing_out_6_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_address), .auto_tl_master_clock_xing_out_6_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_mask), .auto_tl_master_clock_xing_out_6_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_data), .auto_tl_master_clock_xing_out_6_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_6_a_bits_corrupt), .auto_tl_master_clock_xing_out_6_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_6_d_ready), .auto_tl_master_clock_xing_out_6_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_6_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_6_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_6_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_6_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_6_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_6_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_6_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_6_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_5_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_5_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_valid), .auto_tl_master_clock_xing_out_5_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_opcode), .auto_tl_master_clock_xing_out_5_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_param), .auto_tl_master_clock_xing_out_5_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_size), .auto_tl_master_clock_xing_out_5_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_source), .auto_tl_master_clock_xing_out_5_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_address), .auto_tl_master_clock_xing_out_5_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_mask), .auto_tl_master_clock_xing_out_5_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_data), .auto_tl_master_clock_xing_out_5_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_5_a_bits_corrupt), .auto_tl_master_clock_xing_out_5_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_5_d_ready), .auto_tl_master_clock_xing_out_5_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_5_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_5_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_5_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_5_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_5_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_5_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_5_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_5_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_4_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_4_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_valid), .auto_tl_master_clock_xing_out_4_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_opcode), .auto_tl_master_clock_xing_out_4_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_param), .auto_tl_master_clock_xing_out_4_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_size), .auto_tl_master_clock_xing_out_4_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_source), .auto_tl_master_clock_xing_out_4_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_address), .auto_tl_master_clock_xing_out_4_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_mask), .auto_tl_master_clock_xing_out_4_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_data), .auto_tl_master_clock_xing_out_4_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_4_a_bits_corrupt), .auto_tl_master_clock_xing_out_4_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_4_d_ready), .auto_tl_master_clock_xing_out_4_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_4_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_4_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_4_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_4_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_4_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_4_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_4_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_4_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_3_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_3_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_valid), .auto_tl_master_clock_xing_out_3_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_opcode), .auto_tl_master_clock_xing_out_3_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_param), .auto_tl_master_clock_xing_out_3_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_size), .auto_tl_master_clock_xing_out_3_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_source), .auto_tl_master_clock_xing_out_3_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_address), .auto_tl_master_clock_xing_out_3_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_mask), .auto_tl_master_clock_xing_out_3_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_data), .auto_tl_master_clock_xing_out_3_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_3_a_bits_corrupt), .auto_tl_master_clock_xing_out_3_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_3_d_ready), .auto_tl_master_clock_xing_out_3_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_3_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_3_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_3_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_3_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_3_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_3_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_3_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_3_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_2_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_2_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_valid), .auto_tl_master_clock_xing_out_2_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_opcode), .auto_tl_master_clock_xing_out_2_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_param), .auto_tl_master_clock_xing_out_2_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_size), .auto_tl_master_clock_xing_out_2_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_source), .auto_tl_master_clock_xing_out_2_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_address), .auto_tl_master_clock_xing_out_2_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_mask), .auto_tl_master_clock_xing_out_2_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_data), .auto_tl_master_clock_xing_out_2_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_2_a_bits_corrupt), .auto_tl_master_clock_xing_out_2_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_2_d_ready), .auto_tl_master_clock_xing_out_2_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_2_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_2_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_2_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_2_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_2_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_2_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_2_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_2_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_valid), .auto_tl_master_clock_xing_out_1_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_opcode), .auto_tl_master_clock_xing_out_1_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_param), .auto_tl_master_clock_xing_out_1_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_size), .auto_tl_master_clock_xing_out_1_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_source), .auto_tl_master_clock_xing_out_1_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_address), .auto_tl_master_clock_xing_out_1_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_mask), .auto_tl_master_clock_xing_out_1_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_data), .auto_tl_master_clock_xing_out_1_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_corrupt), .auto_tl_master_clock_xing_out_1_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_1_d_ready), .auto_tl_master_clock_xing_out_1_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_valid), .auto_tl_master_clock_xing_out_0_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_opcode), .auto_tl_master_clock_xing_out_0_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_param), .auto_tl_master_clock_xing_out_0_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_size), .auto_tl_master_clock_xing_out_0_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_source), .auto_tl_master_clock_xing_out_0_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_address), .auto_tl_master_clock_xing_out_0_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_mask), .auto_tl_master_clock_xing_out_0_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_data), .auto_tl_master_clock_xing_out_0_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_corrupt), .auto_tl_master_clock_xing_out_0_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_0_d_ready), .auto_tl_master_clock_xing_out_0_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tap_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), // @[SystemBus.scala:31:26] .auto_tap_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_1_reset) // @[SystemBus.scala:31:26] ); // @[HasTiles.scala:163:38] IntXbar_i1_o1_1 xbar (); // @[Xbar.scala:52:26] IntXbar_i1_o1_2 xbar_1 ( // @[Xbar.scala:52:26] .auto_anon_in_0 (_tile_prci_domain_auto_intsink_out_1_0), // @[HasTiles.scala:163:38] .auto_anon_out_0 (tileWFISinkNodeIn_0) ); // @[Xbar.scala:52:26] IntXbar_i1_o1_3 xbar_2 (); // @[Xbar.scala:52:26] BundleBridgeNexus_UInt1_1 tileHartIdNexusNode ( // @[HasTiles.scala:75:39] .auto_out (_tileHartIdNexusNode_auto_out) ); // @[HasTiles.scala:75:39] CLINTClockSinkDomain clint_domain ( // @[BusWrapper.scala:89:28] .auto_clint_in_a_ready (_clint_domain_auto_clint_in_a_ready), .auto_clint_in_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_clint_in_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_clint_in_d_valid (_clint_domain_auto_clint_in_d_valid), .auto_clint_in_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), .auto_clint_in_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), .auto_clint_in_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), .auto_clint_in_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), .auto_int_in_clock_xing_out_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), .auto_int_in_clock_xing_out_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), // @[PeripheryBus.scala:37:26] .tick (int_rtc_tick), // @[Counter.scala:117:24] .clock (_clint_domain_clock), .reset (_clint_domain_reset) ); // @[BusWrapper.scala:89:28] PLICClockSinkDomain plic_domain ( // @[BusWrapper.scala:89:28] .auto_plic_int_in_0 (ibus_auto_int_bus_anon_out_0), // @[ClockDomain.scala:14:9] .auto_plic_in_a_ready (_plic_domain_auto_plic_in_a_ready), .auto_plic_in_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_plic_in_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_plic_in_d_valid (_plic_domain_auto_plic_in_d_valid), .auto_plic_in_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), .auto_plic_in_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), .auto_plic_in_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), .auto_plic_in_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), .auto_int_in_clock_xing_out_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), .auto_int_in_clock_xing_out_0_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_1_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] TLDebugModule tlDM ( // @[Periphery.scala:88:26] .auto_dmInner_dmInner_sb2tlOpt_out_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), .auto_dmInner_dmInner_sb2tlOpt_out_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), .auto_dmInner_dmInner_sb2tlOpt_out_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_tl_in_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), .auto_dmInner_dmInner_tl_in_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), .auto_dmInner_dmInner_tl_in_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), .auto_dmInner_dmInner_tl_in_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), .auto_dmInner_dmInner_tl_in_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), .auto_dmInner_dmInner_tl_in_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), .auto_dmOuter_int_out_sync_0 (debugNodesIn_sync_0), .io_debug_clock (debug_clock_0), // @[DigitalTop.scala:47:7] .io_debug_reset (debug_reset_0), // @[DigitalTop.scala:47:7] .io_tl_clock (domainIn_clock), // @[MixedNode.scala:551:17] .io_tl_reset (domainIn_reset), // @[MixedNode.scala:551:17] .io_ctrl_ndreset (debug_ndreset), .io_ctrl_dmactive (debug_dmactive_0), .io_ctrl_dmactiveAck (debug_dmactiveAck_0), // @[DigitalTop.scala:47:7] .io_dmi_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), .io_dmi_dmi_req_valid (_dtm_io_dmi_req_valid), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), // @[Periphery.scala:166:21] .io_dmi_dmi_resp_ready (_dtm_io_dmi_resp_ready), // @[Periphery.scala:166:21] .io_dmi_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), .io_dmi_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), .io_dmi_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), .io_dmi_dmiClock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_dmi_dmiReset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7] .io_hartIsInReset_0 (resetctrl_hartIsInReset_0_0) // @[DigitalTop.scala:47:7] ); // @[Periphery.scala:88:26] DebugCustomXbar debugCustomXbarOpt (); // @[Periphery.scala:80:75] BootROMClockSinkDomain bootrom_domain ( // @[BusWrapper.scala:89:28] .auto_bootrom_in_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), .auto_bootrom_in_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), .auto_bootrom_in_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), .auto_bootrom_in_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), .auto_bootrom_in_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_3_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] ScratchpadBank bank ( // @[Scratchpad.scala:65:28] .auto_xbar_anon_in_a_ready (_bank_auto_xbar_anon_in_a_ready), .auto_xbar_anon_in_a_valid (_mbus_auto_buffer_out_a_valid), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_param (_mbus_auto_buffer_out_a_bits_param), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_size (_mbus_auto_buffer_out_a_bits_size), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_source (_mbus_auto_buffer_out_a_bits_source), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_address (_mbus_auto_buffer_out_a_bits_address), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_data (_mbus_auto_buffer_out_a_bits_data), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_d_ready (_mbus_auto_buffer_out_d_ready), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_d_valid (_bank_auto_xbar_anon_in_d_valid), .auto_xbar_anon_in_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), .auto_xbar_anon_in_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), .auto_xbar_anon_in_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), .auto_xbar_anon_in_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), .auto_xbar_anon_in_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), .auto_xbar_anon_in_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), .auto_xbar_anon_in_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), .auto_xbar_anon_in_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), .auto_clock_in_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), // @[MemoryBus.scala:30:26] .auto_clock_in_reset (_mbus_auto_fixedClockNode_anon_out_0_reset) // @[MemoryBus.scala:30:26] ); // @[Scratchpad.scala:65:28] SerialTL0ClockSinkDomain serial_tl_domain ( // @[PeripheryTLSerial.scala:116:38] .auto_serdesser_client_out_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), .auto_serdesser_client_out_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), .auto_serdesser_client_out_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), .auto_serdesser_client_out_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), .auto_serdesser_client_out_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), .auto_serdesser_client_out_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), .auto_serdesser_client_out_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), .auto_serdesser_client_out_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), .auto_serdesser_client_out_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), .auto_serdesser_client_out_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), .auto_serdesser_client_out_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_clock_in_clock (_fbus_auto_fixedClockNode_anon_out_clock), // @[FrontBus.scala:23:26] .auto_clock_in_reset (_fbus_auto_fixedClockNode_anon_out_reset), // @[FrontBus.scala:23:26] .serial_tl_0_in_ready (serial_tl_0_in_ready_0), .serial_tl_0_in_valid (serial_tl_0_in_valid_0), // @[DigitalTop.scala:47:7] .serial_tl_0_in_bits_phit (serial_tl_0_in_bits_phit_0), // @[DigitalTop.scala:47:7] .serial_tl_0_out_ready (serial_tl_0_out_ready_0), // @[DigitalTop.scala:47:7] .serial_tl_0_out_valid (serial_tl_0_out_valid_0), .serial_tl_0_out_bits_phit (serial_tl_0_out_bits_phit_0), .serial_tl_0_clock_in (serial_tl_0_clock_in_0), // @[DigitalTop.scala:47:7] .serial_tl_0_debug_ser_busy (_serial_tl_domain_serial_tl_0_debug_ser_busy), .serial_tl_0_debug_des_busy (_serial_tl_domain_serial_tl_0_debug_des_busy) ); // @[PeripheryTLSerial.scala:116:38] TLUARTClockSinkDomain uartClockDomainWrapper ( // @[UART.scala:270:44] .auto_uart_0_int_xing_out_sync_0 (intXingIn_sync_0), .auto_uart_0_control_xing_in_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), .auto_uart_0_control_xing_in_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), .auto_uart_0_control_xing_in_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), .auto_uart_0_control_xing_in_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), .auto_uart_0_control_xing_in_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), .auto_uart_0_control_xing_in_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), .auto_uart_0_io_out_txd (ioNodeIn_txd), .auto_uart_0_io_out_rxd (ioNodeIn_rxd), // @[MixedNode.scala:551:17] .auto_clock_in_clock (_pbus_auto_fixedClockNode_anon_out_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_pbus_auto_fixedClockNode_anon_out_reset) // @[PeripheryBus.scala:37:26] ); // @[UART.scala:270:44] IntSyncSyncCrossingSink_n1x1_5 intsink ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intXingOut_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (ibus_auto_int_bus_anon_in_0) ); // @[Crossing.scala:109:29] ChipyardPRCICtrlClockSinkDomain chipyard_prcictrl_domain ( // @[BusWrapper.scala:89:28] .auto_reset_setter_clock_in_member_allClocks_uncore_clock (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[DigitalTop.scala:47:7] .auto_reset_setter_clock_in_member_allClocks_uncore_reset (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[DigitalTop.scala:47:7] .auto_resetSynchronizer_out_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), .auto_resetSynchronizer_out_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), .auto_xbar_anon_in_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), .auto_xbar_anon_in_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), .auto_xbar_anon_in_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), .auto_xbar_anon_in_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), .auto_xbar_anon_in_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), .auto_xbar_anon_in_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_4_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] ClockGroupAggregator_allClocks aggregator ( // @[HasChipyardPRCI.scala:51:30] .auto_in_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_out_5_member_clockTapNode_clockTapNode_clock_tap_clock (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock), .auto_out_5_member_clockTapNode_clockTapNode_clock_tap_reset (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset), .auto_out_4_member_cbus_cbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock), .auto_out_4_member_cbus_cbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset), .auto_out_3_member_mbus_mbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock), .auto_out_3_member_mbus_mbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset), .auto_out_2_member_fbus_fbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock), .auto_out_2_member_fbus_fbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset), .auto_out_1_member_pbus_pbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock), .auto_out_1_member_pbus_pbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset), .auto_out_0_member_sbus_sbus_1_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock), .auto_out_0_member_sbus_sbus_1_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset), .auto_out_0_member_sbus_sbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock), .auto_out_0_member_sbus_sbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset) ); // @[HasChipyardPRCI.scala:51:30] ClockGroupCombiner clockGroupCombiner ( // @[ClockGroupCombiner.scala:19:15] .auto_clock_group_combiner_in_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), // @[BusWrapper.scala:89:28] .auto_clock_group_combiner_in_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), // @[BusWrapper.scala:89:28] .auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock), .auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset), .auto_clock_group_combiner_out_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock), .auto_clock_group_combiner_out_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset), .auto_clock_group_combiner_out_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset) ); // @[ClockGroupCombiner.scala:19:15] ClockSinkDomain_1 globalNoCDomain ( // @[GlobalNoC.scala:45:40] .auto_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), // @[SystemBus.scala:31:26] .auto_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_2_reset) // @[SystemBus.scala:31:26] ); // @[GlobalNoC.scala:45:40] BundleBridgeNexus_NoOutput_8 reRoCCManagerIdNexusNode (); // @[Integration.scala:34:44] DebugTransportModuleJTAG dtm ( // @[Periphery.scala:166:21] .io_jtag_clock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_jtag_reset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7] .io_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), // @[Periphery.scala:88:26] .io_dmi_req_valid (_dtm_io_dmi_req_valid), .io_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), .io_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), .io_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), .io_dmi_resp_ready (_dtm_io_dmi_resp_ready), .io_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), // @[Periphery.scala:88:26] .io_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), // @[Periphery.scala:88:26] .io_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), // @[Periphery.scala:88:26] .io_jtag_TCK (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_jtag_TMS (debug_systemjtag_jtag_TMS_0), // @[DigitalTop.scala:47:7] .io_jtag_TDI (debug_systemjtag_jtag_TDI_0), // @[DigitalTop.scala:47:7] .io_jtag_TDO_data (debug_systemjtag_jtag_TDO_data_0), .io_jtag_TDO_driven (debug_systemjtag_jtag_TDO_driven), .rf_reset (debug_systemjtag_reset_0) // @[DigitalTop.scala:47:7] ); // @[Periphery.scala:166:21] assign auto_mbus_fixedClockNode_anon_out_clock = auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] assign auto_mbus_fixedClockNode_anon_out_reset = auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] assign auto_cbus_fixedClockNode_anon_out_clock = auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] assign auto_cbus_fixedClockNode_anon_out_reset = auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] assign debug_systemjtag_jtag_TDO_data = debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7] assign debug_dmactive = debug_dmactive_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_valid = mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_id = mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_addr = mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_len = mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_size = mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_burst = mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_lock = mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_cache = mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_prot = mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_qos = mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_valid = mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_data = mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_strb = mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_last = mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_b_ready = mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_valid = mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_id = mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_addr = mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_len = mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_size = mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_burst = mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_lock = mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_cache = mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_prot = mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_qos = mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_r_ready = mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_in_ready = serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_out_valid = serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_out_bits_phit = serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7] assign uart_0_txd = uart_0_txd_0; // @[DigitalTop.scala:47:7] assign clock_tap = clockTapIn_clock; // @[MixedNode.scala:551:17] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_73 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_73( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLDToNoC_4 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<129>, egress_id : UInt}}} inst q of Queue1_TLBundleD_a32d128s7k6z4c_4 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 5, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 4) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 5, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 4) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo_hi = cat(q.io.deq.bits.source, q.io.deq.bits.sink) node const_lo = cat(const_lo_hi, q.io.deq.bits.denied) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_uncommonBits_T = or(q.io.deq.bits.source, UInt<5>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T, 4, 0) node _io_flit_bits_egress_id_requestOH_T = shr(q.io.deq.bits.source, 5) node _io_flit_bits_egress_id_requestOH_T_1 = eq(_io_flit_bits_egress_id_requestOH_T, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_2 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits) node _io_flit_bits_egress_id_requestOH_T_3 = and(_io_flit_bits_egress_id_requestOH_T_1, _io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = leq(io_flit_bits_egress_id_requestOH_uncommonBits, UInt<5>(0h1f)) node io_flit_bits_egress_id_requestOH_0 = and(_io_flit_bits_egress_id_requestOH_T_3, _io_flit_bits_egress_id_requestOH_T_4) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_1 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_1 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_1, 1, 0) node _io_flit_bits_egress_id_requestOH_T_5 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_6 = eq(_io_flit_bits_egress_id_requestOH_T_5, UInt<5>(0h13)) node _io_flit_bits_egress_id_requestOH_T_7 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_1) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_6, _io_flit_bits_egress_id_requestOH_T_7) node _io_flit_bits_egress_id_requestOH_T_9 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_1, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_1 = and(_io_flit_bits_egress_id_requestOH_T_8, _io_flit_bits_egress_id_requestOH_T_9) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_2 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_2 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_2, 1, 0) node _io_flit_bits_egress_id_requestOH_T_10 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_11 = eq(_io_flit_bits_egress_id_requestOH_T_10, UInt<5>(0h12)) node _io_flit_bits_egress_id_requestOH_T_12 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_2) node _io_flit_bits_egress_id_requestOH_T_13 = and(_io_flit_bits_egress_id_requestOH_T_11, _io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_2, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_2 = and(_io_flit_bits_egress_id_requestOH_T_13, _io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_3 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_3 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_3, 1, 0) node _io_flit_bits_egress_id_requestOH_T_15 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, UInt<5>(0h11)) node _io_flit_bits_egress_id_requestOH_T_17 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_3) node _io_flit_bits_egress_id_requestOH_T_18 = and(_io_flit_bits_egress_id_requestOH_T_16, _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_19 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_3, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_3 = and(_io_flit_bits_egress_id_requestOH_T_18, _io_flit_bits_egress_id_requestOH_T_19) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_4 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_4 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_4, 1, 0) node _io_flit_bits_egress_id_requestOH_T_20 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_21 = eq(_io_flit_bits_egress_id_requestOH_T_20, UInt<5>(0h10)) node _io_flit_bits_egress_id_requestOH_T_22 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_4) node _io_flit_bits_egress_id_requestOH_T_23 = and(_io_flit_bits_egress_id_requestOH_T_21, _io_flit_bits_egress_id_requestOH_T_22) node _io_flit_bits_egress_id_requestOH_T_24 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_4, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_4 = and(_io_flit_bits_egress_id_requestOH_T_23, _io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_5 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_5 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_5, 1, 0) node _io_flit_bits_egress_id_requestOH_T_25 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_26 = eq(_io_flit_bits_egress_id_requestOH_T_25, UInt<4>(0hf)) node _io_flit_bits_egress_id_requestOH_T_27 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_5) node _io_flit_bits_egress_id_requestOH_T_28 = and(_io_flit_bits_egress_id_requestOH_T_26, _io_flit_bits_egress_id_requestOH_T_27) node _io_flit_bits_egress_id_requestOH_T_29 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_5, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_5 = and(_io_flit_bits_egress_id_requestOH_T_28, _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_6 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_6 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_6, 1, 0) node _io_flit_bits_egress_id_requestOH_T_30 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_31 = eq(_io_flit_bits_egress_id_requestOH_T_30, UInt<4>(0he)) node _io_flit_bits_egress_id_requestOH_T_32 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_6) node _io_flit_bits_egress_id_requestOH_T_33 = and(_io_flit_bits_egress_id_requestOH_T_31, _io_flit_bits_egress_id_requestOH_T_32) node _io_flit_bits_egress_id_requestOH_T_34 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_6, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_6 = and(_io_flit_bits_egress_id_requestOH_T_33, _io_flit_bits_egress_id_requestOH_T_34) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_7 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_7 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_7, 1, 0) node _io_flit_bits_egress_id_requestOH_T_35 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_36 = eq(_io_flit_bits_egress_id_requestOH_T_35, UInt<4>(0hd)) node _io_flit_bits_egress_id_requestOH_T_37 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_7) node _io_flit_bits_egress_id_requestOH_T_38 = and(_io_flit_bits_egress_id_requestOH_T_36, _io_flit_bits_egress_id_requestOH_T_37) node _io_flit_bits_egress_id_requestOH_T_39 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_7, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_7 = and(_io_flit_bits_egress_id_requestOH_T_38, _io_flit_bits_egress_id_requestOH_T_39) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_8 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_8 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_8, 1, 0) node _io_flit_bits_egress_id_requestOH_T_40 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_41 = eq(_io_flit_bits_egress_id_requestOH_T_40, UInt<4>(0hc)) node _io_flit_bits_egress_id_requestOH_T_42 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_8) node _io_flit_bits_egress_id_requestOH_T_43 = and(_io_flit_bits_egress_id_requestOH_T_41, _io_flit_bits_egress_id_requestOH_T_42) node _io_flit_bits_egress_id_requestOH_T_44 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_8, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_8 = and(_io_flit_bits_egress_id_requestOH_T_43, _io_flit_bits_egress_id_requestOH_T_44) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_9 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_9 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_9, 1, 0) node _io_flit_bits_egress_id_requestOH_T_45 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_46 = eq(_io_flit_bits_egress_id_requestOH_T_45, UInt<4>(0hb)) node _io_flit_bits_egress_id_requestOH_T_47 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_9) node _io_flit_bits_egress_id_requestOH_T_48 = and(_io_flit_bits_egress_id_requestOH_T_46, _io_flit_bits_egress_id_requestOH_T_47) node _io_flit_bits_egress_id_requestOH_T_49 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_9, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_9 = and(_io_flit_bits_egress_id_requestOH_T_48, _io_flit_bits_egress_id_requestOH_T_49) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_10 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_10 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_10, 1, 0) node _io_flit_bits_egress_id_requestOH_T_50 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_51 = eq(_io_flit_bits_egress_id_requestOH_T_50, UInt<4>(0ha)) node _io_flit_bits_egress_id_requestOH_T_52 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_10) node _io_flit_bits_egress_id_requestOH_T_53 = and(_io_flit_bits_egress_id_requestOH_T_51, _io_flit_bits_egress_id_requestOH_T_52) node _io_flit_bits_egress_id_requestOH_T_54 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_10, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_10 = and(_io_flit_bits_egress_id_requestOH_T_53, _io_flit_bits_egress_id_requestOH_T_54) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_11 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_11 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_11, 1, 0) node _io_flit_bits_egress_id_requestOH_T_55 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_56 = eq(_io_flit_bits_egress_id_requestOH_T_55, UInt<4>(0h9)) node _io_flit_bits_egress_id_requestOH_T_57 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_11) node _io_flit_bits_egress_id_requestOH_T_58 = and(_io_flit_bits_egress_id_requestOH_T_56, _io_flit_bits_egress_id_requestOH_T_57) node _io_flit_bits_egress_id_requestOH_T_59 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_11, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_11 = and(_io_flit_bits_egress_id_requestOH_T_58, _io_flit_bits_egress_id_requestOH_T_59) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_12 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_12 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_12, 1, 0) node _io_flit_bits_egress_id_requestOH_T_60 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_61 = eq(_io_flit_bits_egress_id_requestOH_T_60, UInt<4>(0h8)) node _io_flit_bits_egress_id_requestOH_T_62 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_12) node _io_flit_bits_egress_id_requestOH_T_63 = and(_io_flit_bits_egress_id_requestOH_T_61, _io_flit_bits_egress_id_requestOH_T_62) node _io_flit_bits_egress_id_requestOH_T_64 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_12, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_12 = and(_io_flit_bits_egress_id_requestOH_T_63, _io_flit_bits_egress_id_requestOH_T_64) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<1>(0h0), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<1>(0h1), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<2>(0h2), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<2>(0h3), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<3>(0h4), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = mux(io_flit_bits_egress_id_requestOH_5, UInt<3>(0h5), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_6 = mux(io_flit_bits_egress_id_requestOH_6, UInt<3>(0h6), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_7 = mux(io_flit_bits_egress_id_requestOH_7, UInt<3>(0h7), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_8 = mux(io_flit_bits_egress_id_requestOH_8, UInt<4>(0h8), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_9 = mux(io_flit_bits_egress_id_requestOH_9, UInt<4>(0h9), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_10 = mux(io_flit_bits_egress_id_requestOH_10, UInt<4>(0ha), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_11 = mux(io_flit_bits_egress_id_requestOH_11, UInt<4>(0hb), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_12 = mux(io_flit_bits_egress_id_requestOH_12, UInt<4>(0hc), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_13 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_14 = or(_io_flit_bits_egress_id_T_13, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_15 = or(_io_flit_bits_egress_id_T_14, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_16 = or(_io_flit_bits_egress_id_T_15, _io_flit_bits_egress_id_T_4) node _io_flit_bits_egress_id_T_17 = or(_io_flit_bits_egress_id_T_16, _io_flit_bits_egress_id_T_5) node _io_flit_bits_egress_id_T_18 = or(_io_flit_bits_egress_id_T_17, _io_flit_bits_egress_id_T_6) node _io_flit_bits_egress_id_T_19 = or(_io_flit_bits_egress_id_T_18, _io_flit_bits_egress_id_T_7) node _io_flit_bits_egress_id_T_20 = or(_io_flit_bits_egress_id_T_19, _io_flit_bits_egress_id_T_8) node _io_flit_bits_egress_id_T_21 = or(_io_flit_bits_egress_id_T_20, _io_flit_bits_egress_id_T_9) node _io_flit_bits_egress_id_T_22 = or(_io_flit_bits_egress_id_T_21, _io_flit_bits_egress_id_T_10) node _io_flit_bits_egress_id_T_23 = or(_io_flit_bits_egress_id_T_22, _io_flit_bits_egress_id_T_11) node _io_flit_bits_egress_id_T_24 = or(_io_flit_bits_egress_id_T_23, _io_flit_bits_egress_id_T_12) wire _io_flit_bits_egress_id_WIRE : UInt<4> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_24 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_sink_T = or(io.protocol.bits.sink, UInt<1>(0h0)) connect q.io.enq.bits.sink, _q_io_enq_bits_sink_T
module TLDToNoC_4( // @[TilelinkAdapters.scala:171:7] input clock, // @[TilelinkAdapters.scala:171:7] input reset, // @[TilelinkAdapters.scala:171:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_denied, // @[TilelinkAdapters.scala:19:14] input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [3:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_denied; // @[TilelinkAdapters.scala:26:17] wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [20:0] _tail_beats1_decode_T = 21'h3F << _q_io_deq_bits_size; // @[package.scala:243:71] reg [1:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire [1:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:4]) : 2'h0; // @[package.scala:243:{46,71,76}] reg [1:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 2'h1 | tail_beats1 == 2'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:171:7] if (reset) begin // @[TilelinkAdapters.scala:171:7] head_counter <= 2'h0; // @[Edges.scala:229:27] tail_counter <= 2'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :171:7] end else begin // @[TilelinkAdapters.scala:171:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:4]) : 2'h0) : head_counter - 2'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 2'h0 ? tail_beats1 : tail_counter - 2'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_36 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_329 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_330 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_331 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_332 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_36( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_329 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_330 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_331 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_332 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_10 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_10( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire _common_underflow_T_7 = io_detectTininess_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :222:49] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_7 & _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:{49,77}, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [8:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [8:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [22:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RocketTile : input clock : Clock input reset : Reset output auto : { buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, wfi_out : UInt<1>[1], cease_out : UInt<1>[1], halt_out : UInt<1>[1], flip int_local_in_3 : UInt<1>[1], flip int_local_in_2 : UInt<1>[1], flip int_local_in_1 : UInt<1>[2], flip int_local_in_0 : UInt<1>[1], trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip reset_vector_in : UInt<32>, flip hartid_in : UInt<1>} inst tlMasterXbar of TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s3k3z4c connect tlMasterXbar.clock, clock connect tlMasterXbar.reset, reset inst tlSlaveXbar of TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u connect tlSlaveXbar.clock, clock connect tlSlaveXbar.reset, reset inst intXbar of IntXbar_i4_o1 inst broadcast of BundleBridgeNexus_UInt1 inst broadcast_1 of BundleBridgeNexus_UInt32 inst nexus of BundleBridgeNexus_NoOutput_6 inst nexus_1 of BundleBridgeNexus_TraceAux inst broadcast_2 of BundleBridgeNexus_NoOutput_7 inst widget of TLWidthWidget8_8 connect widget.clock, clock connect widget.reset, reset inst dcache of HellaCachePrefetchWrapper connect dcache.clock, clock connect dcache.reset, reset inst frontend of Frontend connect frontend.clock, clock connect frontend.reset, reset inst widget_1 of TLWidthWidget8_9 connect widget_1.clock, clock connect widget_1.reset, reset inst fragmenter of TLFragmenter connect fragmenter.clock, clock connect fragmenter.reset, reset inst widget_2 of TLWidthWidget8_10 connect widget_2.clock, clock connect widget_2.reset, reset inst buffer of TLBuffer_a32d64s3k3z4c connect buffer.clock, clock connect buffer.reset, reset inst buffer_1 of TLBuffer_1 connect buffer_1.clock, clock connect buffer_1.reset, reset wire tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate tlOtherMastersNodeOut.e.bits.sink invalidate tlOtherMastersNodeOut.e.valid invalidate tlOtherMastersNodeOut.e.ready invalidate tlOtherMastersNodeOut.d.bits.corrupt invalidate tlOtherMastersNodeOut.d.bits.data invalidate tlOtherMastersNodeOut.d.bits.denied invalidate tlOtherMastersNodeOut.d.bits.sink invalidate tlOtherMastersNodeOut.d.bits.source invalidate tlOtherMastersNodeOut.d.bits.size invalidate tlOtherMastersNodeOut.d.bits.param invalidate tlOtherMastersNodeOut.d.bits.opcode invalidate tlOtherMastersNodeOut.d.valid invalidate tlOtherMastersNodeOut.d.ready invalidate tlOtherMastersNodeOut.c.bits.corrupt invalidate tlOtherMastersNodeOut.c.bits.data invalidate tlOtherMastersNodeOut.c.bits.address invalidate tlOtherMastersNodeOut.c.bits.source invalidate tlOtherMastersNodeOut.c.bits.size invalidate tlOtherMastersNodeOut.c.bits.param invalidate tlOtherMastersNodeOut.c.bits.opcode invalidate tlOtherMastersNodeOut.c.valid invalidate tlOtherMastersNodeOut.c.ready invalidate tlOtherMastersNodeOut.b.bits.corrupt invalidate tlOtherMastersNodeOut.b.bits.data invalidate tlOtherMastersNodeOut.b.bits.mask invalidate tlOtherMastersNodeOut.b.bits.address invalidate tlOtherMastersNodeOut.b.bits.source invalidate tlOtherMastersNodeOut.b.bits.size invalidate tlOtherMastersNodeOut.b.bits.param invalidate tlOtherMastersNodeOut.b.bits.opcode invalidate tlOtherMastersNodeOut.b.valid invalidate tlOtherMastersNodeOut.b.ready invalidate tlOtherMastersNodeOut.a.bits.corrupt invalidate tlOtherMastersNodeOut.a.bits.data invalidate tlOtherMastersNodeOut.a.bits.mask invalidate tlOtherMastersNodeOut.a.bits.address invalidate tlOtherMastersNodeOut.a.bits.source invalidate tlOtherMastersNodeOut.a.bits.size invalidate tlOtherMastersNodeOut.a.bits.param invalidate tlOtherMastersNodeOut.a.bits.opcode invalidate tlOtherMastersNodeOut.a.valid invalidate tlOtherMastersNodeOut.a.ready wire tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate tlOtherMastersNodeIn.e.bits.sink invalidate tlOtherMastersNodeIn.e.valid invalidate tlOtherMastersNodeIn.e.ready invalidate tlOtherMastersNodeIn.d.bits.corrupt invalidate tlOtherMastersNodeIn.d.bits.data invalidate tlOtherMastersNodeIn.d.bits.denied invalidate tlOtherMastersNodeIn.d.bits.sink invalidate tlOtherMastersNodeIn.d.bits.source invalidate tlOtherMastersNodeIn.d.bits.size invalidate tlOtherMastersNodeIn.d.bits.param invalidate tlOtherMastersNodeIn.d.bits.opcode invalidate tlOtherMastersNodeIn.d.valid invalidate tlOtherMastersNodeIn.d.ready invalidate tlOtherMastersNodeIn.c.bits.corrupt invalidate tlOtherMastersNodeIn.c.bits.data invalidate tlOtherMastersNodeIn.c.bits.address invalidate tlOtherMastersNodeIn.c.bits.source invalidate tlOtherMastersNodeIn.c.bits.size invalidate tlOtherMastersNodeIn.c.bits.param invalidate tlOtherMastersNodeIn.c.bits.opcode invalidate tlOtherMastersNodeIn.c.valid invalidate tlOtherMastersNodeIn.c.ready invalidate tlOtherMastersNodeIn.b.bits.corrupt invalidate tlOtherMastersNodeIn.b.bits.data invalidate tlOtherMastersNodeIn.b.bits.mask invalidate tlOtherMastersNodeIn.b.bits.address invalidate tlOtherMastersNodeIn.b.bits.source invalidate tlOtherMastersNodeIn.b.bits.size invalidate tlOtherMastersNodeIn.b.bits.param invalidate tlOtherMastersNodeIn.b.bits.opcode invalidate tlOtherMastersNodeIn.b.valid invalidate tlOtherMastersNodeIn.b.ready invalidate tlOtherMastersNodeIn.a.bits.corrupt invalidate tlOtherMastersNodeIn.a.bits.data invalidate tlOtherMastersNodeIn.a.bits.mask invalidate tlOtherMastersNodeIn.a.bits.address invalidate tlOtherMastersNodeIn.a.bits.source invalidate tlOtherMastersNodeIn.a.bits.size invalidate tlOtherMastersNodeIn.a.bits.param invalidate tlOtherMastersNodeIn.a.bits.opcode invalidate tlOtherMastersNodeIn.a.valid invalidate tlOtherMastersNodeIn.a.ready connect tlOtherMastersNodeOut, tlOtherMastersNodeIn wire hartIdSinkNodeIn : UInt<1> invalidate hartIdSinkNodeIn wire hartidOut : UInt<1> invalidate hartidOut wire hartidIn : UInt<1> invalidate hartidIn connect hartidOut, hartidIn wire resetVectorSinkNodeIn : UInt<32> invalidate resetVectorSinkNodeIn wire reset_vectorOut : UInt<32> invalidate reset_vectorOut wire reset_vectorIn : UInt<32> invalidate reset_vectorIn connect reset_vectorOut, reset_vectorIn wire traceSourceNodeOut : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceSourceNodeOut.time invalidate traceSourceNodeOut.insns[0].tval invalidate traceSourceNodeOut.insns[0].cause invalidate traceSourceNodeOut.insns[0].interrupt invalidate traceSourceNodeOut.insns[0].exception invalidate traceSourceNodeOut.insns[0].priv invalidate traceSourceNodeOut.insns[0].insn invalidate traceSourceNodeOut.insns[0].iaddr invalidate traceSourceNodeOut.insns[0].valid wire traceCoreSourceNodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreSourceNodeOut.cause invalidate traceCoreSourceNodeOut.tval invalidate traceCoreSourceNodeOut.priv invalidate traceCoreSourceNodeOut.group[0].ilastsize invalidate traceCoreSourceNodeOut.group[0].itype invalidate traceCoreSourceNodeOut.group[0].iaddr invalidate traceCoreSourceNodeOut.group[0].iretire wire bundleIn_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>} connect bundleIn_x_sourceOpt.stall, UInt<1>(0h0) connect bundleIn_x_sourceOpt.enable, UInt<1>(0h0) wire traceAuxSinkNodeIn : { enable : UInt<1>, stall : UInt<1>} invalidate traceAuxSinkNodeIn.stall invalidate traceAuxSinkNodeIn.enable wire bpwatchSourceNodeOut : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1] invalidate bpwatchSourceNodeOut[0].action invalidate bpwatchSourceNodeOut[0].ivalid[0] invalidate bpwatchSourceNodeOut[0].wvalid[0] invalidate bpwatchSourceNodeOut[0].rvalid[0] invalidate bpwatchSourceNodeOut[0].valid[0] wire int_localOut : UInt<1>[1] invalidate int_localOut[0] wire x1_int_localOut : UInt<1>[2] invalidate x1_int_localOut[0] invalidate x1_int_localOut[1] wire x1_int_localOut_1 : UInt<1>[1] invalidate x1_int_localOut_1[0] wire x1_int_localOut_2 : UInt<1>[1] invalidate x1_int_localOut_2[0] wire int_localIn : UInt<1>[1] invalidate int_localIn[0] wire x1_int_localIn : UInt<1>[2] invalidate x1_int_localIn[0] invalidate x1_int_localIn[1] wire x1_int_localIn_1 : UInt<1>[1] invalidate x1_int_localIn_1[0] wire x1_int_localIn_2 : UInt<1>[1] invalidate x1_int_localIn_2[0] connect int_localOut, int_localIn connect x1_int_localOut, x1_int_localIn connect x1_int_localOut_1, x1_int_localIn_1 connect x1_int_localOut_2, x1_int_localIn_2 wire intSinkNodeIn : UInt<1>[5] invalidate intSinkNodeIn[0] invalidate intSinkNodeIn[1] invalidate intSinkNodeIn[2] invalidate intSinkNodeIn[3] invalidate intSinkNodeIn[4] wire haltNodeOut : UInt<1>[1] invalidate haltNodeOut[0] wire ceaseNodeOut : UInt<1>[1] invalidate ceaseNodeOut[0] wire wfiNodeOut : UInt<1>[1] invalidate wfiNodeOut[0] connect buffer.auto.in, tlOtherMastersNodeOut connect tlOtherMastersNodeIn.e.bits, tlMasterXbar.auto.anon_out.e.bits connect tlOtherMastersNodeIn.e.valid, tlMasterXbar.auto.anon_out.e.valid connect tlMasterXbar.auto.anon_out.e.ready, tlOtherMastersNodeIn.e.ready connect tlMasterXbar.auto.anon_out.d, tlOtherMastersNodeIn.d connect tlOtherMastersNodeIn.c.bits, tlMasterXbar.auto.anon_out.c.bits connect tlOtherMastersNodeIn.c.valid, tlMasterXbar.auto.anon_out.c.valid connect tlMasterXbar.auto.anon_out.c.ready, tlOtherMastersNodeIn.c.ready connect tlMasterXbar.auto.anon_out.b, tlOtherMastersNodeIn.b connect tlOtherMastersNodeIn.a.bits, tlMasterXbar.auto.anon_out.a.bits connect tlOtherMastersNodeIn.a.valid, tlMasterXbar.auto.anon_out.a.valid connect tlMasterXbar.auto.anon_out.a.ready, tlOtherMastersNodeIn.a.ready connect intSinkNodeIn, intXbar.auto.anon_out connect hartIdSinkNodeIn, broadcast.auto.out connect broadcast.auto.in, hartidOut connect resetVectorSinkNodeIn, broadcast_1.auto.out_0 connect frontend.auto.reset_vector_sink_in, broadcast_1.auto.out_1 connect broadcast_1.auto.in, reset_vectorOut connect traceAuxSinkNodeIn, nexus_1.auto.out connect broadcast_2.auto.in[0], bpwatchSourceNodeOut[0] connect intXbar.auto.anon_in_0[0], int_localOut[0] connect intXbar.auto.anon_in_1[0], x1_int_localOut[0] connect intXbar.auto.anon_in_1[1], x1_int_localOut[1] connect intXbar.auto.anon_in_2[0], x1_int_localOut_1[0] connect intXbar.auto.anon_in_3[0], x1_int_localOut_2[0] connect tlMasterXbar.auto.anon_in_0, widget.auto.anon_out connect widget.auto.anon_in, dcache.auto.cache_out connect widget_1.auto.anon_in, frontend.auto.icache_master_out connect tlMasterXbar.auto.anon_in_1, widget_1.auto.anon_out connect hartidIn, auto.hartid_in connect reset_vectorIn, auto.reset_vector_in connect auto.trace_source_out, traceSourceNodeOut connect auto.trace_core_source_out, traceCoreSourceNodeOut connect int_localIn, auto.int_local_in_0 connect x1_int_localIn, auto.int_local_in_1 connect x1_int_localIn_1, auto.int_local_in_2 connect x1_int_localIn_2, auto.int_local_in_3 connect auto.halt_out, haltNodeOut connect auto.cease_out, ceaseNodeOut connect auto.wfi_out, wfiNodeOut connect auto.buffer_out.e.bits, buffer.auto.out.e.bits connect auto.buffer_out.e.valid, buffer.auto.out.e.valid connect buffer.auto.out.e.ready, auto.buffer_out.e.ready connect buffer.auto.out.d, auto.buffer_out.d connect auto.buffer_out.c.bits, buffer.auto.out.c.bits connect auto.buffer_out.c.valid, buffer.auto.out.c.valid connect buffer.auto.out.c.ready, auto.buffer_out.c.ready connect buffer.auto.out.b, auto.buffer_out.b connect auto.buffer_out.a.bits, buffer.auto.out.a.bits connect auto.buffer_out.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, auto.buffer_out.a.ready invalidate dcache.io.tlb_port.s2_kill invalidate dcache.io.tlb_port.s1_resp.cmd invalidate dcache.io.tlb_port.s1_resp.size invalidate dcache.io.tlb_port.s1_resp.prefetchable invalidate dcache.io.tlb_port.s1_resp.must_alloc invalidate dcache.io.tlb_port.s1_resp.cacheable invalidate dcache.io.tlb_port.s1_resp.ma.inst invalidate dcache.io.tlb_port.s1_resp.ma.st invalidate dcache.io.tlb_port.s1_resp.ma.ld invalidate dcache.io.tlb_port.s1_resp.ae.inst invalidate dcache.io.tlb_port.s1_resp.ae.st invalidate dcache.io.tlb_port.s1_resp.ae.ld invalidate dcache.io.tlb_port.s1_resp.gf.inst invalidate dcache.io.tlb_port.s1_resp.gf.st invalidate dcache.io.tlb_port.s1_resp.gf.ld invalidate dcache.io.tlb_port.s1_resp.pf.inst invalidate dcache.io.tlb_port.s1_resp.pf.st invalidate dcache.io.tlb_port.s1_resp.pf.ld invalidate dcache.io.tlb_port.s1_resp.gpa_is_pte invalidate dcache.io.tlb_port.s1_resp.gpa invalidate dcache.io.tlb_port.s1_resp.paddr invalidate dcache.io.tlb_port.s1_resp.miss invalidate dcache.io.tlb_port.req.bits.v invalidate dcache.io.tlb_port.req.bits.prv invalidate dcache.io.tlb_port.req.bits.cmd invalidate dcache.io.tlb_port.req.bits.size invalidate dcache.io.tlb_port.req.bits.passthrough invalidate dcache.io.tlb_port.req.bits.vaddr invalidate dcache.io.tlb_port.req.valid invalidate dcache.io.tlb_port.req.ready inst fpuOpt of FPU connect fpuOpt.clock, clock connect fpuOpt.reset, reset connect fpuOpt.io.cp_req.valid, UInt<1>(0h0) invalidate fpuOpt.io.cp_req.bits.in3 invalidate fpuOpt.io.cp_req.bits.in2 invalidate fpuOpt.io.cp_req.bits.in1 invalidate fpuOpt.io.cp_req.bits.fmt invalidate fpuOpt.io.cp_req.bits.typ invalidate fpuOpt.io.cp_req.bits.fmaCmd invalidate fpuOpt.io.cp_req.bits.rm invalidate fpuOpt.io.cp_req.bits.vec invalidate fpuOpt.io.cp_req.bits.wflags invalidate fpuOpt.io.cp_req.bits.sqrt invalidate fpuOpt.io.cp_req.bits.div invalidate fpuOpt.io.cp_req.bits.fma invalidate fpuOpt.io.cp_req.bits.fastpipe invalidate fpuOpt.io.cp_req.bits.toint invalidate fpuOpt.io.cp_req.bits.fromint invalidate fpuOpt.io.cp_req.bits.typeTagOut invalidate fpuOpt.io.cp_req.bits.typeTagIn invalidate fpuOpt.io.cp_req.bits.swap23 invalidate fpuOpt.io.cp_req.bits.swap12 invalidate fpuOpt.io.cp_req.bits.ren3 invalidate fpuOpt.io.cp_req.bits.ren2 invalidate fpuOpt.io.cp_req.bits.ren1 invalidate fpuOpt.io.cp_req.bits.wen invalidate fpuOpt.io.cp_req.bits.ldst connect fpuOpt.io.cp_resp.ready, UInt<1>(0h0) inst dcacheArb of HellaCacheArbiter connect dcacheArb.clock, clock connect dcacheArb.reset, reset connect dcache.io.cpu, dcacheArb.io.mem inst ptw of PTW connect ptw.clock, clock connect ptw.reset, reset invalidate ptw.io.mem.clock_enabled invalidate ptw.io.mem.keep_clock_enabled invalidate ptw.io.mem.perf.storeBufferEmptyAfterStore invalidate ptw.io.mem.perf.storeBufferEmptyAfterLoad invalidate ptw.io.mem.perf.canAcceptLoadThenLoad invalidate ptw.io.mem.perf.canAcceptStoreThenRMW invalidate ptw.io.mem.perf.canAcceptStoreThenLoad invalidate ptw.io.mem.perf.blocked invalidate ptw.io.mem.perf.tlbMiss invalidate ptw.io.mem.perf.grant invalidate ptw.io.mem.perf.release invalidate ptw.io.mem.perf.acquire invalidate ptw.io.mem.store_pending invalidate ptw.io.mem.ordered invalidate ptw.io.mem.s2_gpa_is_pte invalidate ptw.io.mem.s2_gpa invalidate ptw.io.mem.s2_xcpt.ae.st invalidate ptw.io.mem.s2_xcpt.ae.ld invalidate ptw.io.mem.s2_xcpt.gf.st invalidate ptw.io.mem.s2_xcpt.gf.ld invalidate ptw.io.mem.s2_xcpt.pf.st invalidate ptw.io.mem.s2_xcpt.pf.ld invalidate ptw.io.mem.s2_xcpt.ma.st invalidate ptw.io.mem.s2_xcpt.ma.ld invalidate ptw.io.mem.replay_next invalidate ptw.io.mem.resp.bits.store_data invalidate ptw.io.mem.resp.bits.data_raw invalidate ptw.io.mem.resp.bits.data_word_bypass invalidate ptw.io.mem.resp.bits.has_data invalidate ptw.io.mem.resp.bits.replay invalidate ptw.io.mem.resp.bits.mask invalidate ptw.io.mem.resp.bits.data invalidate ptw.io.mem.resp.bits.dv invalidate ptw.io.mem.resp.bits.dprv invalidate ptw.io.mem.resp.bits.signed invalidate ptw.io.mem.resp.bits.size invalidate ptw.io.mem.resp.bits.cmd invalidate ptw.io.mem.resp.bits.tag invalidate ptw.io.mem.resp.bits.addr invalidate ptw.io.mem.resp.valid invalidate ptw.io.mem.s2_paddr invalidate ptw.io.mem.s2_uncached invalidate ptw.io.mem.s2_kill invalidate ptw.io.mem.s2_nack_cause_raw invalidate ptw.io.mem.s2_nack invalidate ptw.io.mem.s1_data.mask invalidate ptw.io.mem.s1_data.data invalidate ptw.io.mem.s1_kill invalidate ptw.io.mem.req.bits.mask invalidate ptw.io.mem.req.bits.data invalidate ptw.io.mem.req.bits.no_xcpt invalidate ptw.io.mem.req.bits.no_alloc invalidate ptw.io.mem.req.bits.no_resp invalidate ptw.io.mem.req.bits.phys invalidate ptw.io.mem.req.bits.dv invalidate ptw.io.mem.req.bits.dprv invalidate ptw.io.mem.req.bits.signed invalidate ptw.io.mem.req.bits.size invalidate ptw.io.mem.req.bits.cmd invalidate ptw.io.mem.req.bits.tag invalidate ptw.io.mem.req.bits.addr invalidate ptw.io.mem.req.valid invalidate ptw.io.mem.req.ready inst core of Rocket connect core.clock, clock connect core.reset, reset invalidate core.io.reset_vector connect haltNodeOut[0], UInt<1>(0h0) connect ceaseNodeOut[0], UInt<1>(0h0) regreset wfiNodeOut_0_REG : UInt<1>, clock, reset, UInt<1>(0h0) connect wfiNodeOut_0_REG, core.io.wfi connect wfiNodeOut[0], wfiNodeOut_0_REG connect core.io.interrupts.debug, intSinkNodeIn[0] connect core.io.interrupts.msip, intSinkNodeIn[1] connect core.io.interrupts.mtip, intSinkNodeIn[2] connect core.io.interrupts.meip, intSinkNodeIn[3] connect core.io.interrupts.seip, intSinkNodeIn[4] connect traceSourceNodeOut, core.io.trace connect core.io.traceStall, traceAuxSinkNodeIn.stall connect bpwatchSourceNodeOut, core.io.bpwatch connect core.io.hartid, hartIdSinkNodeIn connect frontend.io.cpu, core.io.imem connect fpuOpt.io.keep_clock_enabled, core.io.fpu.keep_clock_enabled connect core.io.fpu.sboard_clra, fpuOpt.io.sboard_clra connect core.io.fpu.sboard_clr, fpuOpt.io.sboard_clr connect core.io.fpu.sboard_set, fpuOpt.io.sboard_set connect core.io.fpu.dec.vec, fpuOpt.io.dec.vec connect core.io.fpu.dec.wflags, fpuOpt.io.dec.wflags connect core.io.fpu.dec.sqrt, fpuOpt.io.dec.sqrt connect core.io.fpu.dec.div, fpuOpt.io.dec.div connect core.io.fpu.dec.fma, fpuOpt.io.dec.fma connect core.io.fpu.dec.fastpipe, fpuOpt.io.dec.fastpipe connect core.io.fpu.dec.toint, fpuOpt.io.dec.toint connect core.io.fpu.dec.fromint, fpuOpt.io.dec.fromint connect core.io.fpu.dec.typeTagOut, fpuOpt.io.dec.typeTagOut connect core.io.fpu.dec.typeTagIn, fpuOpt.io.dec.typeTagIn connect core.io.fpu.dec.swap23, fpuOpt.io.dec.swap23 connect core.io.fpu.dec.swap12, fpuOpt.io.dec.swap12 connect core.io.fpu.dec.ren3, fpuOpt.io.dec.ren3 connect core.io.fpu.dec.ren2, fpuOpt.io.dec.ren2 connect core.io.fpu.dec.ren1, fpuOpt.io.dec.ren1 connect core.io.fpu.dec.wen, fpuOpt.io.dec.wen connect core.io.fpu.dec.ldst, fpuOpt.io.dec.ldst connect fpuOpt.io.killm, core.io.fpu.killm connect fpuOpt.io.killx, core.io.fpu.killx connect core.io.fpu.illegal_rm, fpuOpt.io.illegal_rm connect core.io.fpu.nack_mem, fpuOpt.io.nack_mem connect core.io.fpu.fcsr_rdy, fpuOpt.io.fcsr_rdy connect fpuOpt.io.valid, core.io.fpu.valid connect fpuOpt.io.ll_resp_data, core.io.fpu.ll_resp_data connect fpuOpt.io.ll_resp_tag, core.io.fpu.ll_resp_tag connect fpuOpt.io.ll_resp_type, core.io.fpu.ll_resp_type connect fpuOpt.io.ll_resp_val, core.io.fpu.ll_resp_val connect core.io.fpu.toint_data, fpuOpt.io.toint_data connect core.io.fpu.store_data, fpuOpt.io.store_data connect fpuOpt.io.v_sew, core.io.fpu.v_sew connect core.io.fpu.fcsr_flags.bits, fpuOpt.io.fcsr_flags.bits connect core.io.fpu.fcsr_flags.valid, fpuOpt.io.fcsr_flags.valid connect fpuOpt.io.fcsr_rm, core.io.fpu.fcsr_rm connect fpuOpt.io.fromint_data, core.io.fpu.fromint_data connect fpuOpt.io.inst, core.io.fpu.inst connect fpuOpt.io.time, core.io.fpu.time connect fpuOpt.io.hartid, core.io.fpu.hartid connect core.io.ptw, ptw.io.dpath connect core.io.rocc.cmd.ready, UInt<1>(0h0) connect core.io.rocc.resp.valid, UInt<1>(0h0) invalidate core.io.rocc.resp.bits.data invalidate core.io.rocc.resp.bits.rd invalidate core.io.rocc.busy invalidate core.io.rocc.interrupt invalidate core.io.rocc.mem.clock_enabled invalidate core.io.rocc.mem.keep_clock_enabled invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterStore invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterLoad invalidate core.io.rocc.mem.perf.canAcceptLoadThenLoad invalidate core.io.rocc.mem.perf.canAcceptStoreThenRMW invalidate core.io.rocc.mem.perf.canAcceptStoreThenLoad invalidate core.io.rocc.mem.perf.blocked invalidate core.io.rocc.mem.perf.tlbMiss invalidate core.io.rocc.mem.perf.grant invalidate core.io.rocc.mem.perf.release invalidate core.io.rocc.mem.perf.acquire invalidate core.io.rocc.mem.store_pending invalidate core.io.rocc.mem.ordered invalidate core.io.rocc.mem.s2_gpa_is_pte invalidate core.io.rocc.mem.s2_gpa invalidate core.io.rocc.mem.s2_xcpt.ae.st invalidate core.io.rocc.mem.s2_xcpt.ae.ld invalidate core.io.rocc.mem.s2_xcpt.gf.st invalidate core.io.rocc.mem.s2_xcpt.gf.ld invalidate core.io.rocc.mem.s2_xcpt.pf.st invalidate core.io.rocc.mem.s2_xcpt.pf.ld invalidate core.io.rocc.mem.s2_xcpt.ma.st invalidate core.io.rocc.mem.s2_xcpt.ma.ld invalidate core.io.rocc.mem.replay_next invalidate core.io.rocc.mem.resp.bits.store_data invalidate core.io.rocc.mem.resp.bits.data_raw invalidate core.io.rocc.mem.resp.bits.data_word_bypass invalidate core.io.rocc.mem.resp.bits.has_data invalidate core.io.rocc.mem.resp.bits.replay invalidate core.io.rocc.mem.resp.bits.mask invalidate core.io.rocc.mem.resp.bits.data invalidate core.io.rocc.mem.resp.bits.dv invalidate core.io.rocc.mem.resp.bits.dprv invalidate core.io.rocc.mem.resp.bits.signed invalidate core.io.rocc.mem.resp.bits.size invalidate core.io.rocc.mem.resp.bits.cmd invalidate core.io.rocc.mem.resp.bits.tag invalidate core.io.rocc.mem.resp.bits.addr invalidate core.io.rocc.mem.resp.valid invalidate core.io.rocc.mem.s2_paddr invalidate core.io.rocc.mem.s2_uncached invalidate core.io.rocc.mem.s2_kill invalidate core.io.rocc.mem.s2_nack_cause_raw invalidate core.io.rocc.mem.s2_nack invalidate core.io.rocc.mem.s1_data.mask invalidate core.io.rocc.mem.s1_data.data invalidate core.io.rocc.mem.s1_kill invalidate core.io.rocc.mem.req.bits.mask invalidate core.io.rocc.mem.req.bits.data invalidate core.io.rocc.mem.req.bits.no_xcpt invalidate core.io.rocc.mem.req.bits.no_alloc invalidate core.io.rocc.mem.req.bits.no_resp invalidate core.io.rocc.mem.req.bits.phys invalidate core.io.rocc.mem.req.bits.dv invalidate core.io.rocc.mem.req.bits.dprv invalidate core.io.rocc.mem.req.bits.signed invalidate core.io.rocc.mem.req.bits.size invalidate core.io.rocc.mem.req.bits.cmd invalidate core.io.rocc.mem.req.bits.tag invalidate core.io.rocc.mem.req.bits.addr invalidate core.io.rocc.mem.req.valid invalidate core.io.rocc.mem.req.ready connect dcacheArb.io.requestor[0], ptw.io.mem connect dcacheArb.io.requestor[1], core.io.dmem connect ptw.io.requestor[0], dcache.io.ptw connect ptw.io.requestor[1], frontend.io.ptw
module RocketTile( // @[RocketTile.scala:141:7] input clock, // @[RocketTile.scala:141:7] input reset, // @[RocketTile.scala:141:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_wfi_out_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25] output [31:0] auto_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25] output [2:0] auto_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25] input auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] broadcast_2_auto_in_0_action; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_valid_0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9] wire _core_io_imem_might_request; // @[RocketTile.scala:147:20] wire _core_io_imem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_imem_req_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_req_bits_speculative; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_imem_resp_ready; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_valid; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_taken; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_mask; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bridx; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_prediction_target; // @[RocketTile.scala:147:20] wire [4:0] _core_io_imem_btb_update_bits_prediction_entry; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_btb_update_bits_prediction_bht_history; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bht_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_pc; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_target; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_isValid; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_br_pc; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_valid; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_bht_update_bits_prediction_history; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_prediction_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_bht_update_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_branch; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_taken; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_mispredict; // @[RocketTile.scala:147:20] wire _core_io_imem_flush_icache; // @[RocketTile.scala:147:20] wire _core_io_imem_progress; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_dmem_req_bits_addr; // @[RocketTile.scala:147:20] wire [6:0] _core_io_dmem_req_bits_tag; // @[RocketTile.scala:147:20] wire [4:0] _core_io_dmem_req_bits_cmd; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_size; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_signed; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_dprv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_dv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_no_resp; // @[RocketTile.scala:147:20] wire _core_io_dmem_s1_kill; // @[RocketTile.scala:147:20] wire [63:0] _core_io_dmem_s1_data_data; // @[RocketTile.scala:147:20] wire _core_io_dmem_keep_clock_enabled; // @[RocketTile.scala:147:20] wire [3:0] _core_io_ptw_ptbr_mode; // @[RocketTile.scala:147:20] wire [43:0] _core_io_ptw_ptbr_ppn; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_ptw_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_status_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_v; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sd; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_mpp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spvp; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spv; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_gstatus_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_v; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sd; // @[RocketTile.scala:147:20] wire [22:0] _core_io_ptw_gstatus_zero2; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mbe; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sbe; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_sxl; // @[RocketTile.scala:147:20] wire [7:0] _core_io_ptw_gstatus_zero1; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_mpp; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_vs; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_ube; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_upie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_hie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_uie; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_0_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_0_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_1_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_1_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_2_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_2_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_3_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_3_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_4_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_4_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_5_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_5_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_6_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_6_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_7_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_7_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_value; // @[RocketTile.scala:147:20] wire _core_io_fpu_hartid; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_time; // @[RocketTile.scala:147:20] wire [31:0] _core_io_fpu_inst; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_fromint_data; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_fcsr_rm; // @[RocketTile.scala:147:20] wire _core_io_fpu_ll_resp_val; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_ll_resp_type; // @[RocketTile.scala:147:20] wire [4:0] _core_io_fpu_ll_resp_tag; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_ll_resp_data; // @[RocketTile.scala:147:20] wire _core_io_fpu_valid; // @[RocketTile.scala:147:20] wire _core_io_fpu_killx; // @[RocketTile.scala:147:20] wire _core_io_fpu_killm; // @[RocketTile.scala:147:20] wire _core_io_fpu_keep_clock_enabled; // @[RocketTile.scala:147:20] wire _core_io_wfi; // @[RocketTile.scala:147:20] wire _ptw_io_requestor_0_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sd; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sd; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_0_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_0_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sd; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sd; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_1_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_1_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_mem_req_valid; // @[PTW.scala:802:19] wire [39:0] _ptw_io_mem_req_bits_addr; // @[PTW.scala:802:19] wire _ptw_io_mem_req_bits_dv; // @[PTW.scala:802:19] wire _ptw_io_mem_s1_kill; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_miss; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_hit; // @[PTW.scala:802:19] wire _ptw_io_dpath_clock_enabled; // @[PTW.scala:802:19] wire _dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_0_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_0_resp_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_requestor_0_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_0_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_0_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_1_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_1_resp_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_1_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_dv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_phys; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_no_resp; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_s1_kill; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_keep_clock_enabled; // @[HellaCache.scala:292:25] wire _fpuOpt_io_fcsr_flags_valid; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_fcsr_flags_bits; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_store_data; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_toint_data; // @[RocketTile.scala:242:62] wire _fpuOpt_io_fcsr_rdy; // @[RocketTile.scala:242:62] wire _fpuOpt_io_nack_mem; // @[RocketTile.scala:242:62] wire _fpuOpt_io_illegal_rm; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ldst; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wen; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren1; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren2; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren3; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap12; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap23; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagIn; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagOut; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fromint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_toint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fastpipe; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fma; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_div; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_sqrt; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wflags; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_vec; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_set; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_clr; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_sboard_clra; // @[RocketTile.scala:242:62] wire _frontend_io_cpu_resp_valid; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_cfiType; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_taken; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bridx; // @[Frontend.scala:393:28] wire [38:0] _frontend_io_cpu_resp_bits_btb_target; // @[Frontend.scala:393:28] wire [4:0] _frontend_io_cpu_resp_bits_btb_entry; // @[Frontend.scala:393:28] wire [7:0] _frontend_io_cpu_resp_bits_btb_bht_history; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bht_value; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_resp_bits_pc; // @[Frontend.scala:393:28] wire [31:0] _frontend_io_cpu_resp_bits_data; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_pf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_gf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_replay; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_valid; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_gpa_bits; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_is_pte; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_npc; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_acquire; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_tlbMiss; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_valid; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_valid; // @[Frontend.scala:393:28] wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[Frontend.scala:393:28] wire _dcache_io_cpu_req_ready; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack; // @[HellaCache.scala:278:43] wire [31:0] _dcache_io_cpu_s2_paddr; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_valid; // @[HellaCache.scala:278:43] wire [39:0] _dcache_io_cpu_resp_bits_addr; // @[HellaCache.scala:278:43] wire [6:0] _dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala:278:43] wire [4:0] _dcache_io_cpu_resp_bits_cmd; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_size; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_signed; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_dprv; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_dv; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data; // @[HellaCache.scala:278:43] wire [7:0] _dcache_io_cpu_resp_bits_mask; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_store_data; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_replay_next; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_ordered; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_store_pending; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_acquire; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_release; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_tlbMiss; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_valid; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_bits_valid; // @[HellaCache.scala:278:43] wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[HellaCache.scala:278:43] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[RocketTile.scala:141:7] wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[RocketTile.scala:141:7] wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[RocketTile.scala:141:7] wire auto_hartid_in_0 = auto_hartid_in; // @[RocketTile.scala:141:7] wire auto_buffer_out_a_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_cease_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_halt_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[RocketTile.scala:141:7] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire broadcast_2_auto_in_0_rvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_wvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_ivalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_2_nodeIn_0_rvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_wvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_ivalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire buffer_auto_in_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17] wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17] wire bpwatchSourceNodeOut_0_rvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_wvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_ivalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_in_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_out_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonOut_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonIn_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonIn_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [31:0] auto_reset_vector_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorIn = 32'h10000; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire buffer_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_b_valid = auto_buffer_out_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_b_bits_opcode = auto_buffer_out_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_b_bits_param = auto_buffer_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_b_bits_size = auto_buffer_out_b_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_b_bits_source = auto_buffer_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_b_bits_address = auto_buffer_out_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_b_bits_mask = auto_buffer_out_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_b_bits_data = auto_buffer_out_b_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_b_bits_corrupt = auto_buffer_out_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_ready = auto_buffer_out_c_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_ready = auto_buffer_out_e_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] wire wfiNodeOut_0; // @[MixedNode.scala:542:17] wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[RocketTile.scala:141:7] wire int_localIn_0 = auto_int_local_in_0_0_0; // @[RocketTile.scala:141:7] wire traceSourceNodeOut_insns_0_valid; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_0_insn; // @[MixedNode.scala:542:17] wire [2:0] traceSourceNodeOut_insns_0_priv; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_exception; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_insns_0_cause; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_tval; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17] wire hartidIn = auto_hartid_in_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_a_bits_size_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_c_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_c_bits_size_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_c_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_c_bits_address_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_c_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_e_bits_sink_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_e_valid_0; // @[RocketTile.scala:141:7] wire auto_wfi_out_0_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] wire [2:0] auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] wire hartidOut; // @[MixedNode.scala:542:17] wire broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17] wire broadcast_nodeOut; // @[MixedNode.scala:542:17] wire broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9] wire hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17] assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] wire broadcast_2_nodeIn_0_valid_0 = broadcast_2_auto_in_0_valid_0; // @[MixedNode.scala:551:17] wire [2:0] bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire [2:0] broadcast_2_nodeIn_0_action = broadcast_2_auto_in_0_action; // @[MixedNode.scala:551:17] wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9] assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_b_ready = buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_b_valid = buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_b_bits_opcode = buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_b_bits_param = buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_b_bits_size = buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_b_bits_source = buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] tlOtherMastersNodeOut_b_bits_address = buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] tlOtherMastersNodeOut_b_bits_mask = buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] tlOtherMastersNodeOut_b_bits_data = buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_c_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_b_bits_corrupt = buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_c_ready = buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_c_valid = buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_opcode = buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_param = buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_c_bits_size = buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_source = buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_c_bits_address = buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_c_bits_data = buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_param = buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] tlOtherMastersNodeOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_e_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_e_ready = buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_e_valid = buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_e_bits_sink = buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_valid_0 = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_opcode_0 = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_param_0 = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_size_0 = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_source_0 = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_address_0 = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_mask_0 = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_data_0 = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_b_ready_0 = buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_valid = buffer_auto_out_b_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_b_bits_opcode = buffer_auto_out_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_b_bits_param = buffer_auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_b_bits_size = buffer_auto_out_b_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_b_bits_source = buffer_auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_b_bits_address = buffer_auto_out_b_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_b_bits_mask = buffer_auto_out_b_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_b_bits_data = buffer_auto_out_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_bits_corrupt = buffer_auto_out_b_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_ready = buffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_valid_0 = buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_opcode_0 = buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_param_0 = buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_size_0 = buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_source_0 = buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_address_0 = buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_data_0 = buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_d_ready_0 = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_denied = buffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_ready = buffer_auto_out_e_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_valid_0 = buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_bits_sink_0 = buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_b_ready = buffer_nodeOut_b_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_b_valid = buffer_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_opcode = buffer_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_param = buffer_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_size = buffer_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_source = buffer_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_address = buffer_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_mask = buffer_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_data = buffer_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_corrupt = buffer_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_c_ready = buffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_c_valid = buffer_nodeOut_c_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_opcode = buffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_param = buffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_size = buffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_source = buffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_address = buffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_data = buffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_e_ready = buffer_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_e_valid = buffer_nodeOut_e_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_e_bits_sink = buffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_b_ready = buffer_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_b_valid = buffer_nodeIn_b_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_opcode = buffer_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_param = buffer_nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_size = buffer_nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_source = buffer_nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_address = buffer_nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_mask = buffer_nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_data = buffer_nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_corrupt = buffer_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_c_ready = buffer_nodeIn_c_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_c_valid = buffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_opcode = buffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_param = buffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_size = buffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_source = buffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_address = buffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_data = buffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_e_ready = buffer_nodeIn_e_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_e_valid = buffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_e_bits_sink = buffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_valid = tlOtherMastersNodeOut_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_b_ready = tlOtherMastersNodeOut_b_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_b_valid = tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_b_bits_opcode = tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_b_bits_param = tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_b_bits_size = tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_b_bits_source = tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlOtherMastersNodeIn_b_bits_address = tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] tlOtherMastersNodeIn_b_bits_mask = tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlOtherMastersNodeIn_b_bits_data = tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_b_bits_corrupt = tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_ready = tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_valid = tlOtherMastersNodeOut_c_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_opcode = tlOtherMastersNodeOut_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_param = tlOtherMastersNodeOut_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_size = tlOtherMastersNodeOut_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_source = tlOtherMastersNodeOut_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_address = tlOtherMastersNodeOut_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_data = tlOtherMastersNodeOut_c_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_d_ready = tlOtherMastersNodeOut_d_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_e_ready = tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_valid = tlOtherMastersNodeOut_e_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_bits_sink = tlOtherMastersNodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_ready = tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_valid = tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_opcode = tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_param = tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_size = tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_source = tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_address = tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_data = tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_valid = tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_bits_sink = tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17] assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17] assign auto_trace_source_out_insns_0_valid_0 = traceSourceNodeOut_insns_0_valid; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr_0 = traceSourceNodeOut_insns_0_iaddr; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn_0 = traceSourceNodeOut_insns_0_insn; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv_0 = traceSourceNodeOut_insns_0_priv; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception_0 = traceSourceNodeOut_insns_0_exception; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt_0 = traceSourceNodeOut_insns_0_interrupt; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause_0 = traceSourceNodeOut_insns_0_cause; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval_0 = traceSourceNodeOut_insns_0_tval; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[RocketTile.scala:141:7] assign broadcast_2_auto_in_0_valid_0 = bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] assign broadcast_2_auto_in_0_action = bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1; // @[MixedNode.scala:542:17] wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17] assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17] wire intSinkNodeIn_0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_1; // @[MixedNode.scala:551:17] wire intSinkNodeIn_2; // @[MixedNode.scala:551:17] wire intSinkNodeIn_3; // @[MixedNode.scala:551:17] wire intSinkNodeIn_4; // @[MixedNode.scala:551:17] assign auto_wfi_out_0_0 = wfiNodeOut_0; // @[RocketTile.scala:141:7] reg wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] assign wfiNodeOut_0 = wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] always @(posedge clock) begin // @[RocketTile.scala:141:7] if (reset) // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= 1'h0; // @[Interrupts.scala:131:36] else // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= _core_io_wfi; // @[RocketTile.scala:147:20] always @(posedge) TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s3k3z4c tlMasterXbar ( // @[HierarchicalElement.scala:55:42] .clock (clock), .reset (reset), .auto_anon_in_1_a_ready (widget_1_auto_anon_out_a_ready), .auto_anon_in_1_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_1_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_1_d_valid (widget_1_auto_anon_out_d_valid), .auto_anon_in_1_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode), .auto_anon_in_1_d_bits_param (widget_1_auto_anon_out_d_bits_param), .auto_anon_in_1_d_bits_size (widget_1_auto_anon_out_d_bits_size), .auto_anon_in_1_d_bits_sink (widget_1_auto_anon_out_d_bits_sink), .auto_anon_in_1_d_bits_denied (widget_1_auto_anon_out_d_bits_denied), .auto_anon_in_1_d_bits_data (widget_1_auto_anon_out_d_bits_data), .auto_anon_in_1_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_a_ready (widget_auto_anon_out_a_ready), .auto_anon_in_0_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_ready (widget_auto_anon_out_b_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_valid (widget_auto_anon_out_b_valid), .auto_anon_in_0_b_bits_opcode (widget_auto_anon_out_b_bits_opcode), .auto_anon_in_0_b_bits_param (widget_auto_anon_out_b_bits_param), .auto_anon_in_0_b_bits_size (widget_auto_anon_out_b_bits_size), .auto_anon_in_0_b_bits_source (widget_auto_anon_out_b_bits_source), .auto_anon_in_0_b_bits_address (widget_auto_anon_out_b_bits_address), .auto_anon_in_0_b_bits_mask (widget_auto_anon_out_b_bits_mask), .auto_anon_in_0_b_bits_data (widget_auto_anon_out_b_bits_data), .auto_anon_in_0_b_bits_corrupt (widget_auto_anon_out_b_bits_corrupt), .auto_anon_in_0_c_ready (widget_auto_anon_out_c_ready), .auto_anon_in_0_c_valid (widget_auto_anon_out_c_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_opcode (widget_auto_anon_out_c_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_param (widget_auto_anon_out_c_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_size (widget_auto_anon_out_c_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_source (widget_auto_anon_out_c_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_address (widget_auto_anon_out_c_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_data (widget_auto_anon_out_c_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_valid (widget_auto_anon_out_d_valid), .auto_anon_in_0_d_bits_opcode (widget_auto_anon_out_d_bits_opcode), .auto_anon_in_0_d_bits_param (widget_auto_anon_out_d_bits_param), .auto_anon_in_0_d_bits_size (widget_auto_anon_out_d_bits_size), .auto_anon_in_0_d_bits_source (widget_auto_anon_out_d_bits_source), .auto_anon_in_0_d_bits_sink (widget_auto_anon_out_d_bits_sink), .auto_anon_in_0_d_bits_denied (widget_auto_anon_out_d_bits_denied), .auto_anon_in_0_d_bits_data (widget_auto_anon_out_d_bits_data), .auto_anon_in_0_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_e_ready (widget_auto_anon_out_e_ready), .auto_anon_in_0_e_valid (widget_auto_anon_out_e_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_e_bits_sink (widget_auto_anon_out_e_bits_sink), // @[WidthWidget.scala:27:9] .auto_anon_out_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_anon_out_a_valid (tlOtherMastersNodeIn_a_valid), .auto_anon_out_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode), .auto_anon_out_a_bits_param (tlOtherMastersNodeIn_a_bits_param), .auto_anon_out_a_bits_size (tlOtherMastersNodeIn_a_bits_size), .auto_anon_out_a_bits_source (tlOtherMastersNodeIn_a_bits_source), .auto_anon_out_a_bits_address (tlOtherMastersNodeIn_a_bits_address), .auto_anon_out_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask), .auto_anon_out_a_bits_data (tlOtherMastersNodeIn_a_bits_data), .auto_anon_out_b_ready (tlOtherMastersNodeIn_b_ready), .auto_anon_out_b_valid (tlOtherMastersNodeIn_b_valid), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_opcode (tlOtherMastersNodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_param (tlOtherMastersNodeIn_b_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_size (tlOtherMastersNodeIn_b_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_source (tlOtherMastersNodeIn_b_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_address (tlOtherMastersNodeIn_b_bits_address), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_mask (tlOtherMastersNodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_data (tlOtherMastersNodeIn_b_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_corrupt (tlOtherMastersNodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_c_ready (tlOtherMastersNodeIn_c_ready), // @[MixedNode.scala:551:17] .auto_anon_out_c_valid (tlOtherMastersNodeIn_c_valid), .auto_anon_out_c_bits_opcode (tlOtherMastersNodeIn_c_bits_opcode), .auto_anon_out_c_bits_param (tlOtherMastersNodeIn_c_bits_param), .auto_anon_out_c_bits_size (tlOtherMastersNodeIn_c_bits_size), .auto_anon_out_c_bits_source (tlOtherMastersNodeIn_c_bits_source), .auto_anon_out_c_bits_address (tlOtherMastersNodeIn_c_bits_address), .auto_anon_out_c_bits_data (tlOtherMastersNodeIn_c_bits_data), .auto_anon_out_d_ready (tlOtherMastersNodeIn_d_ready), .auto_anon_out_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_e_ready (tlOtherMastersNodeIn_e_ready), // @[MixedNode.scala:551:17] .auto_anon_out_e_valid (tlOtherMastersNodeIn_e_valid), .auto_anon_out_e_bits_sink (tlOtherMastersNodeIn_e_bits_sink) ); // @[HierarchicalElement.scala:55:42] TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u tlSlaveXbar ( // @[HierarchicalElement.scala:56:41] .clock (clock), .reset (reset) ); // @[HierarchicalElement.scala:56:41] IntXbar_i4_o1 intXbar ( // @[HierarchicalElement.scala:57:37] .auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17] .auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17] .auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_out_0 (intSinkNodeIn_0), .auto_anon_out_1 (intSinkNodeIn_1), .auto_anon_out_2 (intSinkNodeIn_2), .auto_anon_out_3 (intSinkNodeIn_3), .auto_anon_out_4 (intSinkNodeIn_4) ); // @[HierarchicalElement.scala:57:37] HellaCachePrefetchWrapper dcache ( // @[HellaCache.scala:278:43] .clock (clock), .reset (reset), .auto_cache_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_cache_out_a_valid (widget_auto_anon_in_a_valid), .auto_cache_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode), .auto_cache_out_a_bits_param (widget_auto_anon_in_a_bits_param), .auto_cache_out_a_bits_size (widget_auto_anon_in_a_bits_size), .auto_cache_out_a_bits_source (widget_auto_anon_in_a_bits_source), .auto_cache_out_a_bits_address (widget_auto_anon_in_a_bits_address), .auto_cache_out_a_bits_mask (widget_auto_anon_in_a_bits_mask), .auto_cache_out_a_bits_data (widget_auto_anon_in_a_bits_data), .auto_cache_out_b_ready (widget_auto_anon_in_b_ready), .auto_cache_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9] .auto_cache_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9] .auto_cache_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9] .auto_cache_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9] .auto_cache_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9] .auto_cache_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9] .auto_cache_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9] .auto_cache_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9] .auto_cache_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_cache_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9] .auto_cache_out_c_valid (widget_auto_anon_in_c_valid), .auto_cache_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode), .auto_cache_out_c_bits_param (widget_auto_anon_in_c_bits_param), .auto_cache_out_c_bits_size (widget_auto_anon_in_c_bits_size), .auto_cache_out_c_bits_source (widget_auto_anon_in_c_bits_source), .auto_cache_out_c_bits_address (widget_auto_anon_in_c_bits_address), .auto_cache_out_c_bits_data (widget_auto_anon_in_c_bits_data), .auto_cache_out_d_ready (widget_auto_anon_in_d_ready), .auto_cache_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_cache_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_cache_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_cache_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_cache_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9] .auto_cache_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_cache_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_cache_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_cache_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_cache_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9] .auto_cache_out_e_valid (widget_auto_anon_in_e_valid), .auto_cache_out_e_bits_sink (widget_auto_anon_in_e_bits_sink), .io_cpu_req_ready (_dcache_io_cpu_req_ready), .io_cpu_req_valid (_dcacheArb_io_mem_req_valid), // @[HellaCache.scala:292:25] .io_cpu_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), // @[HellaCache.scala:292:25] .io_cpu_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), // @[HellaCache.scala:292:25] .io_cpu_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), // @[HellaCache.scala:292:25] .io_cpu_req_bits_size (_dcacheArb_io_mem_req_bits_size), // @[HellaCache.scala:292:25] .io_cpu_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), // @[HellaCache.scala:292:25] .io_cpu_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), // @[HellaCache.scala:292:25] .io_cpu_s1_kill (_dcacheArb_io_mem_s1_kill), // @[HellaCache.scala:292:25] .io_cpu_s1_data_data (_dcacheArb_io_mem_s1_data_data), // @[HellaCache.scala:292:25] .io_cpu_s1_data_mask (8'h0), // @[RocketTile.scala:147:20] .io_cpu_s2_nack (_dcache_io_cpu_s2_nack), .io_cpu_s2_paddr (_dcache_io_cpu_s2_paddr), .io_cpu_resp_valid (_dcache_io_cpu_resp_valid), .io_cpu_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), .io_cpu_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), .io_cpu_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), .io_cpu_resp_bits_size (_dcache_io_cpu_resp_bits_size), .io_cpu_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), .io_cpu_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), .io_cpu_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), .io_cpu_resp_bits_data (_dcache_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), .io_cpu_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), .io_cpu_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), .io_cpu_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), .io_cpu_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), .io_cpu_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), .io_cpu_replay_next (_dcache_io_cpu_replay_next), .io_cpu_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), .io_cpu_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), .io_cpu_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), .io_cpu_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), .io_cpu_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), .io_cpu_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), .io_cpu_ordered (_dcache_io_cpu_ordered), .io_cpu_store_pending (_dcache_io_cpu_store_pending), .io_cpu_perf_acquire (_dcache_io_cpu_perf_acquire), .io_cpu_perf_release (_dcache_io_cpu_perf_release), .io_cpu_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), .io_cpu_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled), // @[HellaCache.scala:292:25] .io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_dcache_io_ptw_req_valid), .io_ptw_req_bits_valid (_dcache_io_ptw_req_bits_valid), .io_ptw_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_0_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[PTW.scala:802:19] .io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_0_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_sd (_ptw_io_requestor_0_gstatus_sd), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[HellaCache.scala:278:43] Frontend frontend ( // @[Frontend.scala:393:28] .clock (clock), .reset (reset), .auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid), .auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address), .auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .io_cpu_might_request (_core_io_imem_might_request), // @[RocketTile.scala:147:20] .io_cpu_req_valid (_core_io_imem_req_valid), // @[RocketTile.scala:147:20] .io_cpu_req_bits_pc (_core_io_imem_req_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_req_bits_speculative (_core_io_imem_req_bits_speculative), // @[RocketTile.scala:147:20] .io_cpu_sfence_valid (_core_io_imem_sfence_valid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_addr (_core_io_imem_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_asid (_core_io_imem_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hv (_core_io_imem_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hg (_core_io_imem_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_cpu_resp_ready (_core_io_imem_resp_ready), // @[RocketTile.scala:147:20] .io_cpu_resp_valid (_frontend_io_cpu_resp_valid), .io_cpu_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), .io_cpu_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), .io_cpu_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), .io_cpu_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), .io_cpu_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), .io_cpu_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), .io_cpu_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), .io_cpu_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), .io_cpu_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), .io_cpu_resp_bits_data (_frontend_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), .io_cpu_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), .io_cpu_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), .io_cpu_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), .io_cpu_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), .io_cpu_gpa_valid (_frontend_io_cpu_gpa_valid), .io_cpu_gpa_bits (_frontend_io_cpu_gpa_bits), .io_cpu_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), .io_cpu_btb_update_valid (_core_io_imem_btb_update_valid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_target (_core_io_imem_btb_update_bits_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), // @[RocketTile.scala:147:20] .io_cpu_bht_update_valid (_core_io_imem_bht_update_valid), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), // @[RocketTile.scala:147:20] .io_cpu_flush_icache (_core_io_imem_flush_icache), // @[RocketTile.scala:147:20] .io_cpu_npc (_frontend_io_cpu_npc), .io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire), .io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), .io_cpu_progress (_core_io_imem_progress), // @[RocketTile.scala:147:20] .io_ptw_req_ready (_ptw_io_requestor_1_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_frontend_io_ptw_req_valid), .io_ptw_req_bits_valid (_frontend_io_ptw_req_bits_valid), .io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_1_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_1_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_1_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_1_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_1_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_1_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_1_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_1_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_1_status_v), // @[PTW.scala:802:19] .io_ptw_status_sd (_ptw_io_requestor_1_status_sd), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_1_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_1_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_1_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_1_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_1_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_1_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_1_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_1_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_1_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_1_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_1_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_1_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_1_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_1_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_1_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_1_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_sd (_ptw_io_requestor_1_gstatus_sd), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[Frontend.scala:393:28] TLFragmenter fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset) ); // @[Fragmenter.scala:345:34] FPU fpuOpt ( // @[RocketTile.scala:242:62] .clock (clock), .reset (reset), .io_hartid (_core_io_fpu_hartid), // @[RocketTile.scala:147:20] .io_time (_core_io_fpu_time), // @[RocketTile.scala:147:20] .io_inst (_core_io_fpu_inst), // @[RocketTile.scala:147:20] .io_fromint_data (_core_io_fpu_fromint_data), // @[RocketTile.scala:147:20] .io_fcsr_rm (_core_io_fpu_fcsr_rm), // @[RocketTile.scala:147:20] .io_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), .io_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), .io_store_data (_fpuOpt_io_store_data), .io_toint_data (_fpuOpt_io_toint_data), .io_ll_resp_val (_core_io_fpu_ll_resp_val), // @[RocketTile.scala:147:20] .io_ll_resp_type (_core_io_fpu_ll_resp_type), // @[RocketTile.scala:147:20] .io_ll_resp_tag (_core_io_fpu_ll_resp_tag), // @[RocketTile.scala:147:20] .io_ll_resp_data (_core_io_fpu_ll_resp_data), // @[RocketTile.scala:147:20] .io_valid (_core_io_fpu_valid), // @[RocketTile.scala:147:20] .io_fcsr_rdy (_fpuOpt_io_fcsr_rdy), .io_nack_mem (_fpuOpt_io_nack_mem), .io_illegal_rm (_fpuOpt_io_illegal_rm), .io_killx (_core_io_fpu_killx), // @[RocketTile.scala:147:20] .io_killm (_core_io_fpu_killm), // @[RocketTile.scala:147:20] .io_dec_ldst (_fpuOpt_io_dec_ldst), .io_dec_wen (_fpuOpt_io_dec_wen), .io_dec_ren1 (_fpuOpt_io_dec_ren1), .io_dec_ren2 (_fpuOpt_io_dec_ren2), .io_dec_ren3 (_fpuOpt_io_dec_ren3), .io_dec_swap12 (_fpuOpt_io_dec_swap12), .io_dec_swap23 (_fpuOpt_io_dec_swap23), .io_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), .io_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), .io_dec_fromint (_fpuOpt_io_dec_fromint), .io_dec_toint (_fpuOpt_io_dec_toint), .io_dec_fastpipe (_fpuOpt_io_dec_fastpipe), .io_dec_fma (_fpuOpt_io_dec_fma), .io_dec_div (_fpuOpt_io_dec_div), .io_dec_sqrt (_fpuOpt_io_dec_sqrt), .io_dec_wflags (_fpuOpt_io_dec_wflags), .io_dec_vec (_fpuOpt_io_dec_vec), .io_sboard_set (_fpuOpt_io_sboard_set), .io_sboard_clr (_fpuOpt_io_sboard_clr), .io_sboard_clra (_fpuOpt_io_sboard_clra), .io_keep_clock_enabled (_core_io_fpu_keep_clock_enabled) // @[RocketTile.scala:147:20] ); // @[RocketTile.scala:242:62] HellaCacheArbiter dcacheArb ( // @[HellaCache.scala:292:25] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_dcacheArb_io_requestor_0_req_ready), .io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[PTW.scala:802:19] .io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[PTW.scala:802:19] .io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[PTW.scala:802:19] .io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[PTW.scala:802:19] .io_requestor_0_s2_nack (_dcacheArb_io_requestor_0_s2_nack), .io_requestor_0_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), .io_requestor_0_resp_valid (_dcacheArb_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), .io_requestor_0_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), .io_requestor_0_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), .io_requestor_0_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), .io_requestor_0_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), .io_requestor_0_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), .io_requestor_0_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), .io_requestor_0_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), .io_requestor_0_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), .io_requestor_0_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), .io_requestor_0_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), .io_requestor_0_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), .io_requestor_0_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), .io_requestor_0_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), .io_requestor_0_replay_next (_dcacheArb_io_requestor_0_replay_next), .io_requestor_0_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), .io_requestor_0_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), .io_requestor_0_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), .io_requestor_0_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), .io_requestor_0_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), .io_requestor_0_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), .io_requestor_0_ordered (_dcacheArb_io_requestor_0_ordered), .io_requestor_0_store_pending (_dcacheArb_io_requestor_0_store_pending), .io_requestor_0_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), .io_requestor_0_perf_release (_dcacheArb_io_requestor_0_perf_release), .io_requestor_0_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), .io_requestor_1_req_ready (_dcacheArb_io_requestor_1_req_ready), .io_requestor_1_req_valid (_core_io_dmem_req_valid), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_addr (_core_io_dmem_req_bits_addr), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_tag (_core_io_dmem_req_bits_tag), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_cmd (_core_io_dmem_req_bits_cmd), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_size (_core_io_dmem_req_bits_size), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_signed (_core_io_dmem_req_bits_signed), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_dprv (_core_io_dmem_req_bits_dprv), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_dv (_core_io_dmem_req_bits_dv), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), // @[RocketTile.scala:147:20] .io_requestor_1_s1_kill (_core_io_dmem_s1_kill), // @[RocketTile.scala:147:20] .io_requestor_1_s1_data_data (_core_io_dmem_s1_data_data), // @[RocketTile.scala:147:20] .io_requestor_1_s2_nack (_dcacheArb_io_requestor_1_s2_nack), .io_requestor_1_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), .io_requestor_1_resp_valid (_dcacheArb_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), .io_requestor_1_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), .io_requestor_1_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), .io_requestor_1_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), .io_requestor_1_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), .io_requestor_1_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), .io_requestor_1_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), .io_requestor_1_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), .io_requestor_1_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), .io_requestor_1_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), .io_requestor_1_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), .io_requestor_1_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), .io_requestor_1_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), .io_requestor_1_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), .io_requestor_1_replay_next (_dcacheArb_io_requestor_1_replay_next), .io_requestor_1_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), .io_requestor_1_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), .io_requestor_1_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), .io_requestor_1_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), .io_requestor_1_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), .io_requestor_1_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), .io_requestor_1_ordered (_dcacheArb_io_requestor_1_ordered), .io_requestor_1_store_pending (_dcacheArb_io_requestor_1_store_pending), .io_requestor_1_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), .io_requestor_1_perf_release (_dcacheArb_io_requestor_1_perf_release), .io_requestor_1_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), .io_requestor_1_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), // @[RocketTile.scala:147:20] .io_mem_req_ready (_dcache_io_cpu_req_ready), // @[HellaCache.scala:278:43] .io_mem_req_valid (_dcacheArb_io_mem_req_valid), .io_mem_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), .io_mem_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), .io_mem_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), .io_mem_req_bits_size (_dcacheArb_io_mem_req_bits_size), .io_mem_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), .io_mem_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), .io_mem_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), .io_mem_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), .io_mem_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), .io_mem_s1_kill (_dcacheArb_io_mem_s1_kill), .io_mem_s1_data_data (_dcacheArb_io_mem_s1_data_data), .io_mem_s2_nack (_dcache_io_cpu_s2_nack), // @[HellaCache.scala:278:43] .io_mem_s2_paddr (_dcache_io_cpu_s2_paddr), // @[HellaCache.scala:278:43] .io_mem_resp_valid (_dcache_io_cpu_resp_valid), // @[HellaCache.scala:278:43] .io_mem_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), // @[HellaCache.scala:278:43] .io_mem_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), // @[HellaCache.scala:278:43] .io_mem_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), // @[HellaCache.scala:278:43] .io_mem_resp_bits_size (_dcache_io_cpu_resp_bits_size), // @[HellaCache.scala:278:43] .io_mem_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data (_dcache_io_cpu_resp_bits_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), // @[HellaCache.scala:278:43] .io_mem_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), // @[HellaCache.scala:278:43] .io_mem_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), // @[HellaCache.scala:278:43] .io_mem_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), // @[HellaCache.scala:278:43] .io_mem_replay_next (_dcache_io_cpu_replay_next), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), // @[HellaCache.scala:278:43] .io_mem_ordered (_dcache_io_cpu_ordered), // @[HellaCache.scala:278:43] .io_mem_store_pending (_dcache_io_cpu_store_pending), // @[HellaCache.scala:278:43] .io_mem_perf_acquire (_dcache_io_cpu_perf_acquire), // @[HellaCache.scala:278:43] .io_mem_perf_release (_dcache_io_cpu_perf_release), // @[HellaCache.scala:278:43] .io_mem_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), // @[HellaCache.scala:278:43] .io_mem_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled) ); // @[HellaCache.scala:292:25] PTW ptw ( // @[PTW.scala:802:19] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready), .io_requestor_0_req_valid (_dcache_io_ptw_req_valid), // @[HellaCache.scala:278:43] .io_requestor_0_req_bits_valid (_dcache_io_ptw_req_bits_valid), // @[HellaCache.scala:278:43] .io_requestor_0_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), // @[HellaCache.scala:278:43] .io_requestor_0_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), // @[HellaCache.scala:278:43] .io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), .io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), .io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), .io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), .io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), .io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), .io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), .io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), .io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), .io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), .io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), .io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), .io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), .io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), .io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), .io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), .io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), .io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), .io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), .io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), .io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), .io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), .io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), .io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), .io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), .io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug), .io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease), .io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi), .io_requestor_0_status_isa (_ptw_io_requestor_0_status_isa), .io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv), .io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv), .io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv), .io_requestor_0_status_v (_ptw_io_requestor_0_status_v), .io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd), .io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv), .io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva), .io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr), .io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw), .io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm), .io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr), .io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum), .io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv), .io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs), .io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp), .io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp), .io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie), .io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie), .io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie), .io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie), .io_requestor_0_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), .io_requestor_0_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), .io_requestor_0_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), .io_requestor_0_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), .io_requestor_0_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), .io_requestor_0_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), .io_requestor_0_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), .io_requestor_0_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), .io_requestor_0_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), .io_requestor_0_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), .io_requestor_0_gstatus_v (_ptw_io_requestor_0_gstatus_v), .io_requestor_0_gstatus_sd (_ptw_io_requestor_0_gstatus_sd), .io_requestor_0_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), .io_requestor_0_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), .io_requestor_0_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), .io_requestor_0_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), .io_requestor_0_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), .io_requestor_0_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), .io_requestor_0_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), .io_requestor_0_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), .io_requestor_0_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), .io_requestor_0_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), .io_requestor_0_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), .io_requestor_0_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), .io_requestor_0_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), .io_requestor_0_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), .io_requestor_0_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), .io_requestor_0_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), .io_requestor_0_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), .io_requestor_0_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), .io_requestor_0_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), .io_requestor_0_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), .io_requestor_0_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), .io_requestor_0_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), .io_requestor_0_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), .io_requestor_0_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), .io_requestor_0_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), .io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), .io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), .io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), .io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), .io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), .io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), .io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), .io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), .io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), .io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), .io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), .io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), .io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), .io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), .io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), .io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), .io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), .io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), .io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), .io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), .io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), .io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), .io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), .io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), .io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), .io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), .io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), .io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), .io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), .io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), .io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), .io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), .io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), .io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), .io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), .io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), .io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), .io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), .io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), .io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), .io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), .io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), .io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), .io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), .io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), .io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), .io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), .io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), .io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), .io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), .io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), .io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), .io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), .io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), .io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), .io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), .io_requestor_0_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), .io_requestor_0_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), .io_requestor_0_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), .io_requestor_0_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), .io_requestor_0_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), .io_requestor_0_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), .io_requestor_0_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), .io_requestor_0_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), .io_requestor_0_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), .io_requestor_0_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), .io_requestor_0_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), .io_requestor_0_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), .io_requestor_0_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), .io_requestor_0_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), .io_requestor_0_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), .io_requestor_0_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value), .io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready), .io_requestor_1_req_valid (_frontend_io_ptw_req_valid), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_valid (_frontend_io_ptw_req_bits_valid), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[Frontend.scala:393:28] .io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), .io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), .io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), .io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), .io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), .io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), .io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), .io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), .io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), .io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), .io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), .io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), .io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), .io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), .io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), .io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), .io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), .io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), .io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), .io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), .io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), .io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), .io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), .io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), .io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), .io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug), .io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease), .io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi), .io_requestor_1_status_isa (_ptw_io_requestor_1_status_isa), .io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv), .io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv), .io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv), .io_requestor_1_status_v (_ptw_io_requestor_1_status_v), .io_requestor_1_status_sd (_ptw_io_requestor_1_status_sd), .io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv), .io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva), .io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr), .io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw), .io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm), .io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr), .io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum), .io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv), .io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs), .io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp), .io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp), .io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie), .io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie), .io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie), .io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie), .io_requestor_1_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), .io_requestor_1_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), .io_requestor_1_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), .io_requestor_1_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), .io_requestor_1_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), .io_requestor_1_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), .io_requestor_1_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), .io_requestor_1_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), .io_requestor_1_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), .io_requestor_1_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), .io_requestor_1_gstatus_v (_ptw_io_requestor_1_gstatus_v), .io_requestor_1_gstatus_sd (_ptw_io_requestor_1_gstatus_sd), .io_requestor_1_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), .io_requestor_1_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), .io_requestor_1_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), .io_requestor_1_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), .io_requestor_1_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), .io_requestor_1_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), .io_requestor_1_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), .io_requestor_1_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), .io_requestor_1_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), .io_requestor_1_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), .io_requestor_1_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), .io_requestor_1_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), .io_requestor_1_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), .io_requestor_1_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), .io_requestor_1_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), .io_requestor_1_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), .io_requestor_1_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), .io_requestor_1_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), .io_requestor_1_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), .io_requestor_1_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), .io_requestor_1_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), .io_requestor_1_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), .io_requestor_1_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), .io_requestor_1_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), .io_requestor_1_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), .io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), .io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), .io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), .io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), .io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), .io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), .io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), .io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), .io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), .io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), .io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), .io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), .io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), .io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), .io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), .io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), .io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), .io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), .io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), .io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), .io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), .io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), .io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), .io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), .io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), .io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), .io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), .io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), .io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), .io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), .io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), .io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), .io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), .io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), .io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), .io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), .io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), .io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), .io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), .io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), .io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), .io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), .io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), .io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), .io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), .io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), .io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), .io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), .io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), .io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), .io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), .io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), .io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), .io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), .io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), .io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), .io_requestor_1_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), .io_requestor_1_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), .io_requestor_1_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), .io_requestor_1_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), .io_requestor_1_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), .io_requestor_1_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), .io_requestor_1_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), .io_requestor_1_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), .io_requestor_1_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), .io_requestor_1_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), .io_requestor_1_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), .io_requestor_1_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), .io_requestor_1_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), .io_requestor_1_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), .io_requestor_1_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), .io_requestor_1_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value), .io_mem_req_ready (_dcacheArb_io_requestor_0_req_ready), // @[HellaCache.scala:292:25] .io_mem_req_valid (_ptw_io_mem_req_valid), .io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr), .io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv), .io_mem_s1_kill (_ptw_io_mem_s1_kill), .io_mem_s2_nack (_dcacheArb_io_requestor_0_s2_nack), // @[HellaCache.scala:292:25] .io_mem_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), // @[HellaCache.scala:292:25] .io_mem_resp_valid (_dcacheArb_io_requestor_0_resp_valid), // @[HellaCache.scala:292:25] .io_mem_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), // @[HellaCache.scala:292:25] .io_mem_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), // @[HellaCache.scala:292:25] .io_mem_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_mem_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), // @[HellaCache.scala:292:25] .io_mem_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), // @[HellaCache.scala:292:25] .io_mem_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), // @[HellaCache.scala:292:25] .io_mem_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_mem_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_mem_replay_next (_dcacheArb_io_requestor_0_replay_next), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_mem_ordered (_dcacheArb_io_requestor_0_ordered), // @[HellaCache.scala:292:25] .io_mem_store_pending (_dcacheArb_io_requestor_0_store_pending), // @[HellaCache.scala:292:25] .io_mem_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), // @[HellaCache.scala:292:25] .io_mem_perf_release (_dcacheArb_io_requestor_0_perf_release), // @[HellaCache.scala:292:25] .io_mem_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[RocketTile.scala:147:20] .io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[RocketTile.scala:147:20] .io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_dpath_status_debug (_core_io_ptw_status_debug), // @[RocketTile.scala:147:20] .io_dpath_status_cease (_core_io_ptw_status_cease), // @[RocketTile.scala:147:20] .io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[RocketTile.scala:147:20] .io_dpath_status_isa (_core_io_ptw_status_isa), // @[RocketTile.scala:147:20] .io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[RocketTile.scala:147:20] .io_dpath_status_dv (_core_io_ptw_status_dv), // @[RocketTile.scala:147:20] .io_dpath_status_prv (_core_io_ptw_status_prv), // @[RocketTile.scala:147:20] .io_dpath_status_v (_core_io_ptw_status_v), // @[RocketTile.scala:147:20] .io_dpath_status_sd (_core_io_ptw_status_sd), // @[RocketTile.scala:147:20] .io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[RocketTile.scala:147:20] .io_dpath_status_gva (_core_io_ptw_status_gva), // @[RocketTile.scala:147:20] .io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[RocketTile.scala:147:20] .io_dpath_status_tw (_core_io_ptw_status_tw), // @[RocketTile.scala:147:20] .io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[RocketTile.scala:147:20] .io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[RocketTile.scala:147:20] .io_dpath_status_sum (_core_io_ptw_status_sum), // @[RocketTile.scala:147:20] .io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[RocketTile.scala:147:20] .io_dpath_status_fs (_core_io_ptw_status_fs), // @[RocketTile.scala:147:20] .io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[RocketTile.scala:147:20] .io_dpath_status_spp (_core_io_ptw_status_spp), // @[RocketTile.scala:147:20] .io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[RocketTile.scala:147:20] .io_dpath_status_spie (_core_io_ptw_status_spie), // @[RocketTile.scala:147:20] .io_dpath_status_mie (_core_io_ptw_status_mie), // @[RocketTile.scala:147:20] .io_dpath_status_sie (_core_io_ptw_status_sie), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spvp (_core_io_ptw_hstatus_spvp), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spv (_core_io_ptw_hstatus_spv), // @[RocketTile.scala:147:20] .io_dpath_hstatus_gva (_core_io_ptw_hstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_debug (_core_io_ptw_gstatus_debug), // @[RocketTile.scala:147:20] .io_dpath_gstatus_cease (_core_io_ptw_gstatus_cease), // @[RocketTile.scala:147:20] .io_dpath_gstatus_wfi (_core_io_ptw_gstatus_wfi), // @[RocketTile.scala:147:20] .io_dpath_gstatus_isa (_core_io_ptw_gstatus_isa), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dprv (_core_io_ptw_gstatus_dprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dv (_core_io_ptw_gstatus_dv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_prv (_core_io_ptw_gstatus_prv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_v (_core_io_ptw_gstatus_v), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sd (_core_io_ptw_gstatus_sd), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero2 (_core_io_ptw_gstatus_zero2), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpv (_core_io_ptw_gstatus_mpv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_gva (_core_io_ptw_gstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mbe (_core_io_ptw_gstatus_mbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sbe (_core_io_ptw_gstatus_sbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sxl (_core_io_ptw_gstatus_sxl), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero1 (_core_io_ptw_gstatus_zero1), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tsr (_core_io_ptw_gstatus_tsr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tw (_core_io_ptw_gstatus_tw), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tvm (_core_io_ptw_gstatus_tvm), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mxr (_core_io_ptw_gstatus_mxr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sum (_core_io_ptw_gstatus_sum), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mprv (_core_io_ptw_gstatus_mprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_fs (_core_io_ptw_gstatus_fs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpp (_core_io_ptw_gstatus_mpp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_vs (_core_io_ptw_gstatus_vs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spp (_core_io_ptw_gstatus_spp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpie (_core_io_ptw_gstatus_mpie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_ube (_core_io_ptw_gstatus_ube), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spie (_core_io_ptw_gstatus_spie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_upie (_core_io_ptw_gstatus_upie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mie (_core_io_ptw_gstatus_mie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_hie (_core_io_ptw_gstatus_hie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sie (_core_io_ptw_gstatus_sie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_uie (_core_io_ptw_gstatus_uie), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[RocketTile.scala:147:20] .io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), .io_dpath_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), .io_dpath_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), // @[RocketTile.scala:147:20] .io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled) ); // @[PTW.scala:802:19] Rocket core ( // @[RocketTile.scala:147:20] .clock (clock), .reset (reset), .io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17] .io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17] .io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17] .io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17] .io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17] .io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17] .io_imem_might_request (_core_io_imem_might_request), .io_imem_req_valid (_core_io_imem_req_valid), .io_imem_req_bits_pc (_core_io_imem_req_bits_pc), .io_imem_req_bits_speculative (_core_io_imem_req_bits_speculative), .io_imem_sfence_valid (_core_io_imem_sfence_valid), .io_imem_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), .io_imem_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), .io_imem_sfence_bits_addr (_core_io_imem_sfence_bits_addr), .io_imem_sfence_bits_asid (_core_io_imem_sfence_bits_asid), .io_imem_sfence_bits_hv (_core_io_imem_sfence_bits_hv), .io_imem_sfence_bits_hg (_core_io_imem_sfence_bits_hg), .io_imem_resp_ready (_core_io_imem_resp_ready), .io_imem_resp_valid (_frontend_io_cpu_resp_valid), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), // @[Frontend.scala:393:28] .io_imem_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), // @[Frontend.scala:393:28] .io_imem_resp_bits_data (_frontend_io_cpu_resp_bits_data), // @[Frontend.scala:393:28] .io_imem_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), // @[Frontend.scala:393:28] .io_imem_gpa_valid (_frontend_io_cpu_gpa_valid), // @[Frontend.scala:393:28] .io_imem_gpa_bits (_frontend_io_cpu_gpa_bits), // @[Frontend.scala:393:28] .io_imem_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), // @[Frontend.scala:393:28] .io_imem_btb_update_valid (_core_io_imem_btb_update_valid), .io_imem_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), .io_imem_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), .io_imem_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), .io_imem_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), .io_imem_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), .io_imem_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), .io_imem_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), .io_imem_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), .io_imem_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), .io_imem_btb_update_bits_target (_core_io_imem_btb_update_bits_target), .io_imem_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), .io_imem_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), .io_imem_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), .io_imem_bht_update_valid (_core_io_imem_bht_update_valid), .io_imem_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), .io_imem_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), .io_imem_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), .io_imem_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), .io_imem_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), .io_imem_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), .io_imem_flush_icache (_core_io_imem_flush_icache), .io_imem_npc (_frontend_io_cpu_npc), // @[Frontend.scala:393:28] .io_imem_perf_acquire (_frontend_io_cpu_perf_acquire), // @[Frontend.scala:393:28] .io_imem_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[Frontend.scala:393:28] .io_imem_progress (_core_io_imem_progress), .io_dmem_req_ready (_dcacheArb_io_requestor_1_req_ready), // @[HellaCache.scala:292:25] .io_dmem_req_valid (_core_io_dmem_req_valid), .io_dmem_req_bits_addr (_core_io_dmem_req_bits_addr), .io_dmem_req_bits_tag (_core_io_dmem_req_bits_tag), .io_dmem_req_bits_cmd (_core_io_dmem_req_bits_cmd), .io_dmem_req_bits_size (_core_io_dmem_req_bits_size), .io_dmem_req_bits_signed (_core_io_dmem_req_bits_signed), .io_dmem_req_bits_dprv (_core_io_dmem_req_bits_dprv), .io_dmem_req_bits_dv (_core_io_dmem_req_bits_dv), .io_dmem_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), .io_dmem_s1_kill (_core_io_dmem_s1_kill), .io_dmem_s1_data_data (_core_io_dmem_s1_data_data), .io_dmem_s2_nack (_dcacheArb_io_requestor_1_s2_nack), // @[HellaCache.scala:292:25] .io_dmem_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), // @[HellaCache.scala:292:25] .io_dmem_resp_valid (_dcacheArb_io_requestor_1_resp_valid), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_dmem_replay_next (_dcacheArb_io_requestor_1_replay_next), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_dmem_ordered (_dcacheArb_io_requestor_1_ordered), // @[HellaCache.scala:292:25] .io_dmem_store_pending (_dcacheArb_io_requestor_1_store_pending), // @[HellaCache.scala:292:25] .io_dmem_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), // @[HellaCache.scala:292:25] .io_dmem_perf_release (_dcacheArb_io_requestor_1_perf_release), // @[HellaCache.scala:292:25] .io_dmem_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_dmem_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), .io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode), .io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn), .io_ptw_sfence_valid (_core_io_ptw_sfence_valid), .io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), .io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), .io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), .io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), .io_ptw_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), .io_ptw_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), .io_ptw_status_debug (_core_io_ptw_status_debug), .io_ptw_status_cease (_core_io_ptw_status_cease), .io_ptw_status_wfi (_core_io_ptw_status_wfi), .io_ptw_status_isa (_core_io_ptw_status_isa), .io_ptw_status_dprv (_core_io_ptw_status_dprv), .io_ptw_status_dv (_core_io_ptw_status_dv), .io_ptw_status_prv (_core_io_ptw_status_prv), .io_ptw_status_v (_core_io_ptw_status_v), .io_ptw_status_sd (_core_io_ptw_status_sd), .io_ptw_status_mpv (_core_io_ptw_status_mpv), .io_ptw_status_gva (_core_io_ptw_status_gva), .io_ptw_status_tsr (_core_io_ptw_status_tsr), .io_ptw_status_tw (_core_io_ptw_status_tw), .io_ptw_status_tvm (_core_io_ptw_status_tvm), .io_ptw_status_mxr (_core_io_ptw_status_mxr), .io_ptw_status_sum (_core_io_ptw_status_sum), .io_ptw_status_mprv (_core_io_ptw_status_mprv), .io_ptw_status_fs (_core_io_ptw_status_fs), .io_ptw_status_mpp (_core_io_ptw_status_mpp), .io_ptw_status_spp (_core_io_ptw_status_spp), .io_ptw_status_mpie (_core_io_ptw_status_mpie), .io_ptw_status_spie (_core_io_ptw_status_spie), .io_ptw_status_mie (_core_io_ptw_status_mie), .io_ptw_status_sie (_core_io_ptw_status_sie), .io_ptw_hstatus_spvp (_core_io_ptw_hstatus_spvp), .io_ptw_hstatus_spv (_core_io_ptw_hstatus_spv), .io_ptw_hstatus_gva (_core_io_ptw_hstatus_gva), .io_ptw_gstatus_debug (_core_io_ptw_gstatus_debug), .io_ptw_gstatus_cease (_core_io_ptw_gstatus_cease), .io_ptw_gstatus_wfi (_core_io_ptw_gstatus_wfi), .io_ptw_gstatus_isa (_core_io_ptw_gstatus_isa), .io_ptw_gstatus_dprv (_core_io_ptw_gstatus_dprv), .io_ptw_gstatus_dv (_core_io_ptw_gstatus_dv), .io_ptw_gstatus_prv (_core_io_ptw_gstatus_prv), .io_ptw_gstatus_v (_core_io_ptw_gstatus_v), .io_ptw_gstatus_sd (_core_io_ptw_gstatus_sd), .io_ptw_gstatus_zero2 (_core_io_ptw_gstatus_zero2), .io_ptw_gstatus_mpv (_core_io_ptw_gstatus_mpv), .io_ptw_gstatus_gva (_core_io_ptw_gstatus_gva), .io_ptw_gstatus_mbe (_core_io_ptw_gstatus_mbe), .io_ptw_gstatus_sbe (_core_io_ptw_gstatus_sbe), .io_ptw_gstatus_sxl (_core_io_ptw_gstatus_sxl), .io_ptw_gstatus_zero1 (_core_io_ptw_gstatus_zero1), .io_ptw_gstatus_tsr (_core_io_ptw_gstatus_tsr), .io_ptw_gstatus_tw (_core_io_ptw_gstatus_tw), .io_ptw_gstatus_tvm (_core_io_ptw_gstatus_tvm), .io_ptw_gstatus_mxr (_core_io_ptw_gstatus_mxr), .io_ptw_gstatus_sum (_core_io_ptw_gstatus_sum), .io_ptw_gstatus_mprv (_core_io_ptw_gstatus_mprv), .io_ptw_gstatus_fs (_core_io_ptw_gstatus_fs), .io_ptw_gstatus_mpp (_core_io_ptw_gstatus_mpp), .io_ptw_gstatus_vs (_core_io_ptw_gstatus_vs), .io_ptw_gstatus_spp (_core_io_ptw_gstatus_spp), .io_ptw_gstatus_mpie (_core_io_ptw_gstatus_mpie), .io_ptw_gstatus_ube (_core_io_ptw_gstatus_ube), .io_ptw_gstatus_spie (_core_io_ptw_gstatus_spie), .io_ptw_gstatus_upie (_core_io_ptw_gstatus_upie), .io_ptw_gstatus_mie (_core_io_ptw_gstatus_mie), .io_ptw_gstatus_hie (_core_io_ptw_gstatus_hie), .io_ptw_gstatus_sie (_core_io_ptw_gstatus_sie), .io_ptw_gstatus_uie (_core_io_ptw_gstatus_uie), .io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask), .io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[PTW.scala:802:19] .io_ptw_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), .io_ptw_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), .io_ptw_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), .io_ptw_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), .io_ptw_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), .io_ptw_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), .io_ptw_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), .io_ptw_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), .io_ptw_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), .io_ptw_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), .io_ptw_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), .io_ptw_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), .io_ptw_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), .io_ptw_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), .io_ptw_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), .io_ptw_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), .io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[PTW.scala:802:19] .io_fpu_hartid (_core_io_fpu_hartid), .io_fpu_time (_core_io_fpu_time), .io_fpu_inst (_core_io_fpu_inst), .io_fpu_fromint_data (_core_io_fpu_fromint_data), .io_fpu_fcsr_rm (_core_io_fpu_fcsr_rm), .io_fpu_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), // @[RocketTile.scala:242:62] .io_fpu_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), // @[RocketTile.scala:242:62] .io_fpu_store_data (_fpuOpt_io_store_data), // @[RocketTile.scala:242:62] .io_fpu_toint_data (_fpuOpt_io_toint_data), // @[RocketTile.scala:242:62] .io_fpu_ll_resp_val (_core_io_fpu_ll_resp_val), .io_fpu_ll_resp_type (_core_io_fpu_ll_resp_type), .io_fpu_ll_resp_tag (_core_io_fpu_ll_resp_tag), .io_fpu_ll_resp_data (_core_io_fpu_ll_resp_data), .io_fpu_valid (_core_io_fpu_valid), .io_fpu_fcsr_rdy (_fpuOpt_io_fcsr_rdy), // @[RocketTile.scala:242:62] .io_fpu_nack_mem (_fpuOpt_io_nack_mem), // @[RocketTile.scala:242:62] .io_fpu_illegal_rm (_fpuOpt_io_illegal_rm), // @[RocketTile.scala:242:62] .io_fpu_killx (_core_io_fpu_killx), .io_fpu_killm (_core_io_fpu_killm), .io_fpu_dec_ldst (_fpuOpt_io_dec_ldst), // @[RocketTile.scala:242:62] .io_fpu_dec_wen (_fpuOpt_io_dec_wen), // @[RocketTile.scala:242:62] .io_fpu_dec_ren1 (_fpuOpt_io_dec_ren1), // @[RocketTile.scala:242:62] .io_fpu_dec_ren2 (_fpuOpt_io_dec_ren2), // @[RocketTile.scala:242:62] .io_fpu_dec_ren3 (_fpuOpt_io_dec_ren3), // @[RocketTile.scala:242:62] .io_fpu_dec_swap12 (_fpuOpt_io_dec_swap12), // @[RocketTile.scala:242:62] .io_fpu_dec_swap23 (_fpuOpt_io_dec_swap23), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), // @[RocketTile.scala:242:62] .io_fpu_dec_fromint (_fpuOpt_io_dec_fromint), // @[RocketTile.scala:242:62] .io_fpu_dec_toint (_fpuOpt_io_dec_toint), // @[RocketTile.scala:242:62] .io_fpu_dec_fastpipe (_fpuOpt_io_dec_fastpipe), // @[RocketTile.scala:242:62] .io_fpu_dec_fma (_fpuOpt_io_dec_fma), // @[RocketTile.scala:242:62] .io_fpu_dec_div (_fpuOpt_io_dec_div), // @[RocketTile.scala:242:62] .io_fpu_dec_sqrt (_fpuOpt_io_dec_sqrt), // @[RocketTile.scala:242:62] .io_fpu_dec_wflags (_fpuOpt_io_dec_wflags), // @[RocketTile.scala:242:62] .io_fpu_dec_vec (_fpuOpt_io_dec_vec), // @[RocketTile.scala:242:62] .io_fpu_sboard_set (_fpuOpt_io_sboard_set), // @[RocketTile.scala:242:62] .io_fpu_sboard_clr (_fpuOpt_io_sboard_clr), // @[RocketTile.scala:242:62] .io_fpu_sboard_clra (_fpuOpt_io_sboard_clra), // @[RocketTile.scala:242:62] .io_fpu_keep_clock_enabled (_core_io_fpu_keep_clock_enabled), .io_trace_insns_0_valid (traceSourceNodeOut_insns_0_valid), .io_trace_insns_0_iaddr (traceSourceNodeOut_insns_0_iaddr), .io_trace_insns_0_insn (traceSourceNodeOut_insns_0_insn), .io_trace_insns_0_priv (traceSourceNodeOut_insns_0_priv), .io_trace_insns_0_exception (traceSourceNodeOut_insns_0_exception), .io_trace_insns_0_interrupt (traceSourceNodeOut_insns_0_interrupt), .io_trace_insns_0_cause (traceSourceNodeOut_insns_0_cause), .io_trace_insns_0_tval (traceSourceNodeOut_insns_0_tval), .io_trace_time (traceSourceNodeOut_time), .io_bpwatch_0_valid_0 (bpwatchSourceNodeOut_0_valid_0), .io_bpwatch_0_action (bpwatchSourceNodeOut_0_action), .io_wfi (_core_io_wfi) ); // @[RocketTile.scala:147:20] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[RocketTile.scala:141:7] assign auto_wfi_out_0 = auto_wfi_out_0_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_valid = auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr = auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn = auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv = auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception = auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt = auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause = auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval = auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_209 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_209( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_30 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_60 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_61 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_30( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_69 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<27>(0h4000000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<27>(0h4000000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<27>(0h4000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<27>(0h4000000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<27>(0h4000000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<27>(0h4000000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<27>(0h4000000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<27>(0h4000000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<27>(0h4000000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_151 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_152 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_69( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire [2047:0] _GEN = {2037'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [2047:0] _GEN_2 = {2037'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_9 : input clock : Clock input reset : Reset output io : { req : { flip `4` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}}, resp : { `4` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `3` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `2` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `1` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `0` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<17> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<12> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_andMatrixInput_2) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node _decoded_orMatrixOutputs_T = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_lo_lo_hi = cat(_decoded_orMatrixOutputs_T_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi = cat(decoded_orMatrixOutputs_lo_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo = cat(decoded_orMatrixOutputs_hi_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs, 9, 9) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs, 10, 10) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs, 11, 11) node decoded_invMatrixOutputs_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_2, _decoded_invMatrixOutputs_T_1) node decoded_invMatrixOutputs_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_hi, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_lo_hi = cat(decoded_invMatrixOutputs_lo_hi_hi, _decoded_invMatrixOutputs_T_3) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_hi_lo = cat(decoded_invMatrixOutputs_hi_lo_hi, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 7, 0) node _decoded_T_1 = shl(UInt<4>(0hf), 4) node _decoded_T_2 = xor(UInt<8>(0hff), _decoded_T_1) node _decoded_T_3 = shr(_decoded_T, 4) node _decoded_T_4 = and(_decoded_T_3, _decoded_T_2) node _decoded_T_5 = bits(_decoded_T, 3, 0) node _decoded_T_6 = shl(_decoded_T_5, 4) node _decoded_T_7 = not(_decoded_T_2) node _decoded_T_8 = and(_decoded_T_6, _decoded_T_7) node _decoded_T_9 = or(_decoded_T_4, _decoded_T_8) node _decoded_T_10 = bits(_decoded_T_2, 5, 0) node _decoded_T_11 = shl(_decoded_T_10, 2) node _decoded_T_12 = xor(_decoded_T_2, _decoded_T_11) node _decoded_T_13 = shr(_decoded_T_9, 2) node _decoded_T_14 = and(_decoded_T_13, _decoded_T_12) node _decoded_T_15 = bits(_decoded_T_9, 5, 0) node _decoded_T_16 = shl(_decoded_T_15, 2) node _decoded_T_17 = not(_decoded_T_12) node _decoded_T_18 = and(_decoded_T_16, _decoded_T_17) node _decoded_T_19 = or(_decoded_T_14, _decoded_T_18) node _decoded_T_20 = bits(_decoded_T_12, 6, 0) node _decoded_T_21 = shl(_decoded_T_20, 1) node _decoded_T_22 = xor(_decoded_T_12, _decoded_T_21) node _decoded_T_23 = shr(_decoded_T_19, 1) node _decoded_T_24 = and(_decoded_T_23, _decoded_T_22) node _decoded_T_25 = bits(_decoded_T_19, 6, 0) node _decoded_T_26 = shl(_decoded_T_25, 1) node _decoded_T_27 = not(_decoded_T_22) node _decoded_T_28 = and(_decoded_T_26, _decoded_T_27) node _decoded_T_29 = or(_decoded_T_24, _decoded_T_28) node _decoded_T_30 = bits(decoded_plaOutput, 11, 8) node _decoded_T_31 = bits(_decoded_T_30, 1, 0) node _decoded_T_32 = bits(_decoded_T_31, 0, 0) node _decoded_T_33 = bits(_decoded_T_31, 1, 1) node _decoded_T_34 = cat(_decoded_T_32, _decoded_T_33) node _decoded_T_35 = bits(_decoded_T_30, 3, 2) node _decoded_T_36 = bits(_decoded_T_35, 0, 0) node _decoded_T_37 = bits(_decoded_T_35, 1, 1) node _decoded_T_38 = cat(_decoded_T_36, _decoded_T_37) node _decoded_T_39 = cat(_decoded_T_34, _decoded_T_38) node decoded = cat(_decoded_T_29, _decoded_T_39) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_1_0_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T node _io_resp_0_vc_sel_1_1_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T node _io_resp_0_vc_sel_1_2_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`1`[2], _io_resp_0_vc_sel_1_2_T node _io_resp_0_vc_sel_2_0_T = bits(decoded, 6, 6) connect io.resp.`0`.vc_sel.`2`[0], _io_resp_0_vc_sel_2_0_T node _io_resp_0_vc_sel_2_1_T = bits(decoded, 7, 7) connect io.resp.`0`.vc_sel.`2`[1], _io_resp_0_vc_sel_2_1_T node _io_resp_0_vc_sel_2_2_T = bits(decoded, 8, 8) connect io.resp.`0`.vc_sel.`2`[2], _io_resp_0_vc_sel_2_2_T node _io_resp_0_vc_sel_3_0_T = bits(decoded, 9, 9) connect io.resp.`0`.vc_sel.`3`[0], _io_resp_0_vc_sel_3_0_T node _io_resp_0_vc_sel_3_1_T = bits(decoded, 10, 10) connect io.resp.`0`.vc_sel.`3`[1], _io_resp_0_vc_sel_3_1_T node _io_resp_0_vc_sel_3_2_T = bits(decoded, 11, 11) connect io.resp.`0`.vc_sel.`3`[2], _io_resp_0_vc_sel_3_2_T connect io.resp.`0`.vc_sel.`4`[0], UInt<1>(0h0) connect io.resp.`0`.vc_sel.`5`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<17> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<12> node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_11, decoded_andMatrixOutputs_andMatrixInput_12) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_13) node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_7, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_lo_hi_lo) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_6) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_7_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_11_1, decoded_andMatrixOutputs_andMatrixInput_12_1) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_13_1) node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_1, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_lo_hi_lo_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_6_1) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_3, decoded_andMatrixOutputs_andMatrixInput_3_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_11_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12_2) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_13_2) node decoded_andMatrixOutputs_lo_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_7_2, decoded_andMatrixOutputs_andMatrixInput_8_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_lo_hi_lo_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_2, decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_4, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_hi_hi_lo_2) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_11_3, decoded_andMatrixOutputs_andMatrixInput_12_3) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_13_3) node decoded_andMatrixOutputs_lo_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_3, decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_7_3, decoded_andMatrixOutputs_andMatrixInput_8_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_lo_hi_lo_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_4_3, decoded_andMatrixOutputs_andMatrixInput_5_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_2_5, decoded_andMatrixOutputs_andMatrixInput_3_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_hi_hi_lo_3) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_11_4, decoded_andMatrixOutputs_andMatrixInput_12_4) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_13_4) node decoded_andMatrixOutputs_lo_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo_4) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_4_4, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_6, decoded_andMatrixOutputs_andMatrixInput_3_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo_4) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_8_2 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_5) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_13_5) node decoded_andMatrixOutputs_lo_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_7_5, decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_lo_hi_lo_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_4_5, decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_hi_hi_lo_5) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_11_6, decoded_andMatrixOutputs_andMatrixInput_12_6) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_13_6) node decoded_andMatrixOutputs_lo_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_6) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_7_6, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_lo_hi_lo_6) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_4_6, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_6_6) node decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_8, decoded_andMatrixOutputs_andMatrixInput_3_6) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_hi_hi_lo_6) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_11_7, decoded_andMatrixOutputs_andMatrixInput_12_7) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_13_7) node decoded_andMatrixOutputs_lo_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_7) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_lo_hi_lo_7) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_4_7, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_6_7) node decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_2_9, decoded_andMatrixOutputs_andMatrixInput_3_7) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_hi_hi_lo_7) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_11_8, decoded_andMatrixOutputs_andMatrixInput_12_8) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_andMatrixInput_13_8) node decoded_andMatrixOutputs_lo_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_andMatrixOutputs_andMatrixInput_10_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_7_8, decoded_andMatrixOutputs_andMatrixInput_8_8) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_lo_hi_lo_8) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_4_8, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_andMatrixInput_6_8) node decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_2_10, decoded_andMatrixOutputs_andMatrixInput_3_8) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_hi_hi_lo_8) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_9_2 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_11_9, decoded_andMatrixOutputs_andMatrixInput_12_9) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_13_9) node decoded_andMatrixOutputs_lo_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_andMatrixOutputs_andMatrixInput_10_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_7_9, decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_lo_hi_lo_9) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_4_9, decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_6_9) node decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_2_11, decoded_andMatrixOutputs_andMatrixInput_3_9) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_hi_hi_lo_9) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_11_10, decoded_andMatrixOutputs_andMatrixInput_12_10) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_13_10) node decoded_andMatrixOutputs_lo_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_10) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_10) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_4_10, decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_6_10) node decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_2_12, decoded_andMatrixOutputs_andMatrixInput_3_10) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_10) node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_11_11, decoded_andMatrixOutputs_andMatrixInput_12_11) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_lo_lo_hi_11, decoded_andMatrixOutputs_andMatrixInput_13_11) node decoded_andMatrixOutputs_lo_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_9_11, decoded_andMatrixOutputs_andMatrixInput_10_11) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_7_11, decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_lo_hi_lo_11) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_4_11, decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_andMatrixInput_6_11) node decoded_andMatrixOutputs_hi_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_2_13, decoded_andMatrixOutputs_andMatrixInput_3_11) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_hi_hi_lo_11) node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_10_2 = andr(_decoded_andMatrixOutputs_T_13) node decoded_orMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_10_2) node decoded_orMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_3_2) node _decoded_orMatrixOutputs_T_2 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node decoded_orMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_4 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_4_2, decoded_andMatrixOutputs_6_2) node _decoded_orMatrixOutputs_T_7 = orr(_decoded_orMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_11_2) node _decoded_orMatrixOutputs_T_9 = orr(_decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_lo_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_1 = cat(decoded_orMatrixOutputs_lo_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_1, _decoded_orMatrixOutputs_T_3) node decoded_orMatrixOutputs_lo_3 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_1 = cat(decoded_orMatrixOutputs_hi_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_9) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs_1, 8, 8) node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs_1, 9, 9) node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs_1, 10, 10) node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs_1, 11, 11) node decoded_invMatrixOutputs_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_1, _decoded_invMatrixOutputs_T_12) node decoded_invMatrixOutputs_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_1, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_20, _decoded_invMatrixOutputs_T_19) node decoded_invMatrixOutputs_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_1, _decoded_invMatrixOutputs_T_18) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_21) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_40 = bits(decoded_plaOutput_1, 7, 0) node _decoded_T_41 = shl(UInt<4>(0hf), 4) node _decoded_T_42 = xor(UInt<8>(0hff), _decoded_T_41) node _decoded_T_43 = shr(_decoded_T_40, 4) node _decoded_T_44 = and(_decoded_T_43, _decoded_T_42) node _decoded_T_45 = bits(_decoded_T_40, 3, 0) node _decoded_T_46 = shl(_decoded_T_45, 4) node _decoded_T_47 = not(_decoded_T_42) node _decoded_T_48 = and(_decoded_T_46, _decoded_T_47) node _decoded_T_49 = or(_decoded_T_44, _decoded_T_48) node _decoded_T_50 = bits(_decoded_T_42, 5, 0) node _decoded_T_51 = shl(_decoded_T_50, 2) node _decoded_T_52 = xor(_decoded_T_42, _decoded_T_51) node _decoded_T_53 = shr(_decoded_T_49, 2) node _decoded_T_54 = and(_decoded_T_53, _decoded_T_52) node _decoded_T_55 = bits(_decoded_T_49, 5, 0) node _decoded_T_56 = shl(_decoded_T_55, 2) node _decoded_T_57 = not(_decoded_T_52) node _decoded_T_58 = and(_decoded_T_56, _decoded_T_57) node _decoded_T_59 = or(_decoded_T_54, _decoded_T_58) node _decoded_T_60 = bits(_decoded_T_52, 6, 0) node _decoded_T_61 = shl(_decoded_T_60, 1) node _decoded_T_62 = xor(_decoded_T_52, _decoded_T_61) node _decoded_T_63 = shr(_decoded_T_59, 1) node _decoded_T_64 = and(_decoded_T_63, _decoded_T_62) node _decoded_T_65 = bits(_decoded_T_59, 6, 0) node _decoded_T_66 = shl(_decoded_T_65, 1) node _decoded_T_67 = not(_decoded_T_62) node _decoded_T_68 = and(_decoded_T_66, _decoded_T_67) node _decoded_T_69 = or(_decoded_T_64, _decoded_T_68) node _decoded_T_70 = bits(decoded_plaOutput_1, 11, 8) node _decoded_T_71 = bits(_decoded_T_70, 1, 0) node _decoded_T_72 = bits(_decoded_T_71, 0, 0) node _decoded_T_73 = bits(_decoded_T_71, 1, 1) node _decoded_T_74 = cat(_decoded_T_72, _decoded_T_73) node _decoded_T_75 = bits(_decoded_T_70, 3, 2) node _decoded_T_76 = bits(_decoded_T_75, 0, 0) node _decoded_T_77 = bits(_decoded_T_75, 1, 1) node _decoded_T_78 = cat(_decoded_T_76, _decoded_T_77) node _decoded_T_79 = cat(_decoded_T_74, _decoded_T_78) node decoded_1 = cat(_decoded_T_69, _decoded_T_79) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T node _io_resp_1_vc_sel_1_2_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`1`[2], _io_resp_1_vc_sel_1_2_T node _io_resp_1_vc_sel_2_0_T = bits(decoded_1, 6, 6) connect io.resp.`1`.vc_sel.`2`[0], _io_resp_1_vc_sel_2_0_T node _io_resp_1_vc_sel_2_1_T = bits(decoded_1, 7, 7) connect io.resp.`1`.vc_sel.`2`[1], _io_resp_1_vc_sel_2_1_T node _io_resp_1_vc_sel_2_2_T = bits(decoded_1, 8, 8) connect io.resp.`1`.vc_sel.`2`[2], _io_resp_1_vc_sel_2_2_T node _io_resp_1_vc_sel_3_0_T = bits(decoded_1, 9, 9) connect io.resp.`1`.vc_sel.`3`[0], _io_resp_1_vc_sel_3_0_T node _io_resp_1_vc_sel_3_1_T = bits(decoded_1, 10, 10) connect io.resp.`1`.vc_sel.`3`[1], _io_resp_1_vc_sel_3_1_T node _io_resp_1_vc_sel_3_2_T = bits(decoded_1, 11, 11) connect io.resp.`1`.vc_sel.`3`[2], _io_resp_1_vc_sel_3_2_T connect io.resp.`1`.vc_sel.`4`[0], UInt<1>(0h0) connect io.resp.`1`.vc_sel.`5`[0], UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<17> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<12> node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_invInputs_2, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_invInputs_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(decoded_invInputs_2, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_10_12, decoded_andMatrixOutputs_andMatrixInput_11_12) node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_12, decoded_andMatrixOutputs_andMatrixInput_12_12) node decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_7_12, decoded_andMatrixOutputs_andMatrixInput_8_12) node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_9_12) node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12) node decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_4_12, decoded_andMatrixOutputs_andMatrixInput_5_12) node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_12, decoded_andMatrixOutputs_andMatrixInput_6_12) node decoded_andMatrixOutputs_hi_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_2_14, decoded_andMatrixOutputs_andMatrixInput_3_12) node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_hi_hi_lo_12) node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12) node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_12) node decoded_andMatrixOutputs_9_2_1 = andr(_decoded_andMatrixOutputs_T_14) node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs_2, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_invInputs_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_invInputs_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_invInputs_2, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_12_13, decoded_andMatrixOutputs_andMatrixInput_13_12) node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_lo_lo_hi_13, decoded_andMatrixOutputs_andMatrixInput_14) node decoded_andMatrixOutputs_lo_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_10_13, decoded_andMatrixOutputs_andMatrixInput_11_13) node decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_8_13, decoded_andMatrixOutputs_andMatrixInput_9_13) node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_13, decoded_andMatrixOutputs_lo_hi_lo_12) node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13) node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_4_13, decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_13, decoded_andMatrixOutputs_hi_lo_lo) node decoded_andMatrixOutputs_hi_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_2_15, decoded_andMatrixOutputs_andMatrixInput_3_13) node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_hi_hi_lo_13) node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13) node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_13) node decoded_andMatrixOutputs_13_2 = andr(_decoded_andMatrixOutputs_T_15) node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_invInputs_2, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_invInputs_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(decoded_invInputs_2, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_10_14, decoded_andMatrixOutputs_andMatrixInput_11_14) node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_lo_lo_hi_14, decoded_andMatrixOutputs_andMatrixInput_12_14) node decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_7_14, decoded_andMatrixOutputs_andMatrixInput_8_14) node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_9_14) node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14) node decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_4_14, decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_14, decoded_andMatrixOutputs_andMatrixInput_6_14) node decoded_andMatrixOutputs_hi_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_2_16, decoded_andMatrixOutputs_andMatrixInput_3_14) node decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_hi_hi_lo_14) node decoded_andMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14) node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_14) node decoded_andMatrixOutputs_11_2_1 = andr(_decoded_andMatrixOutputs_T_16) node decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_invInputs_2, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_invInputs_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_invInputs_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_invInputs_2, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_12_15, decoded_andMatrixOutputs_andMatrixInput_13_13) node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_lo_lo_hi_15, decoded_andMatrixOutputs_andMatrixInput_14_1) node decoded_andMatrixOutputs_lo_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_10_15, decoded_andMatrixOutputs_andMatrixInput_11_15) node decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_8_15, decoded_andMatrixOutputs_andMatrixInput_9_15) node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_lo_hi_hi_15, decoded_andMatrixOutputs_lo_hi_lo_13) node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15) node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_andMatrixOutputs_andMatrixInput_7_15) node decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_4_15, decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_hi_lo_hi_15, decoded_andMatrixOutputs_hi_lo_lo_1) node decoded_andMatrixOutputs_hi_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_2_17, decoded_andMatrixOutputs_andMatrixInput_3_15) node decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_15, decoded_andMatrixOutputs_hi_hi_lo_15) node decoded_andMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15) node _decoded_andMatrixOutputs_T_17 = cat(decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_15) node decoded_andMatrixOutputs_10_2_1 = andr(_decoded_andMatrixOutputs_T_17) node decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_plaInput_2, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_invInputs_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_invInputs_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(decoded_invInputs_2, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_12_16, decoded_andMatrixOutputs_andMatrixInput_13_14) node decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_andMatrixOutputs_lo_lo_hi_16, decoded_andMatrixOutputs_andMatrixInput_14_2) node decoded_andMatrixOutputs_lo_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_10_16, decoded_andMatrixOutputs_andMatrixInput_11_16) node decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_8_16, decoded_andMatrixOutputs_andMatrixInput_9_16) node decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_andMatrixOutputs_lo_hi_hi_16, decoded_andMatrixOutputs_lo_hi_lo_14) node decoded_andMatrixOutputs_lo_16 = cat(decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16) node decoded_andMatrixOutputs_hi_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_4_16, decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_andMatrixOutputs_hi_lo_hi_16, decoded_andMatrixOutputs_hi_lo_lo_2) node decoded_andMatrixOutputs_hi_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_2_18, decoded_andMatrixOutputs_andMatrixInput_3_16) node decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_hi_16, decoded_andMatrixOutputs_hi_hi_lo_16) node decoded_andMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16) node _decoded_andMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_lo_16) node decoded_andMatrixOutputs_7_2_1 = andr(_decoded_andMatrixOutputs_T_18) node decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_plaInput_2, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_invInputs_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_invInputs_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(decoded_invInputs_2, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_12_17, decoded_andMatrixOutputs_andMatrixInput_13_15) node decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_andMatrixOutputs_lo_lo_hi_17, decoded_andMatrixOutputs_andMatrixInput_14_3) node decoded_andMatrixOutputs_lo_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_10_17, decoded_andMatrixOutputs_andMatrixInput_11_17) node decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_8_17, decoded_andMatrixOutputs_andMatrixInput_9_17) node decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_andMatrixOutputs_lo_hi_hi_17, decoded_andMatrixOutputs_lo_hi_lo_15) node decoded_andMatrixOutputs_lo_17 = cat(decoded_andMatrixOutputs_lo_hi_17, decoded_andMatrixOutputs_lo_lo_17) node decoded_andMatrixOutputs_hi_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_andMatrixOutputs_andMatrixInput_7_17) node decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_4_17, decoded_andMatrixOutputs_andMatrixInput_5_17) node decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_andMatrixOutputs_hi_lo_hi_17, decoded_andMatrixOutputs_hi_lo_lo_3) node decoded_andMatrixOutputs_hi_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_2_19, decoded_andMatrixOutputs_andMatrixInput_3_17) node decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_hi_17, decoded_andMatrixOutputs_hi_hi_lo_17) node decoded_andMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_17, decoded_andMatrixOutputs_hi_lo_17) node _decoded_andMatrixOutputs_T_19 = cat(decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_lo_17) node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_19) node decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_plaInput_2, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_plaInput_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_plaInput_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_invInputs_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(decoded_invInputs_2, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_12_18, decoded_andMatrixOutputs_andMatrixInput_13_16) node decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_andMatrixOutputs_lo_lo_hi_18, decoded_andMatrixOutputs_andMatrixInput_14_4) node decoded_andMatrixOutputs_lo_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_10_18, decoded_andMatrixOutputs_andMatrixInput_11_18) node decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_8_18, decoded_andMatrixOutputs_andMatrixInput_9_18) node decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_andMatrixOutputs_lo_hi_hi_18, decoded_andMatrixOutputs_lo_hi_lo_16) node decoded_andMatrixOutputs_lo_18 = cat(decoded_andMatrixOutputs_lo_hi_18, decoded_andMatrixOutputs_lo_lo_18) node decoded_andMatrixOutputs_hi_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_andMatrixOutputs_andMatrixInput_7_18) node decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_4_18, decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_andMatrixOutputs_hi_lo_hi_18, decoded_andMatrixOutputs_hi_lo_lo_4) node decoded_andMatrixOutputs_hi_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_2_20, decoded_andMatrixOutputs_andMatrixInput_3_18) node decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_hi_18, decoded_andMatrixOutputs_hi_hi_lo_18) node decoded_andMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_18, decoded_andMatrixOutputs_hi_lo_18) node _decoded_andMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_lo_18) node decoded_andMatrixOutputs_1_2_2 = andr(_decoded_andMatrixOutputs_T_20) node decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_plaInput_2, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_invInputs_2, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_plaInput_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_plaInput_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_invInputs_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_19 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_17 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(decoded_invInputs_2, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_12_19, decoded_andMatrixOutputs_andMatrixInput_13_17) node decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_andMatrixOutputs_lo_lo_hi_19, decoded_andMatrixOutputs_andMatrixInput_14_5) node decoded_andMatrixOutputs_lo_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_10_19, decoded_andMatrixOutputs_andMatrixInput_11_19) node decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_8_19, decoded_andMatrixOutputs_andMatrixInput_9_19) node decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_andMatrixOutputs_lo_hi_hi_19, decoded_andMatrixOutputs_lo_hi_lo_17) node decoded_andMatrixOutputs_lo_19 = cat(decoded_andMatrixOutputs_lo_hi_19, decoded_andMatrixOutputs_lo_lo_19) node decoded_andMatrixOutputs_hi_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_andMatrixOutputs_andMatrixInput_7_19) node decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_4_19, decoded_andMatrixOutputs_andMatrixInput_5_19) node decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_andMatrixOutputs_hi_lo_hi_19, decoded_andMatrixOutputs_hi_lo_lo_5) node decoded_andMatrixOutputs_hi_hi_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_2_21, decoded_andMatrixOutputs_andMatrixInput_3_19) node decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21) node decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_hi_19, decoded_andMatrixOutputs_hi_hi_lo_19) node decoded_andMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_19, decoded_andMatrixOutputs_hi_lo_19) node _decoded_andMatrixOutputs_T_21 = cat(decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_lo_19) node decoded_andMatrixOutputs_8_2_1 = andr(_decoded_andMatrixOutputs_T_21) node decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_plaInput_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_plaInput_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_invInputs_2, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_andMatrixOutputs_andMatrixInput_10_20) node decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_andMatrixOutputs_lo_lo_hi_20, decoded_andMatrixOutputs_andMatrixInput_11_20) node decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_6_20, decoded_andMatrixOutputs_andMatrixInput_7_20) node decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_andMatrixOutputs_lo_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_8_20) node decoded_andMatrixOutputs_lo_20 = cat(decoded_andMatrixOutputs_lo_hi_20, decoded_andMatrixOutputs_lo_lo_20) node decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_andMatrixOutputs_andMatrixInput_4_20) node decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_andMatrixOutputs_hi_lo_hi_20, decoded_andMatrixOutputs_andMatrixInput_5_20) node decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22) node decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_2_22) node decoded_andMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_20, decoded_andMatrixOutputs_hi_lo_20) node _decoded_andMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_lo_20) node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_22) node decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_plaInput_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_plaInput_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_invInputs_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_invInputs_2, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_andMatrixOutputs_andMatrixInput_10_21) node decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_andMatrixOutputs_lo_lo_hi_21, decoded_andMatrixOutputs_andMatrixInput_11_21) node decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_andMatrixOutputs_andMatrixInput_7_21) node decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_andMatrixOutputs_lo_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_8_21) node decoded_andMatrixOutputs_lo_21 = cat(decoded_andMatrixOutputs_lo_hi_21, decoded_andMatrixOutputs_lo_lo_21) node decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_andMatrixOutputs_andMatrixInput_4_21) node decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_andMatrixOutputs_hi_lo_hi_21, decoded_andMatrixOutputs_andMatrixInput_5_21) node decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_andMatrixOutputs_andMatrixInput_1_23) node decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_2_23) node decoded_andMatrixOutputs_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_21, decoded_andMatrixOutputs_hi_lo_21) node _decoded_andMatrixOutputs_T_23 = cat(decoded_andMatrixOutputs_hi_23, decoded_andMatrixOutputs_lo_21) node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_23) node decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_invInputs_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_plaInput_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_20 = bits(decoded_invInputs_2, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_10_22, decoded_andMatrixOutputs_andMatrixInput_11_22) node decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_andMatrixOutputs_lo_lo_hi_22, decoded_andMatrixOutputs_andMatrixInput_12_20) node decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_7_22, decoded_andMatrixOutputs_andMatrixInput_8_22) node decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_andMatrixOutputs_lo_hi_hi_22, decoded_andMatrixOutputs_andMatrixInput_9_22) node decoded_andMatrixOutputs_lo_22 = cat(decoded_andMatrixOutputs_lo_hi_22, decoded_andMatrixOutputs_lo_lo_22) node decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_4_22, decoded_andMatrixOutputs_andMatrixInput_5_22) node decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_andMatrixOutputs_hi_lo_hi_22, decoded_andMatrixOutputs_andMatrixInput_6_22) node decoded_andMatrixOutputs_hi_hi_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_2_24, decoded_andMatrixOutputs_andMatrixInput_3_22) node decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_andMatrixOutputs_andMatrixInput_1_24) node decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_hi_22, decoded_andMatrixOutputs_hi_hi_lo_20) node decoded_andMatrixOutputs_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_22, decoded_andMatrixOutputs_hi_lo_22) node _decoded_andMatrixOutputs_T_24 = cat(decoded_andMatrixOutputs_hi_24, decoded_andMatrixOutputs_lo_22) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_24) node decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_invInputs_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_plaInput_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_21 = bits(decoded_invInputs_2, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_10_23, decoded_andMatrixOutputs_andMatrixInput_11_23) node decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_andMatrixOutputs_lo_lo_hi_23, decoded_andMatrixOutputs_andMatrixInput_12_21) node decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_7_23, decoded_andMatrixOutputs_andMatrixInput_8_23) node decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_andMatrixOutputs_lo_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_9_23) node decoded_andMatrixOutputs_lo_23 = cat(decoded_andMatrixOutputs_lo_hi_23, decoded_andMatrixOutputs_lo_lo_23) node decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_4_23, decoded_andMatrixOutputs_andMatrixInput_5_23) node decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_andMatrixOutputs_hi_lo_hi_23, decoded_andMatrixOutputs_andMatrixInput_6_23) node decoded_andMatrixOutputs_hi_hi_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_2_25, decoded_andMatrixOutputs_andMatrixInput_3_23) node decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_andMatrixOutputs_andMatrixInput_1_25) node decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_hi_23, decoded_andMatrixOutputs_hi_hi_lo_21) node decoded_andMatrixOutputs_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_23, decoded_andMatrixOutputs_hi_lo_23) node _decoded_andMatrixOutputs_T_25 = cat(decoded_andMatrixOutputs_hi_25, decoded_andMatrixOutputs_lo_23) node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_25) node decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_plaInput_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_plaInput_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_22 = bits(decoded_invInputs_2, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_10_24, decoded_andMatrixOutputs_andMatrixInput_11_24) node decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_andMatrixOutputs_lo_lo_hi_24, decoded_andMatrixOutputs_andMatrixInput_12_22) node decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_7_24, decoded_andMatrixOutputs_andMatrixInput_8_24) node decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_andMatrixOutputs_lo_hi_hi_24, decoded_andMatrixOutputs_andMatrixInput_9_24) node decoded_andMatrixOutputs_lo_24 = cat(decoded_andMatrixOutputs_lo_hi_24, decoded_andMatrixOutputs_lo_lo_24) node decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_4_24, decoded_andMatrixOutputs_andMatrixInput_5_24) node decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_andMatrixOutputs_hi_lo_hi_24, decoded_andMatrixOutputs_andMatrixInput_6_24) node decoded_andMatrixOutputs_hi_hi_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_2_26, decoded_andMatrixOutputs_andMatrixInput_3_24) node decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_andMatrixOutputs_andMatrixInput_1_26) node decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_hi_24, decoded_andMatrixOutputs_hi_hi_lo_22) node decoded_andMatrixOutputs_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_24, decoded_andMatrixOutputs_hi_lo_24) node _decoded_andMatrixOutputs_T_26 = cat(decoded_andMatrixOutputs_hi_26, decoded_andMatrixOutputs_lo_24) node decoded_andMatrixOutputs_6_2_1 = andr(_decoded_andMatrixOutputs_T_26) node decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_plaInput_2, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_invInputs_2, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_invInputs_2, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_invInputs_2, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_invInputs_2, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_plaInput_2, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_plaInput_2, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_invInputs_2, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoded_plaInput_2, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoded_invInputs_2, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoded_plaInput_2, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_23 = bits(decoded_invInputs_2, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_10_25, decoded_andMatrixOutputs_andMatrixInput_11_25) node decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_andMatrixOutputs_lo_lo_hi_25, decoded_andMatrixOutputs_andMatrixInput_12_23) node decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_7_25, decoded_andMatrixOutputs_andMatrixInput_8_25) node decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_andMatrixOutputs_lo_hi_hi_25, decoded_andMatrixOutputs_andMatrixInput_9_25) node decoded_andMatrixOutputs_lo_25 = cat(decoded_andMatrixOutputs_lo_hi_25, decoded_andMatrixOutputs_lo_lo_25) node decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_4_25, decoded_andMatrixOutputs_andMatrixInput_5_25) node decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_andMatrixOutputs_hi_lo_hi_25, decoded_andMatrixOutputs_andMatrixInput_6_25) node decoded_andMatrixOutputs_hi_hi_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_2_27, decoded_andMatrixOutputs_andMatrixInput_3_25) node decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_andMatrixOutputs_andMatrixInput_1_27) node decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_hi_25, decoded_andMatrixOutputs_hi_hi_lo_23) node decoded_andMatrixOutputs_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_25, decoded_andMatrixOutputs_hi_lo_25) node _decoded_andMatrixOutputs_T_27 = cat(decoded_andMatrixOutputs_hi_27, decoded_andMatrixOutputs_lo_25) node decoded_andMatrixOutputs_12_2 = andr(_decoded_andMatrixOutputs_T_27) node _decoded_orMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_1_2_2, decoded_andMatrixOutputs_8_2_1) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node _decoded_orMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_0_2_2) node _decoded_orMatrixOutputs_T_13 = orr(_decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_11_2_1, decoded_andMatrixOutputs_10_2_1) node decoded_orMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_9_2_1, decoded_andMatrixOutputs_13_2) node _decoded_orMatrixOutputs_T_14 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_4) node _decoded_orMatrixOutputs_T_15 = orr(_decoded_orMatrixOutputs_T_14) node _decoded_orMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_6_2_1, decoded_andMatrixOutputs_12_2) node _decoded_orMatrixOutputs_T_17 = orr(_decoded_orMatrixOutputs_T_16) node _decoded_orMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_5_2_1) node _decoded_orMatrixOutputs_T_19 = orr(_decoded_orMatrixOutputs_T_18) node _decoded_orMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_7_2_1, decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_21 = orr(_decoded_orMatrixOutputs_T_20) node decoded_orMatrixOutputs_lo_lo_hi_2 = cat(_decoded_orMatrixOutputs_T_11, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_2 = cat(decoded_orMatrixOutputs_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_5 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_orMatrixOutputs_lo_lo_2) node decoded_orMatrixOutputs_hi_lo_hi_2 = cat(_decoded_orMatrixOutputs_T_15, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_2 = cat(decoded_orMatrixOutputs_hi_lo_hi_2, _decoded_orMatrixOutputs_T_13) node decoded_orMatrixOutputs_hi_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_21, _decoded_orMatrixOutputs_T_19) node decoded_orMatrixOutputs_hi_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_hi_2, _decoded_orMatrixOutputs_T_17) node decoded_orMatrixOutputs_hi_5 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_orMatrixOutputs_hi_lo_2) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_5, decoded_orMatrixOutputs_lo_5) node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs_2, 5, 5) node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs_2, 6, 6) node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs_2, 7, 7) node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs_2, 8, 8) node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs_2, 9, 9) node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs_2, 10, 10) node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs_2, 11, 11) node decoded_invMatrixOutputs_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_26, _decoded_invMatrixOutputs_T_25) node decoded_invMatrixOutputs_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_2, _decoded_invMatrixOutputs_T_24) node decoded_invMatrixOutputs_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_29, _decoded_invMatrixOutputs_T_28) node decoded_invMatrixOutputs_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_2, _decoded_invMatrixOutputs_T_27) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2) node decoded_invMatrixOutputs_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_32, _decoded_invMatrixOutputs_T_31) node decoded_invMatrixOutputs_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_2, _decoded_invMatrixOutputs_T_30) node decoded_invMatrixOutputs_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_35, _decoded_invMatrixOutputs_T_34) node decoded_invMatrixOutputs_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_2, _decoded_invMatrixOutputs_T_33) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_80 = bits(decoded_plaOutput_2, 7, 0) node _decoded_T_81 = shl(UInt<4>(0hf), 4) node _decoded_T_82 = xor(UInt<8>(0hff), _decoded_T_81) node _decoded_T_83 = shr(_decoded_T_80, 4) node _decoded_T_84 = and(_decoded_T_83, _decoded_T_82) node _decoded_T_85 = bits(_decoded_T_80, 3, 0) node _decoded_T_86 = shl(_decoded_T_85, 4) node _decoded_T_87 = not(_decoded_T_82) node _decoded_T_88 = and(_decoded_T_86, _decoded_T_87) node _decoded_T_89 = or(_decoded_T_84, _decoded_T_88) node _decoded_T_90 = bits(_decoded_T_82, 5, 0) node _decoded_T_91 = shl(_decoded_T_90, 2) node _decoded_T_92 = xor(_decoded_T_82, _decoded_T_91) node _decoded_T_93 = shr(_decoded_T_89, 2) node _decoded_T_94 = and(_decoded_T_93, _decoded_T_92) node _decoded_T_95 = bits(_decoded_T_89, 5, 0) node _decoded_T_96 = shl(_decoded_T_95, 2) node _decoded_T_97 = not(_decoded_T_92) node _decoded_T_98 = and(_decoded_T_96, _decoded_T_97) node _decoded_T_99 = or(_decoded_T_94, _decoded_T_98) node _decoded_T_100 = bits(_decoded_T_92, 6, 0) node _decoded_T_101 = shl(_decoded_T_100, 1) node _decoded_T_102 = xor(_decoded_T_92, _decoded_T_101) node _decoded_T_103 = shr(_decoded_T_99, 1) node _decoded_T_104 = and(_decoded_T_103, _decoded_T_102) node _decoded_T_105 = bits(_decoded_T_99, 6, 0) node _decoded_T_106 = shl(_decoded_T_105, 1) node _decoded_T_107 = not(_decoded_T_102) node _decoded_T_108 = and(_decoded_T_106, _decoded_T_107) node _decoded_T_109 = or(_decoded_T_104, _decoded_T_108) node _decoded_T_110 = bits(decoded_plaOutput_2, 11, 8) node _decoded_T_111 = bits(_decoded_T_110, 1, 0) node _decoded_T_112 = bits(_decoded_T_111, 0, 0) node _decoded_T_113 = bits(_decoded_T_111, 1, 1) node _decoded_T_114 = cat(_decoded_T_112, _decoded_T_113) node _decoded_T_115 = bits(_decoded_T_110, 3, 2) node _decoded_T_116 = bits(_decoded_T_115, 0, 0) node _decoded_T_117 = bits(_decoded_T_115, 1, 1) node _decoded_T_118 = cat(_decoded_T_116, _decoded_T_117) node _decoded_T_119 = cat(_decoded_T_114, _decoded_T_118) node decoded_2 = cat(_decoded_T_109, _decoded_T_119) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_0_2_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`0`[2], _io_resp_2_vc_sel_0_2_T node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T node _io_resp_2_vc_sel_1_2_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`1`[2], _io_resp_2_vc_sel_1_2_T node _io_resp_2_vc_sel_2_0_T = bits(decoded_2, 6, 6) connect io.resp.`2`.vc_sel.`2`[0], _io_resp_2_vc_sel_2_0_T node _io_resp_2_vc_sel_2_1_T = bits(decoded_2, 7, 7) connect io.resp.`2`.vc_sel.`2`[1], _io_resp_2_vc_sel_2_1_T node _io_resp_2_vc_sel_2_2_T = bits(decoded_2, 8, 8) connect io.resp.`2`.vc_sel.`2`[2], _io_resp_2_vc_sel_2_2_T node _io_resp_2_vc_sel_3_0_T = bits(decoded_2, 9, 9) connect io.resp.`2`.vc_sel.`3`[0], _io_resp_2_vc_sel_3_0_T node _io_resp_2_vc_sel_3_1_T = bits(decoded_2, 10, 10) connect io.resp.`2`.vc_sel.`3`[1], _io_resp_2_vc_sel_3_1_T node _io_resp_2_vc_sel_3_2_T = bits(decoded_2, 11, 11) connect io.resp.`2`.vc_sel.`3`[2], _io_resp_2_vc_sel_3_2_T connect io.resp.`2`.vc_sel.`4`[0], UInt<1>(0h0) connect io.resp.`2`.vc_sel.`5`[0], UInt<1>(0h0) connect io.req.`3`.ready, UInt<1>(0h1) node addr_lo_3 = cat(io.req.`3`.bits.flow.egress_node, io.req.`3`.bits.flow.egress_node_id) node addr_hi_hi_3 = cat(io.req.`3`.bits.flow.vnet_id, io.req.`3`.bits.flow.ingress_node) node addr_hi_3 = cat(addr_hi_hi_3, io.req.`3`.bits.flow.ingress_node_id) node _addr_T_3 = cat(addr_hi_3, addr_lo_3) node addr_3 = cat(io.req.`3`.bits.src_virt_id, _addr_T_3) wire decoded_plaInput_3 : UInt<17> node decoded_invInputs_3 = not(decoded_plaInput_3) wire decoded_plaOutput_3 : UInt<12> node decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_plaInput_3, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_invInputs_3, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_plaInput_3, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_invInputs_3, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_plaInput_3, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_invInputs_3, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_invInputs_3, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_plaInput_3, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_plaInput_3, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoded_plaInput_3, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoded_invInputs_3, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoded_invInputs_3, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_andMatrixOutputs_andMatrixInput_10_26) node decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_andMatrixOutputs_lo_lo_hi_26, decoded_andMatrixOutputs_andMatrixInput_11_26) node decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_andMatrixOutputs_andMatrixInput_7_26) node decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_andMatrixOutputs_lo_hi_hi_26, decoded_andMatrixOutputs_andMatrixInput_8_26) node decoded_andMatrixOutputs_lo_26 = cat(decoded_andMatrixOutputs_lo_hi_26, decoded_andMatrixOutputs_lo_lo_26) node decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_andMatrixOutputs_andMatrixInput_4_26) node decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_andMatrixOutputs_hi_lo_hi_26, decoded_andMatrixOutputs_andMatrixInput_5_26) node decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_andMatrixOutputs_andMatrixInput_1_28) node decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_hi_26, decoded_andMatrixOutputs_andMatrixInput_2_28) node decoded_andMatrixOutputs_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_26, decoded_andMatrixOutputs_hi_lo_26) node _decoded_andMatrixOutputs_T_28 = cat(decoded_andMatrixOutputs_hi_28, decoded_andMatrixOutputs_lo_26) node decoded_andMatrixOutputs_0_2_3 = andr(_decoded_andMatrixOutputs_T_28) node decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_plaInput_3, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_invInputs_3, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_plaInput_3, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_invInputs_3, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_plaInput_3, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_invInputs_3, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_invInputs_3, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_plaInput_3, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_plaInput_3, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoded_plaInput_3, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoded_invInputs_3, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoded_invInputs_3, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_andMatrixOutputs_andMatrixInput_10_27) node decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_andMatrixOutputs_lo_lo_hi_27, decoded_andMatrixOutputs_andMatrixInput_11_27) node decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_andMatrixOutputs_andMatrixInput_7_27) node decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_andMatrixOutputs_lo_hi_hi_27, decoded_andMatrixOutputs_andMatrixInput_8_27) node decoded_andMatrixOutputs_lo_27 = cat(decoded_andMatrixOutputs_lo_hi_27, decoded_andMatrixOutputs_lo_lo_27) node decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_andMatrixOutputs_andMatrixInput_4_27) node decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_andMatrixOutputs_hi_lo_hi_27, decoded_andMatrixOutputs_andMatrixInput_5_27) node decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_andMatrixOutputs_andMatrixInput_1_29) node decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_hi_27, decoded_andMatrixOutputs_andMatrixInput_2_29) node decoded_andMatrixOutputs_hi_29 = cat(decoded_andMatrixOutputs_hi_hi_27, decoded_andMatrixOutputs_hi_lo_27) node _decoded_andMatrixOutputs_T_29 = cat(decoded_andMatrixOutputs_hi_29, decoded_andMatrixOutputs_lo_27) node decoded_andMatrixOutputs_1_2_3 = andr(_decoded_andMatrixOutputs_T_29) node decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_invInputs_3, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_invInputs_3, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_plaInput_3, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_invInputs_3, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_invInputs_3, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_invInputs_3, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_invInputs_3, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_plaInput_3, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_plaInput_3, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoded_invInputs_3, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoded_plaInput_3, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoded_invInputs_3, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_andMatrixOutputs_andMatrixInput_10_28) node decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_andMatrixOutputs_lo_lo_hi_28, decoded_andMatrixOutputs_andMatrixInput_11_28) node decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_andMatrixOutputs_andMatrixInput_7_28) node decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_andMatrixOutputs_lo_hi_hi_28, decoded_andMatrixOutputs_andMatrixInput_8_28) node decoded_andMatrixOutputs_lo_28 = cat(decoded_andMatrixOutputs_lo_hi_28, decoded_andMatrixOutputs_lo_lo_28) node decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_andMatrixOutputs_andMatrixInput_4_28) node decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_andMatrixOutputs_hi_lo_hi_28, decoded_andMatrixOutputs_andMatrixInput_5_28) node decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_andMatrixOutputs_andMatrixInput_1_30) node decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_hi_28, decoded_andMatrixOutputs_andMatrixInput_2_30) node decoded_andMatrixOutputs_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_28, decoded_andMatrixOutputs_hi_lo_28) node _decoded_andMatrixOutputs_T_30 = cat(decoded_andMatrixOutputs_hi_30, decoded_andMatrixOutputs_lo_28) node decoded_andMatrixOutputs_2_2_2 = andr(_decoded_andMatrixOutputs_T_30) node decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_invInputs_3, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_invInputs_3, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_plaInput_3, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_invInputs_3, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_invInputs_3, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_invInputs_3, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_invInputs_3, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_plaInput_3, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_plaInput_3, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoded_invInputs_3, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoded_plaInput_3, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoded_invInputs_3, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_andMatrixOutputs_andMatrixInput_10_29) node decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_andMatrixOutputs_lo_lo_hi_29, decoded_andMatrixOutputs_andMatrixInput_11_29) node decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_andMatrixOutputs_andMatrixInput_7_29) node decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_andMatrixOutputs_lo_hi_hi_29, decoded_andMatrixOutputs_andMatrixInput_8_29) node decoded_andMatrixOutputs_lo_29 = cat(decoded_andMatrixOutputs_lo_hi_29, decoded_andMatrixOutputs_lo_lo_29) node decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_andMatrixOutputs_andMatrixInput_4_29) node decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_andMatrixOutputs_hi_lo_hi_29, decoded_andMatrixOutputs_andMatrixInput_5_29) node decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_andMatrixOutputs_andMatrixInput_1_31) node decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_andMatrixOutputs_hi_hi_hi_29, decoded_andMatrixOutputs_andMatrixInput_2_31) node decoded_andMatrixOutputs_hi_31 = cat(decoded_andMatrixOutputs_hi_hi_29, decoded_andMatrixOutputs_hi_lo_29) node _decoded_andMatrixOutputs_T_31 = cat(decoded_andMatrixOutputs_hi_31, decoded_andMatrixOutputs_lo_29) node decoded_andMatrixOutputs_3_2_2 = andr(_decoded_andMatrixOutputs_T_31) node _decoded_orMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_2_2_2, decoded_andMatrixOutputs_3_2_2) node _decoded_orMatrixOutputs_T_23 = orr(_decoded_orMatrixOutputs_T_22) node _decoded_orMatrixOutputs_T_24 = cat(decoded_andMatrixOutputs_0_2_3, decoded_andMatrixOutputs_1_2_3) node _decoded_orMatrixOutputs_T_25 = orr(_decoded_orMatrixOutputs_T_24) node decoded_orMatrixOutputs_lo_lo_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_3 = cat(decoded_orMatrixOutputs_lo_lo_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_3 = cat(decoded_orMatrixOutputs_lo_hi_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_6 = cat(decoded_orMatrixOutputs_lo_hi_3, decoded_orMatrixOutputs_lo_lo_3) node decoded_orMatrixOutputs_hi_lo_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_3 = cat(decoded_orMatrixOutputs_hi_lo_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_3 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_25) node decoded_orMatrixOutputs_hi_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_hi_3, _decoded_orMatrixOutputs_T_23) node decoded_orMatrixOutputs_hi_6 = cat(decoded_orMatrixOutputs_hi_hi_3, decoded_orMatrixOutputs_hi_lo_3) node decoded_orMatrixOutputs_3 = cat(decoded_orMatrixOutputs_hi_6, decoded_orMatrixOutputs_lo_6) node _decoded_invMatrixOutputs_T_36 = bits(decoded_orMatrixOutputs_3, 0, 0) node _decoded_invMatrixOutputs_T_37 = bits(decoded_orMatrixOutputs_3, 1, 1) node _decoded_invMatrixOutputs_T_38 = bits(decoded_orMatrixOutputs_3, 2, 2) node _decoded_invMatrixOutputs_T_39 = bits(decoded_orMatrixOutputs_3, 3, 3) node _decoded_invMatrixOutputs_T_40 = bits(decoded_orMatrixOutputs_3, 4, 4) node _decoded_invMatrixOutputs_T_41 = bits(decoded_orMatrixOutputs_3, 5, 5) node _decoded_invMatrixOutputs_T_42 = bits(decoded_orMatrixOutputs_3, 6, 6) node _decoded_invMatrixOutputs_T_43 = bits(decoded_orMatrixOutputs_3, 7, 7) node _decoded_invMatrixOutputs_T_44 = bits(decoded_orMatrixOutputs_3, 8, 8) node _decoded_invMatrixOutputs_T_45 = bits(decoded_orMatrixOutputs_3, 9, 9) node _decoded_invMatrixOutputs_T_46 = bits(decoded_orMatrixOutputs_3, 10, 10) node _decoded_invMatrixOutputs_T_47 = bits(decoded_orMatrixOutputs_3, 11, 11) node decoded_invMatrixOutputs_lo_lo_hi_3 = cat(_decoded_invMatrixOutputs_T_38, _decoded_invMatrixOutputs_T_37) node decoded_invMatrixOutputs_lo_lo_3 = cat(decoded_invMatrixOutputs_lo_lo_hi_3, _decoded_invMatrixOutputs_T_36) node decoded_invMatrixOutputs_lo_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_41, _decoded_invMatrixOutputs_T_40) node decoded_invMatrixOutputs_lo_hi_3 = cat(decoded_invMatrixOutputs_lo_hi_hi_3, _decoded_invMatrixOutputs_T_39) node decoded_invMatrixOutputs_lo_3 = cat(decoded_invMatrixOutputs_lo_hi_3, decoded_invMatrixOutputs_lo_lo_3) node decoded_invMatrixOutputs_hi_lo_hi_3 = cat(_decoded_invMatrixOutputs_T_44, _decoded_invMatrixOutputs_T_43) node decoded_invMatrixOutputs_hi_lo_3 = cat(decoded_invMatrixOutputs_hi_lo_hi_3, _decoded_invMatrixOutputs_T_42) node decoded_invMatrixOutputs_hi_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_47, _decoded_invMatrixOutputs_T_46) node decoded_invMatrixOutputs_hi_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_hi_3, _decoded_invMatrixOutputs_T_45) node decoded_invMatrixOutputs_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_3, decoded_invMatrixOutputs_hi_lo_3) node decoded_invMatrixOutputs_3 = cat(decoded_invMatrixOutputs_hi_3, decoded_invMatrixOutputs_lo_3) connect decoded_plaOutput_3, decoded_invMatrixOutputs_3 connect decoded_plaInput_3, addr_3 node _decoded_T_120 = bits(decoded_plaOutput_3, 7, 0) node _decoded_T_121 = shl(UInt<4>(0hf), 4) node _decoded_T_122 = xor(UInt<8>(0hff), _decoded_T_121) node _decoded_T_123 = shr(_decoded_T_120, 4) node _decoded_T_124 = and(_decoded_T_123, _decoded_T_122) node _decoded_T_125 = bits(_decoded_T_120, 3, 0) node _decoded_T_126 = shl(_decoded_T_125, 4) node _decoded_T_127 = not(_decoded_T_122) node _decoded_T_128 = and(_decoded_T_126, _decoded_T_127) node _decoded_T_129 = or(_decoded_T_124, _decoded_T_128) node _decoded_T_130 = bits(_decoded_T_122, 5, 0) node _decoded_T_131 = shl(_decoded_T_130, 2) node _decoded_T_132 = xor(_decoded_T_122, _decoded_T_131) node _decoded_T_133 = shr(_decoded_T_129, 2) node _decoded_T_134 = and(_decoded_T_133, _decoded_T_132) node _decoded_T_135 = bits(_decoded_T_129, 5, 0) node _decoded_T_136 = shl(_decoded_T_135, 2) node _decoded_T_137 = not(_decoded_T_132) node _decoded_T_138 = and(_decoded_T_136, _decoded_T_137) node _decoded_T_139 = or(_decoded_T_134, _decoded_T_138) node _decoded_T_140 = bits(_decoded_T_132, 6, 0) node _decoded_T_141 = shl(_decoded_T_140, 1) node _decoded_T_142 = xor(_decoded_T_132, _decoded_T_141) node _decoded_T_143 = shr(_decoded_T_139, 1) node _decoded_T_144 = and(_decoded_T_143, _decoded_T_142) node _decoded_T_145 = bits(_decoded_T_139, 6, 0) node _decoded_T_146 = shl(_decoded_T_145, 1) node _decoded_T_147 = not(_decoded_T_142) node _decoded_T_148 = and(_decoded_T_146, _decoded_T_147) node _decoded_T_149 = or(_decoded_T_144, _decoded_T_148) node _decoded_T_150 = bits(decoded_plaOutput_3, 11, 8) node _decoded_T_151 = bits(_decoded_T_150, 1, 0) node _decoded_T_152 = bits(_decoded_T_151, 0, 0) node _decoded_T_153 = bits(_decoded_T_151, 1, 1) node _decoded_T_154 = cat(_decoded_T_152, _decoded_T_153) node _decoded_T_155 = bits(_decoded_T_150, 3, 2) node _decoded_T_156 = bits(_decoded_T_155, 0, 0) node _decoded_T_157 = bits(_decoded_T_155, 1, 1) node _decoded_T_158 = cat(_decoded_T_156, _decoded_T_157) node _decoded_T_159 = cat(_decoded_T_154, _decoded_T_158) node decoded_3 = cat(_decoded_T_149, _decoded_T_159) node _io_resp_3_vc_sel_0_0_T = bits(decoded_3, 0, 0) connect io.resp.`3`.vc_sel.`0`[0], _io_resp_3_vc_sel_0_0_T node _io_resp_3_vc_sel_0_1_T = bits(decoded_3, 1, 1) connect io.resp.`3`.vc_sel.`0`[1], _io_resp_3_vc_sel_0_1_T node _io_resp_3_vc_sel_0_2_T = bits(decoded_3, 2, 2) connect io.resp.`3`.vc_sel.`0`[2], _io_resp_3_vc_sel_0_2_T node _io_resp_3_vc_sel_1_0_T = bits(decoded_3, 3, 3) connect io.resp.`3`.vc_sel.`1`[0], _io_resp_3_vc_sel_1_0_T node _io_resp_3_vc_sel_1_1_T = bits(decoded_3, 4, 4) connect io.resp.`3`.vc_sel.`1`[1], _io_resp_3_vc_sel_1_1_T node _io_resp_3_vc_sel_1_2_T = bits(decoded_3, 5, 5) connect io.resp.`3`.vc_sel.`1`[2], _io_resp_3_vc_sel_1_2_T node _io_resp_3_vc_sel_2_0_T = bits(decoded_3, 6, 6) connect io.resp.`3`.vc_sel.`2`[0], _io_resp_3_vc_sel_2_0_T node _io_resp_3_vc_sel_2_1_T = bits(decoded_3, 7, 7) connect io.resp.`3`.vc_sel.`2`[1], _io_resp_3_vc_sel_2_1_T node _io_resp_3_vc_sel_2_2_T = bits(decoded_3, 8, 8) connect io.resp.`3`.vc_sel.`2`[2], _io_resp_3_vc_sel_2_2_T node _io_resp_3_vc_sel_3_0_T = bits(decoded_3, 9, 9) connect io.resp.`3`.vc_sel.`3`[0], _io_resp_3_vc_sel_3_0_T node _io_resp_3_vc_sel_3_1_T = bits(decoded_3, 10, 10) connect io.resp.`3`.vc_sel.`3`[1], _io_resp_3_vc_sel_3_1_T node _io_resp_3_vc_sel_3_2_T = bits(decoded_3, 11, 11) connect io.resp.`3`.vc_sel.`3`[2], _io_resp_3_vc_sel_3_2_T connect io.resp.`3`.vc_sel.`4`[0], UInt<1>(0h0) connect io.resp.`3`.vc_sel.`5`[0], UInt<1>(0h0) connect io.req.`4`.ready, UInt<1>(0h1) node addr_lo_4 = cat(io.req.`4`.bits.flow.egress_node, io.req.`4`.bits.flow.egress_node_id) node addr_hi_hi_4 = cat(io.req.`4`.bits.flow.vnet_id, io.req.`4`.bits.flow.ingress_node) node addr_hi_4 = cat(addr_hi_hi_4, io.req.`4`.bits.flow.ingress_node_id) node _addr_T_4 = cat(addr_hi_4, addr_lo_4) node addr_4 = cat(io.req.`4`.bits.src_virt_id, _addr_T_4) wire decoded_plaInput_4 : UInt<17> node decoded_invInputs_4 = not(decoded_plaInput_4) wire decoded_plaOutput_4 : UInt<12> node decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_invInputs_4, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_invInputs_4, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_invInputs_4, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_invInputs_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_invInputs_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_24 = bits(decoded_invInputs_4, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_18 = bits(decoded_invInputs_4, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(decoded_invInputs_4, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_30 = cat(decoded_andMatrixOutputs_andMatrixInput_12_24, decoded_andMatrixOutputs_andMatrixInput_13_18) node decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_andMatrixOutputs_lo_lo_hi_30, decoded_andMatrixOutputs_andMatrixInput_14_6) node decoded_andMatrixOutputs_lo_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_10_30, decoded_andMatrixOutputs_andMatrixInput_11_30) node decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoded_andMatrixOutputs_andMatrixInput_8_30, decoded_andMatrixOutputs_andMatrixInput_9_30) node decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_andMatrixOutputs_lo_hi_hi_30, decoded_andMatrixOutputs_lo_hi_lo_18) node decoded_andMatrixOutputs_lo_30 = cat(decoded_andMatrixOutputs_lo_hi_30, decoded_andMatrixOutputs_lo_lo_30) node decoded_andMatrixOutputs_hi_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_andMatrixOutputs_andMatrixInput_7_30) node decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoded_andMatrixOutputs_andMatrixInput_4_30, decoded_andMatrixOutputs_andMatrixInput_5_30) node decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_andMatrixOutputs_hi_lo_hi_30, decoded_andMatrixOutputs_hi_lo_lo_6) node decoded_andMatrixOutputs_hi_hi_lo_24 = cat(decoded_andMatrixOutputs_andMatrixInput_2_32, decoded_andMatrixOutputs_andMatrixInput_3_30) node decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_andMatrixOutputs_andMatrixInput_1_32) node decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_hi_30, decoded_andMatrixOutputs_hi_hi_lo_24) node decoded_andMatrixOutputs_hi_32 = cat(decoded_andMatrixOutputs_hi_hi_30, decoded_andMatrixOutputs_hi_lo_30) node _decoded_andMatrixOutputs_T_32 = cat(decoded_andMatrixOutputs_hi_32, decoded_andMatrixOutputs_lo_30) node decoded_andMatrixOutputs_3_2_3 = andr(_decoded_andMatrixOutputs_T_32) node decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_invInputs_4, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_invInputs_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_invInputs_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_invInputs_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_invInputs_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_25 = bits(decoded_invInputs_4, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_19 = bits(decoded_invInputs_4, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(decoded_invInputs_4, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_31 = cat(decoded_andMatrixOutputs_andMatrixInput_12_25, decoded_andMatrixOutputs_andMatrixInput_13_19) node decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_andMatrixOutputs_lo_lo_hi_31, decoded_andMatrixOutputs_andMatrixInput_14_7) node decoded_andMatrixOutputs_lo_hi_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_10_31, decoded_andMatrixOutputs_andMatrixInput_11_31) node decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoded_andMatrixOutputs_andMatrixInput_8_31, decoded_andMatrixOutputs_andMatrixInput_9_31) node decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_andMatrixOutputs_lo_hi_hi_31, decoded_andMatrixOutputs_lo_hi_lo_19) node decoded_andMatrixOutputs_lo_31 = cat(decoded_andMatrixOutputs_lo_hi_31, decoded_andMatrixOutputs_lo_lo_31) node decoded_andMatrixOutputs_hi_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_andMatrixOutputs_andMatrixInput_7_31) node decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoded_andMatrixOutputs_andMatrixInput_4_31, decoded_andMatrixOutputs_andMatrixInput_5_31) node decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_andMatrixOutputs_hi_lo_hi_31, decoded_andMatrixOutputs_hi_lo_lo_7) node decoded_andMatrixOutputs_hi_hi_lo_25 = cat(decoded_andMatrixOutputs_andMatrixInput_2_33, decoded_andMatrixOutputs_andMatrixInput_3_31) node decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_andMatrixOutputs_andMatrixInput_1_33) node decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_andMatrixOutputs_hi_hi_hi_31, decoded_andMatrixOutputs_hi_hi_lo_25) node decoded_andMatrixOutputs_hi_33 = cat(decoded_andMatrixOutputs_hi_hi_31, decoded_andMatrixOutputs_hi_lo_31) node _decoded_andMatrixOutputs_T_33 = cat(decoded_andMatrixOutputs_hi_33, decoded_andMatrixOutputs_lo_31) node decoded_andMatrixOutputs_1_2_4 = andr(_decoded_andMatrixOutputs_T_33) node decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_plaInput_4, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_invInputs_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_invInputs_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_invInputs_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_invInputs_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_26 = bits(decoded_invInputs_4, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_20 = bits(decoded_invInputs_4, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(decoded_invInputs_4, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_12_26, decoded_andMatrixOutputs_andMatrixInput_13_20) node decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_andMatrixOutputs_lo_lo_hi_32, decoded_andMatrixOutputs_andMatrixInput_14_8) node decoded_andMatrixOutputs_lo_hi_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_10_32, decoded_andMatrixOutputs_andMatrixInput_11_32) node decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_8_32, decoded_andMatrixOutputs_andMatrixInput_9_32) node decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_andMatrixOutputs_lo_hi_hi_32, decoded_andMatrixOutputs_lo_hi_lo_20) node decoded_andMatrixOutputs_lo_32 = cat(decoded_andMatrixOutputs_lo_hi_32, decoded_andMatrixOutputs_lo_lo_32) node decoded_andMatrixOutputs_hi_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_andMatrixOutputs_andMatrixInput_7_32) node decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_4_32, decoded_andMatrixOutputs_andMatrixInput_5_32) node decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_andMatrixOutputs_hi_lo_hi_32, decoded_andMatrixOutputs_hi_lo_lo_8) node decoded_andMatrixOutputs_hi_hi_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_2_34, decoded_andMatrixOutputs_andMatrixInput_3_32) node decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_andMatrixOutputs_andMatrixInput_1_34) node decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_andMatrixOutputs_hi_hi_hi_32, decoded_andMatrixOutputs_hi_hi_lo_26) node decoded_andMatrixOutputs_hi_34 = cat(decoded_andMatrixOutputs_hi_hi_32, decoded_andMatrixOutputs_hi_lo_32) node _decoded_andMatrixOutputs_T_34 = cat(decoded_andMatrixOutputs_hi_34, decoded_andMatrixOutputs_lo_32) node decoded_andMatrixOutputs_0_2_4 = andr(_decoded_andMatrixOutputs_T_34) node decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_invInputs_4, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_invInputs_4, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_plaInput_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_invInputs_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(decoded_invInputs_4, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_27 = bits(decoded_invInputs_4, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_21 = bits(decoded_invInputs_4, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_11_33, decoded_andMatrixOutputs_andMatrixInput_12_27) node decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_andMatrixOutputs_lo_lo_hi_33, decoded_andMatrixOutputs_andMatrixInput_13_21) node decoded_andMatrixOutputs_lo_hi_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_andMatrixOutputs_andMatrixInput_10_33) node decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_7_33, decoded_andMatrixOutputs_andMatrixInput_8_33) node decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_andMatrixOutputs_lo_hi_hi_33, decoded_andMatrixOutputs_lo_hi_lo_21) node decoded_andMatrixOutputs_lo_33 = cat(decoded_andMatrixOutputs_lo_hi_33, decoded_andMatrixOutputs_lo_lo_33) node decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_4_33, decoded_andMatrixOutputs_andMatrixInput_5_33) node decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_andMatrixOutputs_hi_lo_hi_33, decoded_andMatrixOutputs_andMatrixInput_6_33) node decoded_andMatrixOutputs_hi_hi_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_2_35, decoded_andMatrixOutputs_andMatrixInput_3_33) node decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_andMatrixOutputs_andMatrixInput_1_35) node decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_andMatrixOutputs_hi_hi_hi_33, decoded_andMatrixOutputs_hi_hi_lo_27) node decoded_andMatrixOutputs_hi_35 = cat(decoded_andMatrixOutputs_hi_hi_33, decoded_andMatrixOutputs_hi_lo_33) node _decoded_andMatrixOutputs_T_35 = cat(decoded_andMatrixOutputs_hi_35, decoded_andMatrixOutputs_lo_33) node decoded_andMatrixOutputs_2_2_3 = andr(_decoded_andMatrixOutputs_T_35) node decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_plaInput_4, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_invInputs_4, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_plaInput_4, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_plaInput_4, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_invInputs_4, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_invInputs_4, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_invInputs_4, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_plaInput_4, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_invInputs_4, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoded_invInputs_4, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoded_plaInput_4, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(decoded_invInputs_4, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_28 = bits(decoded_invInputs_4, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_22 = bits(decoded_invInputs_4, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(decoded_invInputs_4, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_12_28, decoded_andMatrixOutputs_andMatrixInput_13_22) node decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_andMatrixOutputs_lo_lo_hi_34, decoded_andMatrixOutputs_andMatrixInput_14_9) node decoded_andMatrixOutputs_lo_hi_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_10_34, decoded_andMatrixOutputs_andMatrixInput_11_34) node decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_8_34, decoded_andMatrixOutputs_andMatrixInput_9_34) node decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_andMatrixOutputs_lo_hi_hi_34, decoded_andMatrixOutputs_lo_hi_lo_22) node decoded_andMatrixOutputs_lo_34 = cat(decoded_andMatrixOutputs_lo_hi_34, decoded_andMatrixOutputs_lo_lo_34) node decoded_andMatrixOutputs_hi_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_andMatrixOutputs_andMatrixInput_7_34) node decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_4_34, decoded_andMatrixOutputs_andMatrixInput_5_34) node decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_andMatrixOutputs_hi_lo_hi_34, decoded_andMatrixOutputs_hi_lo_lo_9) node decoded_andMatrixOutputs_hi_hi_lo_28 = cat(decoded_andMatrixOutputs_andMatrixInput_2_36, decoded_andMatrixOutputs_andMatrixInput_3_34) node decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_andMatrixOutputs_andMatrixInput_1_36) node decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_andMatrixOutputs_hi_hi_hi_34, decoded_andMatrixOutputs_hi_hi_lo_28) node decoded_andMatrixOutputs_hi_36 = cat(decoded_andMatrixOutputs_hi_hi_34, decoded_andMatrixOutputs_hi_lo_34) node _decoded_andMatrixOutputs_T_36 = cat(decoded_andMatrixOutputs_hi_36, decoded_andMatrixOutputs_lo_34) node decoded_andMatrixOutputs_4_2_2 = andr(_decoded_andMatrixOutputs_T_36) node _decoded_orMatrixOutputs_T_26 = orr(decoded_andMatrixOutputs_4_2_2) node _decoded_orMatrixOutputs_T_27 = orr(decoded_andMatrixOutputs_2_2_3) node _decoded_orMatrixOutputs_T_28 = cat(decoded_andMatrixOutputs_3_2_3, decoded_andMatrixOutputs_1_2_4) node _decoded_orMatrixOutputs_T_29 = orr(_decoded_orMatrixOutputs_T_28) node _decoded_orMatrixOutputs_T_30 = orr(decoded_andMatrixOutputs_0_2_4) node decoded_orMatrixOutputs_lo_lo_hi_4 = cat(_decoded_orMatrixOutputs_T_26, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_4 = cat(decoded_orMatrixOutputs_lo_lo_hi_4, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_4 = cat(_decoded_orMatrixOutputs_T_27, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_4 = cat(decoded_orMatrixOutputs_lo_hi_hi_4, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_7 = cat(decoded_orMatrixOutputs_lo_hi_4, decoded_orMatrixOutputs_lo_lo_4) node decoded_orMatrixOutputs_hi_lo_hi_4 = cat(_decoded_orMatrixOutputs_T_29, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_4 = cat(decoded_orMatrixOutputs_hi_lo_hi_4, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_4 = cat(_decoded_orMatrixOutputs_T_30, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_hi_4, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_4, decoded_orMatrixOutputs_hi_lo_4) node decoded_orMatrixOutputs_4 = cat(decoded_orMatrixOutputs_hi_7, decoded_orMatrixOutputs_lo_7) node _decoded_invMatrixOutputs_T_48 = bits(decoded_orMatrixOutputs_4, 0, 0) node _decoded_invMatrixOutputs_T_49 = bits(decoded_orMatrixOutputs_4, 1, 1) node _decoded_invMatrixOutputs_T_50 = bits(decoded_orMatrixOutputs_4, 2, 2) node _decoded_invMatrixOutputs_T_51 = bits(decoded_orMatrixOutputs_4, 3, 3) node _decoded_invMatrixOutputs_T_52 = bits(decoded_orMatrixOutputs_4, 4, 4) node _decoded_invMatrixOutputs_T_53 = bits(decoded_orMatrixOutputs_4, 5, 5) node _decoded_invMatrixOutputs_T_54 = bits(decoded_orMatrixOutputs_4, 6, 6) node _decoded_invMatrixOutputs_T_55 = bits(decoded_orMatrixOutputs_4, 7, 7) node _decoded_invMatrixOutputs_T_56 = bits(decoded_orMatrixOutputs_4, 8, 8) node _decoded_invMatrixOutputs_T_57 = bits(decoded_orMatrixOutputs_4, 9, 9) node _decoded_invMatrixOutputs_T_58 = bits(decoded_orMatrixOutputs_4, 10, 10) node _decoded_invMatrixOutputs_T_59 = bits(decoded_orMatrixOutputs_4, 11, 11) node decoded_invMatrixOutputs_lo_lo_hi_4 = cat(_decoded_invMatrixOutputs_T_50, _decoded_invMatrixOutputs_T_49) node decoded_invMatrixOutputs_lo_lo_4 = cat(decoded_invMatrixOutputs_lo_lo_hi_4, _decoded_invMatrixOutputs_T_48) node decoded_invMatrixOutputs_lo_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_53, _decoded_invMatrixOutputs_T_52) node decoded_invMatrixOutputs_lo_hi_4 = cat(decoded_invMatrixOutputs_lo_hi_hi_4, _decoded_invMatrixOutputs_T_51) node decoded_invMatrixOutputs_lo_4 = cat(decoded_invMatrixOutputs_lo_hi_4, decoded_invMatrixOutputs_lo_lo_4) node decoded_invMatrixOutputs_hi_lo_hi_4 = cat(_decoded_invMatrixOutputs_T_56, _decoded_invMatrixOutputs_T_55) node decoded_invMatrixOutputs_hi_lo_4 = cat(decoded_invMatrixOutputs_hi_lo_hi_4, _decoded_invMatrixOutputs_T_54) node decoded_invMatrixOutputs_hi_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_59, _decoded_invMatrixOutputs_T_58) node decoded_invMatrixOutputs_hi_hi_4 = cat(decoded_invMatrixOutputs_hi_hi_hi_4, _decoded_invMatrixOutputs_T_57) node decoded_invMatrixOutputs_hi_4 = cat(decoded_invMatrixOutputs_hi_hi_4, decoded_invMatrixOutputs_hi_lo_4) node decoded_invMatrixOutputs_4 = cat(decoded_invMatrixOutputs_hi_4, decoded_invMatrixOutputs_lo_4) connect decoded_plaOutput_4, decoded_invMatrixOutputs_4 connect decoded_plaInput_4, addr_4 node _decoded_T_160 = bits(decoded_plaOutput_4, 7, 0) node _decoded_T_161 = shl(UInt<4>(0hf), 4) node _decoded_T_162 = xor(UInt<8>(0hff), _decoded_T_161) node _decoded_T_163 = shr(_decoded_T_160, 4) node _decoded_T_164 = and(_decoded_T_163, _decoded_T_162) node _decoded_T_165 = bits(_decoded_T_160, 3, 0) node _decoded_T_166 = shl(_decoded_T_165, 4) node _decoded_T_167 = not(_decoded_T_162) node _decoded_T_168 = and(_decoded_T_166, _decoded_T_167) node _decoded_T_169 = or(_decoded_T_164, _decoded_T_168) node _decoded_T_170 = bits(_decoded_T_162, 5, 0) node _decoded_T_171 = shl(_decoded_T_170, 2) node _decoded_T_172 = xor(_decoded_T_162, _decoded_T_171) node _decoded_T_173 = shr(_decoded_T_169, 2) node _decoded_T_174 = and(_decoded_T_173, _decoded_T_172) node _decoded_T_175 = bits(_decoded_T_169, 5, 0) node _decoded_T_176 = shl(_decoded_T_175, 2) node _decoded_T_177 = not(_decoded_T_172) node _decoded_T_178 = and(_decoded_T_176, _decoded_T_177) node _decoded_T_179 = or(_decoded_T_174, _decoded_T_178) node _decoded_T_180 = bits(_decoded_T_172, 6, 0) node _decoded_T_181 = shl(_decoded_T_180, 1) node _decoded_T_182 = xor(_decoded_T_172, _decoded_T_181) node _decoded_T_183 = shr(_decoded_T_179, 1) node _decoded_T_184 = and(_decoded_T_183, _decoded_T_182) node _decoded_T_185 = bits(_decoded_T_179, 6, 0) node _decoded_T_186 = shl(_decoded_T_185, 1) node _decoded_T_187 = not(_decoded_T_182) node _decoded_T_188 = and(_decoded_T_186, _decoded_T_187) node _decoded_T_189 = or(_decoded_T_184, _decoded_T_188) node _decoded_T_190 = bits(decoded_plaOutput_4, 11, 8) node _decoded_T_191 = bits(_decoded_T_190, 1, 0) node _decoded_T_192 = bits(_decoded_T_191, 0, 0) node _decoded_T_193 = bits(_decoded_T_191, 1, 1) node _decoded_T_194 = cat(_decoded_T_192, _decoded_T_193) node _decoded_T_195 = bits(_decoded_T_190, 3, 2) node _decoded_T_196 = bits(_decoded_T_195, 0, 0) node _decoded_T_197 = bits(_decoded_T_195, 1, 1) node _decoded_T_198 = cat(_decoded_T_196, _decoded_T_197) node _decoded_T_199 = cat(_decoded_T_194, _decoded_T_198) node decoded_4 = cat(_decoded_T_189, _decoded_T_199) node _io_resp_4_vc_sel_0_0_T = bits(decoded_4, 0, 0) connect io.resp.`4`.vc_sel.`0`[0], _io_resp_4_vc_sel_0_0_T node _io_resp_4_vc_sel_0_1_T = bits(decoded_4, 1, 1) connect io.resp.`4`.vc_sel.`0`[1], _io_resp_4_vc_sel_0_1_T node _io_resp_4_vc_sel_0_2_T = bits(decoded_4, 2, 2) connect io.resp.`4`.vc_sel.`0`[2], _io_resp_4_vc_sel_0_2_T node _io_resp_4_vc_sel_1_0_T = bits(decoded_4, 3, 3) connect io.resp.`4`.vc_sel.`1`[0], _io_resp_4_vc_sel_1_0_T node _io_resp_4_vc_sel_1_1_T = bits(decoded_4, 4, 4) connect io.resp.`4`.vc_sel.`1`[1], _io_resp_4_vc_sel_1_1_T node _io_resp_4_vc_sel_1_2_T = bits(decoded_4, 5, 5) connect io.resp.`4`.vc_sel.`1`[2], _io_resp_4_vc_sel_1_2_T node _io_resp_4_vc_sel_2_0_T = bits(decoded_4, 6, 6) connect io.resp.`4`.vc_sel.`2`[0], _io_resp_4_vc_sel_2_0_T node _io_resp_4_vc_sel_2_1_T = bits(decoded_4, 7, 7) connect io.resp.`4`.vc_sel.`2`[1], _io_resp_4_vc_sel_2_1_T node _io_resp_4_vc_sel_2_2_T = bits(decoded_4, 8, 8) connect io.resp.`4`.vc_sel.`2`[2], _io_resp_4_vc_sel_2_2_T node _io_resp_4_vc_sel_3_0_T = bits(decoded_4, 9, 9) connect io.resp.`4`.vc_sel.`3`[0], _io_resp_4_vc_sel_3_0_T node _io_resp_4_vc_sel_3_1_T = bits(decoded_4, 10, 10) connect io.resp.`4`.vc_sel.`3`[1], _io_resp_4_vc_sel_3_1_T node _io_resp_4_vc_sel_3_2_T = bits(decoded_4, 11, 11) connect io.resp.`4`.vc_sel.`3`[2], _io_resp_4_vc_sel_3_2_T connect io.resp.`4`.vc_sel.`4`[0], UInt<1>(0h0) connect io.resp.`4`.vc_sel.`5`[0], UInt<1>(0h0) extmodule plusarg_reader_35 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20
module RouteComputer_9( // @[RouteComputer.scala:29:7] input [3:0] io_req_4_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_4_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_3_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_3_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_3_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_2 // @[RouteComputer.scala:40:14] ); wire [16:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id, io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [16:0] decoded_invInputs_1 = ~{io_req_1_bits_src_virt_id, io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [16:0] decoded_invInputs_2 = ~{io_req_2_bits_src_virt_id, io_req_2_bits_flow_vnet_id, io_req_2_bits_flow_ingress_node, io_req_2_bits_flow_ingress_node_id, io_req_2_bits_flow_egress_node, io_req_2_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [16:0] decoded_invInputs_3 = ~{io_req_3_bits_src_virt_id, io_req_3_bits_flow_vnet_id, io_req_3_bits_flow_ingress_node, io_req_3_bits_flow_ingress_node_id, io_req_3_bits_flow_egress_node, io_req_3_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [3:0] _GEN = ~io_req_4_bits_flow_egress_node; // @[pla.scala:78:21] wire [1:0] _GEN_0 = ~io_req_4_bits_flow_egress_node_id; // @[pla.scala:78:21] assign io_resp_4_vc_sel_3_0 = &{io_req_4_bits_flow_egress_node[0], _GEN[1], io_req_4_bits_flow_egress_node[2], io_req_4_bits_flow_egress_node[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_3_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_2_0 = &{_GEN_0[0], _GEN_0[1], io_req_4_bits_flow_egress_node[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_0 = |{&{_GEN_0[0], _GEN_0[1], _GEN[0], _GEN[1]}, &{_GEN[0], _GEN[1], _GEN[2], _GEN[3]}}; // @[pla.scala:78:21, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_0 = &{io_req_4_bits_flow_egress_node[0], _GEN[1], _GEN[2], _GEN[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_3_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_0_1 = |{&{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[5], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[2], io_req_3_bits_flow_ingress_node[3], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[14], decoded_invInputs_3[15]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[5], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[2], io_req_3_bits_flow_ingress_node[3], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[14], decoded_invInputs_3[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_2 = |{&{decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[2], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[15]}, &{decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[2], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_0 = |{&{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15]}, &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_3_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_1_0 = |{&{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[2], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15]}, &{decoded_invInputs_2[1], decoded_invInputs_2[2], decoded_invInputs_2[3], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15]}, &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[2], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[16]}, &{decoded_invInputs_2[1], decoded_invInputs_2[2], decoded_invInputs_2[3], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_1_2 = |{&{decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[15]}, &{decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_0 = |{&{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[0], decoded_invInputs_2[3], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15]}, &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[0], decoded_invInputs_2[3], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_1 = |{&{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[15]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_2 = |{&{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[15]}, &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_3_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_2_1 = |{&{io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15]}, &{io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[16]}, &{io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15]}, &{io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_2 = |{&{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[15]}, &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16]}, &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[15]}, &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_1 = |{&{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15]}, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_2 = |{&{decoded_invInputs_1[0], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[15]}, &{decoded_invInputs_1[0], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_0 = |{&{decoded_invInputs[0], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[14], decoded_invInputs[16]}}; // @[pla.scala:78:21, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_3_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_cbus_to_clint : input clock : Clock input reset : Reset output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst fragmenter of TLFragmenter_CLINT connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn connect fragmenter.auto.anon_in, tlOut connect tlIn, auto.tl_in connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready extmodule plusarg_reader_106 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_107 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLInterconnectCoupler_cbus_to_clint( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); TLFragmenter_CLINT fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_tl_in_a_ready), .auto_anon_in_a_valid (auto_tl_in_a_valid), .auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_tl_in_a_bits_param), .auto_anon_in_a_bits_size (auto_tl_in_a_bits_size), .auto_anon_in_a_bits_source (auto_tl_in_a_bits_source), .auto_anon_in_a_bits_address (auto_tl_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_tl_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_tl_in_d_ready), .auto_anon_in_d_valid (auto_tl_in_d_valid), .auto_anon_in_d_bits_opcode (auto_tl_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_tl_in_d_bits_size), .auto_anon_in_d_bits_source (auto_tl_in_d_bits_source), .auto_anon_in_d_bits_data (auto_tl_in_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready), .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid), .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode), .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size), .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source), .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data) ); // @[Fragmenter.scala:345:34] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSink_DebugInternalBundle : input clock : Clock input reset : Reset output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[8], hrmask : UInt<1>[8]}}, flip async : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[8], hrmask : UInt<1>[8]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} wire source_ready : UInt<1> connect source_ready, UInt<1>(0h1) node _ridx_T = asAsyncReset(reset) node _ridx_T_1 = and(io.deq.ready, io.deq.valid) node _ridx_T_2 = eq(source_ready, UInt<1>(0h0)) wire ridx_incremented : UInt<1> regreset ridx_ridx_bin : UInt, clock, _ridx_T, UInt<1>(0h0) connect ridx_ridx_bin, ridx_incremented node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1) node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1) node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>(0h0), _ridx_incremented_T_1) connect ridx_incremented, _ridx_incremented_T_2 node _ridx_T_3 = shr(ridx_incremented, 1) node ridx = xor(ridx_incremented, _ridx_T_3) inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w1_d3_i0_35 connect widx_widx_gray.clock, clock connect widx_widx_gray.reset, reset connect widx_widx_gray.io.d, io.async.widx wire widx : UInt<1> connect widx, widx_widx_gray.io.q node _valid_T = neq(ridx, widx) node valid = and(source_ready, _valid_T) inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w29 connect io_deq_bits_deq_bits_reg.clock, clock connect io_deq_bits_deq_bits_reg.reset, reset node io_deq_bits_deq_bits_reg_io_d_lo_lo = cat(io.async.mem[0].hrmask[1], io.async.mem[0].hrmask[0]) node io_deq_bits_deq_bits_reg_io_d_lo_hi = cat(io.async.mem[0].hrmask[3], io.async.mem[0].hrmask[2]) node io_deq_bits_deq_bits_reg_io_d_lo = cat(io_deq_bits_deq_bits_reg_io_d_lo_hi, io_deq_bits_deq_bits_reg_io_d_lo_lo) node io_deq_bits_deq_bits_reg_io_d_hi_lo = cat(io.async.mem[0].hrmask[5], io.async.mem[0].hrmask[4]) node io_deq_bits_deq_bits_reg_io_d_hi_hi = cat(io.async.mem[0].hrmask[7], io.async.mem[0].hrmask[6]) node io_deq_bits_deq_bits_reg_io_d_hi = cat(io_deq_bits_deq_bits_reg_io_d_hi_hi, io_deq_bits_deq_bits_reg_io_d_hi_lo) node _io_deq_bits_deq_bits_reg_io_d_T = cat(io_deq_bits_deq_bits_reg_io_d_hi, io_deq_bits_deq_bits_reg_io_d_lo) node io_deq_bits_deq_bits_reg_io_d_lo_lo_1 = cat(io.async.mem[0].hamask[1], io.async.mem[0].hamask[0]) node io_deq_bits_deq_bits_reg_io_d_lo_hi_1 = cat(io.async.mem[0].hamask[3], io.async.mem[0].hamask[2]) node io_deq_bits_deq_bits_reg_io_d_lo_1 = cat(io_deq_bits_deq_bits_reg_io_d_lo_hi_1, io_deq_bits_deq_bits_reg_io_d_lo_lo_1) node io_deq_bits_deq_bits_reg_io_d_hi_lo_1 = cat(io.async.mem[0].hamask[5], io.async.mem[0].hamask[4]) node io_deq_bits_deq_bits_reg_io_d_hi_hi_1 = cat(io.async.mem[0].hamask[7], io.async.mem[0].hamask[6]) node io_deq_bits_deq_bits_reg_io_d_hi_1 = cat(io_deq_bits_deq_bits_reg_io_d_hi_hi_1, io_deq_bits_deq_bits_reg_io_d_hi_lo_1) node _io_deq_bits_deq_bits_reg_io_d_T_1 = cat(io_deq_bits_deq_bits_reg_io_d_hi_1, io_deq_bits_deq_bits_reg_io_d_lo_1) node io_deq_bits_deq_bits_reg_io_d_lo_hi_2 = cat(io.async.mem[0].hasel, _io_deq_bits_deq_bits_reg_io_d_T_1) node io_deq_bits_deq_bits_reg_io_d_lo_2 = cat(io_deq_bits_deq_bits_reg_io_d_lo_hi_2, _io_deq_bits_deq_bits_reg_io_d_T) node io_deq_bits_deq_bits_reg_io_d_hi_hi_2 = cat(io.async.mem[0].resumereq, io.async.mem[0].hartsel) node io_deq_bits_deq_bits_reg_io_d_hi_2 = cat(io_deq_bits_deq_bits_reg_io_d_hi_hi_2, io.async.mem[0].ackhavereset) node _io_deq_bits_deq_bits_reg_io_d_T_2 = cat(io_deq_bits_deq_bits_reg_io_d_hi_2, io_deq_bits_deq_bits_reg_io_d_lo_2) connect io_deq_bits_deq_bits_reg.io.d, _io_deq_bits_deq_bits_reg_io_d_T_2 connect io_deq_bits_deq_bits_reg.io.en, valid wire _io_deq_bits_WIRE : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[8], hrmask : UInt<1>[8]} wire _io_deq_bits_WIRE_1 : UInt<29> connect _io_deq_bits_WIRE_1, io_deq_bits_deq_bits_reg.io.q node _io_deq_bits_T = bits(_io_deq_bits_WIRE_1, 0, 0) connect _io_deq_bits_WIRE.hrmask[0], _io_deq_bits_T node _io_deq_bits_T_1 = bits(_io_deq_bits_WIRE_1, 1, 1) connect _io_deq_bits_WIRE.hrmask[1], _io_deq_bits_T_1 node _io_deq_bits_T_2 = bits(_io_deq_bits_WIRE_1, 2, 2) connect _io_deq_bits_WIRE.hrmask[2], _io_deq_bits_T_2 node _io_deq_bits_T_3 = bits(_io_deq_bits_WIRE_1, 3, 3) connect _io_deq_bits_WIRE.hrmask[3], _io_deq_bits_T_3 node _io_deq_bits_T_4 = bits(_io_deq_bits_WIRE_1, 4, 4) connect _io_deq_bits_WIRE.hrmask[4], _io_deq_bits_T_4 node _io_deq_bits_T_5 = bits(_io_deq_bits_WIRE_1, 5, 5) connect _io_deq_bits_WIRE.hrmask[5], _io_deq_bits_T_5 node _io_deq_bits_T_6 = bits(_io_deq_bits_WIRE_1, 6, 6) connect _io_deq_bits_WIRE.hrmask[6], _io_deq_bits_T_6 node _io_deq_bits_T_7 = bits(_io_deq_bits_WIRE_1, 7, 7) connect _io_deq_bits_WIRE.hrmask[7], _io_deq_bits_T_7 node _io_deq_bits_T_8 = bits(_io_deq_bits_WIRE_1, 8, 8) connect _io_deq_bits_WIRE.hamask[0], _io_deq_bits_T_8 node _io_deq_bits_T_9 = bits(_io_deq_bits_WIRE_1, 9, 9) connect _io_deq_bits_WIRE.hamask[1], _io_deq_bits_T_9 node _io_deq_bits_T_10 = bits(_io_deq_bits_WIRE_1, 10, 10) connect _io_deq_bits_WIRE.hamask[2], _io_deq_bits_T_10 node _io_deq_bits_T_11 = bits(_io_deq_bits_WIRE_1, 11, 11) connect _io_deq_bits_WIRE.hamask[3], _io_deq_bits_T_11 node _io_deq_bits_T_12 = bits(_io_deq_bits_WIRE_1, 12, 12) connect _io_deq_bits_WIRE.hamask[4], _io_deq_bits_T_12 node _io_deq_bits_T_13 = bits(_io_deq_bits_WIRE_1, 13, 13) connect _io_deq_bits_WIRE.hamask[5], _io_deq_bits_T_13 node _io_deq_bits_T_14 = bits(_io_deq_bits_WIRE_1, 14, 14) connect _io_deq_bits_WIRE.hamask[6], _io_deq_bits_T_14 node _io_deq_bits_T_15 = bits(_io_deq_bits_WIRE_1, 15, 15) connect _io_deq_bits_WIRE.hamask[7], _io_deq_bits_T_15 node _io_deq_bits_T_16 = bits(_io_deq_bits_WIRE_1, 16, 16) connect _io_deq_bits_WIRE.hasel, _io_deq_bits_T_16 node _io_deq_bits_T_17 = bits(_io_deq_bits_WIRE_1, 17, 17) connect _io_deq_bits_WIRE.ackhavereset, _io_deq_bits_T_17 node _io_deq_bits_T_18 = bits(_io_deq_bits_WIRE_1, 27, 18) connect _io_deq_bits_WIRE.hartsel, _io_deq_bits_T_18 node _io_deq_bits_T_19 = bits(_io_deq_bits_WIRE_1, 28, 28) connect _io_deq_bits_WIRE.resumereq, _io_deq_bits_T_19 connect io.deq.bits, _io_deq_bits_WIRE node _valid_reg_T = asAsyncReset(reset) regreset valid_reg : UInt<1>, clock, _valid_reg_T, UInt<1>(0h0) connect valid_reg, valid node _io_deq_valid_T = and(valid_reg, source_ready) connect io.deq.valid, _io_deq_valid_T node _ridx_reg_T = asAsyncReset(reset) regreset ridx_gray : UInt, clock, _ridx_reg_T, UInt<1>(0h0) connect ridx_gray, ridx connect io.async.ridx, ridx_gray inst sink_valid_0 of AsyncValidSync_20 inst sink_valid_1 of AsyncValidSync_21 inst source_extend of AsyncValidSync_22 inst source_valid of AsyncValidSync_23 node _sink_valid_0_reset_T = asUInt(reset) node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1) node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2) connect sink_valid_0.reset, _sink_valid_0_reset_T_3 node _sink_valid_1_reset_T = asUInt(reset) node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1) node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2) connect sink_valid_1.reset, _sink_valid_1_reset_T_3 node _source_extend_reset_T = asUInt(reset) node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1) node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2) connect source_extend.reset, _source_extend_reset_T_3 node _source_valid_reset_T = asAsyncReset(reset) connect source_valid.reset, _source_valid_reset_T connect sink_valid_0.clock, clock connect sink_valid_1.clock, clock connect source_extend.clock, clock connect source_valid.clock, clock connect sink_valid_0.io.in, UInt<1>(0h1) connect sink_valid_1.io.in, sink_valid_0.io.out connect io.async.safe.ridx_valid, sink_valid_1.io.out connect source_extend.io.in, io.async.safe.widx_valid connect source_valid.io.in, source_extend.io.out connect source_ready, source_valid.io.out node _io_async_safe_sink_reset_n_T = asUInt(reset) node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>(0h0)) connect io.async.safe.sink_reset_n, _io_async_safe_sink_reset_n_T_1
module AsyncQueueSink_DebugInternalBundle( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] output io_deq_valid, // @[AsyncQueue.scala:139:14] output io_deq_bits_resumereq, // @[AsyncQueue.scala:139:14] output [9:0] io_deq_bits_hartsel, // @[AsyncQueue.scala:139:14] output io_deq_bits_ackhavereset, // @[AsyncQueue.scala:139:14] output io_deq_bits_hasel, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_0, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_1, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_2, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_3, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_4, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_5, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_6, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_7, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_0, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_1, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_2, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_3, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_4, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_5, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_6, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_7, // @[AsyncQueue.scala:139:14] input io_async_mem_0_resumereq, // @[AsyncQueue.scala:139:14] input [9:0] io_async_mem_0_hartsel, // @[AsyncQueue.scala:139:14] input io_async_mem_0_ackhavereset, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hasel, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_0, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_1, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_2, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_3, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_4, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_5, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_6, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_7, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_0, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_1, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_2, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_3, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_4, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_5, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_6, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_7, // @[AsyncQueue.scala:139:14] output io_async_ridx, // @[AsyncQueue.scala:139:14] input io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire io_deq_valid_0; // @[AsyncQueue.scala:166:29] wire _source_valid_io_out; // @[AsyncQueue.scala:176:31] wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire [28:0] _io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala:207:25] wire _widx_widx_gray_io_q; // @[ShiftReg.scala:45:23] reg ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire ridx = _source_valid_io_out & ridx_ridx_bin + io_deq_valid_0; // @[AsyncQueue.scala:52:25, :53:{23,43}, :166:29, :176:31] wire valid = _source_valid_io_out & ridx != _widx_widx_gray_io_q; // @[ShiftReg.scala:45:23] reg valid_reg; // @[AsyncQueue.scala:165:56] assign io_deq_valid_0 = valid_reg & _source_valid_io_out; // @[AsyncQueue.scala:165:56, :166:29, :176:31] reg ridx_gray; // @[AsyncQueue.scala:168:55] always @(posedge clock or posedge reset) begin // @[AsyncQueue.scala:136:7] if (reset) begin // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= 1'h0; // @[AsyncQueue.scala:52:25, :136:7] valid_reg <= 1'h0; // @[AsyncQueue.scala:136:7, :165:56] ridx_gray <= 1'h0; // @[AsyncQueue.scala:136:7, :168:55] end else begin // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx; // @[AsyncQueue.scala:52:25, :53:23] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] ridx_gray <= ridx; // @[AsyncQueue.scala:53:23, :168:55] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_171 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_192 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_171( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_192 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ResetCatchAndSync_d3_3 : input clock : Clock input reset : Reset output io : { sync_reset : UInt<1>, flip psd : { test_mode : UInt<1>, test_mode_reset : UInt<1>}} node _post_psd_reset_T = asUInt(reset) node post_psd_reset = mux(io.psd.test_mode, io.psd.test_mode_reset, _post_psd_reset_T) inst io_sync_reset_chain of AsyncResetSynchronizerShiftReg_w1_d3_i0_119 connect io_sync_reset_chain.clock, clock connect io_sync_reset_chain.reset, post_psd_reset connect io_sync_reset_chain.io.d, UInt<1>(0h1) wire _io_sync_reset_WIRE : UInt<1> connect _io_sync_reset_WIRE, io_sync_reset_chain.io.q node _io_sync_reset_T = not(_io_sync_reset_WIRE) node _io_sync_reset_T_1 = mux(io.psd.test_mode, io.psd.test_mode_reset, _io_sync_reset_T) connect io.sync_reset, _io_sync_reset_T_1
module ResetCatchAndSync_d3_3( // @[ResetCatchAndSync.scala:13:7] input clock, // @[ResetCatchAndSync.scala:13:7] input reset, // @[ResetCatchAndSync.scala:13:7] output io_sync_reset // @[ResetCatchAndSync.scala:17:14] ); wire _post_psd_reset_T = reset; // @[ResetCatchAndSync.scala:26:76] wire io_psd_test_mode = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14] wire io_psd_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14] wire _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:28:25] wire io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7] wire post_psd_reset = _post_psd_reset_T; // @[ResetCatchAndSync.scala:26:{27,76}] wire _io_sync_reset_WIRE; // @[ShiftReg.scala:48:24] wire _io_sync_reset_T = ~_io_sync_reset_WIRE; // @[ShiftReg.scala:48:24] assign _io_sync_reset_T_1 = _io_sync_reset_T; // @[ResetCatchAndSync.scala:28:25, :29:7] assign io_sync_reset_0 = _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:13:7, :28:25] AsyncResetSynchronizerShiftReg_w1_d3_i0_119 io_sync_reset_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (post_psd_reset), // @[ResetCatchAndSync.scala:26:27] .io_q (_io_sync_reset_WIRE) ); // @[ShiftReg.scala:45:23] assign io_sync_reset = io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_46 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1) node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2) node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3) node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) node _T_7 = or(_T_6, prs1_wakeups_2) node _T_8 = or(_T_7, prs1_wakeups_3) when _T_8 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_4 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T_4, _next_uop_iw_p1_speculative_child_T_2) node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_3) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<2> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_6 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_4 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T_4, _next_uop_iw_p1_bypass_hint_T_2) node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_3) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_6 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_9 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_10 = or(_T_9, prs1_rebusys_2) node _T_11 = or(_T_10, prs1_rebusys_3) node _T_12 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_13 = neq(_T_12, UInt<1>(0h0)) node _T_14 = or(_T_11, _T_13) node _T_15 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_16 = and(_T_14, _T_15) when _T_16 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_17 = or(prs2_wakeups_0, prs2_wakeups_1) node _T_18 = or(_T_17, prs2_wakeups_2) node _T_19 = or(_T_18, prs2_wakeups_3) when _T_19 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_4 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T_4, _next_uop_iw_p2_speculative_child_T_2) node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_3) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<2> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_6 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_4 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T_4, _next_uop_iw_p2_bypass_hint_T_2) node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_3) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_6 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_20 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_21 = or(_T_20, prs2_rebusys_2) node _T_22 = or(_T_21, prs2_rebusys_3) node _T_23 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_24 = neq(_T_23, UInt<1>(0h0)) node _T_25 = or(_T_22, _T_24) node _T_26 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_27 = and(_T_25, _T_26) when _T_27 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_28 = or(prs3_wakeups_0, prs3_wakeups_1) node _T_29 = or(_T_28, prs3_wakeups_2) node _T_30 = or(_T_29, prs3_wakeups_3) when _T_30 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_4 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T_4, _next_uop_iw_p3_bypass_hint_T_2) node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_3) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_6 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_31 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_32 = and(io.pred_wakeup_port.valid, _T_31) when _T_32 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_33 = eq(io.squash_grant, UInt<1>(0h0)) node _T_34 = and(io.grant, _T_33) when _T_34 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_35 = and(slot_valid, slot_uop.iw_issued) when _T_35 : connect next_valid, rebusied
module IssueSlot_46( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [1:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7] wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module FSECompressorEncoder : input clock : Clock input reset : Reset output io : { flip src_stream : { flip user_consumed_bytes : UInt<6>, available_output_bytes : UInt<6>, output_valid : UInt<1>, flip output_ready : UInt<1>, output_data : UInt<256>, output_last_chunk : UInt<1>}, flip table_log : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<4>}, symbol_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { symbol : UInt<8>, last_symbol : UInt<1>}}[2], flip comp_trans_table : { flip ready : UInt<1>, valid : UInt<1>, bits : { nbbit : UInt<32>, findstate : UInt<32>, from_last_symbol : UInt<1>}}[2], state_table_idx : UInt<16>[2], flip new_state : { valid : UInt<1>, bits : UInt<16>}[2], memwrites_out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>, validbytes : UInt<6>, end_of_message : UInt<1>}}, flip header_writes : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>, validbytes : UInt<6>, end_of_message : UInt<1>}}, lookup_done : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}} inst lookup_symbol_cnt_q of Queue10_UInt2 connect lookup_symbol_cnt_q.clock, clock connect lookup_symbol_cnt_q.reset, reset wire _initCStateDone_WIRE : UInt<1>[2] connect _initCStateDone_WIRE[0], UInt<1>(0h0) connect _initCStateDone_WIRE[1], UInt<1>(0h0) regreset initCStateDone : UInt<1>[2], clock, reset, _initCStateDone_WIRE wire _statePtr_value_WIRE : UInt<16>[2] connect _statePtr_value_WIRE[0], UInt<16>(0h0) connect _statePtr_value_WIRE[1], UInt<16>(0h0) regreset statePtr_value : UInt<16>[2], clock, reset, _statePtr_value_WIRE wire _symbols_WIRE : UInt<8>[2] connect _symbols_WIRE[0], UInt<8>(0h0) connect _symbols_WIRE[1], UInt<8>(0h0) wire symbols : UInt<8>[2] connect symbols, _symbols_WIRE node _symbols_0_T = dshr(io.src_stream.output_data, UInt<8>(0hf8)) connect symbols[0], _symbols_0_T node _symbols_1_T = dshr(io.src_stream.output_data, UInt<8>(0hf0)) connect symbols[1], _symbols_1_T node _T = and(io.src_stream.output_valid, io.src_stream.output_ready) when _T : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "FSE_ENCODER consumed input stream\n") : printf_1 regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "fse_encoder_symbols(%d): %d\n", UInt<1>(0h0), symbols[0]) : printf_3 regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "fse_encoder_symbols(%d): %d\n", UInt<1>(0h1), symbols[1]) : printf_5 inst symbol_info_q_0 of Queue10_FSESymbolInfo connect symbol_info_q_0.clock, clock connect symbol_info_q_0.reset, reset inst symbol_info_q_1 of Queue10_FSESymbolInfo_1 connect symbol_info_q_1.clock, clock connect symbol_info_q_1.reset, reset inst comp_trans_table_q_0 of Queue10_FSECompTransformationTable connect comp_trans_table_q_0.clock, clock connect comp_trans_table_q_0.reset, reset inst comp_trans_table_q_1 of Queue10_FSECompTransformationTable_1 connect comp_trans_table_q_1.clock, clock connect comp_trans_table_q_1.reset, reset connect io.symbol_info[0].bits, symbol_info_q_0.io.deq.bits connect io.symbol_info[0].valid, symbol_info_q_0.io.deq.valid connect symbol_info_q_0.io.deq.ready, io.symbol_info[0].ready connect comp_trans_table_q_0.io.enq, io.comp_trans_table[0] connect io.symbol_info[1].bits, symbol_info_q_1.io.deq.bits connect io.symbol_info[1].valid, symbol_info_q_1.io.deq.valid connect symbol_info_q_1.io.deq.ready, io.symbol_info[1].ready connect comp_trans_table_q_1.io.enq, io.comp_trans_table[1] node all_io_symbol_info_ready = or(symbol_info_q_0.io.enq.ready, symbol_info_q_1.io.enq.ready) node _consumed_bytes_T = gt(UInt<2>(0h2), io.src_stream.available_output_bytes) node consumed_bytes = mux(_consumed_bytes_T, io.src_stream.available_output_bytes, UInt<2>(0h2)) node _lookup_symbol_cnt_q_io_enq_valid_T = and(io.src_stream.output_valid, all_io_symbol_info_ready) connect lookup_symbol_cnt_q.io.enq.valid, _lookup_symbol_cnt_q_io_enq_valid_T connect lookup_symbol_cnt_q.io.enq.bits, consumed_bytes node _io_src_stream_output_ready_T = and(lookup_symbol_cnt_q.io.enq.ready, all_io_symbol_info_ready) connect io.src_stream.output_ready, _io_src_stream_output_ready_T connect io.src_stream.user_consumed_bytes, consumed_bytes regreset track_consumed_bytes : UInt<64>, clock, reset, UInt<64>(0h0) node _T_13 = and(io.src_stream.output_valid, io.src_stream.output_ready) when _T_13 : node _track_consumed_bytes_T = add(track_consumed_bytes, consumed_bytes) node _track_consumed_bytes_T_1 = tail(_track_consumed_bytes_T, 1) connect track_consumed_bytes, _track_consumed_bytes_T_1 regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6 node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "FSE_ENCODER track_consumed_bytes: %d\n", track_consumed_bytes) : printf_7 node _track_consumed_bytes_odd_T = bits(track_consumed_bytes, 0, 0) node track_consumed_bytes_odd = neq(_track_consumed_bytes_odd_T, UInt<1>(0h0)) node use_this_queue = lt(UInt<1>(0h0), consumed_bytes) node _symbol_info_q_0_io_enq_valid_T = and(lookup_symbol_cnt_q.io.enq.ready, io.src_stream.output_valid) node _symbol_info_q_0_io_enq_valid_T_1 = and(_symbol_info_q_0_io_enq_valid_T, use_this_queue) connect symbol_info_q_0.io.enq.valid, _symbol_info_q_0_io_enq_valid_T_1 connect symbol_info_q_0.io.enq.bits.symbol, symbols[0] node _symbol_info_q_0_io_enq_bits_last_symbol_T = sub(io.src_stream.available_output_bytes, UInt<1>(0h1)) node _symbol_info_q_0_io_enq_bits_last_symbol_T_1 = tail(_symbol_info_q_0_io_enq_bits_last_symbol_T, 1) node _symbol_info_q_0_io_enq_bits_last_symbol_T_2 = eq(UInt<1>(0h0), _symbol_info_q_0_io_enq_bits_last_symbol_T_1) node _symbol_info_q_0_io_enq_bits_last_symbol_T_3 = and(_symbol_info_q_0_io_enq_bits_last_symbol_T_2, io.src_stream.output_last_chunk) connect symbol_info_q_0.io.enq.bits.last_symbol, _symbol_info_q_0_io_enq_bits_last_symbol_T_3 node use_this_queue_1 = lt(UInt<1>(0h1), consumed_bytes) node _symbol_info_q_1_io_enq_valid_T = and(lookup_symbol_cnt_q.io.enq.ready, io.src_stream.output_valid) node _symbol_info_q_1_io_enq_valid_T_1 = and(_symbol_info_q_1_io_enq_valid_T, use_this_queue_1) connect symbol_info_q_1.io.enq.valid, _symbol_info_q_1_io_enq_valid_T_1 connect symbol_info_q_1.io.enq.bits.symbol, symbols[1] node _symbol_info_q_1_io_enq_bits_last_symbol_T = sub(io.src_stream.available_output_bytes, UInt<1>(0h1)) node _symbol_info_q_1_io_enq_bits_last_symbol_T_1 = tail(_symbol_info_q_1_io_enq_bits_last_symbol_T, 1) node _symbol_info_q_1_io_enq_bits_last_symbol_T_2 = eq(UInt<1>(0h1), _symbol_info_q_1_io_enq_bits_last_symbol_T_1) node _symbol_info_q_1_io_enq_bits_last_symbol_T_3 = and(_symbol_info_q_1_io_enq_bits_last_symbol_T_2, io.src_stream.output_last_chunk) connect symbol_info_q_1.io.enq.bits.last_symbol, _symbol_info_q_1_io_enq_bits_last_symbol_T_3 regreset input_symbol_cnt : UInt<64>, clock, reset, UInt<64>(0h0) node _T_18 = and(io.src_stream.output_valid, io.src_stream.output_ready) when _T_18 : node _input_symbol_cnt_T = add(input_symbol_cnt, consumed_bytes) node _input_symbol_cnt_T_1 = tail(_input_symbol_cnt_T, 1) connect input_symbol_cnt, _input_symbol_cnt_T_1 regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8 node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "FSE_ENCODER_INPUT_BYTES\n") : printf_9 node _T_23 = lt(UInt<1>(0h0), consumed_bytes) when _T_23 : node _T_24 = add(input_symbol_cnt, UInt<1>(0h0)) node _T_25 = tail(_T_24, 1) regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10 node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "fse_symbol(%d): %d\n", _T_25, symbols[0]) : printf_11 node _T_30 = lt(UInt<1>(0h1), consumed_bytes) when _T_30 : node _T_31 = add(input_symbol_cnt, UInt<1>(0h1)) node _T_32 = tail(_T_31, 1) regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _T_33 = asUInt(reset) node _T_34 = eq(_T_33, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12 node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "fse_symbol(%d): %d\n", _T_32, symbols[1]) : printf_13 regreset flush : UInt<1>, clock, reset, UInt<1>(0h0) wire _nbBitsOut_WIRE : UInt<32>[2] connect _nbBitsOut_WIRE[0], UInt<32>(0h0) connect _nbBitsOut_WIRE[1], UInt<32>(0h0) wire nbBitsOut : UInt<32>[2] connect nbBitsOut, _nbBitsOut_WIRE wire _deltaNbBits_WIRE : UInt<32>[2] connect _deltaNbBits_WIRE[0], UInt<32>(0h0) connect _deltaNbBits_WIRE[1], UInt<32>(0h0) wire deltaNbBits : UInt<32>[2] connect deltaNbBits, _deltaNbBits_WIRE wire _deltaFindState_WIRE : UInt<32>[2] connect _deltaFindState_WIRE[0], UInt<32>(0h0) connect _deltaFindState_WIRE[1], UInt<32>(0h0) wire deltaFindState : UInt<32>[2] connect deltaFindState, _deltaFindState_WIRE wire _statePtr_value_to_shift_WIRE : UInt<16>[2] connect _statePtr_value_to_shift_WIRE[0], UInt<16>(0h0) connect _statePtr_value_to_shift_WIRE[1], UInt<16>(0h0) wire statePtr_value_to_shift : UInt<16>[2] connect statePtr_value_to_shift, _statePtr_value_to_shift_WIRE connect deltaNbBits[0], comp_trans_table_q_0.io.deq.bits.nbbit connect deltaFindState[0], comp_trans_table_q_0.io.deq.bits.findstate node _nbBitsOut_0_T = eq(initCStateDone[0], UInt<1>(0h0)) node _nbBitsOut_0_T_1 = add(deltaNbBits[0], UInt<16>(0h8000)) node _nbBitsOut_0_T_2 = tail(_nbBitsOut_0_T_1, 1) node _nbBitsOut_0_T_3 = dshr(_nbBitsOut_0_T_2, UInt<5>(0h10)) node _nbBitsOut_0_T_4 = add(statePtr_value[0], deltaNbBits[0]) node _nbBitsOut_0_T_5 = tail(_nbBitsOut_0_T_4, 1) node _nbBitsOut_0_T_6 = dshr(_nbBitsOut_0_T_5, UInt<5>(0h10)) node _nbBitsOut_0_T_7 = mux(_nbBitsOut_0_T, _nbBitsOut_0_T_3, _nbBitsOut_0_T_6) node _nbBitsOut_0_T_8 = mux(flush, io.table_log.bits, _nbBitsOut_0_T_7) connect nbBitsOut[0], _nbBitsOut_0_T_8 node _statePtr_value_to_shift_0_T = eq(initCStateDone[0], UInt<1>(0h0)) node _statePtr_value_to_shift_0_T_1 = dshl(nbBitsOut[0], UInt<5>(0h10)) node _statePtr_value_to_shift_0_T_2 = sub(_statePtr_value_to_shift_0_T_1, deltaNbBits[0]) node _statePtr_value_to_shift_0_T_3 = tail(_statePtr_value_to_shift_0_T_2, 1) node _statePtr_value_to_shift_0_T_4 = mux(_statePtr_value_to_shift_0_T, _statePtr_value_to_shift_0_T_3, statePtr_value[0]) connect statePtr_value_to_shift[0], _statePtr_value_to_shift_0_T_4 node _io_state_table_idx_0_T = dshr(statePtr_value_to_shift[0], nbBitsOut[0]) node _io_state_table_idx_0_T_1 = asSInt(_io_state_table_idx_0_T) node _io_state_table_idx_0_T_2 = asSInt(deltaFindState[0]) node _io_state_table_idx_0_T_3 = add(_io_state_table_idx_0_T_1, _io_state_table_idx_0_T_2) node _io_state_table_idx_0_T_4 = tail(_io_state_table_idx_0_T_3, 1) node _io_state_table_idx_0_T_5 = asSInt(_io_state_table_idx_0_T_4) node _io_state_table_idx_0_T_6 = asUInt(_io_state_table_idx_0_T_5) connect io.state_table_idx[0], _io_state_table_idx_0_T_6 connect deltaNbBits[1], comp_trans_table_q_1.io.deq.bits.nbbit connect deltaFindState[1], comp_trans_table_q_1.io.deq.bits.findstate node _nbBitsOut_1_T = eq(initCStateDone[1], UInt<1>(0h0)) node _nbBitsOut_1_T_1 = add(deltaNbBits[1], UInt<16>(0h8000)) node _nbBitsOut_1_T_2 = tail(_nbBitsOut_1_T_1, 1) node _nbBitsOut_1_T_3 = dshr(_nbBitsOut_1_T_2, UInt<5>(0h10)) node _nbBitsOut_1_T_4 = add(statePtr_value[1], deltaNbBits[1]) node _nbBitsOut_1_T_5 = tail(_nbBitsOut_1_T_4, 1) node _nbBitsOut_1_T_6 = dshr(_nbBitsOut_1_T_5, UInt<5>(0h10)) node _nbBitsOut_1_T_7 = mux(_nbBitsOut_1_T, _nbBitsOut_1_T_3, _nbBitsOut_1_T_6) node _nbBitsOut_1_T_8 = mux(flush, io.table_log.bits, _nbBitsOut_1_T_7) connect nbBitsOut[1], _nbBitsOut_1_T_8 node _statePtr_value_to_shift_1_T = eq(initCStateDone[1], UInt<1>(0h0)) node _statePtr_value_to_shift_1_T_1 = dshl(nbBitsOut[1], UInt<5>(0h10)) node _statePtr_value_to_shift_1_T_2 = sub(_statePtr_value_to_shift_1_T_1, deltaNbBits[1]) node _statePtr_value_to_shift_1_T_3 = tail(_statePtr_value_to_shift_1_T_2, 1) node _statePtr_value_to_shift_1_T_4 = mux(_statePtr_value_to_shift_1_T, _statePtr_value_to_shift_1_T_3, statePtr_value[1]) connect statePtr_value_to_shift[1], _statePtr_value_to_shift_1_T_4 node _io_state_table_idx_1_T = dshr(statePtr_value_to_shift[1], nbBitsOut[1]) node _io_state_table_idx_1_T_1 = asSInt(_io_state_table_idx_1_T) node _io_state_table_idx_1_T_2 = asSInt(deltaFindState[1]) node _io_state_table_idx_1_T_3 = add(_io_state_table_idx_1_T_1, _io_state_table_idx_1_T_2) node _io_state_table_idx_1_T_4 = tail(_io_state_table_idx_1_T_3, 1) node _io_state_table_idx_1_T_5 = asSInt(_io_state_table_idx_1_T_4) node _io_state_table_idx_1_T_6 = asUInt(_io_state_table_idx_1_T_5) connect io.state_table_idx[1], _io_state_table_idx_1_T_6 node _comp_trans_table_last_symbols_T = and(comp_trans_table_q_0.io.deq.bits.from_last_symbol, comp_trans_table_q_0.io.deq.valid) node _comp_trans_table_last_symbols_T_1 = and(comp_trans_table_q_1.io.deq.bits.from_last_symbol, comp_trans_table_q_1.io.deq.valid) node comp_trans_table_last_symbols = or(_comp_trans_table_last_symbols_T, _comp_trans_table_last_symbols_T_1) node comp_trans_table_all_valid = and(comp_trans_table_q_0.io.deq.valid, comp_trans_table_q_1.io.deq.valid) node comp_trans_table_valid = or(comp_trans_table_last_symbols, comp_trans_table_all_valid) wire all_new_state_valid_can_be_invalid : UInt<1> connect all_new_state_valid_can_be_invalid, UInt<1>(0h0) node _all_new_state_valid_T = lt(UInt<1>(0h0), lookup_symbol_cnt_q.io.deq.bits) when _all_new_state_valid_T : connect all_new_state_valid_can_be_invalid, io.new_state[0].valid else : connect all_new_state_valid_can_be_invalid, UInt<1>(0h1) wire all_new_state_valid_can_be_invalid_1 : UInt<1> connect all_new_state_valid_can_be_invalid_1, UInt<1>(0h0) node _all_new_state_valid_T_1 = lt(UInt<1>(0h1), lookup_symbol_cnt_q.io.deq.bits) when _all_new_state_valid_T_1 : connect all_new_state_valid_can_be_invalid_1, io.new_state[1].valid else : connect all_new_state_valid_can_be_invalid_1, UInt<1>(0h1) node all_new_state_valid = and(all_new_state_valid_can_be_invalid, all_new_state_valid_can_be_invalid_1) inst comp_bits_buff of CompressedBitsBuff connect comp_bits_buff.clock, clock connect comp_bits_buff.reset, reset node _lookup_symbol_cnt_q_io_deq_ready_T = and(comp_trans_table_valid, all_new_state_valid) node _lookup_symbol_cnt_q_io_deq_ready_T_1 = and(_lookup_symbol_cnt_q_io_deq_ready_T, comp_bits_buff.io.writes_in.ready) connect lookup_symbol_cnt_q.io.deq.ready, _lookup_symbol_cnt_q_io_deq_ready_T_1 node _comp_trans_table_q_0_io_deq_ready_T = and(lookup_symbol_cnt_q.io.deq.valid, all_new_state_valid) node _comp_trans_table_q_0_io_deq_ready_T_1 = and(_comp_trans_table_q_0_io_deq_ready_T, comp_bits_buff.io.writes_in.ready) connect comp_trans_table_q_0.io.deq.ready, _comp_trans_table_q_0_io_deq_ready_T_1 node _comp_trans_table_q_1_io_deq_ready_T = and(lookup_symbol_cnt_q.io.deq.valid, all_new_state_valid) node _comp_trans_table_q_1_io_deq_ready_T_1 = and(_comp_trans_table_q_1_io_deq_ready_T, comp_bits_buff.io.writes_in.ready) connect comp_trans_table_q_1.io.deq.ready, _comp_trans_table_q_1_io_deq_ready_T_1 node valid_new_state = lt(UInt<1>(0h0), lookup_symbol_cnt_q.io.deq.bits) node _statePtr_value_0_T = and(lookup_symbol_cnt_q.io.deq.valid, comp_trans_table_valid) node _statePtr_value_0_T_1 = and(_statePtr_value_0_T, all_new_state_valid) node _statePtr_value_0_T_2 = and(_statePtr_value_0_T_1, comp_bits_buff.io.writes_in.ready) node _statePtr_value_0_T_3 = and(valid_new_state, _statePtr_value_0_T_2) node _statePtr_value_0_T_4 = mux(_statePtr_value_0_T_3, io.new_state[0].bits, statePtr_value[0]) connect statePtr_value[0], _statePtr_value_0_T_4 node valid_new_state_1 = lt(UInt<1>(0h1), lookup_symbol_cnt_q.io.deq.bits) node _statePtr_value_1_T = and(lookup_symbol_cnt_q.io.deq.valid, comp_trans_table_valid) node _statePtr_value_1_T_1 = and(_statePtr_value_1_T, all_new_state_valid) node _statePtr_value_1_T_2 = and(_statePtr_value_1_T_1, comp_bits_buff.io.writes_in.ready) node _statePtr_value_1_T_3 = and(valid_new_state_1, _statePtr_value_1_T_2) node _statePtr_value_1_T_4 = mux(_statePtr_value_1_T_3, io.new_state[1].bits, statePtr_value[1]) connect statePtr_value[1], _statePtr_value_1_T_4 node _T_37 = and(lookup_symbol_cnt_q.io.deq.valid, comp_trans_table_valid) node _T_38 = and(_T_37, all_new_state_valid) node _T_39 = and(_T_38, comp_bits_buff.io.writes_in.ready) node _T_40 = lt(UInt<1>(0h0), lookup_symbol_cnt_q.io.deq.bits) node _T_41 = and(_T_39, _T_40) node _T_42 = eq(initCStateDone[0], UInt<1>(0h0)) node _T_43 = and(_T_41, _T_42) when _T_43 : connect initCStateDone[0], UInt<1>(0h1) node _T_44 = and(lookup_symbol_cnt_q.io.deq.valid, comp_trans_table_valid) node _T_45 = and(_T_44, all_new_state_valid) node _T_46 = and(_T_45, comp_bits_buff.io.writes_in.ready) node _T_47 = lt(UInt<1>(0h1), lookup_symbol_cnt_q.io.deq.bits) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(initCStateDone[1], UInt<1>(0h0)) node _T_50 = and(_T_48, _T_49) when _T_50 : connect initCStateDone[1], UInt<1>(0h1) node _io_lookup_done_valid_T = and(io.table_log.valid, flush) node _io_lookup_done_valid_T_1 = and(_io_lookup_done_valid_T, io.lookup_done.ready) node _io_lookup_done_valid_T_2 = and(_io_lookup_done_valid_T_1, comp_bits_buff.io.writes_in.ready) reg io_lookup_done_valid_REG : UInt<1>, clock connect io_lookup_done_valid_REG, _io_lookup_done_valid_T_2 connect io.lookup_done.valid, io_lookup_done_valid_REG connect io.lookup_done.bits, UInt<1>(0h1) node _io_table_log_ready_T = and(flush, io.lookup_done.ready) node _io_table_log_ready_T_1 = and(_io_table_log_ready_T, comp_bits_buff.io.writes_in.ready) connect io.table_log.ready, _io_table_log_ready_T_1 node _T_51 = and(lookup_symbol_cnt_q.io.deq.valid, comp_trans_table_valid) node _T_52 = and(_T_51, all_new_state_valid) node _T_53 = and(_T_52, comp_bits_buff.io.writes_in.ready) node _T_54 = and(_T_53, comp_trans_table_last_symbols) when _T_54 : connect flush, UInt<1>(0h1) node _T_55 = and(io.table_log.valid, flush) node _T_56 = and(_T_55, io.lookup_done.ready) node _T_57 = and(_T_56, comp_bits_buff.io.writes_in.ready) when _T_57 : connect flush, UInt<1>(0h0) connect statePtr_value[0], UInt<1>(0h0) connect initCStateDone[0], UInt<1>(0h0) connect statePtr_value[1], UInt<1>(0h0) connect initCStateDone[1], UInt<1>(0h0) connect track_consumed_bytes, UInt<1>(0h0) node _T_58 = and(lookup_symbol_cnt_q.io.deq.valid, comp_trans_table_valid) node _T_59 = and(_T_58, all_new_state_valid) node _T_60 = and(_T_59, comp_bits_buff.io.writes_in.ready) node _T_61 = and(io.table_log.valid, flush) node _T_62 = and(_T_61, io.lookup_done.ready) node _T_63 = and(_T_62, comp_bits_buff.io.writes_in.ready) node _T_64 = or(_T_60, _T_63) when _T_64 : regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14 node _T_67 = asUInt(reset) node _T_68 = eq(_T_67, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "new_state_value: %d\n", statePtr_value[0]) : printf_15 regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16 node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "new_state_value: %d\n", statePtr_value[1]) : printf_17 regreset add_padding : UInt<1>, clock, reset, UInt<1>(0h0) node _T_73 = and(io.table_log.valid, flush) node _T_74 = and(_T_73, io.lookup_done.ready) node _T_75 = and(_T_74, comp_bits_buff.io.writes_in.ready) when _T_75 : connect add_padding, UInt<1>(0h1) node _T_76 = and(comp_bits_buff.io.writes_in.ready, add_padding) when _T_76 : connect add_padding, UInt<1>(0h0) wire _cumul_nbBitsOut_WIRE : UInt<32>[2] connect _cumul_nbBitsOut_WIRE[0], UInt<32>(0h0) connect _cumul_nbBitsOut_WIRE[1], UInt<32>(0h0) wire cumul_nbBitsOut : UInt<32>[2] connect cumul_nbBitsOut, _cumul_nbBitsOut_WIRE connect cumul_nbBitsOut[0], nbBitsOut[0] node _valid_bits_T = lt(UInt<1>(0h1), lookup_symbol_cnt_q.io.deq.bits) node _valid_bits_T_1 = mux(_valid_bits_T, nbBitsOut[1], UInt<1>(0h0)) node valid_bits = mux(flush, nbBitsOut[1], _valid_bits_T_1) node _cumul_nbBitsOut_1_T = add(cumul_nbBitsOut[0], valid_bits) node _cumul_nbBitsOut_1_T_1 = tail(_cumul_nbBitsOut_1_T, 1) connect cumul_nbBitsOut[1], _cumul_nbBitsOut_1_T_1 wire _states_masked_WIRE : UInt<16>[2] connect _states_masked_WIRE[0], UInt<16>(0h0) connect _states_masked_WIRE[1], UInt<16>(0h0) wire states_masked : UInt<16>[2] connect states_masked, _states_masked_WIRE node _mask_T = bits(nbBitsOut[0], 4, 0) node _mask_T_1 = dshl(UInt<1>(0h1), _mask_T) node _mask_T_2 = sub(_mask_T_1, UInt<1>(0h1)) node mask = tail(_mask_T_2, 1) node _states_masked_0_T = and(statePtr_value[0], mask) connect states_masked[0], _states_masked_0_T node _mask_T_3 = bits(nbBitsOut[1], 4, 0) node _mask_T_4 = dshl(UInt<1>(0h1), _mask_T_3) node _mask_T_5 = sub(_mask_T_4, UInt<1>(0h1)) node mask_1 = tail(_mask_T_5, 1) node _states_masked_1_T = and(statePtr_value[1], mask_1) connect states_masked[1], _states_masked_1_T wire _states_shifted_WIRE : UInt<32>[2] connect _states_shifted_WIRE[0], UInt<32>(0h0) connect _states_shifted_WIRE[1], UInt<32>(0h0) wire states_shifted : UInt<32>[2] connect states_shifted, _states_shifted_WIRE connect states_shifted[0], states_masked[0] node _states_shifted_1_T = bits(cumul_nbBitsOut[0], 5, 0) node _states_shifted_1_T_1 = dshl(states_masked[1], _states_shifted_1_T) connect states_shifted[1], _states_shifted_1_T_1 node states_concat = or(states_shifted[0], states_shifted[1]) node init_done = and(initCStateDone[0], initCStateDone[1]) node _states_concat_reverse_T = bits(nbBitsOut[1], 5, 0) node _states_concat_reverse_T_1 = dshl(states_masked[0], _states_concat_reverse_T) node states_concat_reverse = or(states_masked[1], _states_concat_reverse_T_1) node _data_to_write_T = and(io.table_log.valid, flush) node _data_to_write_T_1 = and(_data_to_write_T, io.lookup_done.ready) node _data_to_write_T_2 = and(_data_to_write_T_1, comp_bits_buff.io.writes_in.ready) node _data_to_write_T_3 = and(_data_to_write_T_2, track_consumed_bytes_odd) node data_to_write = mux(_data_to_write_T_3, states_concat_reverse, states_concat) regreset sent_bits : UInt<64>, clock, reset, UInt<64>(0h0) node _T_77 = and(comp_bits_buff.io.writes_in.ready, comp_bits_buff.io.writes_in.valid) when _T_77 : node _sent_bits_T = add(sent_bits, comp_bits_buff.io.writes_in.bits.validbits) node _sent_bits_T_1 = tail(_sent_bits_T, 1) node _sent_bits_T_2 = mux(add_padding, UInt<1>(0h0), _sent_bits_T_1) connect sent_bits, _sent_bits_T_2 node extra_bits = and(sent_bits, UInt<3>(0h7)) node _padding_bits_T = sub(UInt<4>(0h8), extra_bits) node padding_bits = tail(_padding_bits_T, 1) node _comp_bits_buff_io_writes_in_valid_T = and(lookup_symbol_cnt_q.io.deq.valid, comp_trans_table_valid) node _comp_bits_buff_io_writes_in_valid_T_1 = and(_comp_bits_buff_io_writes_in_valid_T, all_new_state_valid) node _comp_bits_buff_io_writes_in_valid_T_2 = and(_comp_bits_buff_io_writes_in_valid_T_1, init_done) node _comp_bits_buff_io_writes_in_valid_T_3 = and(io.table_log.valid, flush) node _comp_bits_buff_io_writes_in_valid_T_4 = and(_comp_bits_buff_io_writes_in_valid_T_3, io.lookup_done.ready) node _comp_bits_buff_io_writes_in_valid_T_5 = or(_comp_bits_buff_io_writes_in_valid_T_2, _comp_bits_buff_io_writes_in_valid_T_4) node _comp_bits_buff_io_writes_in_valid_T_6 = or(_comp_bits_buff_io_writes_in_valid_T_5, add_padding) connect comp_bits_buff.io.writes_in.valid, _comp_bits_buff_io_writes_in_valid_T_6 node _comp_bits_buff_io_writes_in_bits_data_T = mux(add_padding, UInt<1>(0h1), data_to_write) connect comp_bits_buff.io.writes_in.bits.data, _comp_bits_buff_io_writes_in_bits_data_T node _comp_bits_buff_io_writes_in_bits_validbits_T = mux(add_padding, padding_bits, cumul_nbBitsOut[1]) connect comp_bits_buff.io.writes_in.bits.validbits, _comp_bits_buff_io_writes_in_bits_validbits_T connect comp_bits_buff.io.writes_in.bits.end_of_message, add_padding node _T_78 = and(lookup_symbol_cnt_q.io.deq.valid, comp_trans_table_valid) node _T_79 = and(_T_78, all_new_state_valid) node _T_80 = and(_T_79, comp_bits_buff.io.writes_in.ready) node _T_81 = and(_T_80, init_done) when _T_81 : regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18 node _T_84 = asUInt(reset) node _T_85 = eq(_T_84, UInt<1>(0h0)) when _T_85 : printf(clock, UInt<1>(0h1), "update_state_fire.fire\n") : printf_19 regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20 node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "%d, state: 0x%x, states_masked: 0x%x, states_shifted: 0x%x, cumul_nbBitsOut: %d, nbBitsOut: %d\n", UInt<1>(0h0), statePtr_value[0], states_masked[0], states_shifted[0], cumul_nbBitsOut[0], nbBitsOut[0]) : printf_21 regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_90 = asUInt(reset) node _T_91 = eq(_T_90, UInt<1>(0h0)) when _T_91 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22 node _T_92 = asUInt(reset) node _T_93 = eq(_T_92, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "%d, state: 0x%x, states_masked: 0x%x, states_shifted: 0x%x, cumul_nbBitsOut: %d, nbBitsOut: %d\n", UInt<1>(0h1), statePtr_value[1], states_masked[1], states_shifted[1], cumul_nbBitsOut[1], nbBitsOut[1]) : printf_23 regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24 node _T_96 = asUInt(reset) node _T_97 = eq(_T_96, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "bitbuf data: 0x%x, validbits: %d\n", comp_bits_buff.io.writes_in.bits.data, comp_bits_buff.io.writes_in.bits.validbits) : printf_25 regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26 node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : printf(clock, UInt<1>(0h1), "comp_trans_table_last_symbols: %d\n", comp_trans_table_last_symbols) : printf_27 node _T_102 = and(io.table_log.valid, flush) node _T_103 = and(_T_102, io.lookup_done.ready) node _T_104 = and(_T_103, comp_bits_buff.io.writes_in.ready) when _T_104 : regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28 node _T_107 = asUInt(reset) node _T_108 = eq(_T_107, UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "flush_state_fire.fire\n") : printf_29 regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_30 node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "%d, state: 0x%x, states_masked: 0x%x, states_shifted: 0x%x, cumul_nbBitsOut: %d, nbBitsOut: %d\n", UInt<1>(0h0), statePtr_value[0], states_masked[0], states_shifted[0], cumul_nbBitsOut[0], nbBitsOut[0]) : printf_31 regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_32 node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : printf(clock, UInt<1>(0h1), "%d, state: 0x%x, states_masked: 0x%x, states_shifted: 0x%x, cumul_nbBitsOut: %d, nbBitsOut: %d\n", UInt<1>(0h1), statePtr_value[1], states_masked[1], states_shifted[1], cumul_nbBitsOut[1], nbBitsOut[1]) : printf_33 regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_34 node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "bitbuf data: 0x%x, validbits: %d\n", comp_bits_buff.io.writes_in.bits.data, comp_bits_buff.io.writes_in.bits.validbits) : printf_35 node _T_121 = and(comp_bits_buff.io.writes_in.ready, add_padding) when _T_121 : regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_36 node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : printf(clock, UInt<1>(0h1), "padding_bits: %d\n", padding_bits) : printf_37 regreset track_fse_total_written_bytes : UInt<64>, clock, reset, UInt<64>(0h0) node _T_126 = and(io.memwrites_out.ready, io.memwrites_out.valid) when _T_126 : when io.memwrites_out.bits.end_of_message : node _T_127 = add(track_fse_total_written_bytes, io.memwrites_out.bits.validbytes) node _T_128 = tail(_T_127, 1) regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_129 = asUInt(reset) node _T_130 = eq(_T_129, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_38 node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "FSE_ENCODER track_fse_total_written_bytes: %d\n", _T_128) : printf_39 connect track_fse_total_written_bytes, UInt<1>(0h0) else : node _track_fse_total_written_bytes_T = add(track_fse_total_written_bytes, io.memwrites_out.bits.validbytes) node _track_fse_total_written_bytes_T_1 = tail(_track_fse_total_written_bytes_T, 1) connect track_fse_total_written_bytes, _track_fse_total_written_bytes_T_1 node _io_memwrites_out_valid_T = or(comp_bits_buff.io.consumer.valid, io.header_writes.valid) connect io.memwrites_out.valid, _io_memwrites_out_valid_T node _io_memwrites_out_bits_data_T = and(io.header_writes.valid, io.memwrites_out.ready) node _io_memwrites_out_bits_data_T_1 = mux(_io_memwrites_out_bits_data_T, io.header_writes.bits.data, comp_bits_buff.io.consumer.data) connect io.memwrites_out.bits.data, _io_memwrites_out_bits_data_T_1 node _io_memwrites_out_bits_validbytes_T = and(io.header_writes.valid, io.memwrites_out.ready) node _io_memwrites_out_bits_validbytes_T_1 = mux(_io_memwrites_out_bits_validbytes_T, io.header_writes.bits.validbytes, comp_bits_buff.io.consumer.avail_bytes) connect io.memwrites_out.bits.validbytes, _io_memwrites_out_bits_validbytes_T_1 node _io_memwrites_out_bits_end_of_message_T = and(io.header_writes.valid, io.memwrites_out.ready) node _io_memwrites_out_bits_end_of_message_T_1 = mux(_io_memwrites_out_bits_end_of_message_T, io.header_writes.bits.end_of_message, comp_bits_buff.io.consumer.last_chunk) connect io.memwrites_out.bits.end_of_message, _io_memwrites_out_bits_end_of_message_T_1 connect io.header_writes.ready, io.memwrites_out.ready connect comp_bits_buff.io.consumer.consumed_bytes, comp_bits_buff.io.consumer.avail_bytes connect comp_bits_buff.io.consumer.ready, io.memwrites_out.ready node _T_133 = and(io.memwrites_out.ready, io.memwrites_out.valid) node _T_134 = and(_T_133, io.memwrites_out.bits.end_of_message) when _T_134 : connect initCStateDone[0], UInt<1>(0h0) connect statePtr_value[0], UInt<1>(0h0) connect track_consumed_bytes, UInt<1>(0h0) connect input_symbol_cnt, UInt<1>(0h0) connect flush, UInt<1>(0h0) connect add_padding, UInt<1>(0h0) connect sent_bits, UInt<1>(0h0) connect track_fse_total_written_bytes, UInt<1>(0h0) connect initCStateDone[1], UInt<1>(0h0) connect statePtr_value[1], UInt<1>(0h0) connect track_consumed_bytes, UInt<1>(0h0) connect input_symbol_cnt, UInt<1>(0h0) connect flush, UInt<1>(0h0) connect add_padding, UInt<1>(0h0) connect sent_bits, UInt<1>(0h0) connect track_fse_total_written_bytes, UInt<1>(0h0)
module FSECompressorEncoder( // @[FSECompressorEncoder.scala:41:7] input clock, // @[FSECompressorEncoder.scala:41:7] input reset, // @[FSECompressorEncoder.scala:41:7] output [5:0] io_src_stream_user_consumed_bytes, // @[FSECompressorEncoder.scala:43:14] input [5:0] io_src_stream_available_output_bytes, // @[FSECompressorEncoder.scala:43:14] input io_src_stream_output_valid, // @[FSECompressorEncoder.scala:43:14] output io_src_stream_output_ready, // @[FSECompressorEncoder.scala:43:14] input [255:0] io_src_stream_output_data, // @[FSECompressorEncoder.scala:43:14] input io_src_stream_output_last_chunk, // @[FSECompressorEncoder.scala:43:14] output io_table_log_ready, // @[FSECompressorEncoder.scala:43:14] input io_table_log_valid, // @[FSECompressorEncoder.scala:43:14] input io_symbol_info_0_ready, // @[FSECompressorEncoder.scala:43:14] output io_symbol_info_0_valid, // @[FSECompressorEncoder.scala:43:14] output [7:0] io_symbol_info_0_bits_symbol, // @[FSECompressorEncoder.scala:43:14] output io_symbol_info_0_bits_last_symbol, // @[FSECompressorEncoder.scala:43:14] input io_symbol_info_1_ready, // @[FSECompressorEncoder.scala:43:14] output io_symbol_info_1_valid, // @[FSECompressorEncoder.scala:43:14] output [7:0] io_symbol_info_1_bits_symbol, // @[FSECompressorEncoder.scala:43:14] output io_symbol_info_1_bits_last_symbol, // @[FSECompressorEncoder.scala:43:14] output io_comp_trans_table_0_ready, // @[FSECompressorEncoder.scala:43:14] input io_comp_trans_table_0_valid, // @[FSECompressorEncoder.scala:43:14] input [31:0] io_comp_trans_table_0_bits_nbbit, // @[FSECompressorEncoder.scala:43:14] input [31:0] io_comp_trans_table_0_bits_findstate, // @[FSECompressorEncoder.scala:43:14] input io_comp_trans_table_0_bits_from_last_symbol, // @[FSECompressorEncoder.scala:43:14] output io_comp_trans_table_1_ready, // @[FSECompressorEncoder.scala:43:14] input io_comp_trans_table_1_valid, // @[FSECompressorEncoder.scala:43:14] input [31:0] io_comp_trans_table_1_bits_nbbit, // @[FSECompressorEncoder.scala:43:14] input [31:0] io_comp_trans_table_1_bits_findstate, // @[FSECompressorEncoder.scala:43:14] input io_comp_trans_table_1_bits_from_last_symbol, // @[FSECompressorEncoder.scala:43:14] output [15:0] io_state_table_idx_0, // @[FSECompressorEncoder.scala:43:14] output [15:0] io_state_table_idx_1, // @[FSECompressorEncoder.scala:43:14] input io_new_state_0_valid, // @[FSECompressorEncoder.scala:43:14] input [15:0] io_new_state_0_bits, // @[FSECompressorEncoder.scala:43:14] input io_new_state_1_valid, // @[FSECompressorEncoder.scala:43:14] input [15:0] io_new_state_1_bits, // @[FSECompressorEncoder.scala:43:14] input io_memwrites_out_ready, // @[FSECompressorEncoder.scala:43:14] output io_memwrites_out_valid, // @[FSECompressorEncoder.scala:43:14] output [255:0] io_memwrites_out_bits_data, // @[FSECompressorEncoder.scala:43:14] output [5:0] io_memwrites_out_bits_validbytes, // @[FSECompressorEncoder.scala:43:14] output io_memwrites_out_bits_end_of_message, // @[FSECompressorEncoder.scala:43:14] output io_header_writes_ready, // @[FSECompressorEncoder.scala:43:14] input io_header_writes_valid, // @[FSECompressorEncoder.scala:43:14] input [255:0] io_header_writes_bits_data, // @[FSECompressorEncoder.scala:43:14] input [5:0] io_header_writes_bits_validbytes, // @[FSECompressorEncoder.scala:43:14] output io_lookup_done_valid // @[FSECompressorEncoder.scala:43:14] ); wire [6:0] comp_bits_buff_io_writes_in_bits_validbits; // @[FSECompressorEncoder.scala:264:46] wire [31:0] deltaFindState_0; // @[FSECompressorEncoder.scala:116:32] wire [31:0] nbBitsOut_0; // @[FSECompressorEncoder.scala:114:27] wire _comp_bits_buff_io_writes_in_ready; // @[FSECompressorEncoder.scala:145:30] wire _comp_bits_buff_io_consumer_valid; // @[FSECompressorEncoder.scala:145:30] wire [6:0] _comp_bits_buff_io_consumer_avail_bytes; // @[FSECompressorEncoder.scala:145:30] wire [63:0] _comp_bits_buff_io_consumer_data; // @[FSECompressorEncoder.scala:145:30] wire _comp_bits_buff_io_consumer_last_chunk; // @[FSECompressorEncoder.scala:145:30] wire _comp_trans_table_q_1_io_deq_valid; // @[FSECompressorEncoder.scala:66:59] wire _comp_trans_table_q_1_io_deq_bits_from_last_symbol; // @[FSECompressorEncoder.scala:66:59] wire _comp_trans_table_q_0_io_deq_valid; // @[FSECompressorEncoder.scala:66:59] wire _comp_trans_table_q_0_io_deq_bits_from_last_symbol; // @[FSECompressorEncoder.scala:66:59] wire _symbol_info_q_1_io_enq_ready; // @[FSECompressorEncoder.scala:65:54] wire _symbol_info_q_0_io_enq_ready; // @[FSECompressorEncoder.scala:65:54] wire _lookup_symbol_cnt_q_io_enq_ready; // @[FSECompressorEncoder.scala:49:35] wire _lookup_symbol_cnt_q_io_deq_valid; // @[FSECompressorEncoder.scala:49:35] wire [1:0] _lookup_symbol_cnt_q_io_deq_bits; // @[FSECompressorEncoder.scala:49:35] wire [5:0] io_src_stream_available_output_bytes_0 = io_src_stream_available_output_bytes; // @[FSECompressorEncoder.scala:41:7] wire io_src_stream_output_valid_0 = io_src_stream_output_valid; // @[FSECompressorEncoder.scala:41:7] wire [255:0] io_src_stream_output_data_0 = io_src_stream_output_data; // @[FSECompressorEncoder.scala:41:7] wire io_src_stream_output_last_chunk_0 = io_src_stream_output_last_chunk; // @[FSECompressorEncoder.scala:41:7] wire io_table_log_valid_0 = io_table_log_valid; // @[FSECompressorEncoder.scala:41:7] wire io_symbol_info_0_ready_0 = io_symbol_info_0_ready; // @[FSECompressorEncoder.scala:41:7] wire io_symbol_info_1_ready_0 = io_symbol_info_1_ready; // @[FSECompressorEncoder.scala:41:7] wire io_comp_trans_table_0_valid_0 = io_comp_trans_table_0_valid; // @[FSECompressorEncoder.scala:41:7] wire [31:0] io_comp_trans_table_0_bits_nbbit_0 = io_comp_trans_table_0_bits_nbbit; // @[FSECompressorEncoder.scala:41:7] wire [31:0] io_comp_trans_table_0_bits_findstate_0 = io_comp_trans_table_0_bits_findstate; // @[FSECompressorEncoder.scala:41:7] wire io_comp_trans_table_0_bits_from_last_symbol_0 = io_comp_trans_table_0_bits_from_last_symbol; // @[FSECompressorEncoder.scala:41:7] wire io_comp_trans_table_1_valid_0 = io_comp_trans_table_1_valid; // @[FSECompressorEncoder.scala:41:7] wire [31:0] io_comp_trans_table_1_bits_nbbit_0 = io_comp_trans_table_1_bits_nbbit; // @[FSECompressorEncoder.scala:41:7] wire [31:0] io_comp_trans_table_1_bits_findstate_0 = io_comp_trans_table_1_bits_findstate; // @[FSECompressorEncoder.scala:41:7] wire io_comp_trans_table_1_bits_from_last_symbol_0 = io_comp_trans_table_1_bits_from_last_symbol; // @[FSECompressorEncoder.scala:41:7] wire io_new_state_0_valid_0 = io_new_state_0_valid; // @[FSECompressorEncoder.scala:41:7] wire [15:0] io_new_state_0_bits_0 = io_new_state_0_bits; // @[FSECompressorEncoder.scala:41:7] wire io_new_state_1_valid_0 = io_new_state_1_valid; // @[FSECompressorEncoder.scala:41:7] wire [15:0] io_new_state_1_bits_0 = io_new_state_1_bits; // @[FSECompressorEncoder.scala:41:7] wire io_memwrites_out_ready_0 = io_memwrites_out_ready; // @[FSECompressorEncoder.scala:41:7] wire io_header_writes_valid_0 = io_header_writes_valid; // @[FSECompressorEncoder.scala:41:7] wire [255:0] io_header_writes_bits_data_0 = io_header_writes_bits_data; // @[FSECompressorEncoder.scala:41:7] wire [5:0] io_header_writes_bits_validbytes_0 = io_header_writes_bits_validbytes; // @[FSECompressorEncoder.scala:41:7] wire [3:0] io_table_log_bits = 4'h6; // @[FSECompressorEncoder.scala:41:7] wire io_header_writes_bits_end_of_message = 1'h0; // @[FSECompressorEncoder.scala:41:7] wire _initCStateDone_WIRE_0 = 1'h0; // @[FSECompressorEncoder.scala:51:39] wire _initCStateDone_WIRE_1 = 1'h0; // @[FSECompressorEncoder.scala:51:39] wire io_lookup_done_ready = 1'h1; // @[FSECompressorEncoder.scala:41:7] wire io_lookup_done_bits = 1'h1; // @[FSECompressorEncoder.scala:41:7] wire [15:0] _statePtr_value_WIRE_0 = 16'h0; // @[FSECompressorEncoder.scala:52:39] wire [15:0] _statePtr_value_WIRE_1 = 16'h0; // @[FSECompressorEncoder.scala:52:39] wire [15:0] _statePtr_value_to_shift_WIRE_0 = 16'h0; // @[FSECompressorEncoder.scala:117:49] wire [15:0] _statePtr_value_to_shift_WIRE_1 = 16'h0; // @[FSECompressorEncoder.scala:117:49] wire [15:0] _states_masked_WIRE_0 = 16'h0; // @[FSECompressorEncoder.scala:222:39] wire [15:0] _states_masked_WIRE_1 = 16'h0; // @[FSECompressorEncoder.scala:222:39] wire [31:0] _nbBitsOut_WIRE_0 = 32'h0; // @[FSECompressorEncoder.scala:114:35] wire [31:0] _nbBitsOut_WIRE_1 = 32'h0; // @[FSECompressorEncoder.scala:114:35] wire [31:0] _deltaNbBits_WIRE_0 = 32'h0; // @[FSECompressorEncoder.scala:115:37] wire [31:0] _deltaNbBits_WIRE_1 = 32'h0; // @[FSECompressorEncoder.scala:115:37] wire [31:0] _deltaFindState_WIRE_0 = 32'h0; // @[FSECompressorEncoder.scala:116:40] wire [31:0] _deltaFindState_WIRE_1 = 32'h0; // @[FSECompressorEncoder.scala:116:40] wire [31:0] _cumul_nbBitsOut_WIRE_0 = 32'h0; // @[FSECompressorEncoder.scala:213:41] wire [31:0] _cumul_nbBitsOut_WIRE_1 = 32'h0; // @[FSECompressorEncoder.scala:213:41] wire [31:0] _states_shifted_WIRE_0 = 32'h0; // @[FSECompressorEncoder.scala:230:40] wire [31:0] _states_shifted_WIRE_1 = 32'h0; // @[FSECompressorEncoder.scala:230:40] wire [7:0] _symbols_WIRE_0 = 8'h0; // @[FSECompressorEncoder.scala:53:33] wire [7:0] _symbols_WIRE_1 = 8'h0; // @[FSECompressorEncoder.scala:53:33] wire [5:0] consumed_bytes; // @[FSECompressorEncoder.scala:78:27] wire _io_src_stream_output_ready_T; // @[Misc.scala:26:53] wire _io_table_log_ready_T_1; // @[Misc.scala:26:53] wire io_header_writes_ready_0 = io_memwrites_out_ready_0; // @[FSECompressorEncoder.scala:41:7] wire _io_memwrites_out_valid_T; // @[FSECompressorEncoder.scala:315:72] wire [255:0] _io_memwrites_out_bits_data_T_1; // @[FSECompressorEncoder.scala:317:36] wire _io_memwrites_out_bits_end_of_message_T_1; // @[FSECompressorEncoder.scala:323:46] wire [5:0] io_src_stream_user_consumed_bytes_0; // @[FSECompressorEncoder.scala:41:7] wire io_src_stream_output_ready_0; // @[FSECompressorEncoder.scala:41:7] wire io_table_log_ready_0; // @[FSECompressorEncoder.scala:41:7] wire [7:0] io_symbol_info_0_bits_symbol_0; // @[FSECompressorEncoder.scala:41:7] wire io_symbol_info_0_bits_last_symbol_0; // @[FSECompressorEncoder.scala:41:7] wire io_symbol_info_0_valid_0; // @[FSECompressorEncoder.scala:41:7] wire [7:0] io_symbol_info_1_bits_symbol_0; // @[FSECompressorEncoder.scala:41:7] wire io_symbol_info_1_bits_last_symbol_0; // @[FSECompressorEncoder.scala:41:7] wire io_symbol_info_1_valid_0; // @[FSECompressorEncoder.scala:41:7] wire io_comp_trans_table_0_ready_0; // @[FSECompressorEncoder.scala:41:7] wire io_comp_trans_table_1_ready_0; // @[FSECompressorEncoder.scala:41:7] wire [15:0] io_state_table_idx_0_0; // @[FSECompressorEncoder.scala:41:7] wire [15:0] io_state_table_idx_1_0; // @[FSECompressorEncoder.scala:41:7] wire [255:0] io_memwrites_out_bits_data_0; // @[FSECompressorEncoder.scala:41:7] wire [5:0] io_memwrites_out_bits_validbytes_0; // @[FSECompressorEncoder.scala:41:7] wire io_memwrites_out_bits_end_of_message_0; // @[FSECompressorEncoder.scala:41:7] wire io_memwrites_out_valid_0; // @[FSECompressorEncoder.scala:41:7] wire io_lookup_done_valid_0; // @[FSECompressorEncoder.scala:41:7] reg initCStateDone_0; // @[FSECompressorEncoder.scala:51:31] reg initCStateDone_1; // @[FSECompressorEncoder.scala:51:31] reg [15:0] statePtr_value_0; // @[FSECompressorEncoder.scala:52:31] reg [15:0] statePtr_value_1; // @[FSECompressorEncoder.scala:52:31] wire [7:0] symbols_0; // @[FSECompressorEncoder.scala:53:25] wire [7:0] symbols_1; // @[FSECompressorEncoder.scala:53:25] wire [255:0] _symbols_0_T = {248'h0, io_src_stream_output_data_0[255:248]}; // @[FSECompressorEncoder.scala:41:7, :55:45] assign symbols_0 = _symbols_0_T[7:0]; // @[FSECompressorEncoder.scala:53:25, :55:{16,45}] wire [255:0] _symbols_1_T = {240'h0, io_src_stream_output_data_0[255:240]}; // @[FSECompressorEncoder.scala:41:7, :55:45] assign symbols_1 = _symbols_1_T[7:0]; // @[FSECompressorEncoder.scala:53:25, :55:{16,45}] wire _T_18 = io_src_stream_output_valid_0 & io_src_stream_output_ready_0; // @[FSECompressorEncoder.scala:41:7, :58:36] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] wire all_io_symbol_info_ready = _symbol_info_q_0_io_enq_ready | _symbol_info_q_1_io_enq_ready; // @[FSECompressorEncoder.scala:65:54, :72:77] wire _consumed_bytes_T = io_src_stream_available_output_bytes_0 < 6'h2; // @[FSECompressorEncoder.scala:41:7, :78:45] assign consumed_bytes = _consumed_bytes_T ? io_src_stream_available_output_bytes_0 : 6'h2; // @[FSECompressorEncoder.scala:41:7, :78:{27,45}] assign io_src_stream_user_consumed_bytes_0 = consumed_bytes; // @[FSECompressorEncoder.scala:41:7, :78:27] wire _lookup_symbol_cnt_q_io_enq_valid_T = io_src_stream_output_valid_0 & all_io_symbol_info_ready; // @[Misc.scala:26:53] assign _io_src_stream_output_ready_T = _lookup_symbol_cnt_q_io_enq_ready & all_io_symbol_info_ready; // @[Misc.scala:26:53] assign io_src_stream_output_ready_0 = _io_src_stream_output_ready_T; // @[Misc.scala:26:53] reg [63:0] track_consumed_bytes; // @[FSECompressorEncoder.scala:88:37] wire [64:0] _GEN = {59'h0, consumed_bytes}; // @[FSECompressorEncoder.scala:78:27, :90:50] wire [64:0] _track_consumed_bytes_T = {1'h0, track_consumed_bytes} + _GEN; // @[FSECompressorEncoder.scala:88:37, :90:50] wire [63:0] _track_consumed_bytes_T_1 = _track_consumed_bytes_T[63:0]; // @[FSECompressorEncoder.scala:90:50] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] wire _track_consumed_bytes_odd_T = track_consumed_bytes[0]; // @[FSECompressorEncoder.scala:88:37, :93:55] wire track_consumed_bytes_odd = _track_consumed_bytes_odd_T; // @[FSECompressorEncoder.scala:93:{55,59}] wire use_this_queue = |consumed_bytes; // @[FSECompressorEncoder.scala:78:27, :96:31] wire _GEN_0 = _lookup_symbol_cnt_q_io_enq_ready & io_src_stream_output_valid_0; // @[Misc.scala:26:53] wire _symbol_info_q_0_io_enq_valid_T; // @[Misc.scala:26:53] assign _symbol_info_q_0_io_enq_valid_T = _GEN_0; // @[Misc.scala:26:53] wire _symbol_info_q_1_io_enq_valid_T; // @[Misc.scala:26:53] assign _symbol_info_q_1_io_enq_valid_T = _GEN_0; // @[Misc.scala:26:53] wire _symbol_info_q_0_io_enq_valid_T_1 = _symbol_info_q_0_io_enq_valid_T & use_this_queue; // @[Misc.scala:26:53] wire [6:0] _GEN_1 = {1'h0, io_src_stream_available_output_bytes_0} - 7'h1; // @[FSECompressorEncoder.scala:41:7, :99:95] wire [6:0] _symbol_info_q_0_io_enq_bits_last_symbol_T; // @[FSECompressorEncoder.scala:99:95] assign _symbol_info_q_0_io_enq_bits_last_symbol_T = _GEN_1; // @[FSECompressorEncoder.scala:99:95] wire [6:0] _symbol_info_q_1_io_enq_bits_last_symbol_T; // @[FSECompressorEncoder.scala:99:95] assign _symbol_info_q_1_io_enq_bits_last_symbol_T = _GEN_1; // @[FSECompressorEncoder.scala:99:95] wire [5:0] _symbol_info_q_0_io_enq_bits_last_symbol_T_1 = _symbol_info_q_0_io_enq_bits_last_symbol_T[5:0]; // @[FSECompressorEncoder.scala:99:95] wire _symbol_info_q_0_io_enq_bits_last_symbol_T_2 = _symbol_info_q_0_io_enq_bits_last_symbol_T_1 == 6'h0; // @[FSECompressorEncoder.scala:99:{54,95}] wire _symbol_info_q_0_io_enq_bits_last_symbol_T_3 = _symbol_info_q_0_io_enq_bits_last_symbol_T_2 & io_src_stream_output_last_chunk_0; // @[FSECompressorEncoder.scala:41:7, :99:{54,102}] wire use_this_queue_1 = |(consumed_bytes[5:1]); // @[FSECompressorEncoder.scala:78:27, :96:31] wire _symbol_info_q_1_io_enq_valid_T_1 = _symbol_info_q_1_io_enq_valid_T & use_this_queue_1; // @[Misc.scala:26:53] wire [5:0] _symbol_info_q_1_io_enq_bits_last_symbol_T_1 = _symbol_info_q_1_io_enq_bits_last_symbol_T[5:0]; // @[FSECompressorEncoder.scala:99:95] wire _symbol_info_q_1_io_enq_bits_last_symbol_T_2 = _symbol_info_q_1_io_enq_bits_last_symbol_T_1 == 6'h1; // @[FSECompressorEncoder.scala:99:{54,95}] wire _symbol_info_q_1_io_enq_bits_last_symbol_T_3 = _symbol_info_q_1_io_enq_bits_last_symbol_T_2 & io_src_stream_output_last_chunk_0; // @[FSECompressorEncoder.scala:41:7, :99:{54,102}] reg [63:0] input_symbol_cnt; // @[FSECompressorEncoder.scala:102:33] wire [64:0] _input_symbol_cnt_T = {1'h0, input_symbol_cnt} + _GEN; // @[FSECompressorEncoder.scala:90:50, :102:33, :104:42] wire [63:0] _input_symbol_cnt_T_1 = _input_symbol_cnt_T[63:0]; // @[FSECompressorEncoder.scala:104:42] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg flush; // @[FSECompressorEncoder.scala:113:22] wire _io_table_log_ready_T = flush; // @[Misc.scala:26:53] wire [31:0] _nbBitsOut_0_T_8; // @[FSECompressorEncoder.scala:121:24] wire [31:0] _nbBitsOut_1_T_8; // @[FSECompressorEncoder.scala:121:24] wire [31:0] cumul_nbBitsOut_0 = nbBitsOut_0; // @[FSECompressorEncoder.scala:114:27, :213:33] wire [31:0] nbBitsOut_1; // @[FSECompressorEncoder.scala:114:27] wire [31:0] deltaNbBits_0; // @[FSECompressorEncoder.scala:115:29] wire [31:0] deltaNbBits_1; // @[FSECompressorEncoder.scala:115:29] wire [31:0] _io_state_table_idx_0_T_2 = deltaFindState_0; // @[FSECompressorEncoder.scala:116:32, :128:103] wire [31:0] deltaFindState_1; // @[FSECompressorEncoder.scala:116:32] wire [31:0] _io_state_table_idx_1_T_2 = deltaFindState_1; // @[FSECompressorEncoder.scala:116:32, :128:103] wire [15:0] statePtr_value_to_shift_0; // @[FSECompressorEncoder.scala:117:41] wire [15:0] statePtr_value_to_shift_1; // @[FSECompressorEncoder.scala:117:41] wire _nbBitsOut_0_T = ~initCStateDone_0; // @[FSECompressorEncoder.scala:51:31, :122:27] wire [32:0] _GEN_2 = {1'h0, deltaNbBits_0}; // @[FSECompressorEncoder.scala:115:29, :123:41] wire [32:0] _nbBitsOut_0_T_1 = _GEN_2 + 33'h8000; // @[FSECompressorEncoder.scala:123:41] wire [31:0] _nbBitsOut_0_T_2 = _nbBitsOut_0_T_1[31:0]; // @[FSECompressorEncoder.scala:123:41] wire [31:0] _nbBitsOut_0_T_3 = {16'h0, _nbBitsOut_0_T_2[31:16]}; // @[FSECompressorEncoder.scala:123:{41,54}] wire [32:0] _nbBitsOut_0_T_4 = {17'h0, statePtr_value_0} + _GEN_2; // @[FSECompressorEncoder.scala:52:31, :123:41, :124:44] wire [31:0] _nbBitsOut_0_T_5 = _nbBitsOut_0_T_4[31:0]; // @[FSECompressorEncoder.scala:124:44] wire [31:0] _nbBitsOut_0_T_6 = {16'h0, _nbBitsOut_0_T_5[31:16]}; // @[FSECompressorEncoder.scala:124:{44,62}] wire [31:0] _nbBitsOut_0_T_7 = _nbBitsOut_0_T ? _nbBitsOut_0_T_3 : _nbBitsOut_0_T_6; // @[FSECompressorEncoder.scala:122:{26,27}, :123:54, :124:62] assign _nbBitsOut_0_T_8 = flush ? 32'h6 : _nbBitsOut_0_T_7; // @[FSECompressorEncoder.scala:113:22, :121:24, :122:26] assign nbBitsOut_0 = _nbBitsOut_0_T_8; // @[FSECompressorEncoder.scala:114:27, :121:24] wire _statePtr_value_to_shift_0_T = ~initCStateDone_0; // @[FSECompressorEncoder.scala:51:31, :122:27, :125:39] wire [62:0] _statePtr_value_to_shift_0_T_1 = {15'h0, nbBitsOut_0, 16'h0}; // @[FSECompressorEncoder.scala:114:27, :126:53] wire [63:0] _statePtr_value_to_shift_0_T_2 = {1'h0, _statePtr_value_to_shift_0_T_1} - {32'h0, deltaNbBits_0}; // @[FSECompressorEncoder.scala:115:29, :126:{53,62}] wire [62:0] _statePtr_value_to_shift_0_T_3 = _statePtr_value_to_shift_0_T_2[62:0]; // @[FSECompressorEncoder.scala:126:62] wire [62:0] _statePtr_value_to_shift_0_T_4 = _statePtr_value_to_shift_0_T ? _statePtr_value_to_shift_0_T_3 : {47'h0, statePtr_value_0}; // @[FSECompressorEncoder.scala:52:31, :125:{38,39}, :126:62] assign statePtr_value_to_shift_0 = _statePtr_value_to_shift_0_T_4[15:0]; // @[FSECompressorEncoder.scala:117:41, :125:{32,38}] wire [31:0] _GEN_3 = {16'h0, statePtr_value_to_shift_0} >> nbBitsOut_0; // @[FSECompressorEncoder.scala:114:27, :117:41, :128:59] wire [15:0] _io_state_table_idx_0_T = _GEN_3[15:0]; // @[FSECompressorEncoder.scala:128:59] wire [15:0] _io_state_table_idx_0_T_1 = _io_state_table_idx_0_T; // @[FSECompressorEncoder.scala:128:{59,76}] wire [32:0] _io_state_table_idx_0_T_3 = {{17{_io_state_table_idx_0_T_1[15]}}, _io_state_table_idx_0_T_1} + {_io_state_table_idx_0_T_2[31], _io_state_table_idx_0_T_2}; // @[FSECompressorEncoder.scala:128:{76,83,103}] wire [31:0] _io_state_table_idx_0_T_4 = _io_state_table_idx_0_T_3[31:0]; // @[FSECompressorEncoder.scala:128:83] wire [31:0] _io_state_table_idx_0_T_5 = _io_state_table_idx_0_T_4; // @[FSECompressorEncoder.scala:128:83] wire [31:0] _io_state_table_idx_0_T_6 = _io_state_table_idx_0_T_5; // @[FSECompressorEncoder.scala:128:{83,111}] assign io_state_table_idx_0_0 = _io_state_table_idx_0_T_6[15:0]; // @[FSECompressorEncoder.scala:41:7, :128:{27,111}] wire _nbBitsOut_1_T = ~initCStateDone_1; // @[FSECompressorEncoder.scala:51:31, :122:27] wire [32:0] _GEN_4 = {1'h0, deltaNbBits_1}; // @[FSECompressorEncoder.scala:115:29, :123:41] wire [32:0] _nbBitsOut_1_T_1 = _GEN_4 + 33'h8000; // @[FSECompressorEncoder.scala:123:41] wire [31:0] _nbBitsOut_1_T_2 = _nbBitsOut_1_T_1[31:0]; // @[FSECompressorEncoder.scala:123:41] wire [31:0] _nbBitsOut_1_T_3 = {16'h0, _nbBitsOut_1_T_2[31:16]}; // @[FSECompressorEncoder.scala:123:{41,54}] wire [32:0] _nbBitsOut_1_T_4 = {17'h0, statePtr_value_1} + _GEN_4; // @[FSECompressorEncoder.scala:52:31, :123:41, :124:44] wire [31:0] _nbBitsOut_1_T_5 = _nbBitsOut_1_T_4[31:0]; // @[FSECompressorEncoder.scala:124:44] wire [31:0] _nbBitsOut_1_T_6 = {16'h0, _nbBitsOut_1_T_5[31:16]}; // @[FSECompressorEncoder.scala:124:{44,62}] wire [31:0] _nbBitsOut_1_T_7 = _nbBitsOut_1_T ? _nbBitsOut_1_T_3 : _nbBitsOut_1_T_6; // @[FSECompressorEncoder.scala:122:{26,27}, :123:54, :124:62] assign _nbBitsOut_1_T_8 = flush ? 32'h6 : _nbBitsOut_1_T_7; // @[FSECompressorEncoder.scala:113:22, :121:24, :122:26] assign nbBitsOut_1 = _nbBitsOut_1_T_8; // @[FSECompressorEncoder.scala:114:27, :121:24] wire _statePtr_value_to_shift_1_T = ~initCStateDone_1; // @[FSECompressorEncoder.scala:51:31, :122:27, :125:39] wire [62:0] _statePtr_value_to_shift_1_T_1 = {15'h0, nbBitsOut_1, 16'h0}; // @[FSECompressorEncoder.scala:114:27, :126:53] wire [63:0] _statePtr_value_to_shift_1_T_2 = {1'h0, _statePtr_value_to_shift_1_T_1} - {32'h0, deltaNbBits_1}; // @[FSECompressorEncoder.scala:115:29, :126:{53,62}] wire [62:0] _statePtr_value_to_shift_1_T_3 = _statePtr_value_to_shift_1_T_2[62:0]; // @[FSECompressorEncoder.scala:126:62] wire [62:0] _statePtr_value_to_shift_1_T_4 = _statePtr_value_to_shift_1_T ? _statePtr_value_to_shift_1_T_3 : {47'h0, statePtr_value_1}; // @[FSECompressorEncoder.scala:52:31, :125:{38,39}, :126:62] assign statePtr_value_to_shift_1 = _statePtr_value_to_shift_1_T_4[15:0]; // @[FSECompressorEncoder.scala:117:41, :125:{32,38}] wire [31:0] _GEN_5 = {16'h0, statePtr_value_to_shift_1} >> nbBitsOut_1; // @[FSECompressorEncoder.scala:114:27, :117:41, :128:59] wire [15:0] _io_state_table_idx_1_T = _GEN_5[15:0]; // @[FSECompressorEncoder.scala:128:59] wire [15:0] _io_state_table_idx_1_T_1 = _io_state_table_idx_1_T; // @[FSECompressorEncoder.scala:128:{59,76}] wire [32:0] _io_state_table_idx_1_T_3 = {{17{_io_state_table_idx_1_T_1[15]}}, _io_state_table_idx_1_T_1} + {_io_state_table_idx_1_T_2[31], _io_state_table_idx_1_T_2}; // @[FSECompressorEncoder.scala:128:{76,83,103}] wire [31:0] _io_state_table_idx_1_T_4 = _io_state_table_idx_1_T_3[31:0]; // @[FSECompressorEncoder.scala:128:83] wire [31:0] _io_state_table_idx_1_T_5 = _io_state_table_idx_1_T_4; // @[FSECompressorEncoder.scala:128:83] wire [31:0] _io_state_table_idx_1_T_6 = _io_state_table_idx_1_T_5; // @[FSECompressorEncoder.scala:128:{83,111}] assign io_state_table_idx_1_0 = _io_state_table_idx_1_T_6[15:0]; // @[FSECompressorEncoder.scala:41:7, :128:{27,111}] wire _comp_trans_table_last_symbols_T = _comp_trans_table_q_0_io_deq_bits_from_last_symbol & _comp_trans_table_q_0_io_deq_valid; // @[FSECompressorEncoder.scala:66:59, :131:98] wire _comp_trans_table_last_symbols_T_1 = _comp_trans_table_q_1_io_deq_bits_from_last_symbol & _comp_trans_table_q_1_io_deq_valid; // @[FSECompressorEncoder.scala:66:59, :131:98] wire comp_trans_table_last_symbols = _comp_trans_table_last_symbols_T | _comp_trans_table_last_symbols_T_1; // @[FSECompressorEncoder.scala:131:{98,126}] wire comp_trans_table_all_valid = _comp_trans_table_q_0_io_deq_valid & _comp_trans_table_q_1_io_deq_valid; // @[FSECompressorEncoder.scala:66:59, :132:84] wire comp_trans_table_valid = comp_trans_table_last_symbols | comp_trans_table_all_valid; // @[FSECompressorEncoder.scala:131:126, :132:84, :133:62] wire all_new_state_valid_can_be_invalid; // @[FSECompressorEncoder.scala:135:34] wire _all_new_state_valid_T = |_lookup_symbol_cnt_q_io_deq_bits; // @[FSECompressorEncoder.scala:49:35, :136:15] assign all_new_state_valid_can_be_invalid = ~_all_new_state_valid_T | io_new_state_0_valid_0; // @[FSECompressorEncoder.scala:41:7, :135:34, :136:{15,50}, :137:22, :139:22] wire all_new_state_valid_can_be_invalid_1; // @[FSECompressorEncoder.scala:135:34] wire _all_new_state_valid_T_1 = _lookup_symbol_cnt_q_io_deq_bits[1]; // @[FSECompressorEncoder.scala:49:35, :136:15] wire valid_new_state_1 = _lookup_symbol_cnt_q_io_deq_bits[1]; // @[FSECompressorEncoder.scala:49:35, :136:15, :159:32] wire _valid_bits_T = _lookup_symbol_cnt_q_io_deq_bits[1]; // @[FSECompressorEncoder.scala:49:35, :136:15, :217:33] assign all_new_state_valid_can_be_invalid_1 = ~_all_new_state_valid_T_1 | io_new_state_1_valid_0; // @[FSECompressorEncoder.scala:41:7, :135:34, :136:{15,50}, :137:22, :139:22] wire all_new_state_valid = all_new_state_valid_can_be_invalid & all_new_state_valid_can_be_invalid_1; // @[FSECompressorEncoder.scala:135:34, :142:14] wire _lookup_symbol_cnt_q_io_deq_ready_T = comp_trans_table_valid & all_new_state_valid; // @[Misc.scala:26:53] wire _lookup_symbol_cnt_q_io_deq_ready_T_1 = _lookup_symbol_cnt_q_io_deq_ready_T & _comp_bits_buff_io_writes_in_ready; // @[Misc.scala:26:53] wire _GEN_6 = _lookup_symbol_cnt_q_io_deq_valid & all_new_state_valid; // @[Misc.scala:26:53] wire _comp_trans_table_q_0_io_deq_ready_T; // @[Misc.scala:26:53] assign _comp_trans_table_q_0_io_deq_ready_T = _GEN_6; // @[Misc.scala:26:53] wire _comp_trans_table_q_1_io_deq_ready_T; // @[Misc.scala:26:53] assign _comp_trans_table_q_1_io_deq_ready_T = _GEN_6; // @[Misc.scala:26:53] wire _comp_trans_table_q_0_io_deq_ready_T_1 = _comp_trans_table_q_0_io_deq_ready_T & _comp_bits_buff_io_writes_in_ready; // @[Misc.scala:26:53] wire _comp_trans_table_q_1_io_deq_ready_T_1 = _comp_trans_table_q_1_io_deq_ready_T & _comp_bits_buff_io_writes_in_ready; // @[Misc.scala:26:53] wire valid_new_state = |_lookup_symbol_cnt_q_io_deq_bits; // @[FSECompressorEncoder.scala:49:35, :136:15, :159:32] wire _T_78 = _lookup_symbol_cnt_q_io_deq_valid & comp_trans_table_valid; // @[Misc.scala:29:18] wire _statePtr_value_0_T; // @[Misc.scala:29:18] assign _statePtr_value_0_T = _T_78; // @[Misc.scala:29:18] wire _statePtr_value_1_T; // @[Misc.scala:29:18] assign _statePtr_value_1_T = _T_78; // @[Misc.scala:29:18] wire _comp_bits_buff_io_writes_in_valid_T; // @[Misc.scala:26:53] assign _comp_bits_buff_io_writes_in_valid_T = _T_78; // @[Misc.scala:26:53, :29:18] wire _statePtr_value_0_T_1 = _statePtr_value_0_T & all_new_state_valid; // @[Misc.scala:29:18] wire _statePtr_value_0_T_2 = _statePtr_value_0_T_1 & _comp_bits_buff_io_writes_in_ready; // @[Misc.scala:29:18] wire _statePtr_value_0_T_3 = valid_new_state & _statePtr_value_0_T_2; // @[Misc.scala:29:18] wire [15:0] _statePtr_value_0_T_4 = _statePtr_value_0_T_3 ? io_new_state_0_bits_0 : statePtr_value_0; // @[FSECompressorEncoder.scala:41:7, :52:31, :160:{29,46}] wire _statePtr_value_1_T_1 = _statePtr_value_1_T & all_new_state_valid; // @[Misc.scala:29:18] wire _statePtr_value_1_T_2 = _statePtr_value_1_T_1 & _comp_bits_buff_io_writes_in_ready; // @[Misc.scala:29:18] wire _statePtr_value_1_T_3 = valid_new_state_1 & _statePtr_value_1_T_2; // @[Misc.scala:29:18] wire [15:0] _statePtr_value_1_T_4 = _statePtr_value_1_T_3 ? io_new_state_1_bits_0 : statePtr_value_1; // @[FSECompressorEncoder.scala:41:7, :52:31, :160:{29,46}] wire _T_102 = io_table_log_valid_0 & flush; // @[Misc.scala:29:18] wire _io_lookup_done_valid_T; // @[Misc.scala:29:18] assign _io_lookup_done_valid_T = _T_102; // @[Misc.scala:29:18] wire _data_to_write_T; // @[Misc.scala:29:18] assign _data_to_write_T = _T_102; // @[Misc.scala:29:18] wire _comp_bits_buff_io_writes_in_valid_T_3; // @[Misc.scala:26:53] assign _comp_bits_buff_io_writes_in_valid_T_3 = _T_102; // @[Misc.scala:26:53, :29:18] wire _io_lookup_done_valid_T_1 = _io_lookup_done_valid_T; // @[Misc.scala:29:18] wire _io_lookup_done_valid_T_2 = _io_lookup_done_valid_T_1 & _comp_bits_buff_io_writes_in_ready; // @[Misc.scala:29:18] reg io_lookup_done_valid_REG; // @[FSECompressorEncoder.scala:175:34] assign io_lookup_done_valid_0 = io_lookup_done_valid_REG; // @[FSECompressorEncoder.scala:41:7, :175:34] assign _io_table_log_ready_T_1 = _io_table_log_ready_T & _comp_bits_buff_io_writes_in_ready; // @[Misc.scala:26:53] assign io_table_log_ready_0 = _io_table_log_ready_T_1; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg add_padding; // @[FSECompressorEncoder.scala:200:28] wire _T_121 = _comp_bits_buff_io_writes_in_ready & add_padding; // @[Misc.scala:29:18] wire [31:0] _cumul_nbBitsOut_1_T_1; // @[FSECompressorEncoder.scala:219:48] wire [31:0] cumul_nbBitsOut_1; // @[FSECompressorEncoder.scala:213:33] wire [31:0] _valid_bits_T_1 = _valid_bits_T ? nbBitsOut_1 : 32'h0; // @[FSECompressorEncoder.scala:114:27, :217:{28,33}] wire [31:0] valid_bits = flush ? nbBitsOut_1 : _valid_bits_T_1; // @[FSECompressorEncoder.scala:113:22, :114:27, :216:25, :217:28] wire [32:0] _cumul_nbBitsOut_1_T = {1'h0, cumul_nbBitsOut_0} + {1'h0, valid_bits}; // @[FSECompressorEncoder.scala:213:33, :216:25, :219:48] assign _cumul_nbBitsOut_1_T_1 = _cumul_nbBitsOut_1_T[31:0]; // @[FSECompressorEncoder.scala:219:48] assign cumul_nbBitsOut_1 = _cumul_nbBitsOut_1_T_1; // @[FSECompressorEncoder.scala:213:33, :219:48] wire [15:0] states_masked_0; // @[FSECompressorEncoder.scala:222:31] wire [15:0] states_masked_1; // @[FSECompressorEncoder.scala:222:31] wire [4:0] _mask_T = nbBitsOut_0[4:0]; // @[FSECompressorEncoder.scala:114:27, :224:36] wire [31:0] _mask_T_1 = 32'h1 << _mask_T; // @[FSECompressorEncoder.scala:224:{21,36}] wire [32:0] _mask_T_2 = {1'h0, _mask_T_1} - 33'h1; // @[FSECompressorEncoder.scala:224:{21,44}] wire [31:0] mask = _mask_T_2[31:0]; // @[FSECompressorEncoder.scala:224:44] wire [31:0] _states_masked_0_T = {16'h0, mask[15:0] & statePtr_value_0}; // @[FSECompressorEncoder.scala:52:31, :224:44, :225:43] assign states_masked_0 = _states_masked_0_T[15:0]; // @[FSECompressorEncoder.scala:222:31, :225:{22,43}] wire [4:0] _mask_T_3 = nbBitsOut_1[4:0]; // @[FSECompressorEncoder.scala:114:27, :224:36] wire [31:0] _mask_T_4 = 32'h1 << _mask_T_3; // @[FSECompressorEncoder.scala:224:{21,36}] wire [32:0] _mask_T_5 = {1'h0, _mask_T_4} - 33'h1; // @[FSECompressorEncoder.scala:224:{21,44}] wire [31:0] mask_1 = _mask_T_5[31:0]; // @[FSECompressorEncoder.scala:224:44] wire [31:0] _states_masked_1_T = {16'h0, mask_1[15:0] & statePtr_value_1}; // @[FSECompressorEncoder.scala:52:31, :224:44, :225:43] assign states_masked_1 = _states_masked_1_T[15:0]; // @[FSECompressorEncoder.scala:222:31, :225:{22,43}] wire [31:0] states_shifted_0; // @[FSECompressorEncoder.scala:230:32] wire [31:0] states_shifted_1; // @[FSECompressorEncoder.scala:230:32] assign states_shifted_0 = {16'h0, states_masked_0}; // @[FSECompressorEncoder.scala:222:31, :230:32, :231:21] wire [5:0] _states_shifted_1_T = cumul_nbBitsOut_0[5:0]; // @[FSECompressorEncoder.scala:213:33, :233:66] wire [78:0] _GEN_7 = {63'h0, states_masked_1}; // @[FSECompressorEncoder.scala:222:31, :233:43] wire [78:0] _states_shifted_1_T_1 = _GEN_7 << _states_shifted_1_T; // @[FSECompressorEncoder.scala:233:{43,66}] assign states_shifted_1 = _states_shifted_1_T_1[31:0]; // @[FSECompressorEncoder.scala:230:32, :233:{23,43}] wire [31:0] states_concat = states_shifted_0 | states_shifted_1; // @[FSECompressorEncoder.scala:230:32, :236:47] wire init_done = initCStateDone_0 & initCStateDone_1; // @[FSECompressorEncoder.scala:51:31, :237:43] wire [5:0] _states_concat_reverse_T = nbBitsOut_1[5:0]; // @[FSECompressorEncoder.scala:114:27, :241:83] wire [78:0] _states_concat_reverse_T_1 = {63'h0, states_masked_0} << _states_concat_reverse_T; // @[FSECompressorEncoder.scala:222:31, :233:43, :241:{68,83}] wire [78:0] states_concat_reverse = _GEN_7 | _states_concat_reverse_T_1; // @[FSECompressorEncoder.scala:233:43, :241:{48,68}] wire _data_to_write_T_1 = _data_to_write_T; // @[Misc.scala:29:18] wire _data_to_write_T_2 = _data_to_write_T_1 & _comp_bits_buff_io_writes_in_ready; // @[Misc.scala:29:18] wire _data_to_write_T_3 = _data_to_write_T_2 & track_consumed_bytes_odd; // @[Misc.scala:29:18] wire [78:0] data_to_write = _data_to_write_T_3 ? states_concat_reverse : {47'h0, states_concat}; // @[FSECompressorEncoder.scala:125:38, :236:47, :241:48, :248:{26,49}] reg [63:0] sent_bits; // @[FSECompressorEncoder.scala:251:26] wire [64:0] _sent_bits_T = {1'h0, sent_bits} + {58'h0, comp_bits_buff_io_writes_in_bits_validbits}; // @[FSECompressorEncoder.scala:251:26, :254:50, :264:46] wire [63:0] _sent_bits_T_1 = _sent_bits_T[63:0]; // @[FSECompressorEncoder.scala:254:50] wire [63:0] _sent_bits_T_2 = add_padding ? 64'h0 : _sent_bits_T_1; // @[FSECompressorEncoder.scala:200:28, :254:{21,50}] wire [63:0] extra_bits = {61'h0, sent_bits[2:0]}; // @[FSECompressorEncoder.scala:251:26, :257:30] wire [64:0] _padding_bits_T = 65'h8 - {1'h0, extra_bits}; // @[FSECompressorEncoder.scala:257:30, :258:26] wire [63:0] padding_bits = _padding_bits_T[63:0]; // @[FSECompressorEncoder.scala:258:26] wire _comp_bits_buff_io_writes_in_valid_T_1 = _comp_bits_buff_io_writes_in_valid_T & all_new_state_valid; // @[Misc.scala:26:53] wire _comp_bits_buff_io_writes_in_valid_T_2 = _comp_bits_buff_io_writes_in_valid_T_1 & init_done; // @[Misc.scala:26:53] wire _comp_bits_buff_io_writes_in_valid_T_4 = _comp_bits_buff_io_writes_in_valid_T_3; // @[Misc.scala:26:53] wire _comp_bits_buff_io_writes_in_valid_T_5 = _comp_bits_buff_io_writes_in_valid_T_2 | _comp_bits_buff_io_writes_in_valid_T_4; // @[Misc.scala:26:53] wire _comp_bits_buff_io_writes_in_valid_T_6 = _comp_bits_buff_io_writes_in_valid_T_5 | add_padding; // @[FSECompressorEncoder.scala:200:28, :260:109, :261:97] wire [78:0] _comp_bits_buff_io_writes_in_bits_data_T = add_padding ? 79'h1 : data_to_write; // @[FSECompressorEncoder.scala:200:28, :248:26, :263:47] wire [63:0] _comp_bits_buff_io_writes_in_bits_validbits_T = add_padding ? padding_bits : {32'h0, cumul_nbBitsOut_1}; // @[FSECompressorEncoder.scala:200:28, :213:33, :258:26, :264:52] assign comp_bits_buff_io_writes_in_bits_validbits = _comp_bits_buff_io_writes_in_bits_validbits_T[6:0]; // @[FSECompressorEncoder.scala:264:{46,52}] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] track_fse_total_written_bytes; // @[FSECompressorEncoder.scala:301:46] wire _T_133 = io_memwrites_out_ready_0 & io_memwrites_out_valid_0; // @[Decoupled.scala:51:35] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module FetchBuffer : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { pc : UInt<40>, next_pc : UInt<40>, next_fetch : UInt<40>, edge_inst : UInt<1>[1], insts : UInt<32>[4], exp_insts : UInt<32>[4], pcs : UInt<40>[4], sfbs : UInt<1>[4], sfb_masks : UInt<8>[4], sfb_dests : UInt<4>[4], shadowable_mask : UInt<1>[4], shadowed_mask : UInt<1>[4], cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_type : UInt<3>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ftq_idx : UInt<5>, mask : UInt<4>, br_mask : UInt<4>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, lhist : UInt<1>[1], xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, bp_debug_if_oh : UInt<1>[4], bp_xcpt_if_oh : UInt<1>[4], end_half : { valid : UInt<1>, bits : UInt<16>}, bpd_meta : UInt[1], fsrc : UInt<3>, tsrc : UInt<3>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[2]}}, flip clear : UInt<1>} reg fb_uop_ram : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[16], clock wire deq_vec : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[2][8] regreset head : UInt<8>, clock, reset, UInt<8>(0h1) regreset tail : UInt<16>, clock, reset, UInt<16>(0h1) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node _might_hit_head_T = bits(tail, 14, 0) node _might_hit_head_T_1 = bits(tail, 15, 15) node _might_hit_head_T_2 = cat(_might_hit_head_T, _might_hit_head_T_1) node _might_hit_head_T_3 = bits(_might_hit_head_T_2, 0, 0) node _might_hit_head_T_4 = bits(_might_hit_head_T_2, 1, 1) node _might_hit_head_T_5 = bits(_might_hit_head_T_2, 2, 2) node _might_hit_head_T_6 = bits(_might_hit_head_T_2, 3, 3) node _might_hit_head_T_7 = bits(_might_hit_head_T_2, 4, 4) node _might_hit_head_T_8 = bits(_might_hit_head_T_2, 5, 5) node _might_hit_head_T_9 = bits(_might_hit_head_T_2, 6, 6) node _might_hit_head_T_10 = bits(_might_hit_head_T_2, 7, 7) node _might_hit_head_T_11 = bits(_might_hit_head_T_2, 8, 8) node _might_hit_head_T_12 = bits(_might_hit_head_T_2, 9, 9) node _might_hit_head_T_13 = bits(_might_hit_head_T_2, 10, 10) node _might_hit_head_T_14 = bits(_might_hit_head_T_2, 11, 11) node _might_hit_head_T_15 = bits(_might_hit_head_T_2, 12, 12) node _might_hit_head_T_16 = bits(_might_hit_head_T_2, 13, 13) node _might_hit_head_T_17 = bits(_might_hit_head_T_2, 14, 14) node _might_hit_head_T_18 = bits(_might_hit_head_T_2, 15, 15) wire _might_hit_head_WIRE : UInt<1>[8] connect _might_hit_head_WIRE[0], _might_hit_head_T_3 connect _might_hit_head_WIRE[1], _might_hit_head_T_5 connect _might_hit_head_WIRE[2], _might_hit_head_T_7 connect _might_hit_head_WIRE[3], _might_hit_head_T_9 connect _might_hit_head_WIRE[4], _might_hit_head_T_11 connect _might_hit_head_WIRE[5], _might_hit_head_T_13 connect _might_hit_head_WIRE[6], _might_hit_head_T_15 connect _might_hit_head_WIRE[7], _might_hit_head_T_17 node might_hit_head_lo_lo = cat(_might_hit_head_WIRE[1], _might_hit_head_WIRE[0]) node might_hit_head_lo_hi = cat(_might_hit_head_WIRE[3], _might_hit_head_WIRE[2]) node might_hit_head_lo = cat(might_hit_head_lo_hi, might_hit_head_lo_lo) node might_hit_head_hi_lo = cat(_might_hit_head_WIRE[5], _might_hit_head_WIRE[4]) node might_hit_head_hi_hi = cat(_might_hit_head_WIRE[7], _might_hit_head_WIRE[6]) node might_hit_head_hi = cat(might_hit_head_hi_hi, might_hit_head_hi_lo) node _might_hit_head_T_19 = cat(might_hit_head_hi, might_hit_head_lo) node _might_hit_head_T_20 = bits(tail, 13, 0) node _might_hit_head_T_21 = bits(tail, 15, 14) node _might_hit_head_T_22 = cat(_might_hit_head_T_20, _might_hit_head_T_21) node _might_hit_head_T_23 = bits(_might_hit_head_T_22, 0, 0) node _might_hit_head_T_24 = bits(_might_hit_head_T_22, 1, 1) node _might_hit_head_T_25 = bits(_might_hit_head_T_22, 2, 2) node _might_hit_head_T_26 = bits(_might_hit_head_T_22, 3, 3) node _might_hit_head_T_27 = bits(_might_hit_head_T_22, 4, 4) node _might_hit_head_T_28 = bits(_might_hit_head_T_22, 5, 5) node _might_hit_head_T_29 = bits(_might_hit_head_T_22, 6, 6) node _might_hit_head_T_30 = bits(_might_hit_head_T_22, 7, 7) node _might_hit_head_T_31 = bits(_might_hit_head_T_22, 8, 8) node _might_hit_head_T_32 = bits(_might_hit_head_T_22, 9, 9) node _might_hit_head_T_33 = bits(_might_hit_head_T_22, 10, 10) node _might_hit_head_T_34 = bits(_might_hit_head_T_22, 11, 11) node _might_hit_head_T_35 = bits(_might_hit_head_T_22, 12, 12) node _might_hit_head_T_36 = bits(_might_hit_head_T_22, 13, 13) node _might_hit_head_T_37 = bits(_might_hit_head_T_22, 14, 14) node _might_hit_head_T_38 = bits(_might_hit_head_T_22, 15, 15) wire _might_hit_head_WIRE_1 : UInt<1>[8] connect _might_hit_head_WIRE_1[0], _might_hit_head_T_23 connect _might_hit_head_WIRE_1[1], _might_hit_head_T_25 connect _might_hit_head_WIRE_1[2], _might_hit_head_T_27 connect _might_hit_head_WIRE_1[3], _might_hit_head_T_29 connect _might_hit_head_WIRE_1[4], _might_hit_head_T_31 connect _might_hit_head_WIRE_1[5], _might_hit_head_T_33 connect _might_hit_head_WIRE_1[6], _might_hit_head_T_35 connect _might_hit_head_WIRE_1[7], _might_hit_head_T_37 node might_hit_head_lo_lo_1 = cat(_might_hit_head_WIRE_1[1], _might_hit_head_WIRE_1[0]) node might_hit_head_lo_hi_1 = cat(_might_hit_head_WIRE_1[3], _might_hit_head_WIRE_1[2]) node might_hit_head_lo_1 = cat(might_hit_head_lo_hi_1, might_hit_head_lo_lo_1) node might_hit_head_hi_lo_1 = cat(_might_hit_head_WIRE_1[5], _might_hit_head_WIRE_1[4]) node might_hit_head_hi_hi_1 = cat(_might_hit_head_WIRE_1[7], _might_hit_head_WIRE_1[6]) node might_hit_head_hi_1 = cat(might_hit_head_hi_hi_1, might_hit_head_hi_lo_1) node _might_hit_head_T_39 = cat(might_hit_head_hi_1, might_hit_head_lo_1) node _might_hit_head_T_40 = bits(tail, 12, 0) node _might_hit_head_T_41 = bits(tail, 15, 13) node _might_hit_head_T_42 = cat(_might_hit_head_T_40, _might_hit_head_T_41) node _might_hit_head_T_43 = bits(_might_hit_head_T_42, 0, 0) node _might_hit_head_T_44 = bits(_might_hit_head_T_42, 1, 1) node _might_hit_head_T_45 = bits(_might_hit_head_T_42, 2, 2) node _might_hit_head_T_46 = bits(_might_hit_head_T_42, 3, 3) node _might_hit_head_T_47 = bits(_might_hit_head_T_42, 4, 4) node _might_hit_head_T_48 = bits(_might_hit_head_T_42, 5, 5) node _might_hit_head_T_49 = bits(_might_hit_head_T_42, 6, 6) node _might_hit_head_T_50 = bits(_might_hit_head_T_42, 7, 7) node _might_hit_head_T_51 = bits(_might_hit_head_T_42, 8, 8) node _might_hit_head_T_52 = bits(_might_hit_head_T_42, 9, 9) node _might_hit_head_T_53 = bits(_might_hit_head_T_42, 10, 10) node _might_hit_head_T_54 = bits(_might_hit_head_T_42, 11, 11) node _might_hit_head_T_55 = bits(_might_hit_head_T_42, 12, 12) node _might_hit_head_T_56 = bits(_might_hit_head_T_42, 13, 13) node _might_hit_head_T_57 = bits(_might_hit_head_T_42, 14, 14) node _might_hit_head_T_58 = bits(_might_hit_head_T_42, 15, 15) wire _might_hit_head_WIRE_2 : UInt<1>[8] connect _might_hit_head_WIRE_2[0], _might_hit_head_T_43 connect _might_hit_head_WIRE_2[1], _might_hit_head_T_45 connect _might_hit_head_WIRE_2[2], _might_hit_head_T_47 connect _might_hit_head_WIRE_2[3], _might_hit_head_T_49 connect _might_hit_head_WIRE_2[4], _might_hit_head_T_51 connect _might_hit_head_WIRE_2[5], _might_hit_head_T_53 connect _might_hit_head_WIRE_2[6], _might_hit_head_T_55 connect _might_hit_head_WIRE_2[7], _might_hit_head_T_57 node might_hit_head_lo_lo_2 = cat(_might_hit_head_WIRE_2[1], _might_hit_head_WIRE_2[0]) node might_hit_head_lo_hi_2 = cat(_might_hit_head_WIRE_2[3], _might_hit_head_WIRE_2[2]) node might_hit_head_lo_2 = cat(might_hit_head_lo_hi_2, might_hit_head_lo_lo_2) node might_hit_head_hi_lo_2 = cat(_might_hit_head_WIRE_2[5], _might_hit_head_WIRE_2[4]) node might_hit_head_hi_hi_2 = cat(_might_hit_head_WIRE_2[7], _might_hit_head_WIRE_2[6]) node might_hit_head_hi_2 = cat(might_hit_head_hi_hi_2, might_hit_head_hi_lo_2) node _might_hit_head_T_59 = cat(might_hit_head_hi_2, might_hit_head_lo_2) node _might_hit_head_T_60 = and(head, _might_hit_head_T_19) node _might_hit_head_T_61 = and(head, _might_hit_head_T_39) node _might_hit_head_T_62 = and(head, _might_hit_head_T_59) node _might_hit_head_T_63 = or(_might_hit_head_T_60, _might_hit_head_T_61) node _might_hit_head_T_64 = or(_might_hit_head_T_63, _might_hit_head_T_62) node might_hit_head = orr(_might_hit_head_T_64) node _at_head_T = bits(tail, 0, 0) node _at_head_T_1 = bits(tail, 1, 1) node _at_head_T_2 = bits(tail, 2, 2) node _at_head_T_3 = bits(tail, 3, 3) node _at_head_T_4 = bits(tail, 4, 4) node _at_head_T_5 = bits(tail, 5, 5) node _at_head_T_6 = bits(tail, 6, 6) node _at_head_T_7 = bits(tail, 7, 7) node _at_head_T_8 = bits(tail, 8, 8) node _at_head_T_9 = bits(tail, 9, 9) node _at_head_T_10 = bits(tail, 10, 10) node _at_head_T_11 = bits(tail, 11, 11) node _at_head_T_12 = bits(tail, 12, 12) node _at_head_T_13 = bits(tail, 13, 13) node _at_head_T_14 = bits(tail, 14, 14) node _at_head_T_15 = bits(tail, 15, 15) wire _at_head_WIRE : UInt<1>[8] connect _at_head_WIRE[0], _at_head_T connect _at_head_WIRE[1], _at_head_T_2 connect _at_head_WIRE[2], _at_head_T_4 connect _at_head_WIRE[3], _at_head_T_6 connect _at_head_WIRE[4], _at_head_T_8 connect _at_head_WIRE[5], _at_head_T_10 connect _at_head_WIRE[6], _at_head_T_12 connect _at_head_WIRE[7], _at_head_T_14 node at_head_lo_lo = cat(_at_head_WIRE[1], _at_head_WIRE[0]) node at_head_lo_hi = cat(_at_head_WIRE[3], _at_head_WIRE[2]) node at_head_lo = cat(at_head_lo_hi, at_head_lo_lo) node at_head_hi_lo = cat(_at_head_WIRE[5], _at_head_WIRE[4]) node at_head_hi_hi = cat(_at_head_WIRE[7], _at_head_WIRE[6]) node at_head_hi = cat(at_head_hi_hi, at_head_hi_lo) node _at_head_T_16 = cat(at_head_hi, at_head_lo) node _at_head_T_17 = and(_at_head_T_16, head) node at_head = orr(_at_head_T_17) node _do_enq_T = and(at_head, maybe_full) node _do_enq_T_1 = or(_do_enq_T, might_hit_head) node do_enq = eq(_do_enq_T_1, UInt<1>(0h0)) connect io.enq.ready, do_enq wire in_mask : UInt<1>[4] wire in_uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[4] node _pc_T = not(io.enq.bits.pc) node _pc_T_1 = or(_pc_T, UInt<3>(0h7)) node _pc_T_2 = not(_pc_T_1) node _pc_T_3 = add(_pc_T_2, UInt<1>(0h0)) node pc = tail(_pc_T_3, 1) invalidate in_uops[0].debug_tsrc invalidate in_uops[0].debug_fsrc invalidate in_uops[0].bp_xcpt_if invalidate in_uops[0].bp_debug_if invalidate in_uops[0].xcpt_ma_if invalidate in_uops[0].xcpt_ae_if invalidate in_uops[0].xcpt_pf_if invalidate in_uops[0].fp_typ invalidate in_uops[0].fp_rm invalidate in_uops[0].fp_val invalidate in_uops[0].fcn_op invalidate in_uops[0].fcn_dw invalidate in_uops[0].frs3_en invalidate in_uops[0].lrs2_rtype invalidate in_uops[0].lrs1_rtype invalidate in_uops[0].dst_rtype invalidate in_uops[0].lrs3 invalidate in_uops[0].lrs2 invalidate in_uops[0].lrs1 invalidate in_uops[0].ldst invalidate in_uops[0].ldst_is_rs1 invalidate in_uops[0].csr_cmd invalidate in_uops[0].flush_on_commit invalidate in_uops[0].is_unique invalidate in_uops[0].uses_stq invalidate in_uops[0].uses_ldq invalidate in_uops[0].mem_signed invalidate in_uops[0].mem_size invalidate in_uops[0].mem_cmd invalidate in_uops[0].exc_cause invalidate in_uops[0].exception invalidate in_uops[0].stale_pdst invalidate in_uops[0].ppred_busy invalidate in_uops[0].prs3_busy invalidate in_uops[0].prs2_busy invalidate in_uops[0].prs1_busy invalidate in_uops[0].ppred invalidate in_uops[0].prs3 invalidate in_uops[0].prs2 invalidate in_uops[0].prs1 invalidate in_uops[0].pdst invalidate in_uops[0].rxq_idx invalidate in_uops[0].stq_idx invalidate in_uops[0].ldq_idx invalidate in_uops[0].rob_idx invalidate in_uops[0].fp_ctrl.vec invalidate in_uops[0].fp_ctrl.wflags invalidate in_uops[0].fp_ctrl.sqrt invalidate in_uops[0].fp_ctrl.div invalidate in_uops[0].fp_ctrl.fma invalidate in_uops[0].fp_ctrl.fastpipe invalidate in_uops[0].fp_ctrl.toint invalidate in_uops[0].fp_ctrl.fromint invalidate in_uops[0].fp_ctrl.typeTagOut invalidate in_uops[0].fp_ctrl.typeTagIn invalidate in_uops[0].fp_ctrl.swap23 invalidate in_uops[0].fp_ctrl.swap12 invalidate in_uops[0].fp_ctrl.ren3 invalidate in_uops[0].fp_ctrl.ren2 invalidate in_uops[0].fp_ctrl.ren1 invalidate in_uops[0].fp_ctrl.wen invalidate in_uops[0].fp_ctrl.ldst invalidate in_uops[0].op2_sel invalidate in_uops[0].op1_sel invalidate in_uops[0].imm_packed invalidate in_uops[0].pimm invalidate in_uops[0].imm_sel invalidate in_uops[0].imm_rename invalidate in_uops[0].taken invalidate in_uops[0].pc_lob invalidate in_uops[0].edge_inst invalidate in_uops[0].ftq_idx invalidate in_uops[0].is_mov invalidate in_uops[0].is_rocc invalidate in_uops[0].is_sys_pc2epc invalidate in_uops[0].is_eret invalidate in_uops[0].is_amo invalidate in_uops[0].is_sfence invalidate in_uops[0].is_fencei invalidate in_uops[0].is_fence invalidate in_uops[0].is_sfb invalidate in_uops[0].br_type invalidate in_uops[0].br_tag invalidate in_uops[0].br_mask invalidate in_uops[0].dis_col_sel invalidate in_uops[0].iw_p3_bypass_hint invalidate in_uops[0].iw_p2_bypass_hint invalidate in_uops[0].iw_p1_bypass_hint invalidate in_uops[0].iw_p2_speculative_child invalidate in_uops[0].iw_p1_speculative_child invalidate in_uops[0].iw_issued_partial_dgen invalidate in_uops[0].iw_issued_partial_agen invalidate in_uops[0].iw_issued invalidate in_uops[0].fu_code[0] invalidate in_uops[0].fu_code[1] invalidate in_uops[0].fu_code[2] invalidate in_uops[0].fu_code[3] invalidate in_uops[0].fu_code[4] invalidate in_uops[0].fu_code[5] invalidate in_uops[0].fu_code[6] invalidate in_uops[0].fu_code[7] invalidate in_uops[0].fu_code[8] invalidate in_uops[0].fu_code[9] invalidate in_uops[0].iq_type[0] invalidate in_uops[0].iq_type[1] invalidate in_uops[0].iq_type[2] invalidate in_uops[0].iq_type[3] invalidate in_uops[0].debug_pc invalidate in_uops[0].is_rvc invalidate in_uops[0].debug_inst invalidate in_uops[0].inst node _in_mask_0_T = bits(io.enq.bits.mask, 0, 0) node _in_mask_0_T_1 = and(io.enq.valid, _in_mask_0_T) connect in_mask[0], _in_mask_0_T_1 connect in_uops[0].edge_inst, UInt<1>(0h0) connect in_uops[0].debug_pc, pc connect in_uops[0].pc_lob, pc node _in_uops_0_is_sfb_T = or(io.enq.bits.sfbs[0], io.enq.bits.shadowed_mask[0]) connect in_uops[0].is_sfb, _in_uops_0_is_sfb_T when io.enq.bits.edge_inst[0] : node _in_uops_0_debug_pc_T = not(io.enq.bits.pc) node _in_uops_0_debug_pc_T_1 = or(_in_uops_0_debug_pc_T, UInt<3>(0h7)) node _in_uops_0_debug_pc_T_2 = not(_in_uops_0_debug_pc_T_1) node _in_uops_0_debug_pc_T_3 = add(_in_uops_0_debug_pc_T_2, UInt<1>(0h0)) node _in_uops_0_debug_pc_T_4 = tail(_in_uops_0_debug_pc_T_3, 1) node _in_uops_0_debug_pc_T_5 = sub(_in_uops_0_debug_pc_T_4, UInt<2>(0h2)) node _in_uops_0_debug_pc_T_6 = tail(_in_uops_0_debug_pc_T_5, 1) connect in_uops[0].debug_pc, _in_uops_0_debug_pc_T_6 node _in_uops_0_pc_lob_T = not(io.enq.bits.pc) node _in_uops_0_pc_lob_T_1 = or(_in_uops_0_pc_lob_T, UInt<3>(0h7)) node _in_uops_0_pc_lob_T_2 = not(_in_uops_0_pc_lob_T_1) node _in_uops_0_pc_lob_T_3 = add(_in_uops_0_pc_lob_T_2, UInt<1>(0h0)) node _in_uops_0_pc_lob_T_4 = tail(_in_uops_0_pc_lob_T_3, 1) connect in_uops[0].pc_lob, _in_uops_0_pc_lob_T_4 connect in_uops[0].edge_inst, UInt<1>(0h1) connect in_uops[0].ftq_idx, io.enq.bits.ftq_idx connect in_uops[0].inst, io.enq.bits.exp_insts[0] connect in_uops[0].debug_inst, io.enq.bits.insts[0] node _in_uops_0_is_rvc_T = bits(io.enq.bits.insts[0], 1, 0) node _in_uops_0_is_rvc_T_1 = neq(_in_uops_0_is_rvc_T, UInt<2>(0h3)) connect in_uops[0].is_rvc, _in_uops_0_is_rvc_T_1 node _in_uops_0_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<1>(0h0)) node _in_uops_0_taken_T_1 = and(_in_uops_0_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[0].taken, _in_uops_0_taken_T_1 connect in_uops[0].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[0].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[0].bp_debug_if, io.enq.bits.bp_debug_if_oh[0] connect in_uops[0].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[0] connect in_uops[0].debug_fsrc, io.enq.bits.fsrc node _pc_T_4 = not(io.enq.bits.pc) node _pc_T_5 = or(_pc_T_4, UInt<3>(0h7)) node _pc_T_6 = not(_pc_T_5) node _pc_T_7 = add(_pc_T_6, UInt<2>(0h2)) node pc_1 = tail(_pc_T_7, 1) invalidate in_uops[1].debug_tsrc invalidate in_uops[1].debug_fsrc invalidate in_uops[1].bp_xcpt_if invalidate in_uops[1].bp_debug_if invalidate in_uops[1].xcpt_ma_if invalidate in_uops[1].xcpt_ae_if invalidate in_uops[1].xcpt_pf_if invalidate in_uops[1].fp_typ invalidate in_uops[1].fp_rm invalidate in_uops[1].fp_val invalidate in_uops[1].fcn_op invalidate in_uops[1].fcn_dw invalidate in_uops[1].frs3_en invalidate in_uops[1].lrs2_rtype invalidate in_uops[1].lrs1_rtype invalidate in_uops[1].dst_rtype invalidate in_uops[1].lrs3 invalidate in_uops[1].lrs2 invalidate in_uops[1].lrs1 invalidate in_uops[1].ldst invalidate in_uops[1].ldst_is_rs1 invalidate in_uops[1].csr_cmd invalidate in_uops[1].flush_on_commit invalidate in_uops[1].is_unique invalidate in_uops[1].uses_stq invalidate in_uops[1].uses_ldq invalidate in_uops[1].mem_signed invalidate in_uops[1].mem_size invalidate in_uops[1].mem_cmd invalidate in_uops[1].exc_cause invalidate in_uops[1].exception invalidate in_uops[1].stale_pdst invalidate in_uops[1].ppred_busy invalidate in_uops[1].prs3_busy invalidate in_uops[1].prs2_busy invalidate in_uops[1].prs1_busy invalidate in_uops[1].ppred invalidate in_uops[1].prs3 invalidate in_uops[1].prs2 invalidate in_uops[1].prs1 invalidate in_uops[1].pdst invalidate in_uops[1].rxq_idx invalidate in_uops[1].stq_idx invalidate in_uops[1].ldq_idx invalidate in_uops[1].rob_idx invalidate in_uops[1].fp_ctrl.vec invalidate in_uops[1].fp_ctrl.wflags invalidate in_uops[1].fp_ctrl.sqrt invalidate in_uops[1].fp_ctrl.div invalidate in_uops[1].fp_ctrl.fma invalidate in_uops[1].fp_ctrl.fastpipe invalidate in_uops[1].fp_ctrl.toint invalidate in_uops[1].fp_ctrl.fromint invalidate in_uops[1].fp_ctrl.typeTagOut invalidate in_uops[1].fp_ctrl.typeTagIn invalidate in_uops[1].fp_ctrl.swap23 invalidate in_uops[1].fp_ctrl.swap12 invalidate in_uops[1].fp_ctrl.ren3 invalidate in_uops[1].fp_ctrl.ren2 invalidate in_uops[1].fp_ctrl.ren1 invalidate in_uops[1].fp_ctrl.wen invalidate in_uops[1].fp_ctrl.ldst invalidate in_uops[1].op2_sel invalidate in_uops[1].op1_sel invalidate in_uops[1].imm_packed invalidate in_uops[1].pimm invalidate in_uops[1].imm_sel invalidate in_uops[1].imm_rename invalidate in_uops[1].taken invalidate in_uops[1].pc_lob invalidate in_uops[1].edge_inst invalidate in_uops[1].ftq_idx invalidate in_uops[1].is_mov invalidate in_uops[1].is_rocc invalidate in_uops[1].is_sys_pc2epc invalidate in_uops[1].is_eret invalidate in_uops[1].is_amo invalidate in_uops[1].is_sfence invalidate in_uops[1].is_fencei invalidate in_uops[1].is_fence invalidate in_uops[1].is_sfb invalidate in_uops[1].br_type invalidate in_uops[1].br_tag invalidate in_uops[1].br_mask invalidate in_uops[1].dis_col_sel invalidate in_uops[1].iw_p3_bypass_hint invalidate in_uops[1].iw_p2_bypass_hint invalidate in_uops[1].iw_p1_bypass_hint invalidate in_uops[1].iw_p2_speculative_child invalidate in_uops[1].iw_p1_speculative_child invalidate in_uops[1].iw_issued_partial_dgen invalidate in_uops[1].iw_issued_partial_agen invalidate in_uops[1].iw_issued invalidate in_uops[1].fu_code[0] invalidate in_uops[1].fu_code[1] invalidate in_uops[1].fu_code[2] invalidate in_uops[1].fu_code[3] invalidate in_uops[1].fu_code[4] invalidate in_uops[1].fu_code[5] invalidate in_uops[1].fu_code[6] invalidate in_uops[1].fu_code[7] invalidate in_uops[1].fu_code[8] invalidate in_uops[1].fu_code[9] invalidate in_uops[1].iq_type[0] invalidate in_uops[1].iq_type[1] invalidate in_uops[1].iq_type[2] invalidate in_uops[1].iq_type[3] invalidate in_uops[1].debug_pc invalidate in_uops[1].is_rvc invalidate in_uops[1].debug_inst invalidate in_uops[1].inst node _in_mask_1_T = bits(io.enq.bits.mask, 1, 1) node _in_mask_1_T_1 = and(io.enq.valid, _in_mask_1_T) connect in_mask[1], _in_mask_1_T_1 connect in_uops[1].edge_inst, UInt<1>(0h0) connect in_uops[1].debug_pc, pc_1 connect in_uops[1].pc_lob, pc_1 node _in_uops_1_is_sfb_T = or(io.enq.bits.sfbs[1], io.enq.bits.shadowed_mask[1]) connect in_uops[1].is_sfb, _in_uops_1_is_sfb_T connect in_uops[1].ftq_idx, io.enq.bits.ftq_idx connect in_uops[1].inst, io.enq.bits.exp_insts[1] connect in_uops[1].debug_inst, io.enq.bits.insts[1] node _in_uops_1_is_rvc_T = bits(io.enq.bits.insts[1], 1, 0) node _in_uops_1_is_rvc_T_1 = neq(_in_uops_1_is_rvc_T, UInt<2>(0h3)) connect in_uops[1].is_rvc, _in_uops_1_is_rvc_T_1 node _in_uops_1_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<1>(0h1)) node _in_uops_1_taken_T_1 = and(_in_uops_1_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[1].taken, _in_uops_1_taken_T_1 connect in_uops[1].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[1].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[1].bp_debug_if, io.enq.bits.bp_debug_if_oh[1] connect in_uops[1].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[1] connect in_uops[1].debug_fsrc, io.enq.bits.fsrc node _pc_T_8 = not(io.enq.bits.pc) node _pc_T_9 = or(_pc_T_8, UInt<3>(0h7)) node _pc_T_10 = not(_pc_T_9) node _pc_T_11 = add(_pc_T_10, UInt<3>(0h4)) node pc_2 = tail(_pc_T_11, 1) invalidate in_uops[2].debug_tsrc invalidate in_uops[2].debug_fsrc invalidate in_uops[2].bp_xcpt_if invalidate in_uops[2].bp_debug_if invalidate in_uops[2].xcpt_ma_if invalidate in_uops[2].xcpt_ae_if invalidate in_uops[2].xcpt_pf_if invalidate in_uops[2].fp_typ invalidate in_uops[2].fp_rm invalidate in_uops[2].fp_val invalidate in_uops[2].fcn_op invalidate in_uops[2].fcn_dw invalidate in_uops[2].frs3_en invalidate in_uops[2].lrs2_rtype invalidate in_uops[2].lrs1_rtype invalidate in_uops[2].dst_rtype invalidate in_uops[2].lrs3 invalidate in_uops[2].lrs2 invalidate in_uops[2].lrs1 invalidate in_uops[2].ldst invalidate in_uops[2].ldst_is_rs1 invalidate in_uops[2].csr_cmd invalidate in_uops[2].flush_on_commit invalidate in_uops[2].is_unique invalidate in_uops[2].uses_stq invalidate in_uops[2].uses_ldq invalidate in_uops[2].mem_signed invalidate in_uops[2].mem_size invalidate in_uops[2].mem_cmd invalidate in_uops[2].exc_cause invalidate in_uops[2].exception invalidate in_uops[2].stale_pdst invalidate in_uops[2].ppred_busy invalidate in_uops[2].prs3_busy invalidate in_uops[2].prs2_busy invalidate in_uops[2].prs1_busy invalidate in_uops[2].ppred invalidate in_uops[2].prs3 invalidate in_uops[2].prs2 invalidate in_uops[2].prs1 invalidate in_uops[2].pdst invalidate in_uops[2].rxq_idx invalidate in_uops[2].stq_idx invalidate in_uops[2].ldq_idx invalidate in_uops[2].rob_idx invalidate in_uops[2].fp_ctrl.vec invalidate in_uops[2].fp_ctrl.wflags invalidate in_uops[2].fp_ctrl.sqrt invalidate in_uops[2].fp_ctrl.div invalidate in_uops[2].fp_ctrl.fma invalidate in_uops[2].fp_ctrl.fastpipe invalidate in_uops[2].fp_ctrl.toint invalidate in_uops[2].fp_ctrl.fromint invalidate in_uops[2].fp_ctrl.typeTagOut invalidate in_uops[2].fp_ctrl.typeTagIn invalidate in_uops[2].fp_ctrl.swap23 invalidate in_uops[2].fp_ctrl.swap12 invalidate in_uops[2].fp_ctrl.ren3 invalidate in_uops[2].fp_ctrl.ren2 invalidate in_uops[2].fp_ctrl.ren1 invalidate in_uops[2].fp_ctrl.wen invalidate in_uops[2].fp_ctrl.ldst invalidate in_uops[2].op2_sel invalidate in_uops[2].op1_sel invalidate in_uops[2].imm_packed invalidate in_uops[2].pimm invalidate in_uops[2].imm_sel invalidate in_uops[2].imm_rename invalidate in_uops[2].taken invalidate in_uops[2].pc_lob invalidate in_uops[2].edge_inst invalidate in_uops[2].ftq_idx invalidate in_uops[2].is_mov invalidate in_uops[2].is_rocc invalidate in_uops[2].is_sys_pc2epc invalidate in_uops[2].is_eret invalidate in_uops[2].is_amo invalidate in_uops[2].is_sfence invalidate in_uops[2].is_fencei invalidate in_uops[2].is_fence invalidate in_uops[2].is_sfb invalidate in_uops[2].br_type invalidate in_uops[2].br_tag invalidate in_uops[2].br_mask invalidate in_uops[2].dis_col_sel invalidate in_uops[2].iw_p3_bypass_hint invalidate in_uops[2].iw_p2_bypass_hint invalidate in_uops[2].iw_p1_bypass_hint invalidate in_uops[2].iw_p2_speculative_child invalidate in_uops[2].iw_p1_speculative_child invalidate in_uops[2].iw_issued_partial_dgen invalidate in_uops[2].iw_issued_partial_agen invalidate in_uops[2].iw_issued invalidate in_uops[2].fu_code[0] invalidate in_uops[2].fu_code[1] invalidate in_uops[2].fu_code[2] invalidate in_uops[2].fu_code[3] invalidate in_uops[2].fu_code[4] invalidate in_uops[2].fu_code[5] invalidate in_uops[2].fu_code[6] invalidate in_uops[2].fu_code[7] invalidate in_uops[2].fu_code[8] invalidate in_uops[2].fu_code[9] invalidate in_uops[2].iq_type[0] invalidate in_uops[2].iq_type[1] invalidate in_uops[2].iq_type[2] invalidate in_uops[2].iq_type[3] invalidate in_uops[2].debug_pc invalidate in_uops[2].is_rvc invalidate in_uops[2].debug_inst invalidate in_uops[2].inst node _in_mask_2_T = bits(io.enq.bits.mask, 2, 2) node _in_mask_2_T_1 = and(io.enq.valid, _in_mask_2_T) connect in_mask[2], _in_mask_2_T_1 connect in_uops[2].edge_inst, UInt<1>(0h0) connect in_uops[2].debug_pc, pc_2 connect in_uops[2].pc_lob, pc_2 node _in_uops_2_is_sfb_T = or(io.enq.bits.sfbs[2], io.enq.bits.shadowed_mask[2]) connect in_uops[2].is_sfb, _in_uops_2_is_sfb_T connect in_uops[2].ftq_idx, io.enq.bits.ftq_idx connect in_uops[2].inst, io.enq.bits.exp_insts[2] connect in_uops[2].debug_inst, io.enq.bits.insts[2] node _in_uops_2_is_rvc_T = bits(io.enq.bits.insts[2], 1, 0) node _in_uops_2_is_rvc_T_1 = neq(_in_uops_2_is_rvc_T, UInt<2>(0h3)) connect in_uops[2].is_rvc, _in_uops_2_is_rvc_T_1 node _in_uops_2_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<2>(0h2)) node _in_uops_2_taken_T_1 = and(_in_uops_2_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[2].taken, _in_uops_2_taken_T_1 connect in_uops[2].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[2].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[2].bp_debug_if, io.enq.bits.bp_debug_if_oh[2] connect in_uops[2].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[2] connect in_uops[2].debug_fsrc, io.enq.bits.fsrc node _pc_T_12 = not(io.enq.bits.pc) node _pc_T_13 = or(_pc_T_12, UInt<3>(0h7)) node _pc_T_14 = not(_pc_T_13) node _pc_T_15 = add(_pc_T_14, UInt<3>(0h6)) node pc_3 = tail(_pc_T_15, 1) invalidate in_uops[3].debug_tsrc invalidate in_uops[3].debug_fsrc invalidate in_uops[3].bp_xcpt_if invalidate in_uops[3].bp_debug_if invalidate in_uops[3].xcpt_ma_if invalidate in_uops[3].xcpt_ae_if invalidate in_uops[3].xcpt_pf_if invalidate in_uops[3].fp_typ invalidate in_uops[3].fp_rm invalidate in_uops[3].fp_val invalidate in_uops[3].fcn_op invalidate in_uops[3].fcn_dw invalidate in_uops[3].frs3_en invalidate in_uops[3].lrs2_rtype invalidate in_uops[3].lrs1_rtype invalidate in_uops[3].dst_rtype invalidate in_uops[3].lrs3 invalidate in_uops[3].lrs2 invalidate in_uops[3].lrs1 invalidate in_uops[3].ldst invalidate in_uops[3].ldst_is_rs1 invalidate in_uops[3].csr_cmd invalidate in_uops[3].flush_on_commit invalidate in_uops[3].is_unique invalidate in_uops[3].uses_stq invalidate in_uops[3].uses_ldq invalidate in_uops[3].mem_signed invalidate in_uops[3].mem_size invalidate in_uops[3].mem_cmd invalidate in_uops[3].exc_cause invalidate in_uops[3].exception invalidate in_uops[3].stale_pdst invalidate in_uops[3].ppred_busy invalidate in_uops[3].prs3_busy invalidate in_uops[3].prs2_busy invalidate in_uops[3].prs1_busy invalidate in_uops[3].ppred invalidate in_uops[3].prs3 invalidate in_uops[3].prs2 invalidate in_uops[3].prs1 invalidate in_uops[3].pdst invalidate in_uops[3].rxq_idx invalidate in_uops[3].stq_idx invalidate in_uops[3].ldq_idx invalidate in_uops[3].rob_idx invalidate in_uops[3].fp_ctrl.vec invalidate in_uops[3].fp_ctrl.wflags invalidate in_uops[3].fp_ctrl.sqrt invalidate in_uops[3].fp_ctrl.div invalidate in_uops[3].fp_ctrl.fma invalidate in_uops[3].fp_ctrl.fastpipe invalidate in_uops[3].fp_ctrl.toint invalidate in_uops[3].fp_ctrl.fromint invalidate in_uops[3].fp_ctrl.typeTagOut invalidate in_uops[3].fp_ctrl.typeTagIn invalidate in_uops[3].fp_ctrl.swap23 invalidate in_uops[3].fp_ctrl.swap12 invalidate in_uops[3].fp_ctrl.ren3 invalidate in_uops[3].fp_ctrl.ren2 invalidate in_uops[3].fp_ctrl.ren1 invalidate in_uops[3].fp_ctrl.wen invalidate in_uops[3].fp_ctrl.ldst invalidate in_uops[3].op2_sel invalidate in_uops[3].op1_sel invalidate in_uops[3].imm_packed invalidate in_uops[3].pimm invalidate in_uops[3].imm_sel invalidate in_uops[3].imm_rename invalidate in_uops[3].taken invalidate in_uops[3].pc_lob invalidate in_uops[3].edge_inst invalidate in_uops[3].ftq_idx invalidate in_uops[3].is_mov invalidate in_uops[3].is_rocc invalidate in_uops[3].is_sys_pc2epc invalidate in_uops[3].is_eret invalidate in_uops[3].is_amo invalidate in_uops[3].is_sfence invalidate in_uops[3].is_fencei invalidate in_uops[3].is_fence invalidate in_uops[3].is_sfb invalidate in_uops[3].br_type invalidate in_uops[3].br_tag invalidate in_uops[3].br_mask invalidate in_uops[3].dis_col_sel invalidate in_uops[3].iw_p3_bypass_hint invalidate in_uops[3].iw_p2_bypass_hint invalidate in_uops[3].iw_p1_bypass_hint invalidate in_uops[3].iw_p2_speculative_child invalidate in_uops[3].iw_p1_speculative_child invalidate in_uops[3].iw_issued_partial_dgen invalidate in_uops[3].iw_issued_partial_agen invalidate in_uops[3].iw_issued invalidate in_uops[3].fu_code[0] invalidate in_uops[3].fu_code[1] invalidate in_uops[3].fu_code[2] invalidate in_uops[3].fu_code[3] invalidate in_uops[3].fu_code[4] invalidate in_uops[3].fu_code[5] invalidate in_uops[3].fu_code[6] invalidate in_uops[3].fu_code[7] invalidate in_uops[3].fu_code[8] invalidate in_uops[3].fu_code[9] invalidate in_uops[3].iq_type[0] invalidate in_uops[3].iq_type[1] invalidate in_uops[3].iq_type[2] invalidate in_uops[3].iq_type[3] invalidate in_uops[3].debug_pc invalidate in_uops[3].is_rvc invalidate in_uops[3].debug_inst invalidate in_uops[3].inst node _in_mask_3_T = bits(io.enq.bits.mask, 3, 3) node _in_mask_3_T_1 = and(io.enq.valid, _in_mask_3_T) connect in_mask[3], _in_mask_3_T_1 connect in_uops[3].edge_inst, UInt<1>(0h0) connect in_uops[3].debug_pc, pc_3 connect in_uops[3].pc_lob, pc_3 node _in_uops_3_is_sfb_T = or(io.enq.bits.sfbs[3], io.enq.bits.shadowed_mask[3]) connect in_uops[3].is_sfb, _in_uops_3_is_sfb_T connect in_uops[3].ftq_idx, io.enq.bits.ftq_idx connect in_uops[3].inst, io.enq.bits.exp_insts[3] connect in_uops[3].debug_inst, io.enq.bits.insts[3] node _in_uops_3_is_rvc_T = bits(io.enq.bits.insts[3], 1, 0) node _in_uops_3_is_rvc_T_1 = neq(_in_uops_3_is_rvc_T, UInt<2>(0h3)) connect in_uops[3].is_rvc, _in_uops_3_is_rvc_T_1 node _in_uops_3_taken_T = eq(io.enq.bits.cfi_idx.bits, UInt<2>(0h3)) node _in_uops_3_taken_T_1 = and(_in_uops_3_taken_T, io.enq.bits.cfi_idx.valid) connect in_uops[3].taken, _in_uops_3_taken_T_1 connect in_uops[3].xcpt_pf_if, io.enq.bits.xcpt_pf_if connect in_uops[3].xcpt_ae_if, io.enq.bits.xcpt_ae_if connect in_uops[3].bp_debug_if, io.enq.bits.bp_debug_if_oh[3] connect in_uops[3].bp_xcpt_if, io.enq.bits.bp_xcpt_if_oh[3] connect in_uops[3].debug_fsrc, io.enq.bits.fsrc wire enq_idxs : UInt<16>[4] connect enq_idxs[0], tail node _T = bits(tail, 14, 0) node _T_1 = bits(tail, 15, 15) node _T_2 = cat(_T, _T_1) node _T_3 = mux(in_mask[0], _T_2, tail) connect enq_idxs[1], _T_3 node _T_4 = bits(_T_3, 14, 0) node _T_5 = bits(_T_3, 15, 15) node _T_6 = cat(_T_4, _T_5) node _T_7 = mux(in_mask[1], _T_6, _T_3) connect enq_idxs[2], _T_7 node _T_8 = bits(_T_7, 14, 0) node _T_9 = bits(_T_7, 15, 15) node _T_10 = cat(_T_8, _T_9) node _T_11 = mux(in_mask[2], _T_10, _T_7) connect enq_idxs[3], _T_11 node _T_12 = bits(_T_11, 14, 0) node _T_13 = bits(_T_11, 15, 15) node _T_14 = cat(_T_12, _T_13) node _T_15 = mux(in_mask[3], _T_14, _T_11) node _T_16 = and(do_enq, in_mask[0]) node _T_17 = bits(enq_idxs[0], 0, 0) node _T_18 = and(_T_16, _T_17) when _T_18 : connect fb_uop_ram[0], in_uops[0] node _T_19 = and(do_enq, in_mask[0]) node _T_20 = bits(enq_idxs[0], 1, 1) node _T_21 = and(_T_19, _T_20) when _T_21 : connect fb_uop_ram[1], in_uops[0] node _T_22 = and(do_enq, in_mask[0]) node _T_23 = bits(enq_idxs[0], 2, 2) node _T_24 = and(_T_22, _T_23) when _T_24 : connect fb_uop_ram[2], in_uops[0] node _T_25 = and(do_enq, in_mask[0]) node _T_26 = bits(enq_idxs[0], 3, 3) node _T_27 = and(_T_25, _T_26) when _T_27 : connect fb_uop_ram[3], in_uops[0] node _T_28 = and(do_enq, in_mask[0]) node _T_29 = bits(enq_idxs[0], 4, 4) node _T_30 = and(_T_28, _T_29) when _T_30 : connect fb_uop_ram[4], in_uops[0] node _T_31 = and(do_enq, in_mask[0]) node _T_32 = bits(enq_idxs[0], 5, 5) node _T_33 = and(_T_31, _T_32) when _T_33 : connect fb_uop_ram[5], in_uops[0] node _T_34 = and(do_enq, in_mask[0]) node _T_35 = bits(enq_idxs[0], 6, 6) node _T_36 = and(_T_34, _T_35) when _T_36 : connect fb_uop_ram[6], in_uops[0] node _T_37 = and(do_enq, in_mask[0]) node _T_38 = bits(enq_idxs[0], 7, 7) node _T_39 = and(_T_37, _T_38) when _T_39 : connect fb_uop_ram[7], in_uops[0] node _T_40 = and(do_enq, in_mask[0]) node _T_41 = bits(enq_idxs[0], 8, 8) node _T_42 = and(_T_40, _T_41) when _T_42 : connect fb_uop_ram[8], in_uops[0] node _T_43 = and(do_enq, in_mask[0]) node _T_44 = bits(enq_idxs[0], 9, 9) node _T_45 = and(_T_43, _T_44) when _T_45 : connect fb_uop_ram[9], in_uops[0] node _T_46 = and(do_enq, in_mask[0]) node _T_47 = bits(enq_idxs[0], 10, 10) node _T_48 = and(_T_46, _T_47) when _T_48 : connect fb_uop_ram[10], in_uops[0] node _T_49 = and(do_enq, in_mask[0]) node _T_50 = bits(enq_idxs[0], 11, 11) node _T_51 = and(_T_49, _T_50) when _T_51 : connect fb_uop_ram[11], in_uops[0] node _T_52 = and(do_enq, in_mask[0]) node _T_53 = bits(enq_idxs[0], 12, 12) node _T_54 = and(_T_52, _T_53) when _T_54 : connect fb_uop_ram[12], in_uops[0] node _T_55 = and(do_enq, in_mask[0]) node _T_56 = bits(enq_idxs[0], 13, 13) node _T_57 = and(_T_55, _T_56) when _T_57 : connect fb_uop_ram[13], in_uops[0] node _T_58 = and(do_enq, in_mask[0]) node _T_59 = bits(enq_idxs[0], 14, 14) node _T_60 = and(_T_58, _T_59) when _T_60 : connect fb_uop_ram[14], in_uops[0] node _T_61 = and(do_enq, in_mask[0]) node _T_62 = bits(enq_idxs[0], 15, 15) node _T_63 = and(_T_61, _T_62) when _T_63 : connect fb_uop_ram[15], in_uops[0] node _T_64 = and(do_enq, in_mask[1]) node _T_65 = bits(enq_idxs[1], 0, 0) node _T_66 = and(_T_64, _T_65) when _T_66 : connect fb_uop_ram[0], in_uops[1] node _T_67 = and(do_enq, in_mask[1]) node _T_68 = bits(enq_idxs[1], 1, 1) node _T_69 = and(_T_67, _T_68) when _T_69 : connect fb_uop_ram[1], in_uops[1] node _T_70 = and(do_enq, in_mask[1]) node _T_71 = bits(enq_idxs[1], 2, 2) node _T_72 = and(_T_70, _T_71) when _T_72 : connect fb_uop_ram[2], in_uops[1] node _T_73 = and(do_enq, in_mask[1]) node _T_74 = bits(enq_idxs[1], 3, 3) node _T_75 = and(_T_73, _T_74) when _T_75 : connect fb_uop_ram[3], in_uops[1] node _T_76 = and(do_enq, in_mask[1]) node _T_77 = bits(enq_idxs[1], 4, 4) node _T_78 = and(_T_76, _T_77) when _T_78 : connect fb_uop_ram[4], in_uops[1] node _T_79 = and(do_enq, in_mask[1]) node _T_80 = bits(enq_idxs[1], 5, 5) node _T_81 = and(_T_79, _T_80) when _T_81 : connect fb_uop_ram[5], in_uops[1] node _T_82 = and(do_enq, in_mask[1]) node _T_83 = bits(enq_idxs[1], 6, 6) node _T_84 = and(_T_82, _T_83) when _T_84 : connect fb_uop_ram[6], in_uops[1] node _T_85 = and(do_enq, in_mask[1]) node _T_86 = bits(enq_idxs[1], 7, 7) node _T_87 = and(_T_85, _T_86) when _T_87 : connect fb_uop_ram[7], in_uops[1] node _T_88 = and(do_enq, in_mask[1]) node _T_89 = bits(enq_idxs[1], 8, 8) node _T_90 = and(_T_88, _T_89) when _T_90 : connect fb_uop_ram[8], in_uops[1] node _T_91 = and(do_enq, in_mask[1]) node _T_92 = bits(enq_idxs[1], 9, 9) node _T_93 = and(_T_91, _T_92) when _T_93 : connect fb_uop_ram[9], in_uops[1] node _T_94 = and(do_enq, in_mask[1]) node _T_95 = bits(enq_idxs[1], 10, 10) node _T_96 = and(_T_94, _T_95) when _T_96 : connect fb_uop_ram[10], in_uops[1] node _T_97 = and(do_enq, in_mask[1]) node _T_98 = bits(enq_idxs[1], 11, 11) node _T_99 = and(_T_97, _T_98) when _T_99 : connect fb_uop_ram[11], in_uops[1] node _T_100 = and(do_enq, in_mask[1]) node _T_101 = bits(enq_idxs[1], 12, 12) node _T_102 = and(_T_100, _T_101) when _T_102 : connect fb_uop_ram[12], in_uops[1] node _T_103 = and(do_enq, in_mask[1]) node _T_104 = bits(enq_idxs[1], 13, 13) node _T_105 = and(_T_103, _T_104) when _T_105 : connect fb_uop_ram[13], in_uops[1] node _T_106 = and(do_enq, in_mask[1]) node _T_107 = bits(enq_idxs[1], 14, 14) node _T_108 = and(_T_106, _T_107) when _T_108 : connect fb_uop_ram[14], in_uops[1] node _T_109 = and(do_enq, in_mask[1]) node _T_110 = bits(enq_idxs[1], 15, 15) node _T_111 = and(_T_109, _T_110) when _T_111 : connect fb_uop_ram[15], in_uops[1] node _T_112 = and(do_enq, in_mask[2]) node _T_113 = bits(enq_idxs[2], 0, 0) node _T_114 = and(_T_112, _T_113) when _T_114 : connect fb_uop_ram[0], in_uops[2] node _T_115 = and(do_enq, in_mask[2]) node _T_116 = bits(enq_idxs[2], 1, 1) node _T_117 = and(_T_115, _T_116) when _T_117 : connect fb_uop_ram[1], in_uops[2] node _T_118 = and(do_enq, in_mask[2]) node _T_119 = bits(enq_idxs[2], 2, 2) node _T_120 = and(_T_118, _T_119) when _T_120 : connect fb_uop_ram[2], in_uops[2] node _T_121 = and(do_enq, in_mask[2]) node _T_122 = bits(enq_idxs[2], 3, 3) node _T_123 = and(_T_121, _T_122) when _T_123 : connect fb_uop_ram[3], in_uops[2] node _T_124 = and(do_enq, in_mask[2]) node _T_125 = bits(enq_idxs[2], 4, 4) node _T_126 = and(_T_124, _T_125) when _T_126 : connect fb_uop_ram[4], in_uops[2] node _T_127 = and(do_enq, in_mask[2]) node _T_128 = bits(enq_idxs[2], 5, 5) node _T_129 = and(_T_127, _T_128) when _T_129 : connect fb_uop_ram[5], in_uops[2] node _T_130 = and(do_enq, in_mask[2]) node _T_131 = bits(enq_idxs[2], 6, 6) node _T_132 = and(_T_130, _T_131) when _T_132 : connect fb_uop_ram[6], in_uops[2] node _T_133 = and(do_enq, in_mask[2]) node _T_134 = bits(enq_idxs[2], 7, 7) node _T_135 = and(_T_133, _T_134) when _T_135 : connect fb_uop_ram[7], in_uops[2] node _T_136 = and(do_enq, in_mask[2]) node _T_137 = bits(enq_idxs[2], 8, 8) node _T_138 = and(_T_136, _T_137) when _T_138 : connect fb_uop_ram[8], in_uops[2] node _T_139 = and(do_enq, in_mask[2]) node _T_140 = bits(enq_idxs[2], 9, 9) node _T_141 = and(_T_139, _T_140) when _T_141 : connect fb_uop_ram[9], in_uops[2] node _T_142 = and(do_enq, in_mask[2]) node _T_143 = bits(enq_idxs[2], 10, 10) node _T_144 = and(_T_142, _T_143) when _T_144 : connect fb_uop_ram[10], in_uops[2] node _T_145 = and(do_enq, in_mask[2]) node _T_146 = bits(enq_idxs[2], 11, 11) node _T_147 = and(_T_145, _T_146) when _T_147 : connect fb_uop_ram[11], in_uops[2] node _T_148 = and(do_enq, in_mask[2]) node _T_149 = bits(enq_idxs[2], 12, 12) node _T_150 = and(_T_148, _T_149) when _T_150 : connect fb_uop_ram[12], in_uops[2] node _T_151 = and(do_enq, in_mask[2]) node _T_152 = bits(enq_idxs[2], 13, 13) node _T_153 = and(_T_151, _T_152) when _T_153 : connect fb_uop_ram[13], in_uops[2] node _T_154 = and(do_enq, in_mask[2]) node _T_155 = bits(enq_idxs[2], 14, 14) node _T_156 = and(_T_154, _T_155) when _T_156 : connect fb_uop_ram[14], in_uops[2] node _T_157 = and(do_enq, in_mask[2]) node _T_158 = bits(enq_idxs[2], 15, 15) node _T_159 = and(_T_157, _T_158) when _T_159 : connect fb_uop_ram[15], in_uops[2] node _T_160 = and(do_enq, in_mask[3]) node _T_161 = bits(enq_idxs[3], 0, 0) node _T_162 = and(_T_160, _T_161) when _T_162 : connect fb_uop_ram[0], in_uops[3] node _T_163 = and(do_enq, in_mask[3]) node _T_164 = bits(enq_idxs[3], 1, 1) node _T_165 = and(_T_163, _T_164) when _T_165 : connect fb_uop_ram[1], in_uops[3] node _T_166 = and(do_enq, in_mask[3]) node _T_167 = bits(enq_idxs[3], 2, 2) node _T_168 = and(_T_166, _T_167) when _T_168 : connect fb_uop_ram[2], in_uops[3] node _T_169 = and(do_enq, in_mask[3]) node _T_170 = bits(enq_idxs[3], 3, 3) node _T_171 = and(_T_169, _T_170) when _T_171 : connect fb_uop_ram[3], in_uops[3] node _T_172 = and(do_enq, in_mask[3]) node _T_173 = bits(enq_idxs[3], 4, 4) node _T_174 = and(_T_172, _T_173) when _T_174 : connect fb_uop_ram[4], in_uops[3] node _T_175 = and(do_enq, in_mask[3]) node _T_176 = bits(enq_idxs[3], 5, 5) node _T_177 = and(_T_175, _T_176) when _T_177 : connect fb_uop_ram[5], in_uops[3] node _T_178 = and(do_enq, in_mask[3]) node _T_179 = bits(enq_idxs[3], 6, 6) node _T_180 = and(_T_178, _T_179) when _T_180 : connect fb_uop_ram[6], in_uops[3] node _T_181 = and(do_enq, in_mask[3]) node _T_182 = bits(enq_idxs[3], 7, 7) node _T_183 = and(_T_181, _T_182) when _T_183 : connect fb_uop_ram[7], in_uops[3] node _T_184 = and(do_enq, in_mask[3]) node _T_185 = bits(enq_idxs[3], 8, 8) node _T_186 = and(_T_184, _T_185) when _T_186 : connect fb_uop_ram[8], in_uops[3] node _T_187 = and(do_enq, in_mask[3]) node _T_188 = bits(enq_idxs[3], 9, 9) node _T_189 = and(_T_187, _T_188) when _T_189 : connect fb_uop_ram[9], in_uops[3] node _T_190 = and(do_enq, in_mask[3]) node _T_191 = bits(enq_idxs[3], 10, 10) node _T_192 = and(_T_190, _T_191) when _T_192 : connect fb_uop_ram[10], in_uops[3] node _T_193 = and(do_enq, in_mask[3]) node _T_194 = bits(enq_idxs[3], 11, 11) node _T_195 = and(_T_193, _T_194) when _T_195 : connect fb_uop_ram[11], in_uops[3] node _T_196 = and(do_enq, in_mask[3]) node _T_197 = bits(enq_idxs[3], 12, 12) node _T_198 = and(_T_196, _T_197) when _T_198 : connect fb_uop_ram[12], in_uops[3] node _T_199 = and(do_enq, in_mask[3]) node _T_200 = bits(enq_idxs[3], 13, 13) node _T_201 = and(_T_199, _T_200) when _T_201 : connect fb_uop_ram[13], in_uops[3] node _T_202 = and(do_enq, in_mask[3]) node _T_203 = bits(enq_idxs[3], 14, 14) node _T_204 = and(_T_202, _T_203) when _T_204 : connect fb_uop_ram[14], in_uops[3] node _T_205 = and(do_enq, in_mask[3]) node _T_206 = bits(enq_idxs[3], 15, 15) node _T_207 = and(_T_205, _T_206) when _T_207 : connect fb_uop_ram[15], in_uops[3] node _tail_collisions_T = bits(head, 0, 0) node _tail_collisions_T_1 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_2 = or(_tail_collisions_T_1, UInt<1>(0h0)) node _tail_collisions_T_3 = and(_tail_collisions_T, _tail_collisions_T_2) node _tail_collisions_T_4 = bits(head, 0, 0) node _tail_collisions_T_5 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_6 = or(_tail_collisions_T_5, UInt<1>(0h1)) node _tail_collisions_T_7 = and(_tail_collisions_T_4, _tail_collisions_T_6) node _tail_collisions_T_8 = bits(head, 1, 1) node _tail_collisions_T_9 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_10 = or(_tail_collisions_T_9, UInt<1>(0h0)) node _tail_collisions_T_11 = and(_tail_collisions_T_8, _tail_collisions_T_10) node _tail_collisions_T_12 = bits(head, 1, 1) node _tail_collisions_T_13 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_14 = or(_tail_collisions_T_13, UInt<1>(0h1)) node _tail_collisions_T_15 = and(_tail_collisions_T_12, _tail_collisions_T_14) node _tail_collisions_T_16 = bits(head, 2, 2) node _tail_collisions_T_17 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_18 = or(_tail_collisions_T_17, UInt<1>(0h0)) node _tail_collisions_T_19 = and(_tail_collisions_T_16, _tail_collisions_T_18) node _tail_collisions_T_20 = bits(head, 2, 2) node _tail_collisions_T_21 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_22 = or(_tail_collisions_T_21, UInt<1>(0h1)) node _tail_collisions_T_23 = and(_tail_collisions_T_20, _tail_collisions_T_22) node _tail_collisions_T_24 = bits(head, 3, 3) node _tail_collisions_T_25 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_26 = or(_tail_collisions_T_25, UInt<1>(0h0)) node _tail_collisions_T_27 = and(_tail_collisions_T_24, _tail_collisions_T_26) node _tail_collisions_T_28 = bits(head, 3, 3) node _tail_collisions_T_29 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_30 = or(_tail_collisions_T_29, UInt<1>(0h1)) node _tail_collisions_T_31 = and(_tail_collisions_T_28, _tail_collisions_T_30) node _tail_collisions_T_32 = bits(head, 4, 4) node _tail_collisions_T_33 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_34 = or(_tail_collisions_T_33, UInt<1>(0h0)) node _tail_collisions_T_35 = and(_tail_collisions_T_32, _tail_collisions_T_34) node _tail_collisions_T_36 = bits(head, 4, 4) node _tail_collisions_T_37 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_38 = or(_tail_collisions_T_37, UInt<1>(0h1)) node _tail_collisions_T_39 = and(_tail_collisions_T_36, _tail_collisions_T_38) node _tail_collisions_T_40 = bits(head, 5, 5) node _tail_collisions_T_41 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_42 = or(_tail_collisions_T_41, UInt<1>(0h0)) node _tail_collisions_T_43 = and(_tail_collisions_T_40, _tail_collisions_T_42) node _tail_collisions_T_44 = bits(head, 5, 5) node _tail_collisions_T_45 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_46 = or(_tail_collisions_T_45, UInt<1>(0h1)) node _tail_collisions_T_47 = and(_tail_collisions_T_44, _tail_collisions_T_46) node _tail_collisions_T_48 = bits(head, 6, 6) node _tail_collisions_T_49 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_50 = or(_tail_collisions_T_49, UInt<1>(0h0)) node _tail_collisions_T_51 = and(_tail_collisions_T_48, _tail_collisions_T_50) node _tail_collisions_T_52 = bits(head, 6, 6) node _tail_collisions_T_53 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_54 = or(_tail_collisions_T_53, UInt<1>(0h1)) node _tail_collisions_T_55 = and(_tail_collisions_T_52, _tail_collisions_T_54) node _tail_collisions_T_56 = bits(head, 7, 7) node _tail_collisions_T_57 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_58 = or(_tail_collisions_T_57, UInt<1>(0h0)) node _tail_collisions_T_59 = and(_tail_collisions_T_56, _tail_collisions_T_58) node _tail_collisions_T_60 = bits(head, 7, 7) node _tail_collisions_T_61 = eq(maybe_full, UInt<1>(0h0)) node _tail_collisions_T_62 = or(_tail_collisions_T_61, UInt<1>(0h1)) node _tail_collisions_T_63 = and(_tail_collisions_T_60, _tail_collisions_T_62) wire _tail_collisions_WIRE : UInt<1>[16] connect _tail_collisions_WIRE[0], _tail_collisions_T_3 connect _tail_collisions_WIRE[1], _tail_collisions_T_7 connect _tail_collisions_WIRE[2], _tail_collisions_T_11 connect _tail_collisions_WIRE[3], _tail_collisions_T_15 connect _tail_collisions_WIRE[4], _tail_collisions_T_19 connect _tail_collisions_WIRE[5], _tail_collisions_T_23 connect _tail_collisions_WIRE[6], _tail_collisions_T_27 connect _tail_collisions_WIRE[7], _tail_collisions_T_31 connect _tail_collisions_WIRE[8], _tail_collisions_T_35 connect _tail_collisions_WIRE[9], _tail_collisions_T_39 connect _tail_collisions_WIRE[10], _tail_collisions_T_43 connect _tail_collisions_WIRE[11], _tail_collisions_T_47 connect _tail_collisions_WIRE[12], _tail_collisions_T_51 connect _tail_collisions_WIRE[13], _tail_collisions_T_55 connect _tail_collisions_WIRE[14], _tail_collisions_T_59 connect _tail_collisions_WIRE[15], _tail_collisions_T_63 node tail_collisions_lo_lo_lo = cat(_tail_collisions_WIRE[1], _tail_collisions_WIRE[0]) node tail_collisions_lo_lo_hi = cat(_tail_collisions_WIRE[3], _tail_collisions_WIRE[2]) node tail_collisions_lo_lo = cat(tail_collisions_lo_lo_hi, tail_collisions_lo_lo_lo) node tail_collisions_lo_hi_lo = cat(_tail_collisions_WIRE[5], _tail_collisions_WIRE[4]) node tail_collisions_lo_hi_hi = cat(_tail_collisions_WIRE[7], _tail_collisions_WIRE[6]) node tail_collisions_lo_hi = cat(tail_collisions_lo_hi_hi, tail_collisions_lo_hi_lo) node tail_collisions_lo = cat(tail_collisions_lo_hi, tail_collisions_lo_lo) node tail_collisions_hi_lo_lo = cat(_tail_collisions_WIRE[9], _tail_collisions_WIRE[8]) node tail_collisions_hi_lo_hi = cat(_tail_collisions_WIRE[11], _tail_collisions_WIRE[10]) node tail_collisions_hi_lo = cat(tail_collisions_hi_lo_hi, tail_collisions_hi_lo_lo) node tail_collisions_hi_hi_lo = cat(_tail_collisions_WIRE[13], _tail_collisions_WIRE[12]) node tail_collisions_hi_hi_hi = cat(_tail_collisions_WIRE[15], _tail_collisions_WIRE[14]) node tail_collisions_hi_hi = cat(tail_collisions_hi_hi_hi, tail_collisions_hi_hi_lo) node tail_collisions_hi = cat(tail_collisions_hi_hi, tail_collisions_hi_lo) node _tail_collisions_T_64 = cat(tail_collisions_hi, tail_collisions_lo) node tail_collisions = and(_tail_collisions_T_64, tail) node _slot_will_hit_tail_T = bits(tail_collisions, 1, 0) node _slot_will_hit_tail_T_1 = bits(tail_collisions, 3, 2) node _slot_will_hit_tail_T_2 = bits(tail_collisions, 5, 4) node _slot_will_hit_tail_T_3 = bits(tail_collisions, 7, 6) node _slot_will_hit_tail_T_4 = bits(tail_collisions, 9, 8) node _slot_will_hit_tail_T_5 = bits(tail_collisions, 11, 10) node _slot_will_hit_tail_T_6 = bits(tail_collisions, 13, 12) node _slot_will_hit_tail_T_7 = bits(tail_collisions, 15, 14) node _slot_will_hit_tail_T_8 = or(_slot_will_hit_tail_T, _slot_will_hit_tail_T_1) node _slot_will_hit_tail_T_9 = or(_slot_will_hit_tail_T_8, _slot_will_hit_tail_T_2) node _slot_will_hit_tail_T_10 = or(_slot_will_hit_tail_T_9, _slot_will_hit_tail_T_3) node _slot_will_hit_tail_T_11 = or(_slot_will_hit_tail_T_10, _slot_will_hit_tail_T_4) node _slot_will_hit_tail_T_12 = or(_slot_will_hit_tail_T_11, _slot_will_hit_tail_T_5) node _slot_will_hit_tail_T_13 = or(_slot_will_hit_tail_T_12, _slot_will_hit_tail_T_6) node slot_will_hit_tail = or(_slot_will_hit_tail_T_13, _slot_will_hit_tail_T_7) node will_hit_tail = orr(slot_will_hit_tail) node _do_deq_T = eq(will_hit_tail, UInt<1>(0h0)) node do_deq = and(io.deq.ready, _do_deq_T) node _deq_valids_T = dshl(slot_will_hit_tail, UInt<1>(0h0)) node _deq_valids_T_1 = bits(_deq_valids_T, 1, 0) node _deq_valids_T_2 = dshl(slot_will_hit_tail, UInt<1>(0h1)) node _deq_valids_T_3 = bits(_deq_valids_T_2, 1, 0) node _deq_valids_T_4 = or(_deq_valids_T_1, _deq_valids_T_3) node _deq_valids_T_5 = not(_deq_valids_T_4) node deq_valids_0 = bits(_deq_valids_T_5, 0, 0) node deq_valids_1 = bits(_deq_valids_T_5, 1, 1) connect deq_vec[0][0], fb_uop_ram[0] connect deq_vec[0][1], fb_uop_ram[1] connect deq_vec[1][0], fb_uop_ram[2] connect deq_vec[1][1], fb_uop_ram[3] connect deq_vec[2][0], fb_uop_ram[4] connect deq_vec[2][1], fb_uop_ram[5] connect deq_vec[3][0], fb_uop_ram[6] connect deq_vec[3][1], fb_uop_ram[7] connect deq_vec[4][0], fb_uop_ram[8] connect deq_vec[4][1], fb_uop_ram[9] connect deq_vec[5][0], fb_uop_ram[10] connect deq_vec[5][1], fb_uop_ram[11] connect deq_vec[6][0], fb_uop_ram[12] connect deq_vec[6][1], fb_uop_ram[13] connect deq_vec[7][0], fb_uop_ram[14] connect deq_vec[7][1], fb_uop_ram[15] connect io.deq.bits.uops[0].valid, deq_valids_0 connect io.deq.bits.uops[1].valid, deq_valids_1 node _T_208 = bits(head, 0, 0) node _T_209 = bits(head, 1, 1) node _T_210 = bits(head, 2, 2) node _T_211 = bits(head, 3, 3) node _T_212 = bits(head, 4, 4) node _T_213 = bits(head, 5, 5) node _T_214 = bits(head, 6, 6) node _T_215 = bits(head, 7, 7) wire _WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[2] wire _WIRE_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} node _T_216 = mux(_T_208, deq_vec[0][0].debug_tsrc, UInt<1>(0h0)) node _T_217 = mux(_T_209, deq_vec[1][0].debug_tsrc, UInt<1>(0h0)) node _T_218 = mux(_T_210, deq_vec[2][0].debug_tsrc, UInt<1>(0h0)) node _T_219 = mux(_T_211, deq_vec[3][0].debug_tsrc, UInt<1>(0h0)) node _T_220 = mux(_T_212, deq_vec[4][0].debug_tsrc, UInt<1>(0h0)) node _T_221 = mux(_T_213, deq_vec[5][0].debug_tsrc, UInt<1>(0h0)) node _T_222 = mux(_T_214, deq_vec[6][0].debug_tsrc, UInt<1>(0h0)) node _T_223 = mux(_T_215, deq_vec[7][0].debug_tsrc, UInt<1>(0h0)) node _T_224 = or(_T_216, _T_217) node _T_225 = or(_T_224, _T_218) node _T_226 = or(_T_225, _T_219) node _T_227 = or(_T_226, _T_220) node _T_228 = or(_T_227, _T_221) node _T_229 = or(_T_228, _T_222) node _T_230 = or(_T_229, _T_223) wire _WIRE_2 : UInt<3> connect _WIRE_2, _T_230 connect _WIRE_1.debug_tsrc, _WIRE_2 node _T_231 = mux(_T_208, deq_vec[0][0].debug_fsrc, UInt<1>(0h0)) node _T_232 = mux(_T_209, deq_vec[1][0].debug_fsrc, UInt<1>(0h0)) node _T_233 = mux(_T_210, deq_vec[2][0].debug_fsrc, UInt<1>(0h0)) node _T_234 = mux(_T_211, deq_vec[3][0].debug_fsrc, UInt<1>(0h0)) node _T_235 = mux(_T_212, deq_vec[4][0].debug_fsrc, UInt<1>(0h0)) node _T_236 = mux(_T_213, deq_vec[5][0].debug_fsrc, UInt<1>(0h0)) node _T_237 = mux(_T_214, deq_vec[6][0].debug_fsrc, UInt<1>(0h0)) node _T_238 = mux(_T_215, deq_vec[7][0].debug_fsrc, UInt<1>(0h0)) node _T_239 = or(_T_231, _T_232) node _T_240 = or(_T_239, _T_233) node _T_241 = or(_T_240, _T_234) node _T_242 = or(_T_241, _T_235) node _T_243 = or(_T_242, _T_236) node _T_244 = or(_T_243, _T_237) node _T_245 = or(_T_244, _T_238) wire _WIRE_3 : UInt<3> connect _WIRE_3, _T_245 connect _WIRE_1.debug_fsrc, _WIRE_3 node _T_246 = mux(_T_208, deq_vec[0][0].bp_xcpt_if, UInt<1>(0h0)) node _T_247 = mux(_T_209, deq_vec[1][0].bp_xcpt_if, UInt<1>(0h0)) node _T_248 = mux(_T_210, deq_vec[2][0].bp_xcpt_if, UInt<1>(0h0)) node _T_249 = mux(_T_211, deq_vec[3][0].bp_xcpt_if, UInt<1>(0h0)) node _T_250 = mux(_T_212, deq_vec[4][0].bp_xcpt_if, UInt<1>(0h0)) node _T_251 = mux(_T_213, deq_vec[5][0].bp_xcpt_if, UInt<1>(0h0)) node _T_252 = mux(_T_214, deq_vec[6][0].bp_xcpt_if, UInt<1>(0h0)) node _T_253 = mux(_T_215, deq_vec[7][0].bp_xcpt_if, UInt<1>(0h0)) node _T_254 = or(_T_246, _T_247) node _T_255 = or(_T_254, _T_248) node _T_256 = or(_T_255, _T_249) node _T_257 = or(_T_256, _T_250) node _T_258 = or(_T_257, _T_251) node _T_259 = or(_T_258, _T_252) node _T_260 = or(_T_259, _T_253) wire _WIRE_4 : UInt<1> connect _WIRE_4, _T_260 connect _WIRE_1.bp_xcpt_if, _WIRE_4 node _T_261 = mux(_T_208, deq_vec[0][0].bp_debug_if, UInt<1>(0h0)) node _T_262 = mux(_T_209, deq_vec[1][0].bp_debug_if, UInt<1>(0h0)) node _T_263 = mux(_T_210, deq_vec[2][0].bp_debug_if, UInt<1>(0h0)) node _T_264 = mux(_T_211, deq_vec[3][0].bp_debug_if, UInt<1>(0h0)) node _T_265 = mux(_T_212, deq_vec[4][0].bp_debug_if, UInt<1>(0h0)) node _T_266 = mux(_T_213, deq_vec[5][0].bp_debug_if, UInt<1>(0h0)) node _T_267 = mux(_T_214, deq_vec[6][0].bp_debug_if, UInt<1>(0h0)) node _T_268 = mux(_T_215, deq_vec[7][0].bp_debug_if, UInt<1>(0h0)) node _T_269 = or(_T_261, _T_262) node _T_270 = or(_T_269, _T_263) node _T_271 = or(_T_270, _T_264) node _T_272 = or(_T_271, _T_265) node _T_273 = or(_T_272, _T_266) node _T_274 = or(_T_273, _T_267) node _T_275 = or(_T_274, _T_268) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_275 connect _WIRE_1.bp_debug_if, _WIRE_5 node _T_276 = mux(_T_208, deq_vec[0][0].xcpt_ma_if, UInt<1>(0h0)) node _T_277 = mux(_T_209, deq_vec[1][0].xcpt_ma_if, UInt<1>(0h0)) node _T_278 = mux(_T_210, deq_vec[2][0].xcpt_ma_if, UInt<1>(0h0)) node _T_279 = mux(_T_211, deq_vec[3][0].xcpt_ma_if, UInt<1>(0h0)) node _T_280 = mux(_T_212, deq_vec[4][0].xcpt_ma_if, UInt<1>(0h0)) node _T_281 = mux(_T_213, deq_vec[5][0].xcpt_ma_if, UInt<1>(0h0)) node _T_282 = mux(_T_214, deq_vec[6][0].xcpt_ma_if, UInt<1>(0h0)) node _T_283 = mux(_T_215, deq_vec[7][0].xcpt_ma_if, UInt<1>(0h0)) node _T_284 = or(_T_276, _T_277) node _T_285 = or(_T_284, _T_278) node _T_286 = or(_T_285, _T_279) node _T_287 = or(_T_286, _T_280) node _T_288 = or(_T_287, _T_281) node _T_289 = or(_T_288, _T_282) node _T_290 = or(_T_289, _T_283) wire _WIRE_6 : UInt<1> connect _WIRE_6, _T_290 connect _WIRE_1.xcpt_ma_if, _WIRE_6 node _T_291 = mux(_T_208, deq_vec[0][0].xcpt_ae_if, UInt<1>(0h0)) node _T_292 = mux(_T_209, deq_vec[1][0].xcpt_ae_if, UInt<1>(0h0)) node _T_293 = mux(_T_210, deq_vec[2][0].xcpt_ae_if, UInt<1>(0h0)) node _T_294 = mux(_T_211, deq_vec[3][0].xcpt_ae_if, UInt<1>(0h0)) node _T_295 = mux(_T_212, deq_vec[4][0].xcpt_ae_if, UInt<1>(0h0)) node _T_296 = mux(_T_213, deq_vec[5][0].xcpt_ae_if, UInt<1>(0h0)) node _T_297 = mux(_T_214, deq_vec[6][0].xcpt_ae_if, UInt<1>(0h0)) node _T_298 = mux(_T_215, deq_vec[7][0].xcpt_ae_if, UInt<1>(0h0)) node _T_299 = or(_T_291, _T_292) node _T_300 = or(_T_299, _T_293) node _T_301 = or(_T_300, _T_294) node _T_302 = or(_T_301, _T_295) node _T_303 = or(_T_302, _T_296) node _T_304 = or(_T_303, _T_297) node _T_305 = or(_T_304, _T_298) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_305 connect _WIRE_1.xcpt_ae_if, _WIRE_7 node _T_306 = mux(_T_208, deq_vec[0][0].xcpt_pf_if, UInt<1>(0h0)) node _T_307 = mux(_T_209, deq_vec[1][0].xcpt_pf_if, UInt<1>(0h0)) node _T_308 = mux(_T_210, deq_vec[2][0].xcpt_pf_if, UInt<1>(0h0)) node _T_309 = mux(_T_211, deq_vec[3][0].xcpt_pf_if, UInt<1>(0h0)) node _T_310 = mux(_T_212, deq_vec[4][0].xcpt_pf_if, UInt<1>(0h0)) node _T_311 = mux(_T_213, deq_vec[5][0].xcpt_pf_if, UInt<1>(0h0)) node _T_312 = mux(_T_214, deq_vec[6][0].xcpt_pf_if, UInt<1>(0h0)) node _T_313 = mux(_T_215, deq_vec[7][0].xcpt_pf_if, UInt<1>(0h0)) node _T_314 = or(_T_306, _T_307) node _T_315 = or(_T_314, _T_308) node _T_316 = or(_T_315, _T_309) node _T_317 = or(_T_316, _T_310) node _T_318 = or(_T_317, _T_311) node _T_319 = or(_T_318, _T_312) node _T_320 = or(_T_319, _T_313) wire _WIRE_8 : UInt<1> connect _WIRE_8, _T_320 connect _WIRE_1.xcpt_pf_if, _WIRE_8 node _T_321 = mux(_T_208, deq_vec[0][0].fp_typ, UInt<1>(0h0)) node _T_322 = mux(_T_209, deq_vec[1][0].fp_typ, UInt<1>(0h0)) node _T_323 = mux(_T_210, deq_vec[2][0].fp_typ, UInt<1>(0h0)) node _T_324 = mux(_T_211, deq_vec[3][0].fp_typ, UInt<1>(0h0)) node _T_325 = mux(_T_212, deq_vec[4][0].fp_typ, UInt<1>(0h0)) node _T_326 = mux(_T_213, deq_vec[5][0].fp_typ, UInt<1>(0h0)) node _T_327 = mux(_T_214, deq_vec[6][0].fp_typ, UInt<1>(0h0)) node _T_328 = mux(_T_215, deq_vec[7][0].fp_typ, UInt<1>(0h0)) node _T_329 = or(_T_321, _T_322) node _T_330 = or(_T_329, _T_323) node _T_331 = or(_T_330, _T_324) node _T_332 = or(_T_331, _T_325) node _T_333 = or(_T_332, _T_326) node _T_334 = or(_T_333, _T_327) node _T_335 = or(_T_334, _T_328) wire _WIRE_9 : UInt<2> connect _WIRE_9, _T_335 connect _WIRE_1.fp_typ, _WIRE_9 node _T_336 = mux(_T_208, deq_vec[0][0].fp_rm, UInt<1>(0h0)) node _T_337 = mux(_T_209, deq_vec[1][0].fp_rm, UInt<1>(0h0)) node _T_338 = mux(_T_210, deq_vec[2][0].fp_rm, UInt<1>(0h0)) node _T_339 = mux(_T_211, deq_vec[3][0].fp_rm, UInt<1>(0h0)) node _T_340 = mux(_T_212, deq_vec[4][0].fp_rm, UInt<1>(0h0)) node _T_341 = mux(_T_213, deq_vec[5][0].fp_rm, UInt<1>(0h0)) node _T_342 = mux(_T_214, deq_vec[6][0].fp_rm, UInt<1>(0h0)) node _T_343 = mux(_T_215, deq_vec[7][0].fp_rm, UInt<1>(0h0)) node _T_344 = or(_T_336, _T_337) node _T_345 = or(_T_344, _T_338) node _T_346 = or(_T_345, _T_339) node _T_347 = or(_T_346, _T_340) node _T_348 = or(_T_347, _T_341) node _T_349 = or(_T_348, _T_342) node _T_350 = or(_T_349, _T_343) wire _WIRE_10 : UInt<3> connect _WIRE_10, _T_350 connect _WIRE_1.fp_rm, _WIRE_10 node _T_351 = mux(_T_208, deq_vec[0][0].fp_val, UInt<1>(0h0)) node _T_352 = mux(_T_209, deq_vec[1][0].fp_val, UInt<1>(0h0)) node _T_353 = mux(_T_210, deq_vec[2][0].fp_val, UInt<1>(0h0)) node _T_354 = mux(_T_211, deq_vec[3][0].fp_val, UInt<1>(0h0)) node _T_355 = mux(_T_212, deq_vec[4][0].fp_val, UInt<1>(0h0)) node _T_356 = mux(_T_213, deq_vec[5][0].fp_val, UInt<1>(0h0)) node _T_357 = mux(_T_214, deq_vec[6][0].fp_val, UInt<1>(0h0)) node _T_358 = mux(_T_215, deq_vec[7][0].fp_val, UInt<1>(0h0)) node _T_359 = or(_T_351, _T_352) node _T_360 = or(_T_359, _T_353) node _T_361 = or(_T_360, _T_354) node _T_362 = or(_T_361, _T_355) node _T_363 = or(_T_362, _T_356) node _T_364 = or(_T_363, _T_357) node _T_365 = or(_T_364, _T_358) wire _WIRE_11 : UInt<1> connect _WIRE_11, _T_365 connect _WIRE_1.fp_val, _WIRE_11 node _T_366 = mux(_T_208, deq_vec[0][0].fcn_op, UInt<1>(0h0)) node _T_367 = mux(_T_209, deq_vec[1][0].fcn_op, UInt<1>(0h0)) node _T_368 = mux(_T_210, deq_vec[2][0].fcn_op, UInt<1>(0h0)) node _T_369 = mux(_T_211, deq_vec[3][0].fcn_op, UInt<1>(0h0)) node _T_370 = mux(_T_212, deq_vec[4][0].fcn_op, UInt<1>(0h0)) node _T_371 = mux(_T_213, deq_vec[5][0].fcn_op, UInt<1>(0h0)) node _T_372 = mux(_T_214, deq_vec[6][0].fcn_op, UInt<1>(0h0)) node _T_373 = mux(_T_215, deq_vec[7][0].fcn_op, UInt<1>(0h0)) node _T_374 = or(_T_366, _T_367) node _T_375 = or(_T_374, _T_368) node _T_376 = or(_T_375, _T_369) node _T_377 = or(_T_376, _T_370) node _T_378 = or(_T_377, _T_371) node _T_379 = or(_T_378, _T_372) node _T_380 = or(_T_379, _T_373) wire _WIRE_12 : UInt<5> connect _WIRE_12, _T_380 connect _WIRE_1.fcn_op, _WIRE_12 node _T_381 = mux(_T_208, deq_vec[0][0].fcn_dw, UInt<1>(0h0)) node _T_382 = mux(_T_209, deq_vec[1][0].fcn_dw, UInt<1>(0h0)) node _T_383 = mux(_T_210, deq_vec[2][0].fcn_dw, UInt<1>(0h0)) node _T_384 = mux(_T_211, deq_vec[3][0].fcn_dw, UInt<1>(0h0)) node _T_385 = mux(_T_212, deq_vec[4][0].fcn_dw, UInt<1>(0h0)) node _T_386 = mux(_T_213, deq_vec[5][0].fcn_dw, UInt<1>(0h0)) node _T_387 = mux(_T_214, deq_vec[6][0].fcn_dw, UInt<1>(0h0)) node _T_388 = mux(_T_215, deq_vec[7][0].fcn_dw, UInt<1>(0h0)) node _T_389 = or(_T_381, _T_382) node _T_390 = or(_T_389, _T_383) node _T_391 = or(_T_390, _T_384) node _T_392 = or(_T_391, _T_385) node _T_393 = or(_T_392, _T_386) node _T_394 = or(_T_393, _T_387) node _T_395 = or(_T_394, _T_388) wire _WIRE_13 : UInt<1> connect _WIRE_13, _T_395 connect _WIRE_1.fcn_dw, _WIRE_13 node _T_396 = mux(_T_208, deq_vec[0][0].frs3_en, UInt<1>(0h0)) node _T_397 = mux(_T_209, deq_vec[1][0].frs3_en, UInt<1>(0h0)) node _T_398 = mux(_T_210, deq_vec[2][0].frs3_en, UInt<1>(0h0)) node _T_399 = mux(_T_211, deq_vec[3][0].frs3_en, UInt<1>(0h0)) node _T_400 = mux(_T_212, deq_vec[4][0].frs3_en, UInt<1>(0h0)) node _T_401 = mux(_T_213, deq_vec[5][0].frs3_en, UInt<1>(0h0)) node _T_402 = mux(_T_214, deq_vec[6][0].frs3_en, UInt<1>(0h0)) node _T_403 = mux(_T_215, deq_vec[7][0].frs3_en, UInt<1>(0h0)) node _T_404 = or(_T_396, _T_397) node _T_405 = or(_T_404, _T_398) node _T_406 = or(_T_405, _T_399) node _T_407 = or(_T_406, _T_400) node _T_408 = or(_T_407, _T_401) node _T_409 = or(_T_408, _T_402) node _T_410 = or(_T_409, _T_403) wire _WIRE_14 : UInt<1> connect _WIRE_14, _T_410 connect _WIRE_1.frs3_en, _WIRE_14 node _T_411 = mux(_T_208, deq_vec[0][0].lrs2_rtype, UInt<1>(0h0)) node _T_412 = mux(_T_209, deq_vec[1][0].lrs2_rtype, UInt<1>(0h0)) node _T_413 = mux(_T_210, deq_vec[2][0].lrs2_rtype, UInt<1>(0h0)) node _T_414 = mux(_T_211, deq_vec[3][0].lrs2_rtype, UInt<1>(0h0)) node _T_415 = mux(_T_212, deq_vec[4][0].lrs2_rtype, UInt<1>(0h0)) node _T_416 = mux(_T_213, deq_vec[5][0].lrs2_rtype, UInt<1>(0h0)) node _T_417 = mux(_T_214, deq_vec[6][0].lrs2_rtype, UInt<1>(0h0)) node _T_418 = mux(_T_215, deq_vec[7][0].lrs2_rtype, UInt<1>(0h0)) node _T_419 = or(_T_411, _T_412) node _T_420 = or(_T_419, _T_413) node _T_421 = or(_T_420, _T_414) node _T_422 = or(_T_421, _T_415) node _T_423 = or(_T_422, _T_416) node _T_424 = or(_T_423, _T_417) node _T_425 = or(_T_424, _T_418) wire _WIRE_15 : UInt<2> connect _WIRE_15, _T_425 connect _WIRE_1.lrs2_rtype, _WIRE_15 node _T_426 = mux(_T_208, deq_vec[0][0].lrs1_rtype, UInt<1>(0h0)) node _T_427 = mux(_T_209, deq_vec[1][0].lrs1_rtype, UInt<1>(0h0)) node _T_428 = mux(_T_210, deq_vec[2][0].lrs1_rtype, UInt<1>(0h0)) node _T_429 = mux(_T_211, deq_vec[3][0].lrs1_rtype, UInt<1>(0h0)) node _T_430 = mux(_T_212, deq_vec[4][0].lrs1_rtype, UInt<1>(0h0)) node _T_431 = mux(_T_213, deq_vec[5][0].lrs1_rtype, UInt<1>(0h0)) node _T_432 = mux(_T_214, deq_vec[6][0].lrs1_rtype, UInt<1>(0h0)) node _T_433 = mux(_T_215, deq_vec[7][0].lrs1_rtype, UInt<1>(0h0)) node _T_434 = or(_T_426, _T_427) node _T_435 = or(_T_434, _T_428) node _T_436 = or(_T_435, _T_429) node _T_437 = or(_T_436, _T_430) node _T_438 = or(_T_437, _T_431) node _T_439 = or(_T_438, _T_432) node _T_440 = or(_T_439, _T_433) wire _WIRE_16 : UInt<2> connect _WIRE_16, _T_440 connect _WIRE_1.lrs1_rtype, _WIRE_16 node _T_441 = mux(_T_208, deq_vec[0][0].dst_rtype, UInt<1>(0h0)) node _T_442 = mux(_T_209, deq_vec[1][0].dst_rtype, UInt<1>(0h0)) node _T_443 = mux(_T_210, deq_vec[2][0].dst_rtype, UInt<1>(0h0)) node _T_444 = mux(_T_211, deq_vec[3][0].dst_rtype, UInt<1>(0h0)) node _T_445 = mux(_T_212, deq_vec[4][0].dst_rtype, UInt<1>(0h0)) node _T_446 = mux(_T_213, deq_vec[5][0].dst_rtype, UInt<1>(0h0)) node _T_447 = mux(_T_214, deq_vec[6][0].dst_rtype, UInt<1>(0h0)) node _T_448 = mux(_T_215, deq_vec[7][0].dst_rtype, UInt<1>(0h0)) node _T_449 = or(_T_441, _T_442) node _T_450 = or(_T_449, _T_443) node _T_451 = or(_T_450, _T_444) node _T_452 = or(_T_451, _T_445) node _T_453 = or(_T_452, _T_446) node _T_454 = or(_T_453, _T_447) node _T_455 = or(_T_454, _T_448) wire _WIRE_17 : UInt<2> connect _WIRE_17, _T_455 connect _WIRE_1.dst_rtype, _WIRE_17 node _T_456 = mux(_T_208, deq_vec[0][0].lrs3, UInt<1>(0h0)) node _T_457 = mux(_T_209, deq_vec[1][0].lrs3, UInt<1>(0h0)) node _T_458 = mux(_T_210, deq_vec[2][0].lrs3, UInt<1>(0h0)) node _T_459 = mux(_T_211, deq_vec[3][0].lrs3, UInt<1>(0h0)) node _T_460 = mux(_T_212, deq_vec[4][0].lrs3, UInt<1>(0h0)) node _T_461 = mux(_T_213, deq_vec[5][0].lrs3, UInt<1>(0h0)) node _T_462 = mux(_T_214, deq_vec[6][0].lrs3, UInt<1>(0h0)) node _T_463 = mux(_T_215, deq_vec[7][0].lrs3, UInt<1>(0h0)) node _T_464 = or(_T_456, _T_457) node _T_465 = or(_T_464, _T_458) node _T_466 = or(_T_465, _T_459) node _T_467 = or(_T_466, _T_460) node _T_468 = or(_T_467, _T_461) node _T_469 = or(_T_468, _T_462) node _T_470 = or(_T_469, _T_463) wire _WIRE_18 : UInt<6> connect _WIRE_18, _T_470 connect _WIRE_1.lrs3, _WIRE_18 node _T_471 = mux(_T_208, deq_vec[0][0].lrs2, UInt<1>(0h0)) node _T_472 = mux(_T_209, deq_vec[1][0].lrs2, UInt<1>(0h0)) node _T_473 = mux(_T_210, deq_vec[2][0].lrs2, UInt<1>(0h0)) node _T_474 = mux(_T_211, deq_vec[3][0].lrs2, UInt<1>(0h0)) node _T_475 = mux(_T_212, deq_vec[4][0].lrs2, UInt<1>(0h0)) node _T_476 = mux(_T_213, deq_vec[5][0].lrs2, UInt<1>(0h0)) node _T_477 = mux(_T_214, deq_vec[6][0].lrs2, UInt<1>(0h0)) node _T_478 = mux(_T_215, deq_vec[7][0].lrs2, UInt<1>(0h0)) node _T_479 = or(_T_471, _T_472) node _T_480 = or(_T_479, _T_473) node _T_481 = or(_T_480, _T_474) node _T_482 = or(_T_481, _T_475) node _T_483 = or(_T_482, _T_476) node _T_484 = or(_T_483, _T_477) node _T_485 = or(_T_484, _T_478) wire _WIRE_19 : UInt<6> connect _WIRE_19, _T_485 connect _WIRE_1.lrs2, _WIRE_19 node _T_486 = mux(_T_208, deq_vec[0][0].lrs1, UInt<1>(0h0)) node _T_487 = mux(_T_209, deq_vec[1][0].lrs1, UInt<1>(0h0)) node _T_488 = mux(_T_210, deq_vec[2][0].lrs1, UInt<1>(0h0)) node _T_489 = mux(_T_211, deq_vec[3][0].lrs1, UInt<1>(0h0)) node _T_490 = mux(_T_212, deq_vec[4][0].lrs1, UInt<1>(0h0)) node _T_491 = mux(_T_213, deq_vec[5][0].lrs1, UInt<1>(0h0)) node _T_492 = mux(_T_214, deq_vec[6][0].lrs1, UInt<1>(0h0)) node _T_493 = mux(_T_215, deq_vec[7][0].lrs1, UInt<1>(0h0)) node _T_494 = or(_T_486, _T_487) node _T_495 = or(_T_494, _T_488) node _T_496 = or(_T_495, _T_489) node _T_497 = or(_T_496, _T_490) node _T_498 = or(_T_497, _T_491) node _T_499 = or(_T_498, _T_492) node _T_500 = or(_T_499, _T_493) wire _WIRE_20 : UInt<6> connect _WIRE_20, _T_500 connect _WIRE_1.lrs1, _WIRE_20 node _T_501 = mux(_T_208, deq_vec[0][0].ldst, UInt<1>(0h0)) node _T_502 = mux(_T_209, deq_vec[1][0].ldst, UInt<1>(0h0)) node _T_503 = mux(_T_210, deq_vec[2][0].ldst, UInt<1>(0h0)) node _T_504 = mux(_T_211, deq_vec[3][0].ldst, UInt<1>(0h0)) node _T_505 = mux(_T_212, deq_vec[4][0].ldst, UInt<1>(0h0)) node _T_506 = mux(_T_213, deq_vec[5][0].ldst, UInt<1>(0h0)) node _T_507 = mux(_T_214, deq_vec[6][0].ldst, UInt<1>(0h0)) node _T_508 = mux(_T_215, deq_vec[7][0].ldst, UInt<1>(0h0)) node _T_509 = or(_T_501, _T_502) node _T_510 = or(_T_509, _T_503) node _T_511 = or(_T_510, _T_504) node _T_512 = or(_T_511, _T_505) node _T_513 = or(_T_512, _T_506) node _T_514 = or(_T_513, _T_507) node _T_515 = or(_T_514, _T_508) wire _WIRE_21 : UInt<6> connect _WIRE_21, _T_515 connect _WIRE_1.ldst, _WIRE_21 node _T_516 = mux(_T_208, deq_vec[0][0].ldst_is_rs1, UInt<1>(0h0)) node _T_517 = mux(_T_209, deq_vec[1][0].ldst_is_rs1, UInt<1>(0h0)) node _T_518 = mux(_T_210, deq_vec[2][0].ldst_is_rs1, UInt<1>(0h0)) node _T_519 = mux(_T_211, deq_vec[3][0].ldst_is_rs1, UInt<1>(0h0)) node _T_520 = mux(_T_212, deq_vec[4][0].ldst_is_rs1, UInt<1>(0h0)) node _T_521 = mux(_T_213, deq_vec[5][0].ldst_is_rs1, UInt<1>(0h0)) node _T_522 = mux(_T_214, deq_vec[6][0].ldst_is_rs1, UInt<1>(0h0)) node _T_523 = mux(_T_215, deq_vec[7][0].ldst_is_rs1, UInt<1>(0h0)) node _T_524 = or(_T_516, _T_517) node _T_525 = or(_T_524, _T_518) node _T_526 = or(_T_525, _T_519) node _T_527 = or(_T_526, _T_520) node _T_528 = or(_T_527, _T_521) node _T_529 = or(_T_528, _T_522) node _T_530 = or(_T_529, _T_523) wire _WIRE_22 : UInt<1> connect _WIRE_22, _T_530 connect _WIRE_1.ldst_is_rs1, _WIRE_22 node _T_531 = mux(_T_208, deq_vec[0][0].csr_cmd, UInt<1>(0h0)) node _T_532 = mux(_T_209, deq_vec[1][0].csr_cmd, UInt<1>(0h0)) node _T_533 = mux(_T_210, deq_vec[2][0].csr_cmd, UInt<1>(0h0)) node _T_534 = mux(_T_211, deq_vec[3][0].csr_cmd, UInt<1>(0h0)) node _T_535 = mux(_T_212, deq_vec[4][0].csr_cmd, UInt<1>(0h0)) node _T_536 = mux(_T_213, deq_vec[5][0].csr_cmd, UInt<1>(0h0)) node _T_537 = mux(_T_214, deq_vec[6][0].csr_cmd, UInt<1>(0h0)) node _T_538 = mux(_T_215, deq_vec[7][0].csr_cmd, UInt<1>(0h0)) node _T_539 = or(_T_531, _T_532) node _T_540 = or(_T_539, _T_533) node _T_541 = or(_T_540, _T_534) node _T_542 = or(_T_541, _T_535) node _T_543 = or(_T_542, _T_536) node _T_544 = or(_T_543, _T_537) node _T_545 = or(_T_544, _T_538) wire _WIRE_23 : UInt<3> connect _WIRE_23, _T_545 connect _WIRE_1.csr_cmd, _WIRE_23 node _T_546 = mux(_T_208, deq_vec[0][0].flush_on_commit, UInt<1>(0h0)) node _T_547 = mux(_T_209, deq_vec[1][0].flush_on_commit, UInt<1>(0h0)) node _T_548 = mux(_T_210, deq_vec[2][0].flush_on_commit, UInt<1>(0h0)) node _T_549 = mux(_T_211, deq_vec[3][0].flush_on_commit, UInt<1>(0h0)) node _T_550 = mux(_T_212, deq_vec[4][0].flush_on_commit, UInt<1>(0h0)) node _T_551 = mux(_T_213, deq_vec[5][0].flush_on_commit, UInt<1>(0h0)) node _T_552 = mux(_T_214, deq_vec[6][0].flush_on_commit, UInt<1>(0h0)) node _T_553 = mux(_T_215, deq_vec[7][0].flush_on_commit, UInt<1>(0h0)) node _T_554 = or(_T_546, _T_547) node _T_555 = or(_T_554, _T_548) node _T_556 = or(_T_555, _T_549) node _T_557 = or(_T_556, _T_550) node _T_558 = or(_T_557, _T_551) node _T_559 = or(_T_558, _T_552) node _T_560 = or(_T_559, _T_553) wire _WIRE_24 : UInt<1> connect _WIRE_24, _T_560 connect _WIRE_1.flush_on_commit, _WIRE_24 node _T_561 = mux(_T_208, deq_vec[0][0].is_unique, UInt<1>(0h0)) node _T_562 = mux(_T_209, deq_vec[1][0].is_unique, UInt<1>(0h0)) node _T_563 = mux(_T_210, deq_vec[2][0].is_unique, UInt<1>(0h0)) node _T_564 = mux(_T_211, deq_vec[3][0].is_unique, UInt<1>(0h0)) node _T_565 = mux(_T_212, deq_vec[4][0].is_unique, UInt<1>(0h0)) node _T_566 = mux(_T_213, deq_vec[5][0].is_unique, UInt<1>(0h0)) node _T_567 = mux(_T_214, deq_vec[6][0].is_unique, UInt<1>(0h0)) node _T_568 = mux(_T_215, deq_vec[7][0].is_unique, UInt<1>(0h0)) node _T_569 = or(_T_561, _T_562) node _T_570 = or(_T_569, _T_563) node _T_571 = or(_T_570, _T_564) node _T_572 = or(_T_571, _T_565) node _T_573 = or(_T_572, _T_566) node _T_574 = or(_T_573, _T_567) node _T_575 = or(_T_574, _T_568) wire _WIRE_25 : UInt<1> connect _WIRE_25, _T_575 connect _WIRE_1.is_unique, _WIRE_25 node _T_576 = mux(_T_208, deq_vec[0][0].uses_stq, UInt<1>(0h0)) node _T_577 = mux(_T_209, deq_vec[1][0].uses_stq, UInt<1>(0h0)) node _T_578 = mux(_T_210, deq_vec[2][0].uses_stq, UInt<1>(0h0)) node _T_579 = mux(_T_211, deq_vec[3][0].uses_stq, UInt<1>(0h0)) node _T_580 = mux(_T_212, deq_vec[4][0].uses_stq, UInt<1>(0h0)) node _T_581 = mux(_T_213, deq_vec[5][0].uses_stq, UInt<1>(0h0)) node _T_582 = mux(_T_214, deq_vec[6][0].uses_stq, UInt<1>(0h0)) node _T_583 = mux(_T_215, deq_vec[7][0].uses_stq, UInt<1>(0h0)) node _T_584 = or(_T_576, _T_577) node _T_585 = or(_T_584, _T_578) node _T_586 = or(_T_585, _T_579) node _T_587 = or(_T_586, _T_580) node _T_588 = or(_T_587, _T_581) node _T_589 = or(_T_588, _T_582) node _T_590 = or(_T_589, _T_583) wire _WIRE_26 : UInt<1> connect _WIRE_26, _T_590 connect _WIRE_1.uses_stq, _WIRE_26 node _T_591 = mux(_T_208, deq_vec[0][0].uses_ldq, UInt<1>(0h0)) node _T_592 = mux(_T_209, deq_vec[1][0].uses_ldq, UInt<1>(0h0)) node _T_593 = mux(_T_210, deq_vec[2][0].uses_ldq, UInt<1>(0h0)) node _T_594 = mux(_T_211, deq_vec[3][0].uses_ldq, UInt<1>(0h0)) node _T_595 = mux(_T_212, deq_vec[4][0].uses_ldq, UInt<1>(0h0)) node _T_596 = mux(_T_213, deq_vec[5][0].uses_ldq, UInt<1>(0h0)) node _T_597 = mux(_T_214, deq_vec[6][0].uses_ldq, UInt<1>(0h0)) node _T_598 = mux(_T_215, deq_vec[7][0].uses_ldq, UInt<1>(0h0)) node _T_599 = or(_T_591, _T_592) node _T_600 = or(_T_599, _T_593) node _T_601 = or(_T_600, _T_594) node _T_602 = or(_T_601, _T_595) node _T_603 = or(_T_602, _T_596) node _T_604 = or(_T_603, _T_597) node _T_605 = or(_T_604, _T_598) wire _WIRE_27 : UInt<1> connect _WIRE_27, _T_605 connect _WIRE_1.uses_ldq, _WIRE_27 node _T_606 = mux(_T_208, deq_vec[0][0].mem_signed, UInt<1>(0h0)) node _T_607 = mux(_T_209, deq_vec[1][0].mem_signed, UInt<1>(0h0)) node _T_608 = mux(_T_210, deq_vec[2][0].mem_signed, UInt<1>(0h0)) node _T_609 = mux(_T_211, deq_vec[3][0].mem_signed, UInt<1>(0h0)) node _T_610 = mux(_T_212, deq_vec[4][0].mem_signed, UInt<1>(0h0)) node _T_611 = mux(_T_213, deq_vec[5][0].mem_signed, UInt<1>(0h0)) node _T_612 = mux(_T_214, deq_vec[6][0].mem_signed, UInt<1>(0h0)) node _T_613 = mux(_T_215, deq_vec[7][0].mem_signed, UInt<1>(0h0)) node _T_614 = or(_T_606, _T_607) node _T_615 = or(_T_614, _T_608) node _T_616 = or(_T_615, _T_609) node _T_617 = or(_T_616, _T_610) node _T_618 = or(_T_617, _T_611) node _T_619 = or(_T_618, _T_612) node _T_620 = or(_T_619, _T_613) wire _WIRE_28 : UInt<1> connect _WIRE_28, _T_620 connect _WIRE_1.mem_signed, _WIRE_28 node _T_621 = mux(_T_208, deq_vec[0][0].mem_size, UInt<1>(0h0)) node _T_622 = mux(_T_209, deq_vec[1][0].mem_size, UInt<1>(0h0)) node _T_623 = mux(_T_210, deq_vec[2][0].mem_size, UInt<1>(0h0)) node _T_624 = mux(_T_211, deq_vec[3][0].mem_size, UInt<1>(0h0)) node _T_625 = mux(_T_212, deq_vec[4][0].mem_size, UInt<1>(0h0)) node _T_626 = mux(_T_213, deq_vec[5][0].mem_size, UInt<1>(0h0)) node _T_627 = mux(_T_214, deq_vec[6][0].mem_size, UInt<1>(0h0)) node _T_628 = mux(_T_215, deq_vec[7][0].mem_size, UInt<1>(0h0)) node _T_629 = or(_T_621, _T_622) node _T_630 = or(_T_629, _T_623) node _T_631 = or(_T_630, _T_624) node _T_632 = or(_T_631, _T_625) node _T_633 = or(_T_632, _T_626) node _T_634 = or(_T_633, _T_627) node _T_635 = or(_T_634, _T_628) wire _WIRE_29 : UInt<2> connect _WIRE_29, _T_635 connect _WIRE_1.mem_size, _WIRE_29 node _T_636 = mux(_T_208, deq_vec[0][0].mem_cmd, UInt<1>(0h0)) node _T_637 = mux(_T_209, deq_vec[1][0].mem_cmd, UInt<1>(0h0)) node _T_638 = mux(_T_210, deq_vec[2][0].mem_cmd, UInt<1>(0h0)) node _T_639 = mux(_T_211, deq_vec[3][0].mem_cmd, UInt<1>(0h0)) node _T_640 = mux(_T_212, deq_vec[4][0].mem_cmd, UInt<1>(0h0)) node _T_641 = mux(_T_213, deq_vec[5][0].mem_cmd, UInt<1>(0h0)) node _T_642 = mux(_T_214, deq_vec[6][0].mem_cmd, UInt<1>(0h0)) node _T_643 = mux(_T_215, deq_vec[7][0].mem_cmd, UInt<1>(0h0)) node _T_644 = or(_T_636, _T_637) node _T_645 = or(_T_644, _T_638) node _T_646 = or(_T_645, _T_639) node _T_647 = or(_T_646, _T_640) node _T_648 = or(_T_647, _T_641) node _T_649 = or(_T_648, _T_642) node _T_650 = or(_T_649, _T_643) wire _WIRE_30 : UInt<5> connect _WIRE_30, _T_650 connect _WIRE_1.mem_cmd, _WIRE_30 node _T_651 = mux(_T_208, deq_vec[0][0].exc_cause, UInt<1>(0h0)) node _T_652 = mux(_T_209, deq_vec[1][0].exc_cause, UInt<1>(0h0)) node _T_653 = mux(_T_210, deq_vec[2][0].exc_cause, UInt<1>(0h0)) node _T_654 = mux(_T_211, deq_vec[3][0].exc_cause, UInt<1>(0h0)) node _T_655 = mux(_T_212, deq_vec[4][0].exc_cause, UInt<1>(0h0)) node _T_656 = mux(_T_213, deq_vec[5][0].exc_cause, UInt<1>(0h0)) node _T_657 = mux(_T_214, deq_vec[6][0].exc_cause, UInt<1>(0h0)) node _T_658 = mux(_T_215, deq_vec[7][0].exc_cause, UInt<1>(0h0)) node _T_659 = or(_T_651, _T_652) node _T_660 = or(_T_659, _T_653) node _T_661 = or(_T_660, _T_654) node _T_662 = or(_T_661, _T_655) node _T_663 = or(_T_662, _T_656) node _T_664 = or(_T_663, _T_657) node _T_665 = or(_T_664, _T_658) wire _WIRE_31 : UInt<64> connect _WIRE_31, _T_665 connect _WIRE_1.exc_cause, _WIRE_31 node _T_666 = mux(_T_208, deq_vec[0][0].exception, UInt<1>(0h0)) node _T_667 = mux(_T_209, deq_vec[1][0].exception, UInt<1>(0h0)) node _T_668 = mux(_T_210, deq_vec[2][0].exception, UInt<1>(0h0)) node _T_669 = mux(_T_211, deq_vec[3][0].exception, UInt<1>(0h0)) node _T_670 = mux(_T_212, deq_vec[4][0].exception, UInt<1>(0h0)) node _T_671 = mux(_T_213, deq_vec[5][0].exception, UInt<1>(0h0)) node _T_672 = mux(_T_214, deq_vec[6][0].exception, UInt<1>(0h0)) node _T_673 = mux(_T_215, deq_vec[7][0].exception, UInt<1>(0h0)) node _T_674 = or(_T_666, _T_667) node _T_675 = or(_T_674, _T_668) node _T_676 = or(_T_675, _T_669) node _T_677 = or(_T_676, _T_670) node _T_678 = or(_T_677, _T_671) node _T_679 = or(_T_678, _T_672) node _T_680 = or(_T_679, _T_673) wire _WIRE_32 : UInt<1> connect _WIRE_32, _T_680 connect _WIRE_1.exception, _WIRE_32 node _T_681 = mux(_T_208, deq_vec[0][0].stale_pdst, UInt<1>(0h0)) node _T_682 = mux(_T_209, deq_vec[1][0].stale_pdst, UInt<1>(0h0)) node _T_683 = mux(_T_210, deq_vec[2][0].stale_pdst, UInt<1>(0h0)) node _T_684 = mux(_T_211, deq_vec[3][0].stale_pdst, UInt<1>(0h0)) node _T_685 = mux(_T_212, deq_vec[4][0].stale_pdst, UInt<1>(0h0)) node _T_686 = mux(_T_213, deq_vec[5][0].stale_pdst, UInt<1>(0h0)) node _T_687 = mux(_T_214, deq_vec[6][0].stale_pdst, UInt<1>(0h0)) node _T_688 = mux(_T_215, deq_vec[7][0].stale_pdst, UInt<1>(0h0)) node _T_689 = or(_T_681, _T_682) node _T_690 = or(_T_689, _T_683) node _T_691 = or(_T_690, _T_684) node _T_692 = or(_T_691, _T_685) node _T_693 = or(_T_692, _T_686) node _T_694 = or(_T_693, _T_687) node _T_695 = or(_T_694, _T_688) wire _WIRE_33 : UInt<7> connect _WIRE_33, _T_695 connect _WIRE_1.stale_pdst, _WIRE_33 node _T_696 = mux(_T_208, deq_vec[0][0].ppred_busy, UInt<1>(0h0)) node _T_697 = mux(_T_209, deq_vec[1][0].ppred_busy, UInt<1>(0h0)) node _T_698 = mux(_T_210, deq_vec[2][0].ppred_busy, UInt<1>(0h0)) node _T_699 = mux(_T_211, deq_vec[3][0].ppred_busy, UInt<1>(0h0)) node _T_700 = mux(_T_212, deq_vec[4][0].ppred_busy, UInt<1>(0h0)) node _T_701 = mux(_T_213, deq_vec[5][0].ppred_busy, UInt<1>(0h0)) node _T_702 = mux(_T_214, deq_vec[6][0].ppred_busy, UInt<1>(0h0)) node _T_703 = mux(_T_215, deq_vec[7][0].ppred_busy, UInt<1>(0h0)) node _T_704 = or(_T_696, _T_697) node _T_705 = or(_T_704, _T_698) node _T_706 = or(_T_705, _T_699) node _T_707 = or(_T_706, _T_700) node _T_708 = or(_T_707, _T_701) node _T_709 = or(_T_708, _T_702) node _T_710 = or(_T_709, _T_703) wire _WIRE_34 : UInt<1> connect _WIRE_34, _T_710 connect _WIRE_1.ppred_busy, _WIRE_34 node _T_711 = mux(_T_208, deq_vec[0][0].prs3_busy, UInt<1>(0h0)) node _T_712 = mux(_T_209, deq_vec[1][0].prs3_busy, UInt<1>(0h0)) node _T_713 = mux(_T_210, deq_vec[2][0].prs3_busy, UInt<1>(0h0)) node _T_714 = mux(_T_211, deq_vec[3][0].prs3_busy, UInt<1>(0h0)) node _T_715 = mux(_T_212, deq_vec[4][0].prs3_busy, UInt<1>(0h0)) node _T_716 = mux(_T_213, deq_vec[5][0].prs3_busy, UInt<1>(0h0)) node _T_717 = mux(_T_214, deq_vec[6][0].prs3_busy, UInt<1>(0h0)) node _T_718 = mux(_T_215, deq_vec[7][0].prs3_busy, UInt<1>(0h0)) node _T_719 = or(_T_711, _T_712) node _T_720 = or(_T_719, _T_713) node _T_721 = or(_T_720, _T_714) node _T_722 = or(_T_721, _T_715) node _T_723 = or(_T_722, _T_716) node _T_724 = or(_T_723, _T_717) node _T_725 = or(_T_724, _T_718) wire _WIRE_35 : UInt<1> connect _WIRE_35, _T_725 connect _WIRE_1.prs3_busy, _WIRE_35 node _T_726 = mux(_T_208, deq_vec[0][0].prs2_busy, UInt<1>(0h0)) node _T_727 = mux(_T_209, deq_vec[1][0].prs2_busy, UInt<1>(0h0)) node _T_728 = mux(_T_210, deq_vec[2][0].prs2_busy, UInt<1>(0h0)) node _T_729 = mux(_T_211, deq_vec[3][0].prs2_busy, UInt<1>(0h0)) node _T_730 = mux(_T_212, deq_vec[4][0].prs2_busy, UInt<1>(0h0)) node _T_731 = mux(_T_213, deq_vec[5][0].prs2_busy, UInt<1>(0h0)) node _T_732 = mux(_T_214, deq_vec[6][0].prs2_busy, UInt<1>(0h0)) node _T_733 = mux(_T_215, deq_vec[7][0].prs2_busy, UInt<1>(0h0)) node _T_734 = or(_T_726, _T_727) node _T_735 = or(_T_734, _T_728) node _T_736 = or(_T_735, _T_729) node _T_737 = or(_T_736, _T_730) node _T_738 = or(_T_737, _T_731) node _T_739 = or(_T_738, _T_732) node _T_740 = or(_T_739, _T_733) wire _WIRE_36 : UInt<1> connect _WIRE_36, _T_740 connect _WIRE_1.prs2_busy, _WIRE_36 node _T_741 = mux(_T_208, deq_vec[0][0].prs1_busy, UInt<1>(0h0)) node _T_742 = mux(_T_209, deq_vec[1][0].prs1_busy, UInt<1>(0h0)) node _T_743 = mux(_T_210, deq_vec[2][0].prs1_busy, UInt<1>(0h0)) node _T_744 = mux(_T_211, deq_vec[3][0].prs1_busy, UInt<1>(0h0)) node _T_745 = mux(_T_212, deq_vec[4][0].prs1_busy, UInt<1>(0h0)) node _T_746 = mux(_T_213, deq_vec[5][0].prs1_busy, UInt<1>(0h0)) node _T_747 = mux(_T_214, deq_vec[6][0].prs1_busy, UInt<1>(0h0)) node _T_748 = mux(_T_215, deq_vec[7][0].prs1_busy, UInt<1>(0h0)) node _T_749 = or(_T_741, _T_742) node _T_750 = or(_T_749, _T_743) node _T_751 = or(_T_750, _T_744) node _T_752 = or(_T_751, _T_745) node _T_753 = or(_T_752, _T_746) node _T_754 = or(_T_753, _T_747) node _T_755 = or(_T_754, _T_748) wire _WIRE_37 : UInt<1> connect _WIRE_37, _T_755 connect _WIRE_1.prs1_busy, _WIRE_37 node _T_756 = mux(_T_208, deq_vec[0][0].ppred, UInt<1>(0h0)) node _T_757 = mux(_T_209, deq_vec[1][0].ppred, UInt<1>(0h0)) node _T_758 = mux(_T_210, deq_vec[2][0].ppred, UInt<1>(0h0)) node _T_759 = mux(_T_211, deq_vec[3][0].ppred, UInt<1>(0h0)) node _T_760 = mux(_T_212, deq_vec[4][0].ppred, UInt<1>(0h0)) node _T_761 = mux(_T_213, deq_vec[5][0].ppred, UInt<1>(0h0)) node _T_762 = mux(_T_214, deq_vec[6][0].ppred, UInt<1>(0h0)) node _T_763 = mux(_T_215, deq_vec[7][0].ppred, UInt<1>(0h0)) node _T_764 = or(_T_756, _T_757) node _T_765 = or(_T_764, _T_758) node _T_766 = or(_T_765, _T_759) node _T_767 = or(_T_766, _T_760) node _T_768 = or(_T_767, _T_761) node _T_769 = or(_T_768, _T_762) node _T_770 = or(_T_769, _T_763) wire _WIRE_38 : UInt<5> connect _WIRE_38, _T_770 connect _WIRE_1.ppred, _WIRE_38 node _T_771 = mux(_T_208, deq_vec[0][0].prs3, UInt<1>(0h0)) node _T_772 = mux(_T_209, deq_vec[1][0].prs3, UInt<1>(0h0)) node _T_773 = mux(_T_210, deq_vec[2][0].prs3, UInt<1>(0h0)) node _T_774 = mux(_T_211, deq_vec[3][0].prs3, UInt<1>(0h0)) node _T_775 = mux(_T_212, deq_vec[4][0].prs3, UInt<1>(0h0)) node _T_776 = mux(_T_213, deq_vec[5][0].prs3, UInt<1>(0h0)) node _T_777 = mux(_T_214, deq_vec[6][0].prs3, UInt<1>(0h0)) node _T_778 = mux(_T_215, deq_vec[7][0].prs3, UInt<1>(0h0)) node _T_779 = or(_T_771, _T_772) node _T_780 = or(_T_779, _T_773) node _T_781 = or(_T_780, _T_774) node _T_782 = or(_T_781, _T_775) node _T_783 = or(_T_782, _T_776) node _T_784 = or(_T_783, _T_777) node _T_785 = or(_T_784, _T_778) wire _WIRE_39 : UInt<7> connect _WIRE_39, _T_785 connect _WIRE_1.prs3, _WIRE_39 node _T_786 = mux(_T_208, deq_vec[0][0].prs2, UInt<1>(0h0)) node _T_787 = mux(_T_209, deq_vec[1][0].prs2, UInt<1>(0h0)) node _T_788 = mux(_T_210, deq_vec[2][0].prs2, UInt<1>(0h0)) node _T_789 = mux(_T_211, deq_vec[3][0].prs2, UInt<1>(0h0)) node _T_790 = mux(_T_212, deq_vec[4][0].prs2, UInt<1>(0h0)) node _T_791 = mux(_T_213, deq_vec[5][0].prs2, UInt<1>(0h0)) node _T_792 = mux(_T_214, deq_vec[6][0].prs2, UInt<1>(0h0)) node _T_793 = mux(_T_215, deq_vec[7][0].prs2, UInt<1>(0h0)) node _T_794 = or(_T_786, _T_787) node _T_795 = or(_T_794, _T_788) node _T_796 = or(_T_795, _T_789) node _T_797 = or(_T_796, _T_790) node _T_798 = or(_T_797, _T_791) node _T_799 = or(_T_798, _T_792) node _T_800 = or(_T_799, _T_793) wire _WIRE_40 : UInt<7> connect _WIRE_40, _T_800 connect _WIRE_1.prs2, _WIRE_40 node _T_801 = mux(_T_208, deq_vec[0][0].prs1, UInt<1>(0h0)) node _T_802 = mux(_T_209, deq_vec[1][0].prs1, UInt<1>(0h0)) node _T_803 = mux(_T_210, deq_vec[2][0].prs1, UInt<1>(0h0)) node _T_804 = mux(_T_211, deq_vec[3][0].prs1, UInt<1>(0h0)) node _T_805 = mux(_T_212, deq_vec[4][0].prs1, UInt<1>(0h0)) node _T_806 = mux(_T_213, deq_vec[5][0].prs1, UInt<1>(0h0)) node _T_807 = mux(_T_214, deq_vec[6][0].prs1, UInt<1>(0h0)) node _T_808 = mux(_T_215, deq_vec[7][0].prs1, UInt<1>(0h0)) node _T_809 = or(_T_801, _T_802) node _T_810 = or(_T_809, _T_803) node _T_811 = or(_T_810, _T_804) node _T_812 = or(_T_811, _T_805) node _T_813 = or(_T_812, _T_806) node _T_814 = or(_T_813, _T_807) node _T_815 = or(_T_814, _T_808) wire _WIRE_41 : UInt<7> connect _WIRE_41, _T_815 connect _WIRE_1.prs1, _WIRE_41 node _T_816 = mux(_T_208, deq_vec[0][0].pdst, UInt<1>(0h0)) node _T_817 = mux(_T_209, deq_vec[1][0].pdst, UInt<1>(0h0)) node _T_818 = mux(_T_210, deq_vec[2][0].pdst, UInt<1>(0h0)) node _T_819 = mux(_T_211, deq_vec[3][0].pdst, UInt<1>(0h0)) node _T_820 = mux(_T_212, deq_vec[4][0].pdst, UInt<1>(0h0)) node _T_821 = mux(_T_213, deq_vec[5][0].pdst, UInt<1>(0h0)) node _T_822 = mux(_T_214, deq_vec[6][0].pdst, UInt<1>(0h0)) node _T_823 = mux(_T_215, deq_vec[7][0].pdst, UInt<1>(0h0)) node _T_824 = or(_T_816, _T_817) node _T_825 = or(_T_824, _T_818) node _T_826 = or(_T_825, _T_819) node _T_827 = or(_T_826, _T_820) node _T_828 = or(_T_827, _T_821) node _T_829 = or(_T_828, _T_822) node _T_830 = or(_T_829, _T_823) wire _WIRE_42 : UInt<7> connect _WIRE_42, _T_830 connect _WIRE_1.pdst, _WIRE_42 node _T_831 = mux(_T_208, deq_vec[0][0].rxq_idx, UInt<1>(0h0)) node _T_832 = mux(_T_209, deq_vec[1][0].rxq_idx, UInt<1>(0h0)) node _T_833 = mux(_T_210, deq_vec[2][0].rxq_idx, UInt<1>(0h0)) node _T_834 = mux(_T_211, deq_vec[3][0].rxq_idx, UInt<1>(0h0)) node _T_835 = mux(_T_212, deq_vec[4][0].rxq_idx, UInt<1>(0h0)) node _T_836 = mux(_T_213, deq_vec[5][0].rxq_idx, UInt<1>(0h0)) node _T_837 = mux(_T_214, deq_vec[6][0].rxq_idx, UInt<1>(0h0)) node _T_838 = mux(_T_215, deq_vec[7][0].rxq_idx, UInt<1>(0h0)) node _T_839 = or(_T_831, _T_832) node _T_840 = or(_T_839, _T_833) node _T_841 = or(_T_840, _T_834) node _T_842 = or(_T_841, _T_835) node _T_843 = or(_T_842, _T_836) node _T_844 = or(_T_843, _T_837) node _T_845 = or(_T_844, _T_838) wire _WIRE_43 : UInt<2> connect _WIRE_43, _T_845 connect _WIRE_1.rxq_idx, _WIRE_43 node _T_846 = mux(_T_208, deq_vec[0][0].stq_idx, UInt<1>(0h0)) node _T_847 = mux(_T_209, deq_vec[1][0].stq_idx, UInt<1>(0h0)) node _T_848 = mux(_T_210, deq_vec[2][0].stq_idx, UInt<1>(0h0)) node _T_849 = mux(_T_211, deq_vec[3][0].stq_idx, UInt<1>(0h0)) node _T_850 = mux(_T_212, deq_vec[4][0].stq_idx, UInt<1>(0h0)) node _T_851 = mux(_T_213, deq_vec[5][0].stq_idx, UInt<1>(0h0)) node _T_852 = mux(_T_214, deq_vec[6][0].stq_idx, UInt<1>(0h0)) node _T_853 = mux(_T_215, deq_vec[7][0].stq_idx, UInt<1>(0h0)) node _T_854 = or(_T_846, _T_847) node _T_855 = or(_T_854, _T_848) node _T_856 = or(_T_855, _T_849) node _T_857 = or(_T_856, _T_850) node _T_858 = or(_T_857, _T_851) node _T_859 = or(_T_858, _T_852) node _T_860 = or(_T_859, _T_853) wire _WIRE_44 : UInt<4> connect _WIRE_44, _T_860 connect _WIRE_1.stq_idx, _WIRE_44 node _T_861 = mux(_T_208, deq_vec[0][0].ldq_idx, UInt<1>(0h0)) node _T_862 = mux(_T_209, deq_vec[1][0].ldq_idx, UInt<1>(0h0)) node _T_863 = mux(_T_210, deq_vec[2][0].ldq_idx, UInt<1>(0h0)) node _T_864 = mux(_T_211, deq_vec[3][0].ldq_idx, UInt<1>(0h0)) node _T_865 = mux(_T_212, deq_vec[4][0].ldq_idx, UInt<1>(0h0)) node _T_866 = mux(_T_213, deq_vec[5][0].ldq_idx, UInt<1>(0h0)) node _T_867 = mux(_T_214, deq_vec[6][0].ldq_idx, UInt<1>(0h0)) node _T_868 = mux(_T_215, deq_vec[7][0].ldq_idx, UInt<1>(0h0)) node _T_869 = or(_T_861, _T_862) node _T_870 = or(_T_869, _T_863) node _T_871 = or(_T_870, _T_864) node _T_872 = or(_T_871, _T_865) node _T_873 = or(_T_872, _T_866) node _T_874 = or(_T_873, _T_867) node _T_875 = or(_T_874, _T_868) wire _WIRE_45 : UInt<4> connect _WIRE_45, _T_875 connect _WIRE_1.ldq_idx, _WIRE_45 node _T_876 = mux(_T_208, deq_vec[0][0].rob_idx, UInt<1>(0h0)) node _T_877 = mux(_T_209, deq_vec[1][0].rob_idx, UInt<1>(0h0)) node _T_878 = mux(_T_210, deq_vec[2][0].rob_idx, UInt<1>(0h0)) node _T_879 = mux(_T_211, deq_vec[3][0].rob_idx, UInt<1>(0h0)) node _T_880 = mux(_T_212, deq_vec[4][0].rob_idx, UInt<1>(0h0)) node _T_881 = mux(_T_213, deq_vec[5][0].rob_idx, UInt<1>(0h0)) node _T_882 = mux(_T_214, deq_vec[6][0].rob_idx, UInt<1>(0h0)) node _T_883 = mux(_T_215, deq_vec[7][0].rob_idx, UInt<1>(0h0)) node _T_884 = or(_T_876, _T_877) node _T_885 = or(_T_884, _T_878) node _T_886 = or(_T_885, _T_879) node _T_887 = or(_T_886, _T_880) node _T_888 = or(_T_887, _T_881) node _T_889 = or(_T_888, _T_882) node _T_890 = or(_T_889, _T_883) wire _WIRE_46 : UInt<6> connect _WIRE_46, _T_890 connect _WIRE_1.rob_idx, _WIRE_46 wire _WIRE_47 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _T_891 = mux(_T_208, deq_vec[0][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_892 = mux(_T_209, deq_vec[1][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_893 = mux(_T_210, deq_vec[2][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_894 = mux(_T_211, deq_vec[3][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_895 = mux(_T_212, deq_vec[4][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_896 = mux(_T_213, deq_vec[5][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_897 = mux(_T_214, deq_vec[6][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_898 = mux(_T_215, deq_vec[7][0].fp_ctrl.vec, UInt<1>(0h0)) node _T_899 = or(_T_891, _T_892) node _T_900 = or(_T_899, _T_893) node _T_901 = or(_T_900, _T_894) node _T_902 = or(_T_901, _T_895) node _T_903 = or(_T_902, _T_896) node _T_904 = or(_T_903, _T_897) node _T_905 = or(_T_904, _T_898) wire _WIRE_48 : UInt<1> connect _WIRE_48, _T_905 connect _WIRE_47.vec, _WIRE_48 node _T_906 = mux(_T_208, deq_vec[0][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_907 = mux(_T_209, deq_vec[1][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_908 = mux(_T_210, deq_vec[2][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_909 = mux(_T_211, deq_vec[3][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_910 = mux(_T_212, deq_vec[4][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_911 = mux(_T_213, deq_vec[5][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_912 = mux(_T_214, deq_vec[6][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_913 = mux(_T_215, deq_vec[7][0].fp_ctrl.wflags, UInt<1>(0h0)) node _T_914 = or(_T_906, _T_907) node _T_915 = or(_T_914, _T_908) node _T_916 = or(_T_915, _T_909) node _T_917 = or(_T_916, _T_910) node _T_918 = or(_T_917, _T_911) node _T_919 = or(_T_918, _T_912) node _T_920 = or(_T_919, _T_913) wire _WIRE_49 : UInt<1> connect _WIRE_49, _T_920 connect _WIRE_47.wflags, _WIRE_49 node _T_921 = mux(_T_208, deq_vec[0][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_922 = mux(_T_209, deq_vec[1][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_923 = mux(_T_210, deq_vec[2][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_924 = mux(_T_211, deq_vec[3][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_925 = mux(_T_212, deq_vec[4][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_926 = mux(_T_213, deq_vec[5][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_927 = mux(_T_214, deq_vec[6][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_928 = mux(_T_215, deq_vec[7][0].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_929 = or(_T_921, _T_922) node _T_930 = or(_T_929, _T_923) node _T_931 = or(_T_930, _T_924) node _T_932 = or(_T_931, _T_925) node _T_933 = or(_T_932, _T_926) node _T_934 = or(_T_933, _T_927) node _T_935 = or(_T_934, _T_928) wire _WIRE_50 : UInt<1> connect _WIRE_50, _T_935 connect _WIRE_47.sqrt, _WIRE_50 node _T_936 = mux(_T_208, deq_vec[0][0].fp_ctrl.div, UInt<1>(0h0)) node _T_937 = mux(_T_209, deq_vec[1][0].fp_ctrl.div, UInt<1>(0h0)) node _T_938 = mux(_T_210, deq_vec[2][0].fp_ctrl.div, UInt<1>(0h0)) node _T_939 = mux(_T_211, deq_vec[3][0].fp_ctrl.div, UInt<1>(0h0)) node _T_940 = mux(_T_212, deq_vec[4][0].fp_ctrl.div, UInt<1>(0h0)) node _T_941 = mux(_T_213, deq_vec[5][0].fp_ctrl.div, UInt<1>(0h0)) node _T_942 = mux(_T_214, deq_vec[6][0].fp_ctrl.div, UInt<1>(0h0)) node _T_943 = mux(_T_215, deq_vec[7][0].fp_ctrl.div, UInt<1>(0h0)) node _T_944 = or(_T_936, _T_937) node _T_945 = or(_T_944, _T_938) node _T_946 = or(_T_945, _T_939) node _T_947 = or(_T_946, _T_940) node _T_948 = or(_T_947, _T_941) node _T_949 = or(_T_948, _T_942) node _T_950 = or(_T_949, _T_943) wire _WIRE_51 : UInt<1> connect _WIRE_51, _T_950 connect _WIRE_47.div, _WIRE_51 node _T_951 = mux(_T_208, deq_vec[0][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_952 = mux(_T_209, deq_vec[1][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_953 = mux(_T_210, deq_vec[2][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_954 = mux(_T_211, deq_vec[3][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_955 = mux(_T_212, deq_vec[4][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_956 = mux(_T_213, deq_vec[5][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_957 = mux(_T_214, deq_vec[6][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_958 = mux(_T_215, deq_vec[7][0].fp_ctrl.fma, UInt<1>(0h0)) node _T_959 = or(_T_951, _T_952) node _T_960 = or(_T_959, _T_953) node _T_961 = or(_T_960, _T_954) node _T_962 = or(_T_961, _T_955) node _T_963 = or(_T_962, _T_956) node _T_964 = or(_T_963, _T_957) node _T_965 = or(_T_964, _T_958) wire _WIRE_52 : UInt<1> connect _WIRE_52, _T_965 connect _WIRE_47.fma, _WIRE_52 node _T_966 = mux(_T_208, deq_vec[0][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_967 = mux(_T_209, deq_vec[1][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_968 = mux(_T_210, deq_vec[2][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_969 = mux(_T_211, deq_vec[3][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_970 = mux(_T_212, deq_vec[4][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_971 = mux(_T_213, deq_vec[5][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_972 = mux(_T_214, deq_vec[6][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_973 = mux(_T_215, deq_vec[7][0].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_974 = or(_T_966, _T_967) node _T_975 = or(_T_974, _T_968) node _T_976 = or(_T_975, _T_969) node _T_977 = or(_T_976, _T_970) node _T_978 = or(_T_977, _T_971) node _T_979 = or(_T_978, _T_972) node _T_980 = or(_T_979, _T_973) wire _WIRE_53 : UInt<1> connect _WIRE_53, _T_980 connect _WIRE_47.fastpipe, _WIRE_53 node _T_981 = mux(_T_208, deq_vec[0][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_982 = mux(_T_209, deq_vec[1][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_983 = mux(_T_210, deq_vec[2][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_984 = mux(_T_211, deq_vec[3][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_985 = mux(_T_212, deq_vec[4][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_986 = mux(_T_213, deq_vec[5][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_987 = mux(_T_214, deq_vec[6][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_988 = mux(_T_215, deq_vec[7][0].fp_ctrl.toint, UInt<1>(0h0)) node _T_989 = or(_T_981, _T_982) node _T_990 = or(_T_989, _T_983) node _T_991 = or(_T_990, _T_984) node _T_992 = or(_T_991, _T_985) node _T_993 = or(_T_992, _T_986) node _T_994 = or(_T_993, _T_987) node _T_995 = or(_T_994, _T_988) wire _WIRE_54 : UInt<1> connect _WIRE_54, _T_995 connect _WIRE_47.toint, _WIRE_54 node _T_996 = mux(_T_208, deq_vec[0][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_997 = mux(_T_209, deq_vec[1][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_998 = mux(_T_210, deq_vec[2][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_999 = mux(_T_211, deq_vec[3][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1000 = mux(_T_212, deq_vec[4][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1001 = mux(_T_213, deq_vec[5][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1002 = mux(_T_214, deq_vec[6][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1003 = mux(_T_215, deq_vec[7][0].fp_ctrl.fromint, UInt<1>(0h0)) node _T_1004 = or(_T_996, _T_997) node _T_1005 = or(_T_1004, _T_998) node _T_1006 = or(_T_1005, _T_999) node _T_1007 = or(_T_1006, _T_1000) node _T_1008 = or(_T_1007, _T_1001) node _T_1009 = or(_T_1008, _T_1002) node _T_1010 = or(_T_1009, _T_1003) wire _WIRE_55 : UInt<1> connect _WIRE_55, _T_1010 connect _WIRE_47.fromint, _WIRE_55 node _T_1011 = mux(_T_208, deq_vec[0][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1012 = mux(_T_209, deq_vec[1][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1013 = mux(_T_210, deq_vec[2][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1014 = mux(_T_211, deq_vec[3][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1015 = mux(_T_212, deq_vec[4][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1016 = mux(_T_213, deq_vec[5][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1017 = mux(_T_214, deq_vec[6][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1018 = mux(_T_215, deq_vec[7][0].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_1019 = or(_T_1011, _T_1012) node _T_1020 = or(_T_1019, _T_1013) node _T_1021 = or(_T_1020, _T_1014) node _T_1022 = or(_T_1021, _T_1015) node _T_1023 = or(_T_1022, _T_1016) node _T_1024 = or(_T_1023, _T_1017) node _T_1025 = or(_T_1024, _T_1018) wire _WIRE_56 : UInt<2> connect _WIRE_56, _T_1025 connect _WIRE_47.typeTagOut, _WIRE_56 node _T_1026 = mux(_T_208, deq_vec[0][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1027 = mux(_T_209, deq_vec[1][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1028 = mux(_T_210, deq_vec[2][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1029 = mux(_T_211, deq_vec[3][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1030 = mux(_T_212, deq_vec[4][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1031 = mux(_T_213, deq_vec[5][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1032 = mux(_T_214, deq_vec[6][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1033 = mux(_T_215, deq_vec[7][0].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_1034 = or(_T_1026, _T_1027) node _T_1035 = or(_T_1034, _T_1028) node _T_1036 = or(_T_1035, _T_1029) node _T_1037 = or(_T_1036, _T_1030) node _T_1038 = or(_T_1037, _T_1031) node _T_1039 = or(_T_1038, _T_1032) node _T_1040 = or(_T_1039, _T_1033) wire _WIRE_57 : UInt<2> connect _WIRE_57, _T_1040 connect _WIRE_47.typeTagIn, _WIRE_57 node _T_1041 = mux(_T_208, deq_vec[0][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1042 = mux(_T_209, deq_vec[1][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1043 = mux(_T_210, deq_vec[2][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1044 = mux(_T_211, deq_vec[3][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1045 = mux(_T_212, deq_vec[4][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1046 = mux(_T_213, deq_vec[5][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1047 = mux(_T_214, deq_vec[6][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1048 = mux(_T_215, deq_vec[7][0].fp_ctrl.swap23, UInt<1>(0h0)) node _T_1049 = or(_T_1041, _T_1042) node _T_1050 = or(_T_1049, _T_1043) node _T_1051 = or(_T_1050, _T_1044) node _T_1052 = or(_T_1051, _T_1045) node _T_1053 = or(_T_1052, _T_1046) node _T_1054 = or(_T_1053, _T_1047) node _T_1055 = or(_T_1054, _T_1048) wire _WIRE_58 : UInt<1> connect _WIRE_58, _T_1055 connect _WIRE_47.swap23, _WIRE_58 node _T_1056 = mux(_T_208, deq_vec[0][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1057 = mux(_T_209, deq_vec[1][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1058 = mux(_T_210, deq_vec[2][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1059 = mux(_T_211, deq_vec[3][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1060 = mux(_T_212, deq_vec[4][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1061 = mux(_T_213, deq_vec[5][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1062 = mux(_T_214, deq_vec[6][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1063 = mux(_T_215, deq_vec[7][0].fp_ctrl.swap12, UInt<1>(0h0)) node _T_1064 = or(_T_1056, _T_1057) node _T_1065 = or(_T_1064, _T_1058) node _T_1066 = or(_T_1065, _T_1059) node _T_1067 = or(_T_1066, _T_1060) node _T_1068 = or(_T_1067, _T_1061) node _T_1069 = or(_T_1068, _T_1062) node _T_1070 = or(_T_1069, _T_1063) wire _WIRE_59 : UInt<1> connect _WIRE_59, _T_1070 connect _WIRE_47.swap12, _WIRE_59 node _T_1071 = mux(_T_208, deq_vec[0][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1072 = mux(_T_209, deq_vec[1][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1073 = mux(_T_210, deq_vec[2][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1074 = mux(_T_211, deq_vec[3][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1075 = mux(_T_212, deq_vec[4][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1076 = mux(_T_213, deq_vec[5][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1077 = mux(_T_214, deq_vec[6][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1078 = mux(_T_215, deq_vec[7][0].fp_ctrl.ren3, UInt<1>(0h0)) node _T_1079 = or(_T_1071, _T_1072) node _T_1080 = or(_T_1079, _T_1073) node _T_1081 = or(_T_1080, _T_1074) node _T_1082 = or(_T_1081, _T_1075) node _T_1083 = or(_T_1082, _T_1076) node _T_1084 = or(_T_1083, _T_1077) node _T_1085 = or(_T_1084, _T_1078) wire _WIRE_60 : UInt<1> connect _WIRE_60, _T_1085 connect _WIRE_47.ren3, _WIRE_60 node _T_1086 = mux(_T_208, deq_vec[0][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1087 = mux(_T_209, deq_vec[1][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1088 = mux(_T_210, deq_vec[2][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1089 = mux(_T_211, deq_vec[3][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1090 = mux(_T_212, deq_vec[4][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1091 = mux(_T_213, deq_vec[5][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1092 = mux(_T_214, deq_vec[6][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1093 = mux(_T_215, deq_vec[7][0].fp_ctrl.ren2, UInt<1>(0h0)) node _T_1094 = or(_T_1086, _T_1087) node _T_1095 = or(_T_1094, _T_1088) node _T_1096 = or(_T_1095, _T_1089) node _T_1097 = or(_T_1096, _T_1090) node _T_1098 = or(_T_1097, _T_1091) node _T_1099 = or(_T_1098, _T_1092) node _T_1100 = or(_T_1099, _T_1093) wire _WIRE_61 : UInt<1> connect _WIRE_61, _T_1100 connect _WIRE_47.ren2, _WIRE_61 node _T_1101 = mux(_T_208, deq_vec[0][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1102 = mux(_T_209, deq_vec[1][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1103 = mux(_T_210, deq_vec[2][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1104 = mux(_T_211, deq_vec[3][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1105 = mux(_T_212, deq_vec[4][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1106 = mux(_T_213, deq_vec[5][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1107 = mux(_T_214, deq_vec[6][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1108 = mux(_T_215, deq_vec[7][0].fp_ctrl.ren1, UInt<1>(0h0)) node _T_1109 = or(_T_1101, _T_1102) node _T_1110 = or(_T_1109, _T_1103) node _T_1111 = or(_T_1110, _T_1104) node _T_1112 = or(_T_1111, _T_1105) node _T_1113 = or(_T_1112, _T_1106) node _T_1114 = or(_T_1113, _T_1107) node _T_1115 = or(_T_1114, _T_1108) wire _WIRE_62 : UInt<1> connect _WIRE_62, _T_1115 connect _WIRE_47.ren1, _WIRE_62 node _T_1116 = mux(_T_208, deq_vec[0][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1117 = mux(_T_209, deq_vec[1][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1118 = mux(_T_210, deq_vec[2][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1119 = mux(_T_211, deq_vec[3][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1120 = mux(_T_212, deq_vec[4][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1121 = mux(_T_213, deq_vec[5][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1122 = mux(_T_214, deq_vec[6][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1123 = mux(_T_215, deq_vec[7][0].fp_ctrl.wen, UInt<1>(0h0)) node _T_1124 = or(_T_1116, _T_1117) node _T_1125 = or(_T_1124, _T_1118) node _T_1126 = or(_T_1125, _T_1119) node _T_1127 = or(_T_1126, _T_1120) node _T_1128 = or(_T_1127, _T_1121) node _T_1129 = or(_T_1128, _T_1122) node _T_1130 = or(_T_1129, _T_1123) wire _WIRE_63 : UInt<1> connect _WIRE_63, _T_1130 connect _WIRE_47.wen, _WIRE_63 node _T_1131 = mux(_T_208, deq_vec[0][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1132 = mux(_T_209, deq_vec[1][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1133 = mux(_T_210, deq_vec[2][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1134 = mux(_T_211, deq_vec[3][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1135 = mux(_T_212, deq_vec[4][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1136 = mux(_T_213, deq_vec[5][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1137 = mux(_T_214, deq_vec[6][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1138 = mux(_T_215, deq_vec[7][0].fp_ctrl.ldst, UInt<1>(0h0)) node _T_1139 = or(_T_1131, _T_1132) node _T_1140 = or(_T_1139, _T_1133) node _T_1141 = or(_T_1140, _T_1134) node _T_1142 = or(_T_1141, _T_1135) node _T_1143 = or(_T_1142, _T_1136) node _T_1144 = or(_T_1143, _T_1137) node _T_1145 = or(_T_1144, _T_1138) wire _WIRE_64 : UInt<1> connect _WIRE_64, _T_1145 connect _WIRE_47.ldst, _WIRE_64 connect _WIRE_1.fp_ctrl, _WIRE_47 node _T_1146 = mux(_T_208, deq_vec[0][0].op2_sel, UInt<1>(0h0)) node _T_1147 = mux(_T_209, deq_vec[1][0].op2_sel, UInt<1>(0h0)) node _T_1148 = mux(_T_210, deq_vec[2][0].op2_sel, UInt<1>(0h0)) node _T_1149 = mux(_T_211, deq_vec[3][0].op2_sel, UInt<1>(0h0)) node _T_1150 = mux(_T_212, deq_vec[4][0].op2_sel, UInt<1>(0h0)) node _T_1151 = mux(_T_213, deq_vec[5][0].op2_sel, UInt<1>(0h0)) node _T_1152 = mux(_T_214, deq_vec[6][0].op2_sel, UInt<1>(0h0)) node _T_1153 = mux(_T_215, deq_vec[7][0].op2_sel, UInt<1>(0h0)) node _T_1154 = or(_T_1146, _T_1147) node _T_1155 = or(_T_1154, _T_1148) node _T_1156 = or(_T_1155, _T_1149) node _T_1157 = or(_T_1156, _T_1150) node _T_1158 = or(_T_1157, _T_1151) node _T_1159 = or(_T_1158, _T_1152) node _T_1160 = or(_T_1159, _T_1153) wire _WIRE_65 : UInt<3> connect _WIRE_65, _T_1160 connect _WIRE_1.op2_sel, _WIRE_65 node _T_1161 = mux(_T_208, deq_vec[0][0].op1_sel, UInt<1>(0h0)) node _T_1162 = mux(_T_209, deq_vec[1][0].op1_sel, UInt<1>(0h0)) node _T_1163 = mux(_T_210, deq_vec[2][0].op1_sel, UInt<1>(0h0)) node _T_1164 = mux(_T_211, deq_vec[3][0].op1_sel, UInt<1>(0h0)) node _T_1165 = mux(_T_212, deq_vec[4][0].op1_sel, UInt<1>(0h0)) node _T_1166 = mux(_T_213, deq_vec[5][0].op1_sel, UInt<1>(0h0)) node _T_1167 = mux(_T_214, deq_vec[6][0].op1_sel, UInt<1>(0h0)) node _T_1168 = mux(_T_215, deq_vec[7][0].op1_sel, UInt<1>(0h0)) node _T_1169 = or(_T_1161, _T_1162) node _T_1170 = or(_T_1169, _T_1163) node _T_1171 = or(_T_1170, _T_1164) node _T_1172 = or(_T_1171, _T_1165) node _T_1173 = or(_T_1172, _T_1166) node _T_1174 = or(_T_1173, _T_1167) node _T_1175 = or(_T_1174, _T_1168) wire _WIRE_66 : UInt<2> connect _WIRE_66, _T_1175 connect _WIRE_1.op1_sel, _WIRE_66 node _T_1176 = mux(_T_208, deq_vec[0][0].imm_packed, UInt<1>(0h0)) node _T_1177 = mux(_T_209, deq_vec[1][0].imm_packed, UInt<1>(0h0)) node _T_1178 = mux(_T_210, deq_vec[2][0].imm_packed, UInt<1>(0h0)) node _T_1179 = mux(_T_211, deq_vec[3][0].imm_packed, UInt<1>(0h0)) node _T_1180 = mux(_T_212, deq_vec[4][0].imm_packed, UInt<1>(0h0)) node _T_1181 = mux(_T_213, deq_vec[5][0].imm_packed, UInt<1>(0h0)) node _T_1182 = mux(_T_214, deq_vec[6][0].imm_packed, UInt<1>(0h0)) node _T_1183 = mux(_T_215, deq_vec[7][0].imm_packed, UInt<1>(0h0)) node _T_1184 = or(_T_1176, _T_1177) node _T_1185 = or(_T_1184, _T_1178) node _T_1186 = or(_T_1185, _T_1179) node _T_1187 = or(_T_1186, _T_1180) node _T_1188 = or(_T_1187, _T_1181) node _T_1189 = or(_T_1188, _T_1182) node _T_1190 = or(_T_1189, _T_1183) wire _WIRE_67 : UInt<20> connect _WIRE_67, _T_1190 connect _WIRE_1.imm_packed, _WIRE_67 node _T_1191 = mux(_T_208, deq_vec[0][0].pimm, UInt<1>(0h0)) node _T_1192 = mux(_T_209, deq_vec[1][0].pimm, UInt<1>(0h0)) node _T_1193 = mux(_T_210, deq_vec[2][0].pimm, UInt<1>(0h0)) node _T_1194 = mux(_T_211, deq_vec[3][0].pimm, UInt<1>(0h0)) node _T_1195 = mux(_T_212, deq_vec[4][0].pimm, UInt<1>(0h0)) node _T_1196 = mux(_T_213, deq_vec[5][0].pimm, UInt<1>(0h0)) node _T_1197 = mux(_T_214, deq_vec[6][0].pimm, UInt<1>(0h0)) node _T_1198 = mux(_T_215, deq_vec[7][0].pimm, UInt<1>(0h0)) node _T_1199 = or(_T_1191, _T_1192) node _T_1200 = or(_T_1199, _T_1193) node _T_1201 = or(_T_1200, _T_1194) node _T_1202 = or(_T_1201, _T_1195) node _T_1203 = or(_T_1202, _T_1196) node _T_1204 = or(_T_1203, _T_1197) node _T_1205 = or(_T_1204, _T_1198) wire _WIRE_68 : UInt<5> connect _WIRE_68, _T_1205 connect _WIRE_1.pimm, _WIRE_68 node _T_1206 = mux(_T_208, deq_vec[0][0].imm_sel, UInt<1>(0h0)) node _T_1207 = mux(_T_209, deq_vec[1][0].imm_sel, UInt<1>(0h0)) node _T_1208 = mux(_T_210, deq_vec[2][0].imm_sel, UInt<1>(0h0)) node _T_1209 = mux(_T_211, deq_vec[3][0].imm_sel, UInt<1>(0h0)) node _T_1210 = mux(_T_212, deq_vec[4][0].imm_sel, UInt<1>(0h0)) node _T_1211 = mux(_T_213, deq_vec[5][0].imm_sel, UInt<1>(0h0)) node _T_1212 = mux(_T_214, deq_vec[6][0].imm_sel, UInt<1>(0h0)) node _T_1213 = mux(_T_215, deq_vec[7][0].imm_sel, UInt<1>(0h0)) node _T_1214 = or(_T_1206, _T_1207) node _T_1215 = or(_T_1214, _T_1208) node _T_1216 = or(_T_1215, _T_1209) node _T_1217 = or(_T_1216, _T_1210) node _T_1218 = or(_T_1217, _T_1211) node _T_1219 = or(_T_1218, _T_1212) node _T_1220 = or(_T_1219, _T_1213) wire _WIRE_69 : UInt<3> connect _WIRE_69, _T_1220 connect _WIRE_1.imm_sel, _WIRE_69 node _T_1221 = mux(_T_208, deq_vec[0][0].imm_rename, UInt<1>(0h0)) node _T_1222 = mux(_T_209, deq_vec[1][0].imm_rename, UInt<1>(0h0)) node _T_1223 = mux(_T_210, deq_vec[2][0].imm_rename, UInt<1>(0h0)) node _T_1224 = mux(_T_211, deq_vec[3][0].imm_rename, UInt<1>(0h0)) node _T_1225 = mux(_T_212, deq_vec[4][0].imm_rename, UInt<1>(0h0)) node _T_1226 = mux(_T_213, deq_vec[5][0].imm_rename, UInt<1>(0h0)) node _T_1227 = mux(_T_214, deq_vec[6][0].imm_rename, UInt<1>(0h0)) node _T_1228 = mux(_T_215, deq_vec[7][0].imm_rename, UInt<1>(0h0)) node _T_1229 = or(_T_1221, _T_1222) node _T_1230 = or(_T_1229, _T_1223) node _T_1231 = or(_T_1230, _T_1224) node _T_1232 = or(_T_1231, _T_1225) node _T_1233 = or(_T_1232, _T_1226) node _T_1234 = or(_T_1233, _T_1227) node _T_1235 = or(_T_1234, _T_1228) wire _WIRE_70 : UInt<1> connect _WIRE_70, _T_1235 connect _WIRE_1.imm_rename, _WIRE_70 node _T_1236 = mux(_T_208, deq_vec[0][0].taken, UInt<1>(0h0)) node _T_1237 = mux(_T_209, deq_vec[1][0].taken, UInt<1>(0h0)) node _T_1238 = mux(_T_210, deq_vec[2][0].taken, UInt<1>(0h0)) node _T_1239 = mux(_T_211, deq_vec[3][0].taken, UInt<1>(0h0)) node _T_1240 = mux(_T_212, deq_vec[4][0].taken, UInt<1>(0h0)) node _T_1241 = mux(_T_213, deq_vec[5][0].taken, UInt<1>(0h0)) node _T_1242 = mux(_T_214, deq_vec[6][0].taken, UInt<1>(0h0)) node _T_1243 = mux(_T_215, deq_vec[7][0].taken, UInt<1>(0h0)) node _T_1244 = or(_T_1236, _T_1237) node _T_1245 = or(_T_1244, _T_1238) node _T_1246 = or(_T_1245, _T_1239) node _T_1247 = or(_T_1246, _T_1240) node _T_1248 = or(_T_1247, _T_1241) node _T_1249 = or(_T_1248, _T_1242) node _T_1250 = or(_T_1249, _T_1243) wire _WIRE_71 : UInt<1> connect _WIRE_71, _T_1250 connect _WIRE_1.taken, _WIRE_71 node _T_1251 = mux(_T_208, deq_vec[0][0].pc_lob, UInt<1>(0h0)) node _T_1252 = mux(_T_209, deq_vec[1][0].pc_lob, UInt<1>(0h0)) node _T_1253 = mux(_T_210, deq_vec[2][0].pc_lob, UInt<1>(0h0)) node _T_1254 = mux(_T_211, deq_vec[3][0].pc_lob, UInt<1>(0h0)) node _T_1255 = mux(_T_212, deq_vec[4][0].pc_lob, UInt<1>(0h0)) node _T_1256 = mux(_T_213, deq_vec[5][0].pc_lob, UInt<1>(0h0)) node _T_1257 = mux(_T_214, deq_vec[6][0].pc_lob, UInt<1>(0h0)) node _T_1258 = mux(_T_215, deq_vec[7][0].pc_lob, UInt<1>(0h0)) node _T_1259 = or(_T_1251, _T_1252) node _T_1260 = or(_T_1259, _T_1253) node _T_1261 = or(_T_1260, _T_1254) node _T_1262 = or(_T_1261, _T_1255) node _T_1263 = or(_T_1262, _T_1256) node _T_1264 = or(_T_1263, _T_1257) node _T_1265 = or(_T_1264, _T_1258) wire _WIRE_72 : UInt<6> connect _WIRE_72, _T_1265 connect _WIRE_1.pc_lob, _WIRE_72 node _T_1266 = mux(_T_208, deq_vec[0][0].edge_inst, UInt<1>(0h0)) node _T_1267 = mux(_T_209, deq_vec[1][0].edge_inst, UInt<1>(0h0)) node _T_1268 = mux(_T_210, deq_vec[2][0].edge_inst, UInt<1>(0h0)) node _T_1269 = mux(_T_211, deq_vec[3][0].edge_inst, UInt<1>(0h0)) node _T_1270 = mux(_T_212, deq_vec[4][0].edge_inst, UInt<1>(0h0)) node _T_1271 = mux(_T_213, deq_vec[5][0].edge_inst, UInt<1>(0h0)) node _T_1272 = mux(_T_214, deq_vec[6][0].edge_inst, UInt<1>(0h0)) node _T_1273 = mux(_T_215, deq_vec[7][0].edge_inst, UInt<1>(0h0)) node _T_1274 = or(_T_1266, _T_1267) node _T_1275 = or(_T_1274, _T_1268) node _T_1276 = or(_T_1275, _T_1269) node _T_1277 = or(_T_1276, _T_1270) node _T_1278 = or(_T_1277, _T_1271) node _T_1279 = or(_T_1278, _T_1272) node _T_1280 = or(_T_1279, _T_1273) wire _WIRE_73 : UInt<1> connect _WIRE_73, _T_1280 connect _WIRE_1.edge_inst, _WIRE_73 node _T_1281 = mux(_T_208, deq_vec[0][0].ftq_idx, UInt<1>(0h0)) node _T_1282 = mux(_T_209, deq_vec[1][0].ftq_idx, UInt<1>(0h0)) node _T_1283 = mux(_T_210, deq_vec[2][0].ftq_idx, UInt<1>(0h0)) node _T_1284 = mux(_T_211, deq_vec[3][0].ftq_idx, UInt<1>(0h0)) node _T_1285 = mux(_T_212, deq_vec[4][0].ftq_idx, UInt<1>(0h0)) node _T_1286 = mux(_T_213, deq_vec[5][0].ftq_idx, UInt<1>(0h0)) node _T_1287 = mux(_T_214, deq_vec[6][0].ftq_idx, UInt<1>(0h0)) node _T_1288 = mux(_T_215, deq_vec[7][0].ftq_idx, UInt<1>(0h0)) node _T_1289 = or(_T_1281, _T_1282) node _T_1290 = or(_T_1289, _T_1283) node _T_1291 = or(_T_1290, _T_1284) node _T_1292 = or(_T_1291, _T_1285) node _T_1293 = or(_T_1292, _T_1286) node _T_1294 = or(_T_1293, _T_1287) node _T_1295 = or(_T_1294, _T_1288) wire _WIRE_74 : UInt<5> connect _WIRE_74, _T_1295 connect _WIRE_1.ftq_idx, _WIRE_74 node _T_1296 = mux(_T_208, deq_vec[0][0].is_mov, UInt<1>(0h0)) node _T_1297 = mux(_T_209, deq_vec[1][0].is_mov, UInt<1>(0h0)) node _T_1298 = mux(_T_210, deq_vec[2][0].is_mov, UInt<1>(0h0)) node _T_1299 = mux(_T_211, deq_vec[3][0].is_mov, UInt<1>(0h0)) node _T_1300 = mux(_T_212, deq_vec[4][0].is_mov, UInt<1>(0h0)) node _T_1301 = mux(_T_213, deq_vec[5][0].is_mov, UInt<1>(0h0)) node _T_1302 = mux(_T_214, deq_vec[6][0].is_mov, UInt<1>(0h0)) node _T_1303 = mux(_T_215, deq_vec[7][0].is_mov, UInt<1>(0h0)) node _T_1304 = or(_T_1296, _T_1297) node _T_1305 = or(_T_1304, _T_1298) node _T_1306 = or(_T_1305, _T_1299) node _T_1307 = or(_T_1306, _T_1300) node _T_1308 = or(_T_1307, _T_1301) node _T_1309 = or(_T_1308, _T_1302) node _T_1310 = or(_T_1309, _T_1303) wire _WIRE_75 : UInt<1> connect _WIRE_75, _T_1310 connect _WIRE_1.is_mov, _WIRE_75 node _T_1311 = mux(_T_208, deq_vec[0][0].is_rocc, UInt<1>(0h0)) node _T_1312 = mux(_T_209, deq_vec[1][0].is_rocc, UInt<1>(0h0)) node _T_1313 = mux(_T_210, deq_vec[2][0].is_rocc, UInt<1>(0h0)) node _T_1314 = mux(_T_211, deq_vec[3][0].is_rocc, UInt<1>(0h0)) node _T_1315 = mux(_T_212, deq_vec[4][0].is_rocc, UInt<1>(0h0)) node _T_1316 = mux(_T_213, deq_vec[5][0].is_rocc, UInt<1>(0h0)) node _T_1317 = mux(_T_214, deq_vec[6][0].is_rocc, UInt<1>(0h0)) node _T_1318 = mux(_T_215, deq_vec[7][0].is_rocc, UInt<1>(0h0)) node _T_1319 = or(_T_1311, _T_1312) node _T_1320 = or(_T_1319, _T_1313) node _T_1321 = or(_T_1320, _T_1314) node _T_1322 = or(_T_1321, _T_1315) node _T_1323 = or(_T_1322, _T_1316) node _T_1324 = or(_T_1323, _T_1317) node _T_1325 = or(_T_1324, _T_1318) wire _WIRE_76 : UInt<1> connect _WIRE_76, _T_1325 connect _WIRE_1.is_rocc, _WIRE_76 node _T_1326 = mux(_T_208, deq_vec[0][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1327 = mux(_T_209, deq_vec[1][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1328 = mux(_T_210, deq_vec[2][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1329 = mux(_T_211, deq_vec[3][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1330 = mux(_T_212, deq_vec[4][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1331 = mux(_T_213, deq_vec[5][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1332 = mux(_T_214, deq_vec[6][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1333 = mux(_T_215, deq_vec[7][0].is_sys_pc2epc, UInt<1>(0h0)) node _T_1334 = or(_T_1326, _T_1327) node _T_1335 = or(_T_1334, _T_1328) node _T_1336 = or(_T_1335, _T_1329) node _T_1337 = or(_T_1336, _T_1330) node _T_1338 = or(_T_1337, _T_1331) node _T_1339 = or(_T_1338, _T_1332) node _T_1340 = or(_T_1339, _T_1333) wire _WIRE_77 : UInt<1> connect _WIRE_77, _T_1340 connect _WIRE_1.is_sys_pc2epc, _WIRE_77 node _T_1341 = mux(_T_208, deq_vec[0][0].is_eret, UInt<1>(0h0)) node _T_1342 = mux(_T_209, deq_vec[1][0].is_eret, UInt<1>(0h0)) node _T_1343 = mux(_T_210, deq_vec[2][0].is_eret, UInt<1>(0h0)) node _T_1344 = mux(_T_211, deq_vec[3][0].is_eret, UInt<1>(0h0)) node _T_1345 = mux(_T_212, deq_vec[4][0].is_eret, UInt<1>(0h0)) node _T_1346 = mux(_T_213, deq_vec[5][0].is_eret, UInt<1>(0h0)) node _T_1347 = mux(_T_214, deq_vec[6][0].is_eret, UInt<1>(0h0)) node _T_1348 = mux(_T_215, deq_vec[7][0].is_eret, UInt<1>(0h0)) node _T_1349 = or(_T_1341, _T_1342) node _T_1350 = or(_T_1349, _T_1343) node _T_1351 = or(_T_1350, _T_1344) node _T_1352 = or(_T_1351, _T_1345) node _T_1353 = or(_T_1352, _T_1346) node _T_1354 = or(_T_1353, _T_1347) node _T_1355 = or(_T_1354, _T_1348) wire _WIRE_78 : UInt<1> connect _WIRE_78, _T_1355 connect _WIRE_1.is_eret, _WIRE_78 node _T_1356 = mux(_T_208, deq_vec[0][0].is_amo, UInt<1>(0h0)) node _T_1357 = mux(_T_209, deq_vec[1][0].is_amo, UInt<1>(0h0)) node _T_1358 = mux(_T_210, deq_vec[2][0].is_amo, UInt<1>(0h0)) node _T_1359 = mux(_T_211, deq_vec[3][0].is_amo, UInt<1>(0h0)) node _T_1360 = mux(_T_212, deq_vec[4][0].is_amo, UInt<1>(0h0)) node _T_1361 = mux(_T_213, deq_vec[5][0].is_amo, UInt<1>(0h0)) node _T_1362 = mux(_T_214, deq_vec[6][0].is_amo, UInt<1>(0h0)) node _T_1363 = mux(_T_215, deq_vec[7][0].is_amo, UInt<1>(0h0)) node _T_1364 = or(_T_1356, _T_1357) node _T_1365 = or(_T_1364, _T_1358) node _T_1366 = or(_T_1365, _T_1359) node _T_1367 = or(_T_1366, _T_1360) node _T_1368 = or(_T_1367, _T_1361) node _T_1369 = or(_T_1368, _T_1362) node _T_1370 = or(_T_1369, _T_1363) wire _WIRE_79 : UInt<1> connect _WIRE_79, _T_1370 connect _WIRE_1.is_amo, _WIRE_79 node _T_1371 = mux(_T_208, deq_vec[0][0].is_sfence, UInt<1>(0h0)) node _T_1372 = mux(_T_209, deq_vec[1][0].is_sfence, UInt<1>(0h0)) node _T_1373 = mux(_T_210, deq_vec[2][0].is_sfence, UInt<1>(0h0)) node _T_1374 = mux(_T_211, deq_vec[3][0].is_sfence, UInt<1>(0h0)) node _T_1375 = mux(_T_212, deq_vec[4][0].is_sfence, UInt<1>(0h0)) node _T_1376 = mux(_T_213, deq_vec[5][0].is_sfence, UInt<1>(0h0)) node _T_1377 = mux(_T_214, deq_vec[6][0].is_sfence, UInt<1>(0h0)) node _T_1378 = mux(_T_215, deq_vec[7][0].is_sfence, UInt<1>(0h0)) node _T_1379 = or(_T_1371, _T_1372) node _T_1380 = or(_T_1379, _T_1373) node _T_1381 = or(_T_1380, _T_1374) node _T_1382 = or(_T_1381, _T_1375) node _T_1383 = or(_T_1382, _T_1376) node _T_1384 = or(_T_1383, _T_1377) node _T_1385 = or(_T_1384, _T_1378) wire _WIRE_80 : UInt<1> connect _WIRE_80, _T_1385 connect _WIRE_1.is_sfence, _WIRE_80 node _T_1386 = mux(_T_208, deq_vec[0][0].is_fencei, UInt<1>(0h0)) node _T_1387 = mux(_T_209, deq_vec[1][0].is_fencei, UInt<1>(0h0)) node _T_1388 = mux(_T_210, deq_vec[2][0].is_fencei, UInt<1>(0h0)) node _T_1389 = mux(_T_211, deq_vec[3][0].is_fencei, UInt<1>(0h0)) node _T_1390 = mux(_T_212, deq_vec[4][0].is_fencei, UInt<1>(0h0)) node _T_1391 = mux(_T_213, deq_vec[5][0].is_fencei, UInt<1>(0h0)) node _T_1392 = mux(_T_214, deq_vec[6][0].is_fencei, UInt<1>(0h0)) node _T_1393 = mux(_T_215, deq_vec[7][0].is_fencei, UInt<1>(0h0)) node _T_1394 = or(_T_1386, _T_1387) node _T_1395 = or(_T_1394, _T_1388) node _T_1396 = or(_T_1395, _T_1389) node _T_1397 = or(_T_1396, _T_1390) node _T_1398 = or(_T_1397, _T_1391) node _T_1399 = or(_T_1398, _T_1392) node _T_1400 = or(_T_1399, _T_1393) wire _WIRE_81 : UInt<1> connect _WIRE_81, _T_1400 connect _WIRE_1.is_fencei, _WIRE_81 node _T_1401 = mux(_T_208, deq_vec[0][0].is_fence, UInt<1>(0h0)) node _T_1402 = mux(_T_209, deq_vec[1][0].is_fence, UInt<1>(0h0)) node _T_1403 = mux(_T_210, deq_vec[2][0].is_fence, UInt<1>(0h0)) node _T_1404 = mux(_T_211, deq_vec[3][0].is_fence, UInt<1>(0h0)) node _T_1405 = mux(_T_212, deq_vec[4][0].is_fence, UInt<1>(0h0)) node _T_1406 = mux(_T_213, deq_vec[5][0].is_fence, UInt<1>(0h0)) node _T_1407 = mux(_T_214, deq_vec[6][0].is_fence, UInt<1>(0h0)) node _T_1408 = mux(_T_215, deq_vec[7][0].is_fence, UInt<1>(0h0)) node _T_1409 = or(_T_1401, _T_1402) node _T_1410 = or(_T_1409, _T_1403) node _T_1411 = or(_T_1410, _T_1404) node _T_1412 = or(_T_1411, _T_1405) node _T_1413 = or(_T_1412, _T_1406) node _T_1414 = or(_T_1413, _T_1407) node _T_1415 = or(_T_1414, _T_1408) wire _WIRE_82 : UInt<1> connect _WIRE_82, _T_1415 connect _WIRE_1.is_fence, _WIRE_82 node _T_1416 = mux(_T_208, deq_vec[0][0].is_sfb, UInt<1>(0h0)) node _T_1417 = mux(_T_209, deq_vec[1][0].is_sfb, UInt<1>(0h0)) node _T_1418 = mux(_T_210, deq_vec[2][0].is_sfb, UInt<1>(0h0)) node _T_1419 = mux(_T_211, deq_vec[3][0].is_sfb, UInt<1>(0h0)) node _T_1420 = mux(_T_212, deq_vec[4][0].is_sfb, UInt<1>(0h0)) node _T_1421 = mux(_T_213, deq_vec[5][0].is_sfb, UInt<1>(0h0)) node _T_1422 = mux(_T_214, deq_vec[6][0].is_sfb, UInt<1>(0h0)) node _T_1423 = mux(_T_215, deq_vec[7][0].is_sfb, UInt<1>(0h0)) node _T_1424 = or(_T_1416, _T_1417) node _T_1425 = or(_T_1424, _T_1418) node _T_1426 = or(_T_1425, _T_1419) node _T_1427 = or(_T_1426, _T_1420) node _T_1428 = or(_T_1427, _T_1421) node _T_1429 = or(_T_1428, _T_1422) node _T_1430 = or(_T_1429, _T_1423) wire _WIRE_83 : UInt<1> connect _WIRE_83, _T_1430 connect _WIRE_1.is_sfb, _WIRE_83 node _T_1431 = mux(_T_208, deq_vec[0][0].br_type, UInt<1>(0h0)) node _T_1432 = mux(_T_209, deq_vec[1][0].br_type, UInt<1>(0h0)) node _T_1433 = mux(_T_210, deq_vec[2][0].br_type, UInt<1>(0h0)) node _T_1434 = mux(_T_211, deq_vec[3][0].br_type, UInt<1>(0h0)) node _T_1435 = mux(_T_212, deq_vec[4][0].br_type, UInt<1>(0h0)) node _T_1436 = mux(_T_213, deq_vec[5][0].br_type, UInt<1>(0h0)) node _T_1437 = mux(_T_214, deq_vec[6][0].br_type, UInt<1>(0h0)) node _T_1438 = mux(_T_215, deq_vec[7][0].br_type, UInt<1>(0h0)) node _T_1439 = or(_T_1431, _T_1432) node _T_1440 = or(_T_1439, _T_1433) node _T_1441 = or(_T_1440, _T_1434) node _T_1442 = or(_T_1441, _T_1435) node _T_1443 = or(_T_1442, _T_1436) node _T_1444 = or(_T_1443, _T_1437) node _T_1445 = or(_T_1444, _T_1438) wire _WIRE_84 : UInt<4> connect _WIRE_84, _T_1445 connect _WIRE_1.br_type, _WIRE_84 node _T_1446 = mux(_T_208, deq_vec[0][0].br_tag, UInt<1>(0h0)) node _T_1447 = mux(_T_209, deq_vec[1][0].br_tag, UInt<1>(0h0)) node _T_1448 = mux(_T_210, deq_vec[2][0].br_tag, UInt<1>(0h0)) node _T_1449 = mux(_T_211, deq_vec[3][0].br_tag, UInt<1>(0h0)) node _T_1450 = mux(_T_212, deq_vec[4][0].br_tag, UInt<1>(0h0)) node _T_1451 = mux(_T_213, deq_vec[5][0].br_tag, UInt<1>(0h0)) node _T_1452 = mux(_T_214, deq_vec[6][0].br_tag, UInt<1>(0h0)) node _T_1453 = mux(_T_215, deq_vec[7][0].br_tag, UInt<1>(0h0)) node _T_1454 = or(_T_1446, _T_1447) node _T_1455 = or(_T_1454, _T_1448) node _T_1456 = or(_T_1455, _T_1449) node _T_1457 = or(_T_1456, _T_1450) node _T_1458 = or(_T_1457, _T_1451) node _T_1459 = or(_T_1458, _T_1452) node _T_1460 = or(_T_1459, _T_1453) wire _WIRE_85 : UInt<4> connect _WIRE_85, _T_1460 connect _WIRE_1.br_tag, _WIRE_85 node _T_1461 = mux(_T_208, deq_vec[0][0].br_mask, UInt<1>(0h0)) node _T_1462 = mux(_T_209, deq_vec[1][0].br_mask, UInt<1>(0h0)) node _T_1463 = mux(_T_210, deq_vec[2][0].br_mask, UInt<1>(0h0)) node _T_1464 = mux(_T_211, deq_vec[3][0].br_mask, UInt<1>(0h0)) node _T_1465 = mux(_T_212, deq_vec[4][0].br_mask, UInt<1>(0h0)) node _T_1466 = mux(_T_213, deq_vec[5][0].br_mask, UInt<1>(0h0)) node _T_1467 = mux(_T_214, deq_vec[6][0].br_mask, UInt<1>(0h0)) node _T_1468 = mux(_T_215, deq_vec[7][0].br_mask, UInt<1>(0h0)) node _T_1469 = or(_T_1461, _T_1462) node _T_1470 = or(_T_1469, _T_1463) node _T_1471 = or(_T_1470, _T_1464) node _T_1472 = or(_T_1471, _T_1465) node _T_1473 = or(_T_1472, _T_1466) node _T_1474 = or(_T_1473, _T_1467) node _T_1475 = or(_T_1474, _T_1468) wire _WIRE_86 : UInt<12> connect _WIRE_86, _T_1475 connect _WIRE_1.br_mask, _WIRE_86 node _T_1476 = mux(_T_208, deq_vec[0][0].dis_col_sel, UInt<1>(0h0)) node _T_1477 = mux(_T_209, deq_vec[1][0].dis_col_sel, UInt<1>(0h0)) node _T_1478 = mux(_T_210, deq_vec[2][0].dis_col_sel, UInt<1>(0h0)) node _T_1479 = mux(_T_211, deq_vec[3][0].dis_col_sel, UInt<1>(0h0)) node _T_1480 = mux(_T_212, deq_vec[4][0].dis_col_sel, UInt<1>(0h0)) node _T_1481 = mux(_T_213, deq_vec[5][0].dis_col_sel, UInt<1>(0h0)) node _T_1482 = mux(_T_214, deq_vec[6][0].dis_col_sel, UInt<1>(0h0)) node _T_1483 = mux(_T_215, deq_vec[7][0].dis_col_sel, UInt<1>(0h0)) node _T_1484 = or(_T_1476, _T_1477) node _T_1485 = or(_T_1484, _T_1478) node _T_1486 = or(_T_1485, _T_1479) node _T_1487 = or(_T_1486, _T_1480) node _T_1488 = or(_T_1487, _T_1481) node _T_1489 = or(_T_1488, _T_1482) node _T_1490 = or(_T_1489, _T_1483) wire _WIRE_87 : UInt<2> connect _WIRE_87, _T_1490 connect _WIRE_1.dis_col_sel, _WIRE_87 node _T_1491 = mux(_T_208, deq_vec[0][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1492 = mux(_T_209, deq_vec[1][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1493 = mux(_T_210, deq_vec[2][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1494 = mux(_T_211, deq_vec[3][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1495 = mux(_T_212, deq_vec[4][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1496 = mux(_T_213, deq_vec[5][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1497 = mux(_T_214, deq_vec[6][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1498 = mux(_T_215, deq_vec[7][0].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_1499 = or(_T_1491, _T_1492) node _T_1500 = or(_T_1499, _T_1493) node _T_1501 = or(_T_1500, _T_1494) node _T_1502 = or(_T_1501, _T_1495) node _T_1503 = or(_T_1502, _T_1496) node _T_1504 = or(_T_1503, _T_1497) node _T_1505 = or(_T_1504, _T_1498) wire _WIRE_88 : UInt<1> connect _WIRE_88, _T_1505 connect _WIRE_1.iw_p3_bypass_hint, _WIRE_88 node _T_1506 = mux(_T_208, deq_vec[0][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1507 = mux(_T_209, deq_vec[1][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1508 = mux(_T_210, deq_vec[2][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1509 = mux(_T_211, deq_vec[3][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1510 = mux(_T_212, deq_vec[4][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1511 = mux(_T_213, deq_vec[5][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1512 = mux(_T_214, deq_vec[6][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1513 = mux(_T_215, deq_vec[7][0].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_1514 = or(_T_1506, _T_1507) node _T_1515 = or(_T_1514, _T_1508) node _T_1516 = or(_T_1515, _T_1509) node _T_1517 = or(_T_1516, _T_1510) node _T_1518 = or(_T_1517, _T_1511) node _T_1519 = or(_T_1518, _T_1512) node _T_1520 = or(_T_1519, _T_1513) wire _WIRE_89 : UInt<1> connect _WIRE_89, _T_1520 connect _WIRE_1.iw_p2_bypass_hint, _WIRE_89 node _T_1521 = mux(_T_208, deq_vec[0][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1522 = mux(_T_209, deq_vec[1][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1523 = mux(_T_210, deq_vec[2][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1524 = mux(_T_211, deq_vec[3][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1525 = mux(_T_212, deq_vec[4][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1526 = mux(_T_213, deq_vec[5][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1527 = mux(_T_214, deq_vec[6][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1528 = mux(_T_215, deq_vec[7][0].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_1529 = or(_T_1521, _T_1522) node _T_1530 = or(_T_1529, _T_1523) node _T_1531 = or(_T_1530, _T_1524) node _T_1532 = or(_T_1531, _T_1525) node _T_1533 = or(_T_1532, _T_1526) node _T_1534 = or(_T_1533, _T_1527) node _T_1535 = or(_T_1534, _T_1528) wire _WIRE_90 : UInt<1> connect _WIRE_90, _T_1535 connect _WIRE_1.iw_p1_bypass_hint, _WIRE_90 node _T_1536 = mux(_T_208, deq_vec[0][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1537 = mux(_T_209, deq_vec[1][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1538 = mux(_T_210, deq_vec[2][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1539 = mux(_T_211, deq_vec[3][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1540 = mux(_T_212, deq_vec[4][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1541 = mux(_T_213, deq_vec[5][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1542 = mux(_T_214, deq_vec[6][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1543 = mux(_T_215, deq_vec[7][0].iw_p2_speculative_child, UInt<1>(0h0)) node _T_1544 = or(_T_1536, _T_1537) node _T_1545 = or(_T_1544, _T_1538) node _T_1546 = or(_T_1545, _T_1539) node _T_1547 = or(_T_1546, _T_1540) node _T_1548 = or(_T_1547, _T_1541) node _T_1549 = or(_T_1548, _T_1542) node _T_1550 = or(_T_1549, _T_1543) wire _WIRE_91 : UInt<2> connect _WIRE_91, _T_1550 connect _WIRE_1.iw_p2_speculative_child, _WIRE_91 node _T_1551 = mux(_T_208, deq_vec[0][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1552 = mux(_T_209, deq_vec[1][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1553 = mux(_T_210, deq_vec[2][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1554 = mux(_T_211, deq_vec[3][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1555 = mux(_T_212, deq_vec[4][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1556 = mux(_T_213, deq_vec[5][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1557 = mux(_T_214, deq_vec[6][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1558 = mux(_T_215, deq_vec[7][0].iw_p1_speculative_child, UInt<1>(0h0)) node _T_1559 = or(_T_1551, _T_1552) node _T_1560 = or(_T_1559, _T_1553) node _T_1561 = or(_T_1560, _T_1554) node _T_1562 = or(_T_1561, _T_1555) node _T_1563 = or(_T_1562, _T_1556) node _T_1564 = or(_T_1563, _T_1557) node _T_1565 = or(_T_1564, _T_1558) wire _WIRE_92 : UInt<2> connect _WIRE_92, _T_1565 connect _WIRE_1.iw_p1_speculative_child, _WIRE_92 node _T_1566 = mux(_T_208, deq_vec[0][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1567 = mux(_T_209, deq_vec[1][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1568 = mux(_T_210, deq_vec[2][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1569 = mux(_T_211, deq_vec[3][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1570 = mux(_T_212, deq_vec[4][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1571 = mux(_T_213, deq_vec[5][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1572 = mux(_T_214, deq_vec[6][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1573 = mux(_T_215, deq_vec[7][0].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_1574 = or(_T_1566, _T_1567) node _T_1575 = or(_T_1574, _T_1568) node _T_1576 = or(_T_1575, _T_1569) node _T_1577 = or(_T_1576, _T_1570) node _T_1578 = or(_T_1577, _T_1571) node _T_1579 = or(_T_1578, _T_1572) node _T_1580 = or(_T_1579, _T_1573) wire _WIRE_93 : UInt<1> connect _WIRE_93, _T_1580 connect _WIRE_1.iw_issued_partial_dgen, _WIRE_93 node _T_1581 = mux(_T_208, deq_vec[0][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1582 = mux(_T_209, deq_vec[1][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1583 = mux(_T_210, deq_vec[2][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1584 = mux(_T_211, deq_vec[3][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1585 = mux(_T_212, deq_vec[4][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1586 = mux(_T_213, deq_vec[5][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1587 = mux(_T_214, deq_vec[6][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1588 = mux(_T_215, deq_vec[7][0].iw_issued_partial_agen, UInt<1>(0h0)) node _T_1589 = or(_T_1581, _T_1582) node _T_1590 = or(_T_1589, _T_1583) node _T_1591 = or(_T_1590, _T_1584) node _T_1592 = or(_T_1591, _T_1585) node _T_1593 = or(_T_1592, _T_1586) node _T_1594 = or(_T_1593, _T_1587) node _T_1595 = or(_T_1594, _T_1588) wire _WIRE_94 : UInt<1> connect _WIRE_94, _T_1595 connect _WIRE_1.iw_issued_partial_agen, _WIRE_94 node _T_1596 = mux(_T_208, deq_vec[0][0].iw_issued, UInt<1>(0h0)) node _T_1597 = mux(_T_209, deq_vec[1][0].iw_issued, UInt<1>(0h0)) node _T_1598 = mux(_T_210, deq_vec[2][0].iw_issued, UInt<1>(0h0)) node _T_1599 = mux(_T_211, deq_vec[3][0].iw_issued, UInt<1>(0h0)) node _T_1600 = mux(_T_212, deq_vec[4][0].iw_issued, UInt<1>(0h0)) node _T_1601 = mux(_T_213, deq_vec[5][0].iw_issued, UInt<1>(0h0)) node _T_1602 = mux(_T_214, deq_vec[6][0].iw_issued, UInt<1>(0h0)) node _T_1603 = mux(_T_215, deq_vec[7][0].iw_issued, UInt<1>(0h0)) node _T_1604 = or(_T_1596, _T_1597) node _T_1605 = or(_T_1604, _T_1598) node _T_1606 = or(_T_1605, _T_1599) node _T_1607 = or(_T_1606, _T_1600) node _T_1608 = or(_T_1607, _T_1601) node _T_1609 = or(_T_1608, _T_1602) node _T_1610 = or(_T_1609, _T_1603) wire _WIRE_95 : UInt<1> connect _WIRE_95, _T_1610 connect _WIRE_1.iw_issued, _WIRE_95 wire _WIRE_96 : UInt<1>[10] node _T_1611 = mux(_T_208, deq_vec[0][0].fu_code[0], UInt<1>(0h0)) node _T_1612 = mux(_T_209, deq_vec[1][0].fu_code[0], UInt<1>(0h0)) node _T_1613 = mux(_T_210, deq_vec[2][0].fu_code[0], UInt<1>(0h0)) node _T_1614 = mux(_T_211, deq_vec[3][0].fu_code[0], UInt<1>(0h0)) node _T_1615 = mux(_T_212, deq_vec[4][0].fu_code[0], UInt<1>(0h0)) node _T_1616 = mux(_T_213, deq_vec[5][0].fu_code[0], UInt<1>(0h0)) node _T_1617 = mux(_T_214, deq_vec[6][0].fu_code[0], UInt<1>(0h0)) node _T_1618 = mux(_T_215, deq_vec[7][0].fu_code[0], UInt<1>(0h0)) node _T_1619 = or(_T_1611, _T_1612) node _T_1620 = or(_T_1619, _T_1613) node _T_1621 = or(_T_1620, _T_1614) node _T_1622 = or(_T_1621, _T_1615) node _T_1623 = or(_T_1622, _T_1616) node _T_1624 = or(_T_1623, _T_1617) node _T_1625 = or(_T_1624, _T_1618) wire _WIRE_97 : UInt<1> connect _WIRE_97, _T_1625 connect _WIRE_96[0], _WIRE_97 node _T_1626 = mux(_T_208, deq_vec[0][0].fu_code[1], UInt<1>(0h0)) node _T_1627 = mux(_T_209, deq_vec[1][0].fu_code[1], UInt<1>(0h0)) node _T_1628 = mux(_T_210, deq_vec[2][0].fu_code[1], UInt<1>(0h0)) node _T_1629 = mux(_T_211, deq_vec[3][0].fu_code[1], UInt<1>(0h0)) node _T_1630 = mux(_T_212, deq_vec[4][0].fu_code[1], UInt<1>(0h0)) node _T_1631 = mux(_T_213, deq_vec[5][0].fu_code[1], UInt<1>(0h0)) node _T_1632 = mux(_T_214, deq_vec[6][0].fu_code[1], UInt<1>(0h0)) node _T_1633 = mux(_T_215, deq_vec[7][0].fu_code[1], UInt<1>(0h0)) node _T_1634 = or(_T_1626, _T_1627) node _T_1635 = or(_T_1634, _T_1628) node _T_1636 = or(_T_1635, _T_1629) node _T_1637 = or(_T_1636, _T_1630) node _T_1638 = or(_T_1637, _T_1631) node _T_1639 = or(_T_1638, _T_1632) node _T_1640 = or(_T_1639, _T_1633) wire _WIRE_98 : UInt<1> connect _WIRE_98, _T_1640 connect _WIRE_96[1], _WIRE_98 node _T_1641 = mux(_T_208, deq_vec[0][0].fu_code[2], UInt<1>(0h0)) node _T_1642 = mux(_T_209, deq_vec[1][0].fu_code[2], UInt<1>(0h0)) node _T_1643 = mux(_T_210, deq_vec[2][0].fu_code[2], UInt<1>(0h0)) node _T_1644 = mux(_T_211, deq_vec[3][0].fu_code[2], UInt<1>(0h0)) node _T_1645 = mux(_T_212, deq_vec[4][0].fu_code[2], UInt<1>(0h0)) node _T_1646 = mux(_T_213, deq_vec[5][0].fu_code[2], UInt<1>(0h0)) node _T_1647 = mux(_T_214, deq_vec[6][0].fu_code[2], UInt<1>(0h0)) node _T_1648 = mux(_T_215, deq_vec[7][0].fu_code[2], UInt<1>(0h0)) node _T_1649 = or(_T_1641, _T_1642) node _T_1650 = or(_T_1649, _T_1643) node _T_1651 = or(_T_1650, _T_1644) node _T_1652 = or(_T_1651, _T_1645) node _T_1653 = or(_T_1652, _T_1646) node _T_1654 = or(_T_1653, _T_1647) node _T_1655 = or(_T_1654, _T_1648) wire _WIRE_99 : UInt<1> connect _WIRE_99, _T_1655 connect _WIRE_96[2], _WIRE_99 node _T_1656 = mux(_T_208, deq_vec[0][0].fu_code[3], UInt<1>(0h0)) node _T_1657 = mux(_T_209, deq_vec[1][0].fu_code[3], UInt<1>(0h0)) node _T_1658 = mux(_T_210, deq_vec[2][0].fu_code[3], UInt<1>(0h0)) node _T_1659 = mux(_T_211, deq_vec[3][0].fu_code[3], UInt<1>(0h0)) node _T_1660 = mux(_T_212, deq_vec[4][0].fu_code[3], UInt<1>(0h0)) node _T_1661 = mux(_T_213, deq_vec[5][0].fu_code[3], UInt<1>(0h0)) node _T_1662 = mux(_T_214, deq_vec[6][0].fu_code[3], UInt<1>(0h0)) node _T_1663 = mux(_T_215, deq_vec[7][0].fu_code[3], UInt<1>(0h0)) node _T_1664 = or(_T_1656, _T_1657) node _T_1665 = or(_T_1664, _T_1658) node _T_1666 = or(_T_1665, _T_1659) node _T_1667 = or(_T_1666, _T_1660) node _T_1668 = or(_T_1667, _T_1661) node _T_1669 = or(_T_1668, _T_1662) node _T_1670 = or(_T_1669, _T_1663) wire _WIRE_100 : UInt<1> connect _WIRE_100, _T_1670 connect _WIRE_96[3], _WIRE_100 node _T_1671 = mux(_T_208, deq_vec[0][0].fu_code[4], UInt<1>(0h0)) node _T_1672 = mux(_T_209, deq_vec[1][0].fu_code[4], UInt<1>(0h0)) node _T_1673 = mux(_T_210, deq_vec[2][0].fu_code[4], UInt<1>(0h0)) node _T_1674 = mux(_T_211, deq_vec[3][0].fu_code[4], UInt<1>(0h0)) node _T_1675 = mux(_T_212, deq_vec[4][0].fu_code[4], UInt<1>(0h0)) node _T_1676 = mux(_T_213, deq_vec[5][0].fu_code[4], UInt<1>(0h0)) node _T_1677 = mux(_T_214, deq_vec[6][0].fu_code[4], UInt<1>(0h0)) node _T_1678 = mux(_T_215, deq_vec[7][0].fu_code[4], UInt<1>(0h0)) node _T_1679 = or(_T_1671, _T_1672) node _T_1680 = or(_T_1679, _T_1673) node _T_1681 = or(_T_1680, _T_1674) node _T_1682 = or(_T_1681, _T_1675) node _T_1683 = or(_T_1682, _T_1676) node _T_1684 = or(_T_1683, _T_1677) node _T_1685 = or(_T_1684, _T_1678) wire _WIRE_101 : UInt<1> connect _WIRE_101, _T_1685 connect _WIRE_96[4], _WIRE_101 node _T_1686 = mux(_T_208, deq_vec[0][0].fu_code[5], UInt<1>(0h0)) node _T_1687 = mux(_T_209, deq_vec[1][0].fu_code[5], UInt<1>(0h0)) node _T_1688 = mux(_T_210, deq_vec[2][0].fu_code[5], UInt<1>(0h0)) node _T_1689 = mux(_T_211, deq_vec[3][0].fu_code[5], UInt<1>(0h0)) node _T_1690 = mux(_T_212, deq_vec[4][0].fu_code[5], UInt<1>(0h0)) node _T_1691 = mux(_T_213, deq_vec[5][0].fu_code[5], UInt<1>(0h0)) node _T_1692 = mux(_T_214, deq_vec[6][0].fu_code[5], UInt<1>(0h0)) node _T_1693 = mux(_T_215, deq_vec[7][0].fu_code[5], UInt<1>(0h0)) node _T_1694 = or(_T_1686, _T_1687) node _T_1695 = or(_T_1694, _T_1688) node _T_1696 = or(_T_1695, _T_1689) node _T_1697 = or(_T_1696, _T_1690) node _T_1698 = or(_T_1697, _T_1691) node _T_1699 = or(_T_1698, _T_1692) node _T_1700 = or(_T_1699, _T_1693) wire _WIRE_102 : UInt<1> connect _WIRE_102, _T_1700 connect _WIRE_96[5], _WIRE_102 node _T_1701 = mux(_T_208, deq_vec[0][0].fu_code[6], UInt<1>(0h0)) node _T_1702 = mux(_T_209, deq_vec[1][0].fu_code[6], UInt<1>(0h0)) node _T_1703 = mux(_T_210, deq_vec[2][0].fu_code[6], UInt<1>(0h0)) node _T_1704 = mux(_T_211, deq_vec[3][0].fu_code[6], UInt<1>(0h0)) node _T_1705 = mux(_T_212, deq_vec[4][0].fu_code[6], UInt<1>(0h0)) node _T_1706 = mux(_T_213, deq_vec[5][0].fu_code[6], UInt<1>(0h0)) node _T_1707 = mux(_T_214, deq_vec[6][0].fu_code[6], UInt<1>(0h0)) node _T_1708 = mux(_T_215, deq_vec[7][0].fu_code[6], UInt<1>(0h0)) node _T_1709 = or(_T_1701, _T_1702) node _T_1710 = or(_T_1709, _T_1703) node _T_1711 = or(_T_1710, _T_1704) node _T_1712 = or(_T_1711, _T_1705) node _T_1713 = or(_T_1712, _T_1706) node _T_1714 = or(_T_1713, _T_1707) node _T_1715 = or(_T_1714, _T_1708) wire _WIRE_103 : UInt<1> connect _WIRE_103, _T_1715 connect _WIRE_96[6], _WIRE_103 node _T_1716 = mux(_T_208, deq_vec[0][0].fu_code[7], UInt<1>(0h0)) node _T_1717 = mux(_T_209, deq_vec[1][0].fu_code[7], UInt<1>(0h0)) node _T_1718 = mux(_T_210, deq_vec[2][0].fu_code[7], UInt<1>(0h0)) node _T_1719 = mux(_T_211, deq_vec[3][0].fu_code[7], UInt<1>(0h0)) node _T_1720 = mux(_T_212, deq_vec[4][0].fu_code[7], UInt<1>(0h0)) node _T_1721 = mux(_T_213, deq_vec[5][0].fu_code[7], UInt<1>(0h0)) node _T_1722 = mux(_T_214, deq_vec[6][0].fu_code[7], UInt<1>(0h0)) node _T_1723 = mux(_T_215, deq_vec[7][0].fu_code[7], UInt<1>(0h0)) node _T_1724 = or(_T_1716, _T_1717) node _T_1725 = or(_T_1724, _T_1718) node _T_1726 = or(_T_1725, _T_1719) node _T_1727 = or(_T_1726, _T_1720) node _T_1728 = or(_T_1727, _T_1721) node _T_1729 = or(_T_1728, _T_1722) node _T_1730 = or(_T_1729, _T_1723) wire _WIRE_104 : UInt<1> connect _WIRE_104, _T_1730 connect _WIRE_96[7], _WIRE_104 node _T_1731 = mux(_T_208, deq_vec[0][0].fu_code[8], UInt<1>(0h0)) node _T_1732 = mux(_T_209, deq_vec[1][0].fu_code[8], UInt<1>(0h0)) node _T_1733 = mux(_T_210, deq_vec[2][0].fu_code[8], UInt<1>(0h0)) node _T_1734 = mux(_T_211, deq_vec[3][0].fu_code[8], UInt<1>(0h0)) node _T_1735 = mux(_T_212, deq_vec[4][0].fu_code[8], UInt<1>(0h0)) node _T_1736 = mux(_T_213, deq_vec[5][0].fu_code[8], UInt<1>(0h0)) node _T_1737 = mux(_T_214, deq_vec[6][0].fu_code[8], UInt<1>(0h0)) node _T_1738 = mux(_T_215, deq_vec[7][0].fu_code[8], UInt<1>(0h0)) node _T_1739 = or(_T_1731, _T_1732) node _T_1740 = or(_T_1739, _T_1733) node _T_1741 = or(_T_1740, _T_1734) node _T_1742 = or(_T_1741, _T_1735) node _T_1743 = or(_T_1742, _T_1736) node _T_1744 = or(_T_1743, _T_1737) node _T_1745 = or(_T_1744, _T_1738) wire _WIRE_105 : UInt<1> connect _WIRE_105, _T_1745 connect _WIRE_96[8], _WIRE_105 node _T_1746 = mux(_T_208, deq_vec[0][0].fu_code[9], UInt<1>(0h0)) node _T_1747 = mux(_T_209, deq_vec[1][0].fu_code[9], UInt<1>(0h0)) node _T_1748 = mux(_T_210, deq_vec[2][0].fu_code[9], UInt<1>(0h0)) node _T_1749 = mux(_T_211, deq_vec[3][0].fu_code[9], UInt<1>(0h0)) node _T_1750 = mux(_T_212, deq_vec[4][0].fu_code[9], UInt<1>(0h0)) node _T_1751 = mux(_T_213, deq_vec[5][0].fu_code[9], UInt<1>(0h0)) node _T_1752 = mux(_T_214, deq_vec[6][0].fu_code[9], UInt<1>(0h0)) node _T_1753 = mux(_T_215, deq_vec[7][0].fu_code[9], UInt<1>(0h0)) node _T_1754 = or(_T_1746, _T_1747) node _T_1755 = or(_T_1754, _T_1748) node _T_1756 = or(_T_1755, _T_1749) node _T_1757 = or(_T_1756, _T_1750) node _T_1758 = or(_T_1757, _T_1751) node _T_1759 = or(_T_1758, _T_1752) node _T_1760 = or(_T_1759, _T_1753) wire _WIRE_106 : UInt<1> connect _WIRE_106, _T_1760 connect _WIRE_96[9], _WIRE_106 connect _WIRE_1.fu_code, _WIRE_96 wire _WIRE_107 : UInt<1>[4] node _T_1761 = mux(_T_208, deq_vec[0][0].iq_type[0], UInt<1>(0h0)) node _T_1762 = mux(_T_209, deq_vec[1][0].iq_type[0], UInt<1>(0h0)) node _T_1763 = mux(_T_210, deq_vec[2][0].iq_type[0], UInt<1>(0h0)) node _T_1764 = mux(_T_211, deq_vec[3][0].iq_type[0], UInt<1>(0h0)) node _T_1765 = mux(_T_212, deq_vec[4][0].iq_type[0], UInt<1>(0h0)) node _T_1766 = mux(_T_213, deq_vec[5][0].iq_type[0], UInt<1>(0h0)) node _T_1767 = mux(_T_214, deq_vec[6][0].iq_type[0], UInt<1>(0h0)) node _T_1768 = mux(_T_215, deq_vec[7][0].iq_type[0], UInt<1>(0h0)) node _T_1769 = or(_T_1761, _T_1762) node _T_1770 = or(_T_1769, _T_1763) node _T_1771 = or(_T_1770, _T_1764) node _T_1772 = or(_T_1771, _T_1765) node _T_1773 = or(_T_1772, _T_1766) node _T_1774 = or(_T_1773, _T_1767) node _T_1775 = or(_T_1774, _T_1768) wire _WIRE_108 : UInt<1> connect _WIRE_108, _T_1775 connect _WIRE_107[0], _WIRE_108 node _T_1776 = mux(_T_208, deq_vec[0][0].iq_type[1], UInt<1>(0h0)) node _T_1777 = mux(_T_209, deq_vec[1][0].iq_type[1], UInt<1>(0h0)) node _T_1778 = mux(_T_210, deq_vec[2][0].iq_type[1], UInt<1>(0h0)) node _T_1779 = mux(_T_211, deq_vec[3][0].iq_type[1], UInt<1>(0h0)) node _T_1780 = mux(_T_212, deq_vec[4][0].iq_type[1], UInt<1>(0h0)) node _T_1781 = mux(_T_213, deq_vec[5][0].iq_type[1], UInt<1>(0h0)) node _T_1782 = mux(_T_214, deq_vec[6][0].iq_type[1], UInt<1>(0h0)) node _T_1783 = mux(_T_215, deq_vec[7][0].iq_type[1], UInt<1>(0h0)) node _T_1784 = or(_T_1776, _T_1777) node _T_1785 = or(_T_1784, _T_1778) node _T_1786 = or(_T_1785, _T_1779) node _T_1787 = or(_T_1786, _T_1780) node _T_1788 = or(_T_1787, _T_1781) node _T_1789 = or(_T_1788, _T_1782) node _T_1790 = or(_T_1789, _T_1783) wire _WIRE_109 : UInt<1> connect _WIRE_109, _T_1790 connect _WIRE_107[1], _WIRE_109 node _T_1791 = mux(_T_208, deq_vec[0][0].iq_type[2], UInt<1>(0h0)) node _T_1792 = mux(_T_209, deq_vec[1][0].iq_type[2], UInt<1>(0h0)) node _T_1793 = mux(_T_210, deq_vec[2][0].iq_type[2], UInt<1>(0h0)) node _T_1794 = mux(_T_211, deq_vec[3][0].iq_type[2], UInt<1>(0h0)) node _T_1795 = mux(_T_212, deq_vec[4][0].iq_type[2], UInt<1>(0h0)) node _T_1796 = mux(_T_213, deq_vec[5][0].iq_type[2], UInt<1>(0h0)) node _T_1797 = mux(_T_214, deq_vec[6][0].iq_type[2], UInt<1>(0h0)) node _T_1798 = mux(_T_215, deq_vec[7][0].iq_type[2], UInt<1>(0h0)) node _T_1799 = or(_T_1791, _T_1792) node _T_1800 = or(_T_1799, _T_1793) node _T_1801 = or(_T_1800, _T_1794) node _T_1802 = or(_T_1801, _T_1795) node _T_1803 = or(_T_1802, _T_1796) node _T_1804 = or(_T_1803, _T_1797) node _T_1805 = or(_T_1804, _T_1798) wire _WIRE_110 : UInt<1> connect _WIRE_110, _T_1805 connect _WIRE_107[2], _WIRE_110 node _T_1806 = mux(_T_208, deq_vec[0][0].iq_type[3], UInt<1>(0h0)) node _T_1807 = mux(_T_209, deq_vec[1][0].iq_type[3], UInt<1>(0h0)) node _T_1808 = mux(_T_210, deq_vec[2][0].iq_type[3], UInt<1>(0h0)) node _T_1809 = mux(_T_211, deq_vec[3][0].iq_type[3], UInt<1>(0h0)) node _T_1810 = mux(_T_212, deq_vec[4][0].iq_type[3], UInt<1>(0h0)) node _T_1811 = mux(_T_213, deq_vec[5][0].iq_type[3], UInt<1>(0h0)) node _T_1812 = mux(_T_214, deq_vec[6][0].iq_type[3], UInt<1>(0h0)) node _T_1813 = mux(_T_215, deq_vec[7][0].iq_type[3], UInt<1>(0h0)) node _T_1814 = or(_T_1806, _T_1807) node _T_1815 = or(_T_1814, _T_1808) node _T_1816 = or(_T_1815, _T_1809) node _T_1817 = or(_T_1816, _T_1810) node _T_1818 = or(_T_1817, _T_1811) node _T_1819 = or(_T_1818, _T_1812) node _T_1820 = or(_T_1819, _T_1813) wire _WIRE_111 : UInt<1> connect _WIRE_111, _T_1820 connect _WIRE_107[3], _WIRE_111 connect _WIRE_1.iq_type, _WIRE_107 node _T_1821 = mux(_T_208, deq_vec[0][0].debug_pc, UInt<1>(0h0)) node _T_1822 = mux(_T_209, deq_vec[1][0].debug_pc, UInt<1>(0h0)) node _T_1823 = mux(_T_210, deq_vec[2][0].debug_pc, UInt<1>(0h0)) node _T_1824 = mux(_T_211, deq_vec[3][0].debug_pc, UInt<1>(0h0)) node _T_1825 = mux(_T_212, deq_vec[4][0].debug_pc, UInt<1>(0h0)) node _T_1826 = mux(_T_213, deq_vec[5][0].debug_pc, UInt<1>(0h0)) node _T_1827 = mux(_T_214, deq_vec[6][0].debug_pc, UInt<1>(0h0)) node _T_1828 = mux(_T_215, deq_vec[7][0].debug_pc, UInt<1>(0h0)) node _T_1829 = or(_T_1821, _T_1822) node _T_1830 = or(_T_1829, _T_1823) node _T_1831 = or(_T_1830, _T_1824) node _T_1832 = or(_T_1831, _T_1825) node _T_1833 = or(_T_1832, _T_1826) node _T_1834 = or(_T_1833, _T_1827) node _T_1835 = or(_T_1834, _T_1828) wire _WIRE_112 : UInt<40> connect _WIRE_112, _T_1835 connect _WIRE_1.debug_pc, _WIRE_112 node _T_1836 = mux(_T_208, deq_vec[0][0].is_rvc, UInt<1>(0h0)) node _T_1837 = mux(_T_209, deq_vec[1][0].is_rvc, UInt<1>(0h0)) node _T_1838 = mux(_T_210, deq_vec[2][0].is_rvc, UInt<1>(0h0)) node _T_1839 = mux(_T_211, deq_vec[3][0].is_rvc, UInt<1>(0h0)) node _T_1840 = mux(_T_212, deq_vec[4][0].is_rvc, UInt<1>(0h0)) node _T_1841 = mux(_T_213, deq_vec[5][0].is_rvc, UInt<1>(0h0)) node _T_1842 = mux(_T_214, deq_vec[6][0].is_rvc, UInt<1>(0h0)) node _T_1843 = mux(_T_215, deq_vec[7][0].is_rvc, UInt<1>(0h0)) node _T_1844 = or(_T_1836, _T_1837) node _T_1845 = or(_T_1844, _T_1838) node _T_1846 = or(_T_1845, _T_1839) node _T_1847 = or(_T_1846, _T_1840) node _T_1848 = or(_T_1847, _T_1841) node _T_1849 = or(_T_1848, _T_1842) node _T_1850 = or(_T_1849, _T_1843) wire _WIRE_113 : UInt<1> connect _WIRE_113, _T_1850 connect _WIRE_1.is_rvc, _WIRE_113 node _T_1851 = mux(_T_208, deq_vec[0][0].debug_inst, UInt<1>(0h0)) node _T_1852 = mux(_T_209, deq_vec[1][0].debug_inst, UInt<1>(0h0)) node _T_1853 = mux(_T_210, deq_vec[2][0].debug_inst, UInt<1>(0h0)) node _T_1854 = mux(_T_211, deq_vec[3][0].debug_inst, UInt<1>(0h0)) node _T_1855 = mux(_T_212, deq_vec[4][0].debug_inst, UInt<1>(0h0)) node _T_1856 = mux(_T_213, deq_vec[5][0].debug_inst, UInt<1>(0h0)) node _T_1857 = mux(_T_214, deq_vec[6][0].debug_inst, UInt<1>(0h0)) node _T_1858 = mux(_T_215, deq_vec[7][0].debug_inst, UInt<1>(0h0)) node _T_1859 = or(_T_1851, _T_1852) node _T_1860 = or(_T_1859, _T_1853) node _T_1861 = or(_T_1860, _T_1854) node _T_1862 = or(_T_1861, _T_1855) node _T_1863 = or(_T_1862, _T_1856) node _T_1864 = or(_T_1863, _T_1857) node _T_1865 = or(_T_1864, _T_1858) wire _WIRE_114 : UInt<32> connect _WIRE_114, _T_1865 connect _WIRE_1.debug_inst, _WIRE_114 node _T_1866 = mux(_T_208, deq_vec[0][0].inst, UInt<1>(0h0)) node _T_1867 = mux(_T_209, deq_vec[1][0].inst, UInt<1>(0h0)) node _T_1868 = mux(_T_210, deq_vec[2][0].inst, UInt<1>(0h0)) node _T_1869 = mux(_T_211, deq_vec[3][0].inst, UInt<1>(0h0)) node _T_1870 = mux(_T_212, deq_vec[4][0].inst, UInt<1>(0h0)) node _T_1871 = mux(_T_213, deq_vec[5][0].inst, UInt<1>(0h0)) node _T_1872 = mux(_T_214, deq_vec[6][0].inst, UInt<1>(0h0)) node _T_1873 = mux(_T_215, deq_vec[7][0].inst, UInt<1>(0h0)) node _T_1874 = or(_T_1866, _T_1867) node _T_1875 = or(_T_1874, _T_1868) node _T_1876 = or(_T_1875, _T_1869) node _T_1877 = or(_T_1876, _T_1870) node _T_1878 = or(_T_1877, _T_1871) node _T_1879 = or(_T_1878, _T_1872) node _T_1880 = or(_T_1879, _T_1873) wire _WIRE_115 : UInt<32> connect _WIRE_115, _T_1880 connect _WIRE_1.inst, _WIRE_115 connect _WIRE[0], _WIRE_1 wire _WIRE_116 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} node _T_1881 = mux(_T_208, deq_vec[0][1].debug_tsrc, UInt<1>(0h0)) node _T_1882 = mux(_T_209, deq_vec[1][1].debug_tsrc, UInt<1>(0h0)) node _T_1883 = mux(_T_210, deq_vec[2][1].debug_tsrc, UInt<1>(0h0)) node _T_1884 = mux(_T_211, deq_vec[3][1].debug_tsrc, UInt<1>(0h0)) node _T_1885 = mux(_T_212, deq_vec[4][1].debug_tsrc, UInt<1>(0h0)) node _T_1886 = mux(_T_213, deq_vec[5][1].debug_tsrc, UInt<1>(0h0)) node _T_1887 = mux(_T_214, deq_vec[6][1].debug_tsrc, UInt<1>(0h0)) node _T_1888 = mux(_T_215, deq_vec[7][1].debug_tsrc, UInt<1>(0h0)) node _T_1889 = or(_T_1881, _T_1882) node _T_1890 = or(_T_1889, _T_1883) node _T_1891 = or(_T_1890, _T_1884) node _T_1892 = or(_T_1891, _T_1885) node _T_1893 = or(_T_1892, _T_1886) node _T_1894 = or(_T_1893, _T_1887) node _T_1895 = or(_T_1894, _T_1888) wire _WIRE_117 : UInt<3> connect _WIRE_117, _T_1895 connect _WIRE_116.debug_tsrc, _WIRE_117 node _T_1896 = mux(_T_208, deq_vec[0][1].debug_fsrc, UInt<1>(0h0)) node _T_1897 = mux(_T_209, deq_vec[1][1].debug_fsrc, UInt<1>(0h0)) node _T_1898 = mux(_T_210, deq_vec[2][1].debug_fsrc, UInt<1>(0h0)) node _T_1899 = mux(_T_211, deq_vec[3][1].debug_fsrc, UInt<1>(0h0)) node _T_1900 = mux(_T_212, deq_vec[4][1].debug_fsrc, UInt<1>(0h0)) node _T_1901 = mux(_T_213, deq_vec[5][1].debug_fsrc, UInt<1>(0h0)) node _T_1902 = mux(_T_214, deq_vec[6][1].debug_fsrc, UInt<1>(0h0)) node _T_1903 = mux(_T_215, deq_vec[7][1].debug_fsrc, UInt<1>(0h0)) node _T_1904 = or(_T_1896, _T_1897) node _T_1905 = or(_T_1904, _T_1898) node _T_1906 = or(_T_1905, _T_1899) node _T_1907 = or(_T_1906, _T_1900) node _T_1908 = or(_T_1907, _T_1901) node _T_1909 = or(_T_1908, _T_1902) node _T_1910 = or(_T_1909, _T_1903) wire _WIRE_118 : UInt<3> connect _WIRE_118, _T_1910 connect _WIRE_116.debug_fsrc, _WIRE_118 node _T_1911 = mux(_T_208, deq_vec[0][1].bp_xcpt_if, UInt<1>(0h0)) node _T_1912 = mux(_T_209, deq_vec[1][1].bp_xcpt_if, UInt<1>(0h0)) node _T_1913 = mux(_T_210, deq_vec[2][1].bp_xcpt_if, UInt<1>(0h0)) node _T_1914 = mux(_T_211, deq_vec[3][1].bp_xcpt_if, UInt<1>(0h0)) node _T_1915 = mux(_T_212, deq_vec[4][1].bp_xcpt_if, UInt<1>(0h0)) node _T_1916 = mux(_T_213, deq_vec[5][1].bp_xcpt_if, UInt<1>(0h0)) node _T_1917 = mux(_T_214, deq_vec[6][1].bp_xcpt_if, UInt<1>(0h0)) node _T_1918 = mux(_T_215, deq_vec[7][1].bp_xcpt_if, UInt<1>(0h0)) node _T_1919 = or(_T_1911, _T_1912) node _T_1920 = or(_T_1919, _T_1913) node _T_1921 = or(_T_1920, _T_1914) node _T_1922 = or(_T_1921, _T_1915) node _T_1923 = or(_T_1922, _T_1916) node _T_1924 = or(_T_1923, _T_1917) node _T_1925 = or(_T_1924, _T_1918) wire _WIRE_119 : UInt<1> connect _WIRE_119, _T_1925 connect _WIRE_116.bp_xcpt_if, _WIRE_119 node _T_1926 = mux(_T_208, deq_vec[0][1].bp_debug_if, UInt<1>(0h0)) node _T_1927 = mux(_T_209, deq_vec[1][1].bp_debug_if, UInt<1>(0h0)) node _T_1928 = mux(_T_210, deq_vec[2][1].bp_debug_if, UInt<1>(0h0)) node _T_1929 = mux(_T_211, deq_vec[3][1].bp_debug_if, UInt<1>(0h0)) node _T_1930 = mux(_T_212, deq_vec[4][1].bp_debug_if, UInt<1>(0h0)) node _T_1931 = mux(_T_213, deq_vec[5][1].bp_debug_if, UInt<1>(0h0)) node _T_1932 = mux(_T_214, deq_vec[6][1].bp_debug_if, UInt<1>(0h0)) node _T_1933 = mux(_T_215, deq_vec[7][1].bp_debug_if, UInt<1>(0h0)) node _T_1934 = or(_T_1926, _T_1927) node _T_1935 = or(_T_1934, _T_1928) node _T_1936 = or(_T_1935, _T_1929) node _T_1937 = or(_T_1936, _T_1930) node _T_1938 = or(_T_1937, _T_1931) node _T_1939 = or(_T_1938, _T_1932) node _T_1940 = or(_T_1939, _T_1933) wire _WIRE_120 : UInt<1> connect _WIRE_120, _T_1940 connect _WIRE_116.bp_debug_if, _WIRE_120 node _T_1941 = mux(_T_208, deq_vec[0][1].xcpt_ma_if, UInt<1>(0h0)) node _T_1942 = mux(_T_209, deq_vec[1][1].xcpt_ma_if, UInt<1>(0h0)) node _T_1943 = mux(_T_210, deq_vec[2][1].xcpt_ma_if, UInt<1>(0h0)) node _T_1944 = mux(_T_211, deq_vec[3][1].xcpt_ma_if, UInt<1>(0h0)) node _T_1945 = mux(_T_212, deq_vec[4][1].xcpt_ma_if, UInt<1>(0h0)) node _T_1946 = mux(_T_213, deq_vec[5][1].xcpt_ma_if, UInt<1>(0h0)) node _T_1947 = mux(_T_214, deq_vec[6][1].xcpt_ma_if, UInt<1>(0h0)) node _T_1948 = mux(_T_215, deq_vec[7][1].xcpt_ma_if, UInt<1>(0h0)) node _T_1949 = or(_T_1941, _T_1942) node _T_1950 = or(_T_1949, _T_1943) node _T_1951 = or(_T_1950, _T_1944) node _T_1952 = or(_T_1951, _T_1945) node _T_1953 = or(_T_1952, _T_1946) node _T_1954 = or(_T_1953, _T_1947) node _T_1955 = or(_T_1954, _T_1948) wire _WIRE_121 : UInt<1> connect _WIRE_121, _T_1955 connect _WIRE_116.xcpt_ma_if, _WIRE_121 node _T_1956 = mux(_T_208, deq_vec[0][1].xcpt_ae_if, UInt<1>(0h0)) node _T_1957 = mux(_T_209, deq_vec[1][1].xcpt_ae_if, UInt<1>(0h0)) node _T_1958 = mux(_T_210, deq_vec[2][1].xcpt_ae_if, UInt<1>(0h0)) node _T_1959 = mux(_T_211, deq_vec[3][1].xcpt_ae_if, UInt<1>(0h0)) node _T_1960 = mux(_T_212, deq_vec[4][1].xcpt_ae_if, UInt<1>(0h0)) node _T_1961 = mux(_T_213, deq_vec[5][1].xcpt_ae_if, UInt<1>(0h0)) node _T_1962 = mux(_T_214, deq_vec[6][1].xcpt_ae_if, UInt<1>(0h0)) node _T_1963 = mux(_T_215, deq_vec[7][1].xcpt_ae_if, UInt<1>(0h0)) node _T_1964 = or(_T_1956, _T_1957) node _T_1965 = or(_T_1964, _T_1958) node _T_1966 = or(_T_1965, _T_1959) node _T_1967 = or(_T_1966, _T_1960) node _T_1968 = or(_T_1967, _T_1961) node _T_1969 = or(_T_1968, _T_1962) node _T_1970 = or(_T_1969, _T_1963) wire _WIRE_122 : UInt<1> connect _WIRE_122, _T_1970 connect _WIRE_116.xcpt_ae_if, _WIRE_122 node _T_1971 = mux(_T_208, deq_vec[0][1].xcpt_pf_if, UInt<1>(0h0)) node _T_1972 = mux(_T_209, deq_vec[1][1].xcpt_pf_if, UInt<1>(0h0)) node _T_1973 = mux(_T_210, deq_vec[2][1].xcpt_pf_if, UInt<1>(0h0)) node _T_1974 = mux(_T_211, deq_vec[3][1].xcpt_pf_if, UInt<1>(0h0)) node _T_1975 = mux(_T_212, deq_vec[4][1].xcpt_pf_if, UInt<1>(0h0)) node _T_1976 = mux(_T_213, deq_vec[5][1].xcpt_pf_if, UInt<1>(0h0)) node _T_1977 = mux(_T_214, deq_vec[6][1].xcpt_pf_if, UInt<1>(0h0)) node _T_1978 = mux(_T_215, deq_vec[7][1].xcpt_pf_if, UInt<1>(0h0)) node _T_1979 = or(_T_1971, _T_1972) node _T_1980 = or(_T_1979, _T_1973) node _T_1981 = or(_T_1980, _T_1974) node _T_1982 = or(_T_1981, _T_1975) node _T_1983 = or(_T_1982, _T_1976) node _T_1984 = or(_T_1983, _T_1977) node _T_1985 = or(_T_1984, _T_1978) wire _WIRE_123 : UInt<1> connect _WIRE_123, _T_1985 connect _WIRE_116.xcpt_pf_if, _WIRE_123 node _T_1986 = mux(_T_208, deq_vec[0][1].fp_typ, UInt<1>(0h0)) node _T_1987 = mux(_T_209, deq_vec[1][1].fp_typ, UInt<1>(0h0)) node _T_1988 = mux(_T_210, deq_vec[2][1].fp_typ, UInt<1>(0h0)) node _T_1989 = mux(_T_211, deq_vec[3][1].fp_typ, UInt<1>(0h0)) node _T_1990 = mux(_T_212, deq_vec[4][1].fp_typ, UInt<1>(0h0)) node _T_1991 = mux(_T_213, deq_vec[5][1].fp_typ, UInt<1>(0h0)) node _T_1992 = mux(_T_214, deq_vec[6][1].fp_typ, UInt<1>(0h0)) node _T_1993 = mux(_T_215, deq_vec[7][1].fp_typ, UInt<1>(0h0)) node _T_1994 = or(_T_1986, _T_1987) node _T_1995 = or(_T_1994, _T_1988) node _T_1996 = or(_T_1995, _T_1989) node _T_1997 = or(_T_1996, _T_1990) node _T_1998 = or(_T_1997, _T_1991) node _T_1999 = or(_T_1998, _T_1992) node _T_2000 = or(_T_1999, _T_1993) wire _WIRE_124 : UInt<2> connect _WIRE_124, _T_2000 connect _WIRE_116.fp_typ, _WIRE_124 node _T_2001 = mux(_T_208, deq_vec[0][1].fp_rm, UInt<1>(0h0)) node _T_2002 = mux(_T_209, deq_vec[1][1].fp_rm, UInt<1>(0h0)) node _T_2003 = mux(_T_210, deq_vec[2][1].fp_rm, UInt<1>(0h0)) node _T_2004 = mux(_T_211, deq_vec[3][1].fp_rm, UInt<1>(0h0)) node _T_2005 = mux(_T_212, deq_vec[4][1].fp_rm, UInt<1>(0h0)) node _T_2006 = mux(_T_213, deq_vec[5][1].fp_rm, UInt<1>(0h0)) node _T_2007 = mux(_T_214, deq_vec[6][1].fp_rm, UInt<1>(0h0)) node _T_2008 = mux(_T_215, deq_vec[7][1].fp_rm, UInt<1>(0h0)) node _T_2009 = or(_T_2001, _T_2002) node _T_2010 = or(_T_2009, _T_2003) node _T_2011 = or(_T_2010, _T_2004) node _T_2012 = or(_T_2011, _T_2005) node _T_2013 = or(_T_2012, _T_2006) node _T_2014 = or(_T_2013, _T_2007) node _T_2015 = or(_T_2014, _T_2008) wire _WIRE_125 : UInt<3> connect _WIRE_125, _T_2015 connect _WIRE_116.fp_rm, _WIRE_125 node _T_2016 = mux(_T_208, deq_vec[0][1].fp_val, UInt<1>(0h0)) node _T_2017 = mux(_T_209, deq_vec[1][1].fp_val, UInt<1>(0h0)) node _T_2018 = mux(_T_210, deq_vec[2][1].fp_val, UInt<1>(0h0)) node _T_2019 = mux(_T_211, deq_vec[3][1].fp_val, UInt<1>(0h0)) node _T_2020 = mux(_T_212, deq_vec[4][1].fp_val, UInt<1>(0h0)) node _T_2021 = mux(_T_213, deq_vec[5][1].fp_val, UInt<1>(0h0)) node _T_2022 = mux(_T_214, deq_vec[6][1].fp_val, UInt<1>(0h0)) node _T_2023 = mux(_T_215, deq_vec[7][1].fp_val, UInt<1>(0h0)) node _T_2024 = or(_T_2016, _T_2017) node _T_2025 = or(_T_2024, _T_2018) node _T_2026 = or(_T_2025, _T_2019) node _T_2027 = or(_T_2026, _T_2020) node _T_2028 = or(_T_2027, _T_2021) node _T_2029 = or(_T_2028, _T_2022) node _T_2030 = or(_T_2029, _T_2023) wire _WIRE_126 : UInt<1> connect _WIRE_126, _T_2030 connect _WIRE_116.fp_val, _WIRE_126 node _T_2031 = mux(_T_208, deq_vec[0][1].fcn_op, UInt<1>(0h0)) node _T_2032 = mux(_T_209, deq_vec[1][1].fcn_op, UInt<1>(0h0)) node _T_2033 = mux(_T_210, deq_vec[2][1].fcn_op, UInt<1>(0h0)) node _T_2034 = mux(_T_211, deq_vec[3][1].fcn_op, UInt<1>(0h0)) node _T_2035 = mux(_T_212, deq_vec[4][1].fcn_op, UInt<1>(0h0)) node _T_2036 = mux(_T_213, deq_vec[5][1].fcn_op, UInt<1>(0h0)) node _T_2037 = mux(_T_214, deq_vec[6][1].fcn_op, UInt<1>(0h0)) node _T_2038 = mux(_T_215, deq_vec[7][1].fcn_op, UInt<1>(0h0)) node _T_2039 = or(_T_2031, _T_2032) node _T_2040 = or(_T_2039, _T_2033) node _T_2041 = or(_T_2040, _T_2034) node _T_2042 = or(_T_2041, _T_2035) node _T_2043 = or(_T_2042, _T_2036) node _T_2044 = or(_T_2043, _T_2037) node _T_2045 = or(_T_2044, _T_2038) wire _WIRE_127 : UInt<5> connect _WIRE_127, _T_2045 connect _WIRE_116.fcn_op, _WIRE_127 node _T_2046 = mux(_T_208, deq_vec[0][1].fcn_dw, UInt<1>(0h0)) node _T_2047 = mux(_T_209, deq_vec[1][1].fcn_dw, UInt<1>(0h0)) node _T_2048 = mux(_T_210, deq_vec[2][1].fcn_dw, UInt<1>(0h0)) node _T_2049 = mux(_T_211, deq_vec[3][1].fcn_dw, UInt<1>(0h0)) node _T_2050 = mux(_T_212, deq_vec[4][1].fcn_dw, UInt<1>(0h0)) node _T_2051 = mux(_T_213, deq_vec[5][1].fcn_dw, UInt<1>(0h0)) node _T_2052 = mux(_T_214, deq_vec[6][1].fcn_dw, UInt<1>(0h0)) node _T_2053 = mux(_T_215, deq_vec[7][1].fcn_dw, UInt<1>(0h0)) node _T_2054 = or(_T_2046, _T_2047) node _T_2055 = or(_T_2054, _T_2048) node _T_2056 = or(_T_2055, _T_2049) node _T_2057 = or(_T_2056, _T_2050) node _T_2058 = or(_T_2057, _T_2051) node _T_2059 = or(_T_2058, _T_2052) node _T_2060 = or(_T_2059, _T_2053) wire _WIRE_128 : UInt<1> connect _WIRE_128, _T_2060 connect _WIRE_116.fcn_dw, _WIRE_128 node _T_2061 = mux(_T_208, deq_vec[0][1].frs3_en, UInt<1>(0h0)) node _T_2062 = mux(_T_209, deq_vec[1][1].frs3_en, UInt<1>(0h0)) node _T_2063 = mux(_T_210, deq_vec[2][1].frs3_en, UInt<1>(0h0)) node _T_2064 = mux(_T_211, deq_vec[3][1].frs3_en, UInt<1>(0h0)) node _T_2065 = mux(_T_212, deq_vec[4][1].frs3_en, UInt<1>(0h0)) node _T_2066 = mux(_T_213, deq_vec[5][1].frs3_en, UInt<1>(0h0)) node _T_2067 = mux(_T_214, deq_vec[6][1].frs3_en, UInt<1>(0h0)) node _T_2068 = mux(_T_215, deq_vec[7][1].frs3_en, UInt<1>(0h0)) node _T_2069 = or(_T_2061, _T_2062) node _T_2070 = or(_T_2069, _T_2063) node _T_2071 = or(_T_2070, _T_2064) node _T_2072 = or(_T_2071, _T_2065) node _T_2073 = or(_T_2072, _T_2066) node _T_2074 = or(_T_2073, _T_2067) node _T_2075 = or(_T_2074, _T_2068) wire _WIRE_129 : UInt<1> connect _WIRE_129, _T_2075 connect _WIRE_116.frs3_en, _WIRE_129 node _T_2076 = mux(_T_208, deq_vec[0][1].lrs2_rtype, UInt<1>(0h0)) node _T_2077 = mux(_T_209, deq_vec[1][1].lrs2_rtype, UInt<1>(0h0)) node _T_2078 = mux(_T_210, deq_vec[2][1].lrs2_rtype, UInt<1>(0h0)) node _T_2079 = mux(_T_211, deq_vec[3][1].lrs2_rtype, UInt<1>(0h0)) node _T_2080 = mux(_T_212, deq_vec[4][1].lrs2_rtype, UInt<1>(0h0)) node _T_2081 = mux(_T_213, deq_vec[5][1].lrs2_rtype, UInt<1>(0h0)) node _T_2082 = mux(_T_214, deq_vec[6][1].lrs2_rtype, UInt<1>(0h0)) node _T_2083 = mux(_T_215, deq_vec[7][1].lrs2_rtype, UInt<1>(0h0)) node _T_2084 = or(_T_2076, _T_2077) node _T_2085 = or(_T_2084, _T_2078) node _T_2086 = or(_T_2085, _T_2079) node _T_2087 = or(_T_2086, _T_2080) node _T_2088 = or(_T_2087, _T_2081) node _T_2089 = or(_T_2088, _T_2082) node _T_2090 = or(_T_2089, _T_2083) wire _WIRE_130 : UInt<2> connect _WIRE_130, _T_2090 connect _WIRE_116.lrs2_rtype, _WIRE_130 node _T_2091 = mux(_T_208, deq_vec[0][1].lrs1_rtype, UInt<1>(0h0)) node _T_2092 = mux(_T_209, deq_vec[1][1].lrs1_rtype, UInt<1>(0h0)) node _T_2093 = mux(_T_210, deq_vec[2][1].lrs1_rtype, UInt<1>(0h0)) node _T_2094 = mux(_T_211, deq_vec[3][1].lrs1_rtype, UInt<1>(0h0)) node _T_2095 = mux(_T_212, deq_vec[4][1].lrs1_rtype, UInt<1>(0h0)) node _T_2096 = mux(_T_213, deq_vec[5][1].lrs1_rtype, UInt<1>(0h0)) node _T_2097 = mux(_T_214, deq_vec[6][1].lrs1_rtype, UInt<1>(0h0)) node _T_2098 = mux(_T_215, deq_vec[7][1].lrs1_rtype, UInt<1>(0h0)) node _T_2099 = or(_T_2091, _T_2092) node _T_2100 = or(_T_2099, _T_2093) node _T_2101 = or(_T_2100, _T_2094) node _T_2102 = or(_T_2101, _T_2095) node _T_2103 = or(_T_2102, _T_2096) node _T_2104 = or(_T_2103, _T_2097) node _T_2105 = or(_T_2104, _T_2098) wire _WIRE_131 : UInt<2> connect _WIRE_131, _T_2105 connect _WIRE_116.lrs1_rtype, _WIRE_131 node _T_2106 = mux(_T_208, deq_vec[0][1].dst_rtype, UInt<1>(0h0)) node _T_2107 = mux(_T_209, deq_vec[1][1].dst_rtype, UInt<1>(0h0)) node _T_2108 = mux(_T_210, deq_vec[2][1].dst_rtype, UInt<1>(0h0)) node _T_2109 = mux(_T_211, deq_vec[3][1].dst_rtype, UInt<1>(0h0)) node _T_2110 = mux(_T_212, deq_vec[4][1].dst_rtype, UInt<1>(0h0)) node _T_2111 = mux(_T_213, deq_vec[5][1].dst_rtype, UInt<1>(0h0)) node _T_2112 = mux(_T_214, deq_vec[6][1].dst_rtype, UInt<1>(0h0)) node _T_2113 = mux(_T_215, deq_vec[7][1].dst_rtype, UInt<1>(0h0)) node _T_2114 = or(_T_2106, _T_2107) node _T_2115 = or(_T_2114, _T_2108) node _T_2116 = or(_T_2115, _T_2109) node _T_2117 = or(_T_2116, _T_2110) node _T_2118 = or(_T_2117, _T_2111) node _T_2119 = or(_T_2118, _T_2112) node _T_2120 = or(_T_2119, _T_2113) wire _WIRE_132 : UInt<2> connect _WIRE_132, _T_2120 connect _WIRE_116.dst_rtype, _WIRE_132 node _T_2121 = mux(_T_208, deq_vec[0][1].lrs3, UInt<1>(0h0)) node _T_2122 = mux(_T_209, deq_vec[1][1].lrs3, UInt<1>(0h0)) node _T_2123 = mux(_T_210, deq_vec[2][1].lrs3, UInt<1>(0h0)) node _T_2124 = mux(_T_211, deq_vec[3][1].lrs3, UInt<1>(0h0)) node _T_2125 = mux(_T_212, deq_vec[4][1].lrs3, UInt<1>(0h0)) node _T_2126 = mux(_T_213, deq_vec[5][1].lrs3, UInt<1>(0h0)) node _T_2127 = mux(_T_214, deq_vec[6][1].lrs3, UInt<1>(0h0)) node _T_2128 = mux(_T_215, deq_vec[7][1].lrs3, UInt<1>(0h0)) node _T_2129 = or(_T_2121, _T_2122) node _T_2130 = or(_T_2129, _T_2123) node _T_2131 = or(_T_2130, _T_2124) node _T_2132 = or(_T_2131, _T_2125) node _T_2133 = or(_T_2132, _T_2126) node _T_2134 = or(_T_2133, _T_2127) node _T_2135 = or(_T_2134, _T_2128) wire _WIRE_133 : UInt<6> connect _WIRE_133, _T_2135 connect _WIRE_116.lrs3, _WIRE_133 node _T_2136 = mux(_T_208, deq_vec[0][1].lrs2, UInt<1>(0h0)) node _T_2137 = mux(_T_209, deq_vec[1][1].lrs2, UInt<1>(0h0)) node _T_2138 = mux(_T_210, deq_vec[2][1].lrs2, UInt<1>(0h0)) node _T_2139 = mux(_T_211, deq_vec[3][1].lrs2, UInt<1>(0h0)) node _T_2140 = mux(_T_212, deq_vec[4][1].lrs2, UInt<1>(0h0)) node _T_2141 = mux(_T_213, deq_vec[5][1].lrs2, UInt<1>(0h0)) node _T_2142 = mux(_T_214, deq_vec[6][1].lrs2, UInt<1>(0h0)) node _T_2143 = mux(_T_215, deq_vec[7][1].lrs2, UInt<1>(0h0)) node _T_2144 = or(_T_2136, _T_2137) node _T_2145 = or(_T_2144, _T_2138) node _T_2146 = or(_T_2145, _T_2139) node _T_2147 = or(_T_2146, _T_2140) node _T_2148 = or(_T_2147, _T_2141) node _T_2149 = or(_T_2148, _T_2142) node _T_2150 = or(_T_2149, _T_2143) wire _WIRE_134 : UInt<6> connect _WIRE_134, _T_2150 connect _WIRE_116.lrs2, _WIRE_134 node _T_2151 = mux(_T_208, deq_vec[0][1].lrs1, UInt<1>(0h0)) node _T_2152 = mux(_T_209, deq_vec[1][1].lrs1, UInt<1>(0h0)) node _T_2153 = mux(_T_210, deq_vec[2][1].lrs1, UInt<1>(0h0)) node _T_2154 = mux(_T_211, deq_vec[3][1].lrs1, UInt<1>(0h0)) node _T_2155 = mux(_T_212, deq_vec[4][1].lrs1, UInt<1>(0h0)) node _T_2156 = mux(_T_213, deq_vec[5][1].lrs1, UInt<1>(0h0)) node _T_2157 = mux(_T_214, deq_vec[6][1].lrs1, UInt<1>(0h0)) node _T_2158 = mux(_T_215, deq_vec[7][1].lrs1, UInt<1>(0h0)) node _T_2159 = or(_T_2151, _T_2152) node _T_2160 = or(_T_2159, _T_2153) node _T_2161 = or(_T_2160, _T_2154) node _T_2162 = or(_T_2161, _T_2155) node _T_2163 = or(_T_2162, _T_2156) node _T_2164 = or(_T_2163, _T_2157) node _T_2165 = or(_T_2164, _T_2158) wire _WIRE_135 : UInt<6> connect _WIRE_135, _T_2165 connect _WIRE_116.lrs1, _WIRE_135 node _T_2166 = mux(_T_208, deq_vec[0][1].ldst, UInt<1>(0h0)) node _T_2167 = mux(_T_209, deq_vec[1][1].ldst, UInt<1>(0h0)) node _T_2168 = mux(_T_210, deq_vec[2][1].ldst, UInt<1>(0h0)) node _T_2169 = mux(_T_211, deq_vec[3][1].ldst, UInt<1>(0h0)) node _T_2170 = mux(_T_212, deq_vec[4][1].ldst, UInt<1>(0h0)) node _T_2171 = mux(_T_213, deq_vec[5][1].ldst, UInt<1>(0h0)) node _T_2172 = mux(_T_214, deq_vec[6][1].ldst, UInt<1>(0h0)) node _T_2173 = mux(_T_215, deq_vec[7][1].ldst, UInt<1>(0h0)) node _T_2174 = or(_T_2166, _T_2167) node _T_2175 = or(_T_2174, _T_2168) node _T_2176 = or(_T_2175, _T_2169) node _T_2177 = or(_T_2176, _T_2170) node _T_2178 = or(_T_2177, _T_2171) node _T_2179 = or(_T_2178, _T_2172) node _T_2180 = or(_T_2179, _T_2173) wire _WIRE_136 : UInt<6> connect _WIRE_136, _T_2180 connect _WIRE_116.ldst, _WIRE_136 node _T_2181 = mux(_T_208, deq_vec[0][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2182 = mux(_T_209, deq_vec[1][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2183 = mux(_T_210, deq_vec[2][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2184 = mux(_T_211, deq_vec[3][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2185 = mux(_T_212, deq_vec[4][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2186 = mux(_T_213, deq_vec[5][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2187 = mux(_T_214, deq_vec[6][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2188 = mux(_T_215, deq_vec[7][1].ldst_is_rs1, UInt<1>(0h0)) node _T_2189 = or(_T_2181, _T_2182) node _T_2190 = or(_T_2189, _T_2183) node _T_2191 = or(_T_2190, _T_2184) node _T_2192 = or(_T_2191, _T_2185) node _T_2193 = or(_T_2192, _T_2186) node _T_2194 = or(_T_2193, _T_2187) node _T_2195 = or(_T_2194, _T_2188) wire _WIRE_137 : UInt<1> connect _WIRE_137, _T_2195 connect _WIRE_116.ldst_is_rs1, _WIRE_137 node _T_2196 = mux(_T_208, deq_vec[0][1].csr_cmd, UInt<1>(0h0)) node _T_2197 = mux(_T_209, deq_vec[1][1].csr_cmd, UInt<1>(0h0)) node _T_2198 = mux(_T_210, deq_vec[2][1].csr_cmd, UInt<1>(0h0)) node _T_2199 = mux(_T_211, deq_vec[3][1].csr_cmd, UInt<1>(0h0)) node _T_2200 = mux(_T_212, deq_vec[4][1].csr_cmd, UInt<1>(0h0)) node _T_2201 = mux(_T_213, deq_vec[5][1].csr_cmd, UInt<1>(0h0)) node _T_2202 = mux(_T_214, deq_vec[6][1].csr_cmd, UInt<1>(0h0)) node _T_2203 = mux(_T_215, deq_vec[7][1].csr_cmd, UInt<1>(0h0)) node _T_2204 = or(_T_2196, _T_2197) node _T_2205 = or(_T_2204, _T_2198) node _T_2206 = or(_T_2205, _T_2199) node _T_2207 = or(_T_2206, _T_2200) node _T_2208 = or(_T_2207, _T_2201) node _T_2209 = or(_T_2208, _T_2202) node _T_2210 = or(_T_2209, _T_2203) wire _WIRE_138 : UInt<3> connect _WIRE_138, _T_2210 connect _WIRE_116.csr_cmd, _WIRE_138 node _T_2211 = mux(_T_208, deq_vec[0][1].flush_on_commit, UInt<1>(0h0)) node _T_2212 = mux(_T_209, deq_vec[1][1].flush_on_commit, UInt<1>(0h0)) node _T_2213 = mux(_T_210, deq_vec[2][1].flush_on_commit, UInt<1>(0h0)) node _T_2214 = mux(_T_211, deq_vec[3][1].flush_on_commit, UInt<1>(0h0)) node _T_2215 = mux(_T_212, deq_vec[4][1].flush_on_commit, UInt<1>(0h0)) node _T_2216 = mux(_T_213, deq_vec[5][1].flush_on_commit, UInt<1>(0h0)) node _T_2217 = mux(_T_214, deq_vec[6][1].flush_on_commit, UInt<1>(0h0)) node _T_2218 = mux(_T_215, deq_vec[7][1].flush_on_commit, UInt<1>(0h0)) node _T_2219 = or(_T_2211, _T_2212) node _T_2220 = or(_T_2219, _T_2213) node _T_2221 = or(_T_2220, _T_2214) node _T_2222 = or(_T_2221, _T_2215) node _T_2223 = or(_T_2222, _T_2216) node _T_2224 = or(_T_2223, _T_2217) node _T_2225 = or(_T_2224, _T_2218) wire _WIRE_139 : UInt<1> connect _WIRE_139, _T_2225 connect _WIRE_116.flush_on_commit, _WIRE_139 node _T_2226 = mux(_T_208, deq_vec[0][1].is_unique, UInt<1>(0h0)) node _T_2227 = mux(_T_209, deq_vec[1][1].is_unique, UInt<1>(0h0)) node _T_2228 = mux(_T_210, deq_vec[2][1].is_unique, UInt<1>(0h0)) node _T_2229 = mux(_T_211, deq_vec[3][1].is_unique, UInt<1>(0h0)) node _T_2230 = mux(_T_212, deq_vec[4][1].is_unique, UInt<1>(0h0)) node _T_2231 = mux(_T_213, deq_vec[5][1].is_unique, UInt<1>(0h0)) node _T_2232 = mux(_T_214, deq_vec[6][1].is_unique, UInt<1>(0h0)) node _T_2233 = mux(_T_215, deq_vec[7][1].is_unique, UInt<1>(0h0)) node _T_2234 = or(_T_2226, _T_2227) node _T_2235 = or(_T_2234, _T_2228) node _T_2236 = or(_T_2235, _T_2229) node _T_2237 = or(_T_2236, _T_2230) node _T_2238 = or(_T_2237, _T_2231) node _T_2239 = or(_T_2238, _T_2232) node _T_2240 = or(_T_2239, _T_2233) wire _WIRE_140 : UInt<1> connect _WIRE_140, _T_2240 connect _WIRE_116.is_unique, _WIRE_140 node _T_2241 = mux(_T_208, deq_vec[0][1].uses_stq, UInt<1>(0h0)) node _T_2242 = mux(_T_209, deq_vec[1][1].uses_stq, UInt<1>(0h0)) node _T_2243 = mux(_T_210, deq_vec[2][1].uses_stq, UInt<1>(0h0)) node _T_2244 = mux(_T_211, deq_vec[3][1].uses_stq, UInt<1>(0h0)) node _T_2245 = mux(_T_212, deq_vec[4][1].uses_stq, UInt<1>(0h0)) node _T_2246 = mux(_T_213, deq_vec[5][1].uses_stq, UInt<1>(0h0)) node _T_2247 = mux(_T_214, deq_vec[6][1].uses_stq, UInt<1>(0h0)) node _T_2248 = mux(_T_215, deq_vec[7][1].uses_stq, UInt<1>(0h0)) node _T_2249 = or(_T_2241, _T_2242) node _T_2250 = or(_T_2249, _T_2243) node _T_2251 = or(_T_2250, _T_2244) node _T_2252 = or(_T_2251, _T_2245) node _T_2253 = or(_T_2252, _T_2246) node _T_2254 = or(_T_2253, _T_2247) node _T_2255 = or(_T_2254, _T_2248) wire _WIRE_141 : UInt<1> connect _WIRE_141, _T_2255 connect _WIRE_116.uses_stq, _WIRE_141 node _T_2256 = mux(_T_208, deq_vec[0][1].uses_ldq, UInt<1>(0h0)) node _T_2257 = mux(_T_209, deq_vec[1][1].uses_ldq, UInt<1>(0h0)) node _T_2258 = mux(_T_210, deq_vec[2][1].uses_ldq, UInt<1>(0h0)) node _T_2259 = mux(_T_211, deq_vec[3][1].uses_ldq, UInt<1>(0h0)) node _T_2260 = mux(_T_212, deq_vec[4][1].uses_ldq, UInt<1>(0h0)) node _T_2261 = mux(_T_213, deq_vec[5][1].uses_ldq, UInt<1>(0h0)) node _T_2262 = mux(_T_214, deq_vec[6][1].uses_ldq, UInt<1>(0h0)) node _T_2263 = mux(_T_215, deq_vec[7][1].uses_ldq, UInt<1>(0h0)) node _T_2264 = or(_T_2256, _T_2257) node _T_2265 = or(_T_2264, _T_2258) node _T_2266 = or(_T_2265, _T_2259) node _T_2267 = or(_T_2266, _T_2260) node _T_2268 = or(_T_2267, _T_2261) node _T_2269 = or(_T_2268, _T_2262) node _T_2270 = or(_T_2269, _T_2263) wire _WIRE_142 : UInt<1> connect _WIRE_142, _T_2270 connect _WIRE_116.uses_ldq, _WIRE_142 node _T_2271 = mux(_T_208, deq_vec[0][1].mem_signed, UInt<1>(0h0)) node _T_2272 = mux(_T_209, deq_vec[1][1].mem_signed, UInt<1>(0h0)) node _T_2273 = mux(_T_210, deq_vec[2][1].mem_signed, UInt<1>(0h0)) node _T_2274 = mux(_T_211, deq_vec[3][1].mem_signed, UInt<1>(0h0)) node _T_2275 = mux(_T_212, deq_vec[4][1].mem_signed, UInt<1>(0h0)) node _T_2276 = mux(_T_213, deq_vec[5][1].mem_signed, UInt<1>(0h0)) node _T_2277 = mux(_T_214, deq_vec[6][1].mem_signed, UInt<1>(0h0)) node _T_2278 = mux(_T_215, deq_vec[7][1].mem_signed, UInt<1>(0h0)) node _T_2279 = or(_T_2271, _T_2272) node _T_2280 = or(_T_2279, _T_2273) node _T_2281 = or(_T_2280, _T_2274) node _T_2282 = or(_T_2281, _T_2275) node _T_2283 = or(_T_2282, _T_2276) node _T_2284 = or(_T_2283, _T_2277) node _T_2285 = or(_T_2284, _T_2278) wire _WIRE_143 : UInt<1> connect _WIRE_143, _T_2285 connect _WIRE_116.mem_signed, _WIRE_143 node _T_2286 = mux(_T_208, deq_vec[0][1].mem_size, UInt<1>(0h0)) node _T_2287 = mux(_T_209, deq_vec[1][1].mem_size, UInt<1>(0h0)) node _T_2288 = mux(_T_210, deq_vec[2][1].mem_size, UInt<1>(0h0)) node _T_2289 = mux(_T_211, deq_vec[3][1].mem_size, UInt<1>(0h0)) node _T_2290 = mux(_T_212, deq_vec[4][1].mem_size, UInt<1>(0h0)) node _T_2291 = mux(_T_213, deq_vec[5][1].mem_size, UInt<1>(0h0)) node _T_2292 = mux(_T_214, deq_vec[6][1].mem_size, UInt<1>(0h0)) node _T_2293 = mux(_T_215, deq_vec[7][1].mem_size, UInt<1>(0h0)) node _T_2294 = or(_T_2286, _T_2287) node _T_2295 = or(_T_2294, _T_2288) node _T_2296 = or(_T_2295, _T_2289) node _T_2297 = or(_T_2296, _T_2290) node _T_2298 = or(_T_2297, _T_2291) node _T_2299 = or(_T_2298, _T_2292) node _T_2300 = or(_T_2299, _T_2293) wire _WIRE_144 : UInt<2> connect _WIRE_144, _T_2300 connect _WIRE_116.mem_size, _WIRE_144 node _T_2301 = mux(_T_208, deq_vec[0][1].mem_cmd, UInt<1>(0h0)) node _T_2302 = mux(_T_209, deq_vec[1][1].mem_cmd, UInt<1>(0h0)) node _T_2303 = mux(_T_210, deq_vec[2][1].mem_cmd, UInt<1>(0h0)) node _T_2304 = mux(_T_211, deq_vec[3][1].mem_cmd, UInt<1>(0h0)) node _T_2305 = mux(_T_212, deq_vec[4][1].mem_cmd, UInt<1>(0h0)) node _T_2306 = mux(_T_213, deq_vec[5][1].mem_cmd, UInt<1>(0h0)) node _T_2307 = mux(_T_214, deq_vec[6][1].mem_cmd, UInt<1>(0h0)) node _T_2308 = mux(_T_215, deq_vec[7][1].mem_cmd, UInt<1>(0h0)) node _T_2309 = or(_T_2301, _T_2302) node _T_2310 = or(_T_2309, _T_2303) node _T_2311 = or(_T_2310, _T_2304) node _T_2312 = or(_T_2311, _T_2305) node _T_2313 = or(_T_2312, _T_2306) node _T_2314 = or(_T_2313, _T_2307) node _T_2315 = or(_T_2314, _T_2308) wire _WIRE_145 : UInt<5> connect _WIRE_145, _T_2315 connect _WIRE_116.mem_cmd, _WIRE_145 node _T_2316 = mux(_T_208, deq_vec[0][1].exc_cause, UInt<1>(0h0)) node _T_2317 = mux(_T_209, deq_vec[1][1].exc_cause, UInt<1>(0h0)) node _T_2318 = mux(_T_210, deq_vec[2][1].exc_cause, UInt<1>(0h0)) node _T_2319 = mux(_T_211, deq_vec[3][1].exc_cause, UInt<1>(0h0)) node _T_2320 = mux(_T_212, deq_vec[4][1].exc_cause, UInt<1>(0h0)) node _T_2321 = mux(_T_213, deq_vec[5][1].exc_cause, UInt<1>(0h0)) node _T_2322 = mux(_T_214, deq_vec[6][1].exc_cause, UInt<1>(0h0)) node _T_2323 = mux(_T_215, deq_vec[7][1].exc_cause, UInt<1>(0h0)) node _T_2324 = or(_T_2316, _T_2317) node _T_2325 = or(_T_2324, _T_2318) node _T_2326 = or(_T_2325, _T_2319) node _T_2327 = or(_T_2326, _T_2320) node _T_2328 = or(_T_2327, _T_2321) node _T_2329 = or(_T_2328, _T_2322) node _T_2330 = or(_T_2329, _T_2323) wire _WIRE_146 : UInt<64> connect _WIRE_146, _T_2330 connect _WIRE_116.exc_cause, _WIRE_146 node _T_2331 = mux(_T_208, deq_vec[0][1].exception, UInt<1>(0h0)) node _T_2332 = mux(_T_209, deq_vec[1][1].exception, UInt<1>(0h0)) node _T_2333 = mux(_T_210, deq_vec[2][1].exception, UInt<1>(0h0)) node _T_2334 = mux(_T_211, deq_vec[3][1].exception, UInt<1>(0h0)) node _T_2335 = mux(_T_212, deq_vec[4][1].exception, UInt<1>(0h0)) node _T_2336 = mux(_T_213, deq_vec[5][1].exception, UInt<1>(0h0)) node _T_2337 = mux(_T_214, deq_vec[6][1].exception, UInt<1>(0h0)) node _T_2338 = mux(_T_215, deq_vec[7][1].exception, UInt<1>(0h0)) node _T_2339 = or(_T_2331, _T_2332) node _T_2340 = or(_T_2339, _T_2333) node _T_2341 = or(_T_2340, _T_2334) node _T_2342 = or(_T_2341, _T_2335) node _T_2343 = or(_T_2342, _T_2336) node _T_2344 = or(_T_2343, _T_2337) node _T_2345 = or(_T_2344, _T_2338) wire _WIRE_147 : UInt<1> connect _WIRE_147, _T_2345 connect _WIRE_116.exception, _WIRE_147 node _T_2346 = mux(_T_208, deq_vec[0][1].stale_pdst, UInt<1>(0h0)) node _T_2347 = mux(_T_209, deq_vec[1][1].stale_pdst, UInt<1>(0h0)) node _T_2348 = mux(_T_210, deq_vec[2][1].stale_pdst, UInt<1>(0h0)) node _T_2349 = mux(_T_211, deq_vec[3][1].stale_pdst, UInt<1>(0h0)) node _T_2350 = mux(_T_212, deq_vec[4][1].stale_pdst, UInt<1>(0h0)) node _T_2351 = mux(_T_213, deq_vec[5][1].stale_pdst, UInt<1>(0h0)) node _T_2352 = mux(_T_214, deq_vec[6][1].stale_pdst, UInt<1>(0h0)) node _T_2353 = mux(_T_215, deq_vec[7][1].stale_pdst, UInt<1>(0h0)) node _T_2354 = or(_T_2346, _T_2347) node _T_2355 = or(_T_2354, _T_2348) node _T_2356 = or(_T_2355, _T_2349) node _T_2357 = or(_T_2356, _T_2350) node _T_2358 = or(_T_2357, _T_2351) node _T_2359 = or(_T_2358, _T_2352) node _T_2360 = or(_T_2359, _T_2353) wire _WIRE_148 : UInt<7> connect _WIRE_148, _T_2360 connect _WIRE_116.stale_pdst, _WIRE_148 node _T_2361 = mux(_T_208, deq_vec[0][1].ppred_busy, UInt<1>(0h0)) node _T_2362 = mux(_T_209, deq_vec[1][1].ppred_busy, UInt<1>(0h0)) node _T_2363 = mux(_T_210, deq_vec[2][1].ppred_busy, UInt<1>(0h0)) node _T_2364 = mux(_T_211, deq_vec[3][1].ppred_busy, UInt<1>(0h0)) node _T_2365 = mux(_T_212, deq_vec[4][1].ppred_busy, UInt<1>(0h0)) node _T_2366 = mux(_T_213, deq_vec[5][1].ppred_busy, UInt<1>(0h0)) node _T_2367 = mux(_T_214, deq_vec[6][1].ppred_busy, UInt<1>(0h0)) node _T_2368 = mux(_T_215, deq_vec[7][1].ppred_busy, UInt<1>(0h0)) node _T_2369 = or(_T_2361, _T_2362) node _T_2370 = or(_T_2369, _T_2363) node _T_2371 = or(_T_2370, _T_2364) node _T_2372 = or(_T_2371, _T_2365) node _T_2373 = or(_T_2372, _T_2366) node _T_2374 = or(_T_2373, _T_2367) node _T_2375 = or(_T_2374, _T_2368) wire _WIRE_149 : UInt<1> connect _WIRE_149, _T_2375 connect _WIRE_116.ppred_busy, _WIRE_149 node _T_2376 = mux(_T_208, deq_vec[0][1].prs3_busy, UInt<1>(0h0)) node _T_2377 = mux(_T_209, deq_vec[1][1].prs3_busy, UInt<1>(0h0)) node _T_2378 = mux(_T_210, deq_vec[2][1].prs3_busy, UInt<1>(0h0)) node _T_2379 = mux(_T_211, deq_vec[3][1].prs3_busy, UInt<1>(0h0)) node _T_2380 = mux(_T_212, deq_vec[4][1].prs3_busy, UInt<1>(0h0)) node _T_2381 = mux(_T_213, deq_vec[5][1].prs3_busy, UInt<1>(0h0)) node _T_2382 = mux(_T_214, deq_vec[6][1].prs3_busy, UInt<1>(0h0)) node _T_2383 = mux(_T_215, deq_vec[7][1].prs3_busy, UInt<1>(0h0)) node _T_2384 = or(_T_2376, _T_2377) node _T_2385 = or(_T_2384, _T_2378) node _T_2386 = or(_T_2385, _T_2379) node _T_2387 = or(_T_2386, _T_2380) node _T_2388 = or(_T_2387, _T_2381) node _T_2389 = or(_T_2388, _T_2382) node _T_2390 = or(_T_2389, _T_2383) wire _WIRE_150 : UInt<1> connect _WIRE_150, _T_2390 connect _WIRE_116.prs3_busy, _WIRE_150 node _T_2391 = mux(_T_208, deq_vec[0][1].prs2_busy, UInt<1>(0h0)) node _T_2392 = mux(_T_209, deq_vec[1][1].prs2_busy, UInt<1>(0h0)) node _T_2393 = mux(_T_210, deq_vec[2][1].prs2_busy, UInt<1>(0h0)) node _T_2394 = mux(_T_211, deq_vec[3][1].prs2_busy, UInt<1>(0h0)) node _T_2395 = mux(_T_212, deq_vec[4][1].prs2_busy, UInt<1>(0h0)) node _T_2396 = mux(_T_213, deq_vec[5][1].prs2_busy, UInt<1>(0h0)) node _T_2397 = mux(_T_214, deq_vec[6][1].prs2_busy, UInt<1>(0h0)) node _T_2398 = mux(_T_215, deq_vec[7][1].prs2_busy, UInt<1>(0h0)) node _T_2399 = or(_T_2391, _T_2392) node _T_2400 = or(_T_2399, _T_2393) node _T_2401 = or(_T_2400, _T_2394) node _T_2402 = or(_T_2401, _T_2395) node _T_2403 = or(_T_2402, _T_2396) node _T_2404 = or(_T_2403, _T_2397) node _T_2405 = or(_T_2404, _T_2398) wire _WIRE_151 : UInt<1> connect _WIRE_151, _T_2405 connect _WIRE_116.prs2_busy, _WIRE_151 node _T_2406 = mux(_T_208, deq_vec[0][1].prs1_busy, UInt<1>(0h0)) node _T_2407 = mux(_T_209, deq_vec[1][1].prs1_busy, UInt<1>(0h0)) node _T_2408 = mux(_T_210, deq_vec[2][1].prs1_busy, UInt<1>(0h0)) node _T_2409 = mux(_T_211, deq_vec[3][1].prs1_busy, UInt<1>(0h0)) node _T_2410 = mux(_T_212, deq_vec[4][1].prs1_busy, UInt<1>(0h0)) node _T_2411 = mux(_T_213, deq_vec[5][1].prs1_busy, UInt<1>(0h0)) node _T_2412 = mux(_T_214, deq_vec[6][1].prs1_busy, UInt<1>(0h0)) node _T_2413 = mux(_T_215, deq_vec[7][1].prs1_busy, UInt<1>(0h0)) node _T_2414 = or(_T_2406, _T_2407) node _T_2415 = or(_T_2414, _T_2408) node _T_2416 = or(_T_2415, _T_2409) node _T_2417 = or(_T_2416, _T_2410) node _T_2418 = or(_T_2417, _T_2411) node _T_2419 = or(_T_2418, _T_2412) node _T_2420 = or(_T_2419, _T_2413) wire _WIRE_152 : UInt<1> connect _WIRE_152, _T_2420 connect _WIRE_116.prs1_busy, _WIRE_152 node _T_2421 = mux(_T_208, deq_vec[0][1].ppred, UInt<1>(0h0)) node _T_2422 = mux(_T_209, deq_vec[1][1].ppred, UInt<1>(0h0)) node _T_2423 = mux(_T_210, deq_vec[2][1].ppred, UInt<1>(0h0)) node _T_2424 = mux(_T_211, deq_vec[3][1].ppred, UInt<1>(0h0)) node _T_2425 = mux(_T_212, deq_vec[4][1].ppred, UInt<1>(0h0)) node _T_2426 = mux(_T_213, deq_vec[5][1].ppred, UInt<1>(0h0)) node _T_2427 = mux(_T_214, deq_vec[6][1].ppred, UInt<1>(0h0)) node _T_2428 = mux(_T_215, deq_vec[7][1].ppred, UInt<1>(0h0)) node _T_2429 = or(_T_2421, _T_2422) node _T_2430 = or(_T_2429, _T_2423) node _T_2431 = or(_T_2430, _T_2424) node _T_2432 = or(_T_2431, _T_2425) node _T_2433 = or(_T_2432, _T_2426) node _T_2434 = or(_T_2433, _T_2427) node _T_2435 = or(_T_2434, _T_2428) wire _WIRE_153 : UInt<5> connect _WIRE_153, _T_2435 connect _WIRE_116.ppred, _WIRE_153 node _T_2436 = mux(_T_208, deq_vec[0][1].prs3, UInt<1>(0h0)) node _T_2437 = mux(_T_209, deq_vec[1][1].prs3, UInt<1>(0h0)) node _T_2438 = mux(_T_210, deq_vec[2][1].prs3, UInt<1>(0h0)) node _T_2439 = mux(_T_211, deq_vec[3][1].prs3, UInt<1>(0h0)) node _T_2440 = mux(_T_212, deq_vec[4][1].prs3, UInt<1>(0h0)) node _T_2441 = mux(_T_213, deq_vec[5][1].prs3, UInt<1>(0h0)) node _T_2442 = mux(_T_214, deq_vec[6][1].prs3, UInt<1>(0h0)) node _T_2443 = mux(_T_215, deq_vec[7][1].prs3, UInt<1>(0h0)) node _T_2444 = or(_T_2436, _T_2437) node _T_2445 = or(_T_2444, _T_2438) node _T_2446 = or(_T_2445, _T_2439) node _T_2447 = or(_T_2446, _T_2440) node _T_2448 = or(_T_2447, _T_2441) node _T_2449 = or(_T_2448, _T_2442) node _T_2450 = or(_T_2449, _T_2443) wire _WIRE_154 : UInt<7> connect _WIRE_154, _T_2450 connect _WIRE_116.prs3, _WIRE_154 node _T_2451 = mux(_T_208, deq_vec[0][1].prs2, UInt<1>(0h0)) node _T_2452 = mux(_T_209, deq_vec[1][1].prs2, UInt<1>(0h0)) node _T_2453 = mux(_T_210, deq_vec[2][1].prs2, UInt<1>(0h0)) node _T_2454 = mux(_T_211, deq_vec[3][1].prs2, UInt<1>(0h0)) node _T_2455 = mux(_T_212, deq_vec[4][1].prs2, UInt<1>(0h0)) node _T_2456 = mux(_T_213, deq_vec[5][1].prs2, UInt<1>(0h0)) node _T_2457 = mux(_T_214, deq_vec[6][1].prs2, UInt<1>(0h0)) node _T_2458 = mux(_T_215, deq_vec[7][1].prs2, UInt<1>(0h0)) node _T_2459 = or(_T_2451, _T_2452) node _T_2460 = or(_T_2459, _T_2453) node _T_2461 = or(_T_2460, _T_2454) node _T_2462 = or(_T_2461, _T_2455) node _T_2463 = or(_T_2462, _T_2456) node _T_2464 = or(_T_2463, _T_2457) node _T_2465 = or(_T_2464, _T_2458) wire _WIRE_155 : UInt<7> connect _WIRE_155, _T_2465 connect _WIRE_116.prs2, _WIRE_155 node _T_2466 = mux(_T_208, deq_vec[0][1].prs1, UInt<1>(0h0)) node _T_2467 = mux(_T_209, deq_vec[1][1].prs1, UInt<1>(0h0)) node _T_2468 = mux(_T_210, deq_vec[2][1].prs1, UInt<1>(0h0)) node _T_2469 = mux(_T_211, deq_vec[3][1].prs1, UInt<1>(0h0)) node _T_2470 = mux(_T_212, deq_vec[4][1].prs1, UInt<1>(0h0)) node _T_2471 = mux(_T_213, deq_vec[5][1].prs1, UInt<1>(0h0)) node _T_2472 = mux(_T_214, deq_vec[6][1].prs1, UInt<1>(0h0)) node _T_2473 = mux(_T_215, deq_vec[7][1].prs1, UInt<1>(0h0)) node _T_2474 = or(_T_2466, _T_2467) node _T_2475 = or(_T_2474, _T_2468) node _T_2476 = or(_T_2475, _T_2469) node _T_2477 = or(_T_2476, _T_2470) node _T_2478 = or(_T_2477, _T_2471) node _T_2479 = or(_T_2478, _T_2472) node _T_2480 = or(_T_2479, _T_2473) wire _WIRE_156 : UInt<7> connect _WIRE_156, _T_2480 connect _WIRE_116.prs1, _WIRE_156 node _T_2481 = mux(_T_208, deq_vec[0][1].pdst, UInt<1>(0h0)) node _T_2482 = mux(_T_209, deq_vec[1][1].pdst, UInt<1>(0h0)) node _T_2483 = mux(_T_210, deq_vec[2][1].pdst, UInt<1>(0h0)) node _T_2484 = mux(_T_211, deq_vec[3][1].pdst, UInt<1>(0h0)) node _T_2485 = mux(_T_212, deq_vec[4][1].pdst, UInt<1>(0h0)) node _T_2486 = mux(_T_213, deq_vec[5][1].pdst, UInt<1>(0h0)) node _T_2487 = mux(_T_214, deq_vec[6][1].pdst, UInt<1>(0h0)) node _T_2488 = mux(_T_215, deq_vec[7][1].pdst, UInt<1>(0h0)) node _T_2489 = or(_T_2481, _T_2482) node _T_2490 = or(_T_2489, _T_2483) node _T_2491 = or(_T_2490, _T_2484) node _T_2492 = or(_T_2491, _T_2485) node _T_2493 = or(_T_2492, _T_2486) node _T_2494 = or(_T_2493, _T_2487) node _T_2495 = or(_T_2494, _T_2488) wire _WIRE_157 : UInt<7> connect _WIRE_157, _T_2495 connect _WIRE_116.pdst, _WIRE_157 node _T_2496 = mux(_T_208, deq_vec[0][1].rxq_idx, UInt<1>(0h0)) node _T_2497 = mux(_T_209, deq_vec[1][1].rxq_idx, UInt<1>(0h0)) node _T_2498 = mux(_T_210, deq_vec[2][1].rxq_idx, UInt<1>(0h0)) node _T_2499 = mux(_T_211, deq_vec[3][1].rxq_idx, UInt<1>(0h0)) node _T_2500 = mux(_T_212, deq_vec[4][1].rxq_idx, UInt<1>(0h0)) node _T_2501 = mux(_T_213, deq_vec[5][1].rxq_idx, UInt<1>(0h0)) node _T_2502 = mux(_T_214, deq_vec[6][1].rxq_idx, UInt<1>(0h0)) node _T_2503 = mux(_T_215, deq_vec[7][1].rxq_idx, UInt<1>(0h0)) node _T_2504 = or(_T_2496, _T_2497) node _T_2505 = or(_T_2504, _T_2498) node _T_2506 = or(_T_2505, _T_2499) node _T_2507 = or(_T_2506, _T_2500) node _T_2508 = or(_T_2507, _T_2501) node _T_2509 = or(_T_2508, _T_2502) node _T_2510 = or(_T_2509, _T_2503) wire _WIRE_158 : UInt<2> connect _WIRE_158, _T_2510 connect _WIRE_116.rxq_idx, _WIRE_158 node _T_2511 = mux(_T_208, deq_vec[0][1].stq_idx, UInt<1>(0h0)) node _T_2512 = mux(_T_209, deq_vec[1][1].stq_idx, UInt<1>(0h0)) node _T_2513 = mux(_T_210, deq_vec[2][1].stq_idx, UInt<1>(0h0)) node _T_2514 = mux(_T_211, deq_vec[3][1].stq_idx, UInt<1>(0h0)) node _T_2515 = mux(_T_212, deq_vec[4][1].stq_idx, UInt<1>(0h0)) node _T_2516 = mux(_T_213, deq_vec[5][1].stq_idx, UInt<1>(0h0)) node _T_2517 = mux(_T_214, deq_vec[6][1].stq_idx, UInt<1>(0h0)) node _T_2518 = mux(_T_215, deq_vec[7][1].stq_idx, UInt<1>(0h0)) node _T_2519 = or(_T_2511, _T_2512) node _T_2520 = or(_T_2519, _T_2513) node _T_2521 = or(_T_2520, _T_2514) node _T_2522 = or(_T_2521, _T_2515) node _T_2523 = or(_T_2522, _T_2516) node _T_2524 = or(_T_2523, _T_2517) node _T_2525 = or(_T_2524, _T_2518) wire _WIRE_159 : UInt<4> connect _WIRE_159, _T_2525 connect _WIRE_116.stq_idx, _WIRE_159 node _T_2526 = mux(_T_208, deq_vec[0][1].ldq_idx, UInt<1>(0h0)) node _T_2527 = mux(_T_209, deq_vec[1][1].ldq_idx, UInt<1>(0h0)) node _T_2528 = mux(_T_210, deq_vec[2][1].ldq_idx, UInt<1>(0h0)) node _T_2529 = mux(_T_211, deq_vec[3][1].ldq_idx, UInt<1>(0h0)) node _T_2530 = mux(_T_212, deq_vec[4][1].ldq_idx, UInt<1>(0h0)) node _T_2531 = mux(_T_213, deq_vec[5][1].ldq_idx, UInt<1>(0h0)) node _T_2532 = mux(_T_214, deq_vec[6][1].ldq_idx, UInt<1>(0h0)) node _T_2533 = mux(_T_215, deq_vec[7][1].ldq_idx, UInt<1>(0h0)) node _T_2534 = or(_T_2526, _T_2527) node _T_2535 = or(_T_2534, _T_2528) node _T_2536 = or(_T_2535, _T_2529) node _T_2537 = or(_T_2536, _T_2530) node _T_2538 = or(_T_2537, _T_2531) node _T_2539 = or(_T_2538, _T_2532) node _T_2540 = or(_T_2539, _T_2533) wire _WIRE_160 : UInt<4> connect _WIRE_160, _T_2540 connect _WIRE_116.ldq_idx, _WIRE_160 node _T_2541 = mux(_T_208, deq_vec[0][1].rob_idx, UInt<1>(0h0)) node _T_2542 = mux(_T_209, deq_vec[1][1].rob_idx, UInt<1>(0h0)) node _T_2543 = mux(_T_210, deq_vec[2][1].rob_idx, UInt<1>(0h0)) node _T_2544 = mux(_T_211, deq_vec[3][1].rob_idx, UInt<1>(0h0)) node _T_2545 = mux(_T_212, deq_vec[4][1].rob_idx, UInt<1>(0h0)) node _T_2546 = mux(_T_213, deq_vec[5][1].rob_idx, UInt<1>(0h0)) node _T_2547 = mux(_T_214, deq_vec[6][1].rob_idx, UInt<1>(0h0)) node _T_2548 = mux(_T_215, deq_vec[7][1].rob_idx, UInt<1>(0h0)) node _T_2549 = or(_T_2541, _T_2542) node _T_2550 = or(_T_2549, _T_2543) node _T_2551 = or(_T_2550, _T_2544) node _T_2552 = or(_T_2551, _T_2545) node _T_2553 = or(_T_2552, _T_2546) node _T_2554 = or(_T_2553, _T_2547) node _T_2555 = or(_T_2554, _T_2548) wire _WIRE_161 : UInt<6> connect _WIRE_161, _T_2555 connect _WIRE_116.rob_idx, _WIRE_161 wire _WIRE_162 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _T_2556 = mux(_T_208, deq_vec[0][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2557 = mux(_T_209, deq_vec[1][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2558 = mux(_T_210, deq_vec[2][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2559 = mux(_T_211, deq_vec[3][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2560 = mux(_T_212, deq_vec[4][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2561 = mux(_T_213, deq_vec[5][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2562 = mux(_T_214, deq_vec[6][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2563 = mux(_T_215, deq_vec[7][1].fp_ctrl.vec, UInt<1>(0h0)) node _T_2564 = or(_T_2556, _T_2557) node _T_2565 = or(_T_2564, _T_2558) node _T_2566 = or(_T_2565, _T_2559) node _T_2567 = or(_T_2566, _T_2560) node _T_2568 = or(_T_2567, _T_2561) node _T_2569 = or(_T_2568, _T_2562) node _T_2570 = or(_T_2569, _T_2563) wire _WIRE_163 : UInt<1> connect _WIRE_163, _T_2570 connect _WIRE_162.vec, _WIRE_163 node _T_2571 = mux(_T_208, deq_vec[0][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2572 = mux(_T_209, deq_vec[1][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2573 = mux(_T_210, deq_vec[2][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2574 = mux(_T_211, deq_vec[3][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2575 = mux(_T_212, deq_vec[4][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2576 = mux(_T_213, deq_vec[5][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2577 = mux(_T_214, deq_vec[6][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2578 = mux(_T_215, deq_vec[7][1].fp_ctrl.wflags, UInt<1>(0h0)) node _T_2579 = or(_T_2571, _T_2572) node _T_2580 = or(_T_2579, _T_2573) node _T_2581 = or(_T_2580, _T_2574) node _T_2582 = or(_T_2581, _T_2575) node _T_2583 = or(_T_2582, _T_2576) node _T_2584 = or(_T_2583, _T_2577) node _T_2585 = or(_T_2584, _T_2578) wire _WIRE_164 : UInt<1> connect _WIRE_164, _T_2585 connect _WIRE_162.wflags, _WIRE_164 node _T_2586 = mux(_T_208, deq_vec[0][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2587 = mux(_T_209, deq_vec[1][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2588 = mux(_T_210, deq_vec[2][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2589 = mux(_T_211, deq_vec[3][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2590 = mux(_T_212, deq_vec[4][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2591 = mux(_T_213, deq_vec[5][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2592 = mux(_T_214, deq_vec[6][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2593 = mux(_T_215, deq_vec[7][1].fp_ctrl.sqrt, UInt<1>(0h0)) node _T_2594 = or(_T_2586, _T_2587) node _T_2595 = or(_T_2594, _T_2588) node _T_2596 = or(_T_2595, _T_2589) node _T_2597 = or(_T_2596, _T_2590) node _T_2598 = or(_T_2597, _T_2591) node _T_2599 = or(_T_2598, _T_2592) node _T_2600 = or(_T_2599, _T_2593) wire _WIRE_165 : UInt<1> connect _WIRE_165, _T_2600 connect _WIRE_162.sqrt, _WIRE_165 node _T_2601 = mux(_T_208, deq_vec[0][1].fp_ctrl.div, UInt<1>(0h0)) node _T_2602 = mux(_T_209, deq_vec[1][1].fp_ctrl.div, UInt<1>(0h0)) node _T_2603 = mux(_T_210, deq_vec[2][1].fp_ctrl.div, UInt<1>(0h0)) node _T_2604 = mux(_T_211, deq_vec[3][1].fp_ctrl.div, UInt<1>(0h0)) node _T_2605 = mux(_T_212, deq_vec[4][1].fp_ctrl.div, UInt<1>(0h0)) node _T_2606 = mux(_T_213, deq_vec[5][1].fp_ctrl.div, UInt<1>(0h0)) node _T_2607 = mux(_T_214, deq_vec[6][1].fp_ctrl.div, UInt<1>(0h0)) node _T_2608 = mux(_T_215, deq_vec[7][1].fp_ctrl.div, UInt<1>(0h0)) node _T_2609 = or(_T_2601, _T_2602) node _T_2610 = or(_T_2609, _T_2603) node _T_2611 = or(_T_2610, _T_2604) node _T_2612 = or(_T_2611, _T_2605) node _T_2613 = or(_T_2612, _T_2606) node _T_2614 = or(_T_2613, _T_2607) node _T_2615 = or(_T_2614, _T_2608) wire _WIRE_166 : UInt<1> connect _WIRE_166, _T_2615 connect _WIRE_162.div, _WIRE_166 node _T_2616 = mux(_T_208, deq_vec[0][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_2617 = mux(_T_209, deq_vec[1][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_2618 = mux(_T_210, deq_vec[2][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_2619 = mux(_T_211, deq_vec[3][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_2620 = mux(_T_212, deq_vec[4][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_2621 = mux(_T_213, deq_vec[5][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_2622 = mux(_T_214, deq_vec[6][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_2623 = mux(_T_215, deq_vec[7][1].fp_ctrl.fma, UInt<1>(0h0)) node _T_2624 = or(_T_2616, _T_2617) node _T_2625 = or(_T_2624, _T_2618) node _T_2626 = or(_T_2625, _T_2619) node _T_2627 = or(_T_2626, _T_2620) node _T_2628 = or(_T_2627, _T_2621) node _T_2629 = or(_T_2628, _T_2622) node _T_2630 = or(_T_2629, _T_2623) wire _WIRE_167 : UInt<1> connect _WIRE_167, _T_2630 connect _WIRE_162.fma, _WIRE_167 node _T_2631 = mux(_T_208, deq_vec[0][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_2632 = mux(_T_209, deq_vec[1][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_2633 = mux(_T_210, deq_vec[2][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_2634 = mux(_T_211, deq_vec[3][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_2635 = mux(_T_212, deq_vec[4][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_2636 = mux(_T_213, deq_vec[5][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_2637 = mux(_T_214, deq_vec[6][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_2638 = mux(_T_215, deq_vec[7][1].fp_ctrl.fastpipe, UInt<1>(0h0)) node _T_2639 = or(_T_2631, _T_2632) node _T_2640 = or(_T_2639, _T_2633) node _T_2641 = or(_T_2640, _T_2634) node _T_2642 = or(_T_2641, _T_2635) node _T_2643 = or(_T_2642, _T_2636) node _T_2644 = or(_T_2643, _T_2637) node _T_2645 = or(_T_2644, _T_2638) wire _WIRE_168 : UInt<1> connect _WIRE_168, _T_2645 connect _WIRE_162.fastpipe, _WIRE_168 node _T_2646 = mux(_T_208, deq_vec[0][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_2647 = mux(_T_209, deq_vec[1][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_2648 = mux(_T_210, deq_vec[2][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_2649 = mux(_T_211, deq_vec[3][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_2650 = mux(_T_212, deq_vec[4][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_2651 = mux(_T_213, deq_vec[5][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_2652 = mux(_T_214, deq_vec[6][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_2653 = mux(_T_215, deq_vec[7][1].fp_ctrl.toint, UInt<1>(0h0)) node _T_2654 = or(_T_2646, _T_2647) node _T_2655 = or(_T_2654, _T_2648) node _T_2656 = or(_T_2655, _T_2649) node _T_2657 = or(_T_2656, _T_2650) node _T_2658 = or(_T_2657, _T_2651) node _T_2659 = or(_T_2658, _T_2652) node _T_2660 = or(_T_2659, _T_2653) wire _WIRE_169 : UInt<1> connect _WIRE_169, _T_2660 connect _WIRE_162.toint, _WIRE_169 node _T_2661 = mux(_T_208, deq_vec[0][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_2662 = mux(_T_209, deq_vec[1][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_2663 = mux(_T_210, deq_vec[2][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_2664 = mux(_T_211, deq_vec[3][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_2665 = mux(_T_212, deq_vec[4][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_2666 = mux(_T_213, deq_vec[5][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_2667 = mux(_T_214, deq_vec[6][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_2668 = mux(_T_215, deq_vec[7][1].fp_ctrl.fromint, UInt<1>(0h0)) node _T_2669 = or(_T_2661, _T_2662) node _T_2670 = or(_T_2669, _T_2663) node _T_2671 = or(_T_2670, _T_2664) node _T_2672 = or(_T_2671, _T_2665) node _T_2673 = or(_T_2672, _T_2666) node _T_2674 = or(_T_2673, _T_2667) node _T_2675 = or(_T_2674, _T_2668) wire _WIRE_170 : UInt<1> connect _WIRE_170, _T_2675 connect _WIRE_162.fromint, _WIRE_170 node _T_2676 = mux(_T_208, deq_vec[0][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_2677 = mux(_T_209, deq_vec[1][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_2678 = mux(_T_210, deq_vec[2][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_2679 = mux(_T_211, deq_vec[3][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_2680 = mux(_T_212, deq_vec[4][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_2681 = mux(_T_213, deq_vec[5][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_2682 = mux(_T_214, deq_vec[6][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_2683 = mux(_T_215, deq_vec[7][1].fp_ctrl.typeTagOut, UInt<1>(0h0)) node _T_2684 = or(_T_2676, _T_2677) node _T_2685 = or(_T_2684, _T_2678) node _T_2686 = or(_T_2685, _T_2679) node _T_2687 = or(_T_2686, _T_2680) node _T_2688 = or(_T_2687, _T_2681) node _T_2689 = or(_T_2688, _T_2682) node _T_2690 = or(_T_2689, _T_2683) wire _WIRE_171 : UInt<2> connect _WIRE_171, _T_2690 connect _WIRE_162.typeTagOut, _WIRE_171 node _T_2691 = mux(_T_208, deq_vec[0][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_2692 = mux(_T_209, deq_vec[1][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_2693 = mux(_T_210, deq_vec[2][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_2694 = mux(_T_211, deq_vec[3][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_2695 = mux(_T_212, deq_vec[4][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_2696 = mux(_T_213, deq_vec[5][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_2697 = mux(_T_214, deq_vec[6][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_2698 = mux(_T_215, deq_vec[7][1].fp_ctrl.typeTagIn, UInt<1>(0h0)) node _T_2699 = or(_T_2691, _T_2692) node _T_2700 = or(_T_2699, _T_2693) node _T_2701 = or(_T_2700, _T_2694) node _T_2702 = or(_T_2701, _T_2695) node _T_2703 = or(_T_2702, _T_2696) node _T_2704 = or(_T_2703, _T_2697) node _T_2705 = or(_T_2704, _T_2698) wire _WIRE_172 : UInt<2> connect _WIRE_172, _T_2705 connect _WIRE_162.typeTagIn, _WIRE_172 node _T_2706 = mux(_T_208, deq_vec[0][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_2707 = mux(_T_209, deq_vec[1][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_2708 = mux(_T_210, deq_vec[2][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_2709 = mux(_T_211, deq_vec[3][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_2710 = mux(_T_212, deq_vec[4][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_2711 = mux(_T_213, deq_vec[5][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_2712 = mux(_T_214, deq_vec[6][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_2713 = mux(_T_215, deq_vec[7][1].fp_ctrl.swap23, UInt<1>(0h0)) node _T_2714 = or(_T_2706, _T_2707) node _T_2715 = or(_T_2714, _T_2708) node _T_2716 = or(_T_2715, _T_2709) node _T_2717 = or(_T_2716, _T_2710) node _T_2718 = or(_T_2717, _T_2711) node _T_2719 = or(_T_2718, _T_2712) node _T_2720 = or(_T_2719, _T_2713) wire _WIRE_173 : UInt<1> connect _WIRE_173, _T_2720 connect _WIRE_162.swap23, _WIRE_173 node _T_2721 = mux(_T_208, deq_vec[0][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_2722 = mux(_T_209, deq_vec[1][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_2723 = mux(_T_210, deq_vec[2][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_2724 = mux(_T_211, deq_vec[3][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_2725 = mux(_T_212, deq_vec[4][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_2726 = mux(_T_213, deq_vec[5][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_2727 = mux(_T_214, deq_vec[6][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_2728 = mux(_T_215, deq_vec[7][1].fp_ctrl.swap12, UInt<1>(0h0)) node _T_2729 = or(_T_2721, _T_2722) node _T_2730 = or(_T_2729, _T_2723) node _T_2731 = or(_T_2730, _T_2724) node _T_2732 = or(_T_2731, _T_2725) node _T_2733 = or(_T_2732, _T_2726) node _T_2734 = or(_T_2733, _T_2727) node _T_2735 = or(_T_2734, _T_2728) wire _WIRE_174 : UInt<1> connect _WIRE_174, _T_2735 connect _WIRE_162.swap12, _WIRE_174 node _T_2736 = mux(_T_208, deq_vec[0][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_2737 = mux(_T_209, deq_vec[1][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_2738 = mux(_T_210, deq_vec[2][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_2739 = mux(_T_211, deq_vec[3][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_2740 = mux(_T_212, deq_vec[4][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_2741 = mux(_T_213, deq_vec[5][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_2742 = mux(_T_214, deq_vec[6][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_2743 = mux(_T_215, deq_vec[7][1].fp_ctrl.ren3, UInt<1>(0h0)) node _T_2744 = or(_T_2736, _T_2737) node _T_2745 = or(_T_2744, _T_2738) node _T_2746 = or(_T_2745, _T_2739) node _T_2747 = or(_T_2746, _T_2740) node _T_2748 = or(_T_2747, _T_2741) node _T_2749 = or(_T_2748, _T_2742) node _T_2750 = or(_T_2749, _T_2743) wire _WIRE_175 : UInt<1> connect _WIRE_175, _T_2750 connect _WIRE_162.ren3, _WIRE_175 node _T_2751 = mux(_T_208, deq_vec[0][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_2752 = mux(_T_209, deq_vec[1][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_2753 = mux(_T_210, deq_vec[2][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_2754 = mux(_T_211, deq_vec[3][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_2755 = mux(_T_212, deq_vec[4][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_2756 = mux(_T_213, deq_vec[5][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_2757 = mux(_T_214, deq_vec[6][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_2758 = mux(_T_215, deq_vec[7][1].fp_ctrl.ren2, UInt<1>(0h0)) node _T_2759 = or(_T_2751, _T_2752) node _T_2760 = or(_T_2759, _T_2753) node _T_2761 = or(_T_2760, _T_2754) node _T_2762 = or(_T_2761, _T_2755) node _T_2763 = or(_T_2762, _T_2756) node _T_2764 = or(_T_2763, _T_2757) node _T_2765 = or(_T_2764, _T_2758) wire _WIRE_176 : UInt<1> connect _WIRE_176, _T_2765 connect _WIRE_162.ren2, _WIRE_176 node _T_2766 = mux(_T_208, deq_vec[0][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_2767 = mux(_T_209, deq_vec[1][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_2768 = mux(_T_210, deq_vec[2][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_2769 = mux(_T_211, deq_vec[3][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_2770 = mux(_T_212, deq_vec[4][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_2771 = mux(_T_213, deq_vec[5][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_2772 = mux(_T_214, deq_vec[6][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_2773 = mux(_T_215, deq_vec[7][1].fp_ctrl.ren1, UInt<1>(0h0)) node _T_2774 = or(_T_2766, _T_2767) node _T_2775 = or(_T_2774, _T_2768) node _T_2776 = or(_T_2775, _T_2769) node _T_2777 = or(_T_2776, _T_2770) node _T_2778 = or(_T_2777, _T_2771) node _T_2779 = or(_T_2778, _T_2772) node _T_2780 = or(_T_2779, _T_2773) wire _WIRE_177 : UInt<1> connect _WIRE_177, _T_2780 connect _WIRE_162.ren1, _WIRE_177 node _T_2781 = mux(_T_208, deq_vec[0][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_2782 = mux(_T_209, deq_vec[1][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_2783 = mux(_T_210, deq_vec[2][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_2784 = mux(_T_211, deq_vec[3][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_2785 = mux(_T_212, deq_vec[4][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_2786 = mux(_T_213, deq_vec[5][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_2787 = mux(_T_214, deq_vec[6][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_2788 = mux(_T_215, deq_vec[7][1].fp_ctrl.wen, UInt<1>(0h0)) node _T_2789 = or(_T_2781, _T_2782) node _T_2790 = or(_T_2789, _T_2783) node _T_2791 = or(_T_2790, _T_2784) node _T_2792 = or(_T_2791, _T_2785) node _T_2793 = or(_T_2792, _T_2786) node _T_2794 = or(_T_2793, _T_2787) node _T_2795 = or(_T_2794, _T_2788) wire _WIRE_178 : UInt<1> connect _WIRE_178, _T_2795 connect _WIRE_162.wen, _WIRE_178 node _T_2796 = mux(_T_208, deq_vec[0][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_2797 = mux(_T_209, deq_vec[1][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_2798 = mux(_T_210, deq_vec[2][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_2799 = mux(_T_211, deq_vec[3][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_2800 = mux(_T_212, deq_vec[4][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_2801 = mux(_T_213, deq_vec[5][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_2802 = mux(_T_214, deq_vec[6][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_2803 = mux(_T_215, deq_vec[7][1].fp_ctrl.ldst, UInt<1>(0h0)) node _T_2804 = or(_T_2796, _T_2797) node _T_2805 = or(_T_2804, _T_2798) node _T_2806 = or(_T_2805, _T_2799) node _T_2807 = or(_T_2806, _T_2800) node _T_2808 = or(_T_2807, _T_2801) node _T_2809 = or(_T_2808, _T_2802) node _T_2810 = or(_T_2809, _T_2803) wire _WIRE_179 : UInt<1> connect _WIRE_179, _T_2810 connect _WIRE_162.ldst, _WIRE_179 connect _WIRE_116.fp_ctrl, _WIRE_162 node _T_2811 = mux(_T_208, deq_vec[0][1].op2_sel, UInt<1>(0h0)) node _T_2812 = mux(_T_209, deq_vec[1][1].op2_sel, UInt<1>(0h0)) node _T_2813 = mux(_T_210, deq_vec[2][1].op2_sel, UInt<1>(0h0)) node _T_2814 = mux(_T_211, deq_vec[3][1].op2_sel, UInt<1>(0h0)) node _T_2815 = mux(_T_212, deq_vec[4][1].op2_sel, UInt<1>(0h0)) node _T_2816 = mux(_T_213, deq_vec[5][1].op2_sel, UInt<1>(0h0)) node _T_2817 = mux(_T_214, deq_vec[6][1].op2_sel, UInt<1>(0h0)) node _T_2818 = mux(_T_215, deq_vec[7][1].op2_sel, UInt<1>(0h0)) node _T_2819 = or(_T_2811, _T_2812) node _T_2820 = or(_T_2819, _T_2813) node _T_2821 = or(_T_2820, _T_2814) node _T_2822 = or(_T_2821, _T_2815) node _T_2823 = or(_T_2822, _T_2816) node _T_2824 = or(_T_2823, _T_2817) node _T_2825 = or(_T_2824, _T_2818) wire _WIRE_180 : UInt<3> connect _WIRE_180, _T_2825 connect _WIRE_116.op2_sel, _WIRE_180 node _T_2826 = mux(_T_208, deq_vec[0][1].op1_sel, UInt<1>(0h0)) node _T_2827 = mux(_T_209, deq_vec[1][1].op1_sel, UInt<1>(0h0)) node _T_2828 = mux(_T_210, deq_vec[2][1].op1_sel, UInt<1>(0h0)) node _T_2829 = mux(_T_211, deq_vec[3][1].op1_sel, UInt<1>(0h0)) node _T_2830 = mux(_T_212, deq_vec[4][1].op1_sel, UInt<1>(0h0)) node _T_2831 = mux(_T_213, deq_vec[5][1].op1_sel, UInt<1>(0h0)) node _T_2832 = mux(_T_214, deq_vec[6][1].op1_sel, UInt<1>(0h0)) node _T_2833 = mux(_T_215, deq_vec[7][1].op1_sel, UInt<1>(0h0)) node _T_2834 = or(_T_2826, _T_2827) node _T_2835 = or(_T_2834, _T_2828) node _T_2836 = or(_T_2835, _T_2829) node _T_2837 = or(_T_2836, _T_2830) node _T_2838 = or(_T_2837, _T_2831) node _T_2839 = or(_T_2838, _T_2832) node _T_2840 = or(_T_2839, _T_2833) wire _WIRE_181 : UInt<2> connect _WIRE_181, _T_2840 connect _WIRE_116.op1_sel, _WIRE_181 node _T_2841 = mux(_T_208, deq_vec[0][1].imm_packed, UInt<1>(0h0)) node _T_2842 = mux(_T_209, deq_vec[1][1].imm_packed, UInt<1>(0h0)) node _T_2843 = mux(_T_210, deq_vec[2][1].imm_packed, UInt<1>(0h0)) node _T_2844 = mux(_T_211, deq_vec[3][1].imm_packed, UInt<1>(0h0)) node _T_2845 = mux(_T_212, deq_vec[4][1].imm_packed, UInt<1>(0h0)) node _T_2846 = mux(_T_213, deq_vec[5][1].imm_packed, UInt<1>(0h0)) node _T_2847 = mux(_T_214, deq_vec[6][1].imm_packed, UInt<1>(0h0)) node _T_2848 = mux(_T_215, deq_vec[7][1].imm_packed, UInt<1>(0h0)) node _T_2849 = or(_T_2841, _T_2842) node _T_2850 = or(_T_2849, _T_2843) node _T_2851 = or(_T_2850, _T_2844) node _T_2852 = or(_T_2851, _T_2845) node _T_2853 = or(_T_2852, _T_2846) node _T_2854 = or(_T_2853, _T_2847) node _T_2855 = or(_T_2854, _T_2848) wire _WIRE_182 : UInt<20> connect _WIRE_182, _T_2855 connect _WIRE_116.imm_packed, _WIRE_182 node _T_2856 = mux(_T_208, deq_vec[0][1].pimm, UInt<1>(0h0)) node _T_2857 = mux(_T_209, deq_vec[1][1].pimm, UInt<1>(0h0)) node _T_2858 = mux(_T_210, deq_vec[2][1].pimm, UInt<1>(0h0)) node _T_2859 = mux(_T_211, deq_vec[3][1].pimm, UInt<1>(0h0)) node _T_2860 = mux(_T_212, deq_vec[4][1].pimm, UInt<1>(0h0)) node _T_2861 = mux(_T_213, deq_vec[5][1].pimm, UInt<1>(0h0)) node _T_2862 = mux(_T_214, deq_vec[6][1].pimm, UInt<1>(0h0)) node _T_2863 = mux(_T_215, deq_vec[7][1].pimm, UInt<1>(0h0)) node _T_2864 = or(_T_2856, _T_2857) node _T_2865 = or(_T_2864, _T_2858) node _T_2866 = or(_T_2865, _T_2859) node _T_2867 = or(_T_2866, _T_2860) node _T_2868 = or(_T_2867, _T_2861) node _T_2869 = or(_T_2868, _T_2862) node _T_2870 = or(_T_2869, _T_2863) wire _WIRE_183 : UInt<5> connect _WIRE_183, _T_2870 connect _WIRE_116.pimm, _WIRE_183 node _T_2871 = mux(_T_208, deq_vec[0][1].imm_sel, UInt<1>(0h0)) node _T_2872 = mux(_T_209, deq_vec[1][1].imm_sel, UInt<1>(0h0)) node _T_2873 = mux(_T_210, deq_vec[2][1].imm_sel, UInt<1>(0h0)) node _T_2874 = mux(_T_211, deq_vec[3][1].imm_sel, UInt<1>(0h0)) node _T_2875 = mux(_T_212, deq_vec[4][1].imm_sel, UInt<1>(0h0)) node _T_2876 = mux(_T_213, deq_vec[5][1].imm_sel, UInt<1>(0h0)) node _T_2877 = mux(_T_214, deq_vec[6][1].imm_sel, UInt<1>(0h0)) node _T_2878 = mux(_T_215, deq_vec[7][1].imm_sel, UInt<1>(0h0)) node _T_2879 = or(_T_2871, _T_2872) node _T_2880 = or(_T_2879, _T_2873) node _T_2881 = or(_T_2880, _T_2874) node _T_2882 = or(_T_2881, _T_2875) node _T_2883 = or(_T_2882, _T_2876) node _T_2884 = or(_T_2883, _T_2877) node _T_2885 = or(_T_2884, _T_2878) wire _WIRE_184 : UInt<3> connect _WIRE_184, _T_2885 connect _WIRE_116.imm_sel, _WIRE_184 node _T_2886 = mux(_T_208, deq_vec[0][1].imm_rename, UInt<1>(0h0)) node _T_2887 = mux(_T_209, deq_vec[1][1].imm_rename, UInt<1>(0h0)) node _T_2888 = mux(_T_210, deq_vec[2][1].imm_rename, UInt<1>(0h0)) node _T_2889 = mux(_T_211, deq_vec[3][1].imm_rename, UInt<1>(0h0)) node _T_2890 = mux(_T_212, deq_vec[4][1].imm_rename, UInt<1>(0h0)) node _T_2891 = mux(_T_213, deq_vec[5][1].imm_rename, UInt<1>(0h0)) node _T_2892 = mux(_T_214, deq_vec[6][1].imm_rename, UInt<1>(0h0)) node _T_2893 = mux(_T_215, deq_vec[7][1].imm_rename, UInt<1>(0h0)) node _T_2894 = or(_T_2886, _T_2887) node _T_2895 = or(_T_2894, _T_2888) node _T_2896 = or(_T_2895, _T_2889) node _T_2897 = or(_T_2896, _T_2890) node _T_2898 = or(_T_2897, _T_2891) node _T_2899 = or(_T_2898, _T_2892) node _T_2900 = or(_T_2899, _T_2893) wire _WIRE_185 : UInt<1> connect _WIRE_185, _T_2900 connect _WIRE_116.imm_rename, _WIRE_185 node _T_2901 = mux(_T_208, deq_vec[0][1].taken, UInt<1>(0h0)) node _T_2902 = mux(_T_209, deq_vec[1][1].taken, UInt<1>(0h0)) node _T_2903 = mux(_T_210, deq_vec[2][1].taken, UInt<1>(0h0)) node _T_2904 = mux(_T_211, deq_vec[3][1].taken, UInt<1>(0h0)) node _T_2905 = mux(_T_212, deq_vec[4][1].taken, UInt<1>(0h0)) node _T_2906 = mux(_T_213, deq_vec[5][1].taken, UInt<1>(0h0)) node _T_2907 = mux(_T_214, deq_vec[6][1].taken, UInt<1>(0h0)) node _T_2908 = mux(_T_215, deq_vec[7][1].taken, UInt<1>(0h0)) node _T_2909 = or(_T_2901, _T_2902) node _T_2910 = or(_T_2909, _T_2903) node _T_2911 = or(_T_2910, _T_2904) node _T_2912 = or(_T_2911, _T_2905) node _T_2913 = or(_T_2912, _T_2906) node _T_2914 = or(_T_2913, _T_2907) node _T_2915 = or(_T_2914, _T_2908) wire _WIRE_186 : UInt<1> connect _WIRE_186, _T_2915 connect _WIRE_116.taken, _WIRE_186 node _T_2916 = mux(_T_208, deq_vec[0][1].pc_lob, UInt<1>(0h0)) node _T_2917 = mux(_T_209, deq_vec[1][1].pc_lob, UInt<1>(0h0)) node _T_2918 = mux(_T_210, deq_vec[2][1].pc_lob, UInt<1>(0h0)) node _T_2919 = mux(_T_211, deq_vec[3][1].pc_lob, UInt<1>(0h0)) node _T_2920 = mux(_T_212, deq_vec[4][1].pc_lob, UInt<1>(0h0)) node _T_2921 = mux(_T_213, deq_vec[5][1].pc_lob, UInt<1>(0h0)) node _T_2922 = mux(_T_214, deq_vec[6][1].pc_lob, UInt<1>(0h0)) node _T_2923 = mux(_T_215, deq_vec[7][1].pc_lob, UInt<1>(0h0)) node _T_2924 = or(_T_2916, _T_2917) node _T_2925 = or(_T_2924, _T_2918) node _T_2926 = or(_T_2925, _T_2919) node _T_2927 = or(_T_2926, _T_2920) node _T_2928 = or(_T_2927, _T_2921) node _T_2929 = or(_T_2928, _T_2922) node _T_2930 = or(_T_2929, _T_2923) wire _WIRE_187 : UInt<6> connect _WIRE_187, _T_2930 connect _WIRE_116.pc_lob, _WIRE_187 node _T_2931 = mux(_T_208, deq_vec[0][1].edge_inst, UInt<1>(0h0)) node _T_2932 = mux(_T_209, deq_vec[1][1].edge_inst, UInt<1>(0h0)) node _T_2933 = mux(_T_210, deq_vec[2][1].edge_inst, UInt<1>(0h0)) node _T_2934 = mux(_T_211, deq_vec[3][1].edge_inst, UInt<1>(0h0)) node _T_2935 = mux(_T_212, deq_vec[4][1].edge_inst, UInt<1>(0h0)) node _T_2936 = mux(_T_213, deq_vec[5][1].edge_inst, UInt<1>(0h0)) node _T_2937 = mux(_T_214, deq_vec[6][1].edge_inst, UInt<1>(0h0)) node _T_2938 = mux(_T_215, deq_vec[7][1].edge_inst, UInt<1>(0h0)) node _T_2939 = or(_T_2931, _T_2932) node _T_2940 = or(_T_2939, _T_2933) node _T_2941 = or(_T_2940, _T_2934) node _T_2942 = or(_T_2941, _T_2935) node _T_2943 = or(_T_2942, _T_2936) node _T_2944 = or(_T_2943, _T_2937) node _T_2945 = or(_T_2944, _T_2938) wire _WIRE_188 : UInt<1> connect _WIRE_188, _T_2945 connect _WIRE_116.edge_inst, _WIRE_188 node _T_2946 = mux(_T_208, deq_vec[0][1].ftq_idx, UInt<1>(0h0)) node _T_2947 = mux(_T_209, deq_vec[1][1].ftq_idx, UInt<1>(0h0)) node _T_2948 = mux(_T_210, deq_vec[2][1].ftq_idx, UInt<1>(0h0)) node _T_2949 = mux(_T_211, deq_vec[3][1].ftq_idx, UInt<1>(0h0)) node _T_2950 = mux(_T_212, deq_vec[4][1].ftq_idx, UInt<1>(0h0)) node _T_2951 = mux(_T_213, deq_vec[5][1].ftq_idx, UInt<1>(0h0)) node _T_2952 = mux(_T_214, deq_vec[6][1].ftq_idx, UInt<1>(0h0)) node _T_2953 = mux(_T_215, deq_vec[7][1].ftq_idx, UInt<1>(0h0)) node _T_2954 = or(_T_2946, _T_2947) node _T_2955 = or(_T_2954, _T_2948) node _T_2956 = or(_T_2955, _T_2949) node _T_2957 = or(_T_2956, _T_2950) node _T_2958 = or(_T_2957, _T_2951) node _T_2959 = or(_T_2958, _T_2952) node _T_2960 = or(_T_2959, _T_2953) wire _WIRE_189 : UInt<5> connect _WIRE_189, _T_2960 connect _WIRE_116.ftq_idx, _WIRE_189 node _T_2961 = mux(_T_208, deq_vec[0][1].is_mov, UInt<1>(0h0)) node _T_2962 = mux(_T_209, deq_vec[1][1].is_mov, UInt<1>(0h0)) node _T_2963 = mux(_T_210, deq_vec[2][1].is_mov, UInt<1>(0h0)) node _T_2964 = mux(_T_211, deq_vec[3][1].is_mov, UInt<1>(0h0)) node _T_2965 = mux(_T_212, deq_vec[4][1].is_mov, UInt<1>(0h0)) node _T_2966 = mux(_T_213, deq_vec[5][1].is_mov, UInt<1>(0h0)) node _T_2967 = mux(_T_214, deq_vec[6][1].is_mov, UInt<1>(0h0)) node _T_2968 = mux(_T_215, deq_vec[7][1].is_mov, UInt<1>(0h0)) node _T_2969 = or(_T_2961, _T_2962) node _T_2970 = or(_T_2969, _T_2963) node _T_2971 = or(_T_2970, _T_2964) node _T_2972 = or(_T_2971, _T_2965) node _T_2973 = or(_T_2972, _T_2966) node _T_2974 = or(_T_2973, _T_2967) node _T_2975 = or(_T_2974, _T_2968) wire _WIRE_190 : UInt<1> connect _WIRE_190, _T_2975 connect _WIRE_116.is_mov, _WIRE_190 node _T_2976 = mux(_T_208, deq_vec[0][1].is_rocc, UInt<1>(0h0)) node _T_2977 = mux(_T_209, deq_vec[1][1].is_rocc, UInt<1>(0h0)) node _T_2978 = mux(_T_210, deq_vec[2][1].is_rocc, UInt<1>(0h0)) node _T_2979 = mux(_T_211, deq_vec[3][1].is_rocc, UInt<1>(0h0)) node _T_2980 = mux(_T_212, deq_vec[4][1].is_rocc, UInt<1>(0h0)) node _T_2981 = mux(_T_213, deq_vec[5][1].is_rocc, UInt<1>(0h0)) node _T_2982 = mux(_T_214, deq_vec[6][1].is_rocc, UInt<1>(0h0)) node _T_2983 = mux(_T_215, deq_vec[7][1].is_rocc, UInt<1>(0h0)) node _T_2984 = or(_T_2976, _T_2977) node _T_2985 = or(_T_2984, _T_2978) node _T_2986 = or(_T_2985, _T_2979) node _T_2987 = or(_T_2986, _T_2980) node _T_2988 = or(_T_2987, _T_2981) node _T_2989 = or(_T_2988, _T_2982) node _T_2990 = or(_T_2989, _T_2983) wire _WIRE_191 : UInt<1> connect _WIRE_191, _T_2990 connect _WIRE_116.is_rocc, _WIRE_191 node _T_2991 = mux(_T_208, deq_vec[0][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_2992 = mux(_T_209, deq_vec[1][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_2993 = mux(_T_210, deq_vec[2][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_2994 = mux(_T_211, deq_vec[3][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_2995 = mux(_T_212, deq_vec[4][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_2996 = mux(_T_213, deq_vec[5][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_2997 = mux(_T_214, deq_vec[6][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_2998 = mux(_T_215, deq_vec[7][1].is_sys_pc2epc, UInt<1>(0h0)) node _T_2999 = or(_T_2991, _T_2992) node _T_3000 = or(_T_2999, _T_2993) node _T_3001 = or(_T_3000, _T_2994) node _T_3002 = or(_T_3001, _T_2995) node _T_3003 = or(_T_3002, _T_2996) node _T_3004 = or(_T_3003, _T_2997) node _T_3005 = or(_T_3004, _T_2998) wire _WIRE_192 : UInt<1> connect _WIRE_192, _T_3005 connect _WIRE_116.is_sys_pc2epc, _WIRE_192 node _T_3006 = mux(_T_208, deq_vec[0][1].is_eret, UInt<1>(0h0)) node _T_3007 = mux(_T_209, deq_vec[1][1].is_eret, UInt<1>(0h0)) node _T_3008 = mux(_T_210, deq_vec[2][1].is_eret, UInt<1>(0h0)) node _T_3009 = mux(_T_211, deq_vec[3][1].is_eret, UInt<1>(0h0)) node _T_3010 = mux(_T_212, deq_vec[4][1].is_eret, UInt<1>(0h0)) node _T_3011 = mux(_T_213, deq_vec[5][1].is_eret, UInt<1>(0h0)) node _T_3012 = mux(_T_214, deq_vec[6][1].is_eret, UInt<1>(0h0)) node _T_3013 = mux(_T_215, deq_vec[7][1].is_eret, UInt<1>(0h0)) node _T_3014 = or(_T_3006, _T_3007) node _T_3015 = or(_T_3014, _T_3008) node _T_3016 = or(_T_3015, _T_3009) node _T_3017 = or(_T_3016, _T_3010) node _T_3018 = or(_T_3017, _T_3011) node _T_3019 = or(_T_3018, _T_3012) node _T_3020 = or(_T_3019, _T_3013) wire _WIRE_193 : UInt<1> connect _WIRE_193, _T_3020 connect _WIRE_116.is_eret, _WIRE_193 node _T_3021 = mux(_T_208, deq_vec[0][1].is_amo, UInt<1>(0h0)) node _T_3022 = mux(_T_209, deq_vec[1][1].is_amo, UInt<1>(0h0)) node _T_3023 = mux(_T_210, deq_vec[2][1].is_amo, UInt<1>(0h0)) node _T_3024 = mux(_T_211, deq_vec[3][1].is_amo, UInt<1>(0h0)) node _T_3025 = mux(_T_212, deq_vec[4][1].is_amo, UInt<1>(0h0)) node _T_3026 = mux(_T_213, deq_vec[5][1].is_amo, UInt<1>(0h0)) node _T_3027 = mux(_T_214, deq_vec[6][1].is_amo, UInt<1>(0h0)) node _T_3028 = mux(_T_215, deq_vec[7][1].is_amo, UInt<1>(0h0)) node _T_3029 = or(_T_3021, _T_3022) node _T_3030 = or(_T_3029, _T_3023) node _T_3031 = or(_T_3030, _T_3024) node _T_3032 = or(_T_3031, _T_3025) node _T_3033 = or(_T_3032, _T_3026) node _T_3034 = or(_T_3033, _T_3027) node _T_3035 = or(_T_3034, _T_3028) wire _WIRE_194 : UInt<1> connect _WIRE_194, _T_3035 connect _WIRE_116.is_amo, _WIRE_194 node _T_3036 = mux(_T_208, deq_vec[0][1].is_sfence, UInt<1>(0h0)) node _T_3037 = mux(_T_209, deq_vec[1][1].is_sfence, UInt<1>(0h0)) node _T_3038 = mux(_T_210, deq_vec[2][1].is_sfence, UInt<1>(0h0)) node _T_3039 = mux(_T_211, deq_vec[3][1].is_sfence, UInt<1>(0h0)) node _T_3040 = mux(_T_212, deq_vec[4][1].is_sfence, UInt<1>(0h0)) node _T_3041 = mux(_T_213, deq_vec[5][1].is_sfence, UInt<1>(0h0)) node _T_3042 = mux(_T_214, deq_vec[6][1].is_sfence, UInt<1>(0h0)) node _T_3043 = mux(_T_215, deq_vec[7][1].is_sfence, UInt<1>(0h0)) node _T_3044 = or(_T_3036, _T_3037) node _T_3045 = or(_T_3044, _T_3038) node _T_3046 = or(_T_3045, _T_3039) node _T_3047 = or(_T_3046, _T_3040) node _T_3048 = or(_T_3047, _T_3041) node _T_3049 = or(_T_3048, _T_3042) node _T_3050 = or(_T_3049, _T_3043) wire _WIRE_195 : UInt<1> connect _WIRE_195, _T_3050 connect _WIRE_116.is_sfence, _WIRE_195 node _T_3051 = mux(_T_208, deq_vec[0][1].is_fencei, UInt<1>(0h0)) node _T_3052 = mux(_T_209, deq_vec[1][1].is_fencei, UInt<1>(0h0)) node _T_3053 = mux(_T_210, deq_vec[2][1].is_fencei, UInt<1>(0h0)) node _T_3054 = mux(_T_211, deq_vec[3][1].is_fencei, UInt<1>(0h0)) node _T_3055 = mux(_T_212, deq_vec[4][1].is_fencei, UInt<1>(0h0)) node _T_3056 = mux(_T_213, deq_vec[5][1].is_fencei, UInt<1>(0h0)) node _T_3057 = mux(_T_214, deq_vec[6][1].is_fencei, UInt<1>(0h0)) node _T_3058 = mux(_T_215, deq_vec[7][1].is_fencei, UInt<1>(0h0)) node _T_3059 = or(_T_3051, _T_3052) node _T_3060 = or(_T_3059, _T_3053) node _T_3061 = or(_T_3060, _T_3054) node _T_3062 = or(_T_3061, _T_3055) node _T_3063 = or(_T_3062, _T_3056) node _T_3064 = or(_T_3063, _T_3057) node _T_3065 = or(_T_3064, _T_3058) wire _WIRE_196 : UInt<1> connect _WIRE_196, _T_3065 connect _WIRE_116.is_fencei, _WIRE_196 node _T_3066 = mux(_T_208, deq_vec[0][1].is_fence, UInt<1>(0h0)) node _T_3067 = mux(_T_209, deq_vec[1][1].is_fence, UInt<1>(0h0)) node _T_3068 = mux(_T_210, deq_vec[2][1].is_fence, UInt<1>(0h0)) node _T_3069 = mux(_T_211, deq_vec[3][1].is_fence, UInt<1>(0h0)) node _T_3070 = mux(_T_212, deq_vec[4][1].is_fence, UInt<1>(0h0)) node _T_3071 = mux(_T_213, deq_vec[5][1].is_fence, UInt<1>(0h0)) node _T_3072 = mux(_T_214, deq_vec[6][1].is_fence, UInt<1>(0h0)) node _T_3073 = mux(_T_215, deq_vec[7][1].is_fence, UInt<1>(0h0)) node _T_3074 = or(_T_3066, _T_3067) node _T_3075 = or(_T_3074, _T_3068) node _T_3076 = or(_T_3075, _T_3069) node _T_3077 = or(_T_3076, _T_3070) node _T_3078 = or(_T_3077, _T_3071) node _T_3079 = or(_T_3078, _T_3072) node _T_3080 = or(_T_3079, _T_3073) wire _WIRE_197 : UInt<1> connect _WIRE_197, _T_3080 connect _WIRE_116.is_fence, _WIRE_197 node _T_3081 = mux(_T_208, deq_vec[0][1].is_sfb, UInt<1>(0h0)) node _T_3082 = mux(_T_209, deq_vec[1][1].is_sfb, UInt<1>(0h0)) node _T_3083 = mux(_T_210, deq_vec[2][1].is_sfb, UInt<1>(0h0)) node _T_3084 = mux(_T_211, deq_vec[3][1].is_sfb, UInt<1>(0h0)) node _T_3085 = mux(_T_212, deq_vec[4][1].is_sfb, UInt<1>(0h0)) node _T_3086 = mux(_T_213, deq_vec[5][1].is_sfb, UInt<1>(0h0)) node _T_3087 = mux(_T_214, deq_vec[6][1].is_sfb, UInt<1>(0h0)) node _T_3088 = mux(_T_215, deq_vec[7][1].is_sfb, UInt<1>(0h0)) node _T_3089 = or(_T_3081, _T_3082) node _T_3090 = or(_T_3089, _T_3083) node _T_3091 = or(_T_3090, _T_3084) node _T_3092 = or(_T_3091, _T_3085) node _T_3093 = or(_T_3092, _T_3086) node _T_3094 = or(_T_3093, _T_3087) node _T_3095 = or(_T_3094, _T_3088) wire _WIRE_198 : UInt<1> connect _WIRE_198, _T_3095 connect _WIRE_116.is_sfb, _WIRE_198 node _T_3096 = mux(_T_208, deq_vec[0][1].br_type, UInt<1>(0h0)) node _T_3097 = mux(_T_209, deq_vec[1][1].br_type, UInt<1>(0h0)) node _T_3098 = mux(_T_210, deq_vec[2][1].br_type, UInt<1>(0h0)) node _T_3099 = mux(_T_211, deq_vec[3][1].br_type, UInt<1>(0h0)) node _T_3100 = mux(_T_212, deq_vec[4][1].br_type, UInt<1>(0h0)) node _T_3101 = mux(_T_213, deq_vec[5][1].br_type, UInt<1>(0h0)) node _T_3102 = mux(_T_214, deq_vec[6][1].br_type, UInt<1>(0h0)) node _T_3103 = mux(_T_215, deq_vec[7][1].br_type, UInt<1>(0h0)) node _T_3104 = or(_T_3096, _T_3097) node _T_3105 = or(_T_3104, _T_3098) node _T_3106 = or(_T_3105, _T_3099) node _T_3107 = or(_T_3106, _T_3100) node _T_3108 = or(_T_3107, _T_3101) node _T_3109 = or(_T_3108, _T_3102) node _T_3110 = or(_T_3109, _T_3103) wire _WIRE_199 : UInt<4> connect _WIRE_199, _T_3110 connect _WIRE_116.br_type, _WIRE_199 node _T_3111 = mux(_T_208, deq_vec[0][1].br_tag, UInt<1>(0h0)) node _T_3112 = mux(_T_209, deq_vec[1][1].br_tag, UInt<1>(0h0)) node _T_3113 = mux(_T_210, deq_vec[2][1].br_tag, UInt<1>(0h0)) node _T_3114 = mux(_T_211, deq_vec[3][1].br_tag, UInt<1>(0h0)) node _T_3115 = mux(_T_212, deq_vec[4][1].br_tag, UInt<1>(0h0)) node _T_3116 = mux(_T_213, deq_vec[5][1].br_tag, UInt<1>(0h0)) node _T_3117 = mux(_T_214, deq_vec[6][1].br_tag, UInt<1>(0h0)) node _T_3118 = mux(_T_215, deq_vec[7][1].br_tag, UInt<1>(0h0)) node _T_3119 = or(_T_3111, _T_3112) node _T_3120 = or(_T_3119, _T_3113) node _T_3121 = or(_T_3120, _T_3114) node _T_3122 = or(_T_3121, _T_3115) node _T_3123 = or(_T_3122, _T_3116) node _T_3124 = or(_T_3123, _T_3117) node _T_3125 = or(_T_3124, _T_3118) wire _WIRE_200 : UInt<4> connect _WIRE_200, _T_3125 connect _WIRE_116.br_tag, _WIRE_200 node _T_3126 = mux(_T_208, deq_vec[0][1].br_mask, UInt<1>(0h0)) node _T_3127 = mux(_T_209, deq_vec[1][1].br_mask, UInt<1>(0h0)) node _T_3128 = mux(_T_210, deq_vec[2][1].br_mask, UInt<1>(0h0)) node _T_3129 = mux(_T_211, deq_vec[3][1].br_mask, UInt<1>(0h0)) node _T_3130 = mux(_T_212, deq_vec[4][1].br_mask, UInt<1>(0h0)) node _T_3131 = mux(_T_213, deq_vec[5][1].br_mask, UInt<1>(0h0)) node _T_3132 = mux(_T_214, deq_vec[6][1].br_mask, UInt<1>(0h0)) node _T_3133 = mux(_T_215, deq_vec[7][1].br_mask, UInt<1>(0h0)) node _T_3134 = or(_T_3126, _T_3127) node _T_3135 = or(_T_3134, _T_3128) node _T_3136 = or(_T_3135, _T_3129) node _T_3137 = or(_T_3136, _T_3130) node _T_3138 = or(_T_3137, _T_3131) node _T_3139 = or(_T_3138, _T_3132) node _T_3140 = or(_T_3139, _T_3133) wire _WIRE_201 : UInt<12> connect _WIRE_201, _T_3140 connect _WIRE_116.br_mask, _WIRE_201 node _T_3141 = mux(_T_208, deq_vec[0][1].dis_col_sel, UInt<1>(0h0)) node _T_3142 = mux(_T_209, deq_vec[1][1].dis_col_sel, UInt<1>(0h0)) node _T_3143 = mux(_T_210, deq_vec[2][1].dis_col_sel, UInt<1>(0h0)) node _T_3144 = mux(_T_211, deq_vec[3][1].dis_col_sel, UInt<1>(0h0)) node _T_3145 = mux(_T_212, deq_vec[4][1].dis_col_sel, UInt<1>(0h0)) node _T_3146 = mux(_T_213, deq_vec[5][1].dis_col_sel, UInt<1>(0h0)) node _T_3147 = mux(_T_214, deq_vec[6][1].dis_col_sel, UInt<1>(0h0)) node _T_3148 = mux(_T_215, deq_vec[7][1].dis_col_sel, UInt<1>(0h0)) node _T_3149 = or(_T_3141, _T_3142) node _T_3150 = or(_T_3149, _T_3143) node _T_3151 = or(_T_3150, _T_3144) node _T_3152 = or(_T_3151, _T_3145) node _T_3153 = or(_T_3152, _T_3146) node _T_3154 = or(_T_3153, _T_3147) node _T_3155 = or(_T_3154, _T_3148) wire _WIRE_202 : UInt<2> connect _WIRE_202, _T_3155 connect _WIRE_116.dis_col_sel, _WIRE_202 node _T_3156 = mux(_T_208, deq_vec[0][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3157 = mux(_T_209, deq_vec[1][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3158 = mux(_T_210, deq_vec[2][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3159 = mux(_T_211, deq_vec[3][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3160 = mux(_T_212, deq_vec[4][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3161 = mux(_T_213, deq_vec[5][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3162 = mux(_T_214, deq_vec[6][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3163 = mux(_T_215, deq_vec[7][1].iw_p3_bypass_hint, UInt<1>(0h0)) node _T_3164 = or(_T_3156, _T_3157) node _T_3165 = or(_T_3164, _T_3158) node _T_3166 = or(_T_3165, _T_3159) node _T_3167 = or(_T_3166, _T_3160) node _T_3168 = or(_T_3167, _T_3161) node _T_3169 = or(_T_3168, _T_3162) node _T_3170 = or(_T_3169, _T_3163) wire _WIRE_203 : UInt<1> connect _WIRE_203, _T_3170 connect _WIRE_116.iw_p3_bypass_hint, _WIRE_203 node _T_3171 = mux(_T_208, deq_vec[0][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3172 = mux(_T_209, deq_vec[1][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3173 = mux(_T_210, deq_vec[2][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3174 = mux(_T_211, deq_vec[3][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3175 = mux(_T_212, deq_vec[4][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3176 = mux(_T_213, deq_vec[5][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3177 = mux(_T_214, deq_vec[6][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3178 = mux(_T_215, deq_vec[7][1].iw_p2_bypass_hint, UInt<1>(0h0)) node _T_3179 = or(_T_3171, _T_3172) node _T_3180 = or(_T_3179, _T_3173) node _T_3181 = or(_T_3180, _T_3174) node _T_3182 = or(_T_3181, _T_3175) node _T_3183 = or(_T_3182, _T_3176) node _T_3184 = or(_T_3183, _T_3177) node _T_3185 = or(_T_3184, _T_3178) wire _WIRE_204 : UInt<1> connect _WIRE_204, _T_3185 connect _WIRE_116.iw_p2_bypass_hint, _WIRE_204 node _T_3186 = mux(_T_208, deq_vec[0][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3187 = mux(_T_209, deq_vec[1][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3188 = mux(_T_210, deq_vec[2][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3189 = mux(_T_211, deq_vec[3][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3190 = mux(_T_212, deq_vec[4][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3191 = mux(_T_213, deq_vec[5][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3192 = mux(_T_214, deq_vec[6][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3193 = mux(_T_215, deq_vec[7][1].iw_p1_bypass_hint, UInt<1>(0h0)) node _T_3194 = or(_T_3186, _T_3187) node _T_3195 = or(_T_3194, _T_3188) node _T_3196 = or(_T_3195, _T_3189) node _T_3197 = or(_T_3196, _T_3190) node _T_3198 = or(_T_3197, _T_3191) node _T_3199 = or(_T_3198, _T_3192) node _T_3200 = or(_T_3199, _T_3193) wire _WIRE_205 : UInt<1> connect _WIRE_205, _T_3200 connect _WIRE_116.iw_p1_bypass_hint, _WIRE_205 node _T_3201 = mux(_T_208, deq_vec[0][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3202 = mux(_T_209, deq_vec[1][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3203 = mux(_T_210, deq_vec[2][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3204 = mux(_T_211, deq_vec[3][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3205 = mux(_T_212, deq_vec[4][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3206 = mux(_T_213, deq_vec[5][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3207 = mux(_T_214, deq_vec[6][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3208 = mux(_T_215, deq_vec[7][1].iw_p2_speculative_child, UInt<1>(0h0)) node _T_3209 = or(_T_3201, _T_3202) node _T_3210 = or(_T_3209, _T_3203) node _T_3211 = or(_T_3210, _T_3204) node _T_3212 = or(_T_3211, _T_3205) node _T_3213 = or(_T_3212, _T_3206) node _T_3214 = or(_T_3213, _T_3207) node _T_3215 = or(_T_3214, _T_3208) wire _WIRE_206 : UInt<2> connect _WIRE_206, _T_3215 connect _WIRE_116.iw_p2_speculative_child, _WIRE_206 node _T_3216 = mux(_T_208, deq_vec[0][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3217 = mux(_T_209, deq_vec[1][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3218 = mux(_T_210, deq_vec[2][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3219 = mux(_T_211, deq_vec[3][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3220 = mux(_T_212, deq_vec[4][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3221 = mux(_T_213, deq_vec[5][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3222 = mux(_T_214, deq_vec[6][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3223 = mux(_T_215, deq_vec[7][1].iw_p1_speculative_child, UInt<1>(0h0)) node _T_3224 = or(_T_3216, _T_3217) node _T_3225 = or(_T_3224, _T_3218) node _T_3226 = or(_T_3225, _T_3219) node _T_3227 = or(_T_3226, _T_3220) node _T_3228 = or(_T_3227, _T_3221) node _T_3229 = or(_T_3228, _T_3222) node _T_3230 = or(_T_3229, _T_3223) wire _WIRE_207 : UInt<2> connect _WIRE_207, _T_3230 connect _WIRE_116.iw_p1_speculative_child, _WIRE_207 node _T_3231 = mux(_T_208, deq_vec[0][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3232 = mux(_T_209, deq_vec[1][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3233 = mux(_T_210, deq_vec[2][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3234 = mux(_T_211, deq_vec[3][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3235 = mux(_T_212, deq_vec[4][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3236 = mux(_T_213, deq_vec[5][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3237 = mux(_T_214, deq_vec[6][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3238 = mux(_T_215, deq_vec[7][1].iw_issued_partial_dgen, UInt<1>(0h0)) node _T_3239 = or(_T_3231, _T_3232) node _T_3240 = or(_T_3239, _T_3233) node _T_3241 = or(_T_3240, _T_3234) node _T_3242 = or(_T_3241, _T_3235) node _T_3243 = or(_T_3242, _T_3236) node _T_3244 = or(_T_3243, _T_3237) node _T_3245 = or(_T_3244, _T_3238) wire _WIRE_208 : UInt<1> connect _WIRE_208, _T_3245 connect _WIRE_116.iw_issued_partial_dgen, _WIRE_208 node _T_3246 = mux(_T_208, deq_vec[0][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3247 = mux(_T_209, deq_vec[1][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3248 = mux(_T_210, deq_vec[2][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3249 = mux(_T_211, deq_vec[3][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3250 = mux(_T_212, deq_vec[4][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3251 = mux(_T_213, deq_vec[5][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3252 = mux(_T_214, deq_vec[6][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3253 = mux(_T_215, deq_vec[7][1].iw_issued_partial_agen, UInt<1>(0h0)) node _T_3254 = or(_T_3246, _T_3247) node _T_3255 = or(_T_3254, _T_3248) node _T_3256 = or(_T_3255, _T_3249) node _T_3257 = or(_T_3256, _T_3250) node _T_3258 = or(_T_3257, _T_3251) node _T_3259 = or(_T_3258, _T_3252) node _T_3260 = or(_T_3259, _T_3253) wire _WIRE_209 : UInt<1> connect _WIRE_209, _T_3260 connect _WIRE_116.iw_issued_partial_agen, _WIRE_209 node _T_3261 = mux(_T_208, deq_vec[0][1].iw_issued, UInt<1>(0h0)) node _T_3262 = mux(_T_209, deq_vec[1][1].iw_issued, UInt<1>(0h0)) node _T_3263 = mux(_T_210, deq_vec[2][1].iw_issued, UInt<1>(0h0)) node _T_3264 = mux(_T_211, deq_vec[3][1].iw_issued, UInt<1>(0h0)) node _T_3265 = mux(_T_212, deq_vec[4][1].iw_issued, UInt<1>(0h0)) node _T_3266 = mux(_T_213, deq_vec[5][1].iw_issued, UInt<1>(0h0)) node _T_3267 = mux(_T_214, deq_vec[6][1].iw_issued, UInt<1>(0h0)) node _T_3268 = mux(_T_215, deq_vec[7][1].iw_issued, UInt<1>(0h0)) node _T_3269 = or(_T_3261, _T_3262) node _T_3270 = or(_T_3269, _T_3263) node _T_3271 = or(_T_3270, _T_3264) node _T_3272 = or(_T_3271, _T_3265) node _T_3273 = or(_T_3272, _T_3266) node _T_3274 = or(_T_3273, _T_3267) node _T_3275 = or(_T_3274, _T_3268) wire _WIRE_210 : UInt<1> connect _WIRE_210, _T_3275 connect _WIRE_116.iw_issued, _WIRE_210 wire _WIRE_211 : UInt<1>[10] node _T_3276 = mux(_T_208, deq_vec[0][1].fu_code[0], UInt<1>(0h0)) node _T_3277 = mux(_T_209, deq_vec[1][1].fu_code[0], UInt<1>(0h0)) node _T_3278 = mux(_T_210, deq_vec[2][1].fu_code[0], UInt<1>(0h0)) node _T_3279 = mux(_T_211, deq_vec[3][1].fu_code[0], UInt<1>(0h0)) node _T_3280 = mux(_T_212, deq_vec[4][1].fu_code[0], UInt<1>(0h0)) node _T_3281 = mux(_T_213, deq_vec[5][1].fu_code[0], UInt<1>(0h0)) node _T_3282 = mux(_T_214, deq_vec[6][1].fu_code[0], UInt<1>(0h0)) node _T_3283 = mux(_T_215, deq_vec[7][1].fu_code[0], UInt<1>(0h0)) node _T_3284 = or(_T_3276, _T_3277) node _T_3285 = or(_T_3284, _T_3278) node _T_3286 = or(_T_3285, _T_3279) node _T_3287 = or(_T_3286, _T_3280) node _T_3288 = or(_T_3287, _T_3281) node _T_3289 = or(_T_3288, _T_3282) node _T_3290 = or(_T_3289, _T_3283) wire _WIRE_212 : UInt<1> connect _WIRE_212, _T_3290 connect _WIRE_211[0], _WIRE_212 node _T_3291 = mux(_T_208, deq_vec[0][1].fu_code[1], UInt<1>(0h0)) node _T_3292 = mux(_T_209, deq_vec[1][1].fu_code[1], UInt<1>(0h0)) node _T_3293 = mux(_T_210, deq_vec[2][1].fu_code[1], UInt<1>(0h0)) node _T_3294 = mux(_T_211, deq_vec[3][1].fu_code[1], UInt<1>(0h0)) node _T_3295 = mux(_T_212, deq_vec[4][1].fu_code[1], UInt<1>(0h0)) node _T_3296 = mux(_T_213, deq_vec[5][1].fu_code[1], UInt<1>(0h0)) node _T_3297 = mux(_T_214, deq_vec[6][1].fu_code[1], UInt<1>(0h0)) node _T_3298 = mux(_T_215, deq_vec[7][1].fu_code[1], UInt<1>(0h0)) node _T_3299 = or(_T_3291, _T_3292) node _T_3300 = or(_T_3299, _T_3293) node _T_3301 = or(_T_3300, _T_3294) node _T_3302 = or(_T_3301, _T_3295) node _T_3303 = or(_T_3302, _T_3296) node _T_3304 = or(_T_3303, _T_3297) node _T_3305 = or(_T_3304, _T_3298) wire _WIRE_213 : UInt<1> connect _WIRE_213, _T_3305 connect _WIRE_211[1], _WIRE_213 node _T_3306 = mux(_T_208, deq_vec[0][1].fu_code[2], UInt<1>(0h0)) node _T_3307 = mux(_T_209, deq_vec[1][1].fu_code[2], UInt<1>(0h0)) node _T_3308 = mux(_T_210, deq_vec[2][1].fu_code[2], UInt<1>(0h0)) node _T_3309 = mux(_T_211, deq_vec[3][1].fu_code[2], UInt<1>(0h0)) node _T_3310 = mux(_T_212, deq_vec[4][1].fu_code[2], UInt<1>(0h0)) node _T_3311 = mux(_T_213, deq_vec[5][1].fu_code[2], UInt<1>(0h0)) node _T_3312 = mux(_T_214, deq_vec[6][1].fu_code[2], UInt<1>(0h0)) node _T_3313 = mux(_T_215, deq_vec[7][1].fu_code[2], UInt<1>(0h0)) node _T_3314 = or(_T_3306, _T_3307) node _T_3315 = or(_T_3314, _T_3308) node _T_3316 = or(_T_3315, _T_3309) node _T_3317 = or(_T_3316, _T_3310) node _T_3318 = or(_T_3317, _T_3311) node _T_3319 = or(_T_3318, _T_3312) node _T_3320 = or(_T_3319, _T_3313) wire _WIRE_214 : UInt<1> connect _WIRE_214, _T_3320 connect _WIRE_211[2], _WIRE_214 node _T_3321 = mux(_T_208, deq_vec[0][1].fu_code[3], UInt<1>(0h0)) node _T_3322 = mux(_T_209, deq_vec[1][1].fu_code[3], UInt<1>(0h0)) node _T_3323 = mux(_T_210, deq_vec[2][1].fu_code[3], UInt<1>(0h0)) node _T_3324 = mux(_T_211, deq_vec[3][1].fu_code[3], UInt<1>(0h0)) node _T_3325 = mux(_T_212, deq_vec[4][1].fu_code[3], UInt<1>(0h0)) node _T_3326 = mux(_T_213, deq_vec[5][1].fu_code[3], UInt<1>(0h0)) node _T_3327 = mux(_T_214, deq_vec[6][1].fu_code[3], UInt<1>(0h0)) node _T_3328 = mux(_T_215, deq_vec[7][1].fu_code[3], UInt<1>(0h0)) node _T_3329 = or(_T_3321, _T_3322) node _T_3330 = or(_T_3329, _T_3323) node _T_3331 = or(_T_3330, _T_3324) node _T_3332 = or(_T_3331, _T_3325) node _T_3333 = or(_T_3332, _T_3326) node _T_3334 = or(_T_3333, _T_3327) node _T_3335 = or(_T_3334, _T_3328) wire _WIRE_215 : UInt<1> connect _WIRE_215, _T_3335 connect _WIRE_211[3], _WIRE_215 node _T_3336 = mux(_T_208, deq_vec[0][1].fu_code[4], UInt<1>(0h0)) node _T_3337 = mux(_T_209, deq_vec[1][1].fu_code[4], UInt<1>(0h0)) node _T_3338 = mux(_T_210, deq_vec[2][1].fu_code[4], UInt<1>(0h0)) node _T_3339 = mux(_T_211, deq_vec[3][1].fu_code[4], UInt<1>(0h0)) node _T_3340 = mux(_T_212, deq_vec[4][1].fu_code[4], UInt<1>(0h0)) node _T_3341 = mux(_T_213, deq_vec[5][1].fu_code[4], UInt<1>(0h0)) node _T_3342 = mux(_T_214, deq_vec[6][1].fu_code[4], UInt<1>(0h0)) node _T_3343 = mux(_T_215, deq_vec[7][1].fu_code[4], UInt<1>(0h0)) node _T_3344 = or(_T_3336, _T_3337) node _T_3345 = or(_T_3344, _T_3338) node _T_3346 = or(_T_3345, _T_3339) node _T_3347 = or(_T_3346, _T_3340) node _T_3348 = or(_T_3347, _T_3341) node _T_3349 = or(_T_3348, _T_3342) node _T_3350 = or(_T_3349, _T_3343) wire _WIRE_216 : UInt<1> connect _WIRE_216, _T_3350 connect _WIRE_211[4], _WIRE_216 node _T_3351 = mux(_T_208, deq_vec[0][1].fu_code[5], UInt<1>(0h0)) node _T_3352 = mux(_T_209, deq_vec[1][1].fu_code[5], UInt<1>(0h0)) node _T_3353 = mux(_T_210, deq_vec[2][1].fu_code[5], UInt<1>(0h0)) node _T_3354 = mux(_T_211, deq_vec[3][1].fu_code[5], UInt<1>(0h0)) node _T_3355 = mux(_T_212, deq_vec[4][1].fu_code[5], UInt<1>(0h0)) node _T_3356 = mux(_T_213, deq_vec[5][1].fu_code[5], UInt<1>(0h0)) node _T_3357 = mux(_T_214, deq_vec[6][1].fu_code[5], UInt<1>(0h0)) node _T_3358 = mux(_T_215, deq_vec[7][1].fu_code[5], UInt<1>(0h0)) node _T_3359 = or(_T_3351, _T_3352) node _T_3360 = or(_T_3359, _T_3353) node _T_3361 = or(_T_3360, _T_3354) node _T_3362 = or(_T_3361, _T_3355) node _T_3363 = or(_T_3362, _T_3356) node _T_3364 = or(_T_3363, _T_3357) node _T_3365 = or(_T_3364, _T_3358) wire _WIRE_217 : UInt<1> connect _WIRE_217, _T_3365 connect _WIRE_211[5], _WIRE_217 node _T_3366 = mux(_T_208, deq_vec[0][1].fu_code[6], UInt<1>(0h0)) node _T_3367 = mux(_T_209, deq_vec[1][1].fu_code[6], UInt<1>(0h0)) node _T_3368 = mux(_T_210, deq_vec[2][1].fu_code[6], UInt<1>(0h0)) node _T_3369 = mux(_T_211, deq_vec[3][1].fu_code[6], UInt<1>(0h0)) node _T_3370 = mux(_T_212, deq_vec[4][1].fu_code[6], UInt<1>(0h0)) node _T_3371 = mux(_T_213, deq_vec[5][1].fu_code[6], UInt<1>(0h0)) node _T_3372 = mux(_T_214, deq_vec[6][1].fu_code[6], UInt<1>(0h0)) node _T_3373 = mux(_T_215, deq_vec[7][1].fu_code[6], UInt<1>(0h0)) node _T_3374 = or(_T_3366, _T_3367) node _T_3375 = or(_T_3374, _T_3368) node _T_3376 = or(_T_3375, _T_3369) node _T_3377 = or(_T_3376, _T_3370) node _T_3378 = or(_T_3377, _T_3371) node _T_3379 = or(_T_3378, _T_3372) node _T_3380 = or(_T_3379, _T_3373) wire _WIRE_218 : UInt<1> connect _WIRE_218, _T_3380 connect _WIRE_211[6], _WIRE_218 node _T_3381 = mux(_T_208, deq_vec[0][1].fu_code[7], UInt<1>(0h0)) node _T_3382 = mux(_T_209, deq_vec[1][1].fu_code[7], UInt<1>(0h0)) node _T_3383 = mux(_T_210, deq_vec[2][1].fu_code[7], UInt<1>(0h0)) node _T_3384 = mux(_T_211, deq_vec[3][1].fu_code[7], UInt<1>(0h0)) node _T_3385 = mux(_T_212, deq_vec[4][1].fu_code[7], UInt<1>(0h0)) node _T_3386 = mux(_T_213, deq_vec[5][1].fu_code[7], UInt<1>(0h0)) node _T_3387 = mux(_T_214, deq_vec[6][1].fu_code[7], UInt<1>(0h0)) node _T_3388 = mux(_T_215, deq_vec[7][1].fu_code[7], UInt<1>(0h0)) node _T_3389 = or(_T_3381, _T_3382) node _T_3390 = or(_T_3389, _T_3383) node _T_3391 = or(_T_3390, _T_3384) node _T_3392 = or(_T_3391, _T_3385) node _T_3393 = or(_T_3392, _T_3386) node _T_3394 = or(_T_3393, _T_3387) node _T_3395 = or(_T_3394, _T_3388) wire _WIRE_219 : UInt<1> connect _WIRE_219, _T_3395 connect _WIRE_211[7], _WIRE_219 node _T_3396 = mux(_T_208, deq_vec[0][1].fu_code[8], UInt<1>(0h0)) node _T_3397 = mux(_T_209, deq_vec[1][1].fu_code[8], UInt<1>(0h0)) node _T_3398 = mux(_T_210, deq_vec[2][1].fu_code[8], UInt<1>(0h0)) node _T_3399 = mux(_T_211, deq_vec[3][1].fu_code[8], UInt<1>(0h0)) node _T_3400 = mux(_T_212, deq_vec[4][1].fu_code[8], UInt<1>(0h0)) node _T_3401 = mux(_T_213, deq_vec[5][1].fu_code[8], UInt<1>(0h0)) node _T_3402 = mux(_T_214, deq_vec[6][1].fu_code[8], UInt<1>(0h0)) node _T_3403 = mux(_T_215, deq_vec[7][1].fu_code[8], UInt<1>(0h0)) node _T_3404 = or(_T_3396, _T_3397) node _T_3405 = or(_T_3404, _T_3398) node _T_3406 = or(_T_3405, _T_3399) node _T_3407 = or(_T_3406, _T_3400) node _T_3408 = or(_T_3407, _T_3401) node _T_3409 = or(_T_3408, _T_3402) node _T_3410 = or(_T_3409, _T_3403) wire _WIRE_220 : UInt<1> connect _WIRE_220, _T_3410 connect _WIRE_211[8], _WIRE_220 node _T_3411 = mux(_T_208, deq_vec[0][1].fu_code[9], UInt<1>(0h0)) node _T_3412 = mux(_T_209, deq_vec[1][1].fu_code[9], UInt<1>(0h0)) node _T_3413 = mux(_T_210, deq_vec[2][1].fu_code[9], UInt<1>(0h0)) node _T_3414 = mux(_T_211, deq_vec[3][1].fu_code[9], UInt<1>(0h0)) node _T_3415 = mux(_T_212, deq_vec[4][1].fu_code[9], UInt<1>(0h0)) node _T_3416 = mux(_T_213, deq_vec[5][1].fu_code[9], UInt<1>(0h0)) node _T_3417 = mux(_T_214, deq_vec[6][1].fu_code[9], UInt<1>(0h0)) node _T_3418 = mux(_T_215, deq_vec[7][1].fu_code[9], UInt<1>(0h0)) node _T_3419 = or(_T_3411, _T_3412) node _T_3420 = or(_T_3419, _T_3413) node _T_3421 = or(_T_3420, _T_3414) node _T_3422 = or(_T_3421, _T_3415) node _T_3423 = or(_T_3422, _T_3416) node _T_3424 = or(_T_3423, _T_3417) node _T_3425 = or(_T_3424, _T_3418) wire _WIRE_221 : UInt<1> connect _WIRE_221, _T_3425 connect _WIRE_211[9], _WIRE_221 connect _WIRE_116.fu_code, _WIRE_211 wire _WIRE_222 : UInt<1>[4] node _T_3426 = mux(_T_208, deq_vec[0][1].iq_type[0], UInt<1>(0h0)) node _T_3427 = mux(_T_209, deq_vec[1][1].iq_type[0], UInt<1>(0h0)) node _T_3428 = mux(_T_210, deq_vec[2][1].iq_type[0], UInt<1>(0h0)) node _T_3429 = mux(_T_211, deq_vec[3][1].iq_type[0], UInt<1>(0h0)) node _T_3430 = mux(_T_212, deq_vec[4][1].iq_type[0], UInt<1>(0h0)) node _T_3431 = mux(_T_213, deq_vec[5][1].iq_type[0], UInt<1>(0h0)) node _T_3432 = mux(_T_214, deq_vec[6][1].iq_type[0], UInt<1>(0h0)) node _T_3433 = mux(_T_215, deq_vec[7][1].iq_type[0], UInt<1>(0h0)) node _T_3434 = or(_T_3426, _T_3427) node _T_3435 = or(_T_3434, _T_3428) node _T_3436 = or(_T_3435, _T_3429) node _T_3437 = or(_T_3436, _T_3430) node _T_3438 = or(_T_3437, _T_3431) node _T_3439 = or(_T_3438, _T_3432) node _T_3440 = or(_T_3439, _T_3433) wire _WIRE_223 : UInt<1> connect _WIRE_223, _T_3440 connect _WIRE_222[0], _WIRE_223 node _T_3441 = mux(_T_208, deq_vec[0][1].iq_type[1], UInt<1>(0h0)) node _T_3442 = mux(_T_209, deq_vec[1][1].iq_type[1], UInt<1>(0h0)) node _T_3443 = mux(_T_210, deq_vec[2][1].iq_type[1], UInt<1>(0h0)) node _T_3444 = mux(_T_211, deq_vec[3][1].iq_type[1], UInt<1>(0h0)) node _T_3445 = mux(_T_212, deq_vec[4][1].iq_type[1], UInt<1>(0h0)) node _T_3446 = mux(_T_213, deq_vec[5][1].iq_type[1], UInt<1>(0h0)) node _T_3447 = mux(_T_214, deq_vec[6][1].iq_type[1], UInt<1>(0h0)) node _T_3448 = mux(_T_215, deq_vec[7][1].iq_type[1], UInt<1>(0h0)) node _T_3449 = or(_T_3441, _T_3442) node _T_3450 = or(_T_3449, _T_3443) node _T_3451 = or(_T_3450, _T_3444) node _T_3452 = or(_T_3451, _T_3445) node _T_3453 = or(_T_3452, _T_3446) node _T_3454 = or(_T_3453, _T_3447) node _T_3455 = or(_T_3454, _T_3448) wire _WIRE_224 : UInt<1> connect _WIRE_224, _T_3455 connect _WIRE_222[1], _WIRE_224 node _T_3456 = mux(_T_208, deq_vec[0][1].iq_type[2], UInt<1>(0h0)) node _T_3457 = mux(_T_209, deq_vec[1][1].iq_type[2], UInt<1>(0h0)) node _T_3458 = mux(_T_210, deq_vec[2][1].iq_type[2], UInt<1>(0h0)) node _T_3459 = mux(_T_211, deq_vec[3][1].iq_type[2], UInt<1>(0h0)) node _T_3460 = mux(_T_212, deq_vec[4][1].iq_type[2], UInt<1>(0h0)) node _T_3461 = mux(_T_213, deq_vec[5][1].iq_type[2], UInt<1>(0h0)) node _T_3462 = mux(_T_214, deq_vec[6][1].iq_type[2], UInt<1>(0h0)) node _T_3463 = mux(_T_215, deq_vec[7][1].iq_type[2], UInt<1>(0h0)) node _T_3464 = or(_T_3456, _T_3457) node _T_3465 = or(_T_3464, _T_3458) node _T_3466 = or(_T_3465, _T_3459) node _T_3467 = or(_T_3466, _T_3460) node _T_3468 = or(_T_3467, _T_3461) node _T_3469 = or(_T_3468, _T_3462) node _T_3470 = or(_T_3469, _T_3463) wire _WIRE_225 : UInt<1> connect _WIRE_225, _T_3470 connect _WIRE_222[2], _WIRE_225 node _T_3471 = mux(_T_208, deq_vec[0][1].iq_type[3], UInt<1>(0h0)) node _T_3472 = mux(_T_209, deq_vec[1][1].iq_type[3], UInt<1>(0h0)) node _T_3473 = mux(_T_210, deq_vec[2][1].iq_type[3], UInt<1>(0h0)) node _T_3474 = mux(_T_211, deq_vec[3][1].iq_type[3], UInt<1>(0h0)) node _T_3475 = mux(_T_212, deq_vec[4][1].iq_type[3], UInt<1>(0h0)) node _T_3476 = mux(_T_213, deq_vec[5][1].iq_type[3], UInt<1>(0h0)) node _T_3477 = mux(_T_214, deq_vec[6][1].iq_type[3], UInt<1>(0h0)) node _T_3478 = mux(_T_215, deq_vec[7][1].iq_type[3], UInt<1>(0h0)) node _T_3479 = or(_T_3471, _T_3472) node _T_3480 = or(_T_3479, _T_3473) node _T_3481 = or(_T_3480, _T_3474) node _T_3482 = or(_T_3481, _T_3475) node _T_3483 = or(_T_3482, _T_3476) node _T_3484 = or(_T_3483, _T_3477) node _T_3485 = or(_T_3484, _T_3478) wire _WIRE_226 : UInt<1> connect _WIRE_226, _T_3485 connect _WIRE_222[3], _WIRE_226 connect _WIRE_116.iq_type, _WIRE_222 node _T_3486 = mux(_T_208, deq_vec[0][1].debug_pc, UInt<1>(0h0)) node _T_3487 = mux(_T_209, deq_vec[1][1].debug_pc, UInt<1>(0h0)) node _T_3488 = mux(_T_210, deq_vec[2][1].debug_pc, UInt<1>(0h0)) node _T_3489 = mux(_T_211, deq_vec[3][1].debug_pc, UInt<1>(0h0)) node _T_3490 = mux(_T_212, deq_vec[4][1].debug_pc, UInt<1>(0h0)) node _T_3491 = mux(_T_213, deq_vec[5][1].debug_pc, UInt<1>(0h0)) node _T_3492 = mux(_T_214, deq_vec[6][1].debug_pc, UInt<1>(0h0)) node _T_3493 = mux(_T_215, deq_vec[7][1].debug_pc, UInt<1>(0h0)) node _T_3494 = or(_T_3486, _T_3487) node _T_3495 = or(_T_3494, _T_3488) node _T_3496 = or(_T_3495, _T_3489) node _T_3497 = or(_T_3496, _T_3490) node _T_3498 = or(_T_3497, _T_3491) node _T_3499 = or(_T_3498, _T_3492) node _T_3500 = or(_T_3499, _T_3493) wire _WIRE_227 : UInt<40> connect _WIRE_227, _T_3500 connect _WIRE_116.debug_pc, _WIRE_227 node _T_3501 = mux(_T_208, deq_vec[0][1].is_rvc, UInt<1>(0h0)) node _T_3502 = mux(_T_209, deq_vec[1][1].is_rvc, UInt<1>(0h0)) node _T_3503 = mux(_T_210, deq_vec[2][1].is_rvc, UInt<1>(0h0)) node _T_3504 = mux(_T_211, deq_vec[3][1].is_rvc, UInt<1>(0h0)) node _T_3505 = mux(_T_212, deq_vec[4][1].is_rvc, UInt<1>(0h0)) node _T_3506 = mux(_T_213, deq_vec[5][1].is_rvc, UInt<1>(0h0)) node _T_3507 = mux(_T_214, deq_vec[6][1].is_rvc, UInt<1>(0h0)) node _T_3508 = mux(_T_215, deq_vec[7][1].is_rvc, UInt<1>(0h0)) node _T_3509 = or(_T_3501, _T_3502) node _T_3510 = or(_T_3509, _T_3503) node _T_3511 = or(_T_3510, _T_3504) node _T_3512 = or(_T_3511, _T_3505) node _T_3513 = or(_T_3512, _T_3506) node _T_3514 = or(_T_3513, _T_3507) node _T_3515 = or(_T_3514, _T_3508) wire _WIRE_228 : UInt<1> connect _WIRE_228, _T_3515 connect _WIRE_116.is_rvc, _WIRE_228 node _T_3516 = mux(_T_208, deq_vec[0][1].debug_inst, UInt<1>(0h0)) node _T_3517 = mux(_T_209, deq_vec[1][1].debug_inst, UInt<1>(0h0)) node _T_3518 = mux(_T_210, deq_vec[2][1].debug_inst, UInt<1>(0h0)) node _T_3519 = mux(_T_211, deq_vec[3][1].debug_inst, UInt<1>(0h0)) node _T_3520 = mux(_T_212, deq_vec[4][1].debug_inst, UInt<1>(0h0)) node _T_3521 = mux(_T_213, deq_vec[5][1].debug_inst, UInt<1>(0h0)) node _T_3522 = mux(_T_214, deq_vec[6][1].debug_inst, UInt<1>(0h0)) node _T_3523 = mux(_T_215, deq_vec[7][1].debug_inst, UInt<1>(0h0)) node _T_3524 = or(_T_3516, _T_3517) node _T_3525 = or(_T_3524, _T_3518) node _T_3526 = or(_T_3525, _T_3519) node _T_3527 = or(_T_3526, _T_3520) node _T_3528 = or(_T_3527, _T_3521) node _T_3529 = or(_T_3528, _T_3522) node _T_3530 = or(_T_3529, _T_3523) wire _WIRE_229 : UInt<32> connect _WIRE_229, _T_3530 connect _WIRE_116.debug_inst, _WIRE_229 node _T_3531 = mux(_T_208, deq_vec[0][1].inst, UInt<1>(0h0)) node _T_3532 = mux(_T_209, deq_vec[1][1].inst, UInt<1>(0h0)) node _T_3533 = mux(_T_210, deq_vec[2][1].inst, UInt<1>(0h0)) node _T_3534 = mux(_T_211, deq_vec[3][1].inst, UInt<1>(0h0)) node _T_3535 = mux(_T_212, deq_vec[4][1].inst, UInt<1>(0h0)) node _T_3536 = mux(_T_213, deq_vec[5][1].inst, UInt<1>(0h0)) node _T_3537 = mux(_T_214, deq_vec[6][1].inst, UInt<1>(0h0)) node _T_3538 = mux(_T_215, deq_vec[7][1].inst, UInt<1>(0h0)) node _T_3539 = or(_T_3531, _T_3532) node _T_3540 = or(_T_3539, _T_3533) node _T_3541 = or(_T_3540, _T_3534) node _T_3542 = or(_T_3541, _T_3535) node _T_3543 = or(_T_3542, _T_3536) node _T_3544 = or(_T_3543, _T_3537) node _T_3545 = or(_T_3544, _T_3538) wire _WIRE_230 : UInt<32> connect _WIRE_230, _T_3545 connect _WIRE_116.inst, _WIRE_230 connect _WIRE[1], _WIRE_116 connect io.deq.bits.uops[0].bits, _WIRE[0] connect io.deq.bits.uops[1].bits, _WIRE[1] node _io_deq_valid_T = or(deq_valids_0, deq_valids_1) connect io.deq.valid, _io_deq_valid_T when do_enq : connect tail, _T_15 node _T_3546 = or(in_mask[0], in_mask[1]) node _T_3547 = or(_T_3546, in_mask[2]) node _T_3548 = or(_T_3547, in_mask[3]) when _T_3548 : connect maybe_full, UInt<1>(0h1) when do_deq : node _head_T = bits(head, 6, 0) node _head_T_1 = bits(head, 7, 7) node _head_T_2 = cat(_head_T, _head_T_1) connect head, _head_T_2 connect maybe_full, UInt<1>(0h0) when io.clear : connect head, UInt<1>(0h1) connect tail, UInt<1>(0h1) connect maybe_full, UInt<1>(0h0) node _T_3549 = asUInt(reset) when _T_3549 : connect io.deq.bits.uops[0].valid, UInt<1>(0h0) connect io.deq.bits.uops[1].valid, UInt<1>(0h0)
module FetchBuffer( // @[fetch-buffer.scala:40:7] input clock, // @[fetch-buffer.scala:40:7] input reset, // @[fetch-buffer.scala:40:7] output io_enq_ready, // @[fetch-buffer.scala:45:14] input io_enq_valid, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pc, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_next_pc, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_next_fetch, // @[fetch-buffer.scala:45:14] input io_enq_bits_edge_inst_0, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_0, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_1, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_2, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_insts_3, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_0, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_1, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_2, // @[fetch-buffer.scala:45:14] input [31:0] io_enq_bits_exp_insts_3, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_0, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_1, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_2, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_pcs_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_sfbs_3, // @[fetch-buffer.scala:45:14] input [7:0] io_enq_bits_sfb_masks_0, // @[fetch-buffer.scala:45:14] input [7:0] io_enq_bits_sfb_masks_1, // @[fetch-buffer.scala:45:14] input [7:0] io_enq_bits_sfb_masks_2, // @[fetch-buffer.scala:45:14] input [7:0] io_enq_bits_sfb_masks_3, // @[fetch-buffer.scala:45:14] input [3:0] io_enq_bits_sfb_dests_0, // @[fetch-buffer.scala:45:14] input [3:0] io_enq_bits_sfb_dests_1, // @[fetch-buffer.scala:45:14] input [3:0] io_enq_bits_sfb_dests_2, // @[fetch-buffer.scala:45:14] input [3:0] io_enq_bits_sfb_dests_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowable_mask_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_shadowed_mask_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_cfi_idx_valid, // @[fetch-buffer.scala:45:14] input [1:0] io_enq_bits_cfi_idx_bits, // @[fetch-buffer.scala:45:14] input [2:0] io_enq_bits_cfi_type, // @[fetch-buffer.scala:45:14] input io_enq_bits_cfi_is_call, // @[fetch-buffer.scala:45:14] input io_enq_bits_cfi_is_ret, // @[fetch-buffer.scala:45:14] input io_enq_bits_cfi_npc_plus4, // @[fetch-buffer.scala:45:14] input [39:0] io_enq_bits_ras_top, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_ftq_idx, // @[fetch-buffer.scala:45:14] input [3:0] io_enq_bits_mask, // @[fetch-buffer.scala:45:14] input [3:0] io_enq_bits_br_mask, // @[fetch-buffer.scala:45:14] input [63:0] io_enq_bits_ghist_old_history, // @[fetch-buffer.scala:45:14] input io_enq_bits_ghist_current_saw_branch_not_taken, // @[fetch-buffer.scala:45:14] input io_enq_bits_ghist_new_saw_branch_not_taken, // @[fetch-buffer.scala:45:14] input io_enq_bits_ghist_new_saw_branch_taken, // @[fetch-buffer.scala:45:14] input [4:0] io_enq_bits_ghist_ras_idx, // @[fetch-buffer.scala:45:14] input io_enq_bits_lhist_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_xcpt_pf_if, // @[fetch-buffer.scala:45:14] input io_enq_bits_xcpt_ae_if, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_debug_if_oh_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_0, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_1, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_2, // @[fetch-buffer.scala:45:14] input io_enq_bits_bp_xcpt_if_oh_3, // @[fetch-buffer.scala:45:14] input io_enq_bits_end_half_valid, // @[fetch-buffer.scala:45:14] input [15:0] io_enq_bits_end_half_bits, // @[fetch-buffer.scala:45:14] input [119:0] io_enq_bits_bpd_meta_0, // @[fetch-buffer.scala:45:14] input [2:0] io_enq_bits_fsrc, // @[fetch-buffer.scala:45:14] input [2:0] io_enq_bits_tsrc, // @[fetch-buffer.scala:45:14] input io_deq_ready, // @[fetch-buffer.scala:45:14] output io_deq_valid, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_valid, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_0_bits_inst, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_0_bits_debug_inst, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_is_rvc, // @[fetch-buffer.scala:45:14] output [39:0] io_deq_bits_uops_0_bits_debug_pc, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_is_sfb, // @[fetch-buffer.scala:45:14] output [4:0] io_deq_bits_uops_0_bits_ftq_idx, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_edge_inst, // @[fetch-buffer.scala:45:14] output [5:0] io_deq_bits_uops_0_bits_pc_lob, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_taken, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_xcpt_pf_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_xcpt_ae_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_bp_debug_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_0_bits_bp_xcpt_if, // @[fetch-buffer.scala:45:14] output [2:0] io_deq_bits_uops_0_bits_debug_fsrc, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_valid, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_1_bits_inst, // @[fetch-buffer.scala:45:14] output [31:0] io_deq_bits_uops_1_bits_debug_inst, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_is_rvc, // @[fetch-buffer.scala:45:14] output [39:0] io_deq_bits_uops_1_bits_debug_pc, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_is_sfb, // @[fetch-buffer.scala:45:14] output [4:0] io_deq_bits_uops_1_bits_ftq_idx, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_edge_inst, // @[fetch-buffer.scala:45:14] output [5:0] io_deq_bits_uops_1_bits_pc_lob, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_taken, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_xcpt_pf_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_xcpt_ae_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_bp_debug_if, // @[fetch-buffer.scala:45:14] output io_deq_bits_uops_1_bits_bp_xcpt_if, // @[fetch-buffer.scala:45:14] output [2:0] io_deq_bits_uops_1_bits_debug_fsrc, // @[fetch-buffer.scala:45:14] input io_clear // @[fetch-buffer.scala:45:14] ); wire io_enq_valid_0 = io_enq_valid; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pc_0 = io_enq_bits_pc; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_next_pc_0 = io_enq_bits_next_pc; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_next_fetch_0 = io_enq_bits_next_fetch; // @[fetch-buffer.scala:40:7] wire io_enq_bits_edge_inst_0_0 = io_enq_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_0_0 = io_enq_bits_insts_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_1_0 = io_enq_bits_insts_1; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_2_0 = io_enq_bits_insts_2; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_insts_3_0 = io_enq_bits_insts_3; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_0_0 = io_enq_bits_exp_insts_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_1_0 = io_enq_bits_exp_insts_1; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_2_0 = io_enq_bits_exp_insts_2; // @[fetch-buffer.scala:40:7] wire [31:0] io_enq_bits_exp_insts_3_0 = io_enq_bits_exp_insts_3; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_0_0 = io_enq_bits_pcs_0; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_1_0 = io_enq_bits_pcs_1; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_2_0 = io_enq_bits_pcs_2; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_pcs_3_0 = io_enq_bits_pcs_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_0_0 = io_enq_bits_sfbs_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_1_0 = io_enq_bits_sfbs_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_2_0 = io_enq_bits_sfbs_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_sfbs_3_0 = io_enq_bits_sfbs_3; // @[fetch-buffer.scala:40:7] wire [7:0] io_enq_bits_sfb_masks_0_0 = io_enq_bits_sfb_masks_0; // @[fetch-buffer.scala:40:7] wire [7:0] io_enq_bits_sfb_masks_1_0 = io_enq_bits_sfb_masks_1; // @[fetch-buffer.scala:40:7] wire [7:0] io_enq_bits_sfb_masks_2_0 = io_enq_bits_sfb_masks_2; // @[fetch-buffer.scala:40:7] wire [7:0] io_enq_bits_sfb_masks_3_0 = io_enq_bits_sfb_masks_3; // @[fetch-buffer.scala:40:7] wire [3:0] io_enq_bits_sfb_dests_0_0 = io_enq_bits_sfb_dests_0; // @[fetch-buffer.scala:40:7] wire [3:0] io_enq_bits_sfb_dests_1_0 = io_enq_bits_sfb_dests_1; // @[fetch-buffer.scala:40:7] wire [3:0] io_enq_bits_sfb_dests_2_0 = io_enq_bits_sfb_dests_2; // @[fetch-buffer.scala:40:7] wire [3:0] io_enq_bits_sfb_dests_3_0 = io_enq_bits_sfb_dests_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_0_0 = io_enq_bits_shadowable_mask_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_1_0 = io_enq_bits_shadowable_mask_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_2_0 = io_enq_bits_shadowable_mask_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowable_mask_3_0 = io_enq_bits_shadowable_mask_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_0_0 = io_enq_bits_shadowed_mask_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_1_0 = io_enq_bits_shadowed_mask_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_2_0 = io_enq_bits_shadowed_mask_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_shadowed_mask_3_0 = io_enq_bits_shadowed_mask_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_cfi_idx_valid_0 = io_enq_bits_cfi_idx_valid; // @[fetch-buffer.scala:40:7] wire [1:0] io_enq_bits_cfi_idx_bits_0 = io_enq_bits_cfi_idx_bits; // @[fetch-buffer.scala:40:7] wire [2:0] io_enq_bits_cfi_type_0 = io_enq_bits_cfi_type; // @[fetch-buffer.scala:40:7] wire io_enq_bits_cfi_is_call_0 = io_enq_bits_cfi_is_call; // @[fetch-buffer.scala:40:7] wire io_enq_bits_cfi_is_ret_0 = io_enq_bits_cfi_is_ret; // @[fetch-buffer.scala:40:7] wire io_enq_bits_cfi_npc_plus4_0 = io_enq_bits_cfi_npc_plus4; // @[fetch-buffer.scala:40:7] wire [39:0] io_enq_bits_ras_top_0 = io_enq_bits_ras_top; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_ftq_idx_0 = io_enq_bits_ftq_idx; // @[fetch-buffer.scala:40:7] wire [3:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[fetch-buffer.scala:40:7] wire [3:0] io_enq_bits_br_mask_0 = io_enq_bits_br_mask; // @[fetch-buffer.scala:40:7] wire [63:0] io_enq_bits_ghist_old_history_0 = io_enq_bits_ghist_old_history; // @[fetch-buffer.scala:40:7] wire io_enq_bits_ghist_current_saw_branch_not_taken_0 = io_enq_bits_ghist_current_saw_branch_not_taken; // @[fetch-buffer.scala:40:7] wire io_enq_bits_ghist_new_saw_branch_not_taken_0 = io_enq_bits_ghist_new_saw_branch_not_taken; // @[fetch-buffer.scala:40:7] wire io_enq_bits_ghist_new_saw_branch_taken_0 = io_enq_bits_ghist_new_saw_branch_taken; // @[fetch-buffer.scala:40:7] wire [4:0] io_enq_bits_ghist_ras_idx_0 = io_enq_bits_ghist_ras_idx; // @[fetch-buffer.scala:40:7] wire io_enq_bits_lhist_0_0 = io_enq_bits_lhist_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_xcpt_pf_if_0 = io_enq_bits_xcpt_pf_if; // @[fetch-buffer.scala:40:7] wire io_enq_bits_xcpt_ae_if_0 = io_enq_bits_xcpt_ae_if; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_0_0 = io_enq_bits_bp_debug_if_oh_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_1_0 = io_enq_bits_bp_debug_if_oh_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_2_0 = io_enq_bits_bp_debug_if_oh_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_debug_if_oh_3_0 = io_enq_bits_bp_debug_if_oh_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_0_0 = io_enq_bits_bp_xcpt_if_oh_0; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_1_0 = io_enq_bits_bp_xcpt_if_oh_1; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_2_0 = io_enq_bits_bp_xcpt_if_oh_2; // @[fetch-buffer.scala:40:7] wire io_enq_bits_bp_xcpt_if_oh_3_0 = io_enq_bits_bp_xcpt_if_oh_3; // @[fetch-buffer.scala:40:7] wire io_enq_bits_end_half_valid_0 = io_enq_bits_end_half_valid; // @[fetch-buffer.scala:40:7] wire [15:0] io_enq_bits_end_half_bits_0 = io_enq_bits_end_half_bits; // @[fetch-buffer.scala:40:7] wire [119:0] io_enq_bits_bpd_meta_0_0 = io_enq_bits_bpd_meta_0; // @[fetch-buffer.scala:40:7] wire [2:0] io_enq_bits_fsrc_0 = io_enq_bits_fsrc; // @[fetch-buffer.scala:40:7] wire [2:0] io_enq_bits_tsrc_0 = io_enq_bits_tsrc; // @[fetch-buffer.scala:40:7] wire io_deq_ready_0 = io_deq_ready; // @[fetch-buffer.scala:40:7] wire io_clear_0 = io_clear; // @[fetch-buffer.scala:40:7] wire _tail_collisions_T_6 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_14 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_22 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_30 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_38 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_46 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_54 = 1'h1; // @[fetch-buffer.scala:155:61] wire _tail_collisions_T_62 = 1'h1; // @[fetch-buffer.scala:155:61] wire [63:0] io_deq_bits_uops_0_bits_exc_cause = 64'h0; // @[fetch-buffer.scala:40:7] wire [63:0] io_deq_bits_uops_1_bits_exc_cause = 64'h0; // @[fetch-buffer.scala:40:7] wire [63:0] deq_vec_0_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_0_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_1_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_1_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_2_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_2_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_3_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_3_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_4_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_4_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_5_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_5_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_6_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_6_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_7_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] deq_vec_7_1_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21] wire [63:0] in_uops_0_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_1_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_2_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [63:0] in_uops_3_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21] wire [6:0] io_deq_bits_uops_0_bits_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_prs1 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_prs2 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_prs3 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_0_bits_stale_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_prs1 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_prs2 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_prs3 = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] io_deq_bits_uops_1_bits_stale_pdst = 7'h0; // @[fetch-buffer.scala:40:7] wire [6:0] deq_vec_0_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_0_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_1_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_2_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_3_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_4_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_5_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_6_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_prs1 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_prs2 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_prs3 = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] deq_vec_7_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:59:21] wire [6:0] in_uops_0_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_0_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_1_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_2_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_prs1 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_prs2 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_prs3 = 7'h0; // @[fetch-buffer.scala:88:21] wire [6:0] in_uops_3_stale_pdst = 7'h0; // @[fetch-buffer.scala:88:21] wire [5:0] io_deq_bits_uops_0_bits_rob_idx = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_0_bits_ldst = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_0_bits_lrs1 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_0_bits_lrs2 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_0_bits_lrs3 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_rob_idx = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_ldst = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_lrs1 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_lrs2 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_lrs3 = 6'h0; // @[fetch-buffer.scala:40:7] wire [5:0] deq_vec_0_0_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_1_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_0_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_0_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_1_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_1_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_0_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_1_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_2_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_0_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_1_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_3_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_0_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_1_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_4_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_0_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_1_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_5_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_0_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_1_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_6_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_0_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_1_rob_idx = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_1_ldst = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_1_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_1_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] deq_vec_7_1_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21] wire [5:0] in_uops_0_rob_idx = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_0_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_0_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_0_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_0_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_rob_idx = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_rob_idx = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_rob_idx = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_ldst = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21] wire [19:0] io_deq_bits_uops_0_bits_imm_packed = 20'h0; // @[fetch-buffer.scala:40:7] wire [19:0] io_deq_bits_uops_1_bits_imm_packed = 20'h0; // @[fetch-buffer.scala:40:7] wire [19:0] deq_vec_0_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_0_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_1_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_1_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_2_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_2_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_3_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_3_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_4_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_4_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_5_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_5_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_6_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_6_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_7_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] deq_vec_7_1_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21] wire [19:0] in_uops_0_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_1_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_2_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [19:0] in_uops_3_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21] wire [4:0] io_deq_bits_uops_0_bits_pimm = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_ppred = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_mem_cmd = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_fcn_op = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_pimm = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_ppred = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_mem_cmd = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_fcn_op = 5'h0; // @[fetch-buffer.scala:40:7] wire [4:0] deq_vec_0_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_0_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_1_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_2_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_3_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_4_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_5_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_6_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_0_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_pimm = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_ppred = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] deq_vec_7_1_fcn_op = 5'h0; // @[fetch-buffer.scala:59:21] wire [4:0] in_uops_0_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_0_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_0_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_1_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_2_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_pimm = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_ppred = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21] wire [4:0] in_uops_3_fcn_op = 5'h0; // @[fetch-buffer.scala:88:21] wire [2:0] io_deq_bits_uops_0_bits_imm_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_op2_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_csr_cmd = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_fp_rm = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_debug_tsrc = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_imm_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_op2_sel = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_csr_cmd = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_fp_rm = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_debug_tsrc = 3'h0; // @[fetch-buffer.scala:40:7] wire [2:0] deq_vec_0_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_0_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_1_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_2_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_3_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_4_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_5_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_6_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_fp_rm = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] deq_vec_7_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:59:21] wire [2:0] in_uops_0_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_0_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_1_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_2_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_fp_rm = 3'h0; // @[fetch-buffer.scala:88:21] wire [2:0] in_uops_3_debug_tsrc = 3'h0; // @[fetch-buffer.scala:88:21] wire [3:0] io_deq_bits_uops_0_bits_br_tag = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_0_bits_br_type = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_0_bits_ldq_idx = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_0_bits_stq_idx = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_1_bits_br_tag = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_1_bits_br_type = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_1_bits_ldq_idx = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] io_deq_bits_uops_1_bits_stq_idx = 4'h0; // @[fetch-buffer.scala:40:7] wire [3:0] deq_vec_0_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_0_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_0_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_1_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_0_1_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_0_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_0_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_1_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_1_1_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_0_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_0_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_1_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_2_1_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_0_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_0_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_1_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_3_1_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_0_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_0_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_1_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_4_1_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_0_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_0_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_1_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_5_1_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_0_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_0_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_1_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_6_1_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_0_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_0_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_0_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_0_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_1_br_tag = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_1_br_type = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_1_ldq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] deq_vec_7_1_stq_idx = 4'h0; // @[fetch-buffer.scala:59:21] wire [3:0] in_uops_0_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_0_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_0_ldq_idx = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_0_stq_idx = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_1_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_1_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_1_ldq_idx = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_1_stq_idx = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_2_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_2_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_2_ldq_idx = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_2_stq_idx = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_3_br_tag = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_3_br_type = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_3_ldq_idx = 4'h0; // @[fetch-buffer.scala:88:21] wire [3:0] in_uops_3_stq_idx = 4'h0; // @[fetch-buffer.scala:88:21] wire [11:0] io_deq_bits_uops_0_bits_br_mask = 12'h0; // @[fetch-buffer.scala:40:7] wire [11:0] io_deq_bits_uops_1_bits_br_mask = 12'h0; // @[fetch-buffer.scala:40:7] wire [11:0] deq_vec_0_0_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_0_1_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_1_0_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_1_1_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_2_0_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_2_1_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_3_0_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_3_1_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_4_0_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_4_1_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_5_0_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_5_1_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_6_0_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_6_1_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_7_0_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] deq_vec_7_1_br_mask = 12'h0; // @[fetch-buffer.scala:59:21] wire [11:0] in_uops_0_br_mask = 12'h0; // @[fetch-buffer.scala:88:21] wire [11:0] in_uops_1_br_mask = 12'h0; // @[fetch-buffer.scala:88:21] wire [11:0] in_uops_2_br_mask = 12'h0; // @[fetch-buffer.scala:88:21] wire [11:0] in_uops_3_br_mask = 12'h0; // @[fetch-buffer.scala:88:21] wire [1:0] io_deq_bits_uops_0_bits_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_dis_col_sel = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_op1_sel = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_rxq_idx = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_mem_size = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_dst_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_0_bits_fp_typ = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_dis_col_sel = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_op1_sel = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_rxq_idx = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_mem_size = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_dst_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] io_deq_bits_uops_1_bits_fp_typ = 2'h0; // @[fetch-buffer.scala:40:7] wire [1:0] deq_vec_0_0_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_0_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_1_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_2_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_3_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_4_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_5_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_6_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_0_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_dis_col_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_mem_size = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] deq_vec_7_1_fp_typ = 2'h0; // @[fetch-buffer.scala:59:21] wire [1:0] in_uops_0_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_dis_col_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_0_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_dis_col_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_1_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_dis_col_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_2_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_iw_p1_speculative_child = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_iw_p2_speculative_child = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_dis_col_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_fp_ctrl_typeTagIn = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_fp_ctrl_typeTagOut = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_mem_size = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21] wire [1:0] in_uops_3_fp_typ = 2'h0; // @[fetch-buffer.scala:88:21] wire io_deq_bits_uops_0_bits_iq_type_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iq_type_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iq_type_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iq_type_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_4 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_5 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_6 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_7 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_8 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fu_code_9 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_issued = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_fence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_fencei = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_sfence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_amo = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_eret = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_rocc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_mov = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_imm_rename = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_prs1_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_prs2_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_prs3_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_ppred_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_exception = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_mem_signed = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_uses_ldq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_uses_stq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_unique = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_flush_on_commit = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_frs3_en = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fcn_dw = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_fp_val = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iq_type_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iq_type_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iq_type_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iq_type_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_0 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_4 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_5 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_6 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_7 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_8 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fu_code_9 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_issued = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_fence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_fencei = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_sfence = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_amo = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_eret = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_rocc = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_mov = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_imm_rename = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_prs1_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_prs2_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_prs3_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_ppred_busy = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_exception = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_mem_signed = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_uses_ldq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_uses_stq = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_unique = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_flush_on_commit = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_frs3_en = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fcn_dw = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_fp_val = 1'h0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:40:7] wire deq_vec_0_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_0_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_1_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_2_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_3_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_4_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_5_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_6_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_issued = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_fence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_sfence = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_amo = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_eret = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_rocc = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_mov = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_imm_rename = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_exception = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_is_unique = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_fp_val = 1'h0; // @[fetch-buffer.scala:59:21] wire deq_vec_7_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21] wire do_enq; // @[fetch-buffer.scala:82:16] wire in_uops_0_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iq_type_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iq_type_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iq_type_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iq_type_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_0 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_4 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_5 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_6 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_7 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_8 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fu_code_9 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_issued = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_issued_partial_agen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_issued_partial_dgen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_p1_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_p2_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_iw_p3_bypass_hint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_fence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_sfence = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_amo = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_eret = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_rocc = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_mov = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_imm_rename = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_ldst = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_wen = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_ren1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_ren2 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_ren3 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_swap12 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_swap23 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_fromint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_toint = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_fastpipe = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_fma = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_div = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_sqrt = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_wflags = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_ctrl_vec = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_exception = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_unique = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_fp_val = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_3_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21] wire in_uops_0_edge_inst = io_enq_bits_edge_inst_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_0_debug_inst = io_enq_bits_insts_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_1_debug_inst = io_enq_bits_insts_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_2_debug_inst = io_enq_bits_insts_2_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_3_debug_inst = io_enq_bits_insts_3_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_0_inst = io_enq_bits_exp_insts_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_1_inst = io_enq_bits_exp_insts_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_2_inst = io_enq_bits_exp_insts_2_0; // @[fetch-buffer.scala:40:7, :88:21] wire [31:0] in_uops_3_inst = io_enq_bits_exp_insts_3_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_0_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_1_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_2_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire [4:0] in_uops_3_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_0_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_1_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_2_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_3_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_0_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_1_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_2_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_3_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_0_bp_debug_if = io_enq_bits_bp_debug_if_oh_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_1_bp_debug_if = io_enq_bits_bp_debug_if_oh_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_2_bp_debug_if = io_enq_bits_bp_debug_if_oh_2_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_3_bp_debug_if = io_enq_bits_bp_debug_if_oh_3_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_0_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_0_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_1_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_1_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_2_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_2_0; // @[fetch-buffer.scala:40:7, :88:21] wire in_uops_3_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_3_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_0_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_1_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_2_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire [2:0] in_uops_3_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21] wire _io_deq_valid_T; // @[fetch-buffer.scala:170:38] wire io_enq_ready_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_0_bits_inst_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_0_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] wire [39:0] io_deq_bits_uops_0_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_0_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_0_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_taken_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_0_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_0_valid_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_1_bits_inst_0; // @[fetch-buffer.scala:40:7] wire [31:0] io_deq_bits_uops_1_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] wire [39:0] io_deq_bits_uops_1_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] wire [4:0] io_deq_bits_uops_1_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] wire [5:0] io_deq_bits_uops_1_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_taken_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] wire [2:0] io_deq_bits_uops_1_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] wire io_deq_bits_uops_1_valid_0; // @[fetch-buffer.scala:40:7] wire io_deq_valid_0; // @[fetch-buffer.scala:40:7] reg [31:0] fb_uop_ram_0_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_0_inst = fb_uop_ram_0_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_0_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_0_debug_inst = fb_uop_ram_0_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_is_rvc = fb_uop_ram_0_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_0_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_0_0_debug_pc = fb_uop_ram_0_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_is_sfb = fb_uop_ram_0_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_0_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_0_0_ftq_idx = fb_uop_ram_0_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_edge_inst = fb_uop_ram_0_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_0_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_0_0_pc_lob = fb_uop_ram_0_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_taken = fb_uop_ram_0_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_xcpt_pf_if = fb_uop_ram_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_xcpt_ae_if = fb_uop_ram_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_bp_debug_if = fb_uop_ram_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_0_bp_xcpt_if = fb_uop_ram_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_0_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_0_0_debug_fsrc = fb_uop_ram_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_1_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_1_inst = fb_uop_ram_1_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_1_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_0_1_debug_inst = fb_uop_ram_1_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_is_rvc = fb_uop_ram_1_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_1_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_0_1_debug_pc = fb_uop_ram_1_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_is_sfb = fb_uop_ram_1_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_1_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_0_1_ftq_idx = fb_uop_ram_1_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_edge_inst = fb_uop_ram_1_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_1_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_0_1_pc_lob = fb_uop_ram_1_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_taken = fb_uop_ram_1_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_xcpt_pf_if = fb_uop_ram_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_xcpt_ae_if = fb_uop_ram_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_bp_debug_if = fb_uop_ram_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_0_1_bp_xcpt_if = fb_uop_ram_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_1_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_0_1_debug_fsrc = fb_uop_ram_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_2_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_0_inst = fb_uop_ram_2_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_2_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_0_debug_inst = fb_uop_ram_2_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_is_rvc = fb_uop_ram_2_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_2_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_1_0_debug_pc = fb_uop_ram_2_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_is_sfb = fb_uop_ram_2_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_2_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_1_0_ftq_idx = fb_uop_ram_2_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_edge_inst = fb_uop_ram_2_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_2_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_1_0_pc_lob = fb_uop_ram_2_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_taken = fb_uop_ram_2_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_xcpt_pf_if = fb_uop_ram_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_xcpt_ae_if = fb_uop_ram_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_bp_debug_if = fb_uop_ram_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_0_bp_xcpt_if = fb_uop_ram_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_2_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_1_0_debug_fsrc = fb_uop_ram_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_3_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_1_inst = fb_uop_ram_3_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_3_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_1_1_debug_inst = fb_uop_ram_3_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_is_rvc = fb_uop_ram_3_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_3_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_1_1_debug_pc = fb_uop_ram_3_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_is_sfb = fb_uop_ram_3_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_3_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_1_1_ftq_idx = fb_uop_ram_3_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_edge_inst = fb_uop_ram_3_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_3_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_1_1_pc_lob = fb_uop_ram_3_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_taken = fb_uop_ram_3_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_xcpt_pf_if = fb_uop_ram_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_xcpt_ae_if = fb_uop_ram_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_bp_debug_if = fb_uop_ram_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_1_1_bp_xcpt_if = fb_uop_ram_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_3_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_1_1_debug_fsrc = fb_uop_ram_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_4_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_0_inst = fb_uop_ram_4_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_4_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_0_debug_inst = fb_uop_ram_4_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_is_rvc = fb_uop_ram_4_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_4_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_2_0_debug_pc = fb_uop_ram_4_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_is_sfb = fb_uop_ram_4_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_4_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_2_0_ftq_idx = fb_uop_ram_4_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_edge_inst = fb_uop_ram_4_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_4_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_2_0_pc_lob = fb_uop_ram_4_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_taken = fb_uop_ram_4_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_xcpt_pf_if = fb_uop_ram_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_xcpt_ae_if = fb_uop_ram_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_bp_debug_if = fb_uop_ram_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_0_bp_xcpt_if = fb_uop_ram_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_4_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_2_0_debug_fsrc = fb_uop_ram_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_5_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_1_inst = fb_uop_ram_5_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_5_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_2_1_debug_inst = fb_uop_ram_5_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_is_rvc = fb_uop_ram_5_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_5_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_2_1_debug_pc = fb_uop_ram_5_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_is_sfb = fb_uop_ram_5_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_5_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_2_1_ftq_idx = fb_uop_ram_5_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_edge_inst = fb_uop_ram_5_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_5_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_2_1_pc_lob = fb_uop_ram_5_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_taken = fb_uop_ram_5_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_xcpt_pf_if = fb_uop_ram_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_xcpt_ae_if = fb_uop_ram_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_bp_debug_if = fb_uop_ram_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_2_1_bp_xcpt_if = fb_uop_ram_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_5_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_2_1_debug_fsrc = fb_uop_ram_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_6_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_0_inst = fb_uop_ram_6_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_6_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_0_debug_inst = fb_uop_ram_6_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_is_rvc = fb_uop_ram_6_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_6_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_3_0_debug_pc = fb_uop_ram_6_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_is_sfb = fb_uop_ram_6_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_6_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_3_0_ftq_idx = fb_uop_ram_6_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_edge_inst = fb_uop_ram_6_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_6_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_3_0_pc_lob = fb_uop_ram_6_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_taken = fb_uop_ram_6_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_xcpt_pf_if = fb_uop_ram_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_xcpt_ae_if = fb_uop_ram_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_bp_debug_if = fb_uop_ram_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_0_bp_xcpt_if = fb_uop_ram_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_6_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_3_0_debug_fsrc = fb_uop_ram_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_7_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_1_inst = fb_uop_ram_7_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_7_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_3_1_debug_inst = fb_uop_ram_7_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_is_rvc = fb_uop_ram_7_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_7_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_3_1_debug_pc = fb_uop_ram_7_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_is_sfb = fb_uop_ram_7_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_7_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_3_1_ftq_idx = fb_uop_ram_7_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_edge_inst = fb_uop_ram_7_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_7_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_3_1_pc_lob = fb_uop_ram_7_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_taken = fb_uop_ram_7_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_xcpt_pf_if = fb_uop_ram_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_xcpt_ae_if = fb_uop_ram_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_bp_debug_if = fb_uop_ram_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_3_1_bp_xcpt_if = fb_uop_ram_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_7_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_3_1_debug_fsrc = fb_uop_ram_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_8_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_0_inst = fb_uop_ram_8_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_8_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_0_debug_inst = fb_uop_ram_8_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_is_rvc = fb_uop_ram_8_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_8_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_4_0_debug_pc = fb_uop_ram_8_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_is_sfb = fb_uop_ram_8_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_8_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_4_0_ftq_idx = fb_uop_ram_8_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_edge_inst = fb_uop_ram_8_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_8_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_4_0_pc_lob = fb_uop_ram_8_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_taken = fb_uop_ram_8_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_xcpt_pf_if = fb_uop_ram_8_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_xcpt_ae_if = fb_uop_ram_8_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_bp_debug_if = fb_uop_ram_8_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_8_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_0_bp_xcpt_if = fb_uop_ram_8_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_8_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_4_0_debug_fsrc = fb_uop_ram_8_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_9_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_1_inst = fb_uop_ram_9_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_9_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_4_1_debug_inst = fb_uop_ram_9_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_is_rvc = fb_uop_ram_9_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_9_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_4_1_debug_pc = fb_uop_ram_9_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_is_sfb = fb_uop_ram_9_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_9_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_4_1_ftq_idx = fb_uop_ram_9_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_edge_inst = fb_uop_ram_9_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_9_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_4_1_pc_lob = fb_uop_ram_9_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_taken = fb_uop_ram_9_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_xcpt_pf_if = fb_uop_ram_9_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_xcpt_ae_if = fb_uop_ram_9_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_bp_debug_if = fb_uop_ram_9_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_9_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_4_1_bp_xcpt_if = fb_uop_ram_9_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_9_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_4_1_debug_fsrc = fb_uop_ram_9_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_10_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_0_inst = fb_uop_ram_10_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_10_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_0_debug_inst = fb_uop_ram_10_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_is_rvc = fb_uop_ram_10_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_10_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_5_0_debug_pc = fb_uop_ram_10_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_is_sfb = fb_uop_ram_10_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_10_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_5_0_ftq_idx = fb_uop_ram_10_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_edge_inst = fb_uop_ram_10_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_10_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_5_0_pc_lob = fb_uop_ram_10_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_taken = fb_uop_ram_10_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_xcpt_pf_if = fb_uop_ram_10_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_xcpt_ae_if = fb_uop_ram_10_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_bp_debug_if = fb_uop_ram_10_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_10_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_0_bp_xcpt_if = fb_uop_ram_10_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_10_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_5_0_debug_fsrc = fb_uop_ram_10_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_11_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_1_inst = fb_uop_ram_11_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_11_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_5_1_debug_inst = fb_uop_ram_11_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_is_rvc = fb_uop_ram_11_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_11_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_5_1_debug_pc = fb_uop_ram_11_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_is_sfb = fb_uop_ram_11_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_11_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_5_1_ftq_idx = fb_uop_ram_11_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_edge_inst = fb_uop_ram_11_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_11_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_5_1_pc_lob = fb_uop_ram_11_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_taken = fb_uop_ram_11_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_xcpt_pf_if = fb_uop_ram_11_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_xcpt_ae_if = fb_uop_ram_11_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_bp_debug_if = fb_uop_ram_11_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_11_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_5_1_bp_xcpt_if = fb_uop_ram_11_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_11_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_5_1_debug_fsrc = fb_uop_ram_11_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_12_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_0_inst = fb_uop_ram_12_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_12_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_0_debug_inst = fb_uop_ram_12_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_is_rvc = fb_uop_ram_12_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_12_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_6_0_debug_pc = fb_uop_ram_12_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_is_sfb = fb_uop_ram_12_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_12_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_6_0_ftq_idx = fb_uop_ram_12_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_edge_inst = fb_uop_ram_12_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_12_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_6_0_pc_lob = fb_uop_ram_12_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_taken = fb_uop_ram_12_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_xcpt_pf_if = fb_uop_ram_12_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_xcpt_ae_if = fb_uop_ram_12_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_bp_debug_if = fb_uop_ram_12_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_12_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_0_bp_xcpt_if = fb_uop_ram_12_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_12_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_6_0_debug_fsrc = fb_uop_ram_12_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_13_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_1_inst = fb_uop_ram_13_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_13_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_6_1_debug_inst = fb_uop_ram_13_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_is_rvc = fb_uop_ram_13_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_13_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_6_1_debug_pc = fb_uop_ram_13_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_is_sfb = fb_uop_ram_13_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_13_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_6_1_ftq_idx = fb_uop_ram_13_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_edge_inst = fb_uop_ram_13_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_13_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_6_1_pc_lob = fb_uop_ram_13_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_taken = fb_uop_ram_13_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_xcpt_pf_if = fb_uop_ram_13_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_xcpt_ae_if = fb_uop_ram_13_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_bp_debug_if = fb_uop_ram_13_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_13_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_6_1_bp_xcpt_if = fb_uop_ram_13_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_13_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_6_1_debug_fsrc = fb_uop_ram_13_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_14_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_0_inst = fb_uop_ram_14_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_14_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_0_debug_inst = fb_uop_ram_14_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_is_rvc = fb_uop_ram_14_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_14_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_7_0_debug_pc = fb_uop_ram_14_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_is_sfb = fb_uop_ram_14_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_14_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_7_0_ftq_idx = fb_uop_ram_14_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_edge_inst = fb_uop_ram_14_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_14_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_7_0_pc_lob = fb_uop_ram_14_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_taken = fb_uop_ram_14_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_xcpt_pf_if = fb_uop_ram_14_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_xcpt_ae_if = fb_uop_ram_14_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_bp_debug_if = fb_uop_ram_14_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_14_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_0_bp_xcpt_if = fb_uop_ram_14_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_14_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_7_0_debug_fsrc = fb_uop_ram_14_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_15_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_1_inst = fb_uop_ram_15_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [31:0] fb_uop_ram_15_debug_inst; // @[fetch-buffer.scala:57:16] wire [31:0] deq_vec_7_1_debug_inst = fb_uop_ram_15_debug_inst; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_is_rvc; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_is_rvc = fb_uop_ram_15_is_rvc; // @[fetch-buffer.scala:57:16, :59:21] reg [39:0] fb_uop_ram_15_debug_pc; // @[fetch-buffer.scala:57:16] wire [39:0] deq_vec_7_1_debug_pc = fb_uop_ram_15_debug_pc; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_is_sfb; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_is_sfb = fb_uop_ram_15_is_sfb; // @[fetch-buffer.scala:57:16, :59:21] reg [4:0] fb_uop_ram_15_ftq_idx; // @[fetch-buffer.scala:57:16] wire [4:0] deq_vec_7_1_ftq_idx = fb_uop_ram_15_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_edge_inst; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_edge_inst = fb_uop_ram_15_edge_inst; // @[fetch-buffer.scala:57:16, :59:21] reg [5:0] fb_uop_ram_15_pc_lob; // @[fetch-buffer.scala:57:16] wire [5:0] deq_vec_7_1_pc_lob = fb_uop_ram_15_pc_lob; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_taken; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_taken = fb_uop_ram_15_taken; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_xcpt_pf_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_xcpt_pf_if = fb_uop_ram_15_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_xcpt_ae_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_xcpt_ae_if = fb_uop_ram_15_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_bp_debug_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_bp_debug_if = fb_uop_ram_15_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21] reg fb_uop_ram_15_bp_xcpt_if; // @[fetch-buffer.scala:57:16] wire deq_vec_7_1_bp_xcpt_if = fb_uop_ram_15_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21] reg [2:0] fb_uop_ram_15_debug_fsrc; // @[fetch-buffer.scala:57:16] wire [2:0] deq_vec_7_1_debug_fsrc = fb_uop_ram_15_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21] reg [7:0] head; // @[fetch-buffer.scala:61:21] reg [15:0] tail; // @[fetch-buffer.scala:62:21] wire [15:0] enq_idxs_0 = tail; // @[fetch-buffer.scala:62:21, :128:22] reg maybe_full; // @[fetch-buffer.scala:64:27] wire [14:0] _might_hit_head_T = tail[14:0]; // @[fetch-buffer.scala:62:21, :75:11] wire _might_hit_head_T_1 = tail[15]; // @[fetch-buffer.scala:62:21, :75:24] wire _at_head_T_15 = tail[15]; // @[fetch-buffer.scala:62:21, :75:24, :80:31] wire [15:0] _might_hit_head_T_2 = {_might_hit_head_T, _might_hit_head_T_1}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_3 = _might_hit_head_T_2[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_0 = _might_hit_head_T_3; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_4 = _might_hit_head_T_2[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_5 = _might_hit_head_T_2[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1 = _might_hit_head_T_5; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_6 = _might_hit_head_T_2[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_7 = _might_hit_head_T_2[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2 = _might_hit_head_T_7; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_8 = _might_hit_head_T_2[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_9 = _might_hit_head_T_2[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_3 = _might_hit_head_T_9; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_10 = _might_hit_head_T_2[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_11 = _might_hit_head_T_2[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_4 = _might_hit_head_T_11; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_12 = _might_hit_head_T_2[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_13 = _might_hit_head_T_2[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_5 = _might_hit_head_T_13; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_14 = _might_hit_head_T_2[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_15 = _might_hit_head_T_2[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_6 = _might_hit_head_T_15; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_16 = _might_hit_head_T_2[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_17 = _might_hit_head_T_2[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_7 = _might_hit_head_T_17; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_18 = _might_hit_head_T_2[15]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo = {_might_hit_head_WIRE_1, _might_hit_head_WIRE_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi = {_might_hit_head_WIRE_3, _might_hit_head_WIRE_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo = {might_hit_head_lo_hi, might_hit_head_lo_lo}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo = {_might_hit_head_WIRE_5, _might_hit_head_WIRE_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi = {_might_hit_head_WIRE_7, _might_hit_head_WIRE_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi = {might_hit_head_hi_hi, might_hit_head_hi_lo}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_19 = {might_hit_head_hi, might_hit_head_lo}; // @[fetch-buffer.scala:79:63] wire [13:0] _might_hit_head_T_20 = tail[13:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [1:0] _might_hit_head_T_21 = tail[15:14]; // @[fetch-buffer.scala:62:21, :75:24] wire [15:0] _might_hit_head_T_22 = {_might_hit_head_T_20, _might_hit_head_T_21}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_23 = _might_hit_head_T_22[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_0 = _might_hit_head_T_23; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_24 = _might_hit_head_T_22[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_25 = _might_hit_head_T_22[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_1 = _might_hit_head_T_25; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_26 = _might_hit_head_T_22[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_27 = _might_hit_head_T_22[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_2 = _might_hit_head_T_27; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_28 = _might_hit_head_T_22[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_29 = _might_hit_head_T_22[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_3 = _might_hit_head_T_29; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_30 = _might_hit_head_T_22[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_31 = _might_hit_head_T_22[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_4 = _might_hit_head_T_31; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_32 = _might_hit_head_T_22[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_33 = _might_hit_head_T_22[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_5 = _might_hit_head_T_33; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_34 = _might_hit_head_T_22[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_35 = _might_hit_head_T_22[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_6 = _might_hit_head_T_35; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_36 = _might_hit_head_T_22[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_37 = _might_hit_head_T_22[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_1_7 = _might_hit_head_T_37; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_38 = _might_hit_head_T_22[15]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_1 = {_might_hit_head_WIRE_1_1, _might_hit_head_WIRE_1_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_1 = {_might_hit_head_WIRE_1_3, _might_hit_head_WIRE_1_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_1 = {might_hit_head_lo_hi_1, might_hit_head_lo_lo_1}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_1 = {_might_hit_head_WIRE_1_5, _might_hit_head_WIRE_1_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_1 = {_might_hit_head_WIRE_1_7, _might_hit_head_WIRE_1_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_1 = {might_hit_head_hi_hi_1, might_hit_head_hi_lo_1}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_39 = {might_hit_head_hi_1, might_hit_head_lo_1}; // @[fetch-buffer.scala:79:63] wire [12:0] _might_hit_head_T_40 = tail[12:0]; // @[fetch-buffer.scala:62:21, :75:11] wire [2:0] _might_hit_head_T_41 = tail[15:13]; // @[fetch-buffer.scala:62:21, :75:24] wire [15:0] _might_hit_head_T_42 = {_might_hit_head_T_40, _might_hit_head_T_41}; // @[fetch-buffer.scala:75:{8,11,24}] wire _might_hit_head_T_43 = _might_hit_head_T_42[0]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_0 = _might_hit_head_T_43; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_44 = _might_hit_head_T_42[1]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_45 = _might_hit_head_T_42[2]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_1 = _might_hit_head_T_45; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_46 = _might_hit_head_T_42[3]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_47 = _might_hit_head_T_42[4]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_2 = _might_hit_head_T_47; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_48 = _might_hit_head_T_42[5]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_49 = _might_hit_head_T_42[6]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_3 = _might_hit_head_T_49; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_50 = _might_hit_head_T_42[7]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_51 = _might_hit_head_T_42[8]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_4 = _might_hit_head_T_51; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_52 = _might_hit_head_T_42[9]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_53 = _might_hit_head_T_42[10]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_5 = _might_hit_head_T_53; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_54 = _might_hit_head_T_42[11]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_55 = _might_hit_head_T_42[12]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_6 = _might_hit_head_T_55; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_56 = _might_hit_head_T_42[13]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_T_57 = _might_hit_head_T_42[14]; // @[fetch-buffer.scala:75:8, :78:82] wire _might_hit_head_WIRE_2_7 = _might_hit_head_T_57; // @[fetch-buffer.scala:78:{61,82}] wire _might_hit_head_T_58 = _might_hit_head_T_42[15]; // @[fetch-buffer.scala:75:8, :78:82] wire [1:0] might_hit_head_lo_lo_2 = {_might_hit_head_WIRE_2_1, _might_hit_head_WIRE_2_0}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_lo_hi_2 = {_might_hit_head_WIRE_2_3, _might_hit_head_WIRE_2_2}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_lo_2 = {might_hit_head_lo_hi_2, might_hit_head_lo_lo_2}; // @[fetch-buffer.scala:79:63] wire [1:0] might_hit_head_hi_lo_2 = {_might_hit_head_WIRE_2_5, _might_hit_head_WIRE_2_4}; // @[fetch-buffer.scala:78:61, :79:63] wire [1:0] might_hit_head_hi_hi_2 = {_might_hit_head_WIRE_2_7, _might_hit_head_WIRE_2_6}; // @[fetch-buffer.scala:78:61, :79:63] wire [3:0] might_hit_head_hi_2 = {might_hit_head_hi_hi_2, might_hit_head_hi_lo_2}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_59 = {might_hit_head_hi_2, might_hit_head_lo_2}; // @[fetch-buffer.scala:79:63] wire [7:0] _might_hit_head_T_60 = head & _might_hit_head_T_19; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_61 = head & _might_hit_head_T_39; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_62 = head & _might_hit_head_T_59; // @[fetch-buffer.scala:61:21, :79:{63,88}] wire [7:0] _might_hit_head_T_63 = _might_hit_head_T_60 | _might_hit_head_T_61; // @[fetch-buffer.scala:79:{88,104}] wire [7:0] _might_hit_head_T_64 = _might_hit_head_T_63 | _might_hit_head_T_62; // @[fetch-buffer.scala:79:{88,104}] wire might_hit_head = |_might_hit_head_T_64; // @[fetch-buffer.scala:79:{104,108}] wire _at_head_T = tail[0]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_0 = _at_head_T; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_1 = tail[1]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_2 = tail[2]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_1 = _at_head_T_2; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_3 = tail[3]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_4 = tail[4]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_2 = _at_head_T_4; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_5 = tail[5]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_6 = tail[6]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_3 = _at_head_T_6; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_7 = tail[7]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_8 = tail[8]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_4 = _at_head_T_8; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_9 = tail[9]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_10 = tail[10]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_5 = _at_head_T_10; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_11 = tail[11]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_12 = tail[12]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_6 = _at_head_T_12; // @[fetch-buffer.scala:80:{25,31}] wire _at_head_T_13 = tail[13]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_T_14 = tail[14]; // @[fetch-buffer.scala:62:21, :80:31] wire _at_head_WIRE_7 = _at_head_T_14; // @[fetch-buffer.scala:80:{25,31}] wire [1:0] at_head_lo_lo = {_at_head_WIRE_1, _at_head_WIRE_0}; // @[fetch-buffer.scala:80:25, :81:29] wire [1:0] at_head_lo_hi = {_at_head_WIRE_3, _at_head_WIRE_2}; // @[fetch-buffer.scala:80:25, :81:29] wire [3:0] at_head_lo = {at_head_lo_hi, at_head_lo_lo}; // @[fetch-buffer.scala:81:29] wire [1:0] at_head_hi_lo = {_at_head_WIRE_5, _at_head_WIRE_4}; // @[fetch-buffer.scala:80:25, :81:29] wire [1:0] at_head_hi_hi = {_at_head_WIRE_7, _at_head_WIRE_6}; // @[fetch-buffer.scala:80:25, :81:29] wire [3:0] at_head_hi = {at_head_hi_hi, at_head_hi_lo}; // @[fetch-buffer.scala:81:29] wire [7:0] _at_head_T_16 = {at_head_hi, at_head_lo}; // @[fetch-buffer.scala:81:29] wire [7:0] _at_head_T_17 = _at_head_T_16 & head; // @[fetch-buffer.scala:61:21, :81:{29,36}] wire at_head = |_at_head_T_17; // @[fetch-buffer.scala:81:{36,44}] wire _do_enq_T = at_head & maybe_full; // @[fetch-buffer.scala:64:27, :81:44, :82:26] wire _do_enq_T_1 = _do_enq_T | might_hit_head; // @[fetch-buffer.scala:79:108, :82:{26,40}] assign do_enq = ~_do_enq_T_1; // @[fetch-buffer.scala:82:{16,40}] assign io_enq_ready_0 = do_enq; // @[fetch-buffer.scala:40:7, :82:16] wire _in_mask_0_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_1_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_2_T_1; // @[fetch-buffer.scala:98:49] wire _in_mask_3_T_1; // @[fetch-buffer.scala:98:49] wire in_mask_0; // @[fetch-buffer.scala:87:21] wire in_mask_1; // @[fetch-buffer.scala:87:21] wire in_mask_2; // @[fetch-buffer.scala:87:21] wire in_mask_3; // @[fetch-buffer.scala:87:21] wire _in_uops_0_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire _in_uops_0_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_0_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_1_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_1; // @[fetch-buffer.scala:95:43] wire _in_uops_1_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_1_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_2_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_2; // @[fetch-buffer.scala:95:43] wire _in_uops_2_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_2_taken_T_1; // @[fetch-buffer.scala:116:69] wire _in_uops_3_is_rvc_T_1; // @[fetch-buffer.scala:115:62] wire [39:0] pc_3; // @[fetch-buffer.scala:95:43] wire _in_uops_3_is_sfb_T; // @[fetch-buffer.scala:103:56] wire _in_uops_3_taken_T_1; // @[fetch-buffer.scala:116:69] wire in_uops_0_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_0_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_0_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_0_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_0_taken; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_1_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_1_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_1_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_1_taken; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_2_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_2_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_2_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_2_taken; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_rvc; // @[fetch-buffer.scala:88:21] wire [39:0] in_uops_3_debug_pc; // @[fetch-buffer.scala:88:21] wire in_uops_3_is_sfb; // @[fetch-buffer.scala:88:21] wire [5:0] in_uops_3_pc_lob; // @[fetch-buffer.scala:88:21] wire in_uops_3_taken; // @[fetch-buffer.scala:88:21] wire [39:0] _pc_T = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_1 = {_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_2 = ~_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_3 = {1'h0, _pc_T_2}; // @[frontend.scala:147:31] wire [39:0] pc = _pc_T_3[39:0]; // @[fetch-buffer.scala:95:43] wire _in_mask_0_T = io_enq_bits_mask_0[0]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_0_T_1 = io_enq_valid_0 & _in_mask_0_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_0 = _in_mask_0_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign _in_uops_0_is_sfb_T = io_enq_bits_sfbs_0_0 | io_enq_bits_shadowed_mask_0_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_0_is_sfb = _in_uops_0_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [39:0] _in_uops_0_debug_pc_T = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _in_uops_0_debug_pc_T_1 = {_in_uops_0_debug_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _in_uops_0_debug_pc_T_2 = ~_in_uops_0_debug_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _in_uops_0_debug_pc_T_3 = {1'h0, _in_uops_0_debug_pc_T_2}; // @[frontend.scala:147:31] wire [39:0] _in_uops_0_debug_pc_T_4 = _in_uops_0_debug_pc_T_3[39:0]; // @[fetch-buffer.scala:107:61] wire [40:0] _in_uops_0_debug_pc_T_5 = {1'h0, _in_uops_0_debug_pc_T_4} - 41'h2; // @[fetch-buffer.scala:107:{61,81}] wire [39:0] _in_uops_0_debug_pc_T_6 = _in_uops_0_debug_pc_T_5[39:0]; // @[fetch-buffer.scala:107:81] assign in_uops_0_debug_pc = io_enq_bits_edge_inst_0_0 ? _in_uops_0_debug_pc_T_6 : pc; // @[fetch-buffer.scala:40:7, :88:21, :95:43, :100:33, :106:41, :107:{32,81}] wire [39:0] _in_uops_0_pc_lob_T = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _in_uops_0_pc_lob_T_1 = {_in_uops_0_pc_lob_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _in_uops_0_pc_lob_T_2 = ~_in_uops_0_pc_lob_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _in_uops_0_pc_lob_T_3 = {1'h0, _in_uops_0_pc_lob_T_2}; // @[frontend.scala:147:31] wire [39:0] _in_uops_0_pc_lob_T_4 = _in_uops_0_pc_lob_T_3[39:0]; // @[fetch-buffer.scala:108:61] assign in_uops_0_pc_lob = io_enq_bits_edge_inst_0_0 ? _in_uops_0_pc_lob_T_4[5:0] : pc[5:0]; // @[fetch-buffer.scala:40:7, :88:21, :95:43, :101:33, :106:41, :108:{32,61}] wire [1:0] _in_uops_0_is_rvc_T = io_enq_bits_insts_0_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_0_is_rvc_T_1 = _in_uops_0_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_0_is_rvc = _in_uops_0_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_0_taken_T = io_enq_bits_cfi_idx_bits_0 == 2'h0; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_0_taken_T_1 = _in_uops_0_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_0_taken = _in_uops_0_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_4 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_5 = {_pc_T_4[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_6 = ~_pc_T_5; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_7 = {1'h0, _pc_T_6} + 41'h2; // @[frontend.scala:147:31] assign pc_1 = _pc_T_7[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_1_debug_pc = pc_1; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_1_T = io_enq_bits_mask_0[1]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_1_T_1 = io_enq_valid_0 & _in_mask_1_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_1 = _in_mask_1_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_1_pc_lob = pc_1[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_1_is_sfb_T = io_enq_bits_sfbs_1_0 | io_enq_bits_shadowed_mask_1_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_1_is_sfb = _in_uops_1_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_1_is_rvc_T = io_enq_bits_insts_1_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_1_is_rvc_T_1 = _in_uops_1_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_1_is_rvc = _in_uops_1_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_1_taken_T = io_enq_bits_cfi_idx_bits_0 == 2'h1; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_1_taken_T_1 = _in_uops_1_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_1_taken = _in_uops_1_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_8 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_9 = {_pc_T_8[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_10 = ~_pc_T_9; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_11 = {1'h0, _pc_T_10} + 41'h4; // @[frontend.scala:147:31] assign pc_2 = _pc_T_11[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_2_debug_pc = pc_2; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_2_T = io_enq_bits_mask_0[2]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_2_T_1 = io_enq_valid_0 & _in_mask_2_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_2 = _in_mask_2_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_2_pc_lob = pc_2[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_2_is_sfb_T = io_enq_bits_sfbs_2_0 | io_enq_bits_shadowed_mask_2_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_2_is_sfb = _in_uops_2_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_2_is_rvc_T = io_enq_bits_insts_2_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_2_is_rvc_T_1 = _in_uops_2_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_2_is_rvc = _in_uops_2_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_2_taken_T = io_enq_bits_cfi_idx_bits_0 == 2'h2; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_2_taken_T_1 = _in_uops_2_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_2_taken = _in_uops_2_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [39:0] _pc_T_12 = ~io_enq_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _pc_T_13 = {_pc_T_12[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _pc_T_14 = ~_pc_T_13; // @[frontend.scala:147:{31,39}] wire [40:0] _pc_T_15 = {1'h0, _pc_T_14} + 41'h6; // @[frontend.scala:147:31] assign pc_3 = _pc_T_15[39:0]; // @[fetch-buffer.scala:95:43] assign in_uops_3_debug_pc = pc_3; // @[fetch-buffer.scala:88:21, :95:43] wire _in_mask_3_T = io_enq_bits_mask_0[3]; // @[fetch-buffer.scala:40:7, :98:68] assign _in_mask_3_T_1 = io_enq_valid_0 & _in_mask_3_T; // @[fetch-buffer.scala:40:7, :98:{49,68}] assign in_mask_3 = _in_mask_3_T_1; // @[fetch-buffer.scala:87:21, :98:49] assign in_uops_3_pc_lob = pc_3[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33] assign _in_uops_3_is_sfb_T = io_enq_bits_sfbs_3_0 | io_enq_bits_shadowed_mask_3_0; // @[fetch-buffer.scala:40:7, :103:56] assign in_uops_3_is_sfb = _in_uops_3_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56] wire [1:0] _in_uops_3_is_rvc_T = io_enq_bits_insts_3_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56] assign _in_uops_3_is_rvc_T_1 = _in_uops_3_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}] assign in_uops_3_is_rvc = _in_uops_3_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62] wire _in_uops_3_taken_T = &io_enq_bits_cfi_idx_bits_0; // @[fetch-buffer.scala:40:7, :116:61] assign _in_uops_3_taken_T_1 = _in_uops_3_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}] assign in_uops_3_taken = _in_uops_3_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69] wire [15:0] enq_idxs_1; // @[fetch-buffer.scala:128:22] wire [15:0] enq_idxs_2; // @[fetch-buffer.scala:128:22] wire [15:0] enq_idxs_3; // @[fetch-buffer.scala:128:22] wire [15:0] _T_2 = {_might_hit_head_T, tail[15]}; // @[fetch-buffer.scala:62:21, :75:{11,24}, :132:8] assign enq_idxs_1 = in_mask_0 ? _T_2 : tail; // @[fetch-buffer.scala:62:21, :87:21, :128:22, :132:8, :138:18] wire [15:0] _T_6 = {enq_idxs_1[14:0], enq_idxs_1[15]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_2 = in_mask_1 ? _T_6 : enq_idxs_1; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire [15:0] _T_10 = {enq_idxs_2[14:0], enq_idxs_2[15]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}] assign enq_idxs_3 = in_mask_2 ? _T_10 : enq_idxs_2; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18] wire _tail_collisions_T = head[0]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_4 = head[0]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_1 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_2 = _tail_collisions_T_1; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_3 = _tail_collisions_T & _tail_collisions_T_2; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_0 = _tail_collisions_T_3; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_7 = _tail_collisions_T_4; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_5 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_1 = _tail_collisions_T_7; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_8 = head[1]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_12 = head[1]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_9 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_10 = _tail_collisions_T_9; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_11 = _tail_collisions_T_8 & _tail_collisions_T_10; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_2 = _tail_collisions_T_11; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_15 = _tail_collisions_T_12; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_13 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_3 = _tail_collisions_T_15; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_16 = head[2]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_20 = head[2]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_17 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_18 = _tail_collisions_T_17; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_19 = _tail_collisions_T_16 & _tail_collisions_T_18; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_4 = _tail_collisions_T_19; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_23 = _tail_collisions_T_20; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_21 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_5 = _tail_collisions_T_23; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_24 = head[3]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_28 = head[3]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_25 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_26 = _tail_collisions_T_25; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_27 = _tail_collisions_T_24 & _tail_collisions_T_26; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_6 = _tail_collisions_T_27; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_31 = _tail_collisions_T_28; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_29 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_7 = _tail_collisions_T_31; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_32 = head[4]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_36 = head[4]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_33 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_34 = _tail_collisions_T_33; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_35 = _tail_collisions_T_32 & _tail_collisions_T_34; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_8 = _tail_collisions_T_35; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_39 = _tail_collisions_T_36; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_37 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_9 = _tail_collisions_T_39; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_40 = head[5]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_44 = head[5]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_41 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_42 = _tail_collisions_T_41; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_43 = _tail_collisions_T_40 & _tail_collisions_T_42; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_10 = _tail_collisions_T_43; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_47 = _tail_collisions_T_44; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_45 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_11 = _tail_collisions_T_47; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_48 = head[6]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_52 = head[6]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_49 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_50 = _tail_collisions_T_49; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_51 = _tail_collisions_T_48 & _tail_collisions_T_50; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_12 = _tail_collisions_T_51; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_55 = _tail_collisions_T_52; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_53 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_13 = _tail_collisions_T_55; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_56 = head[7]; // @[fetch-buffer.scala:61:21, :155:31] wire _tail_collisions_T_60 = head[7]; // @[fetch-buffer.scala:61:21, :155:31] wire _head_T_1 = head[7]; // @[fetch-buffer.scala:61:21, :132:24, :155:31] wire _tail_collisions_T_57 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_T_58 = _tail_collisions_T_57; // @[fetch-buffer.scala:155:{49,61}] wire _tail_collisions_T_59 = _tail_collisions_T_56 & _tail_collisions_T_58; // @[fetch-buffer.scala:155:{31,45,61}] wire _tail_collisions_WIRE_14 = _tail_collisions_T_59; // @[fetch-buffer.scala:154:32, :155:45] wire _tail_collisions_T_63 = _tail_collisions_T_60; // @[fetch-buffer.scala:155:{31,45}] wire _tail_collisions_T_61 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49] wire _tail_collisions_WIRE_15 = _tail_collisions_T_63; // @[fetch-buffer.scala:154:32, :155:45] wire [1:0] tail_collisions_lo_lo_lo = {_tail_collisions_WIRE_1, _tail_collisions_WIRE_0}; // @[fetch-buffer.scala:154:32, :155:90] wire [1:0] tail_collisions_lo_lo_hi = {_tail_collisions_WIRE_3, _tail_collisions_WIRE_2}; // @[fetch-buffer.scala:154:32, :155:90] wire [3:0] tail_collisions_lo_lo = {tail_collisions_lo_lo_hi, tail_collisions_lo_lo_lo}; // @[fetch-buffer.scala:155:90] wire [1:0] tail_collisions_lo_hi_lo = {_tail_collisions_WIRE_5, _tail_collisions_WIRE_4}; // @[fetch-buffer.scala:154:32, :155:90] wire [1:0] tail_collisions_lo_hi_hi = {_tail_collisions_WIRE_7, _tail_collisions_WIRE_6}; // @[fetch-buffer.scala:154:32, :155:90] wire [3:0] tail_collisions_lo_hi = {tail_collisions_lo_hi_hi, tail_collisions_lo_hi_lo}; // @[fetch-buffer.scala:155:90] wire [7:0] tail_collisions_lo = {tail_collisions_lo_hi, tail_collisions_lo_lo}; // @[fetch-buffer.scala:155:90] wire [1:0] tail_collisions_hi_lo_lo = {_tail_collisions_WIRE_9, _tail_collisions_WIRE_8}; // @[fetch-buffer.scala:154:32, :155:90] wire [1:0] tail_collisions_hi_lo_hi = {_tail_collisions_WIRE_11, _tail_collisions_WIRE_10}; // @[fetch-buffer.scala:154:32, :155:90] wire [3:0] tail_collisions_hi_lo = {tail_collisions_hi_lo_hi, tail_collisions_hi_lo_lo}; // @[fetch-buffer.scala:155:90] wire [1:0] tail_collisions_hi_hi_lo = {_tail_collisions_WIRE_13, _tail_collisions_WIRE_12}; // @[fetch-buffer.scala:154:32, :155:90] wire [1:0] tail_collisions_hi_hi_hi = {_tail_collisions_WIRE_15, _tail_collisions_WIRE_14}; // @[fetch-buffer.scala:154:32, :155:90] wire [3:0] tail_collisions_hi_hi = {tail_collisions_hi_hi_hi, tail_collisions_hi_hi_lo}; // @[fetch-buffer.scala:155:90] wire [7:0] tail_collisions_hi = {tail_collisions_hi_hi, tail_collisions_hi_lo}; // @[fetch-buffer.scala:155:90] wire [15:0] _tail_collisions_T_64 = {tail_collisions_hi, tail_collisions_lo}; // @[fetch-buffer.scala:155:90] wire [15:0] tail_collisions = _tail_collisions_T_64 & tail; // @[fetch-buffer.scala:62:21, :155:{90,97}] wire [1:0] _slot_will_hit_tail_T = tail_collisions[1:0]; // @[fetch-buffer.scala:155:97, :156:70] wire [1:0] _slot_will_hit_tail_T_1 = tail_collisions[3:2]; // @[fetch-buffer.scala:155:97, :156:70] wire [1:0] _slot_will_hit_tail_T_2 = tail_collisions[5:4]; // @[fetch-buffer.scala:155:97, :156:70] wire [1:0] _slot_will_hit_tail_T_3 = tail_collisions[7:6]; // @[fetch-buffer.scala:155:97, :156:70] wire [1:0] _slot_will_hit_tail_T_4 = tail_collisions[9:8]; // @[fetch-buffer.scala:155:97, :156:70] wire [1:0] _slot_will_hit_tail_T_5 = tail_collisions[11:10]; // @[fetch-buffer.scala:155:97, :156:70] wire [1:0] _slot_will_hit_tail_T_6 = tail_collisions[13:12]; // @[fetch-buffer.scala:155:97, :156:70] wire [1:0] _slot_will_hit_tail_T_7 = tail_collisions[15:14]; // @[fetch-buffer.scala:155:97, :156:70] wire [1:0] _slot_will_hit_tail_T_8 = _slot_will_hit_tail_T | _slot_will_hit_tail_T_1; // @[fetch-buffer.scala:156:{70,112}] wire [1:0] _slot_will_hit_tail_T_9 = _slot_will_hit_tail_T_8 | _slot_will_hit_tail_T_2; // @[fetch-buffer.scala:156:{70,112}] wire [1:0] _slot_will_hit_tail_T_10 = _slot_will_hit_tail_T_9 | _slot_will_hit_tail_T_3; // @[fetch-buffer.scala:156:{70,112}] wire [1:0] _slot_will_hit_tail_T_11 = _slot_will_hit_tail_T_10 | _slot_will_hit_tail_T_4; // @[fetch-buffer.scala:156:{70,112}] wire [1:0] _slot_will_hit_tail_T_12 = _slot_will_hit_tail_T_11 | _slot_will_hit_tail_T_5; // @[fetch-buffer.scala:156:{70,112}] wire [1:0] _slot_will_hit_tail_T_13 = _slot_will_hit_tail_T_12 | _slot_will_hit_tail_T_6; // @[fetch-buffer.scala:156:{70,112}] wire [1:0] slot_will_hit_tail = _slot_will_hit_tail_T_13 | _slot_will_hit_tail_T_7; // @[fetch-buffer.scala:156:{70,112}] wire will_hit_tail = |slot_will_hit_tail; // @[fetch-buffer.scala:156:112, :157:42] wire _do_deq_T = ~will_hit_tail; // @[fetch-buffer.scala:157:42, :159:32] wire do_deq = io_deq_ready_0 & _do_deq_T; // @[fetch-buffer.scala:40:7, :159:{29,32}] wire [2:0] _deq_valids_T = {1'h0, slot_will_hit_tail}; // @[util.scala:394:30] wire [1:0] _deq_valids_T_1 = _deq_valids_T[1:0]; // @[util.scala:394:{30,37}] wire [2:0] _deq_valids_T_2 = {slot_will_hit_tail, 1'h0}; // @[util.scala:394:30] wire [1:0] _deq_valids_T_3 = _deq_valids_T_2[1:0]; // @[util.scala:394:{30,37}] wire [1:0] _deq_valids_T_4 = _deq_valids_T_1 | _deq_valids_T_3; // @[util.scala:394:{37,54}] wire [1:0] _deq_valids_T_5 = ~_deq_valids_T_4; // @[util.scala:394:54] wire deq_valids_0 = _deq_valids_T_5[0]; // @[fetch-buffer.scala:161:{21,53}] wire deq_valids_1 = _deq_valids_T_5[1]; // @[fetch-buffer.scala:161:{21,53}] assign io_deq_bits_uops_0_bits_debug_fsrc_0 = (head[0] ? deq_vec_0_0_debug_fsrc : 3'h0) | (head[1] ? deq_vec_1_0_debug_fsrc : 3'h0) | (head[2] ? deq_vec_2_0_debug_fsrc : 3'h0) | (head[3] ? deq_vec_3_0_debug_fsrc : 3'h0) | (head[4] ? deq_vec_4_0_debug_fsrc : 3'h0) | (head[5] ? deq_vec_5_0_debug_fsrc : 3'h0) | (head[6] ? deq_vec_6_0_debug_fsrc : 3'h0) | (head[7] ? deq_vec_7_0_debug_fsrc : 3'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_bp_xcpt_if_0 = head[0] & deq_vec_0_0_bp_xcpt_if | head[1] & deq_vec_1_0_bp_xcpt_if | head[2] & deq_vec_2_0_bp_xcpt_if | head[3] & deq_vec_3_0_bp_xcpt_if | head[4] & deq_vec_4_0_bp_xcpt_if | head[5] & deq_vec_5_0_bp_xcpt_if | head[6] & deq_vec_6_0_bp_xcpt_if | head[7] & deq_vec_7_0_bp_xcpt_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_bp_debug_if_0 = head[0] & deq_vec_0_0_bp_debug_if | head[1] & deq_vec_1_0_bp_debug_if | head[2] & deq_vec_2_0_bp_debug_if | head[3] & deq_vec_3_0_bp_debug_if | head[4] & deq_vec_4_0_bp_debug_if | head[5] & deq_vec_5_0_bp_debug_if | head[6] & deq_vec_6_0_bp_debug_if | head[7] & deq_vec_7_0_bp_debug_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_xcpt_ae_if_0 = head[0] & deq_vec_0_0_xcpt_ae_if | head[1] & deq_vec_1_0_xcpt_ae_if | head[2] & deq_vec_2_0_xcpt_ae_if | head[3] & deq_vec_3_0_xcpt_ae_if | head[4] & deq_vec_4_0_xcpt_ae_if | head[5] & deq_vec_5_0_xcpt_ae_if | head[6] & deq_vec_6_0_xcpt_ae_if | head[7] & deq_vec_7_0_xcpt_ae_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_xcpt_pf_if_0 = head[0] & deq_vec_0_0_xcpt_pf_if | head[1] & deq_vec_1_0_xcpt_pf_if | head[2] & deq_vec_2_0_xcpt_pf_if | head[3] & deq_vec_3_0_xcpt_pf_if | head[4] & deq_vec_4_0_xcpt_pf_if | head[5] & deq_vec_5_0_xcpt_pf_if | head[6] & deq_vec_6_0_xcpt_pf_if | head[7] & deq_vec_7_0_xcpt_pf_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_taken_0 = head[0] & deq_vec_0_0_taken | head[1] & deq_vec_1_0_taken | head[2] & deq_vec_2_0_taken | head[3] & deq_vec_3_0_taken | head[4] & deq_vec_4_0_taken | head[5] & deq_vec_5_0_taken | head[6] & deq_vec_6_0_taken | head[7] & deq_vec_7_0_taken; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_pc_lob_0 = (head[0] ? deq_vec_0_0_pc_lob : 6'h0) | (head[1] ? deq_vec_1_0_pc_lob : 6'h0) | (head[2] ? deq_vec_2_0_pc_lob : 6'h0) | (head[3] ? deq_vec_3_0_pc_lob : 6'h0) | (head[4] ? deq_vec_4_0_pc_lob : 6'h0) | (head[5] ? deq_vec_5_0_pc_lob : 6'h0) | (head[6] ? deq_vec_6_0_pc_lob : 6'h0) | (head[7] ? deq_vec_7_0_pc_lob : 6'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_edge_inst_0 = head[0] & deq_vec_0_0_edge_inst | head[1] & deq_vec_1_0_edge_inst | head[2] & deq_vec_2_0_edge_inst | head[3] & deq_vec_3_0_edge_inst | head[4] & deq_vec_4_0_edge_inst | head[5] & deq_vec_5_0_edge_inst | head[6] & deq_vec_6_0_edge_inst | head[7] & deq_vec_7_0_edge_inst; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_ftq_idx_0 = (head[0] ? deq_vec_0_0_ftq_idx : 5'h0) | (head[1] ? deq_vec_1_0_ftq_idx : 5'h0) | (head[2] ? deq_vec_2_0_ftq_idx : 5'h0) | (head[3] ? deq_vec_3_0_ftq_idx : 5'h0) | (head[4] ? deq_vec_4_0_ftq_idx : 5'h0) | (head[5] ? deq_vec_5_0_ftq_idx : 5'h0) | (head[6] ? deq_vec_6_0_ftq_idx : 5'h0) | (head[7] ? deq_vec_7_0_ftq_idx : 5'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_is_sfb_0 = head[0] & deq_vec_0_0_is_sfb | head[1] & deq_vec_1_0_is_sfb | head[2] & deq_vec_2_0_is_sfb | head[3] & deq_vec_3_0_is_sfb | head[4] & deq_vec_4_0_is_sfb | head[5] & deq_vec_5_0_is_sfb | head[6] & deq_vec_6_0_is_sfb | head[7] & deq_vec_7_0_is_sfb; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_debug_pc_0 = (head[0] ? deq_vec_0_0_debug_pc : 40'h0) | (head[1] ? deq_vec_1_0_debug_pc : 40'h0) | (head[2] ? deq_vec_2_0_debug_pc : 40'h0) | (head[3] ? deq_vec_3_0_debug_pc : 40'h0) | (head[4] ? deq_vec_4_0_debug_pc : 40'h0) | (head[5] ? deq_vec_5_0_debug_pc : 40'h0) | (head[6] ? deq_vec_6_0_debug_pc : 40'h0) | (head[7] ? deq_vec_7_0_debug_pc : 40'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_is_rvc_0 = head[0] & deq_vec_0_0_is_rvc | head[1] & deq_vec_1_0_is_rvc | head[2] & deq_vec_2_0_is_rvc | head[3] & deq_vec_3_0_is_rvc | head[4] & deq_vec_4_0_is_rvc | head[5] & deq_vec_5_0_is_rvc | head[6] & deq_vec_6_0_is_rvc | head[7] & deq_vec_7_0_is_rvc; // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_debug_inst_0 = (head[0] ? deq_vec_0_0_debug_inst : 32'h0) | (head[1] ? deq_vec_1_0_debug_inst : 32'h0) | (head[2] ? deq_vec_2_0_debug_inst : 32'h0) | (head[3] ? deq_vec_3_0_debug_inst : 32'h0) | (head[4] ? deq_vec_4_0_debug_inst : 32'h0) | (head[5] ? deq_vec_5_0_debug_inst : 32'h0) | (head[6] ? deq_vec_6_0_debug_inst : 32'h0) | (head[7] ? deq_vec_7_0_debug_inst : 32'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_0_bits_inst_0 = (head[0] ? deq_vec_0_0_inst : 32'h0) | (head[1] ? deq_vec_1_0_inst : 32'h0) | (head[2] ? deq_vec_2_0_inst : 32'h0) | (head[3] ? deq_vec_3_0_inst : 32'h0) | (head[4] ? deq_vec_4_0_inst : 32'h0) | (head[5] ? deq_vec_5_0_inst : 32'h0) | (head[6] ? deq_vec_6_0_inst : 32'h0) | (head[7] ? deq_vec_7_0_inst : 32'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_debug_fsrc_0 = (head[0] ? deq_vec_0_1_debug_fsrc : 3'h0) | (head[1] ? deq_vec_1_1_debug_fsrc : 3'h0) | (head[2] ? deq_vec_2_1_debug_fsrc : 3'h0) | (head[3] ? deq_vec_3_1_debug_fsrc : 3'h0) | (head[4] ? deq_vec_4_1_debug_fsrc : 3'h0) | (head[5] ? deq_vec_5_1_debug_fsrc : 3'h0) | (head[6] ? deq_vec_6_1_debug_fsrc : 3'h0) | (head[7] ? deq_vec_7_1_debug_fsrc : 3'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_bp_xcpt_if_0 = head[0] & deq_vec_0_1_bp_xcpt_if | head[1] & deq_vec_1_1_bp_xcpt_if | head[2] & deq_vec_2_1_bp_xcpt_if | head[3] & deq_vec_3_1_bp_xcpt_if | head[4] & deq_vec_4_1_bp_xcpt_if | head[5] & deq_vec_5_1_bp_xcpt_if | head[6] & deq_vec_6_1_bp_xcpt_if | head[7] & deq_vec_7_1_bp_xcpt_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_bp_debug_if_0 = head[0] & deq_vec_0_1_bp_debug_if | head[1] & deq_vec_1_1_bp_debug_if | head[2] & deq_vec_2_1_bp_debug_if | head[3] & deq_vec_3_1_bp_debug_if | head[4] & deq_vec_4_1_bp_debug_if | head[5] & deq_vec_5_1_bp_debug_if | head[6] & deq_vec_6_1_bp_debug_if | head[7] & deq_vec_7_1_bp_debug_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_xcpt_ae_if_0 = head[0] & deq_vec_0_1_xcpt_ae_if | head[1] & deq_vec_1_1_xcpt_ae_if | head[2] & deq_vec_2_1_xcpt_ae_if | head[3] & deq_vec_3_1_xcpt_ae_if | head[4] & deq_vec_4_1_xcpt_ae_if | head[5] & deq_vec_5_1_xcpt_ae_if | head[6] & deq_vec_6_1_xcpt_ae_if | head[7] & deq_vec_7_1_xcpt_ae_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_xcpt_pf_if_0 = head[0] & deq_vec_0_1_xcpt_pf_if | head[1] & deq_vec_1_1_xcpt_pf_if | head[2] & deq_vec_2_1_xcpt_pf_if | head[3] & deq_vec_3_1_xcpt_pf_if | head[4] & deq_vec_4_1_xcpt_pf_if | head[5] & deq_vec_5_1_xcpt_pf_if | head[6] & deq_vec_6_1_xcpt_pf_if | head[7] & deq_vec_7_1_xcpt_pf_if; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_taken_0 = head[0] & deq_vec_0_1_taken | head[1] & deq_vec_1_1_taken | head[2] & deq_vec_2_1_taken | head[3] & deq_vec_3_1_taken | head[4] & deq_vec_4_1_taken | head[5] & deq_vec_5_1_taken | head[6] & deq_vec_6_1_taken | head[7] & deq_vec_7_1_taken; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_pc_lob_0 = (head[0] ? deq_vec_0_1_pc_lob : 6'h0) | (head[1] ? deq_vec_1_1_pc_lob : 6'h0) | (head[2] ? deq_vec_2_1_pc_lob : 6'h0) | (head[3] ? deq_vec_3_1_pc_lob : 6'h0) | (head[4] ? deq_vec_4_1_pc_lob : 6'h0) | (head[5] ? deq_vec_5_1_pc_lob : 6'h0) | (head[6] ? deq_vec_6_1_pc_lob : 6'h0) | (head[7] ? deq_vec_7_1_pc_lob : 6'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_edge_inst_0 = head[0] & deq_vec_0_1_edge_inst | head[1] & deq_vec_1_1_edge_inst | head[2] & deq_vec_2_1_edge_inst | head[3] & deq_vec_3_1_edge_inst | head[4] & deq_vec_4_1_edge_inst | head[5] & deq_vec_5_1_edge_inst | head[6] & deq_vec_6_1_edge_inst | head[7] & deq_vec_7_1_edge_inst; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_ftq_idx_0 = (head[0] ? deq_vec_0_1_ftq_idx : 5'h0) | (head[1] ? deq_vec_1_1_ftq_idx : 5'h0) | (head[2] ? deq_vec_2_1_ftq_idx : 5'h0) | (head[3] ? deq_vec_3_1_ftq_idx : 5'h0) | (head[4] ? deq_vec_4_1_ftq_idx : 5'h0) | (head[5] ? deq_vec_5_1_ftq_idx : 5'h0) | (head[6] ? deq_vec_6_1_ftq_idx : 5'h0) | (head[7] ? deq_vec_7_1_ftq_idx : 5'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_is_sfb_0 = head[0] & deq_vec_0_1_is_sfb | head[1] & deq_vec_1_1_is_sfb | head[2] & deq_vec_2_1_is_sfb | head[3] & deq_vec_3_1_is_sfb | head[4] & deq_vec_4_1_is_sfb | head[5] & deq_vec_5_1_is_sfb | head[6] & deq_vec_6_1_is_sfb | head[7] & deq_vec_7_1_is_sfb; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_debug_pc_0 = (head[0] ? deq_vec_0_1_debug_pc : 40'h0) | (head[1] ? deq_vec_1_1_debug_pc : 40'h0) | (head[2] ? deq_vec_2_1_debug_pc : 40'h0) | (head[3] ? deq_vec_3_1_debug_pc : 40'h0) | (head[4] ? deq_vec_4_1_debug_pc : 40'h0) | (head[5] ? deq_vec_5_1_debug_pc : 40'h0) | (head[6] ? deq_vec_6_1_debug_pc : 40'h0) | (head[7] ? deq_vec_7_1_debug_pc : 40'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_is_rvc_0 = head[0] & deq_vec_0_1_is_rvc | head[1] & deq_vec_1_1_is_rvc | head[2] & deq_vec_2_1_is_rvc | head[3] & deq_vec_3_1_is_rvc | head[4] & deq_vec_4_1_is_rvc | head[5] & deq_vec_5_1_is_rvc | head[6] & deq_vec_6_1_is_rvc | head[7] & deq_vec_7_1_is_rvc; // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_debug_inst_0 = (head[0] ? deq_vec_0_1_debug_inst : 32'h0) | (head[1] ? deq_vec_1_1_debug_inst : 32'h0) | (head[2] ? deq_vec_2_1_debug_inst : 32'h0) | (head[3] ? deq_vec_3_1_debug_inst : 32'h0) | (head[4] ? deq_vec_4_1_debug_inst : 32'h0) | (head[5] ? deq_vec_5_1_debug_inst : 32'h0) | (head[6] ? deq_vec_6_1_debug_inst : 32'h0) | (head[7] ? deq_vec_7_1_debug_inst : 32'h0); // @[Mux.scala:30:73] assign io_deq_bits_uops_1_bits_inst_0 = (head[0] ? deq_vec_0_1_inst : 32'h0) | (head[1] ? deq_vec_1_1_inst : 32'h0) | (head[2] ? deq_vec_2_1_inst : 32'h0) | (head[3] ? deq_vec_3_1_inst : 32'h0) | (head[4] ? deq_vec_4_1_inst : 32'h0) | (head[5] ? deq_vec_5_1_inst : 32'h0) | (head[6] ? deq_vec_6_1_inst : 32'h0) | (head[7] ? deq_vec_7_1_inst : 32'h0); // @[Mux.scala:30:73] assign _io_deq_valid_T = deq_valids_0 | deq_valids_1; // @[fetch-buffer.scala:161:53, :170:38] assign io_deq_valid_0 = _io_deq_valid_T; // @[fetch-buffer.scala:40:7, :170:38] wire [6:0] _head_T = head[6:0]; // @[fetch-buffer.scala:61:21, :132:12] wire [7:0] _head_T_2 = {_head_T, _head_T_1}; // @[fetch-buffer.scala:132:{8,12,24}] assign io_deq_bits_uops_0_valid_0 = ~reset & deq_valids_0; // @[fetch-buffer.scala:40:7, :161:53, :168:72, :195:23, :196:41] assign io_deq_bits_uops_1_valid_0 = ~reset & deq_valids_1; // @[fetch-buffer.scala:40:7, :161:53, :168:72, :195:23, :196:41] wire _T_61 = do_enq & in_mask_0; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_18 = _T_61 & enq_idxs_0[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_21 = _T_61 & enq_idxs_0[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_24 = _T_61 & enq_idxs_0[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_27 = _T_61 & enq_idxs_0[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_30 = _T_61 & enq_idxs_0[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_33 = _T_61 & enq_idxs_0[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_36 = _T_61 & enq_idxs_0[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_39 = _T_61 & enq_idxs_0[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_42 = _T_61 & enq_idxs_0[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_45 = _T_61 & enq_idxs_0[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_48 = _T_61 & enq_idxs_0[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_51 = _T_61 & enq_idxs_0[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_54 = _T_61 & enq_idxs_0[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_57 = _T_61 & enq_idxs_0[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_60 = _T_61 & enq_idxs_0[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_63 = _T_61 & enq_idxs_0[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_109 = do_enq & in_mask_1; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_66 = _T_109 & enq_idxs_1[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_69 = _T_109 & enq_idxs_1[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_72 = _T_109 & enq_idxs_1[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_75 = _T_109 & enq_idxs_1[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_78 = _T_109 & enq_idxs_1[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_81 = _T_109 & enq_idxs_1[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_84 = _T_109 & enq_idxs_1[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_87 = _T_109 & enq_idxs_1[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_90 = _T_109 & enq_idxs_1[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_93 = _T_109 & enq_idxs_1[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_96 = _T_109 & enq_idxs_1[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_99 = _T_109 & enq_idxs_1[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_102 = _T_109 & enq_idxs_1[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_105 = _T_109 & enq_idxs_1[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_108 = _T_109 & enq_idxs_1[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_111 = _T_109 & enq_idxs_1[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_157 = do_enq & in_mask_2; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_114 = _T_157 & enq_idxs_2[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_117 = _T_157 & enq_idxs_2[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_120 = _T_157 & enq_idxs_2[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_123 = _T_157 & enq_idxs_2[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_126 = _T_157 & enq_idxs_2[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_129 = _T_157 & enq_idxs_2[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_132 = _T_157 & enq_idxs_2[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_135 = _T_157 & enq_idxs_2[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_138 = _T_157 & enq_idxs_2[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_141 = _T_157 & enq_idxs_2[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_144 = _T_157 & enq_idxs_2[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_147 = _T_157 & enq_idxs_2[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_150 = _T_157 & enq_idxs_2[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_153 = _T_157 & enq_idxs_2[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_156 = _T_157 & enq_idxs_2[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_159 = _T_157 & enq_idxs_2[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_205 = do_enq & in_mask_3; // @[fetch-buffer.scala:82:16, :87:21, :144:20] wire _T_162 = _T_205 & enq_idxs_3[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_165 = _T_205 & enq_idxs_3[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_168 = _T_205 & enq_idxs_3[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_171 = _T_205 & enq_idxs_3[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_174 = _T_205 & enq_idxs_3[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_177 = _T_205 & enq_idxs_3[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_180 = _T_205 & enq_idxs_3[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_183 = _T_205 & enq_idxs_3[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_186 = _T_205 & enq_idxs_3[8]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_189 = _T_205 & enq_idxs_3[9]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_192 = _T_205 & enq_idxs_3[10]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_195 = _T_205 & enq_idxs_3[11]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_198 = _T_205 & enq_idxs_3[12]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_201 = _T_205 & enq_idxs_3[13]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_204 = _T_205 & enq_idxs_3[14]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] wire _T_207 = _T_205 & enq_idxs_3[15]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}] always @(posedge clock) begin // @[fetch-buffer.scala:40:7] if (_T_162) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_114) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_66) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_18) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_0_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_0_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_0_edge_inst <= ~(_T_162 | _T_114 | _T_66) & (_T_18 ? in_uops_0_edge_inst : fb_uop_ram_0_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_165) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_117) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_69) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_21) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_1_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_1_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_1_edge_inst <= ~(_T_165 | _T_117 | _T_69) & (_T_21 ? in_uops_0_edge_inst : fb_uop_ram_1_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_168) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_120) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_72) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_24) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_2_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_2_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_2_edge_inst <= ~(_T_168 | _T_120 | _T_72) & (_T_24 ? in_uops_0_edge_inst : fb_uop_ram_2_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_171) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_123) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_75) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_27) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_3_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_3_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_3_edge_inst <= ~(_T_171 | _T_123 | _T_75) & (_T_27 ? in_uops_0_edge_inst : fb_uop_ram_3_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_174) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_126) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_78) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_30) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_4_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_4_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_4_edge_inst <= ~(_T_174 | _T_126 | _T_78) & (_T_30 ? in_uops_0_edge_inst : fb_uop_ram_4_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_177) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_129) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_81) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_33) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_5_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_5_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_5_edge_inst <= ~(_T_177 | _T_129 | _T_81) & (_T_33 ? in_uops_0_edge_inst : fb_uop_ram_5_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_180) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_132) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_84) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_36) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_6_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_6_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_6_edge_inst <= ~(_T_180 | _T_132 | _T_84) & (_T_36 ? in_uops_0_edge_inst : fb_uop_ram_6_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_183) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_135) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_87) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_39) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_7_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_7_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_7_edge_inst <= ~(_T_183 | _T_135 | _T_87) & (_T_39 ? in_uops_0_edge_inst : fb_uop_ram_7_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_186) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_138) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_90) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_42) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_8_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_8_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_8_edge_inst <= ~(_T_186 | _T_138 | _T_90) & (_T_42 ? in_uops_0_edge_inst : fb_uop_ram_8_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_189) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_141) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_93) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_45) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_9_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_9_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_9_edge_inst <= ~(_T_189 | _T_141 | _T_93) & (_T_45 ? in_uops_0_edge_inst : fb_uop_ram_9_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_192) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_144) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_96) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_48) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_10_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_10_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_10_edge_inst <= ~(_T_192 | _T_144 | _T_96) & (_T_48 ? in_uops_0_edge_inst : fb_uop_ram_10_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_195) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_147) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_99) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_51) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_11_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_11_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_11_edge_inst <= ~(_T_195 | _T_147 | _T_99) & (_T_51 ? in_uops_0_edge_inst : fb_uop_ram_11_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_198) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_150) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_102) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_54) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_12_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_12_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_12_edge_inst <= ~(_T_198 | _T_150 | _T_102) & (_T_54 ? in_uops_0_edge_inst : fb_uop_ram_12_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_201) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_153) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_105) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_57) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_13_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_13_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_13_edge_inst <= ~(_T_201 | _T_153 | _T_105) & (_T_57 ? in_uops_0_edge_inst : fb_uop_ram_13_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_204) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_156) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_108) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_60) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_14_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_14_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_14_edge_inst <= ~(_T_204 | _T_156 | _T_108) & (_T_60 ? in_uops_0_edge_inst : fb_uop_ram_14_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (_T_207) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_159) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_111) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end else if (_T_63) begin // @[fetch-buffer.scala:144:34] fb_uop_ram_15_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21] fb_uop_ram_15_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21] end fb_uop_ram_15_edge_inst <= ~(_T_207 | _T_159 | _T_111) & (_T_63 ? in_uops_0_edge_inst : fb_uop_ram_15_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16] if (reset) begin // @[fetch-buffer.scala:40:7] head <= 8'h1; // @[fetch-buffer.scala:61:21] tail <= 16'h1; // @[fetch-buffer.scala:62:21] maybe_full <= 1'h0; // @[fetch-buffer.scala:64:27] end else begin // @[fetch-buffer.scala:40:7] if (io_clear_0) begin // @[fetch-buffer.scala:40:7] head <= 8'h1; // @[fetch-buffer.scala:61:21] tail <= 16'h1; // @[fetch-buffer.scala:62:21] end else begin // @[fetch-buffer.scala:40:7] if (do_deq) // @[fetch-buffer.scala:159:29] head <= _head_T_2; // @[fetch-buffer.scala:61:21, :132:8] if (do_enq) begin // @[fetch-buffer.scala:82:16] if (in_mask_3) // @[fetch-buffer.scala:87:21] tail <= {enq_idxs_3[14:0], enq_idxs_3[15]}; // @[fetch-buffer.scala:62:21, :128:22, :132:{8,12,24}] else if (in_mask_2) // @[fetch-buffer.scala:87:21] tail <= _T_10; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_1) // @[fetch-buffer.scala:87:21] tail <= _T_6; // @[fetch-buffer.scala:62:21, :132:8] else if (in_mask_0) // @[fetch-buffer.scala:87:21] tail <= _T_2; // @[fetch-buffer.scala:62:21, :132:8] end end maybe_full <= ~(io_clear_0 | do_deq) & (do_enq & (in_mask_0 | in_mask_1 | in_mask_2 | in_mask_3) | maybe_full); // @[fetch-buffer.scala:40:7, :64:27, :82:16, :87:21, :159:29, :176:17, :178:{27,33}, :179:18, :183:17, :185:16, :188:19, :191:16] end always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[fetch-buffer.scala:40:7] assign io_deq_valid = io_deq_valid_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_valid = io_deq_bits_uops_0_valid_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_inst = io_deq_bits_uops_0_bits_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_debug_inst = io_deq_bits_uops_0_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_is_rvc = io_deq_bits_uops_0_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_debug_pc = io_deq_bits_uops_0_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_is_sfb = io_deq_bits_uops_0_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_ftq_idx = io_deq_bits_uops_0_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_edge_inst = io_deq_bits_uops_0_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_pc_lob = io_deq_bits_uops_0_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_taken = io_deq_bits_uops_0_bits_taken_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_xcpt_pf_if = io_deq_bits_uops_0_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_xcpt_ae_if = io_deq_bits_uops_0_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_bp_debug_if = io_deq_bits_uops_0_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_bp_xcpt_if = io_deq_bits_uops_0_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_0_bits_debug_fsrc = io_deq_bits_uops_0_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_valid = io_deq_bits_uops_1_valid_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_inst = io_deq_bits_uops_1_bits_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_debug_inst = io_deq_bits_uops_1_bits_debug_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_is_rvc = io_deq_bits_uops_1_bits_is_rvc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_debug_pc = io_deq_bits_uops_1_bits_debug_pc_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_is_sfb = io_deq_bits_uops_1_bits_is_sfb_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_ftq_idx = io_deq_bits_uops_1_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_edge_inst = io_deq_bits_uops_1_bits_edge_inst_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_pc_lob = io_deq_bits_uops_1_bits_pc_lob_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_taken = io_deq_bits_uops_1_bits_taken_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_xcpt_pf_if = io_deq_bits_uops_1_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_xcpt_ae_if = io_deq_bits_uops_1_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_bp_debug_if = io_deq_bits_uops_1_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_bp_xcpt_if = io_deq_bits_uops_1_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7] assign io_deq_bits_uops_1_bits_debug_fsrc = io_deq_bits_uops_1_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7] endmodule